1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
17 #include "llvm/Constants.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/Support/CallSite.h"
27 #include "llvm/Support/ErrorHandling.h"
39 class ExtractElementInst;
40 class ExtractValueInst;
47 class FunctionLoweringInfo;
48 class GetElementPtrInst;
54 class InsertElementInst;
55 class InsertValueInst;
58 class MachineBasicBlock;
59 class MachineFunction;
61 class MachineRegisterInfo;
65 class SDISelAsmOperandInfo;
68 class ShuffleVectorInst;
76 class UnreachableInst;
81 //===----------------------------------------------------------------------===//
82 /// SelectionDAGBuilder - This is the common target-independent lowering
83 /// implementation that is parameterized by a TargetLowering object.
84 /// Also, targets can overload any lowering method.
86 class SelectionDAGBuilder {
87 MachineBasicBlock *CurMBB;
89 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
92 DenseMap<const Value*, SDValue> NodeMap;
94 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
95 /// them up and then emit token factor nodes when possible. This allows us to
96 /// get simple disambiguation between loads without worrying about alias
98 SmallVector<SDValue, 8> PendingLoads;
100 /// PendingExports - CopyToReg nodes that copy values to virtual registers
101 /// for export to other blocks need to be emitted before any terminator
102 /// instruction, but they have no other ordering requirements. We bunch them
103 /// up and the emit a single tokenfactor for them just before terminator
105 SmallVector<SDValue, 8> PendingExports;
107 /// SDNodeOrder - A unique monotonically increasing number used to order the
108 /// SDNodes we create.
109 unsigned SDNodeOrder;
111 /// Case - A struct to record the Value for a switch case, and the
112 /// case's target basic block.
116 MachineBasicBlock* BB;
118 Case() : Low(0), High(0), BB(0) { }
119 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
120 Low(low), High(high), BB(bb) { }
122 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
123 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
124 return (rHigh - rLow + 1ULL);
130 MachineBasicBlock* BB;
133 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
134 Mask(mask), BB(bb), Bits(bits) { }
137 typedef std::vector<Case> CaseVector;
138 typedef std::vector<CaseBits> CaseBitsVector;
139 typedef CaseVector::iterator CaseItr;
140 typedef std::pair<CaseItr, CaseItr> CaseRange;
142 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
143 /// of conditional branches.
145 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
146 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
148 /// CaseBB - The MBB in which to emit the compare and branch
149 MachineBasicBlock *CaseBB;
150 /// LT, GE - If nonzero, we know the current case value must be less-than or
151 /// greater-than-or-equal-to these Constants.
154 /// Range - A pair of iterators representing the range of case values to be
155 /// processed at this point in the binary search tree.
159 typedef std::vector<CaseRec> CaseRecVector;
161 /// The comparison function for sorting the switch case values in the vector.
162 /// WARNING: Case ranges should be disjoint!
164 bool operator () (const Case& C1, const Case& C2) {
165 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
166 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
167 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
168 return CI1->getValue().slt(CI2->getValue());
173 bool operator () (const CaseBits& C1, const CaseBits& C2) {
174 return C1.Bits > C2.Bits;
178 size_t Clusterify(CaseVector& Cases, const SwitchInst &SI);
180 /// CaseBlock - This structure is used to communicate between
181 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
182 /// blocks needed by multi-case switch statements.
184 CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
185 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
186 MachineBasicBlock *me)
187 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
188 TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
189 // CC - the condition code to use for the case block's setcc node
191 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
192 // Emit by default LHS op RHS. MHS is used for range comparisons:
193 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
194 Value *CmpLHS, *CmpMHS, *CmpRHS;
195 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
196 MachineBasicBlock *TrueBB, *FalseBB;
197 // ThisBB - the block into which to emit the code for the setcc and branches
198 MachineBasicBlock *ThisBB;
201 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
202 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
204 /// Reg - the virtual register containing the index of the jump table entry
207 /// JTI - the JumpTableIndex for this jump table in the function.
209 /// MBB - the MBB into which to emit the code for the indirect jump.
210 MachineBasicBlock *MBB;
211 /// Default - the MBB of the default bb, which is a successor of the range
212 /// check MBB. This is when updating PHI nodes in successors.
213 MachineBasicBlock *Default;
215 struct JumpTableHeader {
216 JumpTableHeader(APInt F, APInt L, Value* SV, MachineBasicBlock* H,
218 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
222 MachineBasicBlock *HeaderBB;
225 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
228 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
229 Mask(M), ThisBB(T), TargetBB(Tr) { }
231 MachineBasicBlock* ThisBB;
232 MachineBasicBlock* TargetBB;
235 typedef SmallVector<BitTestCase, 3> BitTestInfo;
237 struct BitTestBlock {
238 BitTestBlock(APInt F, APInt R, Value* SV,
240 MachineBasicBlock* P, MachineBasicBlock* D,
241 const BitTestInfo& C):
242 First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
243 Parent(P), Default(D), Cases(C) { }
249 MachineBasicBlock *Parent;
250 MachineBasicBlock *Default;
255 // TLI - This is information that describes the available target features we
256 // need for lowering. This indicates when operations are unavailable,
257 // implemented with a libcall, etc.
260 const TargetData *TD;
263 /// SwitchCases - Vector of CaseBlock structures used to communicate
264 /// SwitchInst code generation information.
265 std::vector<CaseBlock> SwitchCases;
266 /// JTCases - Vector of JumpTable structures used to communicate
267 /// SwitchInst code generation information.
268 std::vector<JumpTableBlock> JTCases;
269 /// BitTestCases - Vector of BitTestBlock structures used to communicate
270 /// SwitchInst code generation information.
271 std::vector<BitTestBlock> BitTestCases;
273 /// PHINodesToUpdate - A list of phi instructions whose operand list will
274 /// be updated after processing the current basic block.
275 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
277 /// EdgeMapping - If an edge from CurMBB to any MBB is changed (e.g. due to
278 /// scheduler custom lowering), track the change here.
279 DenseMap<MachineBasicBlock*, MachineBasicBlock*> EdgeMapping;
281 // Emit PHI-node-operand constants only once even if used by multiple
283 DenseMap<Constant*, unsigned> ConstantsOut;
285 /// FuncInfo - Information about the function as a whole.
287 FunctionLoweringInfo &FuncInfo;
289 /// OptLevel - What optimization level we're generating code for.
291 CodeGenOpt::Level OptLevel;
293 /// GFI - Garbage collection metadata for the function.
296 /// HasTailCall - This is set to true if a call in the current
297 /// block has been translated as a tail call. In this case,
298 /// no subsequent DAG nodes should be created.
302 LLVMContext *Context;
304 SelectionDAGBuilder(SelectionDAG &dag, TargetLowering &tli,
305 FunctionLoweringInfo &funcinfo,
306 CodeGenOpt::Level ol)
307 : CurDebugLoc(DebugLoc::getUnknownLoc()), SDNodeOrder(0),
308 TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
310 Context(dag.getContext()) {
313 void init(GCFunctionInfo *gfi, AliasAnalysis &aa);
315 /// clear - Clear out the curret SelectionDAG and the associated
316 /// state and prepare this SelectionDAGBuilder object to be used
317 /// for a new block. This doesn't clear out information about
318 /// additional blocks that are needed to complete switch lowering
319 /// or PHI node updating; that information is cleared out as it is
323 /// getRoot - Return the current virtual root of the Selection DAG,
324 /// flushing any PendingLoad items. This must be done before emitting
325 /// a store or any other node that may need to be ordered after any
326 /// prior load instructions.
330 /// getControlRoot - Similar to getRoot, but instead of flushing all the
331 /// PendingLoad items, flush all the PendingExports items. It is necessary
332 /// to do this before emitting a terminator instruction.
334 SDValue getControlRoot();
336 DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
337 void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; }
339 void CopyValueToVirtualRegister(Value *V, unsigned Reg);
341 void visit(Instruction &I);
343 void visit(unsigned Opcode, User &I);
345 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
347 SDValue getValue(const Value *V);
349 void setValue(const Value *V, SDValue NewN) {
350 SDValue &N = NodeMap[V];
351 assert(N.getNode() == 0 && "Already set a value for this node!");
355 void GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
356 std::set<unsigned> &OutputRegs,
357 std::set<unsigned> &InputRegs);
359 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
360 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
362 void EmitBranchForMergedCondition(Value *Cond, MachineBasicBlock *TBB,
363 MachineBasicBlock *FBB,
364 MachineBasicBlock *CurBB);
365 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
366 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
367 void CopyToExportRegsIfNeeded(Value *V);
368 void ExportFromCurrentBlock(Value *V);
369 void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
370 MachineBasicBlock *LandingPad = NULL);
373 // Terminator instructions.
374 void visitRet(ReturnInst &I);
375 void visitBr(BranchInst &I);
376 void visitSwitch(SwitchInst &I);
377 void visitIndirectBr(IndirectBrInst &I);
378 void visitUnreachable(UnreachableInst &I) { /* noop */ }
380 // Helpers for visitSwitch
381 bool handleSmallSwitchRange(CaseRec& CR,
382 CaseRecVector& WorkList,
384 MachineBasicBlock* Default);
385 bool handleJTSwitchCase(CaseRec& CR,
386 CaseRecVector& WorkList,
388 MachineBasicBlock* Default);
389 bool handleBTSplitSwitchCase(CaseRec& CR,
390 CaseRecVector& WorkList,
392 MachineBasicBlock* Default);
393 bool handleBitTestsSwitchCase(CaseRec& CR,
394 CaseRecVector& WorkList,
396 MachineBasicBlock* Default);
398 void visitSwitchCase(CaseBlock &CB);
399 void visitBitTestHeader(BitTestBlock &B);
400 void visitBitTestCase(MachineBasicBlock* NextMBB,
403 void visitJumpTable(JumpTable &JT);
404 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH);
407 // These all get lowered before this pass.
408 void visitInvoke(InvokeInst &I);
409 void visitUnwind(UnwindInst &I);
411 void visitBinary(User &I, unsigned OpCode);
412 void visitShift(User &I, unsigned Opcode);
413 void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
414 void visitFAdd(User &I) { visitBinary(I, ISD::FADD); }
415 void visitSub(User &I) { visitBinary(I, ISD::SUB); }
416 void visitFSub(User &I);
417 void visitMul(User &I) { visitBinary(I, ISD::MUL); }
418 void visitFMul(User &I) { visitBinary(I, ISD::FMUL); }
419 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
420 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
421 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
422 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
423 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
424 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
425 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
426 void visitOr (User &I) { visitBinary(I, ISD::OR); }
427 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
428 void visitShl (User &I) { visitShift(I, ISD::SHL); }
429 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
430 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
431 void visitICmp(User &I);
432 void visitFCmp(User &I);
433 // Visit the conversion instructions
434 void visitTrunc(User &I);
435 void visitZExt(User &I);
436 void visitSExt(User &I);
437 void visitFPTrunc(User &I);
438 void visitFPExt(User &I);
439 void visitFPToUI(User &I);
440 void visitFPToSI(User &I);
441 void visitUIToFP(User &I);
442 void visitSIToFP(User &I);
443 void visitPtrToInt(User &I);
444 void visitIntToPtr(User &I);
445 void visitBitCast(User &I);
447 void visitExtractElement(User &I);
448 void visitInsertElement(User &I);
449 void visitShuffleVector(User &I);
451 void visitExtractValue(ExtractValueInst &I);
452 void visitInsertValue(InsertValueInst &I);
454 void visitGetElementPtr(User &I);
455 void visitSelect(User &I);
457 void visitAlloca(AllocaInst &I);
458 void visitLoad(LoadInst &I);
459 void visitStore(StoreInst &I);
460 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
461 void visitCall(CallInst &I);
462 void visitInlineAsm(CallSite CS);
463 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
464 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
466 void visitPow(CallInst &I);
467 void visitExp2(CallInst &I);
468 void visitExp(CallInst &I);
469 void visitLog(CallInst &I);
470 void visitLog2(CallInst &I);
471 void visitLog10(CallInst &I);
473 void visitVAStart(CallInst &I);
474 void visitVAArg(VAArgInst &I);
475 void visitVAEnd(CallInst &I);
476 void visitVACopy(CallInst &I);
478 void visitUserOp1(Instruction &I) {
479 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
481 void visitUserOp2(Instruction &I) {
482 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
485 const char *implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op);
486 const char *implVisitAluOverflow(CallInst &I, ISD::NodeType Op);
489 } // end namespace llvm