1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 #include "llvm/IR/CallSite.h"
24 #include "llvm/IR/Statepoint.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Target/TargetLowering.h"
32 class AddrSpaceCastInst;
40 class ExtractElementInst;
41 class ExtractValueInst;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
55 class InsertElementInst;
56 class InsertValueInst;
59 class MachineBasicBlock;
61 class MachineRegisterInfo;
70 class ShuffleVectorInst;
75 class TargetLibraryInfo;
79 class UnreachableInst;
83 //===----------------------------------------------------------------------===//
84 /// SelectionDAGBuilder - This is the common target-independent lowering
85 /// implementation that is parameterized by a TargetLowering object.
87 class SelectionDAGBuilder {
88 /// CurInst - The current instruction being visited
89 const Instruction *CurInst;
91 DenseMap<const Value*, SDValue> NodeMap;
93 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
94 /// to preserve debug information for incoming arguments.
95 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
97 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
98 class DanglingDebugInfo {
99 const DbgValueInst* DI;
101 unsigned SDNodeOrder;
103 DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
104 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
105 DI(di), dl(DL), SDNodeOrder(SDNO) { }
106 const DbgValueInst* getDI() { return DI; }
107 DebugLoc getdl() { return dl; }
108 unsigned getSDNodeOrder() { return SDNodeOrder; }
111 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
112 /// yet seen the referent. We defer handling these until we do see it.
113 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
116 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
117 /// them up and then emit token factor nodes when possible. This allows us to
118 /// get simple disambiguation between loads without worrying about alias
120 SmallVector<SDValue, 8> PendingLoads;
122 /// State used while lowering a statepoint sequence (gc_statepoint,
123 /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
124 StatepointLoweringState StatepointLowering;
127 /// PendingExports - CopyToReg nodes that copy values to virtual registers
128 /// for export to other blocks need to be emitted before any terminator
129 /// instruction, but they have no other ordering requirements. We bunch them
130 /// up and the emit a single tokenfactor for them just before terminator
132 SmallVector<SDValue, 8> PendingExports;
134 /// SDNodeOrder - A unique monotonically increasing number used to order the
135 /// SDNodes we create.
136 unsigned SDNodeOrder;
138 enum CaseClusterKind {
139 /// A cluster of adjacent case labels with the same destination, or just one
142 /// A cluster of cases suitable for jump table lowering.
144 /// A cluster of cases suitable for bit test lowering.
148 /// A cluster of case labels.
150 CaseClusterKind Kind;
151 const ConstantInt *Low, *High;
153 MachineBasicBlock *MBB;
154 unsigned JTCasesIndex;
155 unsigned BTCasesIndex;
159 static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
160 MachineBasicBlock *MBB, uint32_t Weight) {
170 static CaseCluster jumpTable(const ConstantInt *Low,
171 const ConstantInt *High, unsigned JTCasesIndex,
174 C.Kind = CC_JumpTable;
177 C.JTCasesIndex = JTCasesIndex;
182 static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
183 unsigned BTCasesIndex, uint32_t Weight) {
185 C.Kind = CC_BitTests;
188 C.BTCasesIndex = BTCasesIndex;
194 typedef std::vector<CaseCluster> CaseClusterVector;
195 typedef CaseClusterVector::iterator CaseClusterIt;
199 MachineBasicBlock* BB;
201 uint32_t ExtraWeight;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
205 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
207 CaseBits() : Mask(0), BB(nullptr), Bits(0), ExtraWeight(0) {}
210 typedef std::vector<CaseBits> CaseBitsVector;
212 /// Sort Clusters and merge adjacent cases.
213 void sortAndRangeify(CaseClusterVector &Clusters);
215 /// CaseBlock - This structure is used to communicate between
216 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
217 /// blocks needed by multi-case switch statements.
219 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
220 const Value *cmpmiddle,
221 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
222 MachineBasicBlock *me,
223 uint32_t trueweight = 0, uint32_t falseweight = 0)
224 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
225 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
226 TrueWeight(trueweight), FalseWeight(falseweight) { }
228 // CC - the condition code to use for the case block's setcc node
231 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
232 // Emit by default LHS op RHS. MHS is used for range comparisons:
233 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
234 const Value *CmpLHS, *CmpMHS, *CmpRHS;
236 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
237 MachineBasicBlock *TrueBB, *FalseBB;
239 // ThisBB - the block into which to emit the code for the setcc and branches
240 MachineBasicBlock *ThisBB;
242 // TrueWeight/FalseWeight - branch weights.
243 uint32_t TrueWeight, FalseWeight;
247 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
248 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
250 /// Reg - the virtual register containing the index of the jump table entry
253 /// JTI - the JumpTableIndex for this jump table in the function.
255 /// MBB - the MBB into which to emit the code for the indirect jump.
256 MachineBasicBlock *MBB;
257 /// Default - the MBB of the default bb, which is a successor of the range
258 /// check MBB. This is when updating PHI nodes in successors.
259 MachineBasicBlock *Default;
261 struct JumpTableHeader {
262 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
264 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
268 MachineBasicBlock *HeaderBB;
271 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
274 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
278 MachineBasicBlock *ThisBB;
279 MachineBasicBlock *TargetBB;
280 uint32_t ExtraWeight;
283 typedef SmallVector<BitTestCase, 3> BitTestInfo;
285 struct BitTestBlock {
286 BitTestBlock(APInt F, APInt R, const Value* SV,
287 unsigned Rg, MVT RgVT, bool E,
288 MachineBasicBlock* P, MachineBasicBlock* D,
290 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
291 Parent(P), Default(D), Cases(std::move(C)) { }
298 MachineBasicBlock *Parent;
299 MachineBasicBlock *Default;
303 /// Minimum jump table density, in percent.
304 enum { MinJumpTableDensity = 40 };
306 /// Check whether a range of clusters is dense enough for a jump table.
307 bool isDense(const CaseClusterVector &Clusters, unsigned *TotalCases,
308 unsigned First, unsigned Last);
310 /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
311 /// decides it's not a good idea.
312 bool buildJumpTable(CaseClusterVector &Clusters, unsigned First,
313 unsigned Last, const SwitchInst *SI,
314 MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
316 /// Find clusters of cases suitable for jump table lowering.
317 void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
318 MachineBasicBlock *DefaultMBB);
320 /// Check whether the range [Low,High] fits in a machine word.
321 bool rangeFitsInWord(const APInt &Low, const APInt &High);
323 /// Check whether these clusters are suitable for lowering with bit tests based
324 /// on the number of destinations, comparison metric, and range.
325 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
326 const APInt &Low, const APInt &High);
328 /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
329 /// decides it's not a good idea.
330 bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
331 const SwitchInst *SI, CaseCluster &BTCluster);
333 /// Find clusters of cases suitable for bit test lowering.
334 void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
336 struct SwitchWorkListItem {
337 MachineBasicBlock *MBB;
338 CaseClusterIt FirstCluster;
339 CaseClusterIt LastCluster;
340 const ConstantInt *GE;
341 const ConstantInt *LT;
343 typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
345 /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
346 /// than each cluster in the range, its rank is 0.
347 static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
350 /// Emit comparison and split W into two subtrees.
351 void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
352 Value *Cond, MachineBasicBlock *SwitchMBB);
355 void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
356 MachineBasicBlock *SwitchMBB,
357 MachineBasicBlock *DefaultMBB);
360 /// A class which encapsulates all of the information needed to generate a
361 /// stack protector check and signals to isel via its state being initialized
362 /// that a stack protector needs to be generated.
364 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
365 /// Protector Generation. The reason that it is placed here is for a lack of
366 /// other good places to stick it.
368 /// High Level Overview of SelectionDAG Stack Protector Generation:
370 /// Previously, generation of stack protectors was done exclusively in the
371 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
372 /// splitting basic blocks at the IR level to create the success/failure basic
373 /// blocks in the tail of the basic block in question. As a result of this,
374 /// calls that would have qualified for the sibling call optimization were no
375 /// longer eligible for optimization since said calls were no longer right in
376 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
379 /// Then it was noticed that since the sibling call optimization causes the
380 /// callee to reuse the caller's stack, if we could delay the generation of
381 /// the stack protector check until later in CodeGen after the sibling call
382 /// decision was made, we get both the tail call optimization and the stack
385 /// A few goals in solving this problem were:
387 /// 1. Preserve the architecture independence of stack protector generation.
389 /// 2. Preserve the normal IR level stack protector check for platforms like
390 /// OpenBSD for which we support platform-specific stack protector
393 /// The main problem that guided the present solution is that one can not
394 /// solve this problem in an architecture independent manner at the IR level
395 /// only. This is because:
397 /// 1. The decision on whether or not to perform a sibling call on certain
398 /// platforms (for instance i386) requires lower level information
399 /// related to available registers that can not be known at the IR level.
401 /// 2. Even if the previous point were not true, the decision on whether to
402 /// perform a tail call is done in LowerCallTo in SelectionDAG which
403 /// occurs after the Stack Protector Pass. As a result, one would need to
404 /// put the relevant callinst into the stack protector check success
405 /// basic block (where the return inst is placed) and then move it back
406 /// later at SelectionDAG/MI time before the stack protector check if the
407 /// tail call optimization failed. The MI level option was nixed
408 /// immediately since it would require platform-specific pattern
409 /// matching. The SelectionDAG level option was nixed because
410 /// SelectionDAG only processes one IR level basic block at a time
411 /// implying one could not create a DAG Combine to move the callinst.
413 /// To get around this problem a few things were realized:
415 /// 1. While one can not handle multiple IR level basic blocks at the
416 /// SelectionDAG Level, one can generate multiple machine basic blocks
417 /// for one IR level basic block. This is how we handle bit tests and
420 /// 2. At the MI level, tail calls are represented via a special return
421 /// MIInst called "tcreturn". Thus if we know the basic block in which we
422 /// wish to insert the stack protector check, we get the correct behavior
423 /// by always inserting the stack protector check right before the return
424 /// statement. This is a "magical transformation" since no matter where
425 /// the stack protector check intrinsic is, we always insert the stack
426 /// protector check code at the end of the BB.
428 /// Given the aforementioned constraints, the following solution was devised:
430 /// 1. On platforms that do not support SelectionDAG stack protector check
431 /// generation, allow for the normal IR level stack protector check
432 /// generation to continue.
434 /// 2. On platforms that do support SelectionDAG stack protector check
437 /// a. Use the IR level stack protector pass to decide if a stack
438 /// protector is required/which BB we insert the stack protector check
439 /// in by reusing the logic already therein. If we wish to generate a
440 /// stack protector check in a basic block, we place a special IR
441 /// intrinsic called llvm.stackprotectorcheck right before the BB's
442 /// returninst or if there is a callinst that could potentially be
443 /// sibling call optimized, before the call inst.
445 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
446 /// normally via SelectBasicBlock. In said process, when we visit the
447 /// stack protector check, we do not actually emit anything into the
448 /// BB. Instead, we just initialize the stack protector descriptor
449 /// class (which involves stashing information/creating the success
450 /// mbbb and the failure mbb if we have not created one for this
451 /// function yet) and export the guard variable that we are going to
454 /// c. After we finish selecting the basic block, in FinishBasicBlock if
455 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
456 /// initialized, we first find a splice point in the parent basic block
457 /// before the terminator and then splice the terminator of said basic
458 /// block into the success basic block. Then we code-gen a new tail for
459 /// the parent basic block consisting of the two loads, the comparison,
460 /// and finally two branches to the success/failure basic blocks. We
461 /// conclude by code-gening the failure basic block if we have not
462 /// code-gened it already (all stack protector checks we generate in
463 /// the same function, use the same failure basic block).
464 class StackProtectorDescriptor {
466 StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
467 FailureMBB(nullptr), Guard(nullptr),
470 /// Returns true if all fields of the stack protector descriptor are
471 /// initialized implying that we should/are ready to emit a stack protector.
472 bool shouldEmitStackProtector() const {
473 return ParentMBB && SuccessMBB && FailureMBB && Guard;
476 /// Initialize the stack protector descriptor structure for a new basic
478 void initialize(const BasicBlock *BB,
479 MachineBasicBlock *MBB,
480 const CallInst &StackProtCheckCall) {
481 // Make sure we are not initialized yet.
482 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
483 "already initialized!");
485 SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
486 FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
488 Guard = StackProtCheckCall.getArgOperand(0);
491 /// Reset state that changes when we handle different basic blocks.
493 /// This currently includes:
495 /// 1. The specific basic block we are generating a
496 /// stack protector for (ParentMBB).
498 /// 2. The successor machine basic block that will contain the tail of
499 /// parent mbb after we create the stack protector check (SuccessMBB). This
500 /// BB is visited only on stack protector check success.
501 void resetPerBBState() {
503 SuccessMBB = nullptr;
506 /// Reset state that only changes when we switch functions.
508 /// This currently includes:
510 /// 1. FailureMBB since we reuse the failure code path for all stack
511 /// protector checks created in an individual function.
513 /// 2.The guard variable since the guard variable we are checking against is
515 void resetPerFunctionState() {
516 FailureMBB = nullptr;
520 MachineBasicBlock *getParentMBB() { return ParentMBB; }
521 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
522 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
523 const Value *getGuard() { return Guard; }
525 unsigned getGuardReg() const { return GuardReg; }
526 void setGuardReg(unsigned R) { GuardReg = R; }
529 /// The basic block for which we are generating the stack protector.
531 /// As a result of stack protector generation, we will splice the
532 /// terminators of this basic block into the successor mbb SuccessMBB and
533 /// replace it with a compare/branch to the successor mbbs
534 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
536 MachineBasicBlock *ParentMBB;
538 /// A basic block visited on stack protector check success that contains the
539 /// terminators of ParentMBB.
540 MachineBasicBlock *SuccessMBB;
542 /// This basic block visited on stack protector check failure that will
543 /// contain a call to __stack_chk_fail().
544 MachineBasicBlock *FailureMBB;
546 /// The guard variable which we will compare against the stored value in the
547 /// stack protector stack slot.
550 /// The virtual register holding the stack guard value.
553 /// Add a successor machine basic block to ParentMBB. If the successor mbb
554 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
555 /// block will be created. Assign a large weight if IsLikely is true.
556 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
557 MachineBasicBlock *ParentMBB,
559 MachineBasicBlock *SuccMBB = nullptr);
563 const TargetMachine &TM;
565 /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
566 /// nodes without a corresponding SDNode.
567 static const unsigned LowestSDNodeOrder = 1;
570 const DataLayout *DL;
572 const TargetLibraryInfo *LibInfo;
574 /// SwitchCases - Vector of CaseBlock structures used to communicate
575 /// SwitchInst code generation information.
576 std::vector<CaseBlock> SwitchCases;
577 /// JTCases - Vector of JumpTable structures used to communicate
578 /// SwitchInst code generation information.
579 std::vector<JumpTableBlock> JTCases;
580 /// BitTestCases - Vector of BitTestBlock structures used to communicate
581 /// SwitchInst code generation information.
582 std::vector<BitTestBlock> BitTestCases;
583 /// A StackProtectorDescriptor structure used to communicate stack protector
584 /// information in between SelectBasicBlock and FinishBasicBlock.
585 StackProtectorDescriptor SPDescriptor;
587 // Emit PHI-node-operand constants only once even if used by multiple
589 DenseMap<const Constant *, unsigned> ConstantsOut;
591 /// FuncInfo - Information about the function as a whole.
593 FunctionLoweringInfo &FuncInfo;
595 /// OptLevel - What optimization level we're generating code for.
597 CodeGenOpt::Level OptLevel;
599 /// GFI - Garbage collection metadata for the function.
602 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
603 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
605 /// HasTailCall - This is set to true if a call in the current
606 /// block has been translated as a tail call. In this case,
607 /// no subsequent DAG nodes should be created.
611 LLVMContext *Context;
613 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
614 CodeGenOpt::Level ol)
615 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
616 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
620 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
621 const TargetLibraryInfo *li);
623 /// clear - Clear out the current SelectionDAG and the associated
624 /// state and prepare this SelectionDAGBuilder object to be used
625 /// for a new block. This doesn't clear out information about
626 /// additional blocks that are needed to complete switch lowering
627 /// or PHI node updating; that information is cleared out as it is
631 /// clearDanglingDebugInfo - Clear the dangling debug information
632 /// map. This function is separated from the clear so that debug
633 /// information that is dangling in a basic block can be properly
634 /// resolved in a different basic block. This allows the
635 /// SelectionDAG to resolve dangling debug information attached
637 void clearDanglingDebugInfo();
639 /// getRoot - Return the current virtual root of the Selection DAG,
640 /// flushing any PendingLoad items. This must be done before emitting
641 /// a store or any other node that may need to be ordered after any
642 /// prior load instructions.
646 /// getControlRoot - Similar to getRoot, but instead of flushing all the
647 /// PendingLoad items, flush all the PendingExports items. It is necessary
648 /// to do this before emitting a terminator instruction.
650 SDValue getControlRoot();
652 SDLoc getCurSDLoc() const {
653 return SDLoc(CurInst, SDNodeOrder);
656 DebugLoc getCurDebugLoc() const {
657 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
660 unsigned getSDNodeOrder() const { return SDNodeOrder; }
662 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
664 void visit(const Instruction &I);
666 void visit(unsigned Opcode, const User &I);
668 /// getCopyFromRegs - If there was virtual register allocated for the value V
669 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
670 SDValue getCopyFromRegs(const Value *V, Type *Ty);
672 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
673 // generate the debug data structures now that we've seen its definition.
674 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
675 SDValue getValue(const Value *V);
676 bool findValue(const Value *V) const;
678 SDValue getNonRegisterValue(const Value *V);
679 SDValue getValueImpl(const Value *V);
681 void setValue(const Value *V, SDValue NewN) {
682 SDValue &N = NodeMap[V];
683 assert(!N.getNode() && "Already set a value for this node!");
687 void setUnusedArgValue(const Value *V, SDValue NewN) {
688 SDValue &N = UnusedArgNodeMap[V];
689 assert(!N.getNode() && "Already set a value for this node!");
693 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
694 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
695 MachineBasicBlock *SwitchBB,
696 Instruction::BinaryOps Opc,
697 uint32_t TW, uint32_t FW);
698 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
699 MachineBasicBlock *FBB,
700 MachineBasicBlock *CurBB,
701 MachineBasicBlock *SwitchBB,
702 uint32_t TW, uint32_t FW);
703 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
704 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
705 void CopyToExportRegsIfNeeded(const Value *V);
706 void ExportFromCurrentBlock(const Value *V);
707 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
708 MachineBasicBlock *LandingPad = nullptr);
710 std::pair<SDValue, SDValue> lowerCallOperands(
711 ImmutableCallSite CS,
716 MachineBasicBlock *LandingPad = nullptr,
717 bool IsPatchPoint = false);
719 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
720 /// references that need to refer to the last resulting block.
721 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
723 // This function is responsible for the whole statepoint lowering process.
724 // It uniformly handles invoke and call statepoints.
725 void LowerStatepoint(ImmutableStatepoint Statepoint,
726 MachineBasicBlock *LandingPad = nullptr);
728 std::pair<SDValue, SDValue> lowerInvokable(
729 TargetLowering::CallLoweringInfo &CLI,
730 MachineBasicBlock *LandingPad);
732 // Terminator instructions.
733 void visitRet(const ReturnInst &I);
734 void visitBr(const BranchInst &I);
735 void visitSwitch(const SwitchInst &I);
736 void visitIndirectBr(const IndirectBrInst &I);
737 void visitUnreachable(const UnreachableInst &I);
738 void visitCleanupRet(const CleanupReturnInst &I);
739 void visitCatchEndPad(const CatchEndPadInst &I);
740 void visitCatchRet(const CatchReturnInst &I);
741 void visitCatchPad(const CatchPadInst &I);
742 void visitTerminatePad(const TerminatePadInst &TPI);
743 void visitCleanupPad(const CleanupPadInst &CPI);
745 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
746 const MachineBasicBlock *Dst) const;
747 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
748 uint32_t Weight = 0);
750 void visitSwitchCase(CaseBlock &CB,
751 MachineBasicBlock *SwitchBB);
752 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
753 MachineBasicBlock *ParentBB);
754 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
755 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
756 void visitBitTestCase(BitTestBlock &BB,
757 MachineBasicBlock* NextMBB,
758 uint32_t BranchWeightToNext,
761 MachineBasicBlock *SwitchBB);
762 void visitJumpTable(JumpTable &JT);
763 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
764 MachineBasicBlock *SwitchBB);
767 // These all get lowered before this pass.
768 void visitInvoke(const InvokeInst &I);
769 void visitResume(const ResumeInst &I);
771 void visitBinary(const User &I, unsigned OpCode);
772 void visitShift(const User &I, unsigned Opcode);
773 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
774 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
775 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
776 void visitFSub(const User &I);
777 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
778 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
779 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
780 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
781 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
782 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
783 void visitSDiv(const User &I);
784 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
785 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
786 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
787 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
788 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
789 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
790 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
791 void visitICmp(const User &I);
792 void visitFCmp(const User &I);
793 // Visit the conversion instructions
794 void visitTrunc(const User &I);
795 void visitZExt(const User &I);
796 void visitSExt(const User &I);
797 void visitFPTrunc(const User &I);
798 void visitFPExt(const User &I);
799 void visitFPToUI(const User &I);
800 void visitFPToSI(const User &I);
801 void visitUIToFP(const User &I);
802 void visitSIToFP(const User &I);
803 void visitPtrToInt(const User &I);
804 void visitIntToPtr(const User &I);
805 void visitBitCast(const User &I);
806 void visitAddrSpaceCast(const User &I);
808 void visitExtractElement(const User &I);
809 void visitInsertElement(const User &I);
810 void visitShuffleVector(const User &I);
812 void visitExtractValue(const ExtractValueInst &I);
813 void visitInsertValue(const InsertValueInst &I);
814 void visitLandingPad(const LandingPadInst &I);
816 void visitGetElementPtr(const User &I);
817 void visitSelect(const User &I);
819 void visitAlloca(const AllocaInst &I);
820 void visitLoad(const LoadInst &I);
821 void visitStore(const StoreInst &I);
822 void visitMaskedLoad(const CallInst &I);
823 void visitMaskedStore(const CallInst &I);
824 void visitMaskedGather(const CallInst &I);
825 void visitMaskedScatter(const CallInst &I);
826 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
827 void visitAtomicRMW(const AtomicRMWInst &I);
828 void visitFence(const FenceInst &I);
829 void visitPHI(const PHINode &I);
830 void visitCall(const CallInst &I);
831 bool visitMemCmpCall(const CallInst &I);
832 bool visitMemChrCall(const CallInst &I);
833 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
834 bool visitStrCmpCall(const CallInst &I);
835 bool visitStrLenCall(const CallInst &I);
836 bool visitStrNLenCall(const CallInst &I);
837 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
838 bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
839 void visitAtomicLoad(const LoadInst &I);
840 void visitAtomicStore(const StoreInst &I);
842 void visitInlineAsm(ImmutableCallSite CS);
843 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
844 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
846 void visitVAStart(const CallInst &I);
847 void visitVAArg(const VAArgInst &I);
848 void visitVAEnd(const CallInst &I);
849 void visitVACopy(const CallInst &I);
850 void visitStackmap(const CallInst &I);
851 void visitPatchpoint(ImmutableCallSite CS,
852 MachineBasicBlock *LandingPad = nullptr);
854 // These three are implemented in StatepointLowering.cpp
855 void visitStatepoint(const CallInst &I);
856 void visitGCRelocate(const CallInst &I);
857 void visitGCResult(const CallInst &I);
859 void visitUserOp1(const Instruction &I) {
860 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
862 void visitUserOp2(const Instruction &I) {
863 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
866 void processIntegerCallValue(const Instruction &I,
867 SDValue Value, bool IsSigned);
869 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
871 /// EmitFuncArgumentDbgValue - If V is an function argument then create
872 /// corresponding DBG_VALUE machine instruction for it now. At the end of
873 /// instruction selection, they will be inserted to the entry BB.
874 bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
875 DIExpression *Expr, DILocation *DL,
876 int64_t Offset, bool IsIndirect,
879 /// Return the next block after MBB, or nullptr if there is none.
880 MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
882 /// Update the DAG and DAG builder with the relevant information after
883 /// a new root node has been created which could be a tail call.
884 void updateDAGForMaybeTailCall(SDValue MaybeTC);
887 /// RegsForValue - This struct represents the registers (physical or virtual)
888 /// that a particular set of values is assigned, and the type information about
889 /// the value. The most common situation is to represent one value at a time,
890 /// but struct or array values are handled element-wise as multiple values. The
891 /// splitting of aggregates is performed recursively, so that we never have
892 /// aggregate-typed registers. The values at this point do not necessarily have
893 /// legal types, so each value may require one or more registers of some legal
896 struct RegsForValue {
897 /// ValueVTs - The value types of the values, which may not be legal, and
898 /// may need be promoted or synthesized from one or more registers.
900 SmallVector<EVT, 4> ValueVTs;
902 /// RegVTs - The value types of the registers. This is the same size as
903 /// ValueVTs and it records, for each value, what the type of the assigned
904 /// register or registers are. (Individual values are never synthesized
905 /// from more than one type of register.)
907 /// With virtual registers, the contents of RegVTs is redundant with TLI's
908 /// getRegisterType member function, however when with physical registers
909 /// it is necessary to have a separate record of the types.
911 SmallVector<MVT, 4> RegVTs;
913 /// Regs - This list holds the registers assigned to the values.
914 /// Each legal or promoted value requires one register, and each
915 /// expanded value requires multiple registers.
917 SmallVector<unsigned, 4> Regs;
921 RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
923 RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
924 const DataLayout &DL, unsigned Reg, Type *Ty);
926 /// append - Add the specified values to this one.
927 void append(const RegsForValue &RHS) {
928 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
929 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
930 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
933 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
934 /// this value and returns the result as a ValueVTs value. This uses
935 /// Chain/Flag as the input and updates them for the output Chain/Flag.
936 /// If the Flag pointer is NULL, no flag is used.
937 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
939 SDValue &Chain, SDValue *Flag,
940 const Value *V = nullptr) const;
942 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified
943 /// value into the registers specified by this object. This uses Chain/Flag
944 /// as the input and updates them for the output Chain/Flag. If the Flag
945 /// pointer is nullptr, no flag is used. If V is not nullptr, then it is used
946 /// in printing better diagnostic messages on error.
948 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
949 SDValue *Flag, const Value *V = nullptr,
950 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
952 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
953 /// operand list. This adds the code marker, matching input operand index
954 /// (if applicable), and includes the number of values added into it.
955 void AddInlineAsmOperands(unsigned Kind,
956 bool HasMatching, unsigned MatchingIdx, SDLoc dl,
958 std::vector<SDValue> &Ops) const;
961 } // end namespace llvm