1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #ifndef SELECTIONDAGBUILDER_H
15 #define SELECTIONDAGBUILDER_H
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SelectionDAGNodes.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/Support/CallSite.h"
24 #include "llvm/Support/ErrorHandling.h"
36 class ExtractElementInst;
37 class ExtractValueInst;
44 class FunctionLoweringInfo;
45 class GetElementPtrInst;
51 class InsertElementInst;
52 class InsertValueInst;
55 class MachineBasicBlock;
57 class MachineRegisterInfo;
65 class ShuffleVectorInst;
70 class TargetLibraryInfo;
74 class UnreachableInst;
78 //===----------------------------------------------------------------------===//
79 /// SelectionDAGBuilder - This is the common target-independent lowering
80 /// implementation that is parameterized by a TargetLowering object.
82 class SelectionDAGBuilder {
83 /// CurInst - The current instruction being visited
84 const Instruction *CurInst;
86 DenseMap<const Value*, SDValue> NodeMap;
88 /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
89 /// to preserve debug information for incoming arguments.
90 DenseMap<const Value*, SDValue> UnusedArgNodeMap;
92 /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
93 class DanglingDebugInfo {
94 const DbgValueInst* DI;
98 DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
99 DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
100 DI(di), dl(DL), SDNodeOrder(SDNO) { }
101 const DbgValueInst* getDI() { return DI; }
102 DebugLoc getdl() { return dl; }
103 unsigned getSDNodeOrder() { return SDNodeOrder; }
106 /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
107 /// yet seen the referent. We defer handling these until we do see it.
108 DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
111 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
112 /// them up and then emit token factor nodes when possible. This allows us to
113 /// get simple disambiguation between loads without worrying about alias
115 SmallVector<SDValue, 8> PendingLoads;
118 /// PendingExports - CopyToReg nodes that copy values to virtual registers
119 /// for export to other blocks need to be emitted before any terminator
120 /// instruction, but they have no other ordering requirements. We bunch them
121 /// up and the emit a single tokenfactor for them just before terminator
123 SmallVector<SDValue, 8> PendingExports;
125 /// SDNodeOrder - A unique monotonically increasing number used to order the
126 /// SDNodes we create.
127 unsigned SDNodeOrder;
129 /// Case - A struct to record the Value for a switch case, and the
130 /// case's target basic block.
133 const Constant *High;
134 MachineBasicBlock* BB;
135 uint32_t ExtraWeight;
137 Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
138 Case(const Constant *low, const Constant *high, MachineBasicBlock *bb,
139 uint32_t extraweight) : Low(low), High(high), BB(bb),
140 ExtraWeight(extraweight) { }
143 const APInt &rHigh = cast<ConstantInt>(High)->getValue();
144 const APInt &rLow = cast<ConstantInt>(Low)->getValue();
145 return (rHigh - rLow + 1ULL);
151 MachineBasicBlock* BB;
153 uint32_t ExtraWeight;
155 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
157 Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
160 typedef std::vector<Case> CaseVector;
161 typedef std::vector<CaseBits> CaseBitsVector;
162 typedef CaseVector::iterator CaseItr;
163 typedef std::pair<CaseItr, CaseItr> CaseRange;
165 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
166 /// of conditional branches.
168 CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
170 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
172 /// CaseBB - The MBB in which to emit the compare and branch
173 MachineBasicBlock *CaseBB;
174 /// LT, GE - If nonzero, we know the current case value must be less-than or
175 /// greater-than-or-equal-to these Constants.
178 /// Range - A pair of iterators representing the range of case values to be
179 /// processed at this point in the binary search tree.
183 typedef std::vector<CaseRec> CaseRecVector;
185 /// The comparison function for sorting the switch case values in the vector.
186 /// WARNING: Case ranges should be disjoint!
188 bool operator()(const Case &C1, const Case &C2) {
189 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
190 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
191 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
192 return CI1->getValue().slt(CI2->getValue());
197 bool operator()(const CaseBits &C1, const CaseBits &C2) {
198 return C1.Bits > C2.Bits;
202 size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
204 /// CaseBlock - This structure is used to communicate between
205 /// SelectionDAGBuilder and SDISel for the code generation of additional basic
206 /// blocks needed by multi-case switch statements.
208 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
209 const Value *cmpmiddle,
210 MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
211 MachineBasicBlock *me,
212 uint32_t trueweight = 0, uint32_t falseweight = 0)
213 : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
214 TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
215 TrueWeight(trueweight), FalseWeight(falseweight) { }
217 // CC - the condition code to use for the case block's setcc node
220 // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
221 // Emit by default LHS op RHS. MHS is used for range comparisons:
222 // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
223 const Value *CmpLHS, *CmpMHS, *CmpRHS;
225 // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
226 MachineBasicBlock *TrueBB, *FalseBB;
228 // ThisBB - the block into which to emit the code for the setcc and branches
229 MachineBasicBlock *ThisBB;
231 // TrueWeight/FalseWeight - branch weights.
232 uint32_t TrueWeight, FalseWeight;
236 JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
237 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
239 /// Reg - the virtual register containing the index of the jump table entry
242 /// JTI - the JumpTableIndex for this jump table in the function.
244 /// MBB - the MBB into which to emit the code for the indirect jump.
245 MachineBasicBlock *MBB;
246 /// Default - the MBB of the default bb, which is a successor of the range
247 /// check MBB. This is when updating PHI nodes in successors.
248 MachineBasicBlock *Default;
250 struct JumpTableHeader {
251 JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
253 First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
257 MachineBasicBlock *HeaderBB;
260 typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
263 BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
265 Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
267 MachineBasicBlock *ThisBB;
268 MachineBasicBlock *TargetBB;
269 uint32_t ExtraWeight;
272 typedef SmallVector<BitTestCase, 3> BitTestInfo;
274 struct BitTestBlock {
275 BitTestBlock(APInt F, APInt R, const Value* SV,
276 unsigned Rg, MVT RgVT, bool E,
277 MachineBasicBlock* P, MachineBasicBlock* D,
278 const BitTestInfo& C):
279 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
280 Parent(P), Default(D), Cases(C) { }
287 MachineBasicBlock *Parent;
288 MachineBasicBlock *Default;
292 /// A class which encapsulates all of the information needed to generate a
293 /// stack protector check and signals to isel via its state being initialized
294 /// that a stack protector needs to be generated.
296 /// *NOTE* The following is a high level documentation of SelectionDAG Stack
297 /// Protector Generation. The reason that it is placed here is for a lack of
298 /// other good places to stick it.
300 /// High Level Overview of SelectionDAG Stack Protector Generation:
302 /// Previously, generation of stack protectors was done exclusively in the
303 /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
304 /// splitting basic blocks at the IR level to create the success/failure basic
305 /// blocks in the tail of the basic block in question. As a result of this,
306 /// calls that would have qualified for the sibling call optimization were no
307 /// longer eligible for optimization since said calls were no longer right in
308 /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
311 /// Then it was noticed that since the sibling call optimization causes the
312 /// callee to reuse the caller's stack, if we could delay the generation of
313 /// the stack protector check until later in CodeGen after the sibling call
314 /// decision was made, we get both the tail call optimization and the stack
317 /// A few goals in solving this problem were:
319 /// 1. Preserve the architecture independence of stack protector generation.
321 /// 2. Preserve the normal IR level stack protector check for platforms like
322 /// OpenBSD for which we support platform specific stack protector
325 /// The main problem that guided the present solution is that one can not
326 /// solve this problem in an architecture independent manner at the IR level
327 /// only. This is because:
329 /// 1. The decision on whether or not to perform a sibling call on certain
330 /// platforms (for instance i386) requires lower level information
331 /// related to available registers that can not be known at the IR level.
333 /// 2. Even if the previous point were not true, the decision on whether to
334 /// perform a tail call is done in LowerCallTo in SelectionDAG which
335 /// occurs after the Stack Protector Pass. As a result, one would need to
336 /// put the relevant callinst into the stack protector check success
337 /// basic block (where the return inst is placed) and then move it back
338 /// later at SelectionDAG/MI time before the stack protector check if the
339 /// tail call optimization failed. The MI level option was nixed
340 /// immediately since it would require platform specific pattern
341 /// matching. The SelectionDAG level option was nixed because
342 /// SelectionDAG only processes one IR level basic block at a time
343 /// implying one could not create a DAG Combine to move the callinst.
345 /// To get around this problem a few things were realized:
347 /// 1. While one can not handle multiple IR level basic blocks at the
348 /// SelectionDAG Level, one can generate multiple machine basic blocks
349 /// for one IR level basic block. This is how we handle bit tests and
352 /// 2. At the MI level, tail calls are represented via a special return
353 /// MIInst called "tcreturn". Thus if we know the basic block in which we
354 /// wish to insert the stack protector check, we get the correct behavior
355 /// by always inserting the stack protector check right before the return
356 /// statement. This is a "magical transformation" since no matter where
357 /// the stack protector check intrinsic is, we always insert the stack
358 /// protector check code at the end of the BB.
360 /// Given the aforementioned constraints, the following solution was devised:
362 /// 1. On platforms that do not support SelectionDAG stack protector check
363 /// generation, allow for the normal IR level stack protector check
364 /// generation to continue.
366 /// 2. On platforms that do support SelectionDAG stack protector check
369 /// a. Use the IR level stack protector pass to decide if a stack
370 /// protector is required/which BB we insert the stack protector check
371 /// in by reusing the logic already therein. If we wish to generate a
372 /// stack protector check in a basic block, we place a special IR
373 /// intrinsic called llvm.stackprotectorcheck right before the BB's
374 /// returninst or if there is a callinst that could potentially be
375 /// sibling call optimized, before the call inst.
377 /// b. Then when a BB with said intrinsic is processed, we codegen the BB
378 /// normally via SelectBasicBlock. In said process, when we visit the
379 /// stack protector check, we do not actually emit anything into the
380 /// BB. Instead, we just initialize the stack protector descriptor
381 /// class (which involves stashing information/creating the success
382 /// mbbb and the failure mbb if we have not created one for this
383 /// function yet) and export the guard variable that we are going to
386 /// c. After we finish selecting the basic block, in FinishBasicBlock if
387 /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
388 /// initialized, we first find a splice point in the parent basic block
389 /// before the terminator and then splice the terminator of said basic
390 /// block into the success basic block. Then we code-gen a new tail for
391 /// the parent basic block consisting of the two loads, the comparison,
392 /// and finally two branches to the success/failure basic blocks. We
393 /// conclude by code-gening the failure basic block if we have not
394 /// code-gened it already (all stack protector checks we generate in
395 /// the same function, use the same failure basic block).
396 class StackProtectorDescriptor {
398 StackProtectorDescriptor() : ParentMBB(0), SuccessMBB(0), FailureMBB(0),
400 ~StackProtectorDescriptor() { }
402 /// Returns true if all fields of the stack protector descriptor are
403 /// initialized implying that we should/are ready to emit a stack protector.
404 bool shouldEmitStackProtector() const {
405 return ParentMBB && SuccessMBB && FailureMBB && Guard;
408 /// Initialize the stack protector descriptor structure for a new basic
410 void initialize(const BasicBlock *BB,
411 MachineBasicBlock *MBB,
412 const CallInst &StackProtCheckCall) {
413 // Make sure we are not initialized yet.
414 assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
415 "already initialized!");
417 SuccessMBB = AddSuccessorMBB(BB, MBB);
418 FailureMBB = AddSuccessorMBB(BB, MBB, FailureMBB);
420 Guard = StackProtCheckCall.getArgOperand(0);
423 /// Reset state that changes when we handle different basic blocks.
425 /// This currently includes:
427 /// 1. The specific basic block we are generating a
428 /// stack protector for (ParentMBB).
430 /// 2. The successor machine basic block that will contain the tail of
431 /// parent mbb after we create the stack protector check (SuccessMBB). This
432 /// BB is visited only on stack protector check success.
433 void resetPerBBState() {
438 /// Reset state that only changes when we switch functions.
440 /// This currently includes:
442 /// 1. FailureMBB since we reuse the failure code path for all stack
443 /// protector checks created in an individual function.
445 /// 2.The guard variable since the guard variable we are checking against is
447 void resetPerFunctionState() {
452 MachineBasicBlock *getParentMBB() { return ParentMBB; }
453 MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
454 MachineBasicBlock *getFailureMBB() { return FailureMBB; }
455 const Value *getGuard() { return Guard; }
458 /// The basic block for which we are generating the stack protector.
460 /// As a result of stack protector generation, we will splice the
461 /// terminators of this basic block into the successor mbb SuccessMBB and
462 /// replace it with a compare/branch to the successor mbbs
463 /// SuccessMBB/FailureMBB depending on whether or not the stack protector
465 MachineBasicBlock *ParentMBB;
467 /// A basic block visited on stack protector check success that contains the
468 /// terminators of ParentMBB.
469 MachineBasicBlock *SuccessMBB;
471 /// This basic block visited on stack protector check failure that will
472 /// contain a call to __stack_chk_fail().
473 MachineBasicBlock *FailureMBB;
475 /// The guard variable which we will compare against the stored value in the
476 /// stack protector stack slot.
479 /// Add a successor machine basic block to ParentMBB. If the successor mbb
480 /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
481 /// block will be created.
482 MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
483 MachineBasicBlock *ParentMBB,
484 MachineBasicBlock *SuccMBB = 0);
488 const TargetMachine &TM;
491 const DataLayout *TD;
493 const TargetLibraryInfo *LibInfo;
495 /// SwitchCases - Vector of CaseBlock structures used to communicate
496 /// SwitchInst code generation information.
497 std::vector<CaseBlock> SwitchCases;
498 /// JTCases - Vector of JumpTable structures used to communicate
499 /// SwitchInst code generation information.
500 std::vector<JumpTableBlock> JTCases;
501 /// BitTestCases - Vector of BitTestBlock structures used to communicate
502 /// SwitchInst code generation information.
503 std::vector<BitTestBlock> BitTestCases;
504 /// A StackProtectorDescriptor structure used to communicate stack protector
505 /// information in between SelectBasicBlock and FinishBasicBlock.
506 StackProtectorDescriptor SPDescriptor;
508 // Emit PHI-node-operand constants only once even if used by multiple
510 DenseMap<const Constant *, unsigned> ConstantsOut;
512 /// FuncInfo - Information about the function as a whole.
514 FunctionLoweringInfo &FuncInfo;
516 /// OptLevel - What optimization level we're generating code for.
518 CodeGenOpt::Level OptLevel;
520 /// GFI - Garbage collection metadata for the function.
523 /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
524 DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
526 /// HasTailCall - This is set to true if a call in the current
527 /// block has been translated as a tail call. In this case,
528 /// no subsequent DAG nodes should be created.
532 LLVMContext *Context;
534 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
535 CodeGenOpt::Level ol)
536 : CurInst(NULL), SDNodeOrder(0), TM(dag.getTarget()),
537 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
541 void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
542 const TargetLibraryInfo *li);
544 /// clear - Clear out the current SelectionDAG and the associated
545 /// state and prepare this SelectionDAGBuilder object to be used
546 /// for a new block. This doesn't clear out information about
547 /// additional blocks that are needed to complete switch lowering
548 /// or PHI node updating; that information is cleared out as it is
552 /// clearDanglingDebugInfo - Clear the dangling debug information
553 /// map. This function is separated from the clear so that debug
554 /// information that is dangling in a basic block can be properly
555 /// resolved in a different basic block. This allows the
556 /// SelectionDAG to resolve dangling debug information attached
558 void clearDanglingDebugInfo();
560 /// getRoot - Return the current virtual root of the Selection DAG,
561 /// flushing any PendingLoad items. This must be done before emitting
562 /// a store or any other node that may need to be ordered after any
563 /// prior load instructions.
567 /// getControlRoot - Similar to getRoot, but instead of flushing all the
568 /// PendingLoad items, flush all the PendingExports items. It is necessary
569 /// to do this before emitting a terminator instruction.
571 SDValue getControlRoot();
573 SDLoc getCurSDLoc() const {
574 return SDLoc(CurInst, SDNodeOrder);
577 DebugLoc getCurDebugLoc() const {
578 return CurInst ? CurInst->getDebugLoc() : DebugLoc();
581 unsigned getSDNodeOrder() const { return SDNodeOrder; }
583 void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
585 void visit(const Instruction &I);
587 void visit(unsigned Opcode, const User &I);
589 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
590 // generate the debug data structures now that we've seen its definition.
591 void resolveDanglingDebugInfo(const Value *V, SDValue Val);
592 SDValue getValue(const Value *V);
593 SDValue getNonRegisterValue(const Value *V);
594 SDValue getValueImpl(const Value *V);
596 void setValue(const Value *V, SDValue NewN) {
597 SDValue &N = NodeMap[V];
598 assert(N.getNode() == 0 && "Already set a value for this node!");
602 void setUnusedArgValue(const Value *V, SDValue NewN) {
603 SDValue &N = UnusedArgNodeMap[V];
604 assert(N.getNode() == 0 && "Already set a value for this node!");
608 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
609 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
610 MachineBasicBlock *SwitchBB, unsigned Opc);
611 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
612 MachineBasicBlock *FBB,
613 MachineBasicBlock *CurBB,
614 MachineBasicBlock *SwitchBB);
615 bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
616 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
617 void CopyToExportRegsIfNeeded(const Value *V);
618 void ExportFromCurrentBlock(const Value *V);
619 void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
620 MachineBasicBlock *LandingPad = NULL);
622 /// UpdateSplitBlock - When an MBB was split during scheduling, update the
623 /// references that ned to refer to the last resulting block.
624 void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
627 // Terminator instructions.
628 void visitRet(const ReturnInst &I);
629 void visitBr(const BranchInst &I);
630 void visitSwitch(const SwitchInst &I);
631 void visitIndirectBr(const IndirectBrInst &I);
632 void visitUnreachable(const UnreachableInst &I) { /* noop */ }
634 // Helpers for visitSwitch
635 bool handleSmallSwitchRange(CaseRec& CR,
636 CaseRecVector& WorkList,
638 MachineBasicBlock* Default,
639 MachineBasicBlock *SwitchBB);
640 bool handleJTSwitchCase(CaseRec& CR,
641 CaseRecVector& WorkList,
643 MachineBasicBlock* Default,
644 MachineBasicBlock *SwitchBB);
645 bool handleBTSplitSwitchCase(CaseRec& CR,
646 CaseRecVector& WorkList,
648 MachineBasicBlock* Default,
649 MachineBasicBlock *SwitchBB);
650 bool handleBitTestsSwitchCase(CaseRec& CR,
651 CaseRecVector& WorkList,
653 MachineBasicBlock* Default,
654 MachineBasicBlock *SwitchBB);
656 uint32_t getEdgeWeight(const MachineBasicBlock *Src,
657 const MachineBasicBlock *Dst) const;
658 void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
659 uint32_t Weight = 0);
661 void visitSwitchCase(CaseBlock &CB,
662 MachineBasicBlock *SwitchBB);
663 void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
664 MachineBasicBlock *ParentBB);
665 void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
666 void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
667 void visitBitTestCase(BitTestBlock &BB,
668 MachineBasicBlock* NextMBB,
669 uint32_t BranchWeightToNext,
672 MachineBasicBlock *SwitchBB);
673 void visitJumpTable(JumpTable &JT);
674 void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
675 MachineBasicBlock *SwitchBB);
678 // These all get lowered before this pass.
679 void visitInvoke(const InvokeInst &I);
680 void visitResume(const ResumeInst &I);
682 void visitBinary(const User &I, unsigned OpCode);
683 void visitShift(const User &I, unsigned Opcode);
684 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
685 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
686 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
687 void visitFSub(const User &I);
688 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
689 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
690 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
691 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
692 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
693 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
694 void visitSDiv(const User &I);
695 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
696 void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
697 void visitOr (const User &I) { visitBinary(I, ISD::OR); }
698 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
699 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
700 void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
701 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
702 void visitICmp(const User &I);
703 void visitFCmp(const User &I);
704 // Visit the conversion instructions
705 void visitTrunc(const User &I);
706 void visitZExt(const User &I);
707 void visitSExt(const User &I);
708 void visitFPTrunc(const User &I);
709 void visitFPExt(const User &I);
710 void visitFPToUI(const User &I);
711 void visitFPToSI(const User &I);
712 void visitUIToFP(const User &I);
713 void visitSIToFP(const User &I);
714 void visitPtrToInt(const User &I);
715 void visitIntToPtr(const User &I);
716 void visitBitCast(const User &I);
718 void visitExtractElement(const User &I);
719 void visitInsertElement(const User &I);
720 void visitShuffleVector(const User &I);
722 void visitExtractValue(const ExtractValueInst &I);
723 void visitInsertValue(const InsertValueInst &I);
724 void visitLandingPad(const LandingPadInst &I);
726 void visitGetElementPtr(const User &I);
727 void visitSelect(const User &I);
729 void visitAlloca(const AllocaInst &I);
730 void visitLoad(const LoadInst &I);
731 void visitStore(const StoreInst &I);
732 void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
733 void visitAtomicRMW(const AtomicRMWInst &I);
734 void visitFence(const FenceInst &I);
735 void visitPHI(const PHINode &I);
736 void visitCall(const CallInst &I);
737 bool visitMemCmpCall(const CallInst &I);
738 bool visitMemChrCall(const CallInst &I);
739 bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
740 bool visitStrCmpCall(const CallInst &I);
741 bool visitStrLenCall(const CallInst &I);
742 bool visitStrNLenCall(const CallInst &I);
743 bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
744 void visitAtomicLoad(const LoadInst &I);
745 void visitAtomicStore(const StoreInst &I);
747 void visitInlineAsm(ImmutableCallSite CS);
748 const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
749 void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
751 void visitVAStart(const CallInst &I);
752 void visitVAArg(const VAArgInst &I);
753 void visitVAEnd(const CallInst &I);
754 void visitVACopy(const CallInst &I);
756 void visitUserOp1(const Instruction &I) {
757 llvm_unreachable("UserOp1 should not exist at instruction selection time!");
759 void visitUserOp2(const Instruction &I) {
760 llvm_unreachable("UserOp2 should not exist at instruction selection time!");
763 void processIntegerCallValue(const Instruction &I,
764 SDValue Value, bool IsSigned);
766 void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
768 /// EmitFuncArgumentDbgValue - If V is an function argument then create
769 /// corresponding DBG_VALUE machine instruction for it now. At the end of
770 /// instruction selection, they will be inserted to the entry BB.
771 bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
772 int64_t Offset, const SDValue &N);
775 } // end namespace llvm