1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert(PartVT.isInteger() && ValueVT.isInteger() &&
357 "Unknown mismatch!");
358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 } else if (PartBits == ValueVT.getSizeInBits()) {
362 // Different types of the same size.
363 assert(NumParts == 1 && PartVT != ValueVT);
364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
366 // If the parts cover less bits than value has, truncate the value.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Unknown mismatch!");
369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
373 // The value may have changed - recompute ValueVT.
374 ValueVT = Val.getValueType();
375 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
376 "Failed to tile the value with PartVT!");
379 assert(PartVT == ValueVT && "Type conversion failed!");
384 // Expand the value into multiple parts.
385 if (NumParts & (NumParts - 1)) {
386 // The number of parts is not a power of 2. Split off and copy the tail.
387 assert(PartVT.isInteger() && ValueVT.isInteger() &&
388 "Do not know what to expand to!");
389 unsigned RoundParts = 1 << Log2_32(NumParts);
390 unsigned RoundBits = RoundParts * PartBits;
391 unsigned OddParts = NumParts - RoundParts;
392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
393 DAG.getIntPtrConstant(RoundBits));
394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
396 if (TLI.isBigEndian())
397 // The odd parts were reversed by getCopyToParts - unreverse them.
398 std::reverse(Parts + RoundParts, Parts + NumParts);
400 NumParts = RoundParts;
401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 // The number of parts is a power of 2. Repeatedly bisect the value using
407 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
408 EVT::getIntegerVT(*DAG.getContext(),
409 ValueVT.getSizeInBits()),
412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
413 for (unsigned i = 0; i < NumParts; i += StepSize) {
414 unsigned ThisBits = StepSize * PartBits / 2;
415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
416 SDValue &Part0 = Parts[i];
417 SDValue &Part1 = Parts[i+StepSize/2];
419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
420 ThisVT, Part0, DAG.getIntPtrConstant(1));
421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
422 ThisVT, Part0, DAG.getIntPtrConstant(0));
424 if (ThisBits == PartBits && ThisVT != PartVT) {
425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
431 if (TLI.isBigEndian())
432 std::reverse(Parts, Parts + OrigNumParts);
436 /// getCopyToPartsVector - Create a series of nodes that contain the specified
437 /// value split into legal parts.
438 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
439 SDValue Val, SDValue *Parts, unsigned NumParts,
441 EVT ValueVT = Val.getValueType();
442 assert(ValueVT.isVector() && "Not a vector");
443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
446 if (PartVT == ValueVT) {
448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
449 // Bitconvert vector->vector case.
450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
451 } else if (PartVT.isVector() &&
452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
454 EVT ElementVT = PartVT.getVectorElementType();
455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
457 SmallVector<SDValue, 16> Ops;
458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
460 ElementVT, Val, DAG.getIntPtrConstant(i)));
462 for (unsigned i = ValueVT.getVectorNumElements(),
463 e = PartVT.getVectorNumElements(); i != e; ++i)
464 Ops.push_back(DAG.getUNDEF(ElementVT));
466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
468 // FIXME: Use CONCAT for 2x -> 4x.
470 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
472 } else if (PartVT.isVector() &&
473 PartVT.getVectorElementType().bitsGE(
474 ValueVT.getVectorElementType()) &&
475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
477 // Promoted vector extract
478 bool Smaller = PartVT.bitsLE(ValueVT);
479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
482 // Vector -> scalar conversion.
483 assert(ValueVT.getVectorNumElements() == 1 &&
484 "Only trivial vector-to-scalar conversions should get here!");
485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 PartVT, Val, DAG.getIntPtrConstant(0));
488 bool Smaller = ValueVT.bitsLE(PartVT);
489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
497 // Handle a multi-element vector.
498 EVT IntermediateVT, RegisterVT;
499 unsigned NumIntermediates;
500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
502 NumIntermediates, RegisterVT);
503 unsigned NumElements = ValueVT.getVectorNumElements();
505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
506 NumParts = NumRegs; // Silence a compiler warning.
507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
509 // Split the vector into intermediate operands.
510 SmallVector<SDValue, 8> Ops(NumIntermediates);
511 for (unsigned i = 0; i != NumIntermediates; ++i) {
512 if (IntermediateVT.isVector())
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 IntermediateVT, Val, DAG.getIntPtrConstant(i));
521 // Split the intermediate operands into legal parts.
522 if (NumParts == NumIntermediates) {
523 // If the register was not expanded, promote or copy the value,
525 for (unsigned i = 0; i != NumParts; ++i)
526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
527 } else if (NumParts > 0) {
528 // If the intermediate type was expanded, split each the value into
530 assert(NumParts % NumIntermediates == 0 &&
531 "Must expand into a divisible number of parts!");
532 unsigned Factor = NumParts / NumIntermediates;
533 for (unsigned i = 0; i != NumIntermediates; ++i)
534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
542 /// RegsForValue - This struct represents the registers (physical or virtual)
543 /// that a particular set of values is assigned, and the type information
544 /// about the value. The most common situation is to represent one value at a
545 /// time, but struct or array values are handled element-wise as multiple
546 /// values. The splitting of aggregates is performed recursively, so that we
547 /// never have aggregate-typed registers. The values at this point do not
548 /// necessarily have legal types, so each value may require one or more
549 /// registers of some legal type.
551 struct RegsForValue {
552 /// ValueVTs - The value types of the values, which may not be legal, and
553 /// may need be promoted or synthesized from one or more registers.
555 SmallVector<EVT, 4> ValueVTs;
557 /// RegVTs - The value types of the registers. This is the same size as
558 /// ValueVTs and it records, for each value, what the type of the assigned
559 /// register or registers are. (Individual values are never synthesized
560 /// from more than one type of register.)
562 /// With virtual registers, the contents of RegVTs is redundant with TLI's
563 /// getRegisterType member function, however when with physical registers
564 /// it is necessary to have a separate record of the types.
566 SmallVector<EVT, 4> RegVTs;
568 /// Regs - This list holds the registers assigned to the values.
569 /// Each legal or promoted value requires one register, and each
570 /// expanded value requires multiple registers.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> ®s,
577 EVT regvt, EVT valuevt)
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
580 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
581 unsigned Reg, Type *Ty) {
582 ComputeValueVTs(tli, Ty, ValueVTs);
584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
585 EVT ValueVT = ValueVTs[Value];
586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
588 for (unsigned i = 0; i != NumRegs; ++i)
589 Regs.push_back(Reg + i);
590 RegVTs.push_back(RegisterVT);
595 /// areValueTypesLegal - Return true if types of all the values are legal.
596 bool areValueTypesLegal(const TargetLowering &TLI) {
597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
598 EVT RegisterVT = RegVTs[Value];
599 if (!TLI.isTypeLegal(RegisterVT))
605 /// append - Add the specified values to this one.
606 void append(const RegsForValue &RHS) {
607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
613 /// this value and returns the result as a ValueVTs value. This uses
614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
615 /// If the Flag pointer is NULL, no flag is used.
616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
618 SDValue &Chain, SDValue *Flag) const;
620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
621 /// specified value into the registers specified by this object. This uses
622 /// Chain/Flag as the input and updates them for the output Chain/Flag.
623 /// If the Flag pointer is NULL, no flag is used.
624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
625 SDValue &Chain, SDValue *Flag) const;
627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
628 /// operand list. This adds the code marker, matching input operand index
629 /// (if applicable), and includes the number of values added into it.
630 void AddInlineAsmOperands(unsigned Kind,
631 bool HasMatching, unsigned MatchingIdx,
633 std::vector<SDValue> &Ops) const;
637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
638 /// this value and returns the result as a ValueVT value. This uses
639 /// Chain/Flag as the input and updates them for the output Chain/Flag.
640 /// If the Flag pointer is NULL, no flag is used.
641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
642 FunctionLoweringInfo &FuncInfo,
644 SDValue &Chain, SDValue *Flag) const {
645 // A Value with type {} or [0 x %t] needs no registers.
646 if (ValueVTs.empty())
649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
651 // Assemble the legal parts into the final values.
652 SmallVector<SDValue, 4> Values(ValueVTs.size());
653 SmallVector<SDValue, 8> Parts;
654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
655 // Copy the legal parts from the registers.
656 EVT ValueVT = ValueVTs[Value];
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
658 EVT RegisterVT = RegVTs[Value];
660 Parts.resize(NumRegs);
661 for (unsigned i = 0; i != NumRegs; ++i) {
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
667 *Flag = P.getValue(2);
670 Chain = P.getValue(1);
673 // If the source register was virtual and if we know something about it,
674 // add an assert node.
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
676 !RegisterVT.isInteger() || RegisterVT.isVector())
679 const FunctionLoweringInfo::LiveOutInfo *LOI =
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
684 unsigned RegSize = RegisterVT.getSizeInBits();
685 unsigned NumSignBits = LOI->NumSignBits;
686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
688 // FIXME: We capture more information than the dag can represent. For
689 // now, just use the tightest assertzext/assertsext possible.
691 EVT FromVT(MVT::Other);
692 if (NumSignBits == RegSize)
693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
694 else if (NumZeroBits >= RegSize-1)
695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
696 else if (NumSignBits > RegSize-8)
697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
698 else if (NumZeroBits >= RegSize-8)
699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
700 else if (NumSignBits > RegSize-16)
701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
702 else if (NumZeroBits >= RegSize-16)
703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
704 else if (NumSignBits > RegSize-32)
705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
706 else if (NumZeroBits >= RegSize-32)
707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
711 // Add an assertion node.
712 assert(FromVT != MVT::Other);
713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
714 RegisterVT, P, DAG.getValueType(FromVT));
717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
718 NumRegs, RegisterVT, ValueVT);
723 return DAG.getNode(ISD::MERGE_VALUES, dl,
724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
725 &Values[0], ValueVTs.size());
728 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
729 /// specified value into the registers specified by this object. This uses
730 /// Chain/Flag as the input and updates them for the output Chain/Flag.
731 /// If the Flag pointer is NULL, no flag is used.
732 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
733 SDValue &Chain, SDValue *Flag) const {
734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 // Get the list of the values's legal parts.
737 unsigned NumRegs = Regs.size();
738 SmallVector<SDValue, 8> Parts(NumRegs);
739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
740 EVT ValueVT = ValueVTs[Value];
741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
742 EVT RegisterVT = RegVTs[Value];
744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
745 &Parts[Part], NumParts, RegisterVT);
749 // Copy the parts into the registers.
750 SmallVector<SDValue, 8> Chains(NumRegs);
751 for (unsigned i = 0; i != NumRegs; ++i) {
754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
757 *Flag = Part.getValue(1);
760 Chains[i] = Part.getValue(0);
763 if (NumRegs == 1 || Flag)
764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
765 // flagged to it. That is the CopyToReg nodes and the user are considered
766 // a single scheduling unit. If we create a TokenFactor and return it as
767 // chain, then the TokenFactor is both a predecessor (operand) of the
768 // user as well as a successor (the TF operands are flagged to the user).
769 // c1, f1 = CopyToReg
770 // c2, f2 = CopyToReg
771 // c3 = TokenFactor c1, c2
774 Chain = Chains[NumRegs-1];
776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
779 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
780 /// operand list. This adds the code marker and includes the number of
781 /// values added into it.
782 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
783 unsigned MatchingIdx,
785 std::vector<SDValue> &Ops) const {
786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
796 EVT RegisterVT = RegVTs[Value];
797 for (unsigned i = 0; i != NumRegs; ++i) {
798 assert(Reg < Regs.size() && "Mismatch in # registers expected");
799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
804 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
807 TD = DAG.getTarget().getTargetData();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
821 CurDebugLoc = DebugLoc();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is seperated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
853 &PendingLoads[0], PendingLoads.size());
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
884 PendingExports.size());
885 PendingExports.clear();
890 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
892 DAG.AssignOrdering(Node, SDNodeOrder);
894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
895 AssignOrderingToNode(Node->getOperand(I).getNode());
898 void SelectionDAGBuilder::visit(const Instruction &I) {
899 // Set up outgoing PHI node register values before emitting the terminator.
900 if (isa<TerminatorInst>(&I))
901 HandlePHINodesInSuccessorBlocks(I.getParent());
903 CurDebugLoc = I.getDebugLoc();
905 visit(I.getOpcode(), I);
907 if (!isa<TerminatorInst>(&I) && !HasTailCall)
908 CopyToExportRegsIfNeeded(&I);
910 CurDebugLoc = DebugLoc();
913 void SelectionDAGBuilder::visitPHI(const PHINode &) {
914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
917 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
918 // Note: this doesn't use InstVisitor, because it has to work with
919 // ConstantExpr's in addition to instructions.
921 default: llvm_unreachable("Unknown instruction type encountered!");
922 // Build the switch statement using the Instruction.def file.
923 #define HANDLE_INST(NUM, OPCODE, CLASS) \
924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
925 #include "llvm/Instruction.def"
928 // Assign the ordering to the freshly created DAG nodes.
929 if (NodeMap.count(&I)) {
931 AssignOrderingToNode(getValue(&I).getNode());
935 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
936 // generate the debug data structures now that we've seen its definition.
937 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
941 const DbgValueInst *DI = DDI.getDI();
942 DebugLoc dl = DDI.getdl();
943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
944 MDNode *Variable = DI->getVariable();
945 uint64_t Offset = DI->getOffset();
948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
949 SDV = DAG.getDbgValue(Variable, Val.getNode(),
950 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
951 DAG.AddDbgValue(SDV, Val.getNode(), false);
954 DEBUG(dbgs() << "Dropping debug info for " << DI);
955 DanglingDebugInfoMap[V] = DanglingDebugInfo();
959 // getValue - Return an SDValue for the given Value.
960 SDValue SelectionDAGBuilder::getValue(const Value *V) {
961 // If we already have an SDValue for this value, use it. It's important
962 // to do this first, so that we don't create a CopyFromReg if we already
963 // have a regular SDValue.
964 SDValue &N = NodeMap[V];
965 if (N.getNode()) return N;
967 // If there's a virtual register allocated and initialized for this
969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
970 if (It != FuncInfo.ValueMap.end()) {
971 unsigned InReg = It->second;
972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
973 SDValue Chain = DAG.getEntryNode();
974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
975 resolveDanglingDebugInfo(V, N);
979 // Otherwise create a new SDValue and remember it.
980 SDValue Val = getValueImpl(V);
982 resolveDanglingDebugInfo(V, Val);
986 /// getNonRegisterValue - Return an SDValue for the given Value, but
987 /// don't look in FuncInfo.ValueMap for a virtual register.
988 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
989 // If we already have an SDValue for this value, use it.
990 SDValue &N = NodeMap[V];
991 if (N.getNode()) return N;
993 // Otherwise create a new SDValue and remember it.
994 SDValue Val = getValueImpl(V);
996 resolveDanglingDebugInfo(V, Val);
1000 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1001 /// Create an SDValue for the given value.
1002 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1003 if (const Constant *C = dyn_cast<Constant>(V)) {
1004 EVT VT = TLI.getValueType(V->getType(), true);
1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1007 return DAG.getConstant(*CI, VT);
1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1012 if (isa<ConstantPointerNull>(C))
1013 return DAG.getConstant(0, TLI.getPointerTy());
1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1016 return DAG.getConstantFP(*CFP, VT);
1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1019 return DAG.getUNDEF(VT);
1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1022 visit(CE->getOpcode(), *CE);
1023 SDValue N1 = NodeMap[V];
1024 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1029 SmallVector<SDValue, 4> Constants;
1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1032 SDNode *Val = getValue(*OI).getNode();
1033 // If the operand is an empty aggregate, there are no values.
1035 // Add each leaf value from the operand to the Constants list
1036 // to form a flattened list of all the values.
1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1038 Constants.push_back(SDValue(Val, i));
1041 return DAG.getMergeValues(&Constants[0], Constants.size(),
1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1047 "Unknown struct or array constant!");
1049 SmallVector<EVT, 4> ValueVTs;
1050 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1051 unsigned NumElts = ValueVTs.size();
1053 return SDValue(); // empty struct
1054 SmallVector<SDValue, 4> Constants(NumElts);
1055 for (unsigned i = 0; i != NumElts; ++i) {
1056 EVT EltVT = ValueVTs[i];
1057 if (isa<UndefValue>(C))
1058 Constants[i] = DAG.getUNDEF(EltVT);
1059 else if (EltVT.isFloatingPoint())
1060 Constants[i] = DAG.getConstantFP(0, EltVT);
1062 Constants[i] = DAG.getConstant(0, EltVT);
1065 return DAG.getMergeValues(&Constants[0], NumElts,
1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1070 return DAG.getBlockAddress(BA, VT);
1072 VectorType *VecTy = cast<VectorType>(V->getType());
1073 unsigned NumElements = VecTy->getNumElements();
1075 // Now that we know the number and type of the elements, get that number of
1076 // elements into the Ops array based on what kind of constant it is.
1077 SmallVector<SDValue, 16> Ops;
1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1079 for (unsigned i = 0; i != NumElements; ++i)
1080 Ops.push_back(getValue(CP->getOperand(i)));
1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1083 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1086 if (EltVT.isFloatingPoint())
1087 Op = DAG.getConstantFP(0, EltVT);
1089 Op = DAG.getConstant(0, EltVT);
1090 Ops.assign(NumElements, Op);
1093 // Create a BUILD_VECTOR node.
1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1095 VT, &Ops[0], Ops.size());
1098 // If this is a static alloca, generate it as the frameindex instead of
1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1101 DenseMap<const AllocaInst*, int>::iterator SI =
1102 FuncInfo.StaticAllocaMap.find(AI);
1103 if (SI != FuncInfo.StaticAllocaMap.end())
1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1107 // If this is an instruction which fast-isel has deferred, select it now.
1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1111 SDValue Chain = DAG.getEntryNode();
1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1115 llvm_unreachable("Can't get register for value!");
1119 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1120 SDValue Chain = getControlRoot();
1121 SmallVector<ISD::OutputArg, 8> Outs;
1122 SmallVector<SDValue, 8> OutVals;
1124 if (!FuncInfo.CanLowerReturn) {
1125 unsigned DemoteReg = FuncInfo.DemoteRegister;
1126 const Function *F = I.getParent()->getParent();
1128 // Emit a store of the return value through the virtual register.
1129 // Leave Outs empty so that LowerReturn won't try to load return
1130 // registers the usual way.
1131 SmallVector<EVT, 1> PtrValueVTs;
1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1136 SDValue RetOp = getValue(I.getOperand(0));
1138 SmallVector<EVT, 4> ValueVTs;
1139 SmallVector<uint64_t, 4> Offsets;
1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1141 unsigned NumValues = ValueVTs.size();
1143 SmallVector<SDValue, 4> Chains(NumValues);
1144 for (unsigned i = 0; i != NumValues; ++i) {
1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1146 RetPtr.getValueType(), RetPtr,
1147 DAG.getIntPtrConstant(Offsets[i]));
1149 DAG.getStore(Chain, getCurDebugLoc(),
1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1151 // FIXME: better loc info would be nice.
1152 Add, MachinePointerInfo(), false, false, 0);
1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1156 MVT::Other, &Chains[0], NumValues);
1157 } else if (I.getNumOperands() != 0) {
1158 SmallVector<EVT, 4> ValueVTs;
1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1160 unsigned NumValues = ValueVTs.size();
1162 SDValue RetOp = getValue(I.getOperand(0));
1163 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1164 EVT VT = ValueVTs[j];
1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1168 const Function *F = I.getParent()->getParent();
1169 if (F->paramHasAttr(0, Attribute::SExt))
1170 ExtendKind = ISD::SIGN_EXTEND;
1171 else if (F->paramHasAttr(0, Attribute::ZExt))
1172 ExtendKind = ISD::ZERO_EXTEND;
1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1179 SmallVector<SDValue, 4> Parts(NumParts);
1180 getCopyToParts(DAG, getCurDebugLoc(),
1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1182 &Parts[0], NumParts, PartVT, ExtendKind);
1184 // 'inreg' on function refers to return value
1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1186 if (F->paramHasAttr(0, Attribute::InReg))
1189 // Propagate extension type if any
1190 if (ExtendKind == ISD::SIGN_EXTEND)
1192 else if (ExtendKind == ISD::ZERO_EXTEND)
1195 for (unsigned i = 0; i < NumParts; ++i) {
1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1198 OutVals.push_back(Parts[i]);
1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1205 CallingConv::ID CallConv =
1206 DAG.getMachineFunction().getFunction()->getCallingConv();
1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1208 Outs, OutVals, getCurDebugLoc(), DAG);
1210 // Verify that the target's LowerReturn behaved as expected.
1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1212 "LowerReturn didn't return a valid chain!");
1214 // Update the DAG with the new chain value resulting from return lowering.
1218 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1219 /// created for it, emit nodes to copy the value into the virtual
1221 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1223 if (V->getType()->isEmptyTy())
1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1227 if (VMI != FuncInfo.ValueMap.end()) {
1228 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1229 CopyValueToVirtualRegister(V, VMI->second);
1233 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1234 /// the current basic block, add it to ValueMap now so that we'll get a
1236 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1237 // No need to export constants.
1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1240 // Already exported?
1241 if (FuncInfo.isExportedInst(V)) return;
1243 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1244 CopyValueToVirtualRegister(V, Reg);
1247 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1248 const BasicBlock *FromBB) {
1249 // The operands of the setcc have to be in this block. We don't know
1250 // how to export them from some other block.
1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1252 // Can export from current BB.
1253 if (VI->getParent() == FromBB)
1256 // Is already exported, noop.
1257 return FuncInfo.isExportedInst(V);
1260 // If this is an argument, we can export it if the BB is the entry block or
1261 // if it is already exported.
1262 if (isa<Argument>(V)) {
1263 if (FromBB == &FromBB->getParent()->getEntryBlock())
1266 // Otherwise, can only export this if it is already exported.
1267 return FuncInfo.isExportedInst(V);
1270 // Otherwise, constants can always be exported.
1274 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1275 uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src,
1276 MachineBasicBlock *Dst) {
1277 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1280 BasicBlock *SrcBB = const_cast<BasicBlock*>(Src->getBasicBlock());
1281 BasicBlock *DstBB = const_cast<BasicBlock*>(Dst->getBasicBlock());
1282 return BPI->getEdgeWeight(SrcBB, DstBB);
1285 void SelectionDAGBuilder::addSuccessorWithWeight(MachineBasicBlock *Src,
1286 MachineBasicBlock *Dst) {
1287 uint32_t weight = getEdgeWeight(Src, Dst);
1288 Src->addSuccessor(Dst, weight);
1292 static bool InBlock(const Value *V, const BasicBlock *BB) {
1293 if (const Instruction *I = dyn_cast<Instruction>(V))
1294 return I->getParent() == BB;
1298 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1299 /// This function emits a branch and is used at the leaves of an OR or an
1300 /// AND operator tree.
1303 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1304 MachineBasicBlock *TBB,
1305 MachineBasicBlock *FBB,
1306 MachineBasicBlock *CurBB,
1307 MachineBasicBlock *SwitchBB) {
1308 const BasicBlock *BB = CurBB->getBasicBlock();
1310 // If the leaf of the tree is a comparison, merge the condition into
1312 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1313 // The operands of the cmp have to be in this block. We don't know
1314 // how to export them from some other block. If this is the first block
1315 // of the sequence, no exporting is needed.
1316 if (CurBB == SwitchBB ||
1317 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1318 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1319 ISD::CondCode Condition;
1320 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1321 Condition = getICmpCondCode(IC->getPredicate());
1322 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1323 Condition = getFCmpCondCode(FC->getPredicate());
1325 Condition = ISD::SETEQ; // silence warning.
1326 llvm_unreachable("Unknown compare instruction");
1329 CaseBlock CB(Condition, BOp->getOperand(0),
1330 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1331 SwitchCases.push_back(CB);
1336 // Create a CaseBlock record representing this branch.
1337 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1338 NULL, TBB, FBB, CurBB);
1339 SwitchCases.push_back(CB);
1342 /// FindMergedConditions - If Cond is an expression like
1343 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1344 MachineBasicBlock *TBB,
1345 MachineBasicBlock *FBB,
1346 MachineBasicBlock *CurBB,
1347 MachineBasicBlock *SwitchBB,
1349 // If this node is not part of the or/and tree, emit it as a branch.
1350 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1351 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1352 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1353 BOp->getParent() != CurBB->getBasicBlock() ||
1354 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1355 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1356 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1360 // Create TmpBB after CurBB.
1361 MachineFunction::iterator BBI = CurBB;
1362 MachineFunction &MF = DAG.getMachineFunction();
1363 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1364 CurBB->getParent()->insert(++BBI, TmpBB);
1366 if (Opc == Instruction::Or) {
1367 // Codegen X | Y as:
1375 // Emit the LHS condition.
1376 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1378 // Emit the RHS condition into TmpBB.
1379 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1381 assert(Opc == Instruction::And && "Unknown merge op!");
1382 // Codegen X & Y as:
1389 // This requires creation of TmpBB after CurBB.
1391 // Emit the LHS condition.
1392 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1394 // Emit the RHS condition into TmpBB.
1395 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1399 /// If the set of cases should be emitted as a series of branches, return true.
1400 /// If we should emit this as a bunch of and/or'd together conditions, return
1403 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1404 if (Cases.size() != 2) return true;
1406 // If this is two comparisons of the same values or'd or and'd together, they
1407 // will get folded into a single comparison, so don't emit two blocks.
1408 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1409 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1410 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1411 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1415 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1416 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1417 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1418 Cases[0].CC == Cases[1].CC &&
1419 isa<Constant>(Cases[0].CmpRHS) &&
1420 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1421 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1430 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1431 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1433 // Update machine-CFG edges.
1434 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1436 // Figure out which block is immediately after the current one.
1437 MachineBasicBlock *NextBlock = 0;
1438 MachineFunction::iterator BBI = BrMBB;
1439 if (++BBI != FuncInfo.MF->end())
1442 if (I.isUnconditional()) {
1443 // Update machine-CFG edges.
1444 BrMBB->addSuccessor(Succ0MBB);
1446 // If this is not a fall-through branch, emit the branch.
1447 if (Succ0MBB != NextBlock)
1448 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1449 MVT::Other, getControlRoot(),
1450 DAG.getBasicBlock(Succ0MBB)));
1455 // If this condition is one of the special cases we handle, do special stuff
1457 const Value *CondVal = I.getCondition();
1458 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1460 // If this is a series of conditions that are or'd or and'd together, emit
1461 // this as a sequence of branches instead of setcc's with and/or operations.
1462 // As long as jumps are not expensive, this should improve performance.
1463 // For example, instead of something like:
1476 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1477 if (!TLI.isJumpExpensive() &&
1479 (BOp->getOpcode() == Instruction::And ||
1480 BOp->getOpcode() == Instruction::Or)) {
1481 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1483 // If the compares in later blocks need to use values not currently
1484 // exported from this block, export them now. This block should always
1485 // be the first entry.
1486 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1488 // Allow some cases to be rejected.
1489 if (ShouldEmitAsBranches(SwitchCases)) {
1490 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1491 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1492 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1495 // Emit the branch for this block.
1496 visitSwitchCase(SwitchCases[0], BrMBB);
1497 SwitchCases.erase(SwitchCases.begin());
1501 // Okay, we decided not to do this, remove any inserted MBB's and clear
1503 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1504 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1506 SwitchCases.clear();
1510 // Create a CaseBlock record representing this branch.
1511 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1512 NULL, Succ0MBB, Succ1MBB, BrMBB);
1514 // Use visitSwitchCase to actually insert the fast branch sequence for this
1516 visitSwitchCase(CB, BrMBB);
1519 /// visitSwitchCase - Emits the necessary code to represent a single node in
1520 /// the binary search tree resulting from lowering a switch instruction.
1521 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1522 MachineBasicBlock *SwitchBB) {
1524 SDValue CondLHS = getValue(CB.CmpLHS);
1525 DebugLoc dl = getCurDebugLoc();
1527 // Build the setcc now.
1528 if (CB.CmpMHS == NULL) {
1529 // Fold "(X == true)" to X and "(X == false)" to !X to
1530 // handle common cases produced by branch lowering.
1531 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1532 CB.CC == ISD::SETEQ)
1534 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1535 CB.CC == ISD::SETEQ) {
1536 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1537 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1539 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1541 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1543 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1544 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1546 SDValue CmpOp = getValue(CB.CmpMHS);
1547 EVT VT = CmpOp.getValueType();
1549 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1550 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1553 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1554 VT, CmpOp, DAG.getConstant(Low, VT));
1555 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1556 DAG.getConstant(High-Low, VT), ISD::SETULE);
1560 // Update successor info
1561 addSuccessorWithWeight(SwitchBB, CB.TrueBB);
1562 addSuccessorWithWeight(SwitchBB, CB.FalseBB);
1564 // Set NextBlock to be the MBB immediately after the current one, if any.
1565 // This is used to avoid emitting unnecessary branches to the next block.
1566 MachineBasicBlock *NextBlock = 0;
1567 MachineFunction::iterator BBI = SwitchBB;
1568 if (++BBI != FuncInfo.MF->end())
1571 // If the lhs block is the next block, invert the condition so that we can
1572 // fall through to the lhs instead of the rhs block.
1573 if (CB.TrueBB == NextBlock) {
1574 std::swap(CB.TrueBB, CB.FalseBB);
1575 SDValue True = DAG.getConstant(1, Cond.getValueType());
1576 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1579 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1580 MVT::Other, getControlRoot(), Cond,
1581 DAG.getBasicBlock(CB.TrueBB));
1583 // Insert the false branch. Do this even if it's a fall through branch,
1584 // this makes it easier to do DAG optimizations which require inverting
1585 // the branch condition.
1586 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1587 DAG.getBasicBlock(CB.FalseBB));
1589 DAG.setRoot(BrCond);
1592 /// visitJumpTable - Emit JumpTable node in the current MBB
1593 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1594 // Emit the code for the jump table
1595 assert(JT.Reg != -1U && "Should lower JT Header first!");
1596 EVT PTy = TLI.getPointerTy();
1597 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1599 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1600 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1601 MVT::Other, Index.getValue(1),
1603 DAG.setRoot(BrJumpTable);
1606 /// visitJumpTableHeader - This function emits necessary code to produce index
1607 /// in the JumpTable from switch case.
1608 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1609 JumpTableHeader &JTH,
1610 MachineBasicBlock *SwitchBB) {
1611 // Subtract the lowest switch case value from the value being switched on and
1612 // conditional branch to default mbb if the result is greater than the
1613 // difference between smallest and largest cases.
1614 SDValue SwitchOp = getValue(JTH.SValue);
1615 EVT VT = SwitchOp.getValueType();
1616 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1617 DAG.getConstant(JTH.First, VT));
1619 // The SDNode we just created, which holds the value being switched on minus
1620 // the smallest case value, needs to be copied to a virtual register so it
1621 // can be used as an index into the jump table in a subsequent basic block.
1622 // This value may be smaller or larger than the target's pointer type, and
1623 // therefore require extension or truncating.
1624 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1626 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1627 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1628 JumpTableReg, SwitchOp);
1629 JT.Reg = JumpTableReg;
1631 // Emit the range check for the jump table, and branch to the default block
1632 // for the switch statement if the value being switched on exceeds the largest
1633 // case in the switch.
1634 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1635 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1636 DAG.getConstant(JTH.Last-JTH.First,VT),
1639 // Set NextBlock to be the MBB immediately after the current one, if any.
1640 // This is used to avoid emitting unnecessary branches to the next block.
1641 MachineBasicBlock *NextBlock = 0;
1642 MachineFunction::iterator BBI = SwitchBB;
1644 if (++BBI != FuncInfo.MF->end())
1647 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1648 MVT::Other, CopyTo, CMP,
1649 DAG.getBasicBlock(JT.Default));
1651 if (JT.MBB != NextBlock)
1652 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1653 DAG.getBasicBlock(JT.MBB));
1655 DAG.setRoot(BrCond);
1658 /// visitBitTestHeader - This function emits necessary code to produce value
1659 /// suitable for "bit tests"
1660 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1661 MachineBasicBlock *SwitchBB) {
1662 // Subtract the minimum value
1663 SDValue SwitchOp = getValue(B.SValue);
1664 EVT VT = SwitchOp.getValueType();
1665 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1666 DAG.getConstant(B.First, VT));
1669 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1670 TLI.getSetCCResultType(Sub.getValueType()),
1671 Sub, DAG.getConstant(B.Range, VT),
1674 // Determine the type of the test operands.
1675 bool UsePtrType = false;
1676 if (!TLI.isTypeLegal(VT))
1679 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1680 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1681 // Switch table case range are encoded into series of masks.
1682 // Just use pointer type, it's guaranteed to fit.
1688 VT = TLI.getPointerTy();
1689 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1693 B.Reg = FuncInfo.CreateReg(VT);
1694 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1697 // Set NextBlock to be the MBB immediately after the current one, if any.
1698 // This is used to avoid emitting unnecessary branches to the next block.
1699 MachineBasicBlock *NextBlock = 0;
1700 MachineFunction::iterator BBI = SwitchBB;
1701 if (++BBI != FuncInfo.MF->end())
1704 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1706 addSuccessorWithWeight(SwitchBB, B.Default);
1707 addSuccessorWithWeight(SwitchBB, MBB);
1709 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1710 MVT::Other, CopyTo, RangeCmp,
1711 DAG.getBasicBlock(B.Default));
1713 if (MBB != NextBlock)
1714 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1715 DAG.getBasicBlock(MBB));
1717 DAG.setRoot(BrRange);
1720 /// visitBitTestCase - this function produces one "bit test"
1721 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1722 MachineBasicBlock* NextMBB,
1725 MachineBasicBlock *SwitchBB) {
1727 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1730 unsigned PopCount = CountPopulation_64(B.Mask);
1731 if (PopCount == 1) {
1732 // Testing for a single bit; just compare the shift count with what it
1733 // would need to be to shift a 1 bit in that position.
1734 Cmp = DAG.getSetCC(getCurDebugLoc(),
1735 TLI.getSetCCResultType(VT),
1737 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1739 } else if (PopCount == BB.Range) {
1740 // There is only one zero bit in the range, test for it directly.
1741 Cmp = DAG.getSetCC(getCurDebugLoc(),
1742 TLI.getSetCCResultType(VT),
1744 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1747 // Make desired shift
1748 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1749 DAG.getConstant(1, VT), ShiftOp);
1751 // Emit bit tests and jumps
1752 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1753 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1754 Cmp = DAG.getSetCC(getCurDebugLoc(),
1755 TLI.getSetCCResultType(VT),
1756 AndOp, DAG.getConstant(0, VT),
1760 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1761 addSuccessorWithWeight(SwitchBB, NextMBB);
1763 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1764 MVT::Other, getControlRoot(),
1765 Cmp, DAG.getBasicBlock(B.TargetBB));
1767 // Set NextBlock to be the MBB immediately after the current one, if any.
1768 // This is used to avoid emitting unnecessary branches to the next block.
1769 MachineBasicBlock *NextBlock = 0;
1770 MachineFunction::iterator BBI = SwitchBB;
1771 if (++BBI != FuncInfo.MF->end())
1774 if (NextMBB != NextBlock)
1775 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1776 DAG.getBasicBlock(NextMBB));
1781 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1782 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1784 // Retrieve successors.
1785 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1786 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1788 const Value *Callee(I.getCalledValue());
1789 if (isa<InlineAsm>(Callee))
1792 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1794 // If the value of the invoke is used outside of its defining block, make it
1795 // available as a virtual register.
1796 CopyToExportRegsIfNeeded(&I);
1798 // Update successor info
1799 InvokeMBB->addSuccessor(Return);
1800 InvokeMBB->addSuccessor(LandingPad);
1802 // Drop into normal successor.
1803 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1804 MVT::Other, getControlRoot(),
1805 DAG.getBasicBlock(Return)));
1808 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1811 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1812 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1815 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &) {
1816 // FIXME: Handle this
1817 assert(FuncInfo.MBB->isLandingPad() &&
1818 "Call to landingpad not in landing pad!");
1821 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1822 /// small case ranges).
1823 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1824 CaseRecVector& WorkList,
1826 MachineBasicBlock *Default,
1827 MachineBasicBlock *SwitchBB) {
1828 Case& BackCase = *(CR.Range.second-1);
1830 // Size is the number of Cases represented by this range.
1831 size_t Size = CR.Range.second - CR.Range.first;
1835 // Get the MachineFunction which holds the current MBB. This is used when
1836 // inserting any additional MBBs necessary to represent the switch.
1837 MachineFunction *CurMF = FuncInfo.MF;
1839 // Figure out which block is immediately after the current one.
1840 MachineBasicBlock *NextBlock = 0;
1841 MachineFunction::iterator BBI = CR.CaseBB;
1843 if (++BBI != FuncInfo.MF->end())
1846 // If any two of the cases has the same destination, and if one value
1847 // is the same as the other, but has one bit unset that the other has set,
1848 // use bit manipulation to do two compares at once. For example:
1849 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1850 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1851 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1852 if (Size == 2 && CR.CaseBB == SwitchBB) {
1853 Case &Small = *CR.Range.first;
1854 Case &Big = *(CR.Range.second-1);
1856 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1857 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1858 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1860 // Check that there is only one bit different.
1861 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1862 (SmallValue | BigValue) == BigValue) {
1863 // Isolate the common bit.
1864 APInt CommonBit = BigValue & ~SmallValue;
1865 assert((SmallValue | CommonBit) == BigValue &&
1866 CommonBit.countPopulation() == 1 && "Not a common bit?");
1868 SDValue CondLHS = getValue(SV);
1869 EVT VT = CondLHS.getValueType();
1870 DebugLoc DL = getCurDebugLoc();
1872 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1873 DAG.getConstant(CommonBit, VT));
1874 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1875 Or, DAG.getConstant(BigValue, VT),
1878 // Update successor info.
1879 SwitchBB->addSuccessor(Small.BB);
1880 SwitchBB->addSuccessor(Default);
1882 // Insert the true branch.
1883 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1884 getControlRoot(), Cond,
1885 DAG.getBasicBlock(Small.BB));
1887 // Insert the false branch.
1888 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1889 DAG.getBasicBlock(Default));
1891 DAG.setRoot(BrCond);
1897 // Rearrange the case blocks so that the last one falls through if possible.
1898 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1899 // The last case block won't fall through into 'NextBlock' if we emit the
1900 // branches in this order. See if rearranging a case value would help.
1901 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1902 if (I->BB == NextBlock) {
1903 std::swap(*I, BackCase);
1909 // Create a CaseBlock record representing a conditional branch to
1910 // the Case's target mbb if the value being switched on SV is equal
1912 MachineBasicBlock *CurBlock = CR.CaseBB;
1913 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1914 MachineBasicBlock *FallThrough;
1916 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1917 CurMF->insert(BBI, FallThrough);
1919 // Put SV in a virtual register to make it available from the new blocks.
1920 ExportFromCurrentBlock(SV);
1922 // If the last case doesn't match, go to the default block.
1923 FallThrough = Default;
1926 const Value *RHS, *LHS, *MHS;
1928 if (I->High == I->Low) {
1929 // This is just small small case range :) containing exactly 1 case
1931 LHS = SV; RHS = I->High; MHS = NULL;
1934 LHS = I->Low; MHS = SV; RHS = I->High;
1936 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1938 // If emitting the first comparison, just call visitSwitchCase to emit the
1939 // code into the current block. Otherwise, push the CaseBlock onto the
1940 // vector to be later processed by SDISel, and insert the node's MBB
1941 // before the next MBB.
1942 if (CurBlock == SwitchBB)
1943 visitSwitchCase(CB, SwitchBB);
1945 SwitchCases.push_back(CB);
1947 CurBlock = FallThrough;
1953 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1954 return !DisableJumpTables &&
1955 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1956 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1959 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1960 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1961 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1962 return (LastExt - FirstExt + 1ULL);
1965 /// handleJTSwitchCase - Emit jumptable for current switch case range
1966 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1967 CaseRecVector& WorkList,
1969 MachineBasicBlock* Default,
1970 MachineBasicBlock *SwitchBB) {
1971 Case& FrontCase = *CR.Range.first;
1972 Case& BackCase = *(CR.Range.second-1);
1974 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1975 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1977 APInt TSize(First.getBitWidth(), 0);
1978 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1982 if (!areJTsAllowed(TLI) || TSize.ult(4))
1985 APInt Range = ComputeRange(First, Last);
1986 double Density = TSize.roundToDouble() / Range.roundToDouble();
1990 DEBUG(dbgs() << "Lowering jump table\n"
1991 << "First entry: " << First << ". Last entry: " << Last << '\n'
1992 << "Range: " << Range
1993 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1995 // Get the MachineFunction which holds the current MBB. This is used when
1996 // inserting any additional MBBs necessary to represent the switch.
1997 MachineFunction *CurMF = FuncInfo.MF;
1999 // Figure out which block is immediately after the current one.
2000 MachineFunction::iterator BBI = CR.CaseBB;
2003 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2005 // Create a new basic block to hold the code for loading the address
2006 // of the jump table, and jumping to it. Update successor information;
2007 // we will either branch to the default case for the switch, or the jump
2009 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2010 CurMF->insert(BBI, JumpTableBB);
2012 addSuccessorWithWeight(CR.CaseBB, Default);
2013 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2015 // Build a vector of destination BBs, corresponding to each target
2016 // of the jump table. If the value of the jump table slot corresponds to
2017 // a case statement, push the case's BB onto the vector, otherwise, push
2019 std::vector<MachineBasicBlock*> DestBBs;
2021 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2022 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2023 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2025 if (Low.sle(TEI) && TEI.sle(High)) {
2026 DestBBs.push_back(I->BB);
2030 DestBBs.push_back(Default);
2034 // Update successor info. Add one edge to each unique successor.
2035 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2036 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2037 E = DestBBs.end(); I != E; ++I) {
2038 if (!SuccsHandled[(*I)->getNumber()]) {
2039 SuccsHandled[(*I)->getNumber()] = true;
2040 addSuccessorWithWeight(JumpTableBB, *I);
2044 // Create a jump table index for this jump table.
2045 unsigned JTEncoding = TLI.getJumpTableEncoding();
2046 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2047 ->createJumpTableIndex(DestBBs);
2049 // Set the jump table information so that we can codegen it as a second
2050 // MachineBasicBlock
2051 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2052 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2053 if (CR.CaseBB == SwitchBB)
2054 visitJumpTableHeader(JT, JTH, SwitchBB);
2056 JTCases.push_back(JumpTableBlock(JTH, JT));
2061 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2063 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2064 CaseRecVector& WorkList,
2066 MachineBasicBlock *Default,
2067 MachineBasicBlock *SwitchBB) {
2068 // Get the MachineFunction which holds the current MBB. This is used when
2069 // inserting any additional MBBs necessary to represent the switch.
2070 MachineFunction *CurMF = FuncInfo.MF;
2072 // Figure out which block is immediately after the current one.
2073 MachineFunction::iterator BBI = CR.CaseBB;
2076 Case& FrontCase = *CR.Range.first;
2077 Case& BackCase = *(CR.Range.second-1);
2078 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2080 // Size is the number of Cases represented by this range.
2081 unsigned Size = CR.Range.second - CR.Range.first;
2083 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2084 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2086 CaseItr Pivot = CR.Range.first + Size/2;
2088 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2089 // (heuristically) allow us to emit JumpTable's later.
2090 APInt TSize(First.getBitWidth(), 0);
2091 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2095 APInt LSize = FrontCase.size();
2096 APInt RSize = TSize-LSize;
2097 DEBUG(dbgs() << "Selecting best pivot: \n"
2098 << "First: " << First << ", Last: " << Last <<'\n'
2099 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2100 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2102 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2103 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2104 APInt Range = ComputeRange(LEnd, RBegin);
2105 assert((Range - 2ULL).isNonNegative() &&
2106 "Invalid case distance");
2107 // Use volatile double here to avoid excess precision issues on some hosts,
2108 // e.g. that use 80-bit X87 registers.
2109 volatile double LDensity =
2110 (double)LSize.roundToDouble() /
2111 (LEnd - First + 1ULL).roundToDouble();
2112 volatile double RDensity =
2113 (double)RSize.roundToDouble() /
2114 (Last - RBegin + 1ULL).roundToDouble();
2115 double Metric = Range.logBase2()*(LDensity+RDensity);
2116 // Should always split in some non-trivial place
2117 DEBUG(dbgs() <<"=>Step\n"
2118 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2119 << "LDensity: " << LDensity
2120 << ", RDensity: " << RDensity << '\n'
2121 << "Metric: " << Metric << '\n');
2122 if (FMetric < Metric) {
2125 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2131 if (areJTsAllowed(TLI)) {
2132 // If our case is dense we *really* should handle it earlier!
2133 assert((FMetric > 0) && "Should handle dense range earlier!");
2135 Pivot = CR.Range.first + Size/2;
2138 CaseRange LHSR(CR.Range.first, Pivot);
2139 CaseRange RHSR(Pivot, CR.Range.second);
2140 Constant *C = Pivot->Low;
2141 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2143 // We know that we branch to the LHS if the Value being switched on is
2144 // less than the Pivot value, C. We use this to optimize our binary
2145 // tree a bit, by recognizing that if SV is greater than or equal to the
2146 // LHS's Case Value, and that Case Value is exactly one less than the
2147 // Pivot's Value, then we can branch directly to the LHS's Target,
2148 // rather than creating a leaf node for it.
2149 if ((LHSR.second - LHSR.first) == 1 &&
2150 LHSR.first->High == CR.GE &&
2151 cast<ConstantInt>(C)->getValue() ==
2152 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2153 TrueBB = LHSR.first->BB;
2155 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2156 CurMF->insert(BBI, TrueBB);
2157 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2159 // Put SV in a virtual register to make it available from the new blocks.
2160 ExportFromCurrentBlock(SV);
2163 // Similar to the optimization above, if the Value being switched on is
2164 // known to be less than the Constant CR.LT, and the current Case Value
2165 // is CR.LT - 1, then we can branch directly to the target block for
2166 // the current Case Value, rather than emitting a RHS leaf node for it.
2167 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2168 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2169 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2170 FalseBB = RHSR.first->BB;
2172 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2173 CurMF->insert(BBI, FalseBB);
2174 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2176 // Put SV in a virtual register to make it available from the new blocks.
2177 ExportFromCurrentBlock(SV);
2180 // Create a CaseBlock record representing a conditional branch to
2181 // the LHS node if the value being switched on SV is less than C.
2182 // Otherwise, branch to LHS.
2183 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2185 if (CR.CaseBB == SwitchBB)
2186 visitSwitchCase(CB, SwitchBB);
2188 SwitchCases.push_back(CB);
2193 /// handleBitTestsSwitchCase - if current case range has few destination and
2194 /// range span less, than machine word bitwidth, encode case range into series
2195 /// of masks and emit bit tests with these masks.
2196 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2197 CaseRecVector& WorkList,
2199 MachineBasicBlock* Default,
2200 MachineBasicBlock *SwitchBB){
2201 EVT PTy = TLI.getPointerTy();
2202 unsigned IntPtrBits = PTy.getSizeInBits();
2204 Case& FrontCase = *CR.Range.first;
2205 Case& BackCase = *(CR.Range.second-1);
2207 // Get the MachineFunction which holds the current MBB. This is used when
2208 // inserting any additional MBBs necessary to represent the switch.
2209 MachineFunction *CurMF = FuncInfo.MF;
2211 // If target does not have legal shift left, do not emit bit tests at all.
2212 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2216 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2218 // Single case counts one, case range - two.
2219 numCmps += (I->Low == I->High ? 1 : 2);
2222 // Count unique destinations
2223 SmallSet<MachineBasicBlock*, 4> Dests;
2224 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2225 Dests.insert(I->BB);
2226 if (Dests.size() > 3)
2227 // Don't bother the code below, if there are too much unique destinations
2230 DEBUG(dbgs() << "Total number of unique destinations: "
2231 << Dests.size() << '\n'
2232 << "Total number of comparisons: " << numCmps << '\n');
2234 // Compute span of values.
2235 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2236 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2237 APInt cmpRange = maxValue - minValue;
2239 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2240 << "Low bound: " << minValue << '\n'
2241 << "High bound: " << maxValue << '\n');
2243 if (cmpRange.uge(IntPtrBits) ||
2244 (!(Dests.size() == 1 && numCmps >= 3) &&
2245 !(Dests.size() == 2 && numCmps >= 5) &&
2246 !(Dests.size() >= 3 && numCmps >= 6)))
2249 DEBUG(dbgs() << "Emitting bit tests\n");
2250 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2252 // Optimize the case where all the case values fit in a
2253 // word without having to subtract minValue. In this case,
2254 // we can optimize away the subtraction.
2255 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2256 cmpRange = maxValue;
2258 lowBound = minValue;
2261 CaseBitsVector CasesBits;
2262 unsigned i, count = 0;
2264 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2265 MachineBasicBlock* Dest = I->BB;
2266 for (i = 0; i < count; ++i)
2267 if (Dest == CasesBits[i].BB)
2271 assert((count < 3) && "Too much destinations to test!");
2272 CasesBits.push_back(CaseBits(0, Dest, 0));
2276 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2277 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2279 uint64_t lo = (lowValue - lowBound).getZExtValue();
2280 uint64_t hi = (highValue - lowBound).getZExtValue();
2282 for (uint64_t j = lo; j <= hi; j++) {
2283 CasesBits[i].Mask |= 1ULL << j;
2284 CasesBits[i].Bits++;
2288 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2292 // Figure out which block is immediately after the current one.
2293 MachineFunction::iterator BBI = CR.CaseBB;
2296 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2298 DEBUG(dbgs() << "Cases:\n");
2299 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2300 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2301 << ", Bits: " << CasesBits[i].Bits
2302 << ", BB: " << CasesBits[i].BB << '\n');
2304 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2305 CurMF->insert(BBI, CaseBB);
2306 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2310 // Put SV in a virtual register to make it available from the new blocks.
2311 ExportFromCurrentBlock(SV);
2314 BitTestBlock BTB(lowBound, cmpRange, SV,
2315 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2316 CR.CaseBB, Default, BTC);
2318 if (CR.CaseBB == SwitchBB)
2319 visitBitTestHeader(BTB, SwitchBB);
2321 BitTestCases.push_back(BTB);
2326 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2327 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2328 const SwitchInst& SI) {
2331 // Start with "simple" cases
2332 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2333 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2334 Cases.push_back(Case(SI.getSuccessorValue(i),
2335 SI.getSuccessorValue(i),
2338 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2340 // Merge case into clusters
2341 if (Cases.size() >= 2)
2342 // Must recompute end() each iteration because it may be
2343 // invalidated by erase if we hold on to it
2344 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2345 J != Cases.end(); ) {
2346 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2347 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2348 MachineBasicBlock* nextBB = J->BB;
2349 MachineBasicBlock* currentBB = I->BB;
2351 // If the two neighboring cases go to the same destination, merge them
2352 // into a single case.
2353 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2361 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2362 if (I->Low != I->High)
2363 // A range counts double, since it requires two compares.
2370 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2371 MachineBasicBlock *Last) {
2373 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2374 if (JTCases[i].first.HeaderBB == First)
2375 JTCases[i].first.HeaderBB = Last;
2377 // Update BitTestCases.
2378 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2379 if (BitTestCases[i].Parent == First)
2380 BitTestCases[i].Parent = Last;
2383 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2384 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2386 // Figure out which block is immediately after the current one.
2387 MachineBasicBlock *NextBlock = 0;
2388 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2390 // If there is only the default destination, branch to it if it is not the
2391 // next basic block. Otherwise, just fall through.
2392 if (SI.getNumOperands() == 2) {
2393 // Update machine-CFG edges.
2395 // If this is not a fall-through branch, emit the branch.
2396 SwitchMBB->addSuccessor(Default);
2397 if (Default != NextBlock)
2398 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2399 MVT::Other, getControlRoot(),
2400 DAG.getBasicBlock(Default)));
2405 // If there are any non-default case statements, create a vector of Cases
2406 // representing each one, and sort the vector so that we can efficiently
2407 // create a binary search tree from them.
2409 size_t numCmps = Clusterify(Cases, SI);
2410 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2411 << ". Total compares: " << numCmps << '\n');
2414 // Get the Value to be switched on and default basic blocks, which will be
2415 // inserted into CaseBlock records, representing basic blocks in the binary
2417 const Value *SV = SI.getOperand(0);
2419 // Push the initial CaseRec onto the worklist
2420 CaseRecVector WorkList;
2421 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2422 CaseRange(Cases.begin(),Cases.end())));
2424 while (!WorkList.empty()) {
2425 // Grab a record representing a case range to process off the worklist
2426 CaseRec CR = WorkList.back();
2427 WorkList.pop_back();
2429 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2432 // If the range has few cases (two or less) emit a series of specific
2434 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2437 // If the switch has more than 5 blocks, and at least 40% dense, and the
2438 // target supports indirect branches, then emit a jump table rather than
2439 // lowering the switch to a binary tree of conditional branches.
2440 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2443 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2444 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2445 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2449 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2450 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2452 // Update machine-CFG edges with unique successors.
2453 SmallVector<BasicBlock*, 32> succs;
2454 succs.reserve(I.getNumSuccessors());
2455 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2456 succs.push_back(I.getSuccessor(i));
2457 array_pod_sort(succs.begin(), succs.end());
2458 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2459 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2460 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2461 addSuccessorWithWeight(IndirectBrMBB, Succ);
2464 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2465 MVT::Other, getControlRoot(),
2466 getValue(I.getAddress())));
2469 void SelectionDAGBuilder::visitFSub(const User &I) {
2470 // -0.0 - X --> fneg
2471 Type *Ty = I.getType();
2472 if (isa<Constant>(I.getOperand(0)) &&
2473 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2474 SDValue Op2 = getValue(I.getOperand(1));
2475 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2476 Op2.getValueType(), Op2));
2480 visitBinary(I, ISD::FSUB);
2483 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2484 SDValue Op1 = getValue(I.getOperand(0));
2485 SDValue Op2 = getValue(I.getOperand(1));
2486 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2487 Op1.getValueType(), Op1, Op2));
2490 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2491 SDValue Op1 = getValue(I.getOperand(0));
2492 SDValue Op2 = getValue(I.getOperand(1));
2494 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2496 // Coerce the shift amount to the right type if we can.
2497 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2498 unsigned ShiftSize = ShiftTy.getSizeInBits();
2499 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2500 DebugLoc DL = getCurDebugLoc();
2502 // If the operand is smaller than the shift count type, promote it.
2503 if (ShiftSize > Op2Size)
2504 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2506 // If the operand is larger than the shift count type but the shift
2507 // count type has enough bits to represent any shift value, truncate
2508 // it now. This is a common case and it exposes the truncate to
2509 // optimization early.
2510 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2511 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2512 // Otherwise we'll need to temporarily settle for some other convenient
2513 // type. Type legalization will make adjustments once the shiftee is split.
2515 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2518 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2519 Op1.getValueType(), Op1, Op2));
2522 void SelectionDAGBuilder::visitSDiv(const User &I) {
2523 SDValue Op1 = getValue(I.getOperand(0));
2524 SDValue Op2 = getValue(I.getOperand(1));
2526 // Turn exact SDivs into multiplications.
2527 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2529 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2530 !isa<ConstantSDNode>(Op1) &&
2531 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2532 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2534 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2538 void SelectionDAGBuilder::visitICmp(const User &I) {
2539 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2540 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2541 predicate = IC->getPredicate();
2542 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2543 predicate = ICmpInst::Predicate(IC->getPredicate());
2544 SDValue Op1 = getValue(I.getOperand(0));
2545 SDValue Op2 = getValue(I.getOperand(1));
2546 ISD::CondCode Opcode = getICmpCondCode(predicate);
2548 EVT DestVT = TLI.getValueType(I.getType());
2549 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2552 void SelectionDAGBuilder::visitFCmp(const User &I) {
2553 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2554 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2555 predicate = FC->getPredicate();
2556 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2557 predicate = FCmpInst::Predicate(FC->getPredicate());
2558 SDValue Op1 = getValue(I.getOperand(0));
2559 SDValue Op2 = getValue(I.getOperand(1));
2560 ISD::CondCode Condition = getFCmpCondCode(predicate);
2561 EVT DestVT = TLI.getValueType(I.getType());
2562 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2565 void SelectionDAGBuilder::visitSelect(const User &I) {
2566 SmallVector<EVT, 4> ValueVTs;
2567 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2568 unsigned NumValues = ValueVTs.size();
2569 if (NumValues == 0) return;
2571 SmallVector<SDValue, 4> Values(NumValues);
2572 SDValue Cond = getValue(I.getOperand(0));
2573 SDValue TrueVal = getValue(I.getOperand(1));
2574 SDValue FalseVal = getValue(I.getOperand(2));
2576 for (unsigned i = 0; i != NumValues; ++i)
2577 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2578 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2580 SDValue(TrueVal.getNode(),
2581 TrueVal.getResNo() + i),
2582 SDValue(FalseVal.getNode(),
2583 FalseVal.getResNo() + i));
2585 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2586 DAG.getVTList(&ValueVTs[0], NumValues),
2587 &Values[0], NumValues));
2590 void SelectionDAGBuilder::visitTrunc(const User &I) {
2591 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2592 SDValue N = getValue(I.getOperand(0));
2593 EVT DestVT = TLI.getValueType(I.getType());
2594 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2597 void SelectionDAGBuilder::visitZExt(const User &I) {
2598 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2599 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2600 SDValue N = getValue(I.getOperand(0));
2601 EVT DestVT = TLI.getValueType(I.getType());
2602 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2605 void SelectionDAGBuilder::visitSExt(const User &I) {
2606 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2607 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2608 SDValue N = getValue(I.getOperand(0));
2609 EVT DestVT = TLI.getValueType(I.getType());
2610 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2613 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2614 // FPTrunc is never a no-op cast, no need to check
2615 SDValue N = getValue(I.getOperand(0));
2616 EVT DestVT = TLI.getValueType(I.getType());
2617 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2618 DestVT, N, DAG.getIntPtrConstant(0)));
2621 void SelectionDAGBuilder::visitFPExt(const User &I){
2622 // FPTrunc is never a no-op cast, no need to check
2623 SDValue N = getValue(I.getOperand(0));
2624 EVT DestVT = TLI.getValueType(I.getType());
2625 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2628 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2629 // FPToUI is never a no-op cast, no need to check
2630 SDValue N = getValue(I.getOperand(0));
2631 EVT DestVT = TLI.getValueType(I.getType());
2632 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2635 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2636 // FPToSI is never a no-op cast, no need to check
2637 SDValue N = getValue(I.getOperand(0));
2638 EVT DestVT = TLI.getValueType(I.getType());
2639 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2642 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2643 // UIToFP is never a no-op cast, no need to check
2644 SDValue N = getValue(I.getOperand(0));
2645 EVT DestVT = TLI.getValueType(I.getType());
2646 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2649 void SelectionDAGBuilder::visitSIToFP(const User &I){
2650 // SIToFP is never a no-op cast, no need to check
2651 SDValue N = getValue(I.getOperand(0));
2652 EVT DestVT = TLI.getValueType(I.getType());
2653 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2656 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2657 // What to do depends on the size of the integer and the size of the pointer.
2658 // We can either truncate, zero extend, or no-op, accordingly.
2659 SDValue N = getValue(I.getOperand(0));
2660 EVT DestVT = TLI.getValueType(I.getType());
2661 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2664 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2665 // What to do depends on the size of the integer and the size of the pointer.
2666 // We can either truncate, zero extend, or no-op, accordingly.
2667 SDValue N = getValue(I.getOperand(0));
2668 EVT DestVT = TLI.getValueType(I.getType());
2669 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2672 void SelectionDAGBuilder::visitBitCast(const User &I) {
2673 SDValue N = getValue(I.getOperand(0));
2674 EVT DestVT = TLI.getValueType(I.getType());
2676 // BitCast assures us that source and destination are the same size so this is
2677 // either a BITCAST or a no-op.
2678 if (DestVT != N.getValueType())
2679 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2680 DestVT, N)); // convert types.
2682 setValue(&I, N); // noop cast.
2685 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2686 SDValue InVec = getValue(I.getOperand(0));
2687 SDValue InVal = getValue(I.getOperand(1));
2688 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2690 getValue(I.getOperand(2)));
2691 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2692 TLI.getValueType(I.getType()),
2693 InVec, InVal, InIdx));
2696 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2697 SDValue InVec = getValue(I.getOperand(0));
2698 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2700 getValue(I.getOperand(1)));
2701 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2702 TLI.getValueType(I.getType()), InVec, InIdx));
2705 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2706 // from SIndx and increasing to the element length (undefs are allowed).
2707 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2708 unsigned MaskNumElts = Mask.size();
2709 for (unsigned i = 0; i != MaskNumElts; ++i)
2710 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2715 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2716 SmallVector<int, 8> Mask;
2717 SDValue Src1 = getValue(I.getOperand(0));
2718 SDValue Src2 = getValue(I.getOperand(1));
2720 // Convert the ConstantVector mask operand into an array of ints, with -1
2721 // representing undef values.
2722 SmallVector<Constant*, 8> MaskElts;
2723 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2724 unsigned MaskNumElts = MaskElts.size();
2725 for (unsigned i = 0; i != MaskNumElts; ++i) {
2726 if (isa<UndefValue>(MaskElts[i]))
2729 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2732 EVT VT = TLI.getValueType(I.getType());
2733 EVT SrcVT = Src1.getValueType();
2734 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2736 if (SrcNumElts == MaskNumElts) {
2737 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2742 // Normalize the shuffle vector since mask and vector length don't match.
2743 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2744 // Mask is longer than the source vectors and is a multiple of the source
2745 // vectors. We can use concatenate vector to make the mask and vectors
2747 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2748 // The shuffle is concatenating two vectors together.
2749 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2754 // Pad both vectors with undefs to make them the same length as the mask.
2755 unsigned NumConcat = MaskNumElts / SrcNumElts;
2756 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2757 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2758 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2760 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2761 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2765 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2766 getCurDebugLoc(), VT,
2767 &MOps1[0], NumConcat);
2768 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2769 getCurDebugLoc(), VT,
2770 &MOps2[0], NumConcat);
2772 // Readjust mask for new input vector length.
2773 SmallVector<int, 8> MappedOps;
2774 for (unsigned i = 0; i != MaskNumElts; ++i) {
2776 if (Idx < (int)SrcNumElts)
2777 MappedOps.push_back(Idx);
2779 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2782 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2787 if (SrcNumElts > MaskNumElts) {
2788 // Analyze the access pattern of the vector to see if we can extract
2789 // two subvectors and do the shuffle. The analysis is done by calculating
2790 // the range of elements the mask access on both vectors.
2791 int MinRange[2] = { static_cast<int>(SrcNumElts+1),
2792 static_cast<int>(SrcNumElts+1)};
2793 int MaxRange[2] = {-1, -1};
2795 for (unsigned i = 0; i != MaskNumElts; ++i) {
2801 if (Idx >= (int)SrcNumElts) {
2805 if (Idx > MaxRange[Input])
2806 MaxRange[Input] = Idx;
2807 if (Idx < MinRange[Input])
2808 MinRange[Input] = Idx;
2811 // Check if the access is smaller than the vector size and can we find
2812 // a reasonable extract index.
2813 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2815 int StartIdx[2]; // StartIdx to extract from
2816 for (int Input=0; Input < 2; ++Input) {
2817 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2818 RangeUse[Input] = 0; // Unused
2819 StartIdx[Input] = 0;
2820 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2821 // Fits within range but we should see if we can find a good
2822 // start index that is a multiple of the mask length.
2823 if (MaxRange[Input] < (int)MaskNumElts) {
2824 RangeUse[Input] = 1; // Extract from beginning of the vector
2825 StartIdx[Input] = 0;
2827 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2828 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2829 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2830 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2835 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2836 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2839 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2840 // Extract appropriate subvector and generate a vector shuffle
2841 for (int Input=0; Input < 2; ++Input) {
2842 SDValue &Src = Input == 0 ? Src1 : Src2;
2843 if (RangeUse[Input] == 0)
2844 Src = DAG.getUNDEF(VT);
2846 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2847 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2850 // Calculate new mask.
2851 SmallVector<int, 8> MappedOps;
2852 for (unsigned i = 0; i != MaskNumElts; ++i) {
2855 MappedOps.push_back(Idx);
2856 else if (Idx < (int)SrcNumElts)
2857 MappedOps.push_back(Idx - StartIdx[0]);
2859 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2862 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2868 // We can't use either concat vectors or extract subvectors so fall back to
2869 // replacing the shuffle with extract and build vector.
2870 // to insert and build vector.
2871 EVT EltVT = VT.getVectorElementType();
2872 EVT PtrVT = TLI.getPointerTy();
2873 SmallVector<SDValue,8> Ops;
2874 for (unsigned i = 0; i != MaskNumElts; ++i) {
2876 Ops.push_back(DAG.getUNDEF(EltVT));
2881 if (Idx < (int)SrcNumElts)
2882 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2883 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2885 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2887 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2893 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2894 VT, &Ops[0], Ops.size()));
2897 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2898 const Value *Op0 = I.getOperand(0);
2899 const Value *Op1 = I.getOperand(1);
2900 Type *AggTy = I.getType();
2901 Type *ValTy = Op1->getType();
2902 bool IntoUndef = isa<UndefValue>(Op0);
2903 bool FromUndef = isa<UndefValue>(Op1);
2905 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2907 SmallVector<EVT, 4> AggValueVTs;
2908 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2909 SmallVector<EVT, 4> ValValueVTs;
2910 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2912 unsigned NumAggValues = AggValueVTs.size();
2913 unsigned NumValValues = ValValueVTs.size();
2914 SmallVector<SDValue, 4> Values(NumAggValues);
2916 SDValue Agg = getValue(Op0);
2918 // Copy the beginning value(s) from the original aggregate.
2919 for (; i != LinearIndex; ++i)
2920 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2921 SDValue(Agg.getNode(), Agg.getResNo() + i);
2922 // Copy values from the inserted value(s).
2924 SDValue Val = getValue(Op1);
2925 for (; i != LinearIndex + NumValValues; ++i)
2926 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2927 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2929 // Copy remaining value(s) from the original aggregate.
2930 for (; i != NumAggValues; ++i)
2931 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2932 SDValue(Agg.getNode(), Agg.getResNo() + i);
2934 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2935 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2936 &Values[0], NumAggValues));
2939 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2940 const Value *Op0 = I.getOperand(0);
2941 Type *AggTy = Op0->getType();
2942 Type *ValTy = I.getType();
2943 bool OutOfUndef = isa<UndefValue>(Op0);
2945 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2947 SmallVector<EVT, 4> ValValueVTs;
2948 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2950 unsigned NumValValues = ValValueVTs.size();
2952 // Ignore a extractvalue that produces an empty object
2953 if (!NumValValues) {
2954 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2958 SmallVector<SDValue, 4> Values(NumValValues);
2960 SDValue Agg = getValue(Op0);
2961 // Copy out the selected value(s).
2962 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2963 Values[i - LinearIndex] =
2965 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2966 SDValue(Agg.getNode(), Agg.getResNo() + i);
2968 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2969 DAG.getVTList(&ValValueVTs[0], NumValValues),
2970 &Values[0], NumValValues));
2973 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2974 SDValue N = getValue(I.getOperand(0));
2975 Type *Ty = I.getOperand(0)->getType();
2977 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2979 const Value *Idx = *OI;
2980 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2981 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2984 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2985 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2986 DAG.getIntPtrConstant(Offset));
2989 Ty = StTy->getElementType(Field);
2991 Ty = cast<SequentialType>(Ty)->getElementType();
2993 // If this is a constant subscript, handle it quickly.
2994 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2995 if (CI->isZero()) continue;
2997 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2999 EVT PTy = TLI.getPointerTy();
3000 unsigned PtrBits = PTy.getSizeInBits();
3002 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3004 DAG.getConstant(Offs, MVT::i64));
3006 OffsVal = DAG.getIntPtrConstant(Offs);
3008 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3013 // N = N + Idx * ElementSize;
3014 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3015 TD->getTypeAllocSize(Ty));
3016 SDValue IdxN = getValue(Idx);
3018 // If the index is smaller or larger than intptr_t, truncate or extend
3020 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3022 // If this is a multiply by a power of two, turn it into a shl
3023 // immediately. This is a very common case.
3024 if (ElementSize != 1) {
3025 if (ElementSize.isPowerOf2()) {
3026 unsigned Amt = ElementSize.logBase2();
3027 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3028 N.getValueType(), IdxN,
3029 DAG.getConstant(Amt, TLI.getPointerTy()));
3031 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3032 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3033 N.getValueType(), IdxN, Scale);
3037 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3038 N.getValueType(), N, IdxN);
3045 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3046 // If this is a fixed sized alloca in the entry block of the function,
3047 // allocate it statically on the stack.
3048 if (FuncInfo.StaticAllocaMap.count(&I))
3049 return; // getValue will auto-populate this.
3051 Type *Ty = I.getAllocatedType();
3052 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3054 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3057 SDValue AllocSize = getValue(I.getArraySize());
3059 EVT IntPtr = TLI.getPointerTy();
3060 if (AllocSize.getValueType() != IntPtr)
3061 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3063 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3065 DAG.getConstant(TySize, IntPtr));
3067 // Handle alignment. If the requested alignment is less than or equal to
3068 // the stack alignment, ignore it. If the size is greater than or equal to
3069 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3070 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3071 if (Align <= StackAlign)
3074 // Round the size of the allocation up to the stack alignment size
3075 // by add SA-1 to the size.
3076 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3077 AllocSize.getValueType(), AllocSize,
3078 DAG.getIntPtrConstant(StackAlign-1));
3080 // Mask out the low bits for alignment purposes.
3081 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3082 AllocSize.getValueType(), AllocSize,
3083 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3085 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3086 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3087 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3090 DAG.setRoot(DSA.getValue(1));
3092 // Inform the Frame Information that we have just allocated a variable-sized
3094 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3097 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3098 const Value *SV = I.getOperand(0);
3099 SDValue Ptr = getValue(SV);
3101 Type *Ty = I.getType();
3103 bool isVolatile = I.isVolatile();
3104 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3105 unsigned Alignment = I.getAlignment();
3106 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3108 SmallVector<EVT, 4> ValueVTs;
3109 SmallVector<uint64_t, 4> Offsets;
3110 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3111 unsigned NumValues = ValueVTs.size();
3116 bool ConstantMemory = false;
3117 if (I.isVolatile() || NumValues > MaxParallelChains)
3118 // Serialize volatile loads with other side effects.
3120 else if (AA->pointsToConstantMemory(
3121 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3122 // Do not serialize (non-volatile) loads of constant memory with anything.
3123 Root = DAG.getEntryNode();
3124 ConstantMemory = true;
3126 // Do not serialize non-volatile loads against each other.
3127 Root = DAG.getRoot();
3130 SmallVector<SDValue, 4> Values(NumValues);
3131 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3133 EVT PtrVT = Ptr.getValueType();
3134 unsigned ChainI = 0;
3135 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3136 // Serializing loads here may result in excessive register pressure, and
3137 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3138 // could recover a bit by hoisting nodes upward in the chain by recognizing
3139 // they are side-effect free or do not alias. The optimizer should really
3140 // avoid this case by converting large object/array copies to llvm.memcpy
3141 // (MaxParallelChains should always remain as failsafe).
3142 if (ChainI == MaxParallelChains) {
3143 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3144 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3145 MVT::Other, &Chains[0], ChainI);
3149 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3151 DAG.getConstant(Offsets[i], PtrVT));
3152 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3153 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3154 isNonTemporal, Alignment, TBAAInfo);
3157 Chains[ChainI] = L.getValue(1);
3160 if (!ConstantMemory) {
3161 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3162 MVT::Other, &Chains[0], ChainI);
3166 PendingLoads.push_back(Chain);
3169 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3170 DAG.getVTList(&ValueVTs[0], NumValues),
3171 &Values[0], NumValues));
3174 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3175 const Value *SrcV = I.getOperand(0);
3176 const Value *PtrV = I.getOperand(1);
3178 SmallVector<EVT, 4> ValueVTs;
3179 SmallVector<uint64_t, 4> Offsets;
3180 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3181 unsigned NumValues = ValueVTs.size();
3185 // Get the lowered operands. Note that we do this after
3186 // checking if NumResults is zero, because with zero results
3187 // the operands won't have values in the map.
3188 SDValue Src = getValue(SrcV);
3189 SDValue Ptr = getValue(PtrV);
3191 SDValue Root = getRoot();
3192 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3194 EVT PtrVT = Ptr.getValueType();
3195 bool isVolatile = I.isVolatile();
3196 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3197 unsigned Alignment = I.getAlignment();
3198 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3200 unsigned ChainI = 0;
3201 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3202 // See visitLoad comments.
3203 if (ChainI == MaxParallelChains) {
3204 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3205 MVT::Other, &Chains[0], ChainI);
3209 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3210 DAG.getConstant(Offsets[i], PtrVT));
3211 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3212 SDValue(Src.getNode(), Src.getResNo() + i),
3213 Add, MachinePointerInfo(PtrV, Offsets[i]),
3214 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3215 Chains[ChainI] = St;
3218 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3219 MVT::Other, &Chains[0], ChainI);
3221 AssignOrderingToNode(StoreNode.getNode());
3222 DAG.setRoot(StoreNode);
3225 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3228 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3231 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3232 DebugLoc dl = getCurDebugLoc();
3235 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3236 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3237 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3240 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3242 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3243 unsigned Intrinsic) {
3244 bool HasChain = !I.doesNotAccessMemory();
3245 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3247 // Build the operand list.
3248 SmallVector<SDValue, 8> Ops;
3249 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3251 // We don't need to serialize loads against other loads.
3252 Ops.push_back(DAG.getRoot());
3254 Ops.push_back(getRoot());
3258 // Info is set by getTgtMemInstrinsic
3259 TargetLowering::IntrinsicInfo Info;
3260 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3262 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3263 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3264 Info.opc == ISD::INTRINSIC_W_CHAIN)
3265 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3267 // Add all operands of the call to the operand list.
3268 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3269 SDValue Op = getValue(I.getArgOperand(i));
3270 assert(TLI.isTypeLegal(Op.getValueType()) &&
3271 "Intrinsic uses a non-legal type?");
3275 SmallVector<EVT, 4> ValueVTs;
3276 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3278 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3279 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3280 "Intrinsic uses a non-legal type?");
3285 ValueVTs.push_back(MVT::Other);
3287 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3291 if (IsTgtIntrinsic) {
3292 // This is target intrinsic that touches memory
3293 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3294 VTs, &Ops[0], Ops.size(),
3296 MachinePointerInfo(Info.ptrVal, Info.offset),
3297 Info.align, Info.vol,
3298 Info.readMem, Info.writeMem);
3299 } else if (!HasChain) {
3300 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3301 VTs, &Ops[0], Ops.size());
3302 } else if (!I.getType()->isVoidTy()) {
3303 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3304 VTs, &Ops[0], Ops.size());
3306 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3307 VTs, &Ops[0], Ops.size());
3311 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3313 PendingLoads.push_back(Chain);
3318 if (!I.getType()->isVoidTy()) {
3319 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3320 EVT VT = TLI.getValueType(PTy);
3321 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3324 setValue(&I, Result);
3328 /// GetSignificand - Get the significand and build it into a floating-point
3329 /// number with exponent of 1:
3331 /// Op = (Op & 0x007fffff) | 0x3f800000;
3333 /// where Op is the hexidecimal representation of floating point value.
3335 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3336 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3337 DAG.getConstant(0x007fffff, MVT::i32));
3338 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3339 DAG.getConstant(0x3f800000, MVT::i32));
3340 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3343 /// GetExponent - Get the exponent:
3345 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3347 /// where Op is the hexidecimal representation of floating point value.
3349 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3351 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3352 DAG.getConstant(0x7f800000, MVT::i32));
3353 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3354 DAG.getConstant(23, TLI.getPointerTy()));
3355 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3356 DAG.getConstant(127, MVT::i32));
3357 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3360 /// getF32Constant - Get 32-bit floating point constant.
3362 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3363 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3366 /// Inlined utility function to implement binary input atomic intrinsics for
3367 /// visitIntrinsicCall: I is a call instruction
3368 /// Op is the associated NodeType for I
3370 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3372 SDValue Root = getRoot();
3374 DAG.getAtomic(Op, getCurDebugLoc(),
3375 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3377 getValue(I.getArgOperand(0)),
3378 getValue(I.getArgOperand(1)),
3379 I.getArgOperand(0));
3381 DAG.setRoot(L.getValue(1));
3385 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3387 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3388 SDValue Op1 = getValue(I.getArgOperand(0));
3389 SDValue Op2 = getValue(I.getArgOperand(1));
3391 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3392 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3396 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3397 /// limited-precision mode.
3399 SelectionDAGBuilder::visitExp(const CallInst &I) {
3401 DebugLoc dl = getCurDebugLoc();
3403 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3404 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3405 SDValue Op = getValue(I.getArgOperand(0));
3407 // Put the exponent in the right bit position for later addition to the
3410 // #define LOG2OFe 1.4426950f
3411 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3412 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3413 getF32Constant(DAG, 0x3fb8aa3b));
3414 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3416 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3417 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3418 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3420 // IntegerPartOfX <<= 23;
3421 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3422 DAG.getConstant(23, TLI.getPointerTy()));
3424 if (LimitFloatPrecision <= 6) {
3425 // For floating-point precision of 6:
3427 // TwoToFractionalPartOfX =
3429 // (0.735607626f + 0.252464424f * x) * x;
3431 // error 0.0144103317, which is 6 bits
3432 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3433 getF32Constant(DAG, 0x3e814304));
3434 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3435 getF32Constant(DAG, 0x3f3c50c8));
3436 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3437 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3438 getF32Constant(DAG, 0x3f7f5e7e));
3439 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3441 // Add the exponent into the result in integer domain.
3442 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3443 TwoToFracPartOfX, IntegerPartOfX);
3445 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3446 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3447 // For floating-point precision of 12:
3449 // TwoToFractionalPartOfX =
3452 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3454 // 0.000107046256 error, which is 13 to 14 bits
3455 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3456 getF32Constant(DAG, 0x3da235e3));
3457 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3458 getF32Constant(DAG, 0x3e65b8f3));
3459 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3460 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3461 getF32Constant(DAG, 0x3f324b07));
3462 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3463 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3464 getF32Constant(DAG, 0x3f7ff8fd));
3465 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3467 // Add the exponent into the result in integer domain.
3468 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3469 TwoToFracPartOfX, IntegerPartOfX);
3471 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3472 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3473 // For floating-point precision of 18:
3475 // TwoToFractionalPartOfX =
3479 // (0.554906021e-1f +
3480 // (0.961591928e-2f +
3481 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3483 // error 2.47208000*10^(-7), which is better than 18 bits
3484 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3485 getF32Constant(DAG, 0x3924b03e));
3486 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3487 getF32Constant(DAG, 0x3ab24b87));
3488 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3489 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3490 getF32Constant(DAG, 0x3c1d8c17));
3491 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3492 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3493 getF32Constant(DAG, 0x3d634a1d));
3494 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3495 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3496 getF32Constant(DAG, 0x3e75fe14));
3497 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3498 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3499 getF32Constant(DAG, 0x3f317234));
3500 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3501 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3502 getF32Constant(DAG, 0x3f800000));
3503 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3506 // Add the exponent into the result in integer domain.
3507 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3508 TwoToFracPartOfX, IntegerPartOfX);
3510 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3513 // No special expansion.
3514 result = DAG.getNode(ISD::FEXP, dl,
3515 getValue(I.getArgOperand(0)).getValueType(),
3516 getValue(I.getArgOperand(0)));
3519 setValue(&I, result);
3522 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3523 /// limited-precision mode.
3525 SelectionDAGBuilder::visitLog(const CallInst &I) {
3527 DebugLoc dl = getCurDebugLoc();
3529 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3530 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3531 SDValue Op = getValue(I.getArgOperand(0));
3532 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3534 // Scale the exponent by log(2) [0.69314718f].
3535 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3536 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3537 getF32Constant(DAG, 0x3f317218));
3539 // Get the significand and build it into a floating-point number with
3541 SDValue X = GetSignificand(DAG, Op1, dl);
3543 if (LimitFloatPrecision <= 6) {
3544 // For floating-point precision of 6:
3548 // (1.4034025f - 0.23903021f * x) * x;
3550 // error 0.0034276066, which is better than 8 bits
3551 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3552 getF32Constant(DAG, 0xbe74c456));
3553 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3554 getF32Constant(DAG, 0x3fb3a2b1));
3555 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3556 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3557 getF32Constant(DAG, 0x3f949a29));
3559 result = DAG.getNode(ISD::FADD, dl,
3560 MVT::f32, LogOfExponent, LogOfMantissa);
3561 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3562 // For floating-point precision of 12:
3568 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3570 // error 0.000061011436, which is 14 bits
3571 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3572 getF32Constant(DAG, 0xbd67b6d6));
3573 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3574 getF32Constant(DAG, 0x3ee4f4b8));
3575 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3576 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3577 getF32Constant(DAG, 0x3fbc278b));
3578 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3579 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3580 getF32Constant(DAG, 0x40348e95));
3581 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3582 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3583 getF32Constant(DAG, 0x3fdef31a));
3585 result = DAG.getNode(ISD::FADD, dl,
3586 MVT::f32, LogOfExponent, LogOfMantissa);
3587 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3588 // For floating-point precision of 18:
3596 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3598 // error 0.0000023660568, which is better than 18 bits
3599 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3600 getF32Constant(DAG, 0xbc91e5ac));
3601 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3602 getF32Constant(DAG, 0x3e4350aa));
3603 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3604 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3605 getF32Constant(DAG, 0x3f60d3e3));
3606 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3607 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3608 getF32Constant(DAG, 0x4011cdf0));
3609 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3610 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3611 getF32Constant(DAG, 0x406cfd1c));
3612 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3613 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3614 getF32Constant(DAG, 0x408797cb));
3615 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3616 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3617 getF32Constant(DAG, 0x4006dcab));
3619 result = DAG.getNode(ISD::FADD, dl,
3620 MVT::f32, LogOfExponent, LogOfMantissa);
3623 // No special expansion.
3624 result = DAG.getNode(ISD::FLOG, dl,
3625 getValue(I.getArgOperand(0)).getValueType(),
3626 getValue(I.getArgOperand(0)));
3629 setValue(&I, result);
3632 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3633 /// limited-precision mode.
3635 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3637 DebugLoc dl = getCurDebugLoc();
3639 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3640 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3641 SDValue Op = getValue(I.getArgOperand(0));
3642 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3644 // Get the exponent.
3645 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3647 // Get the significand and build it into a floating-point number with
3649 SDValue X = GetSignificand(DAG, Op1, dl);
3651 // Different possible minimax approximations of significand in
3652 // floating-point for various degrees of accuracy over [1,2].
3653 if (LimitFloatPrecision <= 6) {
3654 // For floating-point precision of 6:
3656 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3658 // error 0.0049451742, which is more than 7 bits
3659 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3660 getF32Constant(DAG, 0xbeb08fe0));
3661 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3662 getF32Constant(DAG, 0x40019463));
3663 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3664 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3665 getF32Constant(DAG, 0x3fd6633d));
3667 result = DAG.getNode(ISD::FADD, dl,
3668 MVT::f32, LogOfExponent, Log2ofMantissa);
3669 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3670 // For floating-point precision of 12:
3676 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3678 // error 0.0000876136000, which is better than 13 bits
3679 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3680 getF32Constant(DAG, 0xbda7262e));
3681 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3682 getF32Constant(DAG, 0x3f25280b));
3683 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3684 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3685 getF32Constant(DAG, 0x4007b923));
3686 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3687 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3688 getF32Constant(DAG, 0x40823e2f));
3689 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3690 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3691 getF32Constant(DAG, 0x4020d29c));
3693 result = DAG.getNode(ISD::FADD, dl,
3694 MVT::f32, LogOfExponent, Log2ofMantissa);
3695 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3696 // For floating-point precision of 18:
3705 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3707 // error 0.0000018516, which is better than 18 bits
3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3709 getF32Constant(DAG, 0xbcd2769e));
3710 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3711 getF32Constant(DAG, 0x3e8ce0b9));
3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3713 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3714 getF32Constant(DAG, 0x3fa22ae7));
3715 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3716 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3717 getF32Constant(DAG, 0x40525723));
3718 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3719 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3720 getF32Constant(DAG, 0x40aaf200));
3721 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3722 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3723 getF32Constant(DAG, 0x40c39dad));
3724 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3725 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3726 getF32Constant(DAG, 0x4042902c));
3728 result = DAG.getNode(ISD::FADD, dl,
3729 MVT::f32, LogOfExponent, Log2ofMantissa);
3732 // No special expansion.
3733 result = DAG.getNode(ISD::FLOG2, dl,
3734 getValue(I.getArgOperand(0)).getValueType(),
3735 getValue(I.getArgOperand(0)));
3738 setValue(&I, result);
3741 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3742 /// limited-precision mode.
3744 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3746 DebugLoc dl = getCurDebugLoc();
3748 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3749 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3750 SDValue Op = getValue(I.getArgOperand(0));
3751 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3753 // Scale the exponent by log10(2) [0.30102999f].
3754 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3755 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3756 getF32Constant(DAG, 0x3e9a209a));
3758 // Get the significand and build it into a floating-point number with
3760 SDValue X = GetSignificand(DAG, Op1, dl);
3762 if (LimitFloatPrecision <= 6) {
3763 // For floating-point precision of 6:
3765 // Log10ofMantissa =
3767 // (0.60948995f - 0.10380950f * x) * x;
3769 // error 0.0014886165, which is 6 bits
3770 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3771 getF32Constant(DAG, 0xbdd49a13));
3772 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3773 getF32Constant(DAG, 0x3f1c0789));
3774 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3775 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3776 getF32Constant(DAG, 0x3f011300));
3778 result = DAG.getNode(ISD::FADD, dl,
3779 MVT::f32, LogOfExponent, Log10ofMantissa);
3780 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3781 // For floating-point precision of 12:
3783 // Log10ofMantissa =
3786 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3788 // error 0.00019228036, which is better than 12 bits
3789 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3790 getF32Constant(DAG, 0x3d431f31));
3791 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3792 getF32Constant(DAG, 0x3ea21fb2));
3793 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3794 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3795 getF32Constant(DAG, 0x3f6ae232));
3796 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3797 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3798 getF32Constant(DAG, 0x3f25f7c3));
3800 result = DAG.getNode(ISD::FADD, dl,
3801 MVT::f32, LogOfExponent, Log10ofMantissa);
3802 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3803 // For floating-point precision of 18:
3805 // Log10ofMantissa =
3810 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3812 // error 0.0000037995730, which is better than 18 bits
3813 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3814 getF32Constant(DAG, 0x3c5d51ce));
3815 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3816 getF32Constant(DAG, 0x3e00685a));
3817 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3818 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3819 getF32Constant(DAG, 0x3efb6798));
3820 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3821 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3822 getF32Constant(DAG, 0x3f88d192));
3823 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3824 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3825 getF32Constant(DAG, 0x3fc4316c));
3826 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3827 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3828 getF32Constant(DAG, 0x3f57ce70));
3830 result = DAG.getNode(ISD::FADD, dl,
3831 MVT::f32, LogOfExponent, Log10ofMantissa);
3834 // No special expansion.
3835 result = DAG.getNode(ISD::FLOG10, dl,
3836 getValue(I.getArgOperand(0)).getValueType(),
3837 getValue(I.getArgOperand(0)));
3840 setValue(&I, result);
3843 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3844 /// limited-precision mode.
3846 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3848 DebugLoc dl = getCurDebugLoc();
3850 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3851 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3852 SDValue Op = getValue(I.getArgOperand(0));
3854 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3856 // FractionalPartOfX = x - (float)IntegerPartOfX;
3857 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3858 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3860 // IntegerPartOfX <<= 23;
3861 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3862 DAG.getConstant(23, TLI.getPointerTy()));
3864 if (LimitFloatPrecision <= 6) {
3865 // For floating-point precision of 6:
3867 // TwoToFractionalPartOfX =
3869 // (0.735607626f + 0.252464424f * x) * x;
3871 // error 0.0144103317, which is 6 bits
3872 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3873 getF32Constant(DAG, 0x3e814304));
3874 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3875 getF32Constant(DAG, 0x3f3c50c8));
3876 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3877 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3878 getF32Constant(DAG, 0x3f7f5e7e));
3879 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3880 SDValue TwoToFractionalPartOfX =
3881 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3883 result = DAG.getNode(ISD::BITCAST, dl,
3884 MVT::f32, TwoToFractionalPartOfX);
3885 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3886 // For floating-point precision of 12:
3888 // TwoToFractionalPartOfX =
3891 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3893 // error 0.000107046256, which is 13 to 14 bits
3894 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3895 getF32Constant(DAG, 0x3da235e3));
3896 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3897 getF32Constant(DAG, 0x3e65b8f3));
3898 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3899 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3900 getF32Constant(DAG, 0x3f324b07));
3901 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3902 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3903 getF32Constant(DAG, 0x3f7ff8fd));
3904 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3905 SDValue TwoToFractionalPartOfX =
3906 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3908 result = DAG.getNode(ISD::BITCAST, dl,
3909 MVT::f32, TwoToFractionalPartOfX);
3910 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3911 // For floating-point precision of 18:
3913 // TwoToFractionalPartOfX =
3917 // (0.554906021e-1f +
3918 // (0.961591928e-2f +
3919 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3920 // error 2.47208000*10^(-7), which is better than 18 bits
3921 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3922 getF32Constant(DAG, 0x3924b03e));
3923 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3924 getF32Constant(DAG, 0x3ab24b87));
3925 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3926 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3927 getF32Constant(DAG, 0x3c1d8c17));
3928 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3929 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3930 getF32Constant(DAG, 0x3d634a1d));
3931 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3932 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3933 getF32Constant(DAG, 0x3e75fe14));
3934 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3935 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3936 getF32Constant(DAG, 0x3f317234));
3937 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3938 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3939 getF32Constant(DAG, 0x3f800000));
3940 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3941 SDValue TwoToFractionalPartOfX =
3942 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3944 result = DAG.getNode(ISD::BITCAST, dl,
3945 MVT::f32, TwoToFractionalPartOfX);
3948 // No special expansion.
3949 result = DAG.getNode(ISD::FEXP2, dl,
3950 getValue(I.getArgOperand(0)).getValueType(),
3951 getValue(I.getArgOperand(0)));
3954 setValue(&I, result);
3957 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3958 /// limited-precision mode with x == 10.0f.
3960 SelectionDAGBuilder::visitPow(const CallInst &I) {
3962 const Value *Val = I.getArgOperand(0);
3963 DebugLoc dl = getCurDebugLoc();
3964 bool IsExp10 = false;
3966 if (getValue(Val).getValueType() == MVT::f32 &&
3967 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3968 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3969 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3970 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3972 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3977 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3978 SDValue Op = getValue(I.getArgOperand(1));
3980 // Put the exponent in the right bit position for later addition to the
3983 // #define LOG2OF10 3.3219281f
3984 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3985 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3986 getF32Constant(DAG, 0x40549a78));
3987 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3989 // FractionalPartOfX = x - (float)IntegerPartOfX;
3990 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3991 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3993 // IntegerPartOfX <<= 23;
3994 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3995 DAG.getConstant(23, TLI.getPointerTy()));
3997 if (LimitFloatPrecision <= 6) {
3998 // For floating-point precision of 6:
4000 // twoToFractionalPartOfX =
4002 // (0.735607626f + 0.252464424f * x) * x;
4004 // error 0.0144103317, which is 6 bits
4005 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4006 getF32Constant(DAG, 0x3e814304));
4007 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4008 getF32Constant(DAG, 0x3f3c50c8));
4009 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4010 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4011 getF32Constant(DAG, 0x3f7f5e7e));
4012 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4013 SDValue TwoToFractionalPartOfX =
4014 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4016 result = DAG.getNode(ISD::BITCAST, dl,
4017 MVT::f32, TwoToFractionalPartOfX);
4018 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4019 // For floating-point precision of 12:
4021 // TwoToFractionalPartOfX =
4024 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4026 // error 0.000107046256, which is 13 to 14 bits
4027 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4028 getF32Constant(DAG, 0x3da235e3));
4029 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4030 getF32Constant(DAG, 0x3e65b8f3));
4031 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4032 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4033 getF32Constant(DAG, 0x3f324b07));
4034 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4035 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4036 getF32Constant(DAG, 0x3f7ff8fd));
4037 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4038 SDValue TwoToFractionalPartOfX =
4039 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4041 result = DAG.getNode(ISD::BITCAST, dl,
4042 MVT::f32, TwoToFractionalPartOfX);
4043 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4044 // For floating-point precision of 18:
4046 // TwoToFractionalPartOfX =
4050 // (0.554906021e-1f +
4051 // (0.961591928e-2f +
4052 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4053 // error 2.47208000*10^(-7), which is better than 18 bits
4054 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4055 getF32Constant(DAG, 0x3924b03e));
4056 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4057 getF32Constant(DAG, 0x3ab24b87));
4058 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4059 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4060 getF32Constant(DAG, 0x3c1d8c17));
4061 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4062 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4063 getF32Constant(DAG, 0x3d634a1d));
4064 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4065 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4066 getF32Constant(DAG, 0x3e75fe14));
4067 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4068 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4069 getF32Constant(DAG, 0x3f317234));
4070 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4071 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4072 getF32Constant(DAG, 0x3f800000));
4073 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4074 SDValue TwoToFractionalPartOfX =
4075 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4077 result = DAG.getNode(ISD::BITCAST, dl,
4078 MVT::f32, TwoToFractionalPartOfX);
4081 // No special expansion.
4082 result = DAG.getNode(ISD::FPOW, dl,
4083 getValue(I.getArgOperand(0)).getValueType(),
4084 getValue(I.getArgOperand(0)),
4085 getValue(I.getArgOperand(1)));
4088 setValue(&I, result);
4092 /// ExpandPowI - Expand a llvm.powi intrinsic.
4093 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4094 SelectionDAG &DAG) {
4095 // If RHS is a constant, we can expand this out to a multiplication tree,
4096 // otherwise we end up lowering to a call to __powidf2 (for example). When
4097 // optimizing for size, we only want to do this if the expansion would produce
4098 // a small number of multiplies, otherwise we do the full expansion.
4099 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4100 // Get the exponent as a positive value.
4101 unsigned Val = RHSC->getSExtValue();
4102 if ((int)Val < 0) Val = -Val;
4104 // powi(x, 0) -> 1.0
4106 return DAG.getConstantFP(1.0, LHS.getValueType());
4108 const Function *F = DAG.getMachineFunction().getFunction();
4109 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4110 // If optimizing for size, don't insert too many multiplies. This
4111 // inserts up to 5 multiplies.
4112 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4113 // We use the simple binary decomposition method to generate the multiply
4114 // sequence. There are more optimal ways to do this (for example,
4115 // powi(x,15) generates one more multiply than it should), but this has
4116 // the benefit of being both really simple and much better than a libcall.
4117 SDValue Res; // Logically starts equal to 1.0
4118 SDValue CurSquare = LHS;
4122 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4124 Res = CurSquare; // 1.0*CurSquare.
4127 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4128 CurSquare, CurSquare);
4132 // If the original was negative, invert the result, producing 1/(x*x*x).
4133 if (RHSC->getSExtValue() < 0)
4134 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4135 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4140 // Otherwise, expand to a libcall.
4141 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4144 // getTruncatedArgReg - Find underlying register used for an truncated
4146 static unsigned getTruncatedArgReg(const SDValue &N) {
4147 if (N.getOpcode() != ISD::TRUNCATE)
4150 const SDValue &Ext = N.getOperand(0);
4151 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4152 const SDValue &CFR = Ext.getOperand(0);
4153 if (CFR.getOpcode() == ISD::CopyFromReg)
4154 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4156 if (CFR.getOpcode() == ISD::TRUNCATE)
4157 return getTruncatedArgReg(CFR);
4162 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4163 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4164 /// At the end of instruction selection, they will be inserted to the entry BB.
4166 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4169 const Argument *Arg = dyn_cast<Argument>(V);
4173 MachineFunction &MF = DAG.getMachineFunction();
4174 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4175 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4177 // Ignore inlined function arguments here.
4178 DIVariable DV(Variable);
4179 if (DV.isInlinedFnArgument(MF.getFunction()))
4183 if (Arg->hasByValAttr()) {
4184 // Byval arguments' frame index is recorded during argument lowering.
4185 // Use this info directly.
4186 Reg = TRI->getFrameRegister(MF);
4187 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4188 // If byval argument ofset is not recorded then ignore this.
4194 if (N.getOpcode() == ISD::CopyFromReg)
4195 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4197 Reg = getTruncatedArgReg(N);
4198 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4199 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4200 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4207 // Check if ValueMap has reg number.
4208 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4209 if (VMI != FuncInfo.ValueMap.end())
4213 if (!Reg && N.getNode()) {
4214 // Check if frame index is available.
4215 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4216 if (FrameIndexSDNode *FINode =
4217 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4218 Reg = TRI->getFrameRegister(MF);
4219 Offset = FINode->getIndex();
4226 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4227 TII->get(TargetOpcode::DBG_VALUE))
4228 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4229 FuncInfo.ArgDbgValues.push_back(&*MIB);
4233 // VisualStudio defines setjmp as _setjmp
4234 #if defined(_MSC_VER) && defined(setjmp) && \
4235 !defined(setjmp_undefined_for_msvc)
4236 # pragma push_macro("setjmp")
4238 # define setjmp_undefined_for_msvc
4241 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4242 /// we want to emit this as a call to a named external function, return the name
4243 /// otherwise lower it and return null.
4245 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4246 DebugLoc dl = getCurDebugLoc();
4249 switch (Intrinsic) {
4251 // By default, turn this into a target intrinsic node.
4252 visitTargetIntrinsic(I, Intrinsic);
4254 case Intrinsic::vastart: visitVAStart(I); return 0;
4255 case Intrinsic::vaend: visitVAEnd(I); return 0;
4256 case Intrinsic::vacopy: visitVACopy(I); return 0;
4257 case Intrinsic::returnaddress:
4258 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4259 getValue(I.getArgOperand(0))));
4261 case Intrinsic::frameaddress:
4262 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4263 getValue(I.getArgOperand(0))));
4265 case Intrinsic::setjmp:
4266 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4267 case Intrinsic::longjmp:
4268 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4269 case Intrinsic::memcpy: {
4270 // Assert for address < 256 since we support only user defined address
4272 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4274 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4276 "Unknown address space");
4277 SDValue Op1 = getValue(I.getArgOperand(0));
4278 SDValue Op2 = getValue(I.getArgOperand(1));
4279 SDValue Op3 = getValue(I.getArgOperand(2));
4280 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4281 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4282 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4283 MachinePointerInfo(I.getArgOperand(0)),
4284 MachinePointerInfo(I.getArgOperand(1))));
4287 case Intrinsic::memset: {
4288 // Assert for address < 256 since we support only user defined address
4290 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4292 "Unknown address space");
4293 SDValue Op1 = getValue(I.getArgOperand(0));
4294 SDValue Op2 = getValue(I.getArgOperand(1));
4295 SDValue Op3 = getValue(I.getArgOperand(2));
4296 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4297 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4298 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4299 MachinePointerInfo(I.getArgOperand(0))));
4302 case Intrinsic::memmove: {
4303 // Assert for address < 256 since we support only user defined address
4305 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4307 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4309 "Unknown address space");
4310 SDValue Op1 = getValue(I.getArgOperand(0));
4311 SDValue Op2 = getValue(I.getArgOperand(1));
4312 SDValue Op3 = getValue(I.getArgOperand(2));
4313 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4314 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4315 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4316 MachinePointerInfo(I.getArgOperand(0)),
4317 MachinePointerInfo(I.getArgOperand(1))));
4320 case Intrinsic::dbg_declare: {
4321 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4322 MDNode *Variable = DI.getVariable();
4323 const Value *Address = DI.getAddress();
4324 if (!Address || !DIVariable(DI.getVariable()).Verify())
4327 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4328 // but do not always have a corresponding SDNode built. The SDNodeOrder
4329 // absolute, but not relative, values are different depending on whether
4330 // debug info exists.
4333 // Check if address has undef value.
4334 if (isa<UndefValue>(Address) ||
4335 (Address->use_empty() && !isa<Argument>(Address))) {
4336 DEBUG(dbgs() << "Dropping debug info for " << DI);
4340 SDValue &N = NodeMap[Address];
4341 if (!N.getNode() && isa<Argument>(Address))
4342 // Check unused arguments map.
4343 N = UnusedArgNodeMap[Address];
4346 // Parameters are handled specially.
4348 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4349 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4350 Address = BCI->getOperand(0);
4351 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4353 if (isParameter && !AI) {
4354 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4356 // Byval parameter. We have a frame index at this point.
4357 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4358 0, dl, SDNodeOrder);
4360 // Address is an argument, so try to emit its dbg value using
4361 // virtual register info from the FuncInfo.ValueMap.
4362 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4366 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4367 0, dl, SDNodeOrder);
4369 // Can't do anything with other non-AI cases yet.
4370 DEBUG(dbgs() << "Dropping debug info for " << DI);
4373 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4375 // If Address is an argument then try to emit its dbg value using
4376 // virtual register info from the FuncInfo.ValueMap.
4377 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4378 // If variable is pinned by a alloca in dominating bb then
4379 // use StaticAllocaMap.
4380 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4381 if (AI->getParent() != DI.getParent()) {
4382 DenseMap<const AllocaInst*, int>::iterator SI =
4383 FuncInfo.StaticAllocaMap.find(AI);
4384 if (SI != FuncInfo.StaticAllocaMap.end()) {
4385 SDV = DAG.getDbgValue(Variable, SI->second,
4386 0, dl, SDNodeOrder);
4387 DAG.AddDbgValue(SDV, 0, false);
4392 DEBUG(dbgs() << "Dropping debug info for " << DI);
4397 case Intrinsic::dbg_value: {
4398 const DbgValueInst &DI = cast<DbgValueInst>(I);
4399 if (!DIVariable(DI.getVariable()).Verify())
4402 MDNode *Variable = DI.getVariable();
4403 uint64_t Offset = DI.getOffset();
4404 const Value *V = DI.getValue();
4408 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4409 // but do not always have a corresponding SDNode built. The SDNodeOrder
4410 // absolute, but not relative, values are different depending on whether
4411 // debug info exists.
4414 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4415 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4416 DAG.AddDbgValue(SDV, 0, false);
4418 // Do not use getValue() in here; we don't want to generate code at
4419 // this point if it hasn't been done yet.
4420 SDValue N = NodeMap[V];
4421 if (!N.getNode() && isa<Argument>(V))
4422 // Check unused arguments map.
4423 N = UnusedArgNodeMap[V];
4425 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4426 SDV = DAG.getDbgValue(Variable, N.getNode(),
4427 N.getResNo(), Offset, dl, SDNodeOrder);
4428 DAG.AddDbgValue(SDV, N.getNode(), false);
4430 } else if (!V->use_empty() ) {
4431 // Do not call getValue(V) yet, as we don't want to generate code.
4432 // Remember it for later.
4433 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4434 DanglingDebugInfoMap[V] = DDI;
4436 // We may expand this to cover more cases. One case where we have no
4437 // data available is an unreferenced parameter.
4438 DEBUG(dbgs() << "Dropping debug info for " << DI);
4442 // Build a debug info table entry.
4443 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4444 V = BCI->getOperand(0);
4445 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4446 // Don't handle byval struct arguments or VLAs, for example.
4449 DenseMap<const AllocaInst*, int>::iterator SI =
4450 FuncInfo.StaticAllocaMap.find(AI);
4451 if (SI == FuncInfo.StaticAllocaMap.end())
4453 int FI = SI->second;
4455 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4456 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4457 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4460 case Intrinsic::eh_exception: {
4461 // Insert the EXCEPTIONADDR instruction.
4462 assert(FuncInfo.MBB->isLandingPad() &&
4463 "Call to eh.exception not in landing pad!");
4464 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4466 Ops[0] = DAG.getRoot();
4467 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4469 DAG.setRoot(Op.getValue(1));
4473 case Intrinsic::eh_selector: {
4474 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4475 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4476 if (CallMBB->isLandingPad())
4477 AddCatchInfo(I, &MMI, CallMBB);
4480 FuncInfo.CatchInfoLost.insert(&I);
4482 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4483 unsigned Reg = TLI.getExceptionSelectorRegister();
4484 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4487 // Insert the EHSELECTION instruction.
4488 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4490 Ops[0] = getValue(I.getArgOperand(0));
4492 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4493 DAG.setRoot(Op.getValue(1));
4494 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4498 case Intrinsic::eh_typeid_for: {
4499 // Find the type id for the given typeinfo.
4500 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4501 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4502 Res = DAG.getConstant(TypeID, MVT::i32);
4507 case Intrinsic::eh_return_i32:
4508 case Intrinsic::eh_return_i64:
4509 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4510 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4513 getValue(I.getArgOperand(0)),
4514 getValue(I.getArgOperand(1))));
4516 case Intrinsic::eh_unwind_init:
4517 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4519 case Intrinsic::eh_dwarf_cfa: {
4520 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4521 TLI.getPointerTy());
4522 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4524 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4525 TLI.getPointerTy()),
4527 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4529 DAG.getConstant(0, TLI.getPointerTy()));
4530 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4534 case Intrinsic::eh_sjlj_callsite: {
4535 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4536 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4537 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4538 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4540 MMI.setCurrentCallSite(CI->getZExtValue());
4543 case Intrinsic::eh_sjlj_setjmp: {
4544 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4545 getValue(I.getArgOperand(0))));
4548 case Intrinsic::eh_sjlj_longjmp: {
4549 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4550 getRoot(), getValue(I.getArgOperand(0))));
4553 case Intrinsic::eh_sjlj_dispatch_setup: {
4554 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4555 getRoot(), getValue(I.getArgOperand(0))));
4559 case Intrinsic::x86_mmx_pslli_w:
4560 case Intrinsic::x86_mmx_pslli_d:
4561 case Intrinsic::x86_mmx_pslli_q:
4562 case Intrinsic::x86_mmx_psrli_w:
4563 case Intrinsic::x86_mmx_psrli_d:
4564 case Intrinsic::x86_mmx_psrli_q:
4565 case Intrinsic::x86_mmx_psrai_w:
4566 case Intrinsic::x86_mmx_psrai_d: {
4567 SDValue ShAmt = getValue(I.getArgOperand(1));
4568 if (isa<ConstantSDNode>(ShAmt)) {
4569 visitTargetIntrinsic(I, Intrinsic);
4572 unsigned NewIntrinsic = 0;
4573 EVT ShAmtVT = MVT::v2i32;
4574 switch (Intrinsic) {
4575 case Intrinsic::x86_mmx_pslli_w:
4576 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4578 case Intrinsic::x86_mmx_pslli_d:
4579 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4581 case Intrinsic::x86_mmx_pslli_q:
4582 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4584 case Intrinsic::x86_mmx_psrli_w:
4585 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4587 case Intrinsic::x86_mmx_psrli_d:
4588 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4590 case Intrinsic::x86_mmx_psrli_q:
4591 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4593 case Intrinsic::x86_mmx_psrai_w:
4594 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4596 case Intrinsic::x86_mmx_psrai_d:
4597 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4599 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4602 // The vector shift intrinsics with scalars uses 32b shift amounts but
4603 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4605 // We must do this early because v2i32 is not a legal type.
4606 DebugLoc dl = getCurDebugLoc();
4609 ShOps[1] = DAG.getConstant(0, MVT::i32);
4610 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4611 EVT DestVT = TLI.getValueType(I.getType());
4612 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4613 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4614 DAG.getConstant(NewIntrinsic, MVT::i32),
4615 getValue(I.getArgOperand(0)), ShAmt);
4619 case Intrinsic::convertff:
4620 case Intrinsic::convertfsi:
4621 case Intrinsic::convertfui:
4622 case Intrinsic::convertsif:
4623 case Intrinsic::convertuif:
4624 case Intrinsic::convertss:
4625 case Intrinsic::convertsu:
4626 case Intrinsic::convertus:
4627 case Intrinsic::convertuu: {
4628 ISD::CvtCode Code = ISD::CVT_INVALID;
4629 switch (Intrinsic) {
4630 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4631 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4632 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4633 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4634 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4635 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4636 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4637 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4638 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4640 EVT DestVT = TLI.getValueType(I.getType());
4641 const Value *Op1 = I.getArgOperand(0);
4642 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4643 DAG.getValueType(DestVT),
4644 DAG.getValueType(getValue(Op1).getValueType()),
4645 getValue(I.getArgOperand(1)),
4646 getValue(I.getArgOperand(2)),
4651 case Intrinsic::sqrt:
4652 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4653 getValue(I.getArgOperand(0)).getValueType(),
4654 getValue(I.getArgOperand(0))));
4656 case Intrinsic::powi:
4657 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4658 getValue(I.getArgOperand(1)), DAG));
4660 case Intrinsic::sin:
4661 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4662 getValue(I.getArgOperand(0)).getValueType(),
4663 getValue(I.getArgOperand(0))));
4665 case Intrinsic::cos:
4666 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4667 getValue(I.getArgOperand(0)).getValueType(),
4668 getValue(I.getArgOperand(0))));
4670 case Intrinsic::log:
4673 case Intrinsic::log2:
4676 case Intrinsic::log10:
4679 case Intrinsic::exp:
4682 case Intrinsic::exp2:
4685 case Intrinsic::pow:
4688 case Intrinsic::fma:
4689 setValue(&I, DAG.getNode(ISD::FMA, dl,
4690 getValue(I.getArgOperand(0)).getValueType(),
4691 getValue(I.getArgOperand(0)),
4692 getValue(I.getArgOperand(1)),
4693 getValue(I.getArgOperand(2))));
4695 case Intrinsic::convert_to_fp16:
4696 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4697 MVT::i16, getValue(I.getArgOperand(0))));
4699 case Intrinsic::convert_from_fp16:
4700 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4701 MVT::f32, getValue(I.getArgOperand(0))));
4703 case Intrinsic::pcmarker: {
4704 SDValue Tmp = getValue(I.getArgOperand(0));
4705 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4708 case Intrinsic::readcyclecounter: {
4709 SDValue Op = getRoot();
4710 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4711 DAG.getVTList(MVT::i64, MVT::Other),
4714 DAG.setRoot(Res.getValue(1));
4717 case Intrinsic::bswap:
4718 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4719 getValue(I.getArgOperand(0)).getValueType(),
4720 getValue(I.getArgOperand(0))));
4722 case Intrinsic::cttz: {
4723 SDValue Arg = getValue(I.getArgOperand(0));
4724 EVT Ty = Arg.getValueType();
4725 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4728 case Intrinsic::ctlz: {
4729 SDValue Arg = getValue(I.getArgOperand(0));
4730 EVT Ty = Arg.getValueType();
4731 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4734 case Intrinsic::ctpop: {
4735 SDValue Arg = getValue(I.getArgOperand(0));
4736 EVT Ty = Arg.getValueType();
4737 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4740 case Intrinsic::stacksave: {
4741 SDValue Op = getRoot();
4742 Res = DAG.getNode(ISD::STACKSAVE, dl,
4743 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4745 DAG.setRoot(Res.getValue(1));
4748 case Intrinsic::stackrestore: {
4749 Res = getValue(I.getArgOperand(0));
4750 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4753 case Intrinsic::stackprotector: {
4754 // Emit code into the DAG to store the stack guard onto the stack.
4755 MachineFunction &MF = DAG.getMachineFunction();
4756 MachineFrameInfo *MFI = MF.getFrameInfo();
4757 EVT PtrTy = TLI.getPointerTy();
4759 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4760 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4762 int FI = FuncInfo.StaticAllocaMap[Slot];
4763 MFI->setStackProtectorIndex(FI);
4765 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4767 // Store the stack protector onto the stack.
4768 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4769 MachinePointerInfo::getFixedStack(FI),
4775 case Intrinsic::objectsize: {
4776 // If we don't know by now, we're never going to know.
4777 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4779 assert(CI && "Non-constant type in __builtin_object_size?");
4781 SDValue Arg = getValue(I.getCalledValue());
4782 EVT Ty = Arg.getValueType();
4785 Res = DAG.getConstant(-1ULL, Ty);
4787 Res = DAG.getConstant(0, Ty);
4792 case Intrinsic::var_annotation:
4793 // Discard annotate attributes
4796 case Intrinsic::init_trampoline: {
4797 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4801 Ops[1] = getValue(I.getArgOperand(0));
4802 Ops[2] = getValue(I.getArgOperand(1));
4803 Ops[3] = getValue(I.getArgOperand(2));
4804 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4805 Ops[5] = DAG.getSrcValue(F);
4807 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4808 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4812 DAG.setRoot(Res.getValue(1));
4815 case Intrinsic::gcroot:
4817 const Value *Alloca = I.getArgOperand(0);
4818 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4820 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4821 GFI->addStackRoot(FI->getIndex(), TypeMap);
4824 case Intrinsic::gcread:
4825 case Intrinsic::gcwrite:
4826 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4828 case Intrinsic::flt_rounds:
4829 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4832 case Intrinsic::expect: {
4833 // Just replace __builtin_expect(exp, c) with EXP.
4834 setValue(&I, getValue(I.getArgOperand(0)));
4838 case Intrinsic::trap: {
4839 StringRef TrapFuncName = getTrapFunctionName();
4840 if (TrapFuncName.empty()) {
4841 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4844 TargetLowering::ArgListTy Args;
4845 std::pair<SDValue, SDValue> Result =
4846 TLI.LowerCallTo(getRoot(), I.getType(),
4847 false, false, false, false, 0, CallingConv::C,
4848 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
4849 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4850 Args, DAG, getCurDebugLoc());
4851 DAG.setRoot(Result.second);
4854 case Intrinsic::uadd_with_overflow:
4855 return implVisitAluOverflow(I, ISD::UADDO);
4856 case Intrinsic::sadd_with_overflow:
4857 return implVisitAluOverflow(I, ISD::SADDO);
4858 case Intrinsic::usub_with_overflow:
4859 return implVisitAluOverflow(I, ISD::USUBO);
4860 case Intrinsic::ssub_with_overflow:
4861 return implVisitAluOverflow(I, ISD::SSUBO);
4862 case Intrinsic::umul_with_overflow:
4863 return implVisitAluOverflow(I, ISD::UMULO);
4864 case Intrinsic::smul_with_overflow:
4865 return implVisitAluOverflow(I, ISD::SMULO);
4867 case Intrinsic::prefetch: {
4869 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4871 Ops[1] = getValue(I.getArgOperand(0));
4872 Ops[2] = getValue(I.getArgOperand(1));
4873 Ops[3] = getValue(I.getArgOperand(2));
4874 Ops[4] = getValue(I.getArgOperand(3));
4875 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4876 DAG.getVTList(MVT::Other),
4878 EVT::getIntegerVT(*Context, 8),
4879 MachinePointerInfo(I.getArgOperand(0)),
4881 false, /* volatile */
4883 rw==1)); /* write */
4886 case Intrinsic::memory_barrier: {
4889 for (int x = 1; x < 6; ++x)
4890 Ops[x] = getValue(I.getArgOperand(x - 1));
4892 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4895 case Intrinsic::atomic_cmp_swap: {
4896 SDValue Root = getRoot();
4898 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4899 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4901 getValue(I.getArgOperand(0)),
4902 getValue(I.getArgOperand(1)),
4903 getValue(I.getArgOperand(2)),
4904 MachinePointerInfo(I.getArgOperand(0)));
4906 DAG.setRoot(L.getValue(1));
4909 case Intrinsic::atomic_load_add:
4910 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4911 case Intrinsic::atomic_load_sub:
4912 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4913 case Intrinsic::atomic_load_or:
4914 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4915 case Intrinsic::atomic_load_xor:
4916 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4917 case Intrinsic::atomic_load_and:
4918 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4919 case Intrinsic::atomic_load_nand:
4920 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4921 case Intrinsic::atomic_load_max:
4922 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4923 case Intrinsic::atomic_load_min:
4924 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4925 case Intrinsic::atomic_load_umin:
4926 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4927 case Intrinsic::atomic_load_umax:
4928 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4929 case Intrinsic::atomic_swap:
4930 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4932 case Intrinsic::invariant_start:
4933 case Intrinsic::lifetime_start:
4934 // Discard region information.
4935 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4937 case Intrinsic::invariant_end:
4938 case Intrinsic::lifetime_end:
4939 // Discard region information.
4944 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4946 MachineBasicBlock *LandingPad) {
4947 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4948 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4949 Type *RetTy = FTy->getReturnType();
4950 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4951 MCSymbol *BeginLabel = 0;
4953 TargetLowering::ArgListTy Args;
4954 TargetLowering::ArgListEntry Entry;
4955 Args.reserve(CS.arg_size());
4957 // Check whether the function can return without sret-demotion.
4958 SmallVector<ISD::OutputArg, 4> Outs;
4959 SmallVector<uint64_t, 4> Offsets;
4960 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4961 Outs, TLI, &Offsets);
4963 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4964 DAG.getMachineFunction(),
4965 FTy->isVarArg(), Outs,
4968 SDValue DemoteStackSlot;
4969 int DemoteStackIdx = -100;
4971 if (!CanLowerReturn) {
4972 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4973 FTy->getReturnType());
4974 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4975 FTy->getReturnType());
4976 MachineFunction &MF = DAG.getMachineFunction();
4977 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4978 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4980 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4981 Entry.Node = DemoteStackSlot;
4982 Entry.Ty = StackSlotPtrType;
4983 Entry.isSExt = false;
4984 Entry.isZExt = false;
4985 Entry.isInReg = false;
4986 Entry.isSRet = true;
4987 Entry.isNest = false;
4988 Entry.isByVal = false;
4989 Entry.Alignment = Align;
4990 Args.push_back(Entry);
4991 RetTy = Type::getVoidTy(FTy->getContext());
4994 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4996 const Value *V = *i;
4999 if (V->getType()->isEmptyTy())
5002 SDValue ArgNode = getValue(V);
5003 Entry.Node = ArgNode; Entry.Ty = V->getType();
5005 unsigned attrInd = i - CS.arg_begin() + 1;
5006 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5007 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5008 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5009 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5010 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5011 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5012 Entry.Alignment = CS.getParamAlignment(attrInd);
5013 Args.push_back(Entry);
5017 // Insert a label before the invoke call to mark the try range. This can be
5018 // used to detect deletion of the invoke via the MachineModuleInfo.
5019 BeginLabel = MMI.getContext().CreateTempSymbol();
5021 // For SjLj, keep track of which landing pads go with which invokes
5022 // so as to maintain the ordering of pads in the LSDA.
5023 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5024 if (CallSiteIndex) {
5025 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5026 // Now that the call site is handled, stop tracking it.
5027 MMI.setCurrentCallSite(0);
5030 // Both PendingLoads and PendingExports must be flushed here;
5031 // this call might not return.
5033 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5036 // Check if target-independent constraints permit a tail call here.
5037 // Target-dependent constraints are checked within TLI.LowerCallTo.
5039 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5042 // If there's a possibility that fast-isel has already selected some amount
5043 // of the current basic block, don't emit a tail call.
5044 if (isTailCall && EnableFastISel)
5047 std::pair<SDValue,SDValue> Result =
5048 TLI.LowerCallTo(getRoot(), RetTy,
5049 CS.paramHasAttr(0, Attribute::SExt),
5050 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5051 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5052 CS.getCallingConv(),
5054 !CS.getInstruction()->use_empty(),
5055 Callee, Args, DAG, getCurDebugLoc());
5056 assert((isTailCall || Result.second.getNode()) &&
5057 "Non-null chain expected with non-tail call!");
5058 assert((Result.second.getNode() || !Result.first.getNode()) &&
5059 "Null value expected with tail call!");
5060 if (Result.first.getNode()) {
5061 setValue(CS.getInstruction(), Result.first);
5062 } else if (!CanLowerReturn && Result.second.getNode()) {
5063 // The instruction result is the result of loading from the
5064 // hidden sret parameter.
5065 SmallVector<EVT, 1> PVTs;
5066 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5068 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5069 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5070 EVT PtrVT = PVTs[0];
5071 unsigned NumValues = Outs.size();
5072 SmallVector<SDValue, 4> Values(NumValues);
5073 SmallVector<SDValue, 4> Chains(NumValues);
5075 for (unsigned i = 0; i < NumValues; ++i) {
5076 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5078 DAG.getConstant(Offsets[i], PtrVT));
5079 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5081 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5084 Chains[i] = L.getValue(1);
5087 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5088 MVT::Other, &Chains[0], NumValues);
5089 PendingLoads.push_back(Chain);
5091 // Collect the legal value parts into potentially illegal values
5092 // that correspond to the original function's return values.
5093 SmallVector<EVT, 4> RetTys;
5094 RetTy = FTy->getReturnType();
5095 ComputeValueVTs(TLI, RetTy, RetTys);
5096 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5097 SmallVector<SDValue, 4> ReturnValues;
5098 unsigned CurReg = 0;
5099 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5101 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5102 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5104 SDValue ReturnValue =
5105 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5106 RegisterVT, VT, AssertOp);
5107 ReturnValues.push_back(ReturnValue);
5111 setValue(CS.getInstruction(),
5112 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5113 DAG.getVTList(&RetTys[0], RetTys.size()),
5114 &ReturnValues[0], ReturnValues.size()));
5117 // Assign order to nodes here. If the call does not produce a result, it won't
5118 // be mapped to a SDNode and visit() will not assign it an order number.
5119 if (!Result.second.getNode()) {
5120 // As a special case, a null chain means that a tail call has been emitted and
5121 // the DAG root is already updated.
5124 AssignOrderingToNode(DAG.getRoot().getNode());
5126 DAG.setRoot(Result.second);
5128 AssignOrderingToNode(Result.second.getNode());
5132 // Insert a label at the end of the invoke call to mark the try range. This
5133 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5134 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5135 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5137 // Inform MachineModuleInfo of range.
5138 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5142 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5143 /// value is equal or not-equal to zero.
5144 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5145 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5147 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5148 if (IC->isEquality())
5149 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5150 if (C->isNullValue())
5152 // Unknown instruction.
5158 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5160 SelectionDAGBuilder &Builder) {
5162 // Check to see if this load can be trivially constant folded, e.g. if the
5163 // input is from a string literal.
5164 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5165 // Cast pointer to the type we really want to load.
5166 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5167 PointerType::getUnqual(LoadTy));
5169 if (const Constant *LoadCst =
5170 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5172 return Builder.getValue(LoadCst);
5175 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5176 // still constant memory, the input chain can be the entry node.
5178 bool ConstantMemory = false;
5180 // Do not serialize (non-volatile) loads of constant memory with anything.
5181 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5182 Root = Builder.DAG.getEntryNode();
5183 ConstantMemory = true;
5185 // Do not serialize non-volatile loads against each other.
5186 Root = Builder.DAG.getRoot();
5189 SDValue Ptr = Builder.getValue(PtrVal);
5190 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5191 Ptr, MachinePointerInfo(PtrVal),
5193 false /*nontemporal*/, 1 /* align=1 */);
5195 if (!ConstantMemory)
5196 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5201 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5202 /// If so, return true and lower it, otherwise return false and it will be
5203 /// lowered like a normal call.
5204 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5205 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5206 if (I.getNumArgOperands() != 3)
5209 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5210 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5211 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5212 !I.getType()->isIntegerTy())
5215 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5217 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5218 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5219 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5220 bool ActuallyDoIt = true;
5223 switch (Size->getZExtValue()) {
5225 LoadVT = MVT::Other;
5227 ActuallyDoIt = false;
5231 LoadTy = Type::getInt16Ty(Size->getContext());
5235 LoadTy = Type::getInt32Ty(Size->getContext());
5239 LoadTy = Type::getInt64Ty(Size->getContext());
5243 LoadVT = MVT::v4i32;
5244 LoadTy = Type::getInt32Ty(Size->getContext());
5245 LoadTy = VectorType::get(LoadTy, 4);
5250 // This turns into unaligned loads. We only do this if the target natively
5251 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5252 // we'll only produce a small number of byte loads.
5254 // Require that we can find a legal MVT, and only do this if the target
5255 // supports unaligned loads of that type. Expanding into byte loads would
5257 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5258 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5259 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5260 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5261 ActuallyDoIt = false;
5265 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5266 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5268 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5270 EVT CallVT = TLI.getValueType(I.getType(), true);
5271 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5281 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5282 // Handle inline assembly differently.
5283 if (isa<InlineAsm>(I.getCalledValue())) {
5288 // See if any floating point values are being passed to this function. This is
5289 // used to emit an undefined reference to fltused on Windows.
5291 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5292 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5293 if (FT->isVarArg() &&
5294 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5295 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5296 Type* T = I.getArgOperand(i)->getType();
5297 for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
5299 if (!i->isFloatingPointTy()) continue;
5300 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5306 const char *RenameFn = 0;
5307 if (Function *F = I.getCalledFunction()) {
5308 if (F->isDeclaration()) {
5309 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5310 if (unsigned IID = II->getIntrinsicID(F)) {
5311 RenameFn = visitIntrinsicCall(I, IID);
5316 if (unsigned IID = F->getIntrinsicID()) {
5317 RenameFn = visitIntrinsicCall(I, IID);
5323 // Check for well-known libc/libm calls. If the function is internal, it
5324 // can't be a library call.
5325 if (!F->hasLocalLinkage() && F->hasName()) {
5326 StringRef Name = F->getName();
5327 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5328 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5329 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5330 I.getType() == I.getArgOperand(0)->getType() &&
5331 I.getType() == I.getArgOperand(1)->getType()) {
5332 SDValue LHS = getValue(I.getArgOperand(0));
5333 SDValue RHS = getValue(I.getArgOperand(1));
5334 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5335 LHS.getValueType(), LHS, RHS));
5338 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5339 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5340 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5341 I.getType() == I.getArgOperand(0)->getType()) {
5342 SDValue Tmp = getValue(I.getArgOperand(0));
5343 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5344 Tmp.getValueType(), Tmp));
5347 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5348 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5349 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5350 I.getType() == I.getArgOperand(0)->getType() &&
5351 I.onlyReadsMemory()) {
5352 SDValue Tmp = getValue(I.getArgOperand(0));
5353 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5354 Tmp.getValueType(), Tmp));
5357 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5358 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5359 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5360 I.getType() == I.getArgOperand(0)->getType() &&
5361 I.onlyReadsMemory()) {
5362 SDValue Tmp = getValue(I.getArgOperand(0));
5363 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5364 Tmp.getValueType(), Tmp));
5367 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5368 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5369 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5370 I.getType() == I.getArgOperand(0)->getType() &&
5371 I.onlyReadsMemory()) {
5372 SDValue Tmp = getValue(I.getArgOperand(0));
5373 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5374 Tmp.getValueType(), Tmp));
5377 } else if (Name == "memcmp") {
5378 if (visitMemCmpCall(I))
5386 Callee = getValue(I.getCalledValue());
5388 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5390 // Check if we can potentially perform a tail call. More detailed checking is
5391 // be done within LowerCallTo, after more information about the call is known.
5392 LowerCallTo(&I, Callee, I.isTailCall());
5397 /// AsmOperandInfo - This contains information for each constraint that we are
5399 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5401 /// CallOperand - If this is the result output operand or a clobber
5402 /// this is null, otherwise it is the incoming operand to the CallInst.
5403 /// This gets modified as the asm is processed.
5404 SDValue CallOperand;
5406 /// AssignedRegs - If this is a register or register class operand, this
5407 /// contains the set of register corresponding to the operand.
5408 RegsForValue AssignedRegs;
5410 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5411 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5414 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5415 /// busy in OutputRegs/InputRegs.
5416 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5417 std::set<unsigned> &OutputRegs,
5418 std::set<unsigned> &InputRegs,
5419 const TargetRegisterInfo &TRI) const {
5421 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5422 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5425 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5426 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5430 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5431 /// corresponds to. If there is no Value* for this operand, it returns
5433 EVT getCallOperandValEVT(LLVMContext &Context,
5434 const TargetLowering &TLI,
5435 const TargetData *TD) const {
5436 if (CallOperandVal == 0) return MVT::Other;
5438 if (isa<BasicBlock>(CallOperandVal))
5439 return TLI.getPointerTy();
5441 llvm::Type *OpTy = CallOperandVal->getType();
5443 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5444 // If this is an indirect operand, the operand is a pointer to the
5447 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5449 report_fatal_error("Indirect operand for inline asm not a pointer!");
5450 OpTy = PtrTy->getElementType();
5453 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5454 if (StructType *STy = dyn_cast<StructType>(OpTy))
5455 if (STy->getNumElements() == 1)
5456 OpTy = STy->getElementType(0);
5458 // If OpTy is not a single value, it may be a struct/union that we
5459 // can tile with integers.
5460 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5461 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5470 OpTy = IntegerType::get(Context, BitSize);
5475 return TLI.getValueType(OpTy, true);
5479 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5481 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5482 const TargetRegisterInfo &TRI) {
5483 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5485 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5486 for (; *Aliases; ++Aliases)
5487 Regs.insert(*Aliases);
5491 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5493 } // end anonymous namespace
5495 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5496 /// specified operand. We prefer to assign virtual registers, to allow the
5497 /// register allocator to handle the assignment process. However, if the asm
5498 /// uses features that we can't model on machineinstrs, we have SDISel do the
5499 /// allocation. This produces generally horrible, but correct, code.
5501 /// OpInfo describes the operand.
5502 /// Input and OutputRegs are the set of already allocated physical registers.
5504 static void GetRegistersForValue(SelectionDAG &DAG,
5505 const TargetLowering &TLI,
5507 SDISelAsmOperandInfo &OpInfo,
5508 std::set<unsigned> &OutputRegs,
5509 std::set<unsigned> &InputRegs) {
5510 LLVMContext &Context = *DAG.getContext();
5512 // Compute whether this value requires an input register, an output register,
5514 bool isOutReg = false;
5515 bool isInReg = false;
5516 switch (OpInfo.Type) {
5517 case InlineAsm::isOutput:
5520 // If there is an input constraint that matches this, we need to reserve
5521 // the input register so no other inputs allocate to it.
5522 isInReg = OpInfo.hasMatchingInput();
5524 case InlineAsm::isInput:
5528 case InlineAsm::isClobber:
5535 MachineFunction &MF = DAG.getMachineFunction();
5536 SmallVector<unsigned, 4> Regs;
5538 // If this is a constraint for a single physreg, or a constraint for a
5539 // register class, find it.
5540 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5541 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5542 OpInfo.ConstraintVT);
5544 unsigned NumRegs = 1;
5545 if (OpInfo.ConstraintVT != MVT::Other) {
5546 // If this is a FP input in an integer register (or visa versa) insert a bit
5547 // cast of the input value. More generally, handle any case where the input
5548 // value disagrees with the register class we plan to stick this in.
5549 if (OpInfo.Type == InlineAsm::isInput &&
5550 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5551 // Try to convert to the first EVT that the reg class contains. If the
5552 // types are identical size, use a bitcast to convert (e.g. two differing
5554 EVT RegVT = *PhysReg.second->vt_begin();
5555 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5556 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5557 RegVT, OpInfo.CallOperand);
5558 OpInfo.ConstraintVT = RegVT;
5559 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5560 // If the input is a FP value and we want it in FP registers, do a
5561 // bitcast to the corresponding integer type. This turns an f64 value
5562 // into i64, which can be passed with two i32 values on a 32-bit
5564 RegVT = EVT::getIntegerVT(Context,
5565 OpInfo.ConstraintVT.getSizeInBits());
5566 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5567 RegVT, OpInfo.CallOperand);
5568 OpInfo.ConstraintVT = RegVT;
5572 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5576 EVT ValueVT = OpInfo.ConstraintVT;
5578 // If this is a constraint for a specific physical register, like {r17},
5580 if (unsigned AssignedReg = PhysReg.first) {
5581 const TargetRegisterClass *RC = PhysReg.second;
5582 if (OpInfo.ConstraintVT == MVT::Other)
5583 ValueVT = *RC->vt_begin();
5585 // Get the actual register value type. This is important, because the user
5586 // may have asked for (e.g.) the AX register in i32 type. We need to
5587 // remember that AX is actually i16 to get the right extension.
5588 RegVT = *RC->vt_begin();
5590 // This is a explicit reference to a physical register.
5591 Regs.push_back(AssignedReg);
5593 // If this is an expanded reference, add the rest of the regs to Regs.
5595 TargetRegisterClass::iterator I = RC->begin();
5596 for (; *I != AssignedReg; ++I)
5597 assert(I != RC->end() && "Didn't find reg!");
5599 // Already added the first reg.
5601 for (; NumRegs; --NumRegs, ++I) {
5602 assert(I != RC->end() && "Ran out of registers to allocate!");
5607 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5608 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5609 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5613 // Otherwise, if this was a reference to an LLVM register class, create vregs
5614 // for this reference.
5615 if (const TargetRegisterClass *RC = PhysReg.second) {
5616 RegVT = *RC->vt_begin();
5617 if (OpInfo.ConstraintVT == MVT::Other)
5620 // Create the appropriate number of virtual registers.
5621 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5622 for (; NumRegs; --NumRegs)
5623 Regs.push_back(RegInfo.createVirtualRegister(RC));
5625 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5629 // Otherwise, we couldn't allocate enough registers for this.
5632 /// visitInlineAsm - Handle a call to an InlineAsm object.
5634 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5635 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5637 /// ConstraintOperands - Information about all of the constraints.
5638 SDISelAsmOperandInfoVector ConstraintOperands;
5640 std::set<unsigned> OutputRegs, InputRegs;
5642 TargetLowering::AsmOperandInfoVector
5643 TargetConstraints = TLI.ParseConstraints(CS);
5645 bool hasMemory = false;
5647 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5648 unsigned ResNo = 0; // ResNo - The result number of the next output.
5649 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5650 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5651 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5653 EVT OpVT = MVT::Other;
5655 // Compute the value type for each operand.
5656 switch (OpInfo.Type) {
5657 case InlineAsm::isOutput:
5658 // Indirect outputs just consume an argument.
5659 if (OpInfo.isIndirect) {
5660 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5664 // The return value of the call is this value. As such, there is no
5665 // corresponding argument.
5666 assert(!CS.getType()->isVoidTy() &&
5668 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5669 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5671 assert(ResNo == 0 && "Asm only has one result!");
5672 OpVT = TLI.getValueType(CS.getType());
5676 case InlineAsm::isInput:
5677 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5679 case InlineAsm::isClobber:
5684 // If this is an input or an indirect output, process the call argument.
5685 // BasicBlocks are labels, currently appearing only in asm's.
5686 if (OpInfo.CallOperandVal) {
5687 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5688 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5690 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5693 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5696 OpInfo.ConstraintVT = OpVT;
5698 // Indirect operand accesses access memory.
5699 if (OpInfo.isIndirect)
5702 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5703 TargetLowering::ConstraintType
5704 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5705 if (CType == TargetLowering::C_Memory) {
5713 SDValue Chain, Flag;
5715 // We won't need to flush pending loads if this asm doesn't touch
5716 // memory and is nonvolatile.
5717 if (hasMemory || IA->hasSideEffects())
5720 Chain = DAG.getRoot();
5722 // Second pass over the constraints: compute which constraint option to use
5723 // and assign registers to constraints that want a specific physreg.
5724 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5725 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5727 // If this is an output operand with a matching input operand, look up the
5728 // matching input. If their types mismatch, e.g. one is an integer, the
5729 // other is floating point, or their sizes are different, flag it as an
5731 if (OpInfo.hasMatchingInput()) {
5732 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5734 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5735 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5736 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
5737 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5738 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
5739 if ((OpInfo.ConstraintVT.isInteger() !=
5740 Input.ConstraintVT.isInteger()) ||
5741 (MatchRC.second != InputRC.second)) {
5742 report_fatal_error("Unsupported asm: input constraint"
5743 " with a matching output constraint of"
5744 " incompatible type!");
5746 Input.ConstraintVT = OpInfo.ConstraintVT;
5750 // Compute the constraint code and ConstraintType to use.
5751 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5753 // If this is a memory input, and if the operand is not indirect, do what we
5754 // need to to provide an address for the memory input.
5755 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5756 !OpInfo.isIndirect) {
5757 assert((OpInfo.isMultipleAlternative ||
5758 (OpInfo.Type == InlineAsm::isInput)) &&
5759 "Can only indirectify direct input operands!");
5761 // Memory operands really want the address of the value. If we don't have
5762 // an indirect input, put it in the constpool if we can, otherwise spill
5763 // it to a stack slot.
5764 // TODO: This isn't quite right. We need to handle these according to
5765 // the addressing mode that the constraint wants. Also, this may take
5766 // an additional register for the computation and we don't want that
5769 // If the operand is a float, integer, or vector constant, spill to a
5770 // constant pool entry to get its address.
5771 const Value *OpVal = OpInfo.CallOperandVal;
5772 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5773 isa<ConstantVector>(OpVal)) {
5774 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5775 TLI.getPointerTy());
5777 // Otherwise, create a stack slot and emit a store to it before the
5779 Type *Ty = OpVal->getType();
5780 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5781 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5782 MachineFunction &MF = DAG.getMachineFunction();
5783 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5784 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5785 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5786 OpInfo.CallOperand, StackSlot,
5787 MachinePointerInfo::getFixedStack(SSFI),
5789 OpInfo.CallOperand = StackSlot;
5792 // There is no longer a Value* corresponding to this operand.
5793 OpInfo.CallOperandVal = 0;
5795 // It is now an indirect operand.
5796 OpInfo.isIndirect = true;
5799 // If this constraint is for a specific register, allocate it before
5801 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5802 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5806 // Second pass - Loop over all of the operands, assigning virtual or physregs
5807 // to register class operands.
5808 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5809 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5811 // C_Register operands have already been allocated, Other/Memory don't need
5813 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5814 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5818 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5819 std::vector<SDValue> AsmNodeOperands;
5820 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5821 AsmNodeOperands.push_back(
5822 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5823 TLI.getPointerTy()));
5825 // If we have a !srcloc metadata node associated with it, we want to attach
5826 // this to the ultimately generated inline asm machineinstr. To do this, we
5827 // pass in the third operand as this (potentially null) inline asm MDNode.
5828 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5829 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5831 // Remember the HasSideEffect and AlignStack bits as operand 3.
5832 unsigned ExtraInfo = 0;
5833 if (IA->hasSideEffects())
5834 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5835 if (IA->isAlignStack())
5836 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5837 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5838 TLI.getPointerTy()));
5840 // Loop over all of the inputs, copying the operand values into the
5841 // appropriate registers and processing the output regs.
5842 RegsForValue RetValRegs;
5844 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5845 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5847 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5848 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5850 switch (OpInfo.Type) {
5851 case InlineAsm::isOutput: {
5852 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5853 OpInfo.ConstraintType != TargetLowering::C_Register) {
5854 // Memory output, or 'other' output (e.g. 'X' constraint).
5855 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5857 // Add information to the INLINEASM node to know about this output.
5858 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5859 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5860 TLI.getPointerTy()));
5861 AsmNodeOperands.push_back(OpInfo.CallOperand);
5865 // Otherwise, this is a register or register class output.
5867 // Copy the output from the appropriate register. Find a register that
5869 if (OpInfo.AssignedRegs.Regs.empty())
5870 report_fatal_error("Couldn't allocate output reg for constraint '" +
5871 Twine(OpInfo.ConstraintCode) + "'!");
5873 // If this is an indirect operand, store through the pointer after the
5875 if (OpInfo.isIndirect) {
5876 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5877 OpInfo.CallOperandVal));
5879 // This is the result value of the call.
5880 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5881 // Concatenate this output onto the outputs list.
5882 RetValRegs.append(OpInfo.AssignedRegs);
5885 // Add information to the INLINEASM node to know that this register is
5887 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5888 InlineAsm::Kind_RegDefEarlyClobber :
5889 InlineAsm::Kind_RegDef,
5896 case InlineAsm::isInput: {
5897 SDValue InOperandVal = OpInfo.CallOperand;
5899 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5900 // If this is required to match an output register we have already set,
5901 // just use its register.
5902 unsigned OperandNo = OpInfo.getMatchedOperand();
5904 // Scan until we find the definition we already emitted of this operand.
5905 // When we find it, create a RegsForValue operand.
5906 unsigned CurOp = InlineAsm::Op_FirstOperand;
5907 for (; OperandNo; --OperandNo) {
5908 // Advance to the next operand.
5910 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5911 assert((InlineAsm::isRegDefKind(OpFlag) ||
5912 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5913 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5914 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5918 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5919 if (InlineAsm::isRegDefKind(OpFlag) ||
5920 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5921 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5922 if (OpInfo.isIndirect) {
5923 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5924 LLVMContext &Ctx = *DAG.getContext();
5925 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5926 " don't know how to handle tied "
5927 "indirect register inputs");
5930 RegsForValue MatchedRegs;
5931 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5932 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5933 MatchedRegs.RegVTs.push_back(RegVT);
5934 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5935 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5937 MatchedRegs.Regs.push_back
5938 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5940 // Use the produced MatchedRegs object to
5941 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5943 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5944 true, OpInfo.getMatchedOperand(),
5945 DAG, AsmNodeOperands);
5949 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5950 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5951 "Unexpected number of operands");
5952 // Add information to the INLINEASM node to know about this input.
5953 // See InlineAsm.h isUseOperandTiedToDef.
5954 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5955 OpInfo.getMatchedOperand());
5956 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5957 TLI.getPointerTy()));
5958 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5962 // Treat indirect 'X' constraint as memory.
5963 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5965 OpInfo.ConstraintType = TargetLowering::C_Memory;
5967 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5968 std::vector<SDValue> Ops;
5969 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
5972 report_fatal_error("Invalid operand for inline asm constraint '" +
5973 Twine(OpInfo.ConstraintCode) + "'!");
5975 // Add information to the INLINEASM node to know about this input.
5976 unsigned ResOpType =
5977 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5978 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5979 TLI.getPointerTy()));
5980 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5984 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5985 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5986 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5987 "Memory operands expect pointer values");
5989 // Add information to the INLINEASM node to know about this input.
5990 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5991 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5992 TLI.getPointerTy()));
5993 AsmNodeOperands.push_back(InOperandVal);
5997 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5998 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5999 "Unknown constraint type!");
6000 assert(!OpInfo.isIndirect &&
6001 "Don't know how to handle indirect register inputs yet!");
6003 // Copy the input into the appropriate registers.
6004 if (OpInfo.AssignedRegs.Regs.empty())
6005 report_fatal_error("Couldn't allocate input reg for constraint '" +
6006 Twine(OpInfo.ConstraintCode) + "'!");
6008 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6011 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6012 DAG, AsmNodeOperands);
6015 case InlineAsm::isClobber: {
6016 // Add the clobbered value to the operand list, so that the register
6017 // allocator is aware that the physreg got clobbered.
6018 if (!OpInfo.AssignedRegs.Regs.empty())
6019 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6027 // Finish up input operands. Set the input chain and add the flag last.
6028 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6029 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6031 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6032 DAG.getVTList(MVT::Other, MVT::Glue),
6033 &AsmNodeOperands[0], AsmNodeOperands.size());
6034 Flag = Chain.getValue(1);
6036 // If this asm returns a register value, copy the result from that register
6037 // and set it as the value of the call.
6038 if (!RetValRegs.Regs.empty()) {
6039 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6042 // FIXME: Why don't we do this for inline asms with MRVs?
6043 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6044 EVT ResultType = TLI.getValueType(CS.getType());
6046 // If any of the results of the inline asm is a vector, it may have the
6047 // wrong width/num elts. This can happen for register classes that can
6048 // contain multiple different value types. The preg or vreg allocated may
6049 // not have the same VT as was expected. Convert it to the right type
6050 // with bit_convert.
6051 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6052 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6055 } else if (ResultType != Val.getValueType() &&
6056 ResultType.isInteger() && Val.getValueType().isInteger()) {
6057 // If a result value was tied to an input value, the computed result may
6058 // have a wider width than the expected result. Extract the relevant
6060 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6063 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6066 setValue(CS.getInstruction(), Val);
6067 // Don't need to use this as a chain in this case.
6068 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6072 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6074 // Process indirect outputs, first output all of the flagged copies out of
6076 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6077 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6078 const Value *Ptr = IndirectStoresToEmit[i].second;
6079 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6081 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6084 // Emit the non-flagged stores from the physregs.
6085 SmallVector<SDValue, 8> OutChains;
6086 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6087 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6088 StoresToEmit[i].first,
6089 getValue(StoresToEmit[i].second),
6090 MachinePointerInfo(StoresToEmit[i].second),
6092 OutChains.push_back(Val);
6095 if (!OutChains.empty())
6096 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6097 &OutChains[0], OutChains.size());
6102 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6103 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6104 MVT::Other, getRoot(),
6105 getValue(I.getArgOperand(0)),
6106 DAG.getSrcValue(I.getArgOperand(0))));
6109 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6110 const TargetData &TD = *TLI.getTargetData();
6111 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6112 getRoot(), getValue(I.getOperand(0)),
6113 DAG.getSrcValue(I.getOperand(0)),
6114 TD.getABITypeAlignment(I.getType()));
6116 DAG.setRoot(V.getValue(1));
6119 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6120 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6121 MVT::Other, getRoot(),
6122 getValue(I.getArgOperand(0)),
6123 DAG.getSrcValue(I.getArgOperand(0))));
6126 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6127 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6128 MVT::Other, getRoot(),
6129 getValue(I.getArgOperand(0)),
6130 getValue(I.getArgOperand(1)),
6131 DAG.getSrcValue(I.getArgOperand(0)),
6132 DAG.getSrcValue(I.getArgOperand(1))));
6135 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6136 /// implementation, which just calls LowerCall.
6137 /// FIXME: When all targets are
6138 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6139 std::pair<SDValue, SDValue>
6140 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6141 bool RetSExt, bool RetZExt, bool isVarArg,
6142 bool isInreg, unsigned NumFixedArgs,
6143 CallingConv::ID CallConv, bool isTailCall,
6144 bool isReturnValueUsed,
6146 ArgListTy &Args, SelectionDAG &DAG,
6147 DebugLoc dl) const {
6148 // Handle all of the outgoing arguments.
6149 SmallVector<ISD::OutputArg, 32> Outs;
6150 SmallVector<SDValue, 32> OutVals;
6151 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6152 SmallVector<EVT, 4> ValueVTs;
6153 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6154 for (unsigned Value = 0, NumValues = ValueVTs.size();
6155 Value != NumValues; ++Value) {
6156 EVT VT = ValueVTs[Value];
6157 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6158 SDValue Op = SDValue(Args[i].Node.getNode(),
6159 Args[i].Node.getResNo() + Value);
6160 ISD::ArgFlagsTy Flags;
6161 unsigned OriginalAlignment =
6162 getTargetData()->getABITypeAlignment(ArgTy);
6168 if (Args[i].isInReg)
6172 if (Args[i].isByVal) {
6174 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6175 Type *ElementTy = Ty->getElementType();
6176 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6177 // For ByVal, alignment should come from FE. BE will guess if this
6178 // info is not there but there are cases it cannot get right.
6179 unsigned FrameAlign;
6180 if (Args[i].Alignment)
6181 FrameAlign = Args[i].Alignment;
6183 FrameAlign = getByValTypeAlignment(ElementTy);
6184 Flags.setByValAlign(FrameAlign);
6188 Flags.setOrigAlign(OriginalAlignment);
6190 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6191 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6192 SmallVector<SDValue, 4> Parts(NumParts);
6193 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6196 ExtendKind = ISD::SIGN_EXTEND;
6197 else if (Args[i].isZExt)
6198 ExtendKind = ISD::ZERO_EXTEND;
6200 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6201 PartVT, ExtendKind);
6203 for (unsigned j = 0; j != NumParts; ++j) {
6204 // if it isn't first piece, alignment must be 1
6205 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6207 if (NumParts > 1 && j == 0)
6208 MyFlags.Flags.setSplit();
6210 MyFlags.Flags.setOrigAlign(1);
6212 Outs.push_back(MyFlags);
6213 OutVals.push_back(Parts[j]);
6218 // Handle the incoming return values from the call.
6219 SmallVector<ISD::InputArg, 32> Ins;
6220 SmallVector<EVT, 4> RetTys;
6221 ComputeValueVTs(*this, RetTy, RetTys);
6222 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6224 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6225 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6226 for (unsigned i = 0; i != NumRegs; ++i) {
6227 ISD::InputArg MyFlags;
6228 MyFlags.VT = RegisterVT.getSimpleVT();
6229 MyFlags.Used = isReturnValueUsed;
6231 MyFlags.Flags.setSExt();
6233 MyFlags.Flags.setZExt();
6235 MyFlags.Flags.setInReg();
6236 Ins.push_back(MyFlags);
6240 SmallVector<SDValue, 4> InVals;
6241 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6242 Outs, OutVals, Ins, dl, DAG, InVals);
6244 // Verify that the target's LowerCall behaved as expected.
6245 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6246 "LowerCall didn't return a valid chain!");
6247 assert((!isTailCall || InVals.empty()) &&
6248 "LowerCall emitted a return value for a tail call!");
6249 assert((isTailCall || InVals.size() == Ins.size()) &&
6250 "LowerCall didn't emit the correct number of values!");
6252 // For a tail call, the return value is merely live-out and there aren't
6253 // any nodes in the DAG representing it. Return a special value to
6254 // indicate that a tail call has been emitted and no more Instructions
6255 // should be processed in the current block.
6258 return std::make_pair(SDValue(), SDValue());
6261 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6262 assert(InVals[i].getNode() &&
6263 "LowerCall emitted a null value!");
6264 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6265 "LowerCall emitted a value with the wrong type!");
6268 // Collect the legal value parts into potentially illegal values
6269 // that correspond to the original function's return values.
6270 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6272 AssertOp = ISD::AssertSext;
6274 AssertOp = ISD::AssertZext;
6275 SmallVector<SDValue, 4> ReturnValues;
6276 unsigned CurReg = 0;
6277 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6279 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6280 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6282 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6283 NumRegs, RegisterVT, VT,
6288 // For a function returning void, there is no return value. We can't create
6289 // such a node, so we just return a null return value in that case. In
6290 // that case, nothing will actually look at the value.
6291 if (ReturnValues.empty())
6292 return std::make_pair(SDValue(), Chain);
6294 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6295 DAG.getVTList(&RetTys[0], RetTys.size()),
6296 &ReturnValues[0], ReturnValues.size());
6297 return std::make_pair(Res, Chain);
6300 void TargetLowering::LowerOperationWrapper(SDNode *N,
6301 SmallVectorImpl<SDValue> &Results,
6302 SelectionDAG &DAG) const {
6303 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6305 Results.push_back(Res);
6308 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6309 llvm_unreachable("LowerOperation not implemented for this target!");
6314 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6315 SDValue Op = getNonRegisterValue(V);
6316 assert((Op.getOpcode() != ISD::CopyFromReg ||
6317 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6318 "Copy from a reg to the same reg!");
6319 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6321 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6322 SDValue Chain = DAG.getEntryNode();
6323 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6324 PendingExports.push_back(Chain);
6327 #include "llvm/CodeGen/SelectionDAGISel.h"
6329 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6330 /// entry block, return true. This includes arguments used by switches, since
6331 /// the switch may expand into multiple basic blocks.
6332 static bool isOnlyUsedInEntryBlock(const Argument *A) {
6333 // With FastISel active, we may be splitting blocks, so force creation
6334 // of virtual registers for all non-dead arguments.
6336 return A->use_empty();
6338 const BasicBlock *Entry = A->getParent()->begin();
6339 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6341 const User *U = *UI;
6342 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6343 return false; // Use not in entry block.
6348 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6349 // If this is the entry block, emit arguments.
6350 const Function &F = *LLVMBB->getParent();
6351 SelectionDAG &DAG = SDB->DAG;
6352 DebugLoc dl = SDB->getCurDebugLoc();
6353 const TargetData *TD = TLI.getTargetData();
6354 SmallVector<ISD::InputArg, 16> Ins;
6356 // Check whether the function can return without sret-demotion.
6357 SmallVector<ISD::OutputArg, 4> Outs;
6358 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6361 if (!FuncInfo->CanLowerReturn) {
6362 // Put in an sret pointer parameter before all the other parameters.
6363 SmallVector<EVT, 1> ValueVTs;
6364 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6366 // NOTE: Assuming that a pointer will never break down to more than one VT
6368 ISD::ArgFlagsTy Flags;
6370 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6371 ISD::InputArg RetArg(Flags, RegisterVT, true);
6372 Ins.push_back(RetArg);
6375 // Set up the incoming argument description vector.
6377 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6378 I != E; ++I, ++Idx) {
6379 SmallVector<EVT, 4> ValueVTs;
6380 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6381 bool isArgValueUsed = !I->use_empty();
6382 for (unsigned Value = 0, NumValues = ValueVTs.size();
6383 Value != NumValues; ++Value) {
6384 EVT VT = ValueVTs[Value];
6385 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6386 ISD::ArgFlagsTy Flags;
6387 unsigned OriginalAlignment =
6388 TD->getABITypeAlignment(ArgTy);
6390 if (F.paramHasAttr(Idx, Attribute::ZExt))
6392 if (F.paramHasAttr(Idx, Attribute::SExt))
6394 if (F.paramHasAttr(Idx, Attribute::InReg))
6396 if (F.paramHasAttr(Idx, Attribute::StructRet))
6398 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6400 PointerType *Ty = cast<PointerType>(I->getType());
6401 Type *ElementTy = Ty->getElementType();
6402 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6403 // For ByVal, alignment should be passed from FE. BE will guess if
6404 // this info is not there but there are cases it cannot get right.
6405 unsigned FrameAlign;
6406 if (F.getParamAlignment(Idx))
6407 FrameAlign = F.getParamAlignment(Idx);
6409 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6410 Flags.setByValAlign(FrameAlign);
6412 if (F.paramHasAttr(Idx, Attribute::Nest))
6414 Flags.setOrigAlign(OriginalAlignment);
6416 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6417 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6418 for (unsigned i = 0; i != NumRegs; ++i) {
6419 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6420 if (NumRegs > 1 && i == 0)
6421 MyFlags.Flags.setSplit();
6422 // if it isn't first piece, alignment must be 1
6424 MyFlags.Flags.setOrigAlign(1);
6425 Ins.push_back(MyFlags);
6430 // Call the target to set up the argument values.
6431 SmallVector<SDValue, 8> InVals;
6432 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6436 // Verify that the target's LowerFormalArguments behaved as expected.
6437 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6438 "LowerFormalArguments didn't return a valid chain!");
6439 assert(InVals.size() == Ins.size() &&
6440 "LowerFormalArguments didn't emit the correct number of values!");
6442 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6443 assert(InVals[i].getNode() &&
6444 "LowerFormalArguments emitted a null value!");
6445 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6446 "LowerFormalArguments emitted a value with the wrong type!");
6450 // Update the DAG with the new chain value resulting from argument lowering.
6451 DAG.setRoot(NewRoot);
6453 // Set up the argument values.
6456 if (!FuncInfo->CanLowerReturn) {
6457 // Create a virtual register for the sret pointer, and put in a copy
6458 // from the sret argument into it.
6459 SmallVector<EVT, 1> ValueVTs;
6460 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6461 EVT VT = ValueVTs[0];
6462 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6463 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6464 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6465 RegVT, VT, AssertOp);
6467 MachineFunction& MF = SDB->DAG.getMachineFunction();
6468 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6469 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6470 FuncInfo->DemoteRegister = SRetReg;
6471 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6473 DAG.setRoot(NewRoot);
6475 // i indexes lowered arguments. Bump it past the hidden sret argument.
6476 // Idx indexes LLVM arguments. Don't touch it.
6480 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6482 SmallVector<SDValue, 4> ArgValues;
6483 SmallVector<EVT, 4> ValueVTs;
6484 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6485 unsigned NumValues = ValueVTs.size();
6487 // If this argument is unused then remember its value. It is used to generate
6488 // debugging information.
6489 if (I->use_empty() && NumValues)
6490 SDB->setUnusedArgValue(I, InVals[i]);
6492 for (unsigned Val = 0; Val != NumValues; ++Val) {
6493 EVT VT = ValueVTs[Val];
6494 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6495 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6497 if (!I->use_empty()) {
6498 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6499 if (F.paramHasAttr(Idx, Attribute::SExt))
6500 AssertOp = ISD::AssertSext;
6501 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6502 AssertOp = ISD::AssertZext;
6504 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6505 NumParts, PartVT, VT,
6512 // We don't need to do anything else for unused arguments.
6513 if (ArgValues.empty())
6516 // Note down frame index for byval arguments.
6517 if (I->hasByValAttr())
6518 if (FrameIndexSDNode *FI =
6519 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6520 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6522 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6523 SDB->getCurDebugLoc());
6524 SDB->setValue(I, Res);
6526 // If this argument is live outside of the entry block, insert a copy from
6527 // wherever we got it to the vreg that other BB's will reference it as.
6528 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6529 // If we can, though, try to skip creating an unnecessary vreg.
6530 // FIXME: This isn't very clean... it would be nice to make this more
6531 // general. It's also subtly incompatible with the hacks FastISel
6533 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6534 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6535 FuncInfo->ValueMap[I] = Reg;
6539 if (!isOnlyUsedInEntryBlock(I)) {
6540 FuncInfo->InitializeRegForValue(I);
6541 SDB->CopyToExportRegsIfNeeded(I);
6545 assert(i == InVals.size() && "Argument register count mismatch!");
6547 // Finally, if the target has anything special to do, allow it to do so.
6548 // FIXME: this should insert code into the DAG!
6549 EmitFunctionEntryCode();
6552 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6553 /// ensure constants are generated when needed. Remember the virtual registers
6554 /// that need to be added to the Machine PHI nodes as input. We cannot just
6555 /// directly add them, because expansion might result in multiple MBB's for one
6556 /// BB. As such, the start of the BB might correspond to a different MBB than
6560 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6561 const TerminatorInst *TI = LLVMBB->getTerminator();
6563 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6565 // Check successor nodes' PHI nodes that expect a constant to be available
6567 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6568 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6569 if (!isa<PHINode>(SuccBB->begin())) continue;
6570 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6572 // If this terminator has multiple identical successors (common for
6573 // switches), only handle each succ once.
6574 if (!SuccsHandled.insert(SuccMBB)) continue;
6576 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6578 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6579 // nodes and Machine PHI nodes, but the incoming operands have not been
6581 for (BasicBlock::const_iterator I = SuccBB->begin();
6582 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6583 // Ignore dead phi's.
6584 if (PN->use_empty()) continue;
6587 if (PN->getType()->isEmptyTy())
6591 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6593 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6594 unsigned &RegOut = ConstantsOut[C];
6596 RegOut = FuncInfo.CreateRegs(C->getType());
6597 CopyValueToVirtualRegister(C, RegOut);
6601 DenseMap<const Value *, unsigned>::iterator I =
6602 FuncInfo.ValueMap.find(PHIOp);
6603 if (I != FuncInfo.ValueMap.end())
6606 assert(isa<AllocaInst>(PHIOp) &&
6607 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6608 "Didn't codegen value into a register!??");
6609 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6610 CopyValueToVirtualRegister(PHIOp, Reg);
6614 // Remember that this register needs to added to the machine PHI node as
6615 // the input for this MBB.
6616 SmallVector<EVT, 4> ValueVTs;
6617 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6618 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6619 EVT VT = ValueVTs[vti];
6620 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6621 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6622 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6623 Reg += NumRegisters;
6627 ConstantsOut.clear();