1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert(PartVT.isInteger() && ValueVT.isInteger() &&
357 "Unknown mismatch!");
358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 } else if (PartBits == ValueVT.getSizeInBits()) {
362 // Different types of the same size.
363 assert(NumParts == 1 && PartVT != ValueVT);
364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
366 // If the parts cover less bits than value has, truncate the value.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Unknown mismatch!");
369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
373 // The value may have changed - recompute ValueVT.
374 ValueVT = Val.getValueType();
375 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
376 "Failed to tile the value with PartVT!");
379 assert(PartVT == ValueVT && "Type conversion failed!");
384 // Expand the value into multiple parts.
385 if (NumParts & (NumParts - 1)) {
386 // The number of parts is not a power of 2. Split off and copy the tail.
387 assert(PartVT.isInteger() && ValueVT.isInteger() &&
388 "Do not know what to expand to!");
389 unsigned RoundParts = 1 << Log2_32(NumParts);
390 unsigned RoundBits = RoundParts * PartBits;
391 unsigned OddParts = NumParts - RoundParts;
392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
393 DAG.getIntPtrConstant(RoundBits));
394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
396 if (TLI.isBigEndian())
397 // The odd parts were reversed by getCopyToParts - unreverse them.
398 std::reverse(Parts + RoundParts, Parts + NumParts);
400 NumParts = RoundParts;
401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 // The number of parts is a power of 2. Repeatedly bisect the value using
407 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
408 EVT::getIntegerVT(*DAG.getContext(),
409 ValueVT.getSizeInBits()),
412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
413 for (unsigned i = 0; i < NumParts; i += StepSize) {
414 unsigned ThisBits = StepSize * PartBits / 2;
415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
416 SDValue &Part0 = Parts[i];
417 SDValue &Part1 = Parts[i+StepSize/2];
419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
420 ThisVT, Part0, DAG.getIntPtrConstant(1));
421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
422 ThisVT, Part0, DAG.getIntPtrConstant(0));
424 if (ThisBits == PartBits && ThisVT != PartVT) {
425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
431 if (TLI.isBigEndian())
432 std::reverse(Parts, Parts + OrigNumParts);
436 /// getCopyToPartsVector - Create a series of nodes that contain the specified
437 /// value split into legal parts.
438 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
439 SDValue Val, SDValue *Parts, unsigned NumParts,
441 EVT ValueVT = Val.getValueType();
442 assert(ValueVT.isVector() && "Not a vector");
443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
446 if (PartVT == ValueVT) {
448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
449 // Bitconvert vector->vector case.
450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
451 } else if (PartVT.isVector() &&
452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
454 EVT ElementVT = PartVT.getVectorElementType();
455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
457 SmallVector<SDValue, 16> Ops;
458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
460 ElementVT, Val, DAG.getIntPtrConstant(i)));
462 for (unsigned i = ValueVT.getVectorNumElements(),
463 e = PartVT.getVectorNumElements(); i != e; ++i)
464 Ops.push_back(DAG.getUNDEF(ElementVT));
466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
468 // FIXME: Use CONCAT for 2x -> 4x.
470 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
472 } else if (PartVT.isVector() &&
473 PartVT.getVectorElementType().bitsGE(
474 ValueVT.getVectorElementType()) &&
475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
477 // Promoted vector extract
478 bool Smaller = PartVT.bitsLE(ValueVT);
479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
482 // Vector -> scalar conversion.
483 assert(ValueVT.getVectorNumElements() == 1 &&
484 "Only trivial vector-to-scalar conversions should get here!");
485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 PartVT, Val, DAG.getIntPtrConstant(0));
488 bool Smaller = ValueVT.bitsLE(PartVT);
489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
497 // Handle a multi-element vector.
498 EVT IntermediateVT, RegisterVT;
499 unsigned NumIntermediates;
500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
502 NumIntermediates, RegisterVT);
503 unsigned NumElements = ValueVT.getVectorNumElements();
505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
506 NumParts = NumRegs; // Silence a compiler warning.
507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
509 // Split the vector into intermediate operands.
510 SmallVector<SDValue, 8> Ops(NumIntermediates);
511 for (unsigned i = 0; i != NumIntermediates; ++i) {
512 if (IntermediateVT.isVector())
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 IntermediateVT, Val, DAG.getIntPtrConstant(i));
521 // Split the intermediate operands into legal parts.
522 if (NumParts == NumIntermediates) {
523 // If the register was not expanded, promote or copy the value,
525 for (unsigned i = 0; i != NumParts; ++i)
526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
527 } else if (NumParts > 0) {
528 // If the intermediate type was expanded, split each the value into
530 assert(NumParts % NumIntermediates == 0 &&
531 "Must expand into a divisible number of parts!");
532 unsigned Factor = NumParts / NumIntermediates;
533 for (unsigned i = 0; i != NumIntermediates; ++i)
534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
542 /// RegsForValue - This struct represents the registers (physical or virtual)
543 /// that a particular set of values is assigned, and the type information
544 /// about the value. The most common situation is to represent one value at a
545 /// time, but struct or array values are handled element-wise as multiple
546 /// values. The splitting of aggregates is performed recursively, so that we
547 /// never have aggregate-typed registers. The values at this point do not
548 /// necessarily have legal types, so each value may require one or more
549 /// registers of some legal type.
551 struct RegsForValue {
552 /// ValueVTs - The value types of the values, which may not be legal, and
553 /// may need be promoted or synthesized from one or more registers.
555 SmallVector<EVT, 4> ValueVTs;
557 /// RegVTs - The value types of the registers. This is the same size as
558 /// ValueVTs and it records, for each value, what the type of the assigned
559 /// register or registers are. (Individual values are never synthesized
560 /// from more than one type of register.)
562 /// With virtual registers, the contents of RegVTs is redundant with TLI's
563 /// getRegisterType member function, however when with physical registers
564 /// it is necessary to have a separate record of the types.
566 SmallVector<EVT, 4> RegVTs;
568 /// Regs - This list holds the registers assigned to the values.
569 /// Each legal or promoted value requires one register, and each
570 /// expanded value requires multiple registers.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> ®s,
577 EVT regvt, EVT valuevt)
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
580 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
581 unsigned Reg, Type *Ty) {
582 ComputeValueVTs(tli, Ty, ValueVTs);
584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
585 EVT ValueVT = ValueVTs[Value];
586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
588 for (unsigned i = 0; i != NumRegs; ++i)
589 Regs.push_back(Reg + i);
590 RegVTs.push_back(RegisterVT);
595 /// areValueTypesLegal - Return true if types of all the values are legal.
596 bool areValueTypesLegal(const TargetLowering &TLI) {
597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
598 EVT RegisterVT = RegVTs[Value];
599 if (!TLI.isTypeLegal(RegisterVT))
605 /// append - Add the specified values to this one.
606 void append(const RegsForValue &RHS) {
607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
613 /// this value and returns the result as a ValueVTs value. This uses
614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
615 /// If the Flag pointer is NULL, no flag is used.
616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
618 SDValue &Chain, SDValue *Flag) const;
620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
621 /// specified value into the registers specified by this object. This uses
622 /// Chain/Flag as the input and updates them for the output Chain/Flag.
623 /// If the Flag pointer is NULL, no flag is used.
624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
625 SDValue &Chain, SDValue *Flag) const;
627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
628 /// operand list. This adds the code marker, matching input operand index
629 /// (if applicable), and includes the number of values added into it.
630 void AddInlineAsmOperands(unsigned Kind,
631 bool HasMatching, unsigned MatchingIdx,
633 std::vector<SDValue> &Ops) const;
637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
638 /// this value and returns the result as a ValueVT value. This uses
639 /// Chain/Flag as the input and updates them for the output Chain/Flag.
640 /// If the Flag pointer is NULL, no flag is used.
641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
642 FunctionLoweringInfo &FuncInfo,
644 SDValue &Chain, SDValue *Flag) const {
645 // A Value with type {} or [0 x %t] needs no registers.
646 if (ValueVTs.empty())
649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
651 // Assemble the legal parts into the final values.
652 SmallVector<SDValue, 4> Values(ValueVTs.size());
653 SmallVector<SDValue, 8> Parts;
654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
655 // Copy the legal parts from the registers.
656 EVT ValueVT = ValueVTs[Value];
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
658 EVT RegisterVT = RegVTs[Value];
660 Parts.resize(NumRegs);
661 for (unsigned i = 0; i != NumRegs; ++i) {
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
667 *Flag = P.getValue(2);
670 Chain = P.getValue(1);
673 // If the source register was virtual and if we know something about it,
674 // add an assert node.
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
676 !RegisterVT.isInteger() || RegisterVT.isVector())
679 const FunctionLoweringInfo::LiveOutInfo *LOI =
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
684 unsigned RegSize = RegisterVT.getSizeInBits();
685 unsigned NumSignBits = LOI->NumSignBits;
686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
688 // FIXME: We capture more information than the dag can represent. For
689 // now, just use the tightest assertzext/assertsext possible.
691 EVT FromVT(MVT::Other);
692 if (NumSignBits == RegSize)
693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
694 else if (NumZeroBits >= RegSize-1)
695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
696 else if (NumSignBits > RegSize-8)
697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
698 else if (NumZeroBits >= RegSize-8)
699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
700 else if (NumSignBits > RegSize-16)
701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
702 else if (NumZeroBits >= RegSize-16)
703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
704 else if (NumSignBits > RegSize-32)
705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
706 else if (NumZeroBits >= RegSize-32)
707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
711 // Add an assertion node.
712 assert(FromVT != MVT::Other);
713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
714 RegisterVT, P, DAG.getValueType(FromVT));
717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
718 NumRegs, RegisterVT, ValueVT);
723 return DAG.getNode(ISD::MERGE_VALUES, dl,
724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
725 &Values[0], ValueVTs.size());
728 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
729 /// specified value into the registers specified by this object. This uses
730 /// Chain/Flag as the input and updates them for the output Chain/Flag.
731 /// If the Flag pointer is NULL, no flag is used.
732 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
733 SDValue &Chain, SDValue *Flag) const {
734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 // Get the list of the values's legal parts.
737 unsigned NumRegs = Regs.size();
738 SmallVector<SDValue, 8> Parts(NumRegs);
739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
740 EVT ValueVT = ValueVTs[Value];
741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
742 EVT RegisterVT = RegVTs[Value];
744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
745 &Parts[Part], NumParts, RegisterVT);
749 // Copy the parts into the registers.
750 SmallVector<SDValue, 8> Chains(NumRegs);
751 for (unsigned i = 0; i != NumRegs; ++i) {
754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
757 *Flag = Part.getValue(1);
760 Chains[i] = Part.getValue(0);
763 if (NumRegs == 1 || Flag)
764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
765 // flagged to it. That is the CopyToReg nodes and the user are considered
766 // a single scheduling unit. If we create a TokenFactor and return it as
767 // chain, then the TokenFactor is both a predecessor (operand) of the
768 // user as well as a successor (the TF operands are flagged to the user).
769 // c1, f1 = CopyToReg
770 // c2, f2 = CopyToReg
771 // c3 = TokenFactor c1, c2
774 Chain = Chains[NumRegs-1];
776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
779 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
780 /// operand list. This adds the code marker and includes the number of
781 /// values added into it.
782 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
783 unsigned MatchingIdx,
785 std::vector<SDValue> &Ops) const {
786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
796 EVT RegisterVT = RegVTs[Value];
797 for (unsigned i = 0; i != NumRegs; ++i) {
798 assert(Reg < Regs.size() && "Mismatch in # registers expected");
799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
804 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
807 TD = DAG.getTarget().getTargetData();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
821 CurDebugLoc = DebugLoc();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is seperated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
853 &PendingLoads[0], PendingLoads.size());
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
884 PendingExports.size());
885 PendingExports.clear();
890 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
892 DAG.AssignOrdering(Node, SDNodeOrder);
894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
895 AssignOrderingToNode(Node->getOperand(I).getNode());
898 void SelectionDAGBuilder::visit(const Instruction &I) {
899 // Set up outgoing PHI node register values before emitting the terminator.
900 if (isa<TerminatorInst>(&I))
901 HandlePHINodesInSuccessorBlocks(I.getParent());
903 CurDebugLoc = I.getDebugLoc();
905 visit(I.getOpcode(), I);
907 if (!isa<TerminatorInst>(&I) && !HasTailCall)
908 CopyToExportRegsIfNeeded(&I);
910 CurDebugLoc = DebugLoc();
913 void SelectionDAGBuilder::visitPHI(const PHINode &) {
914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
917 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
918 // Note: this doesn't use InstVisitor, because it has to work with
919 // ConstantExpr's in addition to instructions.
921 default: llvm_unreachable("Unknown instruction type encountered!");
922 // Build the switch statement using the Instruction.def file.
923 #define HANDLE_INST(NUM, OPCODE, CLASS) \
924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
925 #include "llvm/Instruction.def"
928 // Assign the ordering to the freshly created DAG nodes.
929 if (NodeMap.count(&I)) {
931 AssignOrderingToNode(getValue(&I).getNode());
935 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
936 // generate the debug data structures now that we've seen its definition.
937 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
941 const DbgValueInst *DI = DDI.getDI();
942 DebugLoc dl = DDI.getdl();
943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
944 MDNode *Variable = DI->getVariable();
945 uint64_t Offset = DI->getOffset();
948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
949 SDV = DAG.getDbgValue(Variable, Val.getNode(),
950 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
951 DAG.AddDbgValue(SDV, Val.getNode(), false);
954 DEBUG(dbgs() << "Dropping debug info for " << DI);
955 DanglingDebugInfoMap[V] = DanglingDebugInfo();
959 // getValue - Return an SDValue for the given Value.
960 SDValue SelectionDAGBuilder::getValue(const Value *V) {
961 // If we already have an SDValue for this value, use it. It's important
962 // to do this first, so that we don't create a CopyFromReg if we already
963 // have a regular SDValue.
964 SDValue &N = NodeMap[V];
965 if (N.getNode()) return N;
967 // If there's a virtual register allocated and initialized for this
969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
970 if (It != FuncInfo.ValueMap.end()) {
971 unsigned InReg = It->second;
972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
973 SDValue Chain = DAG.getEntryNode();
974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
975 resolveDanglingDebugInfo(V, N);
979 // Otherwise create a new SDValue and remember it.
980 SDValue Val = getValueImpl(V);
982 resolveDanglingDebugInfo(V, Val);
986 /// getNonRegisterValue - Return an SDValue for the given Value, but
987 /// don't look in FuncInfo.ValueMap for a virtual register.
988 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
989 // If we already have an SDValue for this value, use it.
990 SDValue &N = NodeMap[V];
991 if (N.getNode()) return N;
993 // Otherwise create a new SDValue and remember it.
994 SDValue Val = getValueImpl(V);
996 resolveDanglingDebugInfo(V, Val);
1000 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1001 /// Create an SDValue for the given value.
1002 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1003 if (const Constant *C = dyn_cast<Constant>(V)) {
1004 EVT VT = TLI.getValueType(V->getType(), true);
1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1007 return DAG.getConstant(*CI, VT);
1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1012 if (isa<ConstantPointerNull>(C))
1013 return DAG.getConstant(0, TLI.getPointerTy());
1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1016 return DAG.getConstantFP(*CFP, VT);
1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1019 return DAG.getUNDEF(VT);
1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1022 visit(CE->getOpcode(), *CE);
1023 SDValue N1 = NodeMap[V];
1024 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1029 SmallVector<SDValue, 4> Constants;
1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1032 SDNode *Val = getValue(*OI).getNode();
1033 // If the operand is an empty aggregate, there are no values.
1035 // Add each leaf value from the operand to the Constants list
1036 // to form a flattened list of all the values.
1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1038 Constants.push_back(SDValue(Val, i));
1041 return DAG.getMergeValues(&Constants[0], Constants.size(),
1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1047 "Unknown struct or array constant!");
1049 SmallVector<EVT, 4> ValueVTs;
1050 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1051 unsigned NumElts = ValueVTs.size();
1053 return SDValue(); // empty struct
1054 SmallVector<SDValue, 4> Constants(NumElts);
1055 for (unsigned i = 0; i != NumElts; ++i) {
1056 EVT EltVT = ValueVTs[i];
1057 if (isa<UndefValue>(C))
1058 Constants[i] = DAG.getUNDEF(EltVT);
1059 else if (EltVT.isFloatingPoint())
1060 Constants[i] = DAG.getConstantFP(0, EltVT);
1062 Constants[i] = DAG.getConstant(0, EltVT);
1065 return DAG.getMergeValues(&Constants[0], NumElts,
1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1070 return DAG.getBlockAddress(BA, VT);
1072 VectorType *VecTy = cast<VectorType>(V->getType());
1073 unsigned NumElements = VecTy->getNumElements();
1075 // Now that we know the number and type of the elements, get that number of
1076 // elements into the Ops array based on what kind of constant it is.
1077 SmallVector<SDValue, 16> Ops;
1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1079 for (unsigned i = 0; i != NumElements; ++i)
1080 Ops.push_back(getValue(CP->getOperand(i)));
1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1083 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1086 if (EltVT.isFloatingPoint())
1087 Op = DAG.getConstantFP(0, EltVT);
1089 Op = DAG.getConstant(0, EltVT);
1090 Ops.assign(NumElements, Op);
1093 // Create a BUILD_VECTOR node.
1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1095 VT, &Ops[0], Ops.size());
1098 // If this is a static alloca, generate it as the frameindex instead of
1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1101 DenseMap<const AllocaInst*, int>::iterator SI =
1102 FuncInfo.StaticAllocaMap.find(AI);
1103 if (SI != FuncInfo.StaticAllocaMap.end())
1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1107 // If this is an instruction which fast-isel has deferred, select it now.
1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1111 SDValue Chain = DAG.getEntryNode();
1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1115 llvm_unreachable("Can't get register for value!");
1119 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1120 SDValue Chain = getControlRoot();
1121 SmallVector<ISD::OutputArg, 8> Outs;
1122 SmallVector<SDValue, 8> OutVals;
1124 if (!FuncInfo.CanLowerReturn) {
1125 unsigned DemoteReg = FuncInfo.DemoteRegister;
1126 const Function *F = I.getParent()->getParent();
1128 // Emit a store of the return value through the virtual register.
1129 // Leave Outs empty so that LowerReturn won't try to load return
1130 // registers the usual way.
1131 SmallVector<EVT, 1> PtrValueVTs;
1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1136 SDValue RetOp = getValue(I.getOperand(0));
1138 SmallVector<EVT, 4> ValueVTs;
1139 SmallVector<uint64_t, 4> Offsets;
1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1141 unsigned NumValues = ValueVTs.size();
1143 SmallVector<SDValue, 4> Chains(NumValues);
1144 for (unsigned i = 0; i != NumValues; ++i) {
1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1146 RetPtr.getValueType(), RetPtr,
1147 DAG.getIntPtrConstant(Offsets[i]));
1149 DAG.getStore(Chain, getCurDebugLoc(),
1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1151 // FIXME: better loc info would be nice.
1152 Add, MachinePointerInfo(), false, false, 0);
1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1156 MVT::Other, &Chains[0], NumValues);
1157 } else if (I.getNumOperands() != 0) {
1158 SmallVector<EVT, 4> ValueVTs;
1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1160 unsigned NumValues = ValueVTs.size();
1162 SDValue RetOp = getValue(I.getOperand(0));
1163 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1164 EVT VT = ValueVTs[j];
1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1168 const Function *F = I.getParent()->getParent();
1169 if (F->paramHasAttr(0, Attribute::SExt))
1170 ExtendKind = ISD::SIGN_EXTEND;
1171 else if (F->paramHasAttr(0, Attribute::ZExt))
1172 ExtendKind = ISD::ZERO_EXTEND;
1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1179 SmallVector<SDValue, 4> Parts(NumParts);
1180 getCopyToParts(DAG, getCurDebugLoc(),
1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1182 &Parts[0], NumParts, PartVT, ExtendKind);
1184 // 'inreg' on function refers to return value
1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1186 if (F->paramHasAttr(0, Attribute::InReg))
1189 // Propagate extension type if any
1190 if (ExtendKind == ISD::SIGN_EXTEND)
1192 else if (ExtendKind == ISD::ZERO_EXTEND)
1195 for (unsigned i = 0; i < NumParts; ++i) {
1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1198 OutVals.push_back(Parts[i]);
1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1205 CallingConv::ID CallConv =
1206 DAG.getMachineFunction().getFunction()->getCallingConv();
1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1208 Outs, OutVals, getCurDebugLoc(), DAG);
1210 // Verify that the target's LowerReturn behaved as expected.
1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1212 "LowerReturn didn't return a valid chain!");
1214 // Update the DAG with the new chain value resulting from return lowering.
1218 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1219 /// created for it, emit nodes to copy the value into the virtual
1221 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1223 if (V->getType()->isEmptyTy())
1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1227 if (VMI != FuncInfo.ValueMap.end()) {
1228 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1229 CopyValueToVirtualRegister(V, VMI->second);
1233 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1234 /// the current basic block, add it to ValueMap now so that we'll get a
1236 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1237 // No need to export constants.
1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1240 // Already exported?
1241 if (FuncInfo.isExportedInst(V)) return;
1243 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1244 CopyValueToVirtualRegister(V, Reg);
1247 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1248 const BasicBlock *FromBB) {
1249 // The operands of the setcc have to be in this block. We don't know
1250 // how to export them from some other block.
1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1252 // Can export from current BB.
1253 if (VI->getParent() == FromBB)
1256 // Is already exported, noop.
1257 return FuncInfo.isExportedInst(V);
1260 // If this is an argument, we can export it if the BB is the entry block or
1261 // if it is already exported.
1262 if (isa<Argument>(V)) {
1263 if (FromBB == &FromBB->getParent()->getEntryBlock())
1266 // Otherwise, can only export this if it is already exported.
1267 return FuncInfo.isExportedInst(V);
1270 // Otherwise, constants can always be exported.
1274 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1275 uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src,
1276 MachineBasicBlock *Dst) {
1277 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1280 BasicBlock *SrcBB = const_cast<BasicBlock*>(Src->getBasicBlock());
1281 BasicBlock *DstBB = const_cast<BasicBlock*>(Dst->getBasicBlock());
1282 return BPI->getEdgeWeight(SrcBB, DstBB);
1285 void SelectionDAGBuilder::addSuccessorWithWeight(MachineBasicBlock *Src,
1286 MachineBasicBlock *Dst) {
1287 uint32_t weight = getEdgeWeight(Src, Dst);
1288 Src->addSuccessor(Dst, weight);
1292 static bool InBlock(const Value *V, const BasicBlock *BB) {
1293 if (const Instruction *I = dyn_cast<Instruction>(V))
1294 return I->getParent() == BB;
1298 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1299 /// This function emits a branch and is used at the leaves of an OR or an
1300 /// AND operator tree.
1303 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1304 MachineBasicBlock *TBB,
1305 MachineBasicBlock *FBB,
1306 MachineBasicBlock *CurBB,
1307 MachineBasicBlock *SwitchBB) {
1308 const BasicBlock *BB = CurBB->getBasicBlock();
1310 // If the leaf of the tree is a comparison, merge the condition into
1312 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1313 // The operands of the cmp have to be in this block. We don't know
1314 // how to export them from some other block. If this is the first block
1315 // of the sequence, no exporting is needed.
1316 if (CurBB == SwitchBB ||
1317 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1318 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1319 ISD::CondCode Condition;
1320 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1321 Condition = getICmpCondCode(IC->getPredicate());
1322 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1323 Condition = getFCmpCondCode(FC->getPredicate());
1325 Condition = ISD::SETEQ; // silence warning.
1326 llvm_unreachable("Unknown compare instruction");
1329 CaseBlock CB(Condition, BOp->getOperand(0),
1330 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1331 SwitchCases.push_back(CB);
1336 // Create a CaseBlock record representing this branch.
1337 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1338 NULL, TBB, FBB, CurBB);
1339 SwitchCases.push_back(CB);
1342 /// FindMergedConditions - If Cond is an expression like
1343 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1344 MachineBasicBlock *TBB,
1345 MachineBasicBlock *FBB,
1346 MachineBasicBlock *CurBB,
1347 MachineBasicBlock *SwitchBB,
1349 // If this node is not part of the or/and tree, emit it as a branch.
1350 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1351 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1352 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1353 BOp->getParent() != CurBB->getBasicBlock() ||
1354 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1355 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1356 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1360 // Create TmpBB after CurBB.
1361 MachineFunction::iterator BBI = CurBB;
1362 MachineFunction &MF = DAG.getMachineFunction();
1363 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1364 CurBB->getParent()->insert(++BBI, TmpBB);
1366 if (Opc == Instruction::Or) {
1367 // Codegen X | Y as:
1375 // Emit the LHS condition.
1376 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1378 // Emit the RHS condition into TmpBB.
1379 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1381 assert(Opc == Instruction::And && "Unknown merge op!");
1382 // Codegen X & Y as:
1389 // This requires creation of TmpBB after CurBB.
1391 // Emit the LHS condition.
1392 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1394 // Emit the RHS condition into TmpBB.
1395 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1399 /// If the set of cases should be emitted as a series of branches, return true.
1400 /// If we should emit this as a bunch of and/or'd together conditions, return
1403 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1404 if (Cases.size() != 2) return true;
1406 // If this is two comparisons of the same values or'd or and'd together, they
1407 // will get folded into a single comparison, so don't emit two blocks.
1408 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1409 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1410 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1411 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1415 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1416 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1417 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1418 Cases[0].CC == Cases[1].CC &&
1419 isa<Constant>(Cases[0].CmpRHS) &&
1420 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1421 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1430 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1431 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1433 // Update machine-CFG edges.
1434 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1436 // Figure out which block is immediately after the current one.
1437 MachineBasicBlock *NextBlock = 0;
1438 MachineFunction::iterator BBI = BrMBB;
1439 if (++BBI != FuncInfo.MF->end())
1442 if (I.isUnconditional()) {
1443 // Update machine-CFG edges.
1444 BrMBB->addSuccessor(Succ0MBB);
1446 // If this is not a fall-through branch, emit the branch.
1447 if (Succ0MBB != NextBlock)
1448 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1449 MVT::Other, getControlRoot(),
1450 DAG.getBasicBlock(Succ0MBB)));
1455 // If this condition is one of the special cases we handle, do special stuff
1457 const Value *CondVal = I.getCondition();
1458 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1460 // If this is a series of conditions that are or'd or and'd together, emit
1461 // this as a sequence of branches instead of setcc's with and/or operations.
1462 // As long as jumps are not expensive, this should improve performance.
1463 // For example, instead of something like:
1476 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1477 if (!TLI.isJumpExpensive() &&
1479 (BOp->getOpcode() == Instruction::And ||
1480 BOp->getOpcode() == Instruction::Or)) {
1481 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1483 // If the compares in later blocks need to use values not currently
1484 // exported from this block, export them now. This block should always
1485 // be the first entry.
1486 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1488 // Allow some cases to be rejected.
1489 if (ShouldEmitAsBranches(SwitchCases)) {
1490 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1491 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1492 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1495 // Emit the branch for this block.
1496 visitSwitchCase(SwitchCases[0], BrMBB);
1497 SwitchCases.erase(SwitchCases.begin());
1501 // Okay, we decided not to do this, remove any inserted MBB's and clear
1503 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1504 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1506 SwitchCases.clear();
1510 // Create a CaseBlock record representing this branch.
1511 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1512 NULL, Succ0MBB, Succ1MBB, BrMBB);
1514 // Use visitSwitchCase to actually insert the fast branch sequence for this
1516 visitSwitchCase(CB, BrMBB);
1519 /// visitSwitchCase - Emits the necessary code to represent a single node in
1520 /// the binary search tree resulting from lowering a switch instruction.
1521 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1522 MachineBasicBlock *SwitchBB) {
1524 SDValue CondLHS = getValue(CB.CmpLHS);
1525 DebugLoc dl = getCurDebugLoc();
1527 // Build the setcc now.
1528 if (CB.CmpMHS == NULL) {
1529 // Fold "(X == true)" to X and "(X == false)" to !X to
1530 // handle common cases produced by branch lowering.
1531 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1532 CB.CC == ISD::SETEQ)
1534 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1535 CB.CC == ISD::SETEQ) {
1536 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1537 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1539 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1541 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1543 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1544 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1546 SDValue CmpOp = getValue(CB.CmpMHS);
1547 EVT VT = CmpOp.getValueType();
1549 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1550 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1553 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1554 VT, CmpOp, DAG.getConstant(Low, VT));
1555 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1556 DAG.getConstant(High-Low, VT), ISD::SETULE);
1560 // Update successor info
1561 addSuccessorWithWeight(SwitchBB, CB.TrueBB);
1562 addSuccessorWithWeight(SwitchBB, CB.FalseBB);
1564 // Set NextBlock to be the MBB immediately after the current one, if any.
1565 // This is used to avoid emitting unnecessary branches to the next block.
1566 MachineBasicBlock *NextBlock = 0;
1567 MachineFunction::iterator BBI = SwitchBB;
1568 if (++BBI != FuncInfo.MF->end())
1571 // If the lhs block is the next block, invert the condition so that we can
1572 // fall through to the lhs instead of the rhs block.
1573 if (CB.TrueBB == NextBlock) {
1574 std::swap(CB.TrueBB, CB.FalseBB);
1575 SDValue True = DAG.getConstant(1, Cond.getValueType());
1576 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1579 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1580 MVT::Other, getControlRoot(), Cond,
1581 DAG.getBasicBlock(CB.TrueBB));
1583 // Insert the false branch. Do this even if it's a fall through branch,
1584 // this makes it easier to do DAG optimizations which require inverting
1585 // the branch condition.
1586 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1587 DAG.getBasicBlock(CB.FalseBB));
1589 DAG.setRoot(BrCond);
1592 /// visitJumpTable - Emit JumpTable node in the current MBB
1593 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1594 // Emit the code for the jump table
1595 assert(JT.Reg != -1U && "Should lower JT Header first!");
1596 EVT PTy = TLI.getPointerTy();
1597 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1599 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1600 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1601 MVT::Other, Index.getValue(1),
1603 DAG.setRoot(BrJumpTable);
1606 /// visitJumpTableHeader - This function emits necessary code to produce index
1607 /// in the JumpTable from switch case.
1608 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1609 JumpTableHeader &JTH,
1610 MachineBasicBlock *SwitchBB) {
1611 // Subtract the lowest switch case value from the value being switched on and
1612 // conditional branch to default mbb if the result is greater than the
1613 // difference between smallest and largest cases.
1614 SDValue SwitchOp = getValue(JTH.SValue);
1615 EVT VT = SwitchOp.getValueType();
1616 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1617 DAG.getConstant(JTH.First, VT));
1619 // The SDNode we just created, which holds the value being switched on minus
1620 // the smallest case value, needs to be copied to a virtual register so it
1621 // can be used as an index into the jump table in a subsequent basic block.
1622 // This value may be smaller or larger than the target's pointer type, and
1623 // therefore require extension or truncating.
1624 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1626 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1627 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1628 JumpTableReg, SwitchOp);
1629 JT.Reg = JumpTableReg;
1631 // Emit the range check for the jump table, and branch to the default block
1632 // for the switch statement if the value being switched on exceeds the largest
1633 // case in the switch.
1634 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1635 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1636 DAG.getConstant(JTH.Last-JTH.First,VT),
1639 // Set NextBlock to be the MBB immediately after the current one, if any.
1640 // This is used to avoid emitting unnecessary branches to the next block.
1641 MachineBasicBlock *NextBlock = 0;
1642 MachineFunction::iterator BBI = SwitchBB;
1644 if (++BBI != FuncInfo.MF->end())
1647 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1648 MVT::Other, CopyTo, CMP,
1649 DAG.getBasicBlock(JT.Default));
1651 if (JT.MBB != NextBlock)
1652 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1653 DAG.getBasicBlock(JT.MBB));
1655 DAG.setRoot(BrCond);
1658 /// visitBitTestHeader - This function emits necessary code to produce value
1659 /// suitable for "bit tests"
1660 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1661 MachineBasicBlock *SwitchBB) {
1662 // Subtract the minimum value
1663 SDValue SwitchOp = getValue(B.SValue);
1664 EVT VT = SwitchOp.getValueType();
1665 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1666 DAG.getConstant(B.First, VT));
1669 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1670 TLI.getSetCCResultType(Sub.getValueType()),
1671 Sub, DAG.getConstant(B.Range, VT),
1674 // Determine the type of the test operands.
1675 bool UsePtrType = false;
1676 if (!TLI.isTypeLegal(VT))
1679 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1680 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1681 // Switch table case range are encoded into series of masks.
1682 // Just use pointer type, it's guaranteed to fit.
1688 VT = TLI.getPointerTy();
1689 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1693 B.Reg = FuncInfo.CreateReg(VT);
1694 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1697 // Set NextBlock to be the MBB immediately after the current one, if any.
1698 // This is used to avoid emitting unnecessary branches to the next block.
1699 MachineBasicBlock *NextBlock = 0;
1700 MachineFunction::iterator BBI = SwitchBB;
1701 if (++BBI != FuncInfo.MF->end())
1704 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1706 addSuccessorWithWeight(SwitchBB, B.Default);
1707 addSuccessorWithWeight(SwitchBB, MBB);
1709 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1710 MVT::Other, CopyTo, RangeCmp,
1711 DAG.getBasicBlock(B.Default));
1713 if (MBB != NextBlock)
1714 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1715 DAG.getBasicBlock(MBB));
1717 DAG.setRoot(BrRange);
1720 /// visitBitTestCase - this function produces one "bit test"
1721 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1722 MachineBasicBlock* NextMBB,
1725 MachineBasicBlock *SwitchBB) {
1727 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1730 unsigned PopCount = CountPopulation_64(B.Mask);
1731 if (PopCount == 1) {
1732 // Testing for a single bit; just compare the shift count with what it
1733 // would need to be to shift a 1 bit in that position.
1734 Cmp = DAG.getSetCC(getCurDebugLoc(),
1735 TLI.getSetCCResultType(VT),
1737 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1739 } else if (PopCount == BB.Range) {
1740 // There is only one zero bit in the range, test for it directly.
1741 Cmp = DAG.getSetCC(getCurDebugLoc(),
1742 TLI.getSetCCResultType(VT),
1744 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1747 // Make desired shift
1748 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1749 DAG.getConstant(1, VT), ShiftOp);
1751 // Emit bit tests and jumps
1752 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1753 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1754 Cmp = DAG.getSetCC(getCurDebugLoc(),
1755 TLI.getSetCCResultType(VT),
1756 AndOp, DAG.getConstant(0, VT),
1760 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1761 addSuccessorWithWeight(SwitchBB, NextMBB);
1763 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1764 MVT::Other, getControlRoot(),
1765 Cmp, DAG.getBasicBlock(B.TargetBB));
1767 // Set NextBlock to be the MBB immediately after the current one, if any.
1768 // This is used to avoid emitting unnecessary branches to the next block.
1769 MachineBasicBlock *NextBlock = 0;
1770 MachineFunction::iterator BBI = SwitchBB;
1771 if (++BBI != FuncInfo.MF->end())
1774 if (NextMBB != NextBlock)
1775 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1776 DAG.getBasicBlock(NextMBB));
1781 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1782 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1784 // Retrieve successors.
1785 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1786 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1788 const Value *Callee(I.getCalledValue());
1789 if (isa<InlineAsm>(Callee))
1792 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1794 // If the value of the invoke is used outside of its defining block, make it
1795 // available as a virtual register.
1796 CopyToExportRegsIfNeeded(&I);
1798 // Update successor info
1799 InvokeMBB->addSuccessor(Return);
1800 InvokeMBB->addSuccessor(LandingPad);
1802 // Drop into normal successor.
1803 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1804 MVT::Other, getControlRoot(),
1805 DAG.getBasicBlock(Return)));
1808 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1811 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1812 /// small case ranges).
1813 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1814 CaseRecVector& WorkList,
1816 MachineBasicBlock *Default,
1817 MachineBasicBlock *SwitchBB) {
1818 Case& BackCase = *(CR.Range.second-1);
1820 // Size is the number of Cases represented by this range.
1821 size_t Size = CR.Range.second - CR.Range.first;
1825 // Get the MachineFunction which holds the current MBB. This is used when
1826 // inserting any additional MBBs necessary to represent the switch.
1827 MachineFunction *CurMF = FuncInfo.MF;
1829 // Figure out which block is immediately after the current one.
1830 MachineBasicBlock *NextBlock = 0;
1831 MachineFunction::iterator BBI = CR.CaseBB;
1833 if (++BBI != FuncInfo.MF->end())
1836 // If any two of the cases has the same destination, and if one value
1837 // is the same as the other, but has one bit unset that the other has set,
1838 // use bit manipulation to do two compares at once. For example:
1839 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1840 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1841 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1842 if (Size == 2 && CR.CaseBB == SwitchBB) {
1843 Case &Small = *CR.Range.first;
1844 Case &Big = *(CR.Range.second-1);
1846 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1847 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1848 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1850 // Check that there is only one bit different.
1851 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1852 (SmallValue | BigValue) == BigValue) {
1853 // Isolate the common bit.
1854 APInt CommonBit = BigValue & ~SmallValue;
1855 assert((SmallValue | CommonBit) == BigValue &&
1856 CommonBit.countPopulation() == 1 && "Not a common bit?");
1858 SDValue CondLHS = getValue(SV);
1859 EVT VT = CondLHS.getValueType();
1860 DebugLoc DL = getCurDebugLoc();
1862 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1863 DAG.getConstant(CommonBit, VT));
1864 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1865 Or, DAG.getConstant(BigValue, VT),
1868 // Update successor info.
1869 SwitchBB->addSuccessor(Small.BB);
1870 SwitchBB->addSuccessor(Default);
1872 // Insert the true branch.
1873 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1874 getControlRoot(), Cond,
1875 DAG.getBasicBlock(Small.BB));
1877 // Insert the false branch.
1878 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1879 DAG.getBasicBlock(Default));
1881 DAG.setRoot(BrCond);
1887 // Rearrange the case blocks so that the last one falls through if possible.
1888 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1889 // The last case block won't fall through into 'NextBlock' if we emit the
1890 // branches in this order. See if rearranging a case value would help.
1891 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1892 if (I->BB == NextBlock) {
1893 std::swap(*I, BackCase);
1899 // Create a CaseBlock record representing a conditional branch to
1900 // the Case's target mbb if the value being switched on SV is equal
1902 MachineBasicBlock *CurBlock = CR.CaseBB;
1903 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1904 MachineBasicBlock *FallThrough;
1906 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1907 CurMF->insert(BBI, FallThrough);
1909 // Put SV in a virtual register to make it available from the new blocks.
1910 ExportFromCurrentBlock(SV);
1912 // If the last case doesn't match, go to the default block.
1913 FallThrough = Default;
1916 const Value *RHS, *LHS, *MHS;
1918 if (I->High == I->Low) {
1919 // This is just small small case range :) containing exactly 1 case
1921 LHS = SV; RHS = I->High; MHS = NULL;
1924 LHS = I->Low; MHS = SV; RHS = I->High;
1926 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1928 // If emitting the first comparison, just call visitSwitchCase to emit the
1929 // code into the current block. Otherwise, push the CaseBlock onto the
1930 // vector to be later processed by SDISel, and insert the node's MBB
1931 // before the next MBB.
1932 if (CurBlock == SwitchBB)
1933 visitSwitchCase(CB, SwitchBB);
1935 SwitchCases.push_back(CB);
1937 CurBlock = FallThrough;
1943 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1944 return !DisableJumpTables &&
1945 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1946 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1949 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1950 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1951 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1952 return (LastExt - FirstExt + 1ULL);
1955 /// handleJTSwitchCase - Emit jumptable for current switch case range
1956 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1957 CaseRecVector& WorkList,
1959 MachineBasicBlock* Default,
1960 MachineBasicBlock *SwitchBB) {
1961 Case& FrontCase = *CR.Range.first;
1962 Case& BackCase = *(CR.Range.second-1);
1964 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1965 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1967 APInt TSize(First.getBitWidth(), 0);
1968 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1972 if (!areJTsAllowed(TLI) || TSize.ult(4))
1975 APInt Range = ComputeRange(First, Last);
1976 double Density = TSize.roundToDouble() / Range.roundToDouble();
1980 DEBUG(dbgs() << "Lowering jump table\n"
1981 << "First entry: " << First << ". Last entry: " << Last << '\n'
1982 << "Range: " << Range
1983 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1985 // Get the MachineFunction which holds the current MBB. This is used when
1986 // inserting any additional MBBs necessary to represent the switch.
1987 MachineFunction *CurMF = FuncInfo.MF;
1989 // Figure out which block is immediately after the current one.
1990 MachineFunction::iterator BBI = CR.CaseBB;
1993 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1995 // Create a new basic block to hold the code for loading the address
1996 // of the jump table, and jumping to it. Update successor information;
1997 // we will either branch to the default case for the switch, or the jump
1999 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2000 CurMF->insert(BBI, JumpTableBB);
2002 addSuccessorWithWeight(CR.CaseBB, Default);
2003 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2005 // Build a vector of destination BBs, corresponding to each target
2006 // of the jump table. If the value of the jump table slot corresponds to
2007 // a case statement, push the case's BB onto the vector, otherwise, push
2009 std::vector<MachineBasicBlock*> DestBBs;
2011 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2012 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2013 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2015 if (Low.sle(TEI) && TEI.sle(High)) {
2016 DestBBs.push_back(I->BB);
2020 DestBBs.push_back(Default);
2024 // Update successor info. Add one edge to each unique successor.
2025 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2026 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2027 E = DestBBs.end(); I != E; ++I) {
2028 if (!SuccsHandled[(*I)->getNumber()]) {
2029 SuccsHandled[(*I)->getNumber()] = true;
2030 addSuccessorWithWeight(JumpTableBB, *I);
2034 // Create a jump table index for this jump table.
2035 unsigned JTEncoding = TLI.getJumpTableEncoding();
2036 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2037 ->createJumpTableIndex(DestBBs);
2039 // Set the jump table information so that we can codegen it as a second
2040 // MachineBasicBlock
2041 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2042 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2043 if (CR.CaseBB == SwitchBB)
2044 visitJumpTableHeader(JT, JTH, SwitchBB);
2046 JTCases.push_back(JumpTableBlock(JTH, JT));
2051 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2053 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2054 CaseRecVector& WorkList,
2056 MachineBasicBlock *Default,
2057 MachineBasicBlock *SwitchBB) {
2058 // Get the MachineFunction which holds the current MBB. This is used when
2059 // inserting any additional MBBs necessary to represent the switch.
2060 MachineFunction *CurMF = FuncInfo.MF;
2062 // Figure out which block is immediately after the current one.
2063 MachineFunction::iterator BBI = CR.CaseBB;
2066 Case& FrontCase = *CR.Range.first;
2067 Case& BackCase = *(CR.Range.second-1);
2068 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2070 // Size is the number of Cases represented by this range.
2071 unsigned Size = CR.Range.second - CR.Range.first;
2073 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2074 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2076 CaseItr Pivot = CR.Range.first + Size/2;
2078 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2079 // (heuristically) allow us to emit JumpTable's later.
2080 APInt TSize(First.getBitWidth(), 0);
2081 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2085 APInt LSize = FrontCase.size();
2086 APInt RSize = TSize-LSize;
2087 DEBUG(dbgs() << "Selecting best pivot: \n"
2088 << "First: " << First << ", Last: " << Last <<'\n'
2089 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2090 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2092 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2093 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2094 APInt Range = ComputeRange(LEnd, RBegin);
2095 assert((Range - 2ULL).isNonNegative() &&
2096 "Invalid case distance");
2097 // Use volatile double here to avoid excess precision issues on some hosts,
2098 // e.g. that use 80-bit X87 registers.
2099 volatile double LDensity =
2100 (double)LSize.roundToDouble() /
2101 (LEnd - First + 1ULL).roundToDouble();
2102 volatile double RDensity =
2103 (double)RSize.roundToDouble() /
2104 (Last - RBegin + 1ULL).roundToDouble();
2105 double Metric = Range.logBase2()*(LDensity+RDensity);
2106 // Should always split in some non-trivial place
2107 DEBUG(dbgs() <<"=>Step\n"
2108 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2109 << "LDensity: " << LDensity
2110 << ", RDensity: " << RDensity << '\n'
2111 << "Metric: " << Metric << '\n');
2112 if (FMetric < Metric) {
2115 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2121 if (areJTsAllowed(TLI)) {
2122 // If our case is dense we *really* should handle it earlier!
2123 assert((FMetric > 0) && "Should handle dense range earlier!");
2125 Pivot = CR.Range.first + Size/2;
2128 CaseRange LHSR(CR.Range.first, Pivot);
2129 CaseRange RHSR(Pivot, CR.Range.second);
2130 Constant *C = Pivot->Low;
2131 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2133 // We know that we branch to the LHS if the Value being switched on is
2134 // less than the Pivot value, C. We use this to optimize our binary
2135 // tree a bit, by recognizing that if SV is greater than or equal to the
2136 // LHS's Case Value, and that Case Value is exactly one less than the
2137 // Pivot's Value, then we can branch directly to the LHS's Target,
2138 // rather than creating a leaf node for it.
2139 if ((LHSR.second - LHSR.first) == 1 &&
2140 LHSR.first->High == CR.GE &&
2141 cast<ConstantInt>(C)->getValue() ==
2142 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2143 TrueBB = LHSR.first->BB;
2145 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2146 CurMF->insert(BBI, TrueBB);
2147 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2149 // Put SV in a virtual register to make it available from the new blocks.
2150 ExportFromCurrentBlock(SV);
2153 // Similar to the optimization above, if the Value being switched on is
2154 // known to be less than the Constant CR.LT, and the current Case Value
2155 // is CR.LT - 1, then we can branch directly to the target block for
2156 // the current Case Value, rather than emitting a RHS leaf node for it.
2157 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2158 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2159 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2160 FalseBB = RHSR.first->BB;
2162 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2163 CurMF->insert(BBI, FalseBB);
2164 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2166 // Put SV in a virtual register to make it available from the new blocks.
2167 ExportFromCurrentBlock(SV);
2170 // Create a CaseBlock record representing a conditional branch to
2171 // the LHS node if the value being switched on SV is less than C.
2172 // Otherwise, branch to LHS.
2173 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2175 if (CR.CaseBB == SwitchBB)
2176 visitSwitchCase(CB, SwitchBB);
2178 SwitchCases.push_back(CB);
2183 /// handleBitTestsSwitchCase - if current case range has few destination and
2184 /// range span less, than machine word bitwidth, encode case range into series
2185 /// of masks and emit bit tests with these masks.
2186 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2187 CaseRecVector& WorkList,
2189 MachineBasicBlock* Default,
2190 MachineBasicBlock *SwitchBB){
2191 EVT PTy = TLI.getPointerTy();
2192 unsigned IntPtrBits = PTy.getSizeInBits();
2194 Case& FrontCase = *CR.Range.first;
2195 Case& BackCase = *(CR.Range.second-1);
2197 // Get the MachineFunction which holds the current MBB. This is used when
2198 // inserting any additional MBBs necessary to represent the switch.
2199 MachineFunction *CurMF = FuncInfo.MF;
2201 // If target does not have legal shift left, do not emit bit tests at all.
2202 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2206 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2208 // Single case counts one, case range - two.
2209 numCmps += (I->Low == I->High ? 1 : 2);
2212 // Count unique destinations
2213 SmallSet<MachineBasicBlock*, 4> Dests;
2214 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2215 Dests.insert(I->BB);
2216 if (Dests.size() > 3)
2217 // Don't bother the code below, if there are too much unique destinations
2220 DEBUG(dbgs() << "Total number of unique destinations: "
2221 << Dests.size() << '\n'
2222 << "Total number of comparisons: " << numCmps << '\n');
2224 // Compute span of values.
2225 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2226 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2227 APInt cmpRange = maxValue - minValue;
2229 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2230 << "Low bound: " << minValue << '\n'
2231 << "High bound: " << maxValue << '\n');
2233 if (cmpRange.uge(IntPtrBits) ||
2234 (!(Dests.size() == 1 && numCmps >= 3) &&
2235 !(Dests.size() == 2 && numCmps >= 5) &&
2236 !(Dests.size() >= 3 && numCmps >= 6)))
2239 DEBUG(dbgs() << "Emitting bit tests\n");
2240 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2242 // Optimize the case where all the case values fit in a
2243 // word without having to subtract minValue. In this case,
2244 // we can optimize away the subtraction.
2245 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2246 cmpRange = maxValue;
2248 lowBound = minValue;
2251 CaseBitsVector CasesBits;
2252 unsigned i, count = 0;
2254 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2255 MachineBasicBlock* Dest = I->BB;
2256 for (i = 0; i < count; ++i)
2257 if (Dest == CasesBits[i].BB)
2261 assert((count < 3) && "Too much destinations to test!");
2262 CasesBits.push_back(CaseBits(0, Dest, 0));
2266 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2267 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2269 uint64_t lo = (lowValue - lowBound).getZExtValue();
2270 uint64_t hi = (highValue - lowBound).getZExtValue();
2272 for (uint64_t j = lo; j <= hi; j++) {
2273 CasesBits[i].Mask |= 1ULL << j;
2274 CasesBits[i].Bits++;
2278 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2282 // Figure out which block is immediately after the current one.
2283 MachineFunction::iterator BBI = CR.CaseBB;
2286 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2288 DEBUG(dbgs() << "Cases:\n");
2289 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2290 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2291 << ", Bits: " << CasesBits[i].Bits
2292 << ", BB: " << CasesBits[i].BB << '\n');
2294 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2295 CurMF->insert(BBI, CaseBB);
2296 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2300 // Put SV in a virtual register to make it available from the new blocks.
2301 ExportFromCurrentBlock(SV);
2304 BitTestBlock BTB(lowBound, cmpRange, SV,
2305 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2306 CR.CaseBB, Default, BTC);
2308 if (CR.CaseBB == SwitchBB)
2309 visitBitTestHeader(BTB, SwitchBB);
2311 BitTestCases.push_back(BTB);
2316 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2317 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2318 const SwitchInst& SI) {
2321 // Start with "simple" cases
2322 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2323 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2324 Cases.push_back(Case(SI.getSuccessorValue(i),
2325 SI.getSuccessorValue(i),
2328 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2330 // Merge case into clusters
2331 if (Cases.size() >= 2)
2332 // Must recompute end() each iteration because it may be
2333 // invalidated by erase if we hold on to it
2334 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2335 J != Cases.end(); ) {
2336 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2337 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2338 MachineBasicBlock* nextBB = J->BB;
2339 MachineBasicBlock* currentBB = I->BB;
2341 // If the two neighboring cases go to the same destination, merge them
2342 // into a single case.
2343 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2351 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2352 if (I->Low != I->High)
2353 // A range counts double, since it requires two compares.
2360 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2361 MachineBasicBlock *Last) {
2363 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2364 if (JTCases[i].first.HeaderBB == First)
2365 JTCases[i].first.HeaderBB = Last;
2367 // Update BitTestCases.
2368 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2369 if (BitTestCases[i].Parent == First)
2370 BitTestCases[i].Parent = Last;
2373 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2374 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2376 // Figure out which block is immediately after the current one.
2377 MachineBasicBlock *NextBlock = 0;
2378 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2380 // If there is only the default destination, branch to it if it is not the
2381 // next basic block. Otherwise, just fall through.
2382 if (SI.getNumOperands() == 2) {
2383 // Update machine-CFG edges.
2385 // If this is not a fall-through branch, emit the branch.
2386 SwitchMBB->addSuccessor(Default);
2387 if (Default != NextBlock)
2388 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2389 MVT::Other, getControlRoot(),
2390 DAG.getBasicBlock(Default)));
2395 // If there are any non-default case statements, create a vector of Cases
2396 // representing each one, and sort the vector so that we can efficiently
2397 // create a binary search tree from them.
2399 size_t numCmps = Clusterify(Cases, SI);
2400 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2401 << ". Total compares: " << numCmps << '\n');
2404 // Get the Value to be switched on and default basic blocks, which will be
2405 // inserted into CaseBlock records, representing basic blocks in the binary
2407 const Value *SV = SI.getOperand(0);
2409 // Push the initial CaseRec onto the worklist
2410 CaseRecVector WorkList;
2411 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2412 CaseRange(Cases.begin(),Cases.end())));
2414 while (!WorkList.empty()) {
2415 // Grab a record representing a case range to process off the worklist
2416 CaseRec CR = WorkList.back();
2417 WorkList.pop_back();
2419 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2422 // If the range has few cases (two or less) emit a series of specific
2424 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2427 // If the switch has more than 5 blocks, and at least 40% dense, and the
2428 // target supports indirect branches, then emit a jump table rather than
2429 // lowering the switch to a binary tree of conditional branches.
2430 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2433 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2434 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2435 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2439 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2440 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2442 // Update machine-CFG edges with unique successors.
2443 SmallVector<BasicBlock*, 32> succs;
2444 succs.reserve(I.getNumSuccessors());
2445 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2446 succs.push_back(I.getSuccessor(i));
2447 array_pod_sort(succs.begin(), succs.end());
2448 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2449 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2450 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2451 addSuccessorWithWeight(IndirectBrMBB, Succ);
2454 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2455 MVT::Other, getControlRoot(),
2456 getValue(I.getAddress())));
2459 void SelectionDAGBuilder::visitFSub(const User &I) {
2460 // -0.0 - X --> fneg
2461 Type *Ty = I.getType();
2462 if (isa<Constant>(I.getOperand(0)) &&
2463 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2464 SDValue Op2 = getValue(I.getOperand(1));
2465 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2466 Op2.getValueType(), Op2));
2470 visitBinary(I, ISD::FSUB);
2473 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2474 SDValue Op1 = getValue(I.getOperand(0));
2475 SDValue Op2 = getValue(I.getOperand(1));
2476 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2477 Op1.getValueType(), Op1, Op2));
2480 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2481 SDValue Op1 = getValue(I.getOperand(0));
2482 SDValue Op2 = getValue(I.getOperand(1));
2484 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2486 // Coerce the shift amount to the right type if we can.
2487 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2488 unsigned ShiftSize = ShiftTy.getSizeInBits();
2489 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2490 DebugLoc DL = getCurDebugLoc();
2492 // If the operand is smaller than the shift count type, promote it.
2493 if (ShiftSize > Op2Size)
2494 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2496 // If the operand is larger than the shift count type but the shift
2497 // count type has enough bits to represent any shift value, truncate
2498 // it now. This is a common case and it exposes the truncate to
2499 // optimization early.
2500 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2501 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2502 // Otherwise we'll need to temporarily settle for some other convenient
2503 // type. Type legalization will make adjustments once the shiftee is split.
2505 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2508 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2509 Op1.getValueType(), Op1, Op2));
2512 void SelectionDAGBuilder::visitSDiv(const User &I) {
2513 SDValue Op1 = getValue(I.getOperand(0));
2514 SDValue Op2 = getValue(I.getOperand(1));
2516 // Turn exact SDivs into multiplications.
2517 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2519 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2520 !isa<ConstantSDNode>(Op1) &&
2521 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2522 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2524 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2528 void SelectionDAGBuilder::visitICmp(const User &I) {
2529 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2530 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2531 predicate = IC->getPredicate();
2532 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2533 predicate = ICmpInst::Predicate(IC->getPredicate());
2534 SDValue Op1 = getValue(I.getOperand(0));
2535 SDValue Op2 = getValue(I.getOperand(1));
2536 ISD::CondCode Opcode = getICmpCondCode(predicate);
2538 EVT DestVT = TLI.getValueType(I.getType());
2539 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2542 void SelectionDAGBuilder::visitFCmp(const User &I) {
2543 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2544 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2545 predicate = FC->getPredicate();
2546 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2547 predicate = FCmpInst::Predicate(FC->getPredicate());
2548 SDValue Op1 = getValue(I.getOperand(0));
2549 SDValue Op2 = getValue(I.getOperand(1));
2550 ISD::CondCode Condition = getFCmpCondCode(predicate);
2551 EVT DestVT = TLI.getValueType(I.getType());
2552 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2555 void SelectionDAGBuilder::visitSelect(const User &I) {
2556 SmallVector<EVT, 4> ValueVTs;
2557 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2558 unsigned NumValues = ValueVTs.size();
2559 if (NumValues == 0) return;
2561 SmallVector<SDValue, 4> Values(NumValues);
2562 SDValue Cond = getValue(I.getOperand(0));
2563 SDValue TrueVal = getValue(I.getOperand(1));
2564 SDValue FalseVal = getValue(I.getOperand(2));
2566 for (unsigned i = 0; i != NumValues; ++i)
2567 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2568 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2570 SDValue(TrueVal.getNode(),
2571 TrueVal.getResNo() + i),
2572 SDValue(FalseVal.getNode(),
2573 FalseVal.getResNo() + i));
2575 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2576 DAG.getVTList(&ValueVTs[0], NumValues),
2577 &Values[0], NumValues));
2580 void SelectionDAGBuilder::visitTrunc(const User &I) {
2581 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2582 SDValue N = getValue(I.getOperand(0));
2583 EVT DestVT = TLI.getValueType(I.getType());
2584 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2587 void SelectionDAGBuilder::visitZExt(const User &I) {
2588 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2589 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2590 SDValue N = getValue(I.getOperand(0));
2591 EVT DestVT = TLI.getValueType(I.getType());
2592 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2595 void SelectionDAGBuilder::visitSExt(const User &I) {
2596 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2597 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2598 SDValue N = getValue(I.getOperand(0));
2599 EVT DestVT = TLI.getValueType(I.getType());
2600 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2603 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2604 // FPTrunc is never a no-op cast, no need to check
2605 SDValue N = getValue(I.getOperand(0));
2606 EVT DestVT = TLI.getValueType(I.getType());
2607 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2608 DestVT, N, DAG.getIntPtrConstant(0)));
2611 void SelectionDAGBuilder::visitFPExt(const User &I){
2612 // FPTrunc is never a no-op cast, no need to check
2613 SDValue N = getValue(I.getOperand(0));
2614 EVT DestVT = TLI.getValueType(I.getType());
2615 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2618 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2619 // FPToUI is never a no-op cast, no need to check
2620 SDValue N = getValue(I.getOperand(0));
2621 EVT DestVT = TLI.getValueType(I.getType());
2622 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2625 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2626 // FPToSI is never a no-op cast, no need to check
2627 SDValue N = getValue(I.getOperand(0));
2628 EVT DestVT = TLI.getValueType(I.getType());
2629 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2632 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2633 // UIToFP is never a no-op cast, no need to check
2634 SDValue N = getValue(I.getOperand(0));
2635 EVT DestVT = TLI.getValueType(I.getType());
2636 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2639 void SelectionDAGBuilder::visitSIToFP(const User &I){
2640 // SIToFP is never a no-op cast, no need to check
2641 SDValue N = getValue(I.getOperand(0));
2642 EVT DestVT = TLI.getValueType(I.getType());
2643 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2646 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2647 // What to do depends on the size of the integer and the size of the pointer.
2648 // We can either truncate, zero extend, or no-op, accordingly.
2649 SDValue N = getValue(I.getOperand(0));
2650 EVT DestVT = TLI.getValueType(I.getType());
2651 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2654 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2655 // What to do depends on the size of the integer and the size of the pointer.
2656 // We can either truncate, zero extend, or no-op, accordingly.
2657 SDValue N = getValue(I.getOperand(0));
2658 EVT DestVT = TLI.getValueType(I.getType());
2659 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2662 void SelectionDAGBuilder::visitBitCast(const User &I) {
2663 SDValue N = getValue(I.getOperand(0));
2664 EVT DestVT = TLI.getValueType(I.getType());
2666 // BitCast assures us that source and destination are the same size so this is
2667 // either a BITCAST or a no-op.
2668 if (DestVT != N.getValueType())
2669 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2670 DestVT, N)); // convert types.
2672 setValue(&I, N); // noop cast.
2675 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2676 SDValue InVec = getValue(I.getOperand(0));
2677 SDValue InVal = getValue(I.getOperand(1));
2678 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2680 getValue(I.getOperand(2)));
2681 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2682 TLI.getValueType(I.getType()),
2683 InVec, InVal, InIdx));
2686 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2687 SDValue InVec = getValue(I.getOperand(0));
2688 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2690 getValue(I.getOperand(1)));
2691 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2692 TLI.getValueType(I.getType()), InVec, InIdx));
2695 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2696 // from SIndx and increasing to the element length (undefs are allowed).
2697 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2698 unsigned MaskNumElts = Mask.size();
2699 for (unsigned i = 0; i != MaskNumElts; ++i)
2700 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2705 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2706 SmallVector<int, 8> Mask;
2707 SDValue Src1 = getValue(I.getOperand(0));
2708 SDValue Src2 = getValue(I.getOperand(1));
2710 // Convert the ConstantVector mask operand into an array of ints, with -1
2711 // representing undef values.
2712 SmallVector<Constant*, 8> MaskElts;
2713 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2714 unsigned MaskNumElts = MaskElts.size();
2715 for (unsigned i = 0; i != MaskNumElts; ++i) {
2716 if (isa<UndefValue>(MaskElts[i]))
2719 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2722 EVT VT = TLI.getValueType(I.getType());
2723 EVT SrcVT = Src1.getValueType();
2724 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2726 if (SrcNumElts == MaskNumElts) {
2727 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2732 // Normalize the shuffle vector since mask and vector length don't match.
2733 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2734 // Mask is longer than the source vectors and is a multiple of the source
2735 // vectors. We can use concatenate vector to make the mask and vectors
2737 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2738 // The shuffle is concatenating two vectors together.
2739 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2744 // Pad both vectors with undefs to make them the same length as the mask.
2745 unsigned NumConcat = MaskNumElts / SrcNumElts;
2746 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2747 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2748 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2750 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2751 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2755 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2756 getCurDebugLoc(), VT,
2757 &MOps1[0], NumConcat);
2758 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2759 getCurDebugLoc(), VT,
2760 &MOps2[0], NumConcat);
2762 // Readjust mask for new input vector length.
2763 SmallVector<int, 8> MappedOps;
2764 for (unsigned i = 0; i != MaskNumElts; ++i) {
2766 if (Idx < (int)SrcNumElts)
2767 MappedOps.push_back(Idx);
2769 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2772 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2777 if (SrcNumElts > MaskNumElts) {
2778 // Analyze the access pattern of the vector to see if we can extract
2779 // two subvectors and do the shuffle. The analysis is done by calculating
2780 // the range of elements the mask access on both vectors.
2781 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2782 int MaxRange[2] = {-1, -1};
2784 for (unsigned i = 0; i != MaskNumElts; ++i) {
2790 if (Idx >= (int)SrcNumElts) {
2794 if (Idx > MaxRange[Input])
2795 MaxRange[Input] = Idx;
2796 if (Idx < MinRange[Input])
2797 MinRange[Input] = Idx;
2800 // Check if the access is smaller than the vector size and can we find
2801 // a reasonable extract index.
2802 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2804 int StartIdx[2]; // StartIdx to extract from
2805 for (int Input=0; Input < 2; ++Input) {
2806 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2807 RangeUse[Input] = 0; // Unused
2808 StartIdx[Input] = 0;
2809 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2810 // Fits within range but we should see if we can find a good
2811 // start index that is a multiple of the mask length.
2812 if (MaxRange[Input] < (int)MaskNumElts) {
2813 RangeUse[Input] = 1; // Extract from beginning of the vector
2814 StartIdx[Input] = 0;
2816 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2817 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2818 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2819 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2824 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2825 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2828 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2829 // Extract appropriate subvector and generate a vector shuffle
2830 for (int Input=0; Input < 2; ++Input) {
2831 SDValue &Src = Input == 0 ? Src1 : Src2;
2832 if (RangeUse[Input] == 0)
2833 Src = DAG.getUNDEF(VT);
2835 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2836 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2839 // Calculate new mask.
2840 SmallVector<int, 8> MappedOps;
2841 for (unsigned i = 0; i != MaskNumElts; ++i) {
2844 MappedOps.push_back(Idx);
2845 else if (Idx < (int)SrcNumElts)
2846 MappedOps.push_back(Idx - StartIdx[0]);
2848 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2851 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2857 // We can't use either concat vectors or extract subvectors so fall back to
2858 // replacing the shuffle with extract and build vector.
2859 // to insert and build vector.
2860 EVT EltVT = VT.getVectorElementType();
2861 EVT PtrVT = TLI.getPointerTy();
2862 SmallVector<SDValue,8> Ops;
2863 for (unsigned i = 0; i != MaskNumElts; ++i) {
2865 Ops.push_back(DAG.getUNDEF(EltVT));
2870 if (Idx < (int)SrcNumElts)
2871 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2872 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2874 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2876 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2882 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2883 VT, &Ops[0], Ops.size()));
2886 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2887 const Value *Op0 = I.getOperand(0);
2888 const Value *Op1 = I.getOperand(1);
2889 Type *AggTy = I.getType();
2890 Type *ValTy = Op1->getType();
2891 bool IntoUndef = isa<UndefValue>(Op0);
2892 bool FromUndef = isa<UndefValue>(Op1);
2894 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2896 SmallVector<EVT, 4> AggValueVTs;
2897 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2898 SmallVector<EVT, 4> ValValueVTs;
2899 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2901 unsigned NumAggValues = AggValueVTs.size();
2902 unsigned NumValValues = ValValueVTs.size();
2903 SmallVector<SDValue, 4> Values(NumAggValues);
2905 SDValue Agg = getValue(Op0);
2907 // Copy the beginning value(s) from the original aggregate.
2908 for (; i != LinearIndex; ++i)
2909 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2910 SDValue(Agg.getNode(), Agg.getResNo() + i);
2911 // Copy values from the inserted value(s).
2913 SDValue Val = getValue(Op1);
2914 for (; i != LinearIndex + NumValValues; ++i)
2915 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2916 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2918 // Copy remaining value(s) from the original aggregate.
2919 for (; i != NumAggValues; ++i)
2920 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2921 SDValue(Agg.getNode(), Agg.getResNo() + i);
2923 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2924 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2925 &Values[0], NumAggValues));
2928 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2929 const Value *Op0 = I.getOperand(0);
2930 Type *AggTy = Op0->getType();
2931 Type *ValTy = I.getType();
2932 bool OutOfUndef = isa<UndefValue>(Op0);
2934 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2936 SmallVector<EVT, 4> ValValueVTs;
2937 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2939 unsigned NumValValues = ValValueVTs.size();
2941 // Ignore a extractvalue that produces an empty object
2942 if (!NumValValues) {
2943 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2947 SmallVector<SDValue, 4> Values(NumValValues);
2949 SDValue Agg = getValue(Op0);
2950 // Copy out the selected value(s).
2951 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2952 Values[i - LinearIndex] =
2954 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2955 SDValue(Agg.getNode(), Agg.getResNo() + i);
2957 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2958 DAG.getVTList(&ValValueVTs[0], NumValValues),
2959 &Values[0], NumValValues));
2962 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2963 SDValue N = getValue(I.getOperand(0));
2964 Type *Ty = I.getOperand(0)->getType();
2966 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2968 const Value *Idx = *OI;
2969 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2970 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2973 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2974 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2975 DAG.getIntPtrConstant(Offset));
2978 Ty = StTy->getElementType(Field);
2980 Ty = cast<SequentialType>(Ty)->getElementType();
2982 // If this is a constant subscript, handle it quickly.
2983 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2984 if (CI->isZero()) continue;
2986 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2988 EVT PTy = TLI.getPointerTy();
2989 unsigned PtrBits = PTy.getSizeInBits();
2991 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2993 DAG.getConstant(Offs, MVT::i64));
2995 OffsVal = DAG.getIntPtrConstant(Offs);
2997 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3002 // N = N + Idx * ElementSize;
3003 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3004 TD->getTypeAllocSize(Ty));
3005 SDValue IdxN = getValue(Idx);
3007 // If the index is smaller or larger than intptr_t, truncate or extend
3009 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3011 // If this is a multiply by a power of two, turn it into a shl
3012 // immediately. This is a very common case.
3013 if (ElementSize != 1) {
3014 if (ElementSize.isPowerOf2()) {
3015 unsigned Amt = ElementSize.logBase2();
3016 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3017 N.getValueType(), IdxN,
3018 DAG.getConstant(Amt, TLI.getPointerTy()));
3020 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3021 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3022 N.getValueType(), IdxN, Scale);
3026 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3027 N.getValueType(), N, IdxN);
3034 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3035 // If this is a fixed sized alloca in the entry block of the function,
3036 // allocate it statically on the stack.
3037 if (FuncInfo.StaticAllocaMap.count(&I))
3038 return; // getValue will auto-populate this.
3040 Type *Ty = I.getAllocatedType();
3041 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3043 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3046 SDValue AllocSize = getValue(I.getArraySize());
3048 EVT IntPtr = TLI.getPointerTy();
3049 if (AllocSize.getValueType() != IntPtr)
3050 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3052 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3054 DAG.getConstant(TySize, IntPtr));
3056 // Handle alignment. If the requested alignment is less than or equal to
3057 // the stack alignment, ignore it. If the size is greater than or equal to
3058 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3059 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3060 if (Align <= StackAlign)
3063 // Round the size of the allocation up to the stack alignment size
3064 // by add SA-1 to the size.
3065 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3066 AllocSize.getValueType(), AllocSize,
3067 DAG.getIntPtrConstant(StackAlign-1));
3069 // Mask out the low bits for alignment purposes.
3070 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3071 AllocSize.getValueType(), AllocSize,
3072 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3074 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3075 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3076 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3079 DAG.setRoot(DSA.getValue(1));
3081 // Inform the Frame Information that we have just allocated a variable-sized
3083 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3086 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3087 const Value *SV = I.getOperand(0);
3088 SDValue Ptr = getValue(SV);
3090 Type *Ty = I.getType();
3092 bool isVolatile = I.isVolatile();
3093 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3094 unsigned Alignment = I.getAlignment();
3095 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3097 SmallVector<EVT, 4> ValueVTs;
3098 SmallVector<uint64_t, 4> Offsets;
3099 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3100 unsigned NumValues = ValueVTs.size();
3105 bool ConstantMemory = false;
3106 if (I.isVolatile() || NumValues > MaxParallelChains)
3107 // Serialize volatile loads with other side effects.
3109 else if (AA->pointsToConstantMemory(
3110 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3111 // Do not serialize (non-volatile) loads of constant memory with anything.
3112 Root = DAG.getEntryNode();
3113 ConstantMemory = true;
3115 // Do not serialize non-volatile loads against each other.
3116 Root = DAG.getRoot();
3119 SmallVector<SDValue, 4> Values(NumValues);
3120 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3122 EVT PtrVT = Ptr.getValueType();
3123 unsigned ChainI = 0;
3124 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3125 // Serializing loads here may result in excessive register pressure, and
3126 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3127 // could recover a bit by hoisting nodes upward in the chain by recognizing
3128 // they are side-effect free or do not alias. The optimizer should really
3129 // avoid this case by converting large object/array copies to llvm.memcpy
3130 // (MaxParallelChains should always remain as failsafe).
3131 if (ChainI == MaxParallelChains) {
3132 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3133 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3134 MVT::Other, &Chains[0], ChainI);
3138 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3140 DAG.getConstant(Offsets[i], PtrVT));
3141 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3142 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3143 isNonTemporal, Alignment, TBAAInfo);
3146 Chains[ChainI] = L.getValue(1);
3149 if (!ConstantMemory) {
3150 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3151 MVT::Other, &Chains[0], ChainI);
3155 PendingLoads.push_back(Chain);
3158 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3159 DAG.getVTList(&ValueVTs[0], NumValues),
3160 &Values[0], NumValues));
3163 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3164 const Value *SrcV = I.getOperand(0);
3165 const Value *PtrV = I.getOperand(1);
3167 SmallVector<EVT, 4> ValueVTs;
3168 SmallVector<uint64_t, 4> Offsets;
3169 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3170 unsigned NumValues = ValueVTs.size();
3174 // Get the lowered operands. Note that we do this after
3175 // checking if NumResults is zero, because with zero results
3176 // the operands won't have values in the map.
3177 SDValue Src = getValue(SrcV);
3178 SDValue Ptr = getValue(PtrV);
3180 SDValue Root = getRoot();
3181 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3183 EVT PtrVT = Ptr.getValueType();
3184 bool isVolatile = I.isVolatile();
3185 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3186 unsigned Alignment = I.getAlignment();
3187 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3189 unsigned ChainI = 0;
3190 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3191 // See visitLoad comments.
3192 if (ChainI == MaxParallelChains) {
3193 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3194 MVT::Other, &Chains[0], ChainI);
3198 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3199 DAG.getConstant(Offsets[i], PtrVT));
3200 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3201 SDValue(Src.getNode(), Src.getResNo() + i),
3202 Add, MachinePointerInfo(PtrV, Offsets[i]),
3203 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3204 Chains[ChainI] = St;
3207 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3208 MVT::Other, &Chains[0], ChainI);
3210 AssignOrderingToNode(StoreNode.getNode());
3211 DAG.setRoot(StoreNode);
3214 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3215 llvm_unreachable("Not implemented yet");
3218 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3220 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3221 unsigned Intrinsic) {
3222 bool HasChain = !I.doesNotAccessMemory();
3223 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3225 // Build the operand list.
3226 SmallVector<SDValue, 8> Ops;
3227 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3229 // We don't need to serialize loads against other loads.
3230 Ops.push_back(DAG.getRoot());
3232 Ops.push_back(getRoot());
3236 // Info is set by getTgtMemInstrinsic
3237 TargetLowering::IntrinsicInfo Info;
3238 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3240 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3241 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3242 Info.opc == ISD::INTRINSIC_W_CHAIN)
3243 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3245 // Add all operands of the call to the operand list.
3246 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3247 SDValue Op = getValue(I.getArgOperand(i));
3248 assert(TLI.isTypeLegal(Op.getValueType()) &&
3249 "Intrinsic uses a non-legal type?");
3253 SmallVector<EVT, 4> ValueVTs;
3254 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3256 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3257 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3258 "Intrinsic uses a non-legal type?");
3263 ValueVTs.push_back(MVT::Other);
3265 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3269 if (IsTgtIntrinsic) {
3270 // This is target intrinsic that touches memory
3271 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3272 VTs, &Ops[0], Ops.size(),
3274 MachinePointerInfo(Info.ptrVal, Info.offset),
3275 Info.align, Info.vol,
3276 Info.readMem, Info.writeMem);
3277 } else if (!HasChain) {
3278 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3279 VTs, &Ops[0], Ops.size());
3280 } else if (!I.getType()->isVoidTy()) {
3281 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3282 VTs, &Ops[0], Ops.size());
3284 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3285 VTs, &Ops[0], Ops.size());
3289 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3291 PendingLoads.push_back(Chain);
3296 if (!I.getType()->isVoidTy()) {
3297 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3298 EVT VT = TLI.getValueType(PTy);
3299 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3302 setValue(&I, Result);
3306 /// GetSignificand - Get the significand and build it into a floating-point
3307 /// number with exponent of 1:
3309 /// Op = (Op & 0x007fffff) | 0x3f800000;
3311 /// where Op is the hexidecimal representation of floating point value.
3313 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3314 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3315 DAG.getConstant(0x007fffff, MVT::i32));
3316 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3317 DAG.getConstant(0x3f800000, MVT::i32));
3318 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3321 /// GetExponent - Get the exponent:
3323 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3325 /// where Op is the hexidecimal representation of floating point value.
3327 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3329 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3330 DAG.getConstant(0x7f800000, MVT::i32));
3331 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3332 DAG.getConstant(23, TLI.getPointerTy()));
3333 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3334 DAG.getConstant(127, MVT::i32));
3335 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3338 /// getF32Constant - Get 32-bit floating point constant.
3340 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3341 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3344 /// Inlined utility function to implement binary input atomic intrinsics for
3345 /// visitIntrinsicCall: I is a call instruction
3346 /// Op is the associated NodeType for I
3348 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3350 SDValue Root = getRoot();
3352 DAG.getAtomic(Op, getCurDebugLoc(),
3353 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3355 getValue(I.getArgOperand(0)),
3356 getValue(I.getArgOperand(1)),
3357 I.getArgOperand(0));
3359 DAG.setRoot(L.getValue(1));
3363 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3365 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3366 SDValue Op1 = getValue(I.getArgOperand(0));
3367 SDValue Op2 = getValue(I.getArgOperand(1));
3369 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3370 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3374 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3375 /// limited-precision mode.
3377 SelectionDAGBuilder::visitExp(const CallInst &I) {
3379 DebugLoc dl = getCurDebugLoc();
3381 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3382 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3383 SDValue Op = getValue(I.getArgOperand(0));
3385 // Put the exponent in the right bit position for later addition to the
3388 // #define LOG2OFe 1.4426950f
3389 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3390 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3391 getF32Constant(DAG, 0x3fb8aa3b));
3392 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3394 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3395 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3396 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3398 // IntegerPartOfX <<= 23;
3399 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3400 DAG.getConstant(23, TLI.getPointerTy()));
3402 if (LimitFloatPrecision <= 6) {
3403 // For floating-point precision of 6:
3405 // TwoToFractionalPartOfX =
3407 // (0.735607626f + 0.252464424f * x) * x;
3409 // error 0.0144103317, which is 6 bits
3410 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3411 getF32Constant(DAG, 0x3e814304));
3412 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3413 getF32Constant(DAG, 0x3f3c50c8));
3414 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3415 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3416 getF32Constant(DAG, 0x3f7f5e7e));
3417 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3419 // Add the exponent into the result in integer domain.
3420 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3421 TwoToFracPartOfX, IntegerPartOfX);
3423 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3424 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3425 // For floating-point precision of 12:
3427 // TwoToFractionalPartOfX =
3430 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3432 // 0.000107046256 error, which is 13 to 14 bits
3433 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3434 getF32Constant(DAG, 0x3da235e3));
3435 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3436 getF32Constant(DAG, 0x3e65b8f3));
3437 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3438 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3439 getF32Constant(DAG, 0x3f324b07));
3440 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3441 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3442 getF32Constant(DAG, 0x3f7ff8fd));
3443 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3445 // Add the exponent into the result in integer domain.
3446 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3447 TwoToFracPartOfX, IntegerPartOfX);
3449 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3450 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3451 // For floating-point precision of 18:
3453 // TwoToFractionalPartOfX =
3457 // (0.554906021e-1f +
3458 // (0.961591928e-2f +
3459 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3461 // error 2.47208000*10^(-7), which is better than 18 bits
3462 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3463 getF32Constant(DAG, 0x3924b03e));
3464 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3465 getF32Constant(DAG, 0x3ab24b87));
3466 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3467 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3468 getF32Constant(DAG, 0x3c1d8c17));
3469 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3470 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3471 getF32Constant(DAG, 0x3d634a1d));
3472 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3473 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3474 getF32Constant(DAG, 0x3e75fe14));
3475 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3476 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3477 getF32Constant(DAG, 0x3f317234));
3478 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3479 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3480 getF32Constant(DAG, 0x3f800000));
3481 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3484 // Add the exponent into the result in integer domain.
3485 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3486 TwoToFracPartOfX, IntegerPartOfX);
3488 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3491 // No special expansion.
3492 result = DAG.getNode(ISD::FEXP, dl,
3493 getValue(I.getArgOperand(0)).getValueType(),
3494 getValue(I.getArgOperand(0)));
3497 setValue(&I, result);
3500 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3501 /// limited-precision mode.
3503 SelectionDAGBuilder::visitLog(const CallInst &I) {
3505 DebugLoc dl = getCurDebugLoc();
3507 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3508 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3509 SDValue Op = getValue(I.getArgOperand(0));
3510 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3512 // Scale the exponent by log(2) [0.69314718f].
3513 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3514 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3515 getF32Constant(DAG, 0x3f317218));
3517 // Get the significand and build it into a floating-point number with
3519 SDValue X = GetSignificand(DAG, Op1, dl);
3521 if (LimitFloatPrecision <= 6) {
3522 // For floating-point precision of 6:
3526 // (1.4034025f - 0.23903021f * x) * x;
3528 // error 0.0034276066, which is better than 8 bits
3529 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3530 getF32Constant(DAG, 0xbe74c456));
3531 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3532 getF32Constant(DAG, 0x3fb3a2b1));
3533 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3534 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3535 getF32Constant(DAG, 0x3f949a29));
3537 result = DAG.getNode(ISD::FADD, dl,
3538 MVT::f32, LogOfExponent, LogOfMantissa);
3539 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3540 // For floating-point precision of 12:
3546 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3548 // error 0.000061011436, which is 14 bits
3549 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3550 getF32Constant(DAG, 0xbd67b6d6));
3551 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3552 getF32Constant(DAG, 0x3ee4f4b8));
3553 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3554 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3555 getF32Constant(DAG, 0x3fbc278b));
3556 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3557 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3558 getF32Constant(DAG, 0x40348e95));
3559 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3560 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3561 getF32Constant(DAG, 0x3fdef31a));
3563 result = DAG.getNode(ISD::FADD, dl,
3564 MVT::f32, LogOfExponent, LogOfMantissa);
3565 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3566 // For floating-point precision of 18:
3574 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3576 // error 0.0000023660568, which is better than 18 bits
3577 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3578 getF32Constant(DAG, 0xbc91e5ac));
3579 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3580 getF32Constant(DAG, 0x3e4350aa));
3581 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3582 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3583 getF32Constant(DAG, 0x3f60d3e3));
3584 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3585 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3586 getF32Constant(DAG, 0x4011cdf0));
3587 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3588 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3589 getF32Constant(DAG, 0x406cfd1c));
3590 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3591 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3592 getF32Constant(DAG, 0x408797cb));
3593 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3594 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3595 getF32Constant(DAG, 0x4006dcab));
3597 result = DAG.getNode(ISD::FADD, dl,
3598 MVT::f32, LogOfExponent, LogOfMantissa);
3601 // No special expansion.
3602 result = DAG.getNode(ISD::FLOG, dl,
3603 getValue(I.getArgOperand(0)).getValueType(),
3604 getValue(I.getArgOperand(0)));
3607 setValue(&I, result);
3610 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3611 /// limited-precision mode.
3613 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3615 DebugLoc dl = getCurDebugLoc();
3617 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3618 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3619 SDValue Op = getValue(I.getArgOperand(0));
3620 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3622 // Get the exponent.
3623 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3625 // Get the significand and build it into a floating-point number with
3627 SDValue X = GetSignificand(DAG, Op1, dl);
3629 // Different possible minimax approximations of significand in
3630 // floating-point for various degrees of accuracy over [1,2].
3631 if (LimitFloatPrecision <= 6) {
3632 // For floating-point precision of 6:
3634 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3636 // error 0.0049451742, which is more than 7 bits
3637 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3638 getF32Constant(DAG, 0xbeb08fe0));
3639 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3640 getF32Constant(DAG, 0x40019463));
3641 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3642 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3643 getF32Constant(DAG, 0x3fd6633d));
3645 result = DAG.getNode(ISD::FADD, dl,
3646 MVT::f32, LogOfExponent, Log2ofMantissa);
3647 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3648 // For floating-point precision of 12:
3654 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3656 // error 0.0000876136000, which is better than 13 bits
3657 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3658 getF32Constant(DAG, 0xbda7262e));
3659 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3660 getF32Constant(DAG, 0x3f25280b));
3661 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3662 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3663 getF32Constant(DAG, 0x4007b923));
3664 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3665 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3666 getF32Constant(DAG, 0x40823e2f));
3667 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3668 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3669 getF32Constant(DAG, 0x4020d29c));
3671 result = DAG.getNode(ISD::FADD, dl,
3672 MVT::f32, LogOfExponent, Log2ofMantissa);
3673 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3674 // For floating-point precision of 18:
3683 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3685 // error 0.0000018516, which is better than 18 bits
3686 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3687 getF32Constant(DAG, 0xbcd2769e));
3688 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3689 getF32Constant(DAG, 0x3e8ce0b9));
3690 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3691 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3692 getF32Constant(DAG, 0x3fa22ae7));
3693 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3694 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3695 getF32Constant(DAG, 0x40525723));
3696 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3697 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3698 getF32Constant(DAG, 0x40aaf200));
3699 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3700 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3701 getF32Constant(DAG, 0x40c39dad));
3702 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3703 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3704 getF32Constant(DAG, 0x4042902c));
3706 result = DAG.getNode(ISD::FADD, dl,
3707 MVT::f32, LogOfExponent, Log2ofMantissa);
3710 // No special expansion.
3711 result = DAG.getNode(ISD::FLOG2, dl,
3712 getValue(I.getArgOperand(0)).getValueType(),
3713 getValue(I.getArgOperand(0)));
3716 setValue(&I, result);
3719 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3720 /// limited-precision mode.
3722 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3724 DebugLoc dl = getCurDebugLoc();
3726 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3727 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3728 SDValue Op = getValue(I.getArgOperand(0));
3729 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3731 // Scale the exponent by log10(2) [0.30102999f].
3732 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3733 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3734 getF32Constant(DAG, 0x3e9a209a));
3736 // Get the significand and build it into a floating-point number with
3738 SDValue X = GetSignificand(DAG, Op1, dl);
3740 if (LimitFloatPrecision <= 6) {
3741 // For floating-point precision of 6:
3743 // Log10ofMantissa =
3745 // (0.60948995f - 0.10380950f * x) * x;
3747 // error 0.0014886165, which is 6 bits
3748 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3749 getF32Constant(DAG, 0xbdd49a13));
3750 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3751 getF32Constant(DAG, 0x3f1c0789));
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3753 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3754 getF32Constant(DAG, 0x3f011300));
3756 result = DAG.getNode(ISD::FADD, dl,
3757 MVT::f32, LogOfExponent, Log10ofMantissa);
3758 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3759 // For floating-point precision of 12:
3761 // Log10ofMantissa =
3764 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3766 // error 0.00019228036, which is better than 12 bits
3767 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3768 getF32Constant(DAG, 0x3d431f31));
3769 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3770 getF32Constant(DAG, 0x3ea21fb2));
3771 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3772 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3773 getF32Constant(DAG, 0x3f6ae232));
3774 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3775 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3776 getF32Constant(DAG, 0x3f25f7c3));
3778 result = DAG.getNode(ISD::FADD, dl,
3779 MVT::f32, LogOfExponent, Log10ofMantissa);
3780 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3781 // For floating-point precision of 18:
3783 // Log10ofMantissa =
3788 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3790 // error 0.0000037995730, which is better than 18 bits
3791 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3792 getF32Constant(DAG, 0x3c5d51ce));
3793 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3794 getF32Constant(DAG, 0x3e00685a));
3795 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3796 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3797 getF32Constant(DAG, 0x3efb6798));
3798 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3799 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3800 getF32Constant(DAG, 0x3f88d192));
3801 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3802 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3803 getF32Constant(DAG, 0x3fc4316c));
3804 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3805 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3806 getF32Constant(DAG, 0x3f57ce70));
3808 result = DAG.getNode(ISD::FADD, dl,
3809 MVT::f32, LogOfExponent, Log10ofMantissa);
3812 // No special expansion.
3813 result = DAG.getNode(ISD::FLOG10, dl,
3814 getValue(I.getArgOperand(0)).getValueType(),
3815 getValue(I.getArgOperand(0)));
3818 setValue(&I, result);
3821 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3822 /// limited-precision mode.
3824 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3826 DebugLoc dl = getCurDebugLoc();
3828 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3829 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3830 SDValue Op = getValue(I.getArgOperand(0));
3832 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3834 // FractionalPartOfX = x - (float)IntegerPartOfX;
3835 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3836 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3838 // IntegerPartOfX <<= 23;
3839 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3840 DAG.getConstant(23, TLI.getPointerTy()));
3842 if (LimitFloatPrecision <= 6) {
3843 // For floating-point precision of 6:
3845 // TwoToFractionalPartOfX =
3847 // (0.735607626f + 0.252464424f * x) * x;
3849 // error 0.0144103317, which is 6 bits
3850 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3851 getF32Constant(DAG, 0x3e814304));
3852 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3853 getF32Constant(DAG, 0x3f3c50c8));
3854 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3855 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3856 getF32Constant(DAG, 0x3f7f5e7e));
3857 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3858 SDValue TwoToFractionalPartOfX =
3859 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3861 result = DAG.getNode(ISD::BITCAST, dl,
3862 MVT::f32, TwoToFractionalPartOfX);
3863 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3864 // For floating-point precision of 12:
3866 // TwoToFractionalPartOfX =
3869 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3871 // error 0.000107046256, which is 13 to 14 bits
3872 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3873 getF32Constant(DAG, 0x3da235e3));
3874 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3875 getF32Constant(DAG, 0x3e65b8f3));
3876 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3877 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3878 getF32Constant(DAG, 0x3f324b07));
3879 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3880 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3881 getF32Constant(DAG, 0x3f7ff8fd));
3882 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3883 SDValue TwoToFractionalPartOfX =
3884 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3886 result = DAG.getNode(ISD::BITCAST, dl,
3887 MVT::f32, TwoToFractionalPartOfX);
3888 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3889 // For floating-point precision of 18:
3891 // TwoToFractionalPartOfX =
3895 // (0.554906021e-1f +
3896 // (0.961591928e-2f +
3897 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3898 // error 2.47208000*10^(-7), which is better than 18 bits
3899 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3900 getF32Constant(DAG, 0x3924b03e));
3901 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3902 getF32Constant(DAG, 0x3ab24b87));
3903 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3904 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3905 getF32Constant(DAG, 0x3c1d8c17));
3906 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3907 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3908 getF32Constant(DAG, 0x3d634a1d));
3909 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3910 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3911 getF32Constant(DAG, 0x3e75fe14));
3912 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3913 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3914 getF32Constant(DAG, 0x3f317234));
3915 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3916 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3917 getF32Constant(DAG, 0x3f800000));
3918 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3919 SDValue TwoToFractionalPartOfX =
3920 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3922 result = DAG.getNode(ISD::BITCAST, dl,
3923 MVT::f32, TwoToFractionalPartOfX);
3926 // No special expansion.
3927 result = DAG.getNode(ISD::FEXP2, dl,
3928 getValue(I.getArgOperand(0)).getValueType(),
3929 getValue(I.getArgOperand(0)));
3932 setValue(&I, result);
3935 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3936 /// limited-precision mode with x == 10.0f.
3938 SelectionDAGBuilder::visitPow(const CallInst &I) {
3940 const Value *Val = I.getArgOperand(0);
3941 DebugLoc dl = getCurDebugLoc();
3942 bool IsExp10 = false;
3944 if (getValue(Val).getValueType() == MVT::f32 &&
3945 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3946 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3947 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3948 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3950 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3955 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3956 SDValue Op = getValue(I.getArgOperand(1));
3958 // Put the exponent in the right bit position for later addition to the
3961 // #define LOG2OF10 3.3219281f
3962 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3963 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3964 getF32Constant(DAG, 0x40549a78));
3965 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3967 // FractionalPartOfX = x - (float)IntegerPartOfX;
3968 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3969 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3971 // IntegerPartOfX <<= 23;
3972 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3973 DAG.getConstant(23, TLI.getPointerTy()));
3975 if (LimitFloatPrecision <= 6) {
3976 // For floating-point precision of 6:
3978 // twoToFractionalPartOfX =
3980 // (0.735607626f + 0.252464424f * x) * x;
3982 // error 0.0144103317, which is 6 bits
3983 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3984 getF32Constant(DAG, 0x3e814304));
3985 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3986 getF32Constant(DAG, 0x3f3c50c8));
3987 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3988 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3989 getF32Constant(DAG, 0x3f7f5e7e));
3990 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3991 SDValue TwoToFractionalPartOfX =
3992 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3994 result = DAG.getNode(ISD::BITCAST, dl,
3995 MVT::f32, TwoToFractionalPartOfX);
3996 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3997 // For floating-point precision of 12:
3999 // TwoToFractionalPartOfX =
4002 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4004 // error 0.000107046256, which is 13 to 14 bits
4005 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4006 getF32Constant(DAG, 0x3da235e3));
4007 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4008 getF32Constant(DAG, 0x3e65b8f3));
4009 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4010 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4011 getF32Constant(DAG, 0x3f324b07));
4012 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4013 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4014 getF32Constant(DAG, 0x3f7ff8fd));
4015 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4016 SDValue TwoToFractionalPartOfX =
4017 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4019 result = DAG.getNode(ISD::BITCAST, dl,
4020 MVT::f32, TwoToFractionalPartOfX);
4021 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4022 // For floating-point precision of 18:
4024 // TwoToFractionalPartOfX =
4028 // (0.554906021e-1f +
4029 // (0.961591928e-2f +
4030 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4031 // error 2.47208000*10^(-7), which is better than 18 bits
4032 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4033 getF32Constant(DAG, 0x3924b03e));
4034 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4035 getF32Constant(DAG, 0x3ab24b87));
4036 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4037 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4038 getF32Constant(DAG, 0x3c1d8c17));
4039 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4040 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4041 getF32Constant(DAG, 0x3d634a1d));
4042 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4043 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4044 getF32Constant(DAG, 0x3e75fe14));
4045 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4046 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4047 getF32Constant(DAG, 0x3f317234));
4048 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4049 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4050 getF32Constant(DAG, 0x3f800000));
4051 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4052 SDValue TwoToFractionalPartOfX =
4053 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4055 result = DAG.getNode(ISD::BITCAST, dl,
4056 MVT::f32, TwoToFractionalPartOfX);
4059 // No special expansion.
4060 result = DAG.getNode(ISD::FPOW, dl,
4061 getValue(I.getArgOperand(0)).getValueType(),
4062 getValue(I.getArgOperand(0)),
4063 getValue(I.getArgOperand(1)));
4066 setValue(&I, result);
4070 /// ExpandPowI - Expand a llvm.powi intrinsic.
4071 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4072 SelectionDAG &DAG) {
4073 // If RHS is a constant, we can expand this out to a multiplication tree,
4074 // otherwise we end up lowering to a call to __powidf2 (for example). When
4075 // optimizing for size, we only want to do this if the expansion would produce
4076 // a small number of multiplies, otherwise we do the full expansion.
4077 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4078 // Get the exponent as a positive value.
4079 unsigned Val = RHSC->getSExtValue();
4080 if ((int)Val < 0) Val = -Val;
4082 // powi(x, 0) -> 1.0
4084 return DAG.getConstantFP(1.0, LHS.getValueType());
4086 const Function *F = DAG.getMachineFunction().getFunction();
4087 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4088 // If optimizing for size, don't insert too many multiplies. This
4089 // inserts up to 5 multiplies.
4090 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4091 // We use the simple binary decomposition method to generate the multiply
4092 // sequence. There are more optimal ways to do this (for example,
4093 // powi(x,15) generates one more multiply than it should), but this has
4094 // the benefit of being both really simple and much better than a libcall.
4095 SDValue Res; // Logically starts equal to 1.0
4096 SDValue CurSquare = LHS;
4100 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4102 Res = CurSquare; // 1.0*CurSquare.
4105 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4106 CurSquare, CurSquare);
4110 // If the original was negative, invert the result, producing 1/(x*x*x).
4111 if (RHSC->getSExtValue() < 0)
4112 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4113 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4118 // Otherwise, expand to a libcall.
4119 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4122 // getTruncatedArgReg - Find underlying register used for an truncated
4124 static unsigned getTruncatedArgReg(const SDValue &N) {
4125 if (N.getOpcode() != ISD::TRUNCATE)
4128 const SDValue &Ext = N.getOperand(0);
4129 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4130 const SDValue &CFR = Ext.getOperand(0);
4131 if (CFR.getOpcode() == ISD::CopyFromReg)
4132 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4134 if (CFR.getOpcode() == ISD::TRUNCATE)
4135 return getTruncatedArgReg(CFR);
4140 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4141 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4142 /// At the end of instruction selection, they will be inserted to the entry BB.
4144 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4147 const Argument *Arg = dyn_cast<Argument>(V);
4151 MachineFunction &MF = DAG.getMachineFunction();
4152 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4153 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4155 // Ignore inlined function arguments here.
4156 DIVariable DV(Variable);
4157 if (DV.isInlinedFnArgument(MF.getFunction()))
4161 if (Arg->hasByValAttr()) {
4162 // Byval arguments' frame index is recorded during argument lowering.
4163 // Use this info directly.
4164 Reg = TRI->getFrameRegister(MF);
4165 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4166 // If byval argument ofset is not recorded then ignore this.
4172 if (N.getOpcode() == ISD::CopyFromReg)
4173 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4175 Reg = getTruncatedArgReg(N);
4176 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4177 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4178 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4185 // Check if ValueMap has reg number.
4186 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4187 if (VMI != FuncInfo.ValueMap.end())
4191 if (!Reg && N.getNode()) {
4192 // Check if frame index is available.
4193 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4194 if (FrameIndexSDNode *FINode =
4195 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4196 Reg = TRI->getFrameRegister(MF);
4197 Offset = FINode->getIndex();
4204 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4205 TII->get(TargetOpcode::DBG_VALUE))
4206 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4207 FuncInfo.ArgDbgValues.push_back(&*MIB);
4211 // VisualStudio defines setjmp as _setjmp
4212 #if defined(_MSC_VER) && defined(setjmp) && \
4213 !defined(setjmp_undefined_for_msvc)
4214 # pragma push_macro("setjmp")
4216 # define setjmp_undefined_for_msvc
4219 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4220 /// we want to emit this as a call to a named external function, return the name
4221 /// otherwise lower it and return null.
4223 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4224 DebugLoc dl = getCurDebugLoc();
4227 switch (Intrinsic) {
4229 // By default, turn this into a target intrinsic node.
4230 visitTargetIntrinsic(I, Intrinsic);
4232 case Intrinsic::vastart: visitVAStart(I); return 0;
4233 case Intrinsic::vaend: visitVAEnd(I); return 0;
4234 case Intrinsic::vacopy: visitVACopy(I); return 0;
4235 case Intrinsic::returnaddress:
4236 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4237 getValue(I.getArgOperand(0))));
4239 case Intrinsic::frameaddress:
4240 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4241 getValue(I.getArgOperand(0))));
4243 case Intrinsic::setjmp:
4244 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4245 case Intrinsic::longjmp:
4246 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4247 case Intrinsic::memcpy: {
4248 // Assert for address < 256 since we support only user defined address
4250 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4252 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4254 "Unknown address space");
4255 SDValue Op1 = getValue(I.getArgOperand(0));
4256 SDValue Op2 = getValue(I.getArgOperand(1));
4257 SDValue Op3 = getValue(I.getArgOperand(2));
4258 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4259 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4260 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4261 MachinePointerInfo(I.getArgOperand(0)),
4262 MachinePointerInfo(I.getArgOperand(1))));
4265 case Intrinsic::memset: {
4266 // Assert for address < 256 since we support only user defined address
4268 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4270 "Unknown address space");
4271 SDValue Op1 = getValue(I.getArgOperand(0));
4272 SDValue Op2 = getValue(I.getArgOperand(1));
4273 SDValue Op3 = getValue(I.getArgOperand(2));
4274 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4275 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4276 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4277 MachinePointerInfo(I.getArgOperand(0))));
4280 case Intrinsic::memmove: {
4281 // Assert for address < 256 since we support only user defined address
4283 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4285 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4287 "Unknown address space");
4288 SDValue Op1 = getValue(I.getArgOperand(0));
4289 SDValue Op2 = getValue(I.getArgOperand(1));
4290 SDValue Op3 = getValue(I.getArgOperand(2));
4291 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4292 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4293 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4294 MachinePointerInfo(I.getArgOperand(0)),
4295 MachinePointerInfo(I.getArgOperand(1))));
4298 case Intrinsic::dbg_declare: {
4299 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4300 MDNode *Variable = DI.getVariable();
4301 const Value *Address = DI.getAddress();
4302 if (!Address || !DIVariable(DI.getVariable()).Verify())
4305 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4306 // but do not always have a corresponding SDNode built. The SDNodeOrder
4307 // absolute, but not relative, values are different depending on whether
4308 // debug info exists.
4311 // Check if address has undef value.
4312 if (isa<UndefValue>(Address) ||
4313 (Address->use_empty() && !isa<Argument>(Address))) {
4314 DEBUG(dbgs() << "Dropping debug info for " << DI);
4318 SDValue &N = NodeMap[Address];
4319 if (!N.getNode() && isa<Argument>(Address))
4320 // Check unused arguments map.
4321 N = UnusedArgNodeMap[Address];
4324 // Parameters are handled specially.
4326 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4327 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4328 Address = BCI->getOperand(0);
4329 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4331 if (isParameter && !AI) {
4332 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4334 // Byval parameter. We have a frame index at this point.
4335 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4336 0, dl, SDNodeOrder);
4338 // Address is an argument, so try to emit its dbg value using
4339 // virtual register info from the FuncInfo.ValueMap.
4340 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4344 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4345 0, dl, SDNodeOrder);
4347 // Can't do anything with other non-AI cases yet.
4348 DEBUG(dbgs() << "Dropping debug info for " << DI);
4351 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4353 // If Address is an argument then try to emit its dbg value using
4354 // virtual register info from the FuncInfo.ValueMap.
4355 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4356 // If variable is pinned by a alloca in dominating bb then
4357 // use StaticAllocaMap.
4358 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4359 if (AI->getParent() != DI.getParent()) {
4360 DenseMap<const AllocaInst*, int>::iterator SI =
4361 FuncInfo.StaticAllocaMap.find(AI);
4362 if (SI != FuncInfo.StaticAllocaMap.end()) {
4363 SDV = DAG.getDbgValue(Variable, SI->second,
4364 0, dl, SDNodeOrder);
4365 DAG.AddDbgValue(SDV, 0, false);
4370 DEBUG(dbgs() << "Dropping debug info for " << DI);
4375 case Intrinsic::dbg_value: {
4376 const DbgValueInst &DI = cast<DbgValueInst>(I);
4377 if (!DIVariable(DI.getVariable()).Verify())
4380 MDNode *Variable = DI.getVariable();
4381 uint64_t Offset = DI.getOffset();
4382 const Value *V = DI.getValue();
4386 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4387 // but do not always have a corresponding SDNode built. The SDNodeOrder
4388 // absolute, but not relative, values are different depending on whether
4389 // debug info exists.
4392 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4393 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4394 DAG.AddDbgValue(SDV, 0, false);
4396 // Do not use getValue() in here; we don't want to generate code at
4397 // this point if it hasn't been done yet.
4398 SDValue N = NodeMap[V];
4399 if (!N.getNode() && isa<Argument>(V))
4400 // Check unused arguments map.
4401 N = UnusedArgNodeMap[V];
4403 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4404 SDV = DAG.getDbgValue(Variable, N.getNode(),
4405 N.getResNo(), Offset, dl, SDNodeOrder);
4406 DAG.AddDbgValue(SDV, N.getNode(), false);
4408 } else if (!V->use_empty() ) {
4409 // Do not call getValue(V) yet, as we don't want to generate code.
4410 // Remember it for later.
4411 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4412 DanglingDebugInfoMap[V] = DDI;
4414 // We may expand this to cover more cases. One case where we have no
4415 // data available is an unreferenced parameter.
4416 DEBUG(dbgs() << "Dropping debug info for " << DI);
4420 // Build a debug info table entry.
4421 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4422 V = BCI->getOperand(0);
4423 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4424 // Don't handle byval struct arguments or VLAs, for example.
4427 DenseMap<const AllocaInst*, int>::iterator SI =
4428 FuncInfo.StaticAllocaMap.find(AI);
4429 if (SI == FuncInfo.StaticAllocaMap.end())
4431 int FI = SI->second;
4433 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4434 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4435 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4438 case Intrinsic::eh_exception: {
4439 // Insert the EXCEPTIONADDR instruction.
4440 assert(FuncInfo.MBB->isLandingPad() &&
4441 "Call to eh.exception not in landing pad!");
4442 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4444 Ops[0] = DAG.getRoot();
4445 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4447 DAG.setRoot(Op.getValue(1));
4451 case Intrinsic::eh_selector: {
4452 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4453 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4454 if (CallMBB->isLandingPad())
4455 AddCatchInfo(I, &MMI, CallMBB);
4458 FuncInfo.CatchInfoLost.insert(&I);
4460 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4461 unsigned Reg = TLI.getExceptionSelectorRegister();
4462 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4465 // Insert the EHSELECTION instruction.
4466 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4468 Ops[0] = getValue(I.getArgOperand(0));
4470 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4471 DAG.setRoot(Op.getValue(1));
4472 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4476 case Intrinsic::eh_typeid_for: {
4477 // Find the type id for the given typeinfo.
4478 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4479 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4480 Res = DAG.getConstant(TypeID, MVT::i32);
4485 case Intrinsic::eh_return_i32:
4486 case Intrinsic::eh_return_i64:
4487 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4488 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4491 getValue(I.getArgOperand(0)),
4492 getValue(I.getArgOperand(1))));
4494 case Intrinsic::eh_unwind_init:
4495 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4497 case Intrinsic::eh_dwarf_cfa: {
4498 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4499 TLI.getPointerTy());
4500 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4502 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4503 TLI.getPointerTy()),
4505 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4507 DAG.getConstant(0, TLI.getPointerTy()));
4508 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4512 case Intrinsic::eh_sjlj_callsite: {
4513 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4514 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4515 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4516 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4518 MMI.setCurrentCallSite(CI->getZExtValue());
4521 case Intrinsic::eh_sjlj_setjmp: {
4522 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4523 getValue(I.getArgOperand(0))));
4526 case Intrinsic::eh_sjlj_longjmp: {
4527 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4528 getRoot(), getValue(I.getArgOperand(0))));
4531 case Intrinsic::eh_sjlj_dispatch_setup: {
4532 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4533 getRoot(), getValue(I.getArgOperand(0))));
4537 case Intrinsic::x86_mmx_pslli_w:
4538 case Intrinsic::x86_mmx_pslli_d:
4539 case Intrinsic::x86_mmx_pslli_q:
4540 case Intrinsic::x86_mmx_psrli_w:
4541 case Intrinsic::x86_mmx_psrli_d:
4542 case Intrinsic::x86_mmx_psrli_q:
4543 case Intrinsic::x86_mmx_psrai_w:
4544 case Intrinsic::x86_mmx_psrai_d: {
4545 SDValue ShAmt = getValue(I.getArgOperand(1));
4546 if (isa<ConstantSDNode>(ShAmt)) {
4547 visitTargetIntrinsic(I, Intrinsic);
4550 unsigned NewIntrinsic = 0;
4551 EVT ShAmtVT = MVT::v2i32;
4552 switch (Intrinsic) {
4553 case Intrinsic::x86_mmx_pslli_w:
4554 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4556 case Intrinsic::x86_mmx_pslli_d:
4557 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4559 case Intrinsic::x86_mmx_pslli_q:
4560 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4562 case Intrinsic::x86_mmx_psrli_w:
4563 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4565 case Intrinsic::x86_mmx_psrli_d:
4566 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4568 case Intrinsic::x86_mmx_psrli_q:
4569 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4571 case Intrinsic::x86_mmx_psrai_w:
4572 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4574 case Intrinsic::x86_mmx_psrai_d:
4575 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4577 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4580 // The vector shift intrinsics with scalars uses 32b shift amounts but
4581 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4583 // We must do this early because v2i32 is not a legal type.
4584 DebugLoc dl = getCurDebugLoc();
4587 ShOps[1] = DAG.getConstant(0, MVT::i32);
4588 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4589 EVT DestVT = TLI.getValueType(I.getType());
4590 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4591 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4592 DAG.getConstant(NewIntrinsic, MVT::i32),
4593 getValue(I.getArgOperand(0)), ShAmt);
4597 case Intrinsic::convertff:
4598 case Intrinsic::convertfsi:
4599 case Intrinsic::convertfui:
4600 case Intrinsic::convertsif:
4601 case Intrinsic::convertuif:
4602 case Intrinsic::convertss:
4603 case Intrinsic::convertsu:
4604 case Intrinsic::convertus:
4605 case Intrinsic::convertuu: {
4606 ISD::CvtCode Code = ISD::CVT_INVALID;
4607 switch (Intrinsic) {
4608 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4609 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4610 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4611 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4612 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4613 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4614 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4615 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4616 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4618 EVT DestVT = TLI.getValueType(I.getType());
4619 const Value *Op1 = I.getArgOperand(0);
4620 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4621 DAG.getValueType(DestVT),
4622 DAG.getValueType(getValue(Op1).getValueType()),
4623 getValue(I.getArgOperand(1)),
4624 getValue(I.getArgOperand(2)),
4629 case Intrinsic::sqrt:
4630 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4631 getValue(I.getArgOperand(0)).getValueType(),
4632 getValue(I.getArgOperand(0))));
4634 case Intrinsic::powi:
4635 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4636 getValue(I.getArgOperand(1)), DAG));
4638 case Intrinsic::sin:
4639 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4640 getValue(I.getArgOperand(0)).getValueType(),
4641 getValue(I.getArgOperand(0))));
4643 case Intrinsic::cos:
4644 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4645 getValue(I.getArgOperand(0)).getValueType(),
4646 getValue(I.getArgOperand(0))));
4648 case Intrinsic::log:
4651 case Intrinsic::log2:
4654 case Intrinsic::log10:
4657 case Intrinsic::exp:
4660 case Intrinsic::exp2:
4663 case Intrinsic::pow:
4666 case Intrinsic::fma:
4667 setValue(&I, DAG.getNode(ISD::FMA, dl,
4668 getValue(I.getArgOperand(0)).getValueType(),
4669 getValue(I.getArgOperand(0)),
4670 getValue(I.getArgOperand(1)),
4671 getValue(I.getArgOperand(2))));
4673 case Intrinsic::convert_to_fp16:
4674 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4675 MVT::i16, getValue(I.getArgOperand(0))));
4677 case Intrinsic::convert_from_fp16:
4678 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4679 MVT::f32, getValue(I.getArgOperand(0))));
4681 case Intrinsic::pcmarker: {
4682 SDValue Tmp = getValue(I.getArgOperand(0));
4683 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4686 case Intrinsic::readcyclecounter: {
4687 SDValue Op = getRoot();
4688 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4689 DAG.getVTList(MVT::i64, MVT::Other),
4692 DAG.setRoot(Res.getValue(1));
4695 case Intrinsic::bswap:
4696 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4697 getValue(I.getArgOperand(0)).getValueType(),
4698 getValue(I.getArgOperand(0))));
4700 case Intrinsic::cttz: {
4701 SDValue Arg = getValue(I.getArgOperand(0));
4702 EVT Ty = Arg.getValueType();
4703 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4706 case Intrinsic::ctlz: {
4707 SDValue Arg = getValue(I.getArgOperand(0));
4708 EVT Ty = Arg.getValueType();
4709 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4712 case Intrinsic::ctpop: {
4713 SDValue Arg = getValue(I.getArgOperand(0));
4714 EVT Ty = Arg.getValueType();
4715 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4718 case Intrinsic::stacksave: {
4719 SDValue Op = getRoot();
4720 Res = DAG.getNode(ISD::STACKSAVE, dl,
4721 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4723 DAG.setRoot(Res.getValue(1));
4726 case Intrinsic::stackrestore: {
4727 Res = getValue(I.getArgOperand(0));
4728 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4731 case Intrinsic::stackprotector: {
4732 // Emit code into the DAG to store the stack guard onto the stack.
4733 MachineFunction &MF = DAG.getMachineFunction();
4734 MachineFrameInfo *MFI = MF.getFrameInfo();
4735 EVT PtrTy = TLI.getPointerTy();
4737 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4738 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4740 int FI = FuncInfo.StaticAllocaMap[Slot];
4741 MFI->setStackProtectorIndex(FI);
4743 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4745 // Store the stack protector onto the stack.
4746 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4747 MachinePointerInfo::getFixedStack(FI),
4753 case Intrinsic::objectsize: {
4754 // If we don't know by now, we're never going to know.
4755 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4757 assert(CI && "Non-constant type in __builtin_object_size?");
4759 SDValue Arg = getValue(I.getCalledValue());
4760 EVT Ty = Arg.getValueType();
4763 Res = DAG.getConstant(-1ULL, Ty);
4765 Res = DAG.getConstant(0, Ty);
4770 case Intrinsic::var_annotation:
4771 // Discard annotate attributes
4774 case Intrinsic::init_trampoline: {
4775 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4779 Ops[1] = getValue(I.getArgOperand(0));
4780 Ops[2] = getValue(I.getArgOperand(1));
4781 Ops[3] = getValue(I.getArgOperand(2));
4782 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4783 Ops[5] = DAG.getSrcValue(F);
4785 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4786 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4790 DAG.setRoot(Res.getValue(1));
4793 case Intrinsic::gcroot:
4795 const Value *Alloca = I.getArgOperand(0);
4796 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4798 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4799 GFI->addStackRoot(FI->getIndex(), TypeMap);
4802 case Intrinsic::gcread:
4803 case Intrinsic::gcwrite:
4804 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4806 case Intrinsic::flt_rounds:
4807 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4810 case Intrinsic::expect: {
4811 // Just replace __builtin_expect(exp, c) with EXP.
4812 setValue(&I, getValue(I.getArgOperand(0)));
4816 case Intrinsic::trap: {
4817 StringRef TrapFuncName = getTrapFunctionName();
4818 if (TrapFuncName.empty()) {
4819 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4822 TargetLowering::ArgListTy Args;
4823 std::pair<SDValue, SDValue> Result =
4824 TLI.LowerCallTo(getRoot(), I.getType(),
4825 false, false, false, false, 0, CallingConv::C,
4826 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
4827 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4828 Args, DAG, getCurDebugLoc());
4829 DAG.setRoot(Result.second);
4832 case Intrinsic::uadd_with_overflow:
4833 return implVisitAluOverflow(I, ISD::UADDO);
4834 case Intrinsic::sadd_with_overflow:
4835 return implVisitAluOverflow(I, ISD::SADDO);
4836 case Intrinsic::usub_with_overflow:
4837 return implVisitAluOverflow(I, ISD::USUBO);
4838 case Intrinsic::ssub_with_overflow:
4839 return implVisitAluOverflow(I, ISD::SSUBO);
4840 case Intrinsic::umul_with_overflow:
4841 return implVisitAluOverflow(I, ISD::UMULO);
4842 case Intrinsic::smul_with_overflow:
4843 return implVisitAluOverflow(I, ISD::SMULO);
4845 case Intrinsic::prefetch: {
4847 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4849 Ops[1] = getValue(I.getArgOperand(0));
4850 Ops[2] = getValue(I.getArgOperand(1));
4851 Ops[3] = getValue(I.getArgOperand(2));
4852 Ops[4] = getValue(I.getArgOperand(3));
4853 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4854 DAG.getVTList(MVT::Other),
4856 EVT::getIntegerVT(*Context, 8),
4857 MachinePointerInfo(I.getArgOperand(0)),
4859 false, /* volatile */
4861 rw==1)); /* write */
4864 case Intrinsic::memory_barrier: {
4867 for (int x = 1; x < 6; ++x)
4868 Ops[x] = getValue(I.getArgOperand(x - 1));
4870 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4873 case Intrinsic::atomic_cmp_swap: {
4874 SDValue Root = getRoot();
4876 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4877 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4879 getValue(I.getArgOperand(0)),
4880 getValue(I.getArgOperand(1)),
4881 getValue(I.getArgOperand(2)),
4882 MachinePointerInfo(I.getArgOperand(0)));
4884 DAG.setRoot(L.getValue(1));
4887 case Intrinsic::atomic_load_add:
4888 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4889 case Intrinsic::atomic_load_sub:
4890 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4891 case Intrinsic::atomic_load_or:
4892 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4893 case Intrinsic::atomic_load_xor:
4894 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4895 case Intrinsic::atomic_load_and:
4896 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4897 case Intrinsic::atomic_load_nand:
4898 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4899 case Intrinsic::atomic_load_max:
4900 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4901 case Intrinsic::atomic_load_min:
4902 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4903 case Intrinsic::atomic_load_umin:
4904 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4905 case Intrinsic::atomic_load_umax:
4906 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4907 case Intrinsic::atomic_swap:
4908 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4910 case Intrinsic::invariant_start:
4911 case Intrinsic::lifetime_start:
4912 // Discard region information.
4913 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4915 case Intrinsic::invariant_end:
4916 case Intrinsic::lifetime_end:
4917 // Discard region information.
4922 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4924 MachineBasicBlock *LandingPad) {
4925 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4926 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4927 Type *RetTy = FTy->getReturnType();
4928 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4929 MCSymbol *BeginLabel = 0;
4931 TargetLowering::ArgListTy Args;
4932 TargetLowering::ArgListEntry Entry;
4933 Args.reserve(CS.arg_size());
4935 // Check whether the function can return without sret-demotion.
4936 SmallVector<ISD::OutputArg, 4> Outs;
4937 SmallVector<uint64_t, 4> Offsets;
4938 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4939 Outs, TLI, &Offsets);
4941 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4942 DAG.getMachineFunction(),
4943 FTy->isVarArg(), Outs,
4946 SDValue DemoteStackSlot;
4947 int DemoteStackIdx = -100;
4949 if (!CanLowerReturn) {
4950 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4951 FTy->getReturnType());
4952 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4953 FTy->getReturnType());
4954 MachineFunction &MF = DAG.getMachineFunction();
4955 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4956 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4958 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4959 Entry.Node = DemoteStackSlot;
4960 Entry.Ty = StackSlotPtrType;
4961 Entry.isSExt = false;
4962 Entry.isZExt = false;
4963 Entry.isInReg = false;
4964 Entry.isSRet = true;
4965 Entry.isNest = false;
4966 Entry.isByVal = false;
4967 Entry.Alignment = Align;
4968 Args.push_back(Entry);
4969 RetTy = Type::getVoidTy(FTy->getContext());
4972 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4974 const Value *V = *i;
4977 if (V->getType()->isEmptyTy())
4980 SDValue ArgNode = getValue(V);
4981 Entry.Node = ArgNode; Entry.Ty = V->getType();
4983 unsigned attrInd = i - CS.arg_begin() + 1;
4984 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4985 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4986 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4987 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4988 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4989 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4990 Entry.Alignment = CS.getParamAlignment(attrInd);
4991 Args.push_back(Entry);
4995 // Insert a label before the invoke call to mark the try range. This can be
4996 // used to detect deletion of the invoke via the MachineModuleInfo.
4997 BeginLabel = MMI.getContext().CreateTempSymbol();
4999 // For SjLj, keep track of which landing pads go with which invokes
5000 // so as to maintain the ordering of pads in the LSDA.
5001 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5002 if (CallSiteIndex) {
5003 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5004 // Now that the call site is handled, stop tracking it.
5005 MMI.setCurrentCallSite(0);
5008 // Both PendingLoads and PendingExports must be flushed here;
5009 // this call might not return.
5011 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5014 // Check if target-independent constraints permit a tail call here.
5015 // Target-dependent constraints are checked within TLI.LowerCallTo.
5017 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5020 // If there's a possibility that fast-isel has already selected some amount
5021 // of the current basic block, don't emit a tail call.
5022 if (isTailCall && EnableFastISel)
5025 std::pair<SDValue,SDValue> Result =
5026 TLI.LowerCallTo(getRoot(), RetTy,
5027 CS.paramHasAttr(0, Attribute::SExt),
5028 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5029 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5030 CS.getCallingConv(),
5032 !CS.getInstruction()->use_empty(),
5033 Callee, Args, DAG, getCurDebugLoc());
5034 assert((isTailCall || Result.second.getNode()) &&
5035 "Non-null chain expected with non-tail call!");
5036 assert((Result.second.getNode() || !Result.first.getNode()) &&
5037 "Null value expected with tail call!");
5038 if (Result.first.getNode()) {
5039 setValue(CS.getInstruction(), Result.first);
5040 } else if (!CanLowerReturn && Result.second.getNode()) {
5041 // The instruction result is the result of loading from the
5042 // hidden sret parameter.
5043 SmallVector<EVT, 1> PVTs;
5044 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5046 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5047 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5048 EVT PtrVT = PVTs[0];
5049 unsigned NumValues = Outs.size();
5050 SmallVector<SDValue, 4> Values(NumValues);
5051 SmallVector<SDValue, 4> Chains(NumValues);
5053 for (unsigned i = 0; i < NumValues; ++i) {
5054 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5056 DAG.getConstant(Offsets[i], PtrVT));
5057 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5059 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5062 Chains[i] = L.getValue(1);
5065 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5066 MVT::Other, &Chains[0], NumValues);
5067 PendingLoads.push_back(Chain);
5069 // Collect the legal value parts into potentially illegal values
5070 // that correspond to the original function's return values.
5071 SmallVector<EVT, 4> RetTys;
5072 RetTy = FTy->getReturnType();
5073 ComputeValueVTs(TLI, RetTy, RetTys);
5074 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5075 SmallVector<SDValue, 4> ReturnValues;
5076 unsigned CurReg = 0;
5077 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5079 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5080 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5082 SDValue ReturnValue =
5083 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5084 RegisterVT, VT, AssertOp);
5085 ReturnValues.push_back(ReturnValue);
5089 setValue(CS.getInstruction(),
5090 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5091 DAG.getVTList(&RetTys[0], RetTys.size()),
5092 &ReturnValues[0], ReturnValues.size()));
5095 // Assign order to nodes here. If the call does not produce a result, it won't
5096 // be mapped to a SDNode and visit() will not assign it an order number.
5097 if (!Result.second.getNode()) {
5098 // As a special case, a null chain means that a tail call has been emitted and
5099 // the DAG root is already updated.
5102 AssignOrderingToNode(DAG.getRoot().getNode());
5104 DAG.setRoot(Result.second);
5106 AssignOrderingToNode(Result.second.getNode());
5110 // Insert a label at the end of the invoke call to mark the try range. This
5111 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5112 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5113 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5115 // Inform MachineModuleInfo of range.
5116 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5120 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5121 /// value is equal or not-equal to zero.
5122 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5123 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5125 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5126 if (IC->isEquality())
5127 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5128 if (C->isNullValue())
5130 // Unknown instruction.
5136 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5138 SelectionDAGBuilder &Builder) {
5140 // Check to see if this load can be trivially constant folded, e.g. if the
5141 // input is from a string literal.
5142 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5143 // Cast pointer to the type we really want to load.
5144 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5145 PointerType::getUnqual(LoadTy));
5147 if (const Constant *LoadCst =
5148 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5150 return Builder.getValue(LoadCst);
5153 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5154 // still constant memory, the input chain can be the entry node.
5156 bool ConstantMemory = false;
5158 // Do not serialize (non-volatile) loads of constant memory with anything.
5159 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5160 Root = Builder.DAG.getEntryNode();
5161 ConstantMemory = true;
5163 // Do not serialize non-volatile loads against each other.
5164 Root = Builder.DAG.getRoot();
5167 SDValue Ptr = Builder.getValue(PtrVal);
5168 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5169 Ptr, MachinePointerInfo(PtrVal),
5171 false /*nontemporal*/, 1 /* align=1 */);
5173 if (!ConstantMemory)
5174 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5179 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5180 /// If so, return true and lower it, otherwise return false and it will be
5181 /// lowered like a normal call.
5182 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5183 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5184 if (I.getNumArgOperands() != 3)
5187 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5188 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5189 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5190 !I.getType()->isIntegerTy())
5193 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5195 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5196 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5197 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5198 bool ActuallyDoIt = true;
5201 switch (Size->getZExtValue()) {
5203 LoadVT = MVT::Other;
5205 ActuallyDoIt = false;
5209 LoadTy = Type::getInt16Ty(Size->getContext());
5213 LoadTy = Type::getInt32Ty(Size->getContext());
5217 LoadTy = Type::getInt64Ty(Size->getContext());
5221 LoadVT = MVT::v4i32;
5222 LoadTy = Type::getInt32Ty(Size->getContext());
5223 LoadTy = VectorType::get(LoadTy, 4);
5228 // This turns into unaligned loads. We only do this if the target natively
5229 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5230 // we'll only produce a small number of byte loads.
5232 // Require that we can find a legal MVT, and only do this if the target
5233 // supports unaligned loads of that type. Expanding into byte loads would
5235 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5236 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5237 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5238 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5239 ActuallyDoIt = false;
5243 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5244 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5246 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5248 EVT CallVT = TLI.getValueType(I.getType(), true);
5249 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5259 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5260 // Handle inline assembly differently.
5261 if (isa<InlineAsm>(I.getCalledValue())) {
5266 // See if any floating point values are being passed to this function. This is
5267 // used to emit an undefined reference to fltused on Windows.
5269 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5270 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5271 if (FT->isVarArg() &&
5272 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5273 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5274 Type* T = I.getArgOperand(i)->getType();
5275 for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
5277 if (!i->isFloatingPointTy()) continue;
5278 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5284 const char *RenameFn = 0;
5285 if (Function *F = I.getCalledFunction()) {
5286 if (F->isDeclaration()) {
5287 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5288 if (unsigned IID = II->getIntrinsicID(F)) {
5289 RenameFn = visitIntrinsicCall(I, IID);
5294 if (unsigned IID = F->getIntrinsicID()) {
5295 RenameFn = visitIntrinsicCall(I, IID);
5301 // Check for well-known libc/libm calls. If the function is internal, it
5302 // can't be a library call.
5303 if (!F->hasLocalLinkage() && F->hasName()) {
5304 StringRef Name = F->getName();
5305 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5306 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5307 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5308 I.getType() == I.getArgOperand(0)->getType() &&
5309 I.getType() == I.getArgOperand(1)->getType()) {
5310 SDValue LHS = getValue(I.getArgOperand(0));
5311 SDValue RHS = getValue(I.getArgOperand(1));
5312 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5313 LHS.getValueType(), LHS, RHS));
5316 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5317 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5318 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5319 I.getType() == I.getArgOperand(0)->getType()) {
5320 SDValue Tmp = getValue(I.getArgOperand(0));
5321 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5322 Tmp.getValueType(), Tmp));
5325 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5326 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5327 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5328 I.getType() == I.getArgOperand(0)->getType() &&
5329 I.onlyReadsMemory()) {
5330 SDValue Tmp = getValue(I.getArgOperand(0));
5331 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5332 Tmp.getValueType(), Tmp));
5335 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5336 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5337 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5338 I.getType() == I.getArgOperand(0)->getType() &&
5339 I.onlyReadsMemory()) {
5340 SDValue Tmp = getValue(I.getArgOperand(0));
5341 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5342 Tmp.getValueType(), Tmp));
5345 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5346 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5347 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5348 I.getType() == I.getArgOperand(0)->getType() &&
5349 I.onlyReadsMemory()) {
5350 SDValue Tmp = getValue(I.getArgOperand(0));
5351 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5352 Tmp.getValueType(), Tmp));
5355 } else if (Name == "memcmp") {
5356 if (visitMemCmpCall(I))
5364 Callee = getValue(I.getCalledValue());
5366 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5368 // Check if we can potentially perform a tail call. More detailed checking is
5369 // be done within LowerCallTo, after more information about the call is known.
5370 LowerCallTo(&I, Callee, I.isTailCall());
5375 /// AsmOperandInfo - This contains information for each constraint that we are
5377 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5379 /// CallOperand - If this is the result output operand or a clobber
5380 /// this is null, otherwise it is the incoming operand to the CallInst.
5381 /// This gets modified as the asm is processed.
5382 SDValue CallOperand;
5384 /// AssignedRegs - If this is a register or register class operand, this
5385 /// contains the set of register corresponding to the operand.
5386 RegsForValue AssignedRegs;
5388 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5389 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5392 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5393 /// busy in OutputRegs/InputRegs.
5394 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5395 std::set<unsigned> &OutputRegs,
5396 std::set<unsigned> &InputRegs,
5397 const TargetRegisterInfo &TRI) const {
5399 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5400 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5403 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5404 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5408 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5409 /// corresponds to. If there is no Value* for this operand, it returns
5411 EVT getCallOperandValEVT(LLVMContext &Context,
5412 const TargetLowering &TLI,
5413 const TargetData *TD) const {
5414 if (CallOperandVal == 0) return MVT::Other;
5416 if (isa<BasicBlock>(CallOperandVal))
5417 return TLI.getPointerTy();
5419 llvm::Type *OpTy = CallOperandVal->getType();
5421 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5422 // If this is an indirect operand, the operand is a pointer to the
5425 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5427 report_fatal_error("Indirect operand for inline asm not a pointer!");
5428 OpTy = PtrTy->getElementType();
5431 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5432 if (StructType *STy = dyn_cast<StructType>(OpTy))
5433 if (STy->getNumElements() == 1)
5434 OpTy = STy->getElementType(0);
5436 // If OpTy is not a single value, it may be a struct/union that we
5437 // can tile with integers.
5438 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5439 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5448 OpTy = IntegerType::get(Context, BitSize);
5453 return TLI.getValueType(OpTy, true);
5457 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5459 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5460 const TargetRegisterInfo &TRI) {
5461 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5463 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5464 for (; *Aliases; ++Aliases)
5465 Regs.insert(*Aliases);
5469 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5471 } // end anonymous namespace
5473 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5474 /// specified operand. We prefer to assign virtual registers, to allow the
5475 /// register allocator to handle the assignment process. However, if the asm
5476 /// uses features that we can't model on machineinstrs, we have SDISel do the
5477 /// allocation. This produces generally horrible, but correct, code.
5479 /// OpInfo describes the operand.
5480 /// Input and OutputRegs are the set of already allocated physical registers.
5482 static void GetRegistersForValue(SelectionDAG &DAG,
5483 const TargetLowering &TLI,
5485 SDISelAsmOperandInfo &OpInfo,
5486 std::set<unsigned> &OutputRegs,
5487 std::set<unsigned> &InputRegs) {
5488 LLVMContext &Context = *DAG.getContext();
5490 // Compute whether this value requires an input register, an output register,
5492 bool isOutReg = false;
5493 bool isInReg = false;
5494 switch (OpInfo.Type) {
5495 case InlineAsm::isOutput:
5498 // If there is an input constraint that matches this, we need to reserve
5499 // the input register so no other inputs allocate to it.
5500 isInReg = OpInfo.hasMatchingInput();
5502 case InlineAsm::isInput:
5506 case InlineAsm::isClobber:
5513 MachineFunction &MF = DAG.getMachineFunction();
5514 SmallVector<unsigned, 4> Regs;
5516 // If this is a constraint for a single physreg, or a constraint for a
5517 // register class, find it.
5518 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5519 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5520 OpInfo.ConstraintVT);
5522 unsigned NumRegs = 1;
5523 if (OpInfo.ConstraintVT != MVT::Other) {
5524 // If this is a FP input in an integer register (or visa versa) insert a bit
5525 // cast of the input value. More generally, handle any case where the input
5526 // value disagrees with the register class we plan to stick this in.
5527 if (OpInfo.Type == InlineAsm::isInput &&
5528 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5529 // Try to convert to the first EVT that the reg class contains. If the
5530 // types are identical size, use a bitcast to convert (e.g. two differing
5532 EVT RegVT = *PhysReg.second->vt_begin();
5533 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5534 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5535 RegVT, OpInfo.CallOperand);
5536 OpInfo.ConstraintVT = RegVT;
5537 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5538 // If the input is a FP value and we want it in FP registers, do a
5539 // bitcast to the corresponding integer type. This turns an f64 value
5540 // into i64, which can be passed with two i32 values on a 32-bit
5542 RegVT = EVT::getIntegerVT(Context,
5543 OpInfo.ConstraintVT.getSizeInBits());
5544 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5545 RegVT, OpInfo.CallOperand);
5546 OpInfo.ConstraintVT = RegVT;
5550 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5554 EVT ValueVT = OpInfo.ConstraintVT;
5556 // If this is a constraint for a specific physical register, like {r17},
5558 if (unsigned AssignedReg = PhysReg.first) {
5559 const TargetRegisterClass *RC = PhysReg.second;
5560 if (OpInfo.ConstraintVT == MVT::Other)
5561 ValueVT = *RC->vt_begin();
5563 // Get the actual register value type. This is important, because the user
5564 // may have asked for (e.g.) the AX register in i32 type. We need to
5565 // remember that AX is actually i16 to get the right extension.
5566 RegVT = *RC->vt_begin();
5568 // This is a explicit reference to a physical register.
5569 Regs.push_back(AssignedReg);
5571 // If this is an expanded reference, add the rest of the regs to Regs.
5573 TargetRegisterClass::iterator I = RC->begin();
5574 for (; *I != AssignedReg; ++I)
5575 assert(I != RC->end() && "Didn't find reg!");
5577 // Already added the first reg.
5579 for (; NumRegs; --NumRegs, ++I) {
5580 assert(I != RC->end() && "Ran out of registers to allocate!");
5585 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5586 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5587 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5591 // Otherwise, if this was a reference to an LLVM register class, create vregs
5592 // for this reference.
5593 if (const TargetRegisterClass *RC = PhysReg.second) {
5594 RegVT = *RC->vt_begin();
5595 if (OpInfo.ConstraintVT == MVT::Other)
5598 // Create the appropriate number of virtual registers.
5599 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5600 for (; NumRegs; --NumRegs)
5601 Regs.push_back(RegInfo.createVirtualRegister(RC));
5603 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5607 // Otherwise, we couldn't allocate enough registers for this.
5610 /// visitInlineAsm - Handle a call to an InlineAsm object.
5612 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5613 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5615 /// ConstraintOperands - Information about all of the constraints.
5616 SDISelAsmOperandInfoVector ConstraintOperands;
5618 std::set<unsigned> OutputRegs, InputRegs;
5620 TargetLowering::AsmOperandInfoVector
5621 TargetConstraints = TLI.ParseConstraints(CS);
5623 bool hasMemory = false;
5625 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5626 unsigned ResNo = 0; // ResNo - The result number of the next output.
5627 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5628 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5629 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5631 EVT OpVT = MVT::Other;
5633 // Compute the value type for each operand.
5634 switch (OpInfo.Type) {
5635 case InlineAsm::isOutput:
5636 // Indirect outputs just consume an argument.
5637 if (OpInfo.isIndirect) {
5638 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5642 // The return value of the call is this value. As such, there is no
5643 // corresponding argument.
5644 assert(!CS.getType()->isVoidTy() &&
5646 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5647 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5649 assert(ResNo == 0 && "Asm only has one result!");
5650 OpVT = TLI.getValueType(CS.getType());
5654 case InlineAsm::isInput:
5655 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5657 case InlineAsm::isClobber:
5662 // If this is an input or an indirect output, process the call argument.
5663 // BasicBlocks are labels, currently appearing only in asm's.
5664 if (OpInfo.CallOperandVal) {
5665 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5666 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5668 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5671 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5674 OpInfo.ConstraintVT = OpVT;
5676 // Indirect operand accesses access memory.
5677 if (OpInfo.isIndirect)
5680 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5681 TargetLowering::ConstraintType
5682 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5683 if (CType == TargetLowering::C_Memory) {
5691 SDValue Chain, Flag;
5693 // We won't need to flush pending loads if this asm doesn't touch
5694 // memory and is nonvolatile.
5695 if (hasMemory || IA->hasSideEffects())
5698 Chain = DAG.getRoot();
5700 // Second pass over the constraints: compute which constraint option to use
5701 // and assign registers to constraints that want a specific physreg.
5702 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5703 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5705 // If this is an output operand with a matching input operand, look up the
5706 // matching input. If their types mismatch, e.g. one is an integer, the
5707 // other is floating point, or their sizes are different, flag it as an
5709 if (OpInfo.hasMatchingInput()) {
5710 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5712 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5713 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5714 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
5715 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5716 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
5717 if ((OpInfo.ConstraintVT.isInteger() !=
5718 Input.ConstraintVT.isInteger()) ||
5719 (MatchRC.second != InputRC.second)) {
5720 report_fatal_error("Unsupported asm: input constraint"
5721 " with a matching output constraint of"
5722 " incompatible type!");
5724 Input.ConstraintVT = OpInfo.ConstraintVT;
5728 // Compute the constraint code and ConstraintType to use.
5729 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5731 // If this is a memory input, and if the operand is not indirect, do what we
5732 // need to to provide an address for the memory input.
5733 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5734 !OpInfo.isIndirect) {
5735 assert((OpInfo.isMultipleAlternative ||
5736 (OpInfo.Type == InlineAsm::isInput)) &&
5737 "Can only indirectify direct input operands!");
5739 // Memory operands really want the address of the value. If we don't have
5740 // an indirect input, put it in the constpool if we can, otherwise spill
5741 // it to a stack slot.
5742 // TODO: This isn't quite right. We need to handle these according to
5743 // the addressing mode that the constraint wants. Also, this may take
5744 // an additional register for the computation and we don't want that
5747 // If the operand is a float, integer, or vector constant, spill to a
5748 // constant pool entry to get its address.
5749 const Value *OpVal = OpInfo.CallOperandVal;
5750 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5751 isa<ConstantVector>(OpVal)) {
5752 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5753 TLI.getPointerTy());
5755 // Otherwise, create a stack slot and emit a store to it before the
5757 Type *Ty = OpVal->getType();
5758 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5759 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5760 MachineFunction &MF = DAG.getMachineFunction();
5761 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5762 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5763 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5764 OpInfo.CallOperand, StackSlot,
5765 MachinePointerInfo::getFixedStack(SSFI),
5767 OpInfo.CallOperand = StackSlot;
5770 // There is no longer a Value* corresponding to this operand.
5771 OpInfo.CallOperandVal = 0;
5773 // It is now an indirect operand.
5774 OpInfo.isIndirect = true;
5777 // If this constraint is for a specific register, allocate it before
5779 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5780 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5784 // Second pass - Loop over all of the operands, assigning virtual or physregs
5785 // to register class operands.
5786 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5787 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5789 // C_Register operands have already been allocated, Other/Memory don't need
5791 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5792 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
5796 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5797 std::vector<SDValue> AsmNodeOperands;
5798 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5799 AsmNodeOperands.push_back(
5800 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5801 TLI.getPointerTy()));
5803 // If we have a !srcloc metadata node associated with it, we want to attach
5804 // this to the ultimately generated inline asm machineinstr. To do this, we
5805 // pass in the third operand as this (potentially null) inline asm MDNode.
5806 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5807 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5809 // Remember the HasSideEffect and AlignStack bits as operand 3.
5810 unsigned ExtraInfo = 0;
5811 if (IA->hasSideEffects())
5812 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5813 if (IA->isAlignStack())
5814 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5815 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5816 TLI.getPointerTy()));
5818 // Loop over all of the inputs, copying the operand values into the
5819 // appropriate registers and processing the output regs.
5820 RegsForValue RetValRegs;
5822 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5823 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5825 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5826 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5828 switch (OpInfo.Type) {
5829 case InlineAsm::isOutput: {
5830 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5831 OpInfo.ConstraintType != TargetLowering::C_Register) {
5832 // Memory output, or 'other' output (e.g. 'X' constraint).
5833 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5835 // Add information to the INLINEASM node to know about this output.
5836 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5837 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5838 TLI.getPointerTy()));
5839 AsmNodeOperands.push_back(OpInfo.CallOperand);
5843 // Otherwise, this is a register or register class output.
5845 // Copy the output from the appropriate register. Find a register that
5847 if (OpInfo.AssignedRegs.Regs.empty())
5848 report_fatal_error("Couldn't allocate output reg for constraint '" +
5849 Twine(OpInfo.ConstraintCode) + "'!");
5851 // If this is an indirect operand, store through the pointer after the
5853 if (OpInfo.isIndirect) {
5854 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5855 OpInfo.CallOperandVal));
5857 // This is the result value of the call.
5858 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5859 // Concatenate this output onto the outputs list.
5860 RetValRegs.append(OpInfo.AssignedRegs);
5863 // Add information to the INLINEASM node to know that this register is
5865 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5866 InlineAsm::Kind_RegDefEarlyClobber :
5867 InlineAsm::Kind_RegDef,
5874 case InlineAsm::isInput: {
5875 SDValue InOperandVal = OpInfo.CallOperand;
5877 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5878 // If this is required to match an output register we have already set,
5879 // just use its register.
5880 unsigned OperandNo = OpInfo.getMatchedOperand();
5882 // Scan until we find the definition we already emitted of this operand.
5883 // When we find it, create a RegsForValue operand.
5884 unsigned CurOp = InlineAsm::Op_FirstOperand;
5885 for (; OperandNo; --OperandNo) {
5886 // Advance to the next operand.
5888 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5889 assert((InlineAsm::isRegDefKind(OpFlag) ||
5890 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5891 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5892 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5896 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5897 if (InlineAsm::isRegDefKind(OpFlag) ||
5898 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5899 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5900 if (OpInfo.isIndirect) {
5901 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5902 LLVMContext &Ctx = *DAG.getContext();
5903 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5904 " don't know how to handle tied "
5905 "indirect register inputs");
5908 RegsForValue MatchedRegs;
5909 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5910 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5911 MatchedRegs.RegVTs.push_back(RegVT);
5912 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5913 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5915 MatchedRegs.Regs.push_back
5916 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5918 // Use the produced MatchedRegs object to
5919 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5921 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5922 true, OpInfo.getMatchedOperand(),
5923 DAG, AsmNodeOperands);
5927 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5928 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5929 "Unexpected number of operands");
5930 // Add information to the INLINEASM node to know about this input.
5931 // See InlineAsm.h isUseOperandTiedToDef.
5932 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5933 OpInfo.getMatchedOperand());
5934 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5935 TLI.getPointerTy()));
5936 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5940 // Treat indirect 'X' constraint as memory.
5941 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5943 OpInfo.ConstraintType = TargetLowering::C_Memory;
5945 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5946 std::vector<SDValue> Ops;
5947 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
5950 report_fatal_error("Invalid operand for inline asm constraint '" +
5951 Twine(OpInfo.ConstraintCode) + "'!");
5953 // Add information to the INLINEASM node to know about this input.
5954 unsigned ResOpType =
5955 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5956 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5957 TLI.getPointerTy()));
5958 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5962 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5963 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5964 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5965 "Memory operands expect pointer values");
5967 // Add information to the INLINEASM node to know about this input.
5968 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5969 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5970 TLI.getPointerTy()));
5971 AsmNodeOperands.push_back(InOperandVal);
5975 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5976 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5977 "Unknown constraint type!");
5978 assert(!OpInfo.isIndirect &&
5979 "Don't know how to handle indirect register inputs yet!");
5981 // Copy the input into the appropriate registers.
5982 if (OpInfo.AssignedRegs.Regs.empty())
5983 report_fatal_error("Couldn't allocate input reg for constraint '" +
5984 Twine(OpInfo.ConstraintCode) + "'!");
5986 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5989 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5990 DAG, AsmNodeOperands);
5993 case InlineAsm::isClobber: {
5994 // Add the clobbered value to the operand list, so that the register
5995 // allocator is aware that the physreg got clobbered.
5996 if (!OpInfo.AssignedRegs.Regs.empty())
5997 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6005 // Finish up input operands. Set the input chain and add the flag last.
6006 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6007 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6009 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6010 DAG.getVTList(MVT::Other, MVT::Glue),
6011 &AsmNodeOperands[0], AsmNodeOperands.size());
6012 Flag = Chain.getValue(1);
6014 // If this asm returns a register value, copy the result from that register
6015 // and set it as the value of the call.
6016 if (!RetValRegs.Regs.empty()) {
6017 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6020 // FIXME: Why don't we do this for inline asms with MRVs?
6021 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6022 EVT ResultType = TLI.getValueType(CS.getType());
6024 // If any of the results of the inline asm is a vector, it may have the
6025 // wrong width/num elts. This can happen for register classes that can
6026 // contain multiple different value types. The preg or vreg allocated may
6027 // not have the same VT as was expected. Convert it to the right type
6028 // with bit_convert.
6029 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6030 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6033 } else if (ResultType != Val.getValueType() &&
6034 ResultType.isInteger() && Val.getValueType().isInteger()) {
6035 // If a result value was tied to an input value, the computed result may
6036 // have a wider width than the expected result. Extract the relevant
6038 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6041 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6044 setValue(CS.getInstruction(), Val);
6045 // Don't need to use this as a chain in this case.
6046 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6050 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6052 // Process indirect outputs, first output all of the flagged copies out of
6054 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6055 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6056 const Value *Ptr = IndirectStoresToEmit[i].second;
6057 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6059 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6062 // Emit the non-flagged stores from the physregs.
6063 SmallVector<SDValue, 8> OutChains;
6064 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6065 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6066 StoresToEmit[i].first,
6067 getValue(StoresToEmit[i].second),
6068 MachinePointerInfo(StoresToEmit[i].second),
6070 OutChains.push_back(Val);
6073 if (!OutChains.empty())
6074 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6075 &OutChains[0], OutChains.size());
6080 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6081 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6082 MVT::Other, getRoot(),
6083 getValue(I.getArgOperand(0)),
6084 DAG.getSrcValue(I.getArgOperand(0))));
6087 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6088 const TargetData &TD = *TLI.getTargetData();
6089 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6090 getRoot(), getValue(I.getOperand(0)),
6091 DAG.getSrcValue(I.getOperand(0)),
6092 TD.getABITypeAlignment(I.getType()));
6094 DAG.setRoot(V.getValue(1));
6097 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6098 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6099 MVT::Other, getRoot(),
6100 getValue(I.getArgOperand(0)),
6101 DAG.getSrcValue(I.getArgOperand(0))));
6104 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6105 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6106 MVT::Other, getRoot(),
6107 getValue(I.getArgOperand(0)),
6108 getValue(I.getArgOperand(1)),
6109 DAG.getSrcValue(I.getArgOperand(0)),
6110 DAG.getSrcValue(I.getArgOperand(1))));
6113 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6114 /// implementation, which just calls LowerCall.
6115 /// FIXME: When all targets are
6116 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6117 std::pair<SDValue, SDValue>
6118 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6119 bool RetSExt, bool RetZExt, bool isVarArg,
6120 bool isInreg, unsigned NumFixedArgs,
6121 CallingConv::ID CallConv, bool isTailCall,
6122 bool isReturnValueUsed,
6124 ArgListTy &Args, SelectionDAG &DAG,
6125 DebugLoc dl) const {
6126 // Handle all of the outgoing arguments.
6127 SmallVector<ISD::OutputArg, 32> Outs;
6128 SmallVector<SDValue, 32> OutVals;
6129 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6130 SmallVector<EVT, 4> ValueVTs;
6131 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6132 for (unsigned Value = 0, NumValues = ValueVTs.size();
6133 Value != NumValues; ++Value) {
6134 EVT VT = ValueVTs[Value];
6135 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6136 SDValue Op = SDValue(Args[i].Node.getNode(),
6137 Args[i].Node.getResNo() + Value);
6138 ISD::ArgFlagsTy Flags;
6139 unsigned OriginalAlignment =
6140 getTargetData()->getABITypeAlignment(ArgTy);
6146 if (Args[i].isInReg)
6150 if (Args[i].isByVal) {
6152 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6153 Type *ElementTy = Ty->getElementType();
6154 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6155 // For ByVal, alignment should come from FE. BE will guess if this
6156 // info is not there but there are cases it cannot get right.
6157 unsigned FrameAlign;
6158 if (Args[i].Alignment)
6159 FrameAlign = Args[i].Alignment;
6161 FrameAlign = getByValTypeAlignment(ElementTy);
6162 Flags.setByValAlign(FrameAlign);
6166 Flags.setOrigAlign(OriginalAlignment);
6168 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6169 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6170 SmallVector<SDValue, 4> Parts(NumParts);
6171 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6174 ExtendKind = ISD::SIGN_EXTEND;
6175 else if (Args[i].isZExt)
6176 ExtendKind = ISD::ZERO_EXTEND;
6178 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6179 PartVT, ExtendKind);
6181 for (unsigned j = 0; j != NumParts; ++j) {
6182 // if it isn't first piece, alignment must be 1
6183 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6185 if (NumParts > 1 && j == 0)
6186 MyFlags.Flags.setSplit();
6188 MyFlags.Flags.setOrigAlign(1);
6190 Outs.push_back(MyFlags);
6191 OutVals.push_back(Parts[j]);
6196 // Handle the incoming return values from the call.
6197 SmallVector<ISD::InputArg, 32> Ins;
6198 SmallVector<EVT, 4> RetTys;
6199 ComputeValueVTs(*this, RetTy, RetTys);
6200 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6202 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6203 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6204 for (unsigned i = 0; i != NumRegs; ++i) {
6205 ISD::InputArg MyFlags;
6206 MyFlags.VT = RegisterVT.getSimpleVT();
6207 MyFlags.Used = isReturnValueUsed;
6209 MyFlags.Flags.setSExt();
6211 MyFlags.Flags.setZExt();
6213 MyFlags.Flags.setInReg();
6214 Ins.push_back(MyFlags);
6218 SmallVector<SDValue, 4> InVals;
6219 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6220 Outs, OutVals, Ins, dl, DAG, InVals);
6222 // Verify that the target's LowerCall behaved as expected.
6223 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6224 "LowerCall didn't return a valid chain!");
6225 assert((!isTailCall || InVals.empty()) &&
6226 "LowerCall emitted a return value for a tail call!");
6227 assert((isTailCall || InVals.size() == Ins.size()) &&
6228 "LowerCall didn't emit the correct number of values!");
6230 // For a tail call, the return value is merely live-out and there aren't
6231 // any nodes in the DAG representing it. Return a special value to
6232 // indicate that a tail call has been emitted and no more Instructions
6233 // should be processed in the current block.
6236 return std::make_pair(SDValue(), SDValue());
6239 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6240 assert(InVals[i].getNode() &&
6241 "LowerCall emitted a null value!");
6242 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6243 "LowerCall emitted a value with the wrong type!");
6246 // Collect the legal value parts into potentially illegal values
6247 // that correspond to the original function's return values.
6248 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6250 AssertOp = ISD::AssertSext;
6252 AssertOp = ISD::AssertZext;
6253 SmallVector<SDValue, 4> ReturnValues;
6254 unsigned CurReg = 0;
6255 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6257 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6258 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6260 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6261 NumRegs, RegisterVT, VT,
6266 // For a function returning void, there is no return value. We can't create
6267 // such a node, so we just return a null return value in that case. In
6268 // that case, nothing will actually look at the value.
6269 if (ReturnValues.empty())
6270 return std::make_pair(SDValue(), Chain);
6272 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6273 DAG.getVTList(&RetTys[0], RetTys.size()),
6274 &ReturnValues[0], ReturnValues.size());
6275 return std::make_pair(Res, Chain);
6278 void TargetLowering::LowerOperationWrapper(SDNode *N,
6279 SmallVectorImpl<SDValue> &Results,
6280 SelectionDAG &DAG) const {
6281 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6283 Results.push_back(Res);
6286 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6287 llvm_unreachable("LowerOperation not implemented for this target!");
6292 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6293 SDValue Op = getNonRegisterValue(V);
6294 assert((Op.getOpcode() != ISD::CopyFromReg ||
6295 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6296 "Copy from a reg to the same reg!");
6297 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6299 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6300 SDValue Chain = DAG.getEntryNode();
6301 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6302 PendingExports.push_back(Chain);
6305 #include "llvm/CodeGen/SelectionDAGISel.h"
6307 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6308 /// entry block, return true. This includes arguments used by switches, since
6309 /// the switch may expand into multiple basic blocks.
6310 static bool isOnlyUsedInEntryBlock(const Argument *A) {
6311 // With FastISel active, we may be splitting blocks, so force creation
6312 // of virtual registers for all non-dead arguments.
6314 return A->use_empty();
6316 const BasicBlock *Entry = A->getParent()->begin();
6317 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6319 const User *U = *UI;
6320 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6321 return false; // Use not in entry block.
6326 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6327 // If this is the entry block, emit arguments.
6328 const Function &F = *LLVMBB->getParent();
6329 SelectionDAG &DAG = SDB->DAG;
6330 DebugLoc dl = SDB->getCurDebugLoc();
6331 const TargetData *TD = TLI.getTargetData();
6332 SmallVector<ISD::InputArg, 16> Ins;
6334 // Check whether the function can return without sret-demotion.
6335 SmallVector<ISD::OutputArg, 4> Outs;
6336 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6339 if (!FuncInfo->CanLowerReturn) {
6340 // Put in an sret pointer parameter before all the other parameters.
6341 SmallVector<EVT, 1> ValueVTs;
6342 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6344 // NOTE: Assuming that a pointer will never break down to more than one VT
6346 ISD::ArgFlagsTy Flags;
6348 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6349 ISD::InputArg RetArg(Flags, RegisterVT, true);
6350 Ins.push_back(RetArg);
6353 // Set up the incoming argument description vector.
6355 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6356 I != E; ++I, ++Idx) {
6357 SmallVector<EVT, 4> ValueVTs;
6358 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6359 bool isArgValueUsed = !I->use_empty();
6360 for (unsigned Value = 0, NumValues = ValueVTs.size();
6361 Value != NumValues; ++Value) {
6362 EVT VT = ValueVTs[Value];
6363 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6364 ISD::ArgFlagsTy Flags;
6365 unsigned OriginalAlignment =
6366 TD->getABITypeAlignment(ArgTy);
6368 if (F.paramHasAttr(Idx, Attribute::ZExt))
6370 if (F.paramHasAttr(Idx, Attribute::SExt))
6372 if (F.paramHasAttr(Idx, Attribute::InReg))
6374 if (F.paramHasAttr(Idx, Attribute::StructRet))
6376 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6378 PointerType *Ty = cast<PointerType>(I->getType());
6379 Type *ElementTy = Ty->getElementType();
6380 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6381 // For ByVal, alignment should be passed from FE. BE will guess if
6382 // this info is not there but there are cases it cannot get right.
6383 unsigned FrameAlign;
6384 if (F.getParamAlignment(Idx))
6385 FrameAlign = F.getParamAlignment(Idx);
6387 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6388 Flags.setByValAlign(FrameAlign);
6390 if (F.paramHasAttr(Idx, Attribute::Nest))
6392 Flags.setOrigAlign(OriginalAlignment);
6394 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6395 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6396 for (unsigned i = 0; i != NumRegs; ++i) {
6397 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6398 if (NumRegs > 1 && i == 0)
6399 MyFlags.Flags.setSplit();
6400 // if it isn't first piece, alignment must be 1
6402 MyFlags.Flags.setOrigAlign(1);
6403 Ins.push_back(MyFlags);
6408 // Call the target to set up the argument values.
6409 SmallVector<SDValue, 8> InVals;
6410 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6414 // Verify that the target's LowerFormalArguments behaved as expected.
6415 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6416 "LowerFormalArguments didn't return a valid chain!");
6417 assert(InVals.size() == Ins.size() &&
6418 "LowerFormalArguments didn't emit the correct number of values!");
6420 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6421 assert(InVals[i].getNode() &&
6422 "LowerFormalArguments emitted a null value!");
6423 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6424 "LowerFormalArguments emitted a value with the wrong type!");
6428 // Update the DAG with the new chain value resulting from argument lowering.
6429 DAG.setRoot(NewRoot);
6431 // Set up the argument values.
6434 if (!FuncInfo->CanLowerReturn) {
6435 // Create a virtual register for the sret pointer, and put in a copy
6436 // from the sret argument into it.
6437 SmallVector<EVT, 1> ValueVTs;
6438 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6439 EVT VT = ValueVTs[0];
6440 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6441 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6442 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6443 RegVT, VT, AssertOp);
6445 MachineFunction& MF = SDB->DAG.getMachineFunction();
6446 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6447 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6448 FuncInfo->DemoteRegister = SRetReg;
6449 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6451 DAG.setRoot(NewRoot);
6453 // i indexes lowered arguments. Bump it past the hidden sret argument.
6454 // Idx indexes LLVM arguments. Don't touch it.
6458 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6460 SmallVector<SDValue, 4> ArgValues;
6461 SmallVector<EVT, 4> ValueVTs;
6462 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6463 unsigned NumValues = ValueVTs.size();
6465 // If this argument is unused then remember its value. It is used to generate
6466 // debugging information.
6467 if (I->use_empty() && NumValues)
6468 SDB->setUnusedArgValue(I, InVals[i]);
6470 for (unsigned Val = 0; Val != NumValues; ++Val) {
6471 EVT VT = ValueVTs[Val];
6472 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6473 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6475 if (!I->use_empty()) {
6476 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6477 if (F.paramHasAttr(Idx, Attribute::SExt))
6478 AssertOp = ISD::AssertSext;
6479 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6480 AssertOp = ISD::AssertZext;
6482 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6483 NumParts, PartVT, VT,
6490 // We don't need to do anything else for unused arguments.
6491 if (ArgValues.empty())
6494 // Note down frame index for byval arguments.
6495 if (I->hasByValAttr())
6496 if (FrameIndexSDNode *FI =
6497 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6498 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6500 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6501 SDB->getCurDebugLoc());
6502 SDB->setValue(I, Res);
6504 // If this argument is live outside of the entry block, insert a copy from
6505 // wherever we got it to the vreg that other BB's will reference it as.
6506 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6507 // If we can, though, try to skip creating an unnecessary vreg.
6508 // FIXME: This isn't very clean... it would be nice to make this more
6509 // general. It's also subtly incompatible with the hacks FastISel
6511 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6512 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6513 FuncInfo->ValueMap[I] = Reg;
6517 if (!isOnlyUsedInEntryBlock(I)) {
6518 FuncInfo->InitializeRegForValue(I);
6519 SDB->CopyToExportRegsIfNeeded(I);
6523 assert(i == InVals.size() && "Argument register count mismatch!");
6525 // Finally, if the target has anything special to do, allow it to do so.
6526 // FIXME: this should insert code into the DAG!
6527 EmitFunctionEntryCode();
6530 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6531 /// ensure constants are generated when needed. Remember the virtual registers
6532 /// that need to be added to the Machine PHI nodes as input. We cannot just
6533 /// directly add them, because expansion might result in multiple MBB's for one
6534 /// BB. As such, the start of the BB might correspond to a different MBB than
6538 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6539 const TerminatorInst *TI = LLVMBB->getTerminator();
6541 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6543 // Check successor nodes' PHI nodes that expect a constant to be available
6545 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6546 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6547 if (!isa<PHINode>(SuccBB->begin())) continue;
6548 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6550 // If this terminator has multiple identical successors (common for
6551 // switches), only handle each succ once.
6552 if (!SuccsHandled.insert(SuccMBB)) continue;
6554 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6556 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6557 // nodes and Machine PHI nodes, but the incoming operands have not been
6559 for (BasicBlock::const_iterator I = SuccBB->begin();
6560 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6561 // Ignore dead phi's.
6562 if (PN->use_empty()) continue;
6565 if (PN->getType()->isEmptyTy())
6569 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6571 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6572 unsigned &RegOut = ConstantsOut[C];
6574 RegOut = FuncInfo.CreateRegs(C->getType());
6575 CopyValueToVirtualRegister(C, RegOut);
6579 DenseMap<const Value *, unsigned>::iterator I =
6580 FuncInfo.ValueMap.find(PHIOp);
6581 if (I != FuncInfo.ValueMap.end())
6584 assert(isa<AllocaInst>(PHIOp) &&
6585 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6586 "Didn't codegen value into a register!??");
6587 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6588 CopyValueToVirtualRegister(PHIOp, Reg);
6592 // Remember that this register needs to added to the machine PHI node as
6593 // the input for this MBB.
6594 SmallVector<EVT, 4> ValueVTs;
6595 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6596 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6597 EVT VT = ValueVTs[vti];
6598 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6599 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6600 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6601 Reg += NumRegisters;
6605 ConstantsOut.clear();