1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getIntPtrConstant(1));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert(PartVT.isInteger() && ValueVT.isInteger() &&
357 "Unknown mismatch!");
358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 } else if (PartBits == ValueVT.getSizeInBits()) {
362 // Different types of the same size.
363 assert(NumParts == 1 && PartVT != ValueVT);
364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
366 // If the parts cover less bits than value has, truncate the value.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Unknown mismatch!");
369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
373 // The value may have changed - recompute ValueVT.
374 ValueVT = Val.getValueType();
375 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
376 "Failed to tile the value with PartVT!");
379 assert(PartVT == ValueVT && "Type conversion failed!");
384 // Expand the value into multiple parts.
385 if (NumParts & (NumParts - 1)) {
386 // The number of parts is not a power of 2. Split off and copy the tail.
387 assert(PartVT.isInteger() && ValueVT.isInteger() &&
388 "Do not know what to expand to!");
389 unsigned RoundParts = 1 << Log2_32(NumParts);
390 unsigned RoundBits = RoundParts * PartBits;
391 unsigned OddParts = NumParts - RoundParts;
392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
393 DAG.getIntPtrConstant(RoundBits));
394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
396 if (TLI.isBigEndian())
397 // The odd parts were reversed by getCopyToParts - unreverse them.
398 std::reverse(Parts + RoundParts, Parts + NumParts);
400 NumParts = RoundParts;
401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 // The number of parts is a power of 2. Repeatedly bisect the value using
407 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
408 EVT::getIntegerVT(*DAG.getContext(),
409 ValueVT.getSizeInBits()),
412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
413 for (unsigned i = 0; i < NumParts; i += StepSize) {
414 unsigned ThisBits = StepSize * PartBits / 2;
415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
416 SDValue &Part0 = Parts[i];
417 SDValue &Part1 = Parts[i+StepSize/2];
419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
420 ThisVT, Part0, DAG.getIntPtrConstant(1));
421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
422 ThisVT, Part0, DAG.getIntPtrConstant(0));
424 if (ThisBits == PartBits && ThisVT != PartVT) {
425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
431 if (TLI.isBigEndian())
432 std::reverse(Parts, Parts + OrigNumParts);
436 /// getCopyToPartsVector - Create a series of nodes that contain the specified
437 /// value split into legal parts.
438 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
439 SDValue Val, SDValue *Parts, unsigned NumParts,
441 EVT ValueVT = Val.getValueType();
442 assert(ValueVT.isVector() && "Not a vector");
443 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
446 if (PartVT == ValueVT) {
448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
449 // Bitconvert vector->vector case.
450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
451 } else if (PartVT.isVector() &&
452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
454 EVT ElementVT = PartVT.getVectorElementType();
455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
457 SmallVector<SDValue, 16> Ops;
458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
460 ElementVT, Val, DAG.getIntPtrConstant(i)));
462 for (unsigned i = ValueVT.getVectorNumElements(),
463 e = PartVT.getVectorNumElements(); i != e; ++i)
464 Ops.push_back(DAG.getUNDEF(ElementVT));
466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
468 // FIXME: Use CONCAT for 2x -> 4x.
470 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
472 } else if (PartVT.isVector() &&
473 PartVT.getVectorElementType().bitsGE(
474 ValueVT.getVectorElementType()) &&
475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
477 // Promoted vector extract
478 bool Smaller = PartVT.bitsLE(ValueVT);
479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
482 // Vector -> scalar conversion.
483 assert(ValueVT.getVectorNumElements() == 1 &&
484 "Only trivial vector-to-scalar conversions should get here!");
485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 PartVT, Val, DAG.getIntPtrConstant(0));
488 bool Smaller = ValueVT.bitsLE(PartVT);
489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
497 // Handle a multi-element vector.
498 EVT IntermediateVT, RegisterVT;
499 unsigned NumIntermediates;
500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
502 NumIntermediates, RegisterVT);
503 unsigned NumElements = ValueVT.getVectorNumElements();
505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
506 NumParts = NumRegs; // Silence a compiler warning.
507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
509 // Split the vector into intermediate operands.
510 SmallVector<SDValue, 8> Ops(NumIntermediates);
511 for (unsigned i = 0; i != NumIntermediates; ++i) {
512 if (IntermediateVT.isVector())
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 IntermediateVT, Val, DAG.getIntPtrConstant(i));
521 // Split the intermediate operands into legal parts.
522 if (NumParts == NumIntermediates) {
523 // If the register was not expanded, promote or copy the value,
525 for (unsigned i = 0; i != NumParts; ++i)
526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
527 } else if (NumParts > 0) {
528 // If the intermediate type was expanded, split each the value into
530 assert(NumParts % NumIntermediates == 0 &&
531 "Must expand into a divisible number of parts!");
532 unsigned Factor = NumParts / NumIntermediates;
533 for (unsigned i = 0; i != NumIntermediates; ++i)
534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
542 /// RegsForValue - This struct represents the registers (physical or virtual)
543 /// that a particular set of values is assigned, and the type information
544 /// about the value. The most common situation is to represent one value at a
545 /// time, but struct or array values are handled element-wise as multiple
546 /// values. The splitting of aggregates is performed recursively, so that we
547 /// never have aggregate-typed registers. The values at this point do not
548 /// necessarily have legal types, so each value may require one or more
549 /// registers of some legal type.
551 struct RegsForValue {
552 /// ValueVTs - The value types of the values, which may not be legal, and
553 /// may need be promoted or synthesized from one or more registers.
555 SmallVector<EVT, 4> ValueVTs;
557 /// RegVTs - The value types of the registers. This is the same size as
558 /// ValueVTs and it records, for each value, what the type of the assigned
559 /// register or registers are. (Individual values are never synthesized
560 /// from more than one type of register.)
562 /// With virtual registers, the contents of RegVTs is redundant with TLI's
563 /// getRegisterType member function, however when with physical registers
564 /// it is necessary to have a separate record of the types.
566 SmallVector<EVT, 4> RegVTs;
568 /// Regs - This list holds the registers assigned to the values.
569 /// Each legal or promoted value requires one register, and each
570 /// expanded value requires multiple registers.
572 SmallVector<unsigned, 4> Regs;
576 RegsForValue(const SmallVector<unsigned, 4> ®s,
577 EVT regvt, EVT valuevt)
578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
580 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
581 unsigned Reg, Type *Ty) {
582 ComputeValueVTs(tli, Ty, ValueVTs);
584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
585 EVT ValueVT = ValueVTs[Value];
586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
588 for (unsigned i = 0; i != NumRegs; ++i)
589 Regs.push_back(Reg + i);
590 RegVTs.push_back(RegisterVT);
595 /// areValueTypesLegal - Return true if types of all the values are legal.
596 bool areValueTypesLegal(const TargetLowering &TLI) {
597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
598 EVT RegisterVT = RegVTs[Value];
599 if (!TLI.isTypeLegal(RegisterVT))
605 /// append - Add the specified values to this one.
606 void append(const RegsForValue &RHS) {
607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
609 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
613 /// this value and returns the result as a ValueVTs value. This uses
614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
615 /// If the Flag pointer is NULL, no flag is used.
616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
618 SDValue &Chain, SDValue *Flag) const;
620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
621 /// specified value into the registers specified by this object. This uses
622 /// Chain/Flag as the input and updates them for the output Chain/Flag.
623 /// If the Flag pointer is NULL, no flag is used.
624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
625 SDValue &Chain, SDValue *Flag) const;
627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
628 /// operand list. This adds the code marker, matching input operand index
629 /// (if applicable), and includes the number of values added into it.
630 void AddInlineAsmOperands(unsigned Kind,
631 bool HasMatching, unsigned MatchingIdx,
633 std::vector<SDValue> &Ops) const;
637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
638 /// this value and returns the result as a ValueVT value. This uses
639 /// Chain/Flag as the input and updates them for the output Chain/Flag.
640 /// If the Flag pointer is NULL, no flag is used.
641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
642 FunctionLoweringInfo &FuncInfo,
644 SDValue &Chain, SDValue *Flag) const {
645 // A Value with type {} or [0 x %t] needs no registers.
646 if (ValueVTs.empty())
649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
651 // Assemble the legal parts into the final values.
652 SmallVector<SDValue, 4> Values(ValueVTs.size());
653 SmallVector<SDValue, 8> Parts;
654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
655 // Copy the legal parts from the registers.
656 EVT ValueVT = ValueVTs[Value];
657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
658 EVT RegisterVT = RegVTs[Value];
660 Parts.resize(NumRegs);
661 for (unsigned i = 0; i != NumRegs; ++i) {
664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
667 *Flag = P.getValue(2);
670 Chain = P.getValue(1);
673 // If the source register was virtual and if we know something about it,
674 // add an assert node.
675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
676 !RegisterVT.isInteger() || RegisterVT.isVector())
679 const FunctionLoweringInfo::LiveOutInfo *LOI =
680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
684 unsigned RegSize = RegisterVT.getSizeInBits();
685 unsigned NumSignBits = LOI->NumSignBits;
686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
688 // FIXME: We capture more information than the dag can represent. For
689 // now, just use the tightest assertzext/assertsext possible.
691 EVT FromVT(MVT::Other);
692 if (NumSignBits == RegSize)
693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
694 else if (NumZeroBits >= RegSize-1)
695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
696 else if (NumSignBits > RegSize-8)
697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
698 else if (NumZeroBits >= RegSize-8)
699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
700 else if (NumSignBits > RegSize-16)
701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
702 else if (NumZeroBits >= RegSize-16)
703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
704 else if (NumSignBits > RegSize-32)
705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
706 else if (NumZeroBits >= RegSize-32)
707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
711 // Add an assertion node.
712 assert(FromVT != MVT::Other);
713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
714 RegisterVT, P, DAG.getValueType(FromVT));
717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
718 NumRegs, RegisterVT, ValueVT);
723 return DAG.getNode(ISD::MERGE_VALUES, dl,
724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
725 &Values[0], ValueVTs.size());
728 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
729 /// specified value into the registers specified by this object. This uses
730 /// Chain/Flag as the input and updates them for the output Chain/Flag.
731 /// If the Flag pointer is NULL, no flag is used.
732 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
733 SDValue &Chain, SDValue *Flag) const {
734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
736 // Get the list of the values's legal parts.
737 unsigned NumRegs = Regs.size();
738 SmallVector<SDValue, 8> Parts(NumRegs);
739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
740 EVT ValueVT = ValueVTs[Value];
741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
742 EVT RegisterVT = RegVTs[Value];
744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
745 &Parts[Part], NumParts, RegisterVT);
749 // Copy the parts into the registers.
750 SmallVector<SDValue, 8> Chains(NumRegs);
751 for (unsigned i = 0; i != NumRegs; ++i) {
754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
757 *Flag = Part.getValue(1);
760 Chains[i] = Part.getValue(0);
763 if (NumRegs == 1 || Flag)
764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
765 // flagged to it. That is the CopyToReg nodes and the user are considered
766 // a single scheduling unit. If we create a TokenFactor and return it as
767 // chain, then the TokenFactor is both a predecessor (operand) of the
768 // user as well as a successor (the TF operands are flagged to the user).
769 // c1, f1 = CopyToReg
770 // c2, f2 = CopyToReg
771 // c3 = TokenFactor c1, c2
774 Chain = Chains[NumRegs-1];
776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
779 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
780 /// operand list. This adds the code marker and includes the number of
781 /// values added into it.
782 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
783 unsigned MatchingIdx,
785 std::vector<SDValue> &Ops) const {
786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
796 EVT RegisterVT = RegVTs[Value];
797 for (unsigned i = 0; i != NumRegs; ++i) {
798 assert(Reg < Regs.size() && "Mismatch in # registers expected");
799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
804 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
807 TD = DAG.getTarget().getTargetData();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
821 CurDebugLoc = DebugLoc();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is seperated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
853 &PendingLoads[0], PendingLoads.size());
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
884 PendingExports.size());
885 PendingExports.clear();
890 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
892 DAG.AssignOrdering(Node, SDNodeOrder);
894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
895 AssignOrderingToNode(Node->getOperand(I).getNode());
898 void SelectionDAGBuilder::visit(const Instruction &I) {
899 // Set up outgoing PHI node register values before emitting the terminator.
900 if (isa<TerminatorInst>(&I))
901 HandlePHINodesInSuccessorBlocks(I.getParent());
903 CurDebugLoc = I.getDebugLoc();
905 visit(I.getOpcode(), I);
907 if (!isa<TerminatorInst>(&I) && !HasTailCall)
908 CopyToExportRegsIfNeeded(&I);
910 CurDebugLoc = DebugLoc();
913 void SelectionDAGBuilder::visitPHI(const PHINode &) {
914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
917 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
918 // Note: this doesn't use InstVisitor, because it has to work with
919 // ConstantExpr's in addition to instructions.
921 default: llvm_unreachable("Unknown instruction type encountered!");
922 // Build the switch statement using the Instruction.def file.
923 #define HANDLE_INST(NUM, OPCODE, CLASS) \
924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
925 #include "llvm/Instruction.def"
928 // Assign the ordering to the freshly created DAG nodes.
929 if (NodeMap.count(&I)) {
931 AssignOrderingToNode(getValue(&I).getNode());
935 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
936 // generate the debug data structures now that we've seen its definition.
937 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
941 const DbgValueInst *DI = DDI.getDI();
942 DebugLoc dl = DDI.getdl();
943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
944 MDNode *Variable = DI->getVariable();
945 uint64_t Offset = DI->getOffset();
948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
949 SDV = DAG.getDbgValue(Variable, Val.getNode(),
950 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
951 DAG.AddDbgValue(SDV, Val.getNode(), false);
954 DEBUG(dbgs() << "Dropping debug info for " << DI);
955 DanglingDebugInfoMap[V] = DanglingDebugInfo();
959 // getValue - Return an SDValue for the given Value.
960 SDValue SelectionDAGBuilder::getValue(const Value *V) {
961 // If we already have an SDValue for this value, use it. It's important
962 // to do this first, so that we don't create a CopyFromReg if we already
963 // have a regular SDValue.
964 SDValue &N = NodeMap[V];
965 if (N.getNode()) return N;
967 // If there's a virtual register allocated and initialized for this
969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
970 if (It != FuncInfo.ValueMap.end()) {
971 unsigned InReg = It->second;
972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
973 SDValue Chain = DAG.getEntryNode();
974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
975 resolveDanglingDebugInfo(V, N);
979 // Otherwise create a new SDValue and remember it.
980 SDValue Val = getValueImpl(V);
982 resolveDanglingDebugInfo(V, Val);
986 /// getNonRegisterValue - Return an SDValue for the given Value, but
987 /// don't look in FuncInfo.ValueMap for a virtual register.
988 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
989 // If we already have an SDValue for this value, use it.
990 SDValue &N = NodeMap[V];
991 if (N.getNode()) return N;
993 // Otherwise create a new SDValue and remember it.
994 SDValue Val = getValueImpl(V);
996 resolveDanglingDebugInfo(V, Val);
1000 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1001 /// Create an SDValue for the given value.
1002 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1003 if (const Constant *C = dyn_cast<Constant>(V)) {
1004 EVT VT = TLI.getValueType(V->getType(), true);
1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1007 return DAG.getConstant(*CI, VT);
1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1012 if (isa<ConstantPointerNull>(C))
1013 return DAG.getConstant(0, TLI.getPointerTy());
1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1016 return DAG.getConstantFP(*CFP, VT);
1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1019 return DAG.getUNDEF(VT);
1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1022 visit(CE->getOpcode(), *CE);
1023 SDValue N1 = NodeMap[V];
1024 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1029 SmallVector<SDValue, 4> Constants;
1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1032 SDNode *Val = getValue(*OI).getNode();
1033 // If the operand is an empty aggregate, there are no values.
1035 // Add each leaf value from the operand to the Constants list
1036 // to form a flattened list of all the values.
1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1038 Constants.push_back(SDValue(Val, i));
1041 return DAG.getMergeValues(&Constants[0], Constants.size(),
1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1047 "Unknown struct or array constant!");
1049 SmallVector<EVT, 4> ValueVTs;
1050 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1051 unsigned NumElts = ValueVTs.size();
1053 return SDValue(); // empty struct
1054 SmallVector<SDValue, 4> Constants(NumElts);
1055 for (unsigned i = 0; i != NumElts; ++i) {
1056 EVT EltVT = ValueVTs[i];
1057 if (isa<UndefValue>(C))
1058 Constants[i] = DAG.getUNDEF(EltVT);
1059 else if (EltVT.isFloatingPoint())
1060 Constants[i] = DAG.getConstantFP(0, EltVT);
1062 Constants[i] = DAG.getConstant(0, EltVT);
1065 return DAG.getMergeValues(&Constants[0], NumElts,
1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1070 return DAG.getBlockAddress(BA, VT);
1072 VectorType *VecTy = cast<VectorType>(V->getType());
1073 unsigned NumElements = VecTy->getNumElements();
1075 // Now that we know the number and type of the elements, get that number of
1076 // elements into the Ops array based on what kind of constant it is.
1077 SmallVector<SDValue, 16> Ops;
1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1079 for (unsigned i = 0; i != NumElements; ++i)
1080 Ops.push_back(getValue(CP->getOperand(i)));
1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1083 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1086 if (EltVT.isFloatingPoint())
1087 Op = DAG.getConstantFP(0, EltVT);
1089 Op = DAG.getConstant(0, EltVT);
1090 Ops.assign(NumElements, Op);
1093 // Create a BUILD_VECTOR node.
1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1095 VT, &Ops[0], Ops.size());
1098 // If this is a static alloca, generate it as the frameindex instead of
1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1101 DenseMap<const AllocaInst*, int>::iterator SI =
1102 FuncInfo.StaticAllocaMap.find(AI);
1103 if (SI != FuncInfo.StaticAllocaMap.end())
1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1107 // If this is an instruction which fast-isel has deferred, select it now.
1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1111 SDValue Chain = DAG.getEntryNode();
1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1115 llvm_unreachable("Can't get register for value!");
1119 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1120 SDValue Chain = getControlRoot();
1121 SmallVector<ISD::OutputArg, 8> Outs;
1122 SmallVector<SDValue, 8> OutVals;
1124 if (!FuncInfo.CanLowerReturn) {
1125 unsigned DemoteReg = FuncInfo.DemoteRegister;
1126 const Function *F = I.getParent()->getParent();
1128 // Emit a store of the return value through the virtual register.
1129 // Leave Outs empty so that LowerReturn won't try to load return
1130 // registers the usual way.
1131 SmallVector<EVT, 1> PtrValueVTs;
1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1136 SDValue RetOp = getValue(I.getOperand(0));
1138 SmallVector<EVT, 4> ValueVTs;
1139 SmallVector<uint64_t, 4> Offsets;
1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1141 unsigned NumValues = ValueVTs.size();
1143 SmallVector<SDValue, 4> Chains(NumValues);
1144 for (unsigned i = 0; i != NumValues; ++i) {
1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1146 RetPtr.getValueType(), RetPtr,
1147 DAG.getIntPtrConstant(Offsets[i]));
1149 DAG.getStore(Chain, getCurDebugLoc(),
1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1151 // FIXME: better loc info would be nice.
1152 Add, MachinePointerInfo(), false, false, 0);
1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1156 MVT::Other, &Chains[0], NumValues);
1157 } else if (I.getNumOperands() != 0) {
1158 SmallVector<EVT, 4> ValueVTs;
1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1160 unsigned NumValues = ValueVTs.size();
1162 SDValue RetOp = getValue(I.getOperand(0));
1163 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1164 EVT VT = ValueVTs[j];
1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1168 const Function *F = I.getParent()->getParent();
1169 if (F->paramHasAttr(0, Attribute::SExt))
1170 ExtendKind = ISD::SIGN_EXTEND;
1171 else if (F->paramHasAttr(0, Attribute::ZExt))
1172 ExtendKind = ISD::ZERO_EXTEND;
1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1179 SmallVector<SDValue, 4> Parts(NumParts);
1180 getCopyToParts(DAG, getCurDebugLoc(),
1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1182 &Parts[0], NumParts, PartVT, ExtendKind);
1184 // 'inreg' on function refers to return value
1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1186 if (F->paramHasAttr(0, Attribute::InReg))
1189 // Propagate extension type if any
1190 if (ExtendKind == ISD::SIGN_EXTEND)
1192 else if (ExtendKind == ISD::ZERO_EXTEND)
1195 for (unsigned i = 0; i < NumParts; ++i) {
1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1198 OutVals.push_back(Parts[i]);
1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1205 CallingConv::ID CallConv =
1206 DAG.getMachineFunction().getFunction()->getCallingConv();
1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1208 Outs, OutVals, getCurDebugLoc(), DAG);
1210 // Verify that the target's LowerReturn behaved as expected.
1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1212 "LowerReturn didn't return a valid chain!");
1214 // Update the DAG with the new chain value resulting from return lowering.
1218 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1219 /// created for it, emit nodes to copy the value into the virtual
1221 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1223 if (V->getType()->isEmptyTy())
1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1227 if (VMI != FuncInfo.ValueMap.end()) {
1228 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1229 CopyValueToVirtualRegister(V, VMI->second);
1233 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1234 /// the current basic block, add it to ValueMap now so that we'll get a
1236 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1237 // No need to export constants.
1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1240 // Already exported?
1241 if (FuncInfo.isExportedInst(V)) return;
1243 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1244 CopyValueToVirtualRegister(V, Reg);
1247 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1248 const BasicBlock *FromBB) {
1249 // The operands of the setcc have to be in this block. We don't know
1250 // how to export them from some other block.
1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1252 // Can export from current BB.
1253 if (VI->getParent() == FromBB)
1256 // Is already exported, noop.
1257 return FuncInfo.isExportedInst(V);
1260 // If this is an argument, we can export it if the BB is the entry block or
1261 // if it is already exported.
1262 if (isa<Argument>(V)) {
1263 if (FromBB == &FromBB->getParent()->getEntryBlock())
1266 // Otherwise, can only export this if it is already exported.
1267 return FuncInfo.isExportedInst(V);
1270 // Otherwise, constants can always be exported.
1274 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1275 uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src,
1276 MachineBasicBlock *Dst) {
1277 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1280 const BasicBlock *SrcBB = Src->getBasicBlock();
1281 const BasicBlock *DstBB = Dst->getBasicBlock();
1282 return BPI->getEdgeWeight(SrcBB, DstBB);
1285 void SelectionDAGBuilder::
1286 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1287 uint32_t Weight /* = 0 */) {
1289 Weight = getEdgeWeight(Src, Dst);
1290 Src->addSuccessor(Dst, Weight);
1294 static bool InBlock(const Value *V, const BasicBlock *BB) {
1295 if (const Instruction *I = dyn_cast<Instruction>(V))
1296 return I->getParent() == BB;
1300 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1301 /// This function emits a branch and is used at the leaves of an OR or an
1302 /// AND operator tree.
1305 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1306 MachineBasicBlock *TBB,
1307 MachineBasicBlock *FBB,
1308 MachineBasicBlock *CurBB,
1309 MachineBasicBlock *SwitchBB) {
1310 const BasicBlock *BB = CurBB->getBasicBlock();
1312 // If the leaf of the tree is a comparison, merge the condition into
1314 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1315 // The operands of the cmp have to be in this block. We don't know
1316 // how to export them from some other block. If this is the first block
1317 // of the sequence, no exporting is needed.
1318 if (CurBB == SwitchBB ||
1319 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1320 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1321 ISD::CondCode Condition;
1322 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1323 Condition = getICmpCondCode(IC->getPredicate());
1324 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1325 Condition = getFCmpCondCode(FC->getPredicate());
1327 Condition = ISD::SETEQ; // silence warning.
1328 llvm_unreachable("Unknown compare instruction");
1331 CaseBlock CB(Condition, BOp->getOperand(0),
1332 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1333 SwitchCases.push_back(CB);
1338 // Create a CaseBlock record representing this branch.
1339 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1340 NULL, TBB, FBB, CurBB);
1341 SwitchCases.push_back(CB);
1344 /// FindMergedConditions - If Cond is an expression like
1345 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1346 MachineBasicBlock *TBB,
1347 MachineBasicBlock *FBB,
1348 MachineBasicBlock *CurBB,
1349 MachineBasicBlock *SwitchBB,
1351 // If this node is not part of the or/and tree, emit it as a branch.
1352 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1353 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1354 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1355 BOp->getParent() != CurBB->getBasicBlock() ||
1356 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1357 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1358 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1362 // Create TmpBB after CurBB.
1363 MachineFunction::iterator BBI = CurBB;
1364 MachineFunction &MF = DAG.getMachineFunction();
1365 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1366 CurBB->getParent()->insert(++BBI, TmpBB);
1368 if (Opc == Instruction::Or) {
1369 // Codegen X | Y as:
1377 // Emit the LHS condition.
1378 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1380 // Emit the RHS condition into TmpBB.
1381 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1383 assert(Opc == Instruction::And && "Unknown merge op!");
1384 // Codegen X & Y as:
1391 // This requires creation of TmpBB after CurBB.
1393 // Emit the LHS condition.
1394 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1396 // Emit the RHS condition into TmpBB.
1397 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1401 /// If the set of cases should be emitted as a series of branches, return true.
1402 /// If we should emit this as a bunch of and/or'd together conditions, return
1405 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1406 if (Cases.size() != 2) return true;
1408 // If this is two comparisons of the same values or'd or and'd together, they
1409 // will get folded into a single comparison, so don't emit two blocks.
1410 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1411 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1412 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1413 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1417 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1418 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1419 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1420 Cases[0].CC == Cases[1].CC &&
1421 isa<Constant>(Cases[0].CmpRHS) &&
1422 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1423 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1425 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1432 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1433 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1435 // Update machine-CFG edges.
1436 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1438 // Figure out which block is immediately after the current one.
1439 MachineBasicBlock *NextBlock = 0;
1440 MachineFunction::iterator BBI = BrMBB;
1441 if (++BBI != FuncInfo.MF->end())
1444 if (I.isUnconditional()) {
1445 // Update machine-CFG edges.
1446 BrMBB->addSuccessor(Succ0MBB);
1448 // If this is not a fall-through branch, emit the branch.
1449 if (Succ0MBB != NextBlock)
1450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1451 MVT::Other, getControlRoot(),
1452 DAG.getBasicBlock(Succ0MBB)));
1457 // If this condition is one of the special cases we handle, do special stuff
1459 const Value *CondVal = I.getCondition();
1460 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1462 // If this is a series of conditions that are or'd or and'd together, emit
1463 // this as a sequence of branches instead of setcc's with and/or operations.
1464 // As long as jumps are not expensive, this should improve performance.
1465 // For example, instead of something like:
1478 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1479 if (!TLI.isJumpExpensive() &&
1481 (BOp->getOpcode() == Instruction::And ||
1482 BOp->getOpcode() == Instruction::Or)) {
1483 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1485 // If the compares in later blocks need to use values not currently
1486 // exported from this block, export them now. This block should always
1487 // be the first entry.
1488 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1490 // Allow some cases to be rejected.
1491 if (ShouldEmitAsBranches(SwitchCases)) {
1492 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1493 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1494 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1497 // Emit the branch for this block.
1498 visitSwitchCase(SwitchCases[0], BrMBB);
1499 SwitchCases.erase(SwitchCases.begin());
1503 // Okay, we decided not to do this, remove any inserted MBB's and clear
1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1506 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1508 SwitchCases.clear();
1512 // Create a CaseBlock record representing this branch.
1513 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1514 NULL, Succ0MBB, Succ1MBB, BrMBB);
1516 // Use visitSwitchCase to actually insert the fast branch sequence for this
1518 visitSwitchCase(CB, BrMBB);
1521 /// visitSwitchCase - Emits the necessary code to represent a single node in
1522 /// the binary search tree resulting from lowering a switch instruction.
1523 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1524 MachineBasicBlock *SwitchBB) {
1526 SDValue CondLHS = getValue(CB.CmpLHS);
1527 DebugLoc dl = getCurDebugLoc();
1529 // Build the setcc now.
1530 if (CB.CmpMHS == NULL) {
1531 // Fold "(X == true)" to X and "(X == false)" to !X to
1532 // handle common cases produced by branch lowering.
1533 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1534 CB.CC == ISD::SETEQ)
1536 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1537 CB.CC == ISD::SETEQ) {
1538 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1539 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1541 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1543 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1545 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1546 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1548 SDValue CmpOp = getValue(CB.CmpMHS);
1549 EVT VT = CmpOp.getValueType();
1551 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1552 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1555 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1556 VT, CmpOp, DAG.getConstant(Low, VT));
1557 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1558 DAG.getConstant(High-Low, VT), ISD::SETULE);
1562 // Update successor info
1563 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1564 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1566 // Set NextBlock to be the MBB immediately after the current one, if any.
1567 // This is used to avoid emitting unnecessary branches to the next block.
1568 MachineBasicBlock *NextBlock = 0;
1569 MachineFunction::iterator BBI = SwitchBB;
1570 if (++BBI != FuncInfo.MF->end())
1573 // If the lhs block is the next block, invert the condition so that we can
1574 // fall through to the lhs instead of the rhs block.
1575 if (CB.TrueBB == NextBlock) {
1576 std::swap(CB.TrueBB, CB.FalseBB);
1577 SDValue True = DAG.getConstant(1, Cond.getValueType());
1578 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1582 MVT::Other, getControlRoot(), Cond,
1583 DAG.getBasicBlock(CB.TrueBB));
1585 // Insert the false branch. Do this even if it's a fall through branch,
1586 // this makes it easier to do DAG optimizations which require inverting
1587 // the branch condition.
1588 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1589 DAG.getBasicBlock(CB.FalseBB));
1591 DAG.setRoot(BrCond);
1594 /// visitJumpTable - Emit JumpTable node in the current MBB
1595 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1596 // Emit the code for the jump table
1597 assert(JT.Reg != -1U && "Should lower JT Header first!");
1598 EVT PTy = TLI.getPointerTy();
1599 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1601 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1602 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1603 MVT::Other, Index.getValue(1),
1605 DAG.setRoot(BrJumpTable);
1608 /// visitJumpTableHeader - This function emits necessary code to produce index
1609 /// in the JumpTable from switch case.
1610 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1611 JumpTableHeader &JTH,
1612 MachineBasicBlock *SwitchBB) {
1613 // Subtract the lowest switch case value from the value being switched on and
1614 // conditional branch to default mbb if the result is greater than the
1615 // difference between smallest and largest cases.
1616 SDValue SwitchOp = getValue(JTH.SValue);
1617 EVT VT = SwitchOp.getValueType();
1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1619 DAG.getConstant(JTH.First, VT));
1621 // The SDNode we just created, which holds the value being switched on minus
1622 // the smallest case value, needs to be copied to a virtual register so it
1623 // can be used as an index into the jump table in a subsequent basic block.
1624 // This value may be smaller or larger than the target's pointer type, and
1625 // therefore require extension or truncating.
1626 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1628 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1629 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1630 JumpTableReg, SwitchOp);
1631 JT.Reg = JumpTableReg;
1633 // Emit the range check for the jump table, and branch to the default block
1634 // for the switch statement if the value being switched on exceeds the largest
1635 // case in the switch.
1636 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1637 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1638 DAG.getConstant(JTH.Last-JTH.First,VT),
1641 // Set NextBlock to be the MBB immediately after the current one, if any.
1642 // This is used to avoid emitting unnecessary branches to the next block.
1643 MachineBasicBlock *NextBlock = 0;
1644 MachineFunction::iterator BBI = SwitchBB;
1646 if (++BBI != FuncInfo.MF->end())
1649 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1650 MVT::Other, CopyTo, CMP,
1651 DAG.getBasicBlock(JT.Default));
1653 if (JT.MBB != NextBlock)
1654 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1655 DAG.getBasicBlock(JT.MBB));
1657 DAG.setRoot(BrCond);
1660 /// visitBitTestHeader - This function emits necessary code to produce value
1661 /// suitable for "bit tests"
1662 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1663 MachineBasicBlock *SwitchBB) {
1664 // Subtract the minimum value
1665 SDValue SwitchOp = getValue(B.SValue);
1666 EVT VT = SwitchOp.getValueType();
1667 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1668 DAG.getConstant(B.First, VT));
1671 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1672 TLI.getSetCCResultType(Sub.getValueType()),
1673 Sub, DAG.getConstant(B.Range, VT),
1676 // Determine the type of the test operands.
1677 bool UsePtrType = false;
1678 if (!TLI.isTypeLegal(VT))
1681 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1682 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1683 // Switch table case range are encoded into series of masks.
1684 // Just use pointer type, it's guaranteed to fit.
1690 VT = TLI.getPointerTy();
1691 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1695 B.Reg = FuncInfo.CreateReg(VT);
1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1699 // Set NextBlock to be the MBB immediately after the current one, if any.
1700 // This is used to avoid emitting unnecessary branches to the next block.
1701 MachineBasicBlock *NextBlock = 0;
1702 MachineFunction::iterator BBI = SwitchBB;
1703 if (++BBI != FuncInfo.MF->end())
1706 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1708 addSuccessorWithWeight(SwitchBB, B.Default);
1709 addSuccessorWithWeight(SwitchBB, MBB);
1711 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1712 MVT::Other, CopyTo, RangeCmp,
1713 DAG.getBasicBlock(B.Default));
1715 if (MBB != NextBlock)
1716 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1717 DAG.getBasicBlock(MBB));
1719 DAG.setRoot(BrRange);
1722 /// visitBitTestCase - this function produces one "bit test"
1723 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1724 MachineBasicBlock* NextMBB,
1727 MachineBasicBlock *SwitchBB) {
1729 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1732 unsigned PopCount = CountPopulation_64(B.Mask);
1733 if (PopCount == 1) {
1734 // Testing for a single bit; just compare the shift count with what it
1735 // would need to be to shift a 1 bit in that position.
1736 Cmp = DAG.getSetCC(getCurDebugLoc(),
1737 TLI.getSetCCResultType(VT),
1739 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1741 } else if (PopCount == BB.Range) {
1742 // There is only one zero bit in the range, test for it directly.
1743 Cmp = DAG.getSetCC(getCurDebugLoc(),
1744 TLI.getSetCCResultType(VT),
1746 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1749 // Make desired shift
1750 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1751 DAG.getConstant(1, VT), ShiftOp);
1753 // Emit bit tests and jumps
1754 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1755 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1756 Cmp = DAG.getSetCC(getCurDebugLoc(),
1757 TLI.getSetCCResultType(VT),
1758 AndOp, DAG.getConstant(0, VT),
1762 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1763 addSuccessorWithWeight(SwitchBB, NextMBB);
1765 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1766 MVT::Other, getControlRoot(),
1767 Cmp, DAG.getBasicBlock(B.TargetBB));
1769 // Set NextBlock to be the MBB immediately after the current one, if any.
1770 // This is used to avoid emitting unnecessary branches to the next block.
1771 MachineBasicBlock *NextBlock = 0;
1772 MachineFunction::iterator BBI = SwitchBB;
1773 if (++BBI != FuncInfo.MF->end())
1776 if (NextMBB != NextBlock)
1777 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1778 DAG.getBasicBlock(NextMBB));
1783 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1784 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1786 // Retrieve successors.
1787 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1788 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1790 const Value *Callee(I.getCalledValue());
1791 if (isa<InlineAsm>(Callee))
1794 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1796 // If the value of the invoke is used outside of its defining block, make it
1797 // available as a virtual register.
1798 CopyToExportRegsIfNeeded(&I);
1800 // Update successor info
1801 InvokeMBB->addSuccessor(Return);
1802 InvokeMBB->addSuccessor(LandingPad);
1804 // Drop into normal successor.
1805 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1806 MVT::Other, getControlRoot(),
1807 DAG.getBasicBlock(Return)));
1810 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1813 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1814 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1817 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1818 assert(FuncInfo.MBB->isLandingPad() &&
1819 "Call to landingpad not in landing pad!");
1821 MachineBasicBlock *MBB = FuncInfo.MBB;
1822 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1823 AddLandingPadInfo(LP, MMI, MBB);
1825 SmallVector<EVT, 2> ValueVTs;
1826 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1828 // Insert the EXCEPTIONADDR instruction.
1829 assert(FuncInfo.MBB->isLandingPad() &&
1830 "Call to eh.exception not in landing pad!");
1831 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1833 Ops[0] = DAG.getRoot();
1834 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1835 SDValue Chain = Op1.getValue(1);
1837 // Insert the EHSELECTION instruction.
1838 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1841 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1842 Chain = Op2.getValue(1);
1843 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1847 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1848 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1851 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1852 setValue(&LP, RetPair.first);
1853 DAG.setRoot(RetPair.second);
1856 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1857 /// small case ranges).
1858 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1859 CaseRecVector& WorkList,
1861 MachineBasicBlock *Default,
1862 MachineBasicBlock *SwitchBB) {
1863 Case& BackCase = *(CR.Range.second-1);
1865 // Size is the number of Cases represented by this range.
1866 size_t Size = CR.Range.second - CR.Range.first;
1870 // Get the MachineFunction which holds the current MBB. This is used when
1871 // inserting any additional MBBs necessary to represent the switch.
1872 MachineFunction *CurMF = FuncInfo.MF;
1874 // Figure out which block is immediately after the current one.
1875 MachineBasicBlock *NextBlock = 0;
1876 MachineFunction::iterator BBI = CR.CaseBB;
1878 if (++BBI != FuncInfo.MF->end())
1881 // If any two of the cases has the same destination, and if one value
1882 // is the same as the other, but has one bit unset that the other has set,
1883 // use bit manipulation to do two compares at once. For example:
1884 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1885 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1886 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1887 if (Size == 2 && CR.CaseBB == SwitchBB) {
1888 Case &Small = *CR.Range.first;
1889 Case &Big = *(CR.Range.second-1);
1891 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1892 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1893 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1895 // Check that there is only one bit different.
1896 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1897 (SmallValue | BigValue) == BigValue) {
1898 // Isolate the common bit.
1899 APInt CommonBit = BigValue & ~SmallValue;
1900 assert((SmallValue | CommonBit) == BigValue &&
1901 CommonBit.countPopulation() == 1 && "Not a common bit?");
1903 SDValue CondLHS = getValue(SV);
1904 EVT VT = CondLHS.getValueType();
1905 DebugLoc DL = getCurDebugLoc();
1907 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1908 DAG.getConstant(CommonBit, VT));
1909 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1910 Or, DAG.getConstant(BigValue, VT),
1913 // Update successor info.
1914 addSuccessorWithWeight(SwitchBB, Small.BB);
1915 addSuccessorWithWeight(SwitchBB, Default);
1917 // Insert the true branch.
1918 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1919 getControlRoot(), Cond,
1920 DAG.getBasicBlock(Small.BB));
1922 // Insert the false branch.
1923 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1924 DAG.getBasicBlock(Default));
1926 DAG.setRoot(BrCond);
1932 // Rearrange the case blocks so that the last one falls through if possible.
1933 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1934 // The last case block won't fall through into 'NextBlock' if we emit the
1935 // branches in this order. See if rearranging a case value would help.
1936 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1937 if (I->BB == NextBlock) {
1938 std::swap(*I, BackCase);
1944 // Create a CaseBlock record representing a conditional branch to
1945 // the Case's target mbb if the value being switched on SV is equal
1947 MachineBasicBlock *CurBlock = CR.CaseBB;
1948 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1949 MachineBasicBlock *FallThrough;
1951 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1952 CurMF->insert(BBI, FallThrough);
1954 // Put SV in a virtual register to make it available from the new blocks.
1955 ExportFromCurrentBlock(SV);
1957 // If the last case doesn't match, go to the default block.
1958 FallThrough = Default;
1961 const Value *RHS, *LHS, *MHS;
1963 if (I->High == I->Low) {
1964 // This is just small small case range :) containing exactly 1 case
1966 LHS = SV; RHS = I->High; MHS = NULL;
1969 LHS = I->Low; MHS = SV; RHS = I->High;
1972 uint32_t ExtraWeight = I->ExtraWeight;
1973 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
1975 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
1977 // If emitting the first comparison, just call visitSwitchCase to emit the
1978 // code into the current block. Otherwise, push the CaseBlock onto the
1979 // vector to be later processed by SDISel, and insert the node's MBB
1980 // before the next MBB.
1981 if (CurBlock == SwitchBB)
1982 visitSwitchCase(CB, SwitchBB);
1984 SwitchCases.push_back(CB);
1986 CurBlock = FallThrough;
1992 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1993 return !DisableJumpTables &&
1994 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1995 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1998 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1999 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2000 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2001 return (LastExt - FirstExt + 1ULL);
2004 /// handleJTSwitchCase - Emit jumptable for current switch case range
2005 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
2006 CaseRecVector& WorkList,
2008 MachineBasicBlock* Default,
2009 MachineBasicBlock *SwitchBB) {
2010 Case& FrontCase = *CR.Range.first;
2011 Case& BackCase = *(CR.Range.second-1);
2013 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2014 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2016 APInt TSize(First.getBitWidth(), 0);
2017 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2021 if (!areJTsAllowed(TLI) || TSize.ult(4))
2024 APInt Range = ComputeRange(First, Last);
2025 double Density = TSize.roundToDouble() / Range.roundToDouble();
2029 DEBUG(dbgs() << "Lowering jump table\n"
2030 << "First entry: " << First << ". Last entry: " << Last << '\n'
2031 << "Range: " << Range
2032 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
2034 // Get the MachineFunction which holds the current MBB. This is used when
2035 // inserting any additional MBBs necessary to represent the switch.
2036 MachineFunction *CurMF = FuncInfo.MF;
2038 // Figure out which block is immediately after the current one.
2039 MachineFunction::iterator BBI = CR.CaseBB;
2042 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2044 // Create a new basic block to hold the code for loading the address
2045 // of the jump table, and jumping to it. Update successor information;
2046 // we will either branch to the default case for the switch, or the jump
2048 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2049 CurMF->insert(BBI, JumpTableBB);
2051 addSuccessorWithWeight(CR.CaseBB, Default);
2052 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2054 // Build a vector of destination BBs, corresponding to each target
2055 // of the jump table. If the value of the jump table slot corresponds to
2056 // a case statement, push the case's BB onto the vector, otherwise, push
2058 std::vector<MachineBasicBlock*> DestBBs;
2060 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2061 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2062 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2064 if (Low.sle(TEI) && TEI.sle(High)) {
2065 DestBBs.push_back(I->BB);
2069 DestBBs.push_back(Default);
2073 // Update successor info. Add one edge to each unique successor.
2074 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2075 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2076 E = DestBBs.end(); I != E; ++I) {
2077 if (!SuccsHandled[(*I)->getNumber()]) {
2078 SuccsHandled[(*I)->getNumber()] = true;
2079 addSuccessorWithWeight(JumpTableBB, *I);
2083 // Create a jump table index for this jump table.
2084 unsigned JTEncoding = TLI.getJumpTableEncoding();
2085 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2086 ->createJumpTableIndex(DestBBs);
2088 // Set the jump table information so that we can codegen it as a second
2089 // MachineBasicBlock
2090 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2091 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2092 if (CR.CaseBB == SwitchBB)
2093 visitJumpTableHeader(JT, JTH, SwitchBB);
2095 JTCases.push_back(JumpTableBlock(JTH, JT));
2100 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2102 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2103 CaseRecVector& WorkList,
2105 MachineBasicBlock *Default,
2106 MachineBasicBlock *SwitchBB) {
2107 // Get the MachineFunction which holds the current MBB. This is used when
2108 // inserting any additional MBBs necessary to represent the switch.
2109 MachineFunction *CurMF = FuncInfo.MF;
2111 // Figure out which block is immediately after the current one.
2112 MachineFunction::iterator BBI = CR.CaseBB;
2115 Case& FrontCase = *CR.Range.first;
2116 Case& BackCase = *(CR.Range.second-1);
2117 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2119 // Size is the number of Cases represented by this range.
2120 unsigned Size = CR.Range.second - CR.Range.first;
2122 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2123 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2125 CaseItr Pivot = CR.Range.first + Size/2;
2127 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2128 // (heuristically) allow us to emit JumpTable's later.
2129 APInt TSize(First.getBitWidth(), 0);
2130 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2134 APInt LSize = FrontCase.size();
2135 APInt RSize = TSize-LSize;
2136 DEBUG(dbgs() << "Selecting best pivot: \n"
2137 << "First: " << First << ", Last: " << Last <<'\n'
2138 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2139 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2141 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2142 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2143 APInt Range = ComputeRange(LEnd, RBegin);
2144 assert((Range - 2ULL).isNonNegative() &&
2145 "Invalid case distance");
2146 // Use volatile double here to avoid excess precision issues on some hosts,
2147 // e.g. that use 80-bit X87 registers.
2148 volatile double LDensity =
2149 (double)LSize.roundToDouble() /
2150 (LEnd - First + 1ULL).roundToDouble();
2151 volatile double RDensity =
2152 (double)RSize.roundToDouble() /
2153 (Last - RBegin + 1ULL).roundToDouble();
2154 double Metric = Range.logBase2()*(LDensity+RDensity);
2155 // Should always split in some non-trivial place
2156 DEBUG(dbgs() <<"=>Step\n"
2157 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2158 << "LDensity: " << LDensity
2159 << ", RDensity: " << RDensity << '\n'
2160 << "Metric: " << Metric << '\n');
2161 if (FMetric < Metric) {
2164 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2170 if (areJTsAllowed(TLI)) {
2171 // If our case is dense we *really* should handle it earlier!
2172 assert((FMetric > 0) && "Should handle dense range earlier!");
2174 Pivot = CR.Range.first + Size/2;
2177 CaseRange LHSR(CR.Range.first, Pivot);
2178 CaseRange RHSR(Pivot, CR.Range.second);
2179 Constant *C = Pivot->Low;
2180 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2182 // We know that we branch to the LHS if the Value being switched on is
2183 // less than the Pivot value, C. We use this to optimize our binary
2184 // tree a bit, by recognizing that if SV is greater than or equal to the
2185 // LHS's Case Value, and that Case Value is exactly one less than the
2186 // Pivot's Value, then we can branch directly to the LHS's Target,
2187 // rather than creating a leaf node for it.
2188 if ((LHSR.second - LHSR.first) == 1 &&
2189 LHSR.first->High == CR.GE &&
2190 cast<ConstantInt>(C)->getValue() ==
2191 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2192 TrueBB = LHSR.first->BB;
2194 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2195 CurMF->insert(BBI, TrueBB);
2196 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2198 // Put SV in a virtual register to make it available from the new blocks.
2199 ExportFromCurrentBlock(SV);
2202 // Similar to the optimization above, if the Value being switched on is
2203 // known to be less than the Constant CR.LT, and the current Case Value
2204 // is CR.LT - 1, then we can branch directly to the target block for
2205 // the current Case Value, rather than emitting a RHS leaf node for it.
2206 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2207 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2208 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2209 FalseBB = RHSR.first->BB;
2211 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2212 CurMF->insert(BBI, FalseBB);
2213 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2215 // Put SV in a virtual register to make it available from the new blocks.
2216 ExportFromCurrentBlock(SV);
2219 // Create a CaseBlock record representing a conditional branch to
2220 // the LHS node if the value being switched on SV is less than C.
2221 // Otherwise, branch to LHS.
2222 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2224 if (CR.CaseBB == SwitchBB)
2225 visitSwitchCase(CB, SwitchBB);
2227 SwitchCases.push_back(CB);
2232 /// handleBitTestsSwitchCase - if current case range has few destination and
2233 /// range span less, than machine word bitwidth, encode case range into series
2234 /// of masks and emit bit tests with these masks.
2235 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2236 CaseRecVector& WorkList,
2238 MachineBasicBlock* Default,
2239 MachineBasicBlock *SwitchBB){
2240 EVT PTy = TLI.getPointerTy();
2241 unsigned IntPtrBits = PTy.getSizeInBits();
2243 Case& FrontCase = *CR.Range.first;
2244 Case& BackCase = *(CR.Range.second-1);
2246 // Get the MachineFunction which holds the current MBB. This is used when
2247 // inserting any additional MBBs necessary to represent the switch.
2248 MachineFunction *CurMF = FuncInfo.MF;
2250 // If target does not have legal shift left, do not emit bit tests at all.
2251 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2255 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2257 // Single case counts one, case range - two.
2258 numCmps += (I->Low == I->High ? 1 : 2);
2261 // Count unique destinations
2262 SmallSet<MachineBasicBlock*, 4> Dests;
2263 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2264 Dests.insert(I->BB);
2265 if (Dests.size() > 3)
2266 // Don't bother the code below, if there are too much unique destinations
2269 DEBUG(dbgs() << "Total number of unique destinations: "
2270 << Dests.size() << '\n'
2271 << "Total number of comparisons: " << numCmps << '\n');
2273 // Compute span of values.
2274 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2275 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2276 APInt cmpRange = maxValue - minValue;
2278 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2279 << "Low bound: " << minValue << '\n'
2280 << "High bound: " << maxValue << '\n');
2282 if (cmpRange.uge(IntPtrBits) ||
2283 (!(Dests.size() == 1 && numCmps >= 3) &&
2284 !(Dests.size() == 2 && numCmps >= 5) &&
2285 !(Dests.size() >= 3 && numCmps >= 6)))
2288 DEBUG(dbgs() << "Emitting bit tests\n");
2289 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2291 // Optimize the case where all the case values fit in a
2292 // word without having to subtract minValue. In this case,
2293 // we can optimize away the subtraction.
2294 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2295 cmpRange = maxValue;
2297 lowBound = minValue;
2300 CaseBitsVector CasesBits;
2301 unsigned i, count = 0;
2303 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2304 MachineBasicBlock* Dest = I->BB;
2305 for (i = 0; i < count; ++i)
2306 if (Dest == CasesBits[i].BB)
2310 assert((count < 3) && "Too much destinations to test!");
2311 CasesBits.push_back(CaseBits(0, Dest, 0));
2315 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2316 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2318 uint64_t lo = (lowValue - lowBound).getZExtValue();
2319 uint64_t hi = (highValue - lowBound).getZExtValue();
2321 for (uint64_t j = lo; j <= hi; j++) {
2322 CasesBits[i].Mask |= 1ULL << j;
2323 CasesBits[i].Bits++;
2327 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2331 // Figure out which block is immediately after the current one.
2332 MachineFunction::iterator BBI = CR.CaseBB;
2335 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2337 DEBUG(dbgs() << "Cases:\n");
2338 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2339 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2340 << ", Bits: " << CasesBits[i].Bits
2341 << ", BB: " << CasesBits[i].BB << '\n');
2343 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2344 CurMF->insert(BBI, CaseBB);
2345 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2349 // Put SV in a virtual register to make it available from the new blocks.
2350 ExportFromCurrentBlock(SV);
2353 BitTestBlock BTB(lowBound, cmpRange, SV,
2354 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2355 CR.CaseBB, Default, BTC);
2357 if (CR.CaseBB == SwitchBB)
2358 visitBitTestHeader(BTB, SwitchBB);
2360 BitTestCases.push_back(BTB);
2365 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2366 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2367 const SwitchInst& SI) {
2370 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2371 // Start with "simple" cases
2372 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2373 BasicBlock *SuccBB = SI.getSuccessor(i);
2374 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2376 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0;
2378 Cases.push_back(Case(SI.getSuccessorValue(i),
2379 SI.getSuccessorValue(i),
2380 SMBB, ExtraWeight));
2382 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2384 // Merge case into clusters
2385 if (Cases.size() >= 2)
2386 // Must recompute end() each iteration because it may be
2387 // invalidated by erase if we hold on to it
2388 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2389 J != Cases.end(); ) {
2390 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2391 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2392 MachineBasicBlock* nextBB = J->BB;
2393 MachineBasicBlock* currentBB = I->BB;
2395 // If the two neighboring cases go to the same destination, merge them
2396 // into a single case.
2397 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2401 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) {
2402 uint32_t CurWeight = currentBB->getBasicBlock() ?
2403 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16;
2404 uint32_t NextWeight = nextBB->getBasicBlock() ?
2405 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16;
2407 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(),
2408 CurWeight + NextWeight);
2415 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2416 if (I->Low != I->High)
2417 // A range counts double, since it requires two compares.
2424 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2425 MachineBasicBlock *Last) {
2427 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2428 if (JTCases[i].first.HeaderBB == First)
2429 JTCases[i].first.HeaderBB = Last;
2431 // Update BitTestCases.
2432 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2433 if (BitTestCases[i].Parent == First)
2434 BitTestCases[i].Parent = Last;
2437 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2438 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2440 // Figure out which block is immediately after the current one.
2441 MachineBasicBlock *NextBlock = 0;
2442 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2444 // If there is only the default destination, branch to it if it is not the
2445 // next basic block. Otherwise, just fall through.
2446 if (SI.getNumOperands() == 2) {
2447 // Update machine-CFG edges.
2449 // If this is not a fall-through branch, emit the branch.
2450 SwitchMBB->addSuccessor(Default);
2451 if (Default != NextBlock)
2452 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2453 MVT::Other, getControlRoot(),
2454 DAG.getBasicBlock(Default)));
2459 // If there are any non-default case statements, create a vector of Cases
2460 // representing each one, and sort the vector so that we can efficiently
2461 // create a binary search tree from them.
2463 size_t numCmps = Clusterify(Cases, SI);
2464 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2465 << ". Total compares: " << numCmps << '\n');
2468 // Get the Value to be switched on and default basic blocks, which will be
2469 // inserted into CaseBlock records, representing basic blocks in the binary
2471 const Value *SV = SI.getOperand(0);
2473 // Push the initial CaseRec onto the worklist
2474 CaseRecVector WorkList;
2475 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2476 CaseRange(Cases.begin(),Cases.end())));
2478 while (!WorkList.empty()) {
2479 // Grab a record representing a case range to process off the worklist
2480 CaseRec CR = WorkList.back();
2481 WorkList.pop_back();
2483 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2486 // If the range has few cases (two or less) emit a series of specific
2488 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2491 // If the switch has more than 5 blocks, and at least 40% dense, and the
2492 // target supports indirect branches, then emit a jump table rather than
2493 // lowering the switch to a binary tree of conditional branches.
2494 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2497 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2498 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2499 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2503 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2504 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2506 // Update machine-CFG edges with unique successors.
2507 SmallVector<BasicBlock*, 32> succs;
2508 succs.reserve(I.getNumSuccessors());
2509 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2510 succs.push_back(I.getSuccessor(i));
2511 array_pod_sort(succs.begin(), succs.end());
2512 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2513 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2514 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2515 addSuccessorWithWeight(IndirectBrMBB, Succ);
2518 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2519 MVT::Other, getControlRoot(),
2520 getValue(I.getAddress())));
2523 void SelectionDAGBuilder::visitFSub(const User &I) {
2524 // -0.0 - X --> fneg
2525 Type *Ty = I.getType();
2526 if (isa<Constant>(I.getOperand(0)) &&
2527 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2528 SDValue Op2 = getValue(I.getOperand(1));
2529 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2530 Op2.getValueType(), Op2));
2534 visitBinary(I, ISD::FSUB);
2537 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2538 SDValue Op1 = getValue(I.getOperand(0));
2539 SDValue Op2 = getValue(I.getOperand(1));
2540 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2541 Op1.getValueType(), Op1, Op2));
2544 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2545 SDValue Op1 = getValue(I.getOperand(0));
2546 SDValue Op2 = getValue(I.getOperand(1));
2548 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2550 // Coerce the shift amount to the right type if we can.
2551 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2552 unsigned ShiftSize = ShiftTy.getSizeInBits();
2553 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2554 DebugLoc DL = getCurDebugLoc();
2556 // If the operand is smaller than the shift count type, promote it.
2557 if (ShiftSize > Op2Size)
2558 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2560 // If the operand is larger than the shift count type but the shift
2561 // count type has enough bits to represent any shift value, truncate
2562 // it now. This is a common case and it exposes the truncate to
2563 // optimization early.
2564 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2565 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2566 // Otherwise we'll need to temporarily settle for some other convenient
2567 // type. Type legalization will make adjustments once the shiftee is split.
2569 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2572 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2573 Op1.getValueType(), Op1, Op2));
2576 void SelectionDAGBuilder::visitSDiv(const User &I) {
2577 SDValue Op1 = getValue(I.getOperand(0));
2578 SDValue Op2 = getValue(I.getOperand(1));
2580 // Turn exact SDivs into multiplications.
2581 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2583 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2584 !isa<ConstantSDNode>(Op1) &&
2585 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2586 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2588 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2592 void SelectionDAGBuilder::visitICmp(const User &I) {
2593 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2594 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2595 predicate = IC->getPredicate();
2596 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2597 predicate = ICmpInst::Predicate(IC->getPredicate());
2598 SDValue Op1 = getValue(I.getOperand(0));
2599 SDValue Op2 = getValue(I.getOperand(1));
2600 ISD::CondCode Opcode = getICmpCondCode(predicate);
2602 EVT DestVT = TLI.getValueType(I.getType());
2603 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2606 void SelectionDAGBuilder::visitFCmp(const User &I) {
2607 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2608 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2609 predicate = FC->getPredicate();
2610 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2611 predicate = FCmpInst::Predicate(FC->getPredicate());
2612 SDValue Op1 = getValue(I.getOperand(0));
2613 SDValue Op2 = getValue(I.getOperand(1));
2614 ISD::CondCode Condition = getFCmpCondCode(predicate);
2615 EVT DestVT = TLI.getValueType(I.getType());
2616 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2619 void SelectionDAGBuilder::visitSelect(const User &I) {
2620 SmallVector<EVT, 4> ValueVTs;
2621 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2622 unsigned NumValues = ValueVTs.size();
2623 if (NumValues == 0) return;
2625 SmallVector<SDValue, 4> Values(NumValues);
2626 SDValue Cond = getValue(I.getOperand(0));
2627 SDValue TrueVal = getValue(I.getOperand(1));
2628 SDValue FalseVal = getValue(I.getOperand(2));
2630 for (unsigned i = 0; i != NumValues; ++i)
2631 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2632 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2634 SDValue(TrueVal.getNode(),
2635 TrueVal.getResNo() + i),
2636 SDValue(FalseVal.getNode(),
2637 FalseVal.getResNo() + i));
2639 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2640 DAG.getVTList(&ValueVTs[0], NumValues),
2641 &Values[0], NumValues));
2644 void SelectionDAGBuilder::visitTrunc(const User &I) {
2645 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2646 SDValue N = getValue(I.getOperand(0));
2647 EVT DestVT = TLI.getValueType(I.getType());
2648 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2651 void SelectionDAGBuilder::visitZExt(const User &I) {
2652 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2653 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2654 SDValue N = getValue(I.getOperand(0));
2655 EVT DestVT = TLI.getValueType(I.getType());
2656 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2659 void SelectionDAGBuilder::visitSExt(const User &I) {
2660 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2661 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2662 SDValue N = getValue(I.getOperand(0));
2663 EVT DestVT = TLI.getValueType(I.getType());
2664 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2667 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2668 // FPTrunc is never a no-op cast, no need to check
2669 SDValue N = getValue(I.getOperand(0));
2670 EVT DestVT = TLI.getValueType(I.getType());
2671 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2672 DestVT, N, DAG.getIntPtrConstant(0)));
2675 void SelectionDAGBuilder::visitFPExt(const User &I){
2676 // FPTrunc is never a no-op cast, no need to check
2677 SDValue N = getValue(I.getOperand(0));
2678 EVT DestVT = TLI.getValueType(I.getType());
2679 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2682 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2683 // FPToUI is never a no-op cast, no need to check
2684 SDValue N = getValue(I.getOperand(0));
2685 EVT DestVT = TLI.getValueType(I.getType());
2686 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2689 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2690 // FPToSI is never a no-op cast, no need to check
2691 SDValue N = getValue(I.getOperand(0));
2692 EVT DestVT = TLI.getValueType(I.getType());
2693 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2696 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2697 // UIToFP is never a no-op cast, no need to check
2698 SDValue N = getValue(I.getOperand(0));
2699 EVT DestVT = TLI.getValueType(I.getType());
2700 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2703 void SelectionDAGBuilder::visitSIToFP(const User &I){
2704 // SIToFP is never a no-op cast, no need to check
2705 SDValue N = getValue(I.getOperand(0));
2706 EVT DestVT = TLI.getValueType(I.getType());
2707 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2710 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2711 // What to do depends on the size of the integer and the size of the pointer.
2712 // We can either truncate, zero extend, or no-op, accordingly.
2713 SDValue N = getValue(I.getOperand(0));
2714 EVT DestVT = TLI.getValueType(I.getType());
2715 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2718 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2719 // What to do depends on the size of the integer and the size of the pointer.
2720 // We can either truncate, zero extend, or no-op, accordingly.
2721 SDValue N = getValue(I.getOperand(0));
2722 EVT DestVT = TLI.getValueType(I.getType());
2723 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2726 void SelectionDAGBuilder::visitBitCast(const User &I) {
2727 SDValue N = getValue(I.getOperand(0));
2728 EVT DestVT = TLI.getValueType(I.getType());
2730 // BitCast assures us that source and destination are the same size so this is
2731 // either a BITCAST or a no-op.
2732 if (DestVT != N.getValueType())
2733 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2734 DestVT, N)); // convert types.
2736 setValue(&I, N); // noop cast.
2739 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2740 SDValue InVec = getValue(I.getOperand(0));
2741 SDValue InVal = getValue(I.getOperand(1));
2742 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2744 getValue(I.getOperand(2)));
2745 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2746 TLI.getValueType(I.getType()),
2747 InVec, InVal, InIdx));
2750 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2751 SDValue InVec = getValue(I.getOperand(0));
2752 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2754 getValue(I.getOperand(1)));
2755 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2756 TLI.getValueType(I.getType()), InVec, InIdx));
2759 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2760 // from SIndx and increasing to the element length (undefs are allowed).
2761 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2762 unsigned MaskNumElts = Mask.size();
2763 for (unsigned i = 0; i != MaskNumElts; ++i)
2764 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2769 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2770 SmallVector<int, 8> Mask;
2771 SDValue Src1 = getValue(I.getOperand(0));
2772 SDValue Src2 = getValue(I.getOperand(1));
2774 // Convert the ConstantVector mask operand into an array of ints, with -1
2775 // representing undef values.
2776 SmallVector<Constant*, 8> MaskElts;
2777 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2778 unsigned MaskNumElts = MaskElts.size();
2779 for (unsigned i = 0; i != MaskNumElts; ++i) {
2780 if (isa<UndefValue>(MaskElts[i]))
2783 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2786 EVT VT = TLI.getValueType(I.getType());
2787 EVT SrcVT = Src1.getValueType();
2788 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2790 if (SrcNumElts == MaskNumElts) {
2791 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2796 // Normalize the shuffle vector since mask and vector length don't match.
2797 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2798 // Mask is longer than the source vectors and is a multiple of the source
2799 // vectors. We can use concatenate vector to make the mask and vectors
2801 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2802 // The shuffle is concatenating two vectors together.
2803 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2808 // Pad both vectors with undefs to make them the same length as the mask.
2809 unsigned NumConcat = MaskNumElts / SrcNumElts;
2810 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2811 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2812 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2814 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2815 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2819 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2820 getCurDebugLoc(), VT,
2821 &MOps1[0], NumConcat);
2822 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2823 getCurDebugLoc(), VT,
2824 &MOps2[0], NumConcat);
2826 // Readjust mask for new input vector length.
2827 SmallVector<int, 8> MappedOps;
2828 for (unsigned i = 0; i != MaskNumElts; ++i) {
2830 if (Idx < (int)SrcNumElts)
2831 MappedOps.push_back(Idx);
2833 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2836 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2841 if (SrcNumElts > MaskNumElts) {
2842 // Analyze the access pattern of the vector to see if we can extract
2843 // two subvectors and do the shuffle. The analysis is done by calculating
2844 // the range of elements the mask access on both vectors.
2845 int MinRange[2] = { static_cast<int>(SrcNumElts+1),
2846 static_cast<int>(SrcNumElts+1)};
2847 int MaxRange[2] = {-1, -1};
2849 for (unsigned i = 0; i != MaskNumElts; ++i) {
2855 if (Idx >= (int)SrcNumElts) {
2859 if (Idx > MaxRange[Input])
2860 MaxRange[Input] = Idx;
2861 if (Idx < MinRange[Input])
2862 MinRange[Input] = Idx;
2865 // Check if the access is smaller than the vector size and can we find
2866 // a reasonable extract index.
2867 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2869 int StartIdx[2]; // StartIdx to extract from
2870 for (int Input=0; Input < 2; ++Input) {
2871 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2872 RangeUse[Input] = 0; // Unused
2873 StartIdx[Input] = 0;
2874 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2875 // Fits within range but we should see if we can find a good
2876 // start index that is a multiple of the mask length.
2877 if (MaxRange[Input] < (int)MaskNumElts) {
2878 RangeUse[Input] = 1; // Extract from beginning of the vector
2879 StartIdx[Input] = 0;
2881 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2882 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2883 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2884 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2889 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2890 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2893 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2894 // Extract appropriate subvector and generate a vector shuffle
2895 for (int Input=0; Input < 2; ++Input) {
2896 SDValue &Src = Input == 0 ? Src1 : Src2;
2897 if (RangeUse[Input] == 0)
2898 Src = DAG.getUNDEF(VT);
2900 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2901 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2904 // Calculate new mask.
2905 SmallVector<int, 8> MappedOps;
2906 for (unsigned i = 0; i != MaskNumElts; ++i) {
2909 MappedOps.push_back(Idx);
2910 else if (Idx < (int)SrcNumElts)
2911 MappedOps.push_back(Idx - StartIdx[0]);
2913 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2916 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2922 // We can't use either concat vectors or extract subvectors so fall back to
2923 // replacing the shuffle with extract and build vector.
2924 // to insert and build vector.
2925 EVT EltVT = VT.getVectorElementType();
2926 EVT PtrVT = TLI.getPointerTy();
2927 SmallVector<SDValue,8> Ops;
2928 for (unsigned i = 0; i != MaskNumElts; ++i) {
2930 Ops.push_back(DAG.getUNDEF(EltVT));
2935 if (Idx < (int)SrcNumElts)
2936 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2937 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2939 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2941 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2947 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2948 VT, &Ops[0], Ops.size()));
2951 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2952 const Value *Op0 = I.getOperand(0);
2953 const Value *Op1 = I.getOperand(1);
2954 Type *AggTy = I.getType();
2955 Type *ValTy = Op1->getType();
2956 bool IntoUndef = isa<UndefValue>(Op0);
2957 bool FromUndef = isa<UndefValue>(Op1);
2959 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2961 SmallVector<EVT, 4> AggValueVTs;
2962 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2963 SmallVector<EVT, 4> ValValueVTs;
2964 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2966 unsigned NumAggValues = AggValueVTs.size();
2967 unsigned NumValValues = ValValueVTs.size();
2968 SmallVector<SDValue, 4> Values(NumAggValues);
2970 SDValue Agg = getValue(Op0);
2972 // Copy the beginning value(s) from the original aggregate.
2973 for (; i != LinearIndex; ++i)
2974 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2975 SDValue(Agg.getNode(), Agg.getResNo() + i);
2976 // Copy values from the inserted value(s).
2978 SDValue Val = getValue(Op1);
2979 for (; i != LinearIndex + NumValValues; ++i)
2980 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2981 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2983 // Copy remaining value(s) from the original aggregate.
2984 for (; i != NumAggValues; ++i)
2985 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2986 SDValue(Agg.getNode(), Agg.getResNo() + i);
2988 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2989 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2990 &Values[0], NumAggValues));
2993 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2994 const Value *Op0 = I.getOperand(0);
2995 Type *AggTy = Op0->getType();
2996 Type *ValTy = I.getType();
2997 bool OutOfUndef = isa<UndefValue>(Op0);
2999 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3001 SmallVector<EVT, 4> ValValueVTs;
3002 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3004 unsigned NumValValues = ValValueVTs.size();
3006 // Ignore a extractvalue that produces an empty object
3007 if (!NumValValues) {
3008 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3012 SmallVector<SDValue, 4> Values(NumValValues);
3014 SDValue Agg = getValue(Op0);
3015 // Copy out the selected value(s).
3016 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3017 Values[i - LinearIndex] =
3019 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3020 SDValue(Agg.getNode(), Agg.getResNo() + i);
3022 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3023 DAG.getVTList(&ValValueVTs[0], NumValValues),
3024 &Values[0], NumValValues));
3027 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3028 SDValue N = getValue(I.getOperand(0));
3029 Type *Ty = I.getOperand(0)->getType();
3031 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3033 const Value *Idx = *OI;
3034 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3035 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3038 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3039 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3040 DAG.getIntPtrConstant(Offset));
3043 Ty = StTy->getElementType(Field);
3045 Ty = cast<SequentialType>(Ty)->getElementType();
3047 // If this is a constant subscript, handle it quickly.
3048 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3049 if (CI->isZero()) continue;
3051 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3053 EVT PTy = TLI.getPointerTy();
3054 unsigned PtrBits = PTy.getSizeInBits();
3056 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3058 DAG.getConstant(Offs, MVT::i64));
3060 OffsVal = DAG.getIntPtrConstant(Offs);
3062 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3067 // N = N + Idx * ElementSize;
3068 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3069 TD->getTypeAllocSize(Ty));
3070 SDValue IdxN = getValue(Idx);
3072 // If the index is smaller or larger than intptr_t, truncate or extend
3074 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3076 // If this is a multiply by a power of two, turn it into a shl
3077 // immediately. This is a very common case.
3078 if (ElementSize != 1) {
3079 if (ElementSize.isPowerOf2()) {
3080 unsigned Amt = ElementSize.logBase2();
3081 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3082 N.getValueType(), IdxN,
3083 DAG.getConstant(Amt, TLI.getPointerTy()));
3085 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3086 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3087 N.getValueType(), IdxN, Scale);
3091 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3092 N.getValueType(), N, IdxN);
3099 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3100 // If this is a fixed sized alloca in the entry block of the function,
3101 // allocate it statically on the stack.
3102 if (FuncInfo.StaticAllocaMap.count(&I))
3103 return; // getValue will auto-populate this.
3105 Type *Ty = I.getAllocatedType();
3106 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3108 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3111 SDValue AllocSize = getValue(I.getArraySize());
3113 EVT IntPtr = TLI.getPointerTy();
3114 if (AllocSize.getValueType() != IntPtr)
3115 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3117 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3119 DAG.getConstant(TySize, IntPtr));
3121 // Handle alignment. If the requested alignment is less than or equal to
3122 // the stack alignment, ignore it. If the size is greater than or equal to
3123 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3124 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3125 if (Align <= StackAlign)
3128 // Round the size of the allocation up to the stack alignment size
3129 // by add SA-1 to the size.
3130 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3131 AllocSize.getValueType(), AllocSize,
3132 DAG.getIntPtrConstant(StackAlign-1));
3134 // Mask out the low bits for alignment purposes.
3135 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3136 AllocSize.getValueType(), AllocSize,
3137 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3139 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3140 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3141 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3144 DAG.setRoot(DSA.getValue(1));
3146 // Inform the Frame Information that we have just allocated a variable-sized
3148 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3151 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3153 return visitAtomicLoad(I);
3155 const Value *SV = I.getOperand(0);
3156 SDValue Ptr = getValue(SV);
3158 Type *Ty = I.getType();
3160 bool isVolatile = I.isVolatile();
3161 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3162 unsigned Alignment = I.getAlignment();
3163 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3165 SmallVector<EVT, 4> ValueVTs;
3166 SmallVector<uint64_t, 4> Offsets;
3167 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3168 unsigned NumValues = ValueVTs.size();
3173 bool ConstantMemory = false;
3174 if (I.isVolatile() || NumValues > MaxParallelChains)
3175 // Serialize volatile loads with other side effects.
3177 else if (AA->pointsToConstantMemory(
3178 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3179 // Do not serialize (non-volatile) loads of constant memory with anything.
3180 Root = DAG.getEntryNode();
3181 ConstantMemory = true;
3183 // Do not serialize non-volatile loads against each other.
3184 Root = DAG.getRoot();
3187 SmallVector<SDValue, 4> Values(NumValues);
3188 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3190 EVT PtrVT = Ptr.getValueType();
3191 unsigned ChainI = 0;
3192 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3193 // Serializing loads here may result in excessive register pressure, and
3194 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3195 // could recover a bit by hoisting nodes upward in the chain by recognizing
3196 // they are side-effect free or do not alias. The optimizer should really
3197 // avoid this case by converting large object/array copies to llvm.memcpy
3198 // (MaxParallelChains should always remain as failsafe).
3199 if (ChainI == MaxParallelChains) {
3200 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3201 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3202 MVT::Other, &Chains[0], ChainI);
3206 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3208 DAG.getConstant(Offsets[i], PtrVT));
3209 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3210 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3211 isNonTemporal, Alignment, TBAAInfo);
3214 Chains[ChainI] = L.getValue(1);
3217 if (!ConstantMemory) {
3218 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3219 MVT::Other, &Chains[0], ChainI);
3223 PendingLoads.push_back(Chain);
3226 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3227 DAG.getVTList(&ValueVTs[0], NumValues),
3228 &Values[0], NumValues));
3231 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3233 return visitAtomicStore(I);
3235 const Value *SrcV = I.getOperand(0);
3236 const Value *PtrV = I.getOperand(1);
3238 SmallVector<EVT, 4> ValueVTs;
3239 SmallVector<uint64_t, 4> Offsets;
3240 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3241 unsigned NumValues = ValueVTs.size();
3245 // Get the lowered operands. Note that we do this after
3246 // checking if NumResults is zero, because with zero results
3247 // the operands won't have values in the map.
3248 SDValue Src = getValue(SrcV);
3249 SDValue Ptr = getValue(PtrV);
3251 SDValue Root = getRoot();
3252 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3254 EVT PtrVT = Ptr.getValueType();
3255 bool isVolatile = I.isVolatile();
3256 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3257 unsigned Alignment = I.getAlignment();
3258 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3260 unsigned ChainI = 0;
3261 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3262 // See visitLoad comments.
3263 if (ChainI == MaxParallelChains) {
3264 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3265 MVT::Other, &Chains[0], ChainI);
3269 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3270 DAG.getConstant(Offsets[i], PtrVT));
3271 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3272 SDValue(Src.getNode(), Src.getResNo() + i),
3273 Add, MachinePointerInfo(PtrV, Offsets[i]),
3274 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3275 Chains[ChainI] = St;
3278 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3279 MVT::Other, &Chains[0], ChainI);
3281 AssignOrderingToNode(StoreNode.getNode());
3282 DAG.setRoot(StoreNode);
3285 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3286 SynchronizationScope Scope,
3287 bool Before, DebugLoc dl,
3289 const TargetLowering &TLI) {
3290 // Fence, if necessary
3292 if (Order == AcquireRelease)
3294 else if (Order == Acquire || Order == Monotonic)
3297 if (Order == AcquireRelease)
3299 else if (Order == Release || Order == Monotonic)
3304 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3305 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3306 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3309 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3310 DebugLoc dl = getCurDebugLoc();
3311 AtomicOrdering Order = I.getOrdering();
3312 SynchronizationScope Scope = I.getSynchScope();
3314 SDValue InChain = getRoot();
3316 if (TLI.getInsertFencesForAtomic())
3317 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3321 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3322 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3324 getValue(I.getPointerOperand()),
3325 getValue(I.getCompareOperand()),
3326 getValue(I.getNewValOperand()),
3327 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3328 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3331 SDValue OutChain = L.getValue(1);
3333 if (TLI.getInsertFencesForAtomic())
3334 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3338 DAG.setRoot(OutChain);
3341 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3342 DebugLoc dl = getCurDebugLoc();
3344 switch (I.getOperation()) {
3345 default: llvm_unreachable("Unknown atomicrmw operation"); return;
3346 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3347 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3348 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3349 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3350 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3351 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3352 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3353 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3354 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3355 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3356 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3358 AtomicOrdering Order = I.getOrdering();
3359 SynchronizationScope Scope = I.getSynchScope();
3361 SDValue InChain = getRoot();
3363 if (TLI.getInsertFencesForAtomic())
3364 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3368 DAG.getAtomic(NT, dl,
3369 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3371 getValue(I.getPointerOperand()),
3372 getValue(I.getValOperand()),
3373 I.getPointerOperand(), 0 /* Alignment */,
3374 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3377 SDValue OutChain = L.getValue(1);
3379 if (TLI.getInsertFencesForAtomic())
3380 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3384 DAG.setRoot(OutChain);
3387 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3388 DebugLoc dl = getCurDebugLoc();
3391 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3392 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3393 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3396 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3397 DebugLoc dl = getCurDebugLoc();
3398 AtomicOrdering Order = I.getOrdering();
3399 SynchronizationScope Scope = I.getSynchScope();
3401 SDValue InChain = getRoot();
3403 if (TLI.getInsertFencesForAtomic())
3404 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3407 EVT VT = EVT::getEVT(I.getType());
3410 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3411 getValue(I.getPointerOperand()),
3412 I.getPointerOperand(), I.getAlignment(),
3413 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3416 SDValue OutChain = L.getValue(1);
3418 if (TLI.getInsertFencesForAtomic())
3419 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3423 DAG.setRoot(OutChain);
3426 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3427 DebugLoc dl = getCurDebugLoc();
3429 AtomicOrdering Order = I.getOrdering();
3430 SynchronizationScope Scope = I.getSynchScope();
3432 SDValue InChain = getRoot();
3434 if (TLI.getInsertFencesForAtomic())
3435 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3439 DAG.getAtomic(ISD::ATOMIC_STORE, dl,
3440 getValue(I.getValueOperand()).getValueType().getSimpleVT(),
3442 getValue(I.getPointerOperand()),
3443 getValue(I.getValueOperand()),
3444 I.getPointerOperand(), I.getAlignment(),
3445 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3448 if (TLI.getInsertFencesForAtomic())
3449 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3452 DAG.setRoot(OutChain);
3455 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3457 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3458 unsigned Intrinsic) {
3459 bool HasChain = !I.doesNotAccessMemory();
3460 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3462 // Build the operand list.
3463 SmallVector<SDValue, 8> Ops;
3464 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3466 // We don't need to serialize loads against other loads.
3467 Ops.push_back(DAG.getRoot());
3469 Ops.push_back(getRoot());
3473 // Info is set by getTgtMemInstrinsic
3474 TargetLowering::IntrinsicInfo Info;
3475 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3477 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3478 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3479 Info.opc == ISD::INTRINSIC_W_CHAIN)
3480 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3482 // Add all operands of the call to the operand list.
3483 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3484 SDValue Op = getValue(I.getArgOperand(i));
3485 assert(TLI.isTypeLegal(Op.getValueType()) &&
3486 "Intrinsic uses a non-legal type?");
3490 SmallVector<EVT, 4> ValueVTs;
3491 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3493 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3494 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3495 "Intrinsic uses a non-legal type?");
3500 ValueVTs.push_back(MVT::Other);
3502 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3506 if (IsTgtIntrinsic) {
3507 // This is target intrinsic that touches memory
3508 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3509 VTs, &Ops[0], Ops.size(),
3511 MachinePointerInfo(Info.ptrVal, Info.offset),
3512 Info.align, Info.vol,
3513 Info.readMem, Info.writeMem);
3514 } else if (!HasChain) {
3515 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3516 VTs, &Ops[0], Ops.size());
3517 } else if (!I.getType()->isVoidTy()) {
3518 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3519 VTs, &Ops[0], Ops.size());
3521 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3522 VTs, &Ops[0], Ops.size());
3526 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3528 PendingLoads.push_back(Chain);
3533 if (!I.getType()->isVoidTy()) {
3534 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3535 EVT VT = TLI.getValueType(PTy);
3536 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3539 setValue(&I, Result);
3543 /// GetSignificand - Get the significand and build it into a floating-point
3544 /// number with exponent of 1:
3546 /// Op = (Op & 0x007fffff) | 0x3f800000;
3548 /// where Op is the hexidecimal representation of floating point value.
3550 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3551 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3552 DAG.getConstant(0x007fffff, MVT::i32));
3553 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3554 DAG.getConstant(0x3f800000, MVT::i32));
3555 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3558 /// GetExponent - Get the exponent:
3560 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3562 /// where Op is the hexidecimal representation of floating point value.
3564 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3566 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3567 DAG.getConstant(0x7f800000, MVT::i32));
3568 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3569 DAG.getConstant(23, TLI.getPointerTy()));
3570 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3571 DAG.getConstant(127, MVT::i32));
3572 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3575 /// getF32Constant - Get 32-bit floating point constant.
3577 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3578 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3581 /// Inlined utility function to implement binary input atomic intrinsics for
3582 /// visitIntrinsicCall: I is a call instruction
3583 /// Op is the associated NodeType for I
3585 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3587 SDValue Root = getRoot();
3589 DAG.getAtomic(Op, getCurDebugLoc(),
3590 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3592 getValue(I.getArgOperand(0)),
3593 getValue(I.getArgOperand(1)),
3594 I.getArgOperand(0), 0 /* Alignment */,
3595 Monotonic, CrossThread);
3597 DAG.setRoot(L.getValue(1));
3601 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3603 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3604 SDValue Op1 = getValue(I.getArgOperand(0));
3605 SDValue Op2 = getValue(I.getArgOperand(1));
3607 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3608 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3612 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3613 /// limited-precision mode.
3615 SelectionDAGBuilder::visitExp(const CallInst &I) {
3617 DebugLoc dl = getCurDebugLoc();
3619 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3620 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3621 SDValue Op = getValue(I.getArgOperand(0));
3623 // Put the exponent in the right bit position for later addition to the
3626 // #define LOG2OFe 1.4426950f
3627 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3628 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3629 getF32Constant(DAG, 0x3fb8aa3b));
3630 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3632 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3633 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3634 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3636 // IntegerPartOfX <<= 23;
3637 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3638 DAG.getConstant(23, TLI.getPointerTy()));
3640 if (LimitFloatPrecision <= 6) {
3641 // For floating-point precision of 6:
3643 // TwoToFractionalPartOfX =
3645 // (0.735607626f + 0.252464424f * x) * x;
3647 // error 0.0144103317, which is 6 bits
3648 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3649 getF32Constant(DAG, 0x3e814304));
3650 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3651 getF32Constant(DAG, 0x3f3c50c8));
3652 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3653 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3654 getF32Constant(DAG, 0x3f7f5e7e));
3655 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3657 // Add the exponent into the result in integer domain.
3658 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3659 TwoToFracPartOfX, IntegerPartOfX);
3661 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3662 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3663 // For floating-point precision of 12:
3665 // TwoToFractionalPartOfX =
3668 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3670 // 0.000107046256 error, which is 13 to 14 bits
3671 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3672 getF32Constant(DAG, 0x3da235e3));
3673 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3674 getF32Constant(DAG, 0x3e65b8f3));
3675 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3676 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3677 getF32Constant(DAG, 0x3f324b07));
3678 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3679 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3680 getF32Constant(DAG, 0x3f7ff8fd));
3681 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3683 // Add the exponent into the result in integer domain.
3684 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3685 TwoToFracPartOfX, IntegerPartOfX);
3687 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3688 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3689 // For floating-point precision of 18:
3691 // TwoToFractionalPartOfX =
3695 // (0.554906021e-1f +
3696 // (0.961591928e-2f +
3697 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3699 // error 2.47208000*10^(-7), which is better than 18 bits
3700 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3701 getF32Constant(DAG, 0x3924b03e));
3702 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3703 getF32Constant(DAG, 0x3ab24b87));
3704 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3705 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3706 getF32Constant(DAG, 0x3c1d8c17));
3707 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3708 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3709 getF32Constant(DAG, 0x3d634a1d));
3710 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3711 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3712 getF32Constant(DAG, 0x3e75fe14));
3713 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3714 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3715 getF32Constant(DAG, 0x3f317234));
3716 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3717 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3718 getF32Constant(DAG, 0x3f800000));
3719 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3722 // Add the exponent into the result in integer domain.
3723 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3724 TwoToFracPartOfX, IntegerPartOfX);
3726 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3729 // No special expansion.
3730 result = DAG.getNode(ISD::FEXP, dl,
3731 getValue(I.getArgOperand(0)).getValueType(),
3732 getValue(I.getArgOperand(0)));
3735 setValue(&I, result);
3738 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3739 /// limited-precision mode.
3741 SelectionDAGBuilder::visitLog(const CallInst &I) {
3743 DebugLoc dl = getCurDebugLoc();
3745 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3746 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3747 SDValue Op = getValue(I.getArgOperand(0));
3748 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3750 // Scale the exponent by log(2) [0.69314718f].
3751 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3752 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3753 getF32Constant(DAG, 0x3f317218));
3755 // Get the significand and build it into a floating-point number with
3757 SDValue X = GetSignificand(DAG, Op1, dl);
3759 if (LimitFloatPrecision <= 6) {
3760 // For floating-point precision of 6:
3764 // (1.4034025f - 0.23903021f * x) * x;
3766 // error 0.0034276066, which is better than 8 bits
3767 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3768 getF32Constant(DAG, 0xbe74c456));
3769 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3770 getF32Constant(DAG, 0x3fb3a2b1));
3771 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3772 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3773 getF32Constant(DAG, 0x3f949a29));
3775 result = DAG.getNode(ISD::FADD, dl,
3776 MVT::f32, LogOfExponent, LogOfMantissa);
3777 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3778 // For floating-point precision of 12:
3784 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3786 // error 0.000061011436, which is 14 bits
3787 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3788 getF32Constant(DAG, 0xbd67b6d6));
3789 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3790 getF32Constant(DAG, 0x3ee4f4b8));
3791 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3792 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3793 getF32Constant(DAG, 0x3fbc278b));
3794 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3795 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3796 getF32Constant(DAG, 0x40348e95));
3797 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3798 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3799 getF32Constant(DAG, 0x3fdef31a));
3801 result = DAG.getNode(ISD::FADD, dl,
3802 MVT::f32, LogOfExponent, LogOfMantissa);
3803 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3804 // For floating-point precision of 18:
3812 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3814 // error 0.0000023660568, which is better than 18 bits
3815 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3816 getF32Constant(DAG, 0xbc91e5ac));
3817 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3818 getF32Constant(DAG, 0x3e4350aa));
3819 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3820 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3821 getF32Constant(DAG, 0x3f60d3e3));
3822 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3823 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3824 getF32Constant(DAG, 0x4011cdf0));
3825 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3826 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3827 getF32Constant(DAG, 0x406cfd1c));
3828 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3829 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3830 getF32Constant(DAG, 0x408797cb));
3831 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3832 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3833 getF32Constant(DAG, 0x4006dcab));
3835 result = DAG.getNode(ISD::FADD, dl,
3836 MVT::f32, LogOfExponent, LogOfMantissa);
3839 // No special expansion.
3840 result = DAG.getNode(ISD::FLOG, dl,
3841 getValue(I.getArgOperand(0)).getValueType(),
3842 getValue(I.getArgOperand(0)));
3845 setValue(&I, result);
3848 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3849 /// limited-precision mode.
3851 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3853 DebugLoc dl = getCurDebugLoc();
3855 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3856 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3857 SDValue Op = getValue(I.getArgOperand(0));
3858 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3860 // Get the exponent.
3861 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3863 // Get the significand and build it into a floating-point number with
3865 SDValue X = GetSignificand(DAG, Op1, dl);
3867 // Different possible minimax approximations of significand in
3868 // floating-point for various degrees of accuracy over [1,2].
3869 if (LimitFloatPrecision <= 6) {
3870 // For floating-point precision of 6:
3872 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3874 // error 0.0049451742, which is more than 7 bits
3875 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3876 getF32Constant(DAG, 0xbeb08fe0));
3877 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3878 getF32Constant(DAG, 0x40019463));
3879 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3880 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3881 getF32Constant(DAG, 0x3fd6633d));
3883 result = DAG.getNode(ISD::FADD, dl,
3884 MVT::f32, LogOfExponent, Log2ofMantissa);
3885 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3886 // For floating-point precision of 12:
3892 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3894 // error 0.0000876136000, which is better than 13 bits
3895 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3896 getF32Constant(DAG, 0xbda7262e));
3897 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3898 getF32Constant(DAG, 0x3f25280b));
3899 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3900 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3901 getF32Constant(DAG, 0x4007b923));
3902 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3903 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3904 getF32Constant(DAG, 0x40823e2f));
3905 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3906 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3907 getF32Constant(DAG, 0x4020d29c));
3909 result = DAG.getNode(ISD::FADD, dl,
3910 MVT::f32, LogOfExponent, Log2ofMantissa);
3911 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3912 // For floating-point precision of 18:
3921 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3923 // error 0.0000018516, which is better than 18 bits
3924 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3925 getF32Constant(DAG, 0xbcd2769e));
3926 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3927 getF32Constant(DAG, 0x3e8ce0b9));
3928 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3929 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3930 getF32Constant(DAG, 0x3fa22ae7));
3931 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3932 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3933 getF32Constant(DAG, 0x40525723));
3934 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3935 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3936 getF32Constant(DAG, 0x40aaf200));
3937 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3938 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3939 getF32Constant(DAG, 0x40c39dad));
3940 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3941 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3942 getF32Constant(DAG, 0x4042902c));
3944 result = DAG.getNode(ISD::FADD, dl,
3945 MVT::f32, LogOfExponent, Log2ofMantissa);
3948 // No special expansion.
3949 result = DAG.getNode(ISD::FLOG2, dl,
3950 getValue(I.getArgOperand(0)).getValueType(),
3951 getValue(I.getArgOperand(0)));
3954 setValue(&I, result);
3957 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3958 /// limited-precision mode.
3960 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3962 DebugLoc dl = getCurDebugLoc();
3964 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3965 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3966 SDValue Op = getValue(I.getArgOperand(0));
3967 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3969 // Scale the exponent by log10(2) [0.30102999f].
3970 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3971 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3972 getF32Constant(DAG, 0x3e9a209a));
3974 // Get the significand and build it into a floating-point number with
3976 SDValue X = GetSignificand(DAG, Op1, dl);
3978 if (LimitFloatPrecision <= 6) {
3979 // For floating-point precision of 6:
3981 // Log10ofMantissa =
3983 // (0.60948995f - 0.10380950f * x) * x;
3985 // error 0.0014886165, which is 6 bits
3986 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3987 getF32Constant(DAG, 0xbdd49a13));
3988 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3989 getF32Constant(DAG, 0x3f1c0789));
3990 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3991 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3992 getF32Constant(DAG, 0x3f011300));
3994 result = DAG.getNode(ISD::FADD, dl,
3995 MVT::f32, LogOfExponent, Log10ofMantissa);
3996 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3997 // For floating-point precision of 12:
3999 // Log10ofMantissa =
4002 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4004 // error 0.00019228036, which is better than 12 bits
4005 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4006 getF32Constant(DAG, 0x3d431f31));
4007 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4008 getF32Constant(DAG, 0x3ea21fb2));
4009 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4010 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4011 getF32Constant(DAG, 0x3f6ae232));
4012 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4013 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4014 getF32Constant(DAG, 0x3f25f7c3));
4016 result = DAG.getNode(ISD::FADD, dl,
4017 MVT::f32, LogOfExponent, Log10ofMantissa);
4018 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4019 // For floating-point precision of 18:
4021 // Log10ofMantissa =
4026 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4028 // error 0.0000037995730, which is better than 18 bits
4029 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4030 getF32Constant(DAG, 0x3c5d51ce));
4031 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4032 getF32Constant(DAG, 0x3e00685a));
4033 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4034 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4035 getF32Constant(DAG, 0x3efb6798));
4036 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4037 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4038 getF32Constant(DAG, 0x3f88d192));
4039 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4040 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4041 getF32Constant(DAG, 0x3fc4316c));
4042 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4043 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4044 getF32Constant(DAG, 0x3f57ce70));
4046 result = DAG.getNode(ISD::FADD, dl,
4047 MVT::f32, LogOfExponent, Log10ofMantissa);
4050 // No special expansion.
4051 result = DAG.getNode(ISD::FLOG10, dl,
4052 getValue(I.getArgOperand(0)).getValueType(),
4053 getValue(I.getArgOperand(0)));
4056 setValue(&I, result);
4059 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4060 /// limited-precision mode.
4062 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4064 DebugLoc dl = getCurDebugLoc();
4066 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4067 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4068 SDValue Op = getValue(I.getArgOperand(0));
4070 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4072 // FractionalPartOfX = x - (float)IntegerPartOfX;
4073 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4074 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4076 // IntegerPartOfX <<= 23;
4077 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4078 DAG.getConstant(23, TLI.getPointerTy()));
4080 if (LimitFloatPrecision <= 6) {
4081 // For floating-point precision of 6:
4083 // TwoToFractionalPartOfX =
4085 // (0.735607626f + 0.252464424f * x) * x;
4087 // error 0.0144103317, which is 6 bits
4088 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4089 getF32Constant(DAG, 0x3e814304));
4090 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4091 getF32Constant(DAG, 0x3f3c50c8));
4092 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4093 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4094 getF32Constant(DAG, 0x3f7f5e7e));
4095 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4096 SDValue TwoToFractionalPartOfX =
4097 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4099 result = DAG.getNode(ISD::BITCAST, dl,
4100 MVT::f32, TwoToFractionalPartOfX);
4101 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4102 // For floating-point precision of 12:
4104 // TwoToFractionalPartOfX =
4107 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4109 // error 0.000107046256, which is 13 to 14 bits
4110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4111 getF32Constant(DAG, 0x3da235e3));
4112 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4113 getF32Constant(DAG, 0x3e65b8f3));
4114 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4115 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4116 getF32Constant(DAG, 0x3f324b07));
4117 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4118 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4119 getF32Constant(DAG, 0x3f7ff8fd));
4120 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4121 SDValue TwoToFractionalPartOfX =
4122 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4124 result = DAG.getNode(ISD::BITCAST, dl,
4125 MVT::f32, TwoToFractionalPartOfX);
4126 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4127 // For floating-point precision of 18:
4129 // TwoToFractionalPartOfX =
4133 // (0.554906021e-1f +
4134 // (0.961591928e-2f +
4135 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4136 // error 2.47208000*10^(-7), which is better than 18 bits
4137 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4138 getF32Constant(DAG, 0x3924b03e));
4139 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4140 getF32Constant(DAG, 0x3ab24b87));
4141 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4142 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4143 getF32Constant(DAG, 0x3c1d8c17));
4144 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4145 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4146 getF32Constant(DAG, 0x3d634a1d));
4147 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4148 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4149 getF32Constant(DAG, 0x3e75fe14));
4150 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4151 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4152 getF32Constant(DAG, 0x3f317234));
4153 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4154 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4155 getF32Constant(DAG, 0x3f800000));
4156 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4157 SDValue TwoToFractionalPartOfX =
4158 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4160 result = DAG.getNode(ISD::BITCAST, dl,
4161 MVT::f32, TwoToFractionalPartOfX);
4164 // No special expansion.
4165 result = DAG.getNode(ISD::FEXP2, dl,
4166 getValue(I.getArgOperand(0)).getValueType(),
4167 getValue(I.getArgOperand(0)));
4170 setValue(&I, result);
4173 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4174 /// limited-precision mode with x == 10.0f.
4176 SelectionDAGBuilder::visitPow(const CallInst &I) {
4178 const Value *Val = I.getArgOperand(0);
4179 DebugLoc dl = getCurDebugLoc();
4180 bool IsExp10 = false;
4182 if (getValue(Val).getValueType() == MVT::f32 &&
4183 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4184 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4185 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4186 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4188 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4193 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4194 SDValue Op = getValue(I.getArgOperand(1));
4196 // Put the exponent in the right bit position for later addition to the
4199 // #define LOG2OF10 3.3219281f
4200 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4201 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4202 getF32Constant(DAG, 0x40549a78));
4203 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4205 // FractionalPartOfX = x - (float)IntegerPartOfX;
4206 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4207 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4209 // IntegerPartOfX <<= 23;
4210 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4211 DAG.getConstant(23, TLI.getPointerTy()));
4213 if (LimitFloatPrecision <= 6) {
4214 // For floating-point precision of 6:
4216 // twoToFractionalPartOfX =
4218 // (0.735607626f + 0.252464424f * x) * x;
4220 // error 0.0144103317, which is 6 bits
4221 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4222 getF32Constant(DAG, 0x3e814304));
4223 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4224 getF32Constant(DAG, 0x3f3c50c8));
4225 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4226 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4227 getF32Constant(DAG, 0x3f7f5e7e));
4228 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4229 SDValue TwoToFractionalPartOfX =
4230 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4232 result = DAG.getNode(ISD::BITCAST, dl,
4233 MVT::f32, TwoToFractionalPartOfX);
4234 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4235 // For floating-point precision of 12:
4237 // TwoToFractionalPartOfX =
4240 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4242 // error 0.000107046256, which is 13 to 14 bits
4243 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4244 getF32Constant(DAG, 0x3da235e3));
4245 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4246 getF32Constant(DAG, 0x3e65b8f3));
4247 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4248 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4249 getF32Constant(DAG, 0x3f324b07));
4250 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4251 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4252 getF32Constant(DAG, 0x3f7ff8fd));
4253 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4254 SDValue TwoToFractionalPartOfX =
4255 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4257 result = DAG.getNode(ISD::BITCAST, dl,
4258 MVT::f32, TwoToFractionalPartOfX);
4259 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4260 // For floating-point precision of 18:
4262 // TwoToFractionalPartOfX =
4266 // (0.554906021e-1f +
4267 // (0.961591928e-2f +
4268 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4269 // error 2.47208000*10^(-7), which is better than 18 bits
4270 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4271 getF32Constant(DAG, 0x3924b03e));
4272 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4273 getF32Constant(DAG, 0x3ab24b87));
4274 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4275 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4276 getF32Constant(DAG, 0x3c1d8c17));
4277 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4278 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4279 getF32Constant(DAG, 0x3d634a1d));
4280 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4281 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4282 getF32Constant(DAG, 0x3e75fe14));
4283 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4284 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4285 getF32Constant(DAG, 0x3f317234));
4286 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4287 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4288 getF32Constant(DAG, 0x3f800000));
4289 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4290 SDValue TwoToFractionalPartOfX =
4291 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4293 result = DAG.getNode(ISD::BITCAST, dl,
4294 MVT::f32, TwoToFractionalPartOfX);
4297 // No special expansion.
4298 result = DAG.getNode(ISD::FPOW, dl,
4299 getValue(I.getArgOperand(0)).getValueType(),
4300 getValue(I.getArgOperand(0)),
4301 getValue(I.getArgOperand(1)));
4304 setValue(&I, result);
4308 /// ExpandPowI - Expand a llvm.powi intrinsic.
4309 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4310 SelectionDAG &DAG) {
4311 // If RHS is a constant, we can expand this out to a multiplication tree,
4312 // otherwise we end up lowering to a call to __powidf2 (for example). When
4313 // optimizing for size, we only want to do this if the expansion would produce
4314 // a small number of multiplies, otherwise we do the full expansion.
4315 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4316 // Get the exponent as a positive value.
4317 unsigned Val = RHSC->getSExtValue();
4318 if ((int)Val < 0) Val = -Val;
4320 // powi(x, 0) -> 1.0
4322 return DAG.getConstantFP(1.0, LHS.getValueType());
4324 const Function *F = DAG.getMachineFunction().getFunction();
4325 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4326 // If optimizing for size, don't insert too many multiplies. This
4327 // inserts up to 5 multiplies.
4328 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4329 // We use the simple binary decomposition method to generate the multiply
4330 // sequence. There are more optimal ways to do this (for example,
4331 // powi(x,15) generates one more multiply than it should), but this has
4332 // the benefit of being both really simple and much better than a libcall.
4333 SDValue Res; // Logically starts equal to 1.0
4334 SDValue CurSquare = LHS;
4338 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4340 Res = CurSquare; // 1.0*CurSquare.
4343 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4344 CurSquare, CurSquare);
4348 // If the original was negative, invert the result, producing 1/(x*x*x).
4349 if (RHSC->getSExtValue() < 0)
4350 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4351 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4356 // Otherwise, expand to a libcall.
4357 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4360 // getTruncatedArgReg - Find underlying register used for an truncated
4362 static unsigned getTruncatedArgReg(const SDValue &N) {
4363 if (N.getOpcode() != ISD::TRUNCATE)
4366 const SDValue &Ext = N.getOperand(0);
4367 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4368 const SDValue &CFR = Ext.getOperand(0);
4369 if (CFR.getOpcode() == ISD::CopyFromReg)
4370 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4372 if (CFR.getOpcode() == ISD::TRUNCATE)
4373 return getTruncatedArgReg(CFR);
4378 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4379 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4380 /// At the end of instruction selection, they will be inserted to the entry BB.
4382 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4385 const Argument *Arg = dyn_cast<Argument>(V);
4389 MachineFunction &MF = DAG.getMachineFunction();
4390 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4391 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4393 // Ignore inlined function arguments here.
4394 DIVariable DV(Variable);
4395 if (DV.isInlinedFnArgument(MF.getFunction()))
4399 if (Arg->hasByValAttr()) {
4400 // Byval arguments' frame index is recorded during argument lowering.
4401 // Use this info directly.
4402 Reg = TRI->getFrameRegister(MF);
4403 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4404 // If byval argument ofset is not recorded then ignore this.
4410 if (N.getOpcode() == ISD::CopyFromReg)
4411 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4413 Reg = getTruncatedArgReg(N);
4414 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4415 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4416 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4423 // Check if ValueMap has reg number.
4424 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4425 if (VMI != FuncInfo.ValueMap.end())
4429 if (!Reg && N.getNode()) {
4430 // Check if frame index is available.
4431 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4432 if (FrameIndexSDNode *FINode =
4433 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4434 Reg = TRI->getFrameRegister(MF);
4435 Offset = FINode->getIndex();
4442 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4443 TII->get(TargetOpcode::DBG_VALUE))
4444 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4445 FuncInfo.ArgDbgValues.push_back(&*MIB);
4449 // VisualStudio defines setjmp as _setjmp
4450 #if defined(_MSC_VER) && defined(setjmp) && \
4451 !defined(setjmp_undefined_for_msvc)
4452 # pragma push_macro("setjmp")
4454 # define setjmp_undefined_for_msvc
4457 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4458 /// we want to emit this as a call to a named external function, return the name
4459 /// otherwise lower it and return null.
4461 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4462 DebugLoc dl = getCurDebugLoc();
4465 switch (Intrinsic) {
4467 // By default, turn this into a target intrinsic node.
4468 visitTargetIntrinsic(I, Intrinsic);
4470 case Intrinsic::vastart: visitVAStart(I); return 0;
4471 case Intrinsic::vaend: visitVAEnd(I); return 0;
4472 case Intrinsic::vacopy: visitVACopy(I); return 0;
4473 case Intrinsic::returnaddress:
4474 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4475 getValue(I.getArgOperand(0))));
4477 case Intrinsic::frameaddress:
4478 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4479 getValue(I.getArgOperand(0))));
4481 case Intrinsic::setjmp:
4482 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4483 case Intrinsic::longjmp:
4484 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4485 case Intrinsic::memcpy: {
4486 // Assert for address < 256 since we support only user defined address
4488 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4490 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4492 "Unknown address space");
4493 SDValue Op1 = getValue(I.getArgOperand(0));
4494 SDValue Op2 = getValue(I.getArgOperand(1));
4495 SDValue Op3 = getValue(I.getArgOperand(2));
4496 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4497 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4498 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4499 MachinePointerInfo(I.getArgOperand(0)),
4500 MachinePointerInfo(I.getArgOperand(1))));
4503 case Intrinsic::memset: {
4504 // Assert for address < 256 since we support only user defined address
4506 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4508 "Unknown address space");
4509 SDValue Op1 = getValue(I.getArgOperand(0));
4510 SDValue Op2 = getValue(I.getArgOperand(1));
4511 SDValue Op3 = getValue(I.getArgOperand(2));
4512 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4513 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4514 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4515 MachinePointerInfo(I.getArgOperand(0))));
4518 case Intrinsic::memmove: {
4519 // Assert for address < 256 since we support only user defined address
4521 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4523 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4525 "Unknown address space");
4526 SDValue Op1 = getValue(I.getArgOperand(0));
4527 SDValue Op2 = getValue(I.getArgOperand(1));
4528 SDValue Op3 = getValue(I.getArgOperand(2));
4529 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4530 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4531 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4532 MachinePointerInfo(I.getArgOperand(0)),
4533 MachinePointerInfo(I.getArgOperand(1))));
4536 case Intrinsic::dbg_declare: {
4537 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4538 MDNode *Variable = DI.getVariable();
4539 const Value *Address = DI.getAddress();
4540 if (!Address || !DIVariable(DI.getVariable()).Verify())
4543 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4544 // but do not always have a corresponding SDNode built. The SDNodeOrder
4545 // absolute, but not relative, values are different depending on whether
4546 // debug info exists.
4549 // Check if address has undef value.
4550 if (isa<UndefValue>(Address) ||
4551 (Address->use_empty() && !isa<Argument>(Address))) {
4552 DEBUG(dbgs() << "Dropping debug info for " << DI);
4556 SDValue &N = NodeMap[Address];
4557 if (!N.getNode() && isa<Argument>(Address))
4558 // Check unused arguments map.
4559 N = UnusedArgNodeMap[Address];
4562 // Parameters are handled specially.
4564 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4565 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4566 Address = BCI->getOperand(0);
4567 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4569 if (isParameter && !AI) {
4570 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4572 // Byval parameter. We have a frame index at this point.
4573 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4574 0, dl, SDNodeOrder);
4576 // Address is an argument, so try to emit its dbg value using
4577 // virtual register info from the FuncInfo.ValueMap.
4578 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4582 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4583 0, dl, SDNodeOrder);
4585 // Can't do anything with other non-AI cases yet.
4586 DEBUG(dbgs() << "Dropping debug info for " << DI);
4589 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4591 // If Address is an argument then try to emit its dbg value using
4592 // virtual register info from the FuncInfo.ValueMap.
4593 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4594 // If variable is pinned by a alloca in dominating bb then
4595 // use StaticAllocaMap.
4596 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4597 if (AI->getParent() != DI.getParent()) {
4598 DenseMap<const AllocaInst*, int>::iterator SI =
4599 FuncInfo.StaticAllocaMap.find(AI);
4600 if (SI != FuncInfo.StaticAllocaMap.end()) {
4601 SDV = DAG.getDbgValue(Variable, SI->second,
4602 0, dl, SDNodeOrder);
4603 DAG.AddDbgValue(SDV, 0, false);
4608 DEBUG(dbgs() << "Dropping debug info for " << DI);
4613 case Intrinsic::dbg_value: {
4614 const DbgValueInst &DI = cast<DbgValueInst>(I);
4615 if (!DIVariable(DI.getVariable()).Verify())
4618 MDNode *Variable = DI.getVariable();
4619 uint64_t Offset = DI.getOffset();
4620 const Value *V = DI.getValue();
4624 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4625 // but do not always have a corresponding SDNode built. The SDNodeOrder
4626 // absolute, but not relative, values are different depending on whether
4627 // debug info exists.
4630 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4631 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4632 DAG.AddDbgValue(SDV, 0, false);
4634 // Do not use getValue() in here; we don't want to generate code at
4635 // this point if it hasn't been done yet.
4636 SDValue N = NodeMap[V];
4637 if (!N.getNode() && isa<Argument>(V))
4638 // Check unused arguments map.
4639 N = UnusedArgNodeMap[V];
4641 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4642 SDV = DAG.getDbgValue(Variable, N.getNode(),
4643 N.getResNo(), Offset, dl, SDNodeOrder);
4644 DAG.AddDbgValue(SDV, N.getNode(), false);
4646 } else if (!V->use_empty() ) {
4647 // Do not call getValue(V) yet, as we don't want to generate code.
4648 // Remember it for later.
4649 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4650 DanglingDebugInfoMap[V] = DDI;
4652 // We may expand this to cover more cases. One case where we have no
4653 // data available is an unreferenced parameter.
4654 DEBUG(dbgs() << "Dropping debug info for " << DI);
4658 // Build a debug info table entry.
4659 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4660 V = BCI->getOperand(0);
4661 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4662 // Don't handle byval struct arguments or VLAs, for example.
4665 DenseMap<const AllocaInst*, int>::iterator SI =
4666 FuncInfo.StaticAllocaMap.find(AI);
4667 if (SI == FuncInfo.StaticAllocaMap.end())
4669 int FI = SI->second;
4671 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4672 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4673 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4676 case Intrinsic::eh_exception: {
4677 // Insert the EXCEPTIONADDR instruction.
4678 assert(FuncInfo.MBB->isLandingPad() &&
4679 "Call to eh.exception not in landing pad!");
4680 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4682 Ops[0] = DAG.getRoot();
4683 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4685 DAG.setRoot(Op.getValue(1));
4689 case Intrinsic::eh_selector: {
4690 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4691 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4692 if (CallMBB->isLandingPad())
4693 AddCatchInfo(I, &MMI, CallMBB);
4696 FuncInfo.CatchInfoLost.insert(&I);
4698 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4699 unsigned Reg = TLI.getExceptionSelectorRegister();
4700 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4703 // Insert the EHSELECTION instruction.
4704 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4706 Ops[0] = getValue(I.getArgOperand(0));
4708 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4709 DAG.setRoot(Op.getValue(1));
4710 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4714 case Intrinsic::eh_typeid_for: {
4715 // Find the type id for the given typeinfo.
4716 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4717 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4718 Res = DAG.getConstant(TypeID, MVT::i32);
4723 case Intrinsic::eh_return_i32:
4724 case Intrinsic::eh_return_i64:
4725 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4726 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4729 getValue(I.getArgOperand(0)),
4730 getValue(I.getArgOperand(1))));
4732 case Intrinsic::eh_unwind_init:
4733 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4735 case Intrinsic::eh_dwarf_cfa: {
4736 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4737 TLI.getPointerTy());
4738 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4740 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4741 TLI.getPointerTy()),
4743 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4745 DAG.getConstant(0, TLI.getPointerTy()));
4746 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4750 case Intrinsic::eh_sjlj_callsite: {
4751 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4752 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4753 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4754 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4756 MMI.setCurrentCallSite(CI->getZExtValue());
4759 case Intrinsic::eh_sjlj_setjmp: {
4760 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4761 getValue(I.getArgOperand(0))));
4764 case Intrinsic::eh_sjlj_longjmp: {
4765 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4766 getRoot(), getValue(I.getArgOperand(0))));
4769 case Intrinsic::eh_sjlj_dispatch_setup: {
4770 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4771 getRoot(), getValue(I.getArgOperand(0))));
4775 case Intrinsic::x86_mmx_pslli_w:
4776 case Intrinsic::x86_mmx_pslli_d:
4777 case Intrinsic::x86_mmx_pslli_q:
4778 case Intrinsic::x86_mmx_psrli_w:
4779 case Intrinsic::x86_mmx_psrli_d:
4780 case Intrinsic::x86_mmx_psrli_q:
4781 case Intrinsic::x86_mmx_psrai_w:
4782 case Intrinsic::x86_mmx_psrai_d: {
4783 SDValue ShAmt = getValue(I.getArgOperand(1));
4784 if (isa<ConstantSDNode>(ShAmt)) {
4785 visitTargetIntrinsic(I, Intrinsic);
4788 unsigned NewIntrinsic = 0;
4789 EVT ShAmtVT = MVT::v2i32;
4790 switch (Intrinsic) {
4791 case Intrinsic::x86_mmx_pslli_w:
4792 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4794 case Intrinsic::x86_mmx_pslli_d:
4795 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4797 case Intrinsic::x86_mmx_pslli_q:
4798 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4800 case Intrinsic::x86_mmx_psrli_w:
4801 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4803 case Intrinsic::x86_mmx_psrli_d:
4804 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4806 case Intrinsic::x86_mmx_psrli_q:
4807 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4809 case Intrinsic::x86_mmx_psrai_w:
4810 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4812 case Intrinsic::x86_mmx_psrai_d:
4813 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4815 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4818 // The vector shift intrinsics with scalars uses 32b shift amounts but
4819 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4821 // We must do this early because v2i32 is not a legal type.
4822 DebugLoc dl = getCurDebugLoc();
4825 ShOps[1] = DAG.getConstant(0, MVT::i32);
4826 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4827 EVT DestVT = TLI.getValueType(I.getType());
4828 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4829 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4830 DAG.getConstant(NewIntrinsic, MVT::i32),
4831 getValue(I.getArgOperand(0)), ShAmt);
4835 case Intrinsic::convertff:
4836 case Intrinsic::convertfsi:
4837 case Intrinsic::convertfui:
4838 case Intrinsic::convertsif:
4839 case Intrinsic::convertuif:
4840 case Intrinsic::convertss:
4841 case Intrinsic::convertsu:
4842 case Intrinsic::convertus:
4843 case Intrinsic::convertuu: {
4844 ISD::CvtCode Code = ISD::CVT_INVALID;
4845 switch (Intrinsic) {
4846 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4847 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4848 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4849 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4850 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4851 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4852 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4853 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4854 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4856 EVT DestVT = TLI.getValueType(I.getType());
4857 const Value *Op1 = I.getArgOperand(0);
4858 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4859 DAG.getValueType(DestVT),
4860 DAG.getValueType(getValue(Op1).getValueType()),
4861 getValue(I.getArgOperand(1)),
4862 getValue(I.getArgOperand(2)),
4867 case Intrinsic::sqrt:
4868 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4869 getValue(I.getArgOperand(0)).getValueType(),
4870 getValue(I.getArgOperand(0))));
4872 case Intrinsic::powi:
4873 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4874 getValue(I.getArgOperand(1)), DAG));
4876 case Intrinsic::sin:
4877 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4878 getValue(I.getArgOperand(0)).getValueType(),
4879 getValue(I.getArgOperand(0))));
4881 case Intrinsic::cos:
4882 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4883 getValue(I.getArgOperand(0)).getValueType(),
4884 getValue(I.getArgOperand(0))));
4886 case Intrinsic::log:
4889 case Intrinsic::log2:
4892 case Intrinsic::log10:
4895 case Intrinsic::exp:
4898 case Intrinsic::exp2:
4901 case Intrinsic::pow:
4904 case Intrinsic::fma:
4905 setValue(&I, DAG.getNode(ISD::FMA, dl,
4906 getValue(I.getArgOperand(0)).getValueType(),
4907 getValue(I.getArgOperand(0)),
4908 getValue(I.getArgOperand(1)),
4909 getValue(I.getArgOperand(2))));
4911 case Intrinsic::convert_to_fp16:
4912 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4913 MVT::i16, getValue(I.getArgOperand(0))));
4915 case Intrinsic::convert_from_fp16:
4916 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4917 MVT::f32, getValue(I.getArgOperand(0))));
4919 case Intrinsic::pcmarker: {
4920 SDValue Tmp = getValue(I.getArgOperand(0));
4921 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4924 case Intrinsic::readcyclecounter: {
4925 SDValue Op = getRoot();
4926 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4927 DAG.getVTList(MVT::i64, MVT::Other),
4930 DAG.setRoot(Res.getValue(1));
4933 case Intrinsic::bswap:
4934 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4935 getValue(I.getArgOperand(0)).getValueType(),
4936 getValue(I.getArgOperand(0))));
4938 case Intrinsic::cttz: {
4939 SDValue Arg = getValue(I.getArgOperand(0));
4940 EVT Ty = Arg.getValueType();
4941 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4944 case Intrinsic::ctlz: {
4945 SDValue Arg = getValue(I.getArgOperand(0));
4946 EVT Ty = Arg.getValueType();
4947 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4950 case Intrinsic::ctpop: {
4951 SDValue Arg = getValue(I.getArgOperand(0));
4952 EVT Ty = Arg.getValueType();
4953 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4956 case Intrinsic::stacksave: {
4957 SDValue Op = getRoot();
4958 Res = DAG.getNode(ISD::STACKSAVE, dl,
4959 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4961 DAG.setRoot(Res.getValue(1));
4964 case Intrinsic::stackrestore: {
4965 Res = getValue(I.getArgOperand(0));
4966 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4969 case Intrinsic::stackprotector: {
4970 // Emit code into the DAG to store the stack guard onto the stack.
4971 MachineFunction &MF = DAG.getMachineFunction();
4972 MachineFrameInfo *MFI = MF.getFrameInfo();
4973 EVT PtrTy = TLI.getPointerTy();
4975 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4976 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4978 int FI = FuncInfo.StaticAllocaMap[Slot];
4979 MFI->setStackProtectorIndex(FI);
4981 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4983 // Store the stack protector onto the stack.
4984 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4985 MachinePointerInfo::getFixedStack(FI),
4991 case Intrinsic::objectsize: {
4992 // If we don't know by now, we're never going to know.
4993 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4995 assert(CI && "Non-constant type in __builtin_object_size?");
4997 SDValue Arg = getValue(I.getCalledValue());
4998 EVT Ty = Arg.getValueType();
5001 Res = DAG.getConstant(-1ULL, Ty);
5003 Res = DAG.getConstant(0, Ty);
5008 case Intrinsic::var_annotation:
5009 // Discard annotate attributes
5012 case Intrinsic::init_trampoline: {
5013 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5017 Ops[1] = getValue(I.getArgOperand(0));
5018 Ops[2] = getValue(I.getArgOperand(1));
5019 Ops[3] = getValue(I.getArgOperand(2));
5020 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5021 Ops[5] = DAG.getSrcValue(F);
5023 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
5024 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
5028 DAG.setRoot(Res.getValue(1));
5031 case Intrinsic::gcroot:
5033 const Value *Alloca = I.getArgOperand(0);
5034 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5036 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5037 GFI->addStackRoot(FI->getIndex(), TypeMap);
5040 case Intrinsic::gcread:
5041 case Intrinsic::gcwrite:
5042 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5044 case Intrinsic::flt_rounds:
5045 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5048 case Intrinsic::expect: {
5049 // Just replace __builtin_expect(exp, c) with EXP.
5050 setValue(&I, getValue(I.getArgOperand(0)));
5054 case Intrinsic::trap: {
5055 StringRef TrapFuncName = getTrapFunctionName();
5056 if (TrapFuncName.empty()) {
5057 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5060 TargetLowering::ArgListTy Args;
5061 std::pair<SDValue, SDValue> Result =
5062 TLI.LowerCallTo(getRoot(), I.getType(),
5063 false, false, false, false, 0, CallingConv::C,
5064 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
5065 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5066 Args, DAG, getCurDebugLoc());
5067 DAG.setRoot(Result.second);
5070 case Intrinsic::uadd_with_overflow:
5071 return implVisitAluOverflow(I, ISD::UADDO);
5072 case Intrinsic::sadd_with_overflow:
5073 return implVisitAluOverflow(I, ISD::SADDO);
5074 case Intrinsic::usub_with_overflow:
5075 return implVisitAluOverflow(I, ISD::USUBO);
5076 case Intrinsic::ssub_with_overflow:
5077 return implVisitAluOverflow(I, ISD::SSUBO);
5078 case Intrinsic::umul_with_overflow:
5079 return implVisitAluOverflow(I, ISD::UMULO);
5080 case Intrinsic::smul_with_overflow:
5081 return implVisitAluOverflow(I, ISD::SMULO);
5083 case Intrinsic::prefetch: {
5085 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5087 Ops[1] = getValue(I.getArgOperand(0));
5088 Ops[2] = getValue(I.getArgOperand(1));
5089 Ops[3] = getValue(I.getArgOperand(2));
5090 Ops[4] = getValue(I.getArgOperand(3));
5091 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5092 DAG.getVTList(MVT::Other),
5094 EVT::getIntegerVT(*Context, 8),
5095 MachinePointerInfo(I.getArgOperand(0)),
5097 false, /* volatile */
5099 rw==1)); /* write */
5102 case Intrinsic::memory_barrier: {
5105 for (int x = 1; x < 6; ++x)
5106 Ops[x] = getValue(I.getArgOperand(x - 1));
5108 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
5111 case Intrinsic::atomic_cmp_swap: {
5112 SDValue Root = getRoot();
5114 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
5115 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
5117 getValue(I.getArgOperand(0)),
5118 getValue(I.getArgOperand(1)),
5119 getValue(I.getArgOperand(2)),
5120 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */,
5121 Monotonic, CrossThread);
5123 DAG.setRoot(L.getValue(1));
5126 case Intrinsic::atomic_load_add:
5127 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
5128 case Intrinsic::atomic_load_sub:
5129 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
5130 case Intrinsic::atomic_load_or:
5131 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
5132 case Intrinsic::atomic_load_xor:
5133 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
5134 case Intrinsic::atomic_load_and:
5135 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
5136 case Intrinsic::atomic_load_nand:
5137 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
5138 case Intrinsic::atomic_load_max:
5139 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
5140 case Intrinsic::atomic_load_min:
5141 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
5142 case Intrinsic::atomic_load_umin:
5143 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
5144 case Intrinsic::atomic_load_umax:
5145 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
5146 case Intrinsic::atomic_swap:
5147 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
5149 case Intrinsic::invariant_start:
5150 case Intrinsic::lifetime_start:
5151 // Discard region information.
5152 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5154 case Intrinsic::invariant_end:
5155 case Intrinsic::lifetime_end:
5156 // Discard region information.
5161 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5163 MachineBasicBlock *LandingPad) {
5164 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5165 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5166 Type *RetTy = FTy->getReturnType();
5167 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5168 MCSymbol *BeginLabel = 0;
5170 TargetLowering::ArgListTy Args;
5171 TargetLowering::ArgListEntry Entry;
5172 Args.reserve(CS.arg_size());
5174 // Check whether the function can return without sret-demotion.
5175 SmallVector<ISD::OutputArg, 4> Outs;
5176 SmallVector<uint64_t, 4> Offsets;
5177 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5178 Outs, TLI, &Offsets);
5180 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5181 DAG.getMachineFunction(),
5182 FTy->isVarArg(), Outs,
5185 SDValue DemoteStackSlot;
5186 int DemoteStackIdx = -100;
5188 if (!CanLowerReturn) {
5189 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5190 FTy->getReturnType());
5191 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5192 FTy->getReturnType());
5193 MachineFunction &MF = DAG.getMachineFunction();
5194 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5195 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5197 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5198 Entry.Node = DemoteStackSlot;
5199 Entry.Ty = StackSlotPtrType;
5200 Entry.isSExt = false;
5201 Entry.isZExt = false;
5202 Entry.isInReg = false;
5203 Entry.isSRet = true;
5204 Entry.isNest = false;
5205 Entry.isByVal = false;
5206 Entry.Alignment = Align;
5207 Args.push_back(Entry);
5208 RetTy = Type::getVoidTy(FTy->getContext());
5211 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5213 const Value *V = *i;
5216 if (V->getType()->isEmptyTy())
5219 SDValue ArgNode = getValue(V);
5220 Entry.Node = ArgNode; Entry.Ty = V->getType();
5222 unsigned attrInd = i - CS.arg_begin() + 1;
5223 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5224 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5225 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5226 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5227 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5228 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5229 Entry.Alignment = CS.getParamAlignment(attrInd);
5230 Args.push_back(Entry);
5234 // Insert a label before the invoke call to mark the try range. This can be
5235 // used to detect deletion of the invoke via the MachineModuleInfo.
5236 BeginLabel = MMI.getContext().CreateTempSymbol();
5238 // For SjLj, keep track of which landing pads go with which invokes
5239 // so as to maintain the ordering of pads in the LSDA.
5240 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5241 if (CallSiteIndex) {
5242 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5243 // Now that the call site is handled, stop tracking it.
5244 MMI.setCurrentCallSite(0);
5247 // Both PendingLoads and PendingExports must be flushed here;
5248 // this call might not return.
5250 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5253 // Check if target-independent constraints permit a tail call here.
5254 // Target-dependent constraints are checked within TLI.LowerCallTo.
5256 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5259 // If there's a possibility that fast-isel has already selected some amount
5260 // of the current basic block, don't emit a tail call.
5261 if (isTailCall && EnableFastISel)
5264 std::pair<SDValue,SDValue> Result =
5265 TLI.LowerCallTo(getRoot(), RetTy,
5266 CS.paramHasAttr(0, Attribute::SExt),
5267 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5268 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5269 CS.getCallingConv(),
5271 !CS.getInstruction()->use_empty(),
5272 Callee, Args, DAG, getCurDebugLoc());
5273 assert((isTailCall || Result.second.getNode()) &&
5274 "Non-null chain expected with non-tail call!");
5275 assert((Result.second.getNode() || !Result.first.getNode()) &&
5276 "Null value expected with tail call!");
5277 if (Result.first.getNode()) {
5278 setValue(CS.getInstruction(), Result.first);
5279 } else if (!CanLowerReturn && Result.second.getNode()) {
5280 // The instruction result is the result of loading from the
5281 // hidden sret parameter.
5282 SmallVector<EVT, 1> PVTs;
5283 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5285 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5286 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5287 EVT PtrVT = PVTs[0];
5288 unsigned NumValues = Outs.size();
5289 SmallVector<SDValue, 4> Values(NumValues);
5290 SmallVector<SDValue, 4> Chains(NumValues);
5292 for (unsigned i = 0; i < NumValues; ++i) {
5293 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5295 DAG.getConstant(Offsets[i], PtrVT));
5296 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5298 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5301 Chains[i] = L.getValue(1);
5304 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5305 MVT::Other, &Chains[0], NumValues);
5306 PendingLoads.push_back(Chain);
5308 // Collect the legal value parts into potentially illegal values
5309 // that correspond to the original function's return values.
5310 SmallVector<EVT, 4> RetTys;
5311 RetTy = FTy->getReturnType();
5312 ComputeValueVTs(TLI, RetTy, RetTys);
5313 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5314 SmallVector<SDValue, 4> ReturnValues;
5315 unsigned CurReg = 0;
5316 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5318 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5319 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5321 SDValue ReturnValue =
5322 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5323 RegisterVT, VT, AssertOp);
5324 ReturnValues.push_back(ReturnValue);
5328 setValue(CS.getInstruction(),
5329 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5330 DAG.getVTList(&RetTys[0], RetTys.size()),
5331 &ReturnValues[0], ReturnValues.size()));
5334 // Assign order to nodes here. If the call does not produce a result, it won't
5335 // be mapped to a SDNode and visit() will not assign it an order number.
5336 if (!Result.second.getNode()) {
5337 // As a special case, a null chain means that a tail call has been emitted and
5338 // the DAG root is already updated.
5341 AssignOrderingToNode(DAG.getRoot().getNode());
5343 DAG.setRoot(Result.second);
5345 AssignOrderingToNode(Result.second.getNode());
5349 // Insert a label at the end of the invoke call to mark the try range. This
5350 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5351 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5352 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5354 // Inform MachineModuleInfo of range.
5355 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5359 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5360 /// value is equal or not-equal to zero.
5361 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5362 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5364 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5365 if (IC->isEquality())
5366 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5367 if (C->isNullValue())
5369 // Unknown instruction.
5375 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5377 SelectionDAGBuilder &Builder) {
5379 // Check to see if this load can be trivially constant folded, e.g. if the
5380 // input is from a string literal.
5381 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5382 // Cast pointer to the type we really want to load.
5383 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5384 PointerType::getUnqual(LoadTy));
5386 if (const Constant *LoadCst =
5387 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5389 return Builder.getValue(LoadCst);
5392 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5393 // still constant memory, the input chain can be the entry node.
5395 bool ConstantMemory = false;
5397 // Do not serialize (non-volatile) loads of constant memory with anything.
5398 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5399 Root = Builder.DAG.getEntryNode();
5400 ConstantMemory = true;
5402 // Do not serialize non-volatile loads against each other.
5403 Root = Builder.DAG.getRoot();
5406 SDValue Ptr = Builder.getValue(PtrVal);
5407 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5408 Ptr, MachinePointerInfo(PtrVal),
5410 false /*nontemporal*/, 1 /* align=1 */);
5412 if (!ConstantMemory)
5413 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5418 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5419 /// If so, return true and lower it, otherwise return false and it will be
5420 /// lowered like a normal call.
5421 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5422 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5423 if (I.getNumArgOperands() != 3)
5426 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5427 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5428 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5429 !I.getType()->isIntegerTy())
5432 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5434 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5435 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5436 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5437 bool ActuallyDoIt = true;
5440 switch (Size->getZExtValue()) {
5442 LoadVT = MVT::Other;
5444 ActuallyDoIt = false;
5448 LoadTy = Type::getInt16Ty(Size->getContext());
5452 LoadTy = Type::getInt32Ty(Size->getContext());
5456 LoadTy = Type::getInt64Ty(Size->getContext());
5460 LoadVT = MVT::v4i32;
5461 LoadTy = Type::getInt32Ty(Size->getContext());
5462 LoadTy = VectorType::get(LoadTy, 4);
5467 // This turns into unaligned loads. We only do this if the target natively
5468 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5469 // we'll only produce a small number of byte loads.
5471 // Require that we can find a legal MVT, and only do this if the target
5472 // supports unaligned loads of that type. Expanding into byte loads would
5474 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5475 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5476 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5477 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5478 ActuallyDoIt = false;
5482 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5483 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5485 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5487 EVT CallVT = TLI.getValueType(I.getType(), true);
5488 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5498 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5499 // Handle inline assembly differently.
5500 if (isa<InlineAsm>(I.getCalledValue())) {
5505 // See if any floating point values are being passed to this function. This is
5506 // used to emit an undefined reference to fltused on Windows.
5508 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5509 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5510 if (FT->isVarArg() &&
5511 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5512 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5513 Type* T = I.getArgOperand(i)->getType();
5514 for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
5516 if (!i->isFloatingPointTy()) continue;
5517 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5523 const char *RenameFn = 0;
5524 if (Function *F = I.getCalledFunction()) {
5525 if (F->isDeclaration()) {
5526 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5527 if (unsigned IID = II->getIntrinsicID(F)) {
5528 RenameFn = visitIntrinsicCall(I, IID);
5533 if (unsigned IID = F->getIntrinsicID()) {
5534 RenameFn = visitIntrinsicCall(I, IID);
5540 // Check for well-known libc/libm calls. If the function is internal, it
5541 // can't be a library call.
5542 if (!F->hasLocalLinkage() && F->hasName()) {
5543 StringRef Name = F->getName();
5544 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5545 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5546 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5547 I.getType() == I.getArgOperand(0)->getType() &&
5548 I.getType() == I.getArgOperand(1)->getType()) {
5549 SDValue LHS = getValue(I.getArgOperand(0));
5550 SDValue RHS = getValue(I.getArgOperand(1));
5551 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5552 LHS.getValueType(), LHS, RHS));
5555 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5556 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5557 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5558 I.getType() == I.getArgOperand(0)->getType()) {
5559 SDValue Tmp = getValue(I.getArgOperand(0));
5560 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5561 Tmp.getValueType(), Tmp));
5564 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5565 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5566 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5567 I.getType() == I.getArgOperand(0)->getType() &&
5568 I.onlyReadsMemory()) {
5569 SDValue Tmp = getValue(I.getArgOperand(0));
5570 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5571 Tmp.getValueType(), Tmp));
5574 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5575 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5576 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5577 I.getType() == I.getArgOperand(0)->getType() &&
5578 I.onlyReadsMemory()) {
5579 SDValue Tmp = getValue(I.getArgOperand(0));
5580 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5581 Tmp.getValueType(), Tmp));
5584 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5585 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5586 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5587 I.getType() == I.getArgOperand(0)->getType() &&
5588 I.onlyReadsMemory()) {
5589 SDValue Tmp = getValue(I.getArgOperand(0));
5590 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5591 Tmp.getValueType(), Tmp));
5594 } else if (Name == "memcmp") {
5595 if (visitMemCmpCall(I))
5603 Callee = getValue(I.getCalledValue());
5605 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5607 // Check if we can potentially perform a tail call. More detailed checking is
5608 // be done within LowerCallTo, after more information about the call is known.
5609 LowerCallTo(&I, Callee, I.isTailCall());
5614 /// AsmOperandInfo - This contains information for each constraint that we are
5616 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5618 /// CallOperand - If this is the result output operand or a clobber
5619 /// this is null, otherwise it is the incoming operand to the CallInst.
5620 /// This gets modified as the asm is processed.
5621 SDValue CallOperand;
5623 /// AssignedRegs - If this is a register or register class operand, this
5624 /// contains the set of register corresponding to the operand.
5625 RegsForValue AssignedRegs;
5627 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5628 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5631 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5632 /// busy in OutputRegs/InputRegs.
5633 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5634 std::set<unsigned> &OutputRegs,
5635 std::set<unsigned> &InputRegs,
5636 const TargetRegisterInfo &TRI) const {
5638 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5639 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5642 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5643 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5647 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5648 /// corresponds to. If there is no Value* for this operand, it returns
5650 EVT getCallOperandValEVT(LLVMContext &Context,
5651 const TargetLowering &TLI,
5652 const TargetData *TD) const {
5653 if (CallOperandVal == 0) return MVT::Other;
5655 if (isa<BasicBlock>(CallOperandVal))
5656 return TLI.getPointerTy();
5658 llvm::Type *OpTy = CallOperandVal->getType();
5660 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5661 // If this is an indirect operand, the operand is a pointer to the
5664 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5666 report_fatal_error("Indirect operand for inline asm not a pointer!");
5667 OpTy = PtrTy->getElementType();
5670 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5671 if (StructType *STy = dyn_cast<StructType>(OpTy))
5672 if (STy->getNumElements() == 1)
5673 OpTy = STy->getElementType(0);
5675 // If OpTy is not a single value, it may be a struct/union that we
5676 // can tile with integers.
5677 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5678 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5687 OpTy = IntegerType::get(Context, BitSize);
5692 return TLI.getValueType(OpTy, true);
5696 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5698 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5699 const TargetRegisterInfo &TRI) {
5700 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5702 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5703 for (; *Aliases; ++Aliases)
5704 Regs.insert(*Aliases);
5708 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5710 } // end anonymous namespace
5712 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5713 /// specified operand. We prefer to assign virtual registers, to allow the
5714 /// register allocator to handle the assignment process. However, if the asm
5715 /// uses features that we can't model on machineinstrs, we have SDISel do the
5716 /// allocation. This produces generally horrible, but correct, code.
5718 /// OpInfo describes the operand.
5719 /// Input and OutputRegs are the set of already allocated physical registers.
5721 static void GetRegistersForValue(SelectionDAG &DAG,
5722 const TargetLowering &TLI,
5724 SDISelAsmOperandInfo &OpInfo,
5725 std::set<unsigned> &OutputRegs,
5726 std::set<unsigned> &InputRegs) {
5727 LLVMContext &Context = *DAG.getContext();
5729 // Compute whether this value requires an input register, an output register,
5731 bool isOutReg = false;
5732 bool isInReg = false;
5733 switch (OpInfo.Type) {
5734 case InlineAsm::isOutput:
5737 // If there is an input constraint that matches this, we need to reserve
5738 // the input register so no other inputs allocate to it.
5739 isInReg = OpInfo.hasMatchingInput();
5741 case InlineAsm::isInput:
5745 case InlineAsm::isClobber:
5752 MachineFunction &MF = DAG.getMachineFunction();
5753 SmallVector<unsigned, 4> Regs;
5755 // If this is a constraint for a single physreg, or a constraint for a
5756 // register class, find it.
5757 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5758 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5759 OpInfo.ConstraintVT);
5761 unsigned NumRegs = 1;
5762 if (OpInfo.ConstraintVT != MVT::Other) {
5763 // If this is a FP input in an integer register (or visa versa) insert a bit
5764 // cast of the input value. More generally, handle any case where the input
5765 // value disagrees with the register class we plan to stick this in.
5766 if (OpInfo.Type == InlineAsm::isInput &&
5767 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5768 // Try to convert to the first EVT that the reg class contains. If the
5769 // types are identical size, use a bitcast to convert (e.g. two differing
5771 EVT RegVT = *PhysReg.second->vt_begin();
5772 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5773 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5774 RegVT, OpInfo.CallOperand);
5775 OpInfo.ConstraintVT = RegVT;
5776 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5777 // If the input is a FP value and we want it in FP registers, do a
5778 // bitcast to the corresponding integer type. This turns an f64 value
5779 // into i64, which can be passed with two i32 values on a 32-bit
5781 RegVT = EVT::getIntegerVT(Context,
5782 OpInfo.ConstraintVT.getSizeInBits());
5783 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5784 RegVT, OpInfo.CallOperand);
5785 OpInfo.ConstraintVT = RegVT;
5789 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5793 EVT ValueVT = OpInfo.ConstraintVT;
5795 // If this is a constraint for a specific physical register, like {r17},
5797 if (unsigned AssignedReg = PhysReg.first) {
5798 const TargetRegisterClass *RC = PhysReg.second;
5799 if (OpInfo.ConstraintVT == MVT::Other)
5800 ValueVT = *RC->vt_begin();
5802 // Get the actual register value type. This is important, because the user
5803 // may have asked for (e.g.) the AX register in i32 type. We need to
5804 // remember that AX is actually i16 to get the right extension.
5805 RegVT = *RC->vt_begin();
5807 // This is a explicit reference to a physical register.
5808 Regs.push_back(AssignedReg);
5810 // If this is an expanded reference, add the rest of the regs to Regs.
5812 TargetRegisterClass::iterator I = RC->begin();
5813 for (; *I != AssignedReg; ++I)
5814 assert(I != RC->end() && "Didn't find reg!");
5816 // Already added the first reg.
5818 for (; NumRegs; --NumRegs, ++I) {
5819 assert(I != RC->end() && "Ran out of registers to allocate!");
5824 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5825 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5826 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5830 // Otherwise, if this was a reference to an LLVM register class, create vregs
5831 // for this reference.
5832 if (const TargetRegisterClass *RC = PhysReg.second) {
5833 RegVT = *RC->vt_begin();
5834 if (OpInfo.ConstraintVT == MVT::Other)
5837 // Create the appropriate number of virtual registers.
5838 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5839 for (; NumRegs; --NumRegs)
5840 Regs.push_back(RegInfo.createVirtualRegister(RC));
5842 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5846 // Otherwise, we couldn't allocate enough registers for this.
5849 /// visitInlineAsm - Handle a call to an InlineAsm object.
5851 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5852 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5854 /// ConstraintOperands - Information about all of the constraints.
5855 SDISelAsmOperandInfoVector ConstraintOperands;
5857 std::set<unsigned> OutputRegs, InputRegs;
5859 TargetLowering::AsmOperandInfoVector
5860 TargetConstraints = TLI.ParseConstraints(CS);
5862 bool hasMemory = false;
5864 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5865 unsigned ResNo = 0; // ResNo - The result number of the next output.
5866 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5867 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5868 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5870 EVT OpVT = MVT::Other;
5872 // Compute the value type for each operand.
5873 switch (OpInfo.Type) {
5874 case InlineAsm::isOutput:
5875 // Indirect outputs just consume an argument.
5876 if (OpInfo.isIndirect) {
5877 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5881 // The return value of the call is this value. As such, there is no
5882 // corresponding argument.
5883 assert(!CS.getType()->isVoidTy() &&
5885 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5886 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5888 assert(ResNo == 0 && "Asm only has one result!");
5889 OpVT = TLI.getValueType(CS.getType());
5893 case InlineAsm::isInput:
5894 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5896 case InlineAsm::isClobber:
5901 // If this is an input or an indirect output, process the call argument.
5902 // BasicBlocks are labels, currently appearing only in asm's.
5903 if (OpInfo.CallOperandVal) {
5904 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5905 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5907 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5910 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5913 OpInfo.ConstraintVT = OpVT;
5915 // Indirect operand accesses access memory.
5916 if (OpInfo.isIndirect)
5919 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5920 TargetLowering::ConstraintType
5921 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5922 if (CType == TargetLowering::C_Memory) {
5930 SDValue Chain, Flag;
5932 // We won't need to flush pending loads if this asm doesn't touch
5933 // memory and is nonvolatile.
5934 if (hasMemory || IA->hasSideEffects())
5937 Chain = DAG.getRoot();
5939 // Second pass over the constraints: compute which constraint option to use
5940 // and assign registers to constraints that want a specific physreg.
5941 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5942 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5944 // If this is an output operand with a matching input operand, look up the
5945 // matching input. If their types mismatch, e.g. one is an integer, the
5946 // other is floating point, or their sizes are different, flag it as an
5948 if (OpInfo.hasMatchingInput()) {
5949 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5951 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5952 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5953 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5954 OpInfo.ConstraintVT);
5955 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5956 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5957 Input.ConstraintVT);
5958 if ((OpInfo.ConstraintVT.isInteger() !=
5959 Input.ConstraintVT.isInteger()) ||
5960 (MatchRC.second != InputRC.second)) {
5961 report_fatal_error("Unsupported asm: input constraint"
5962 " with a matching output constraint of"
5963 " incompatible type!");
5965 Input.ConstraintVT = OpInfo.ConstraintVT;
5969 // Compute the constraint code and ConstraintType to use.
5970 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5972 // If this is a memory input, and if the operand is not indirect, do what we
5973 // need to to provide an address for the memory input.
5974 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5975 !OpInfo.isIndirect) {
5976 assert((OpInfo.isMultipleAlternative ||
5977 (OpInfo.Type == InlineAsm::isInput)) &&
5978 "Can only indirectify direct input operands!");
5980 // Memory operands really want the address of the value. If we don't have
5981 // an indirect input, put it in the constpool if we can, otherwise spill
5982 // it to a stack slot.
5983 // TODO: This isn't quite right. We need to handle these according to
5984 // the addressing mode that the constraint wants. Also, this may take
5985 // an additional register for the computation and we don't want that
5988 // If the operand is a float, integer, or vector constant, spill to a
5989 // constant pool entry to get its address.
5990 const Value *OpVal = OpInfo.CallOperandVal;
5991 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5992 isa<ConstantVector>(OpVal)) {
5993 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5994 TLI.getPointerTy());
5996 // Otherwise, create a stack slot and emit a store to it before the
5998 Type *Ty = OpVal->getType();
5999 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
6000 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
6001 MachineFunction &MF = DAG.getMachineFunction();
6002 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6003 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6004 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6005 OpInfo.CallOperand, StackSlot,
6006 MachinePointerInfo::getFixedStack(SSFI),
6008 OpInfo.CallOperand = StackSlot;
6011 // There is no longer a Value* corresponding to this operand.
6012 OpInfo.CallOperandVal = 0;
6014 // It is now an indirect operand.
6015 OpInfo.isIndirect = true;
6018 // If this constraint is for a specific register, allocate it before
6020 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6021 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
6025 // Second pass - Loop over all of the operands, assigning virtual or physregs
6026 // to register class operands.
6027 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6028 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6030 // C_Register operands have already been allocated, Other/Memory don't need
6032 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6033 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
6037 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6038 std::vector<SDValue> AsmNodeOperands;
6039 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6040 AsmNodeOperands.push_back(
6041 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6042 TLI.getPointerTy()));
6044 // If we have a !srcloc metadata node associated with it, we want to attach
6045 // this to the ultimately generated inline asm machineinstr. To do this, we
6046 // pass in the third operand as this (potentially null) inline asm MDNode.
6047 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6048 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6050 // Remember the HasSideEffect and AlignStack bits as operand 3.
6051 unsigned ExtraInfo = 0;
6052 if (IA->hasSideEffects())
6053 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6054 if (IA->isAlignStack())
6055 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6056 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6057 TLI.getPointerTy()));
6059 // Loop over all of the inputs, copying the operand values into the
6060 // appropriate registers and processing the output regs.
6061 RegsForValue RetValRegs;
6063 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6064 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6066 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6067 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6069 switch (OpInfo.Type) {
6070 case InlineAsm::isOutput: {
6071 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6072 OpInfo.ConstraintType != TargetLowering::C_Register) {
6073 // Memory output, or 'other' output (e.g. 'X' constraint).
6074 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6076 // Add information to the INLINEASM node to know about this output.
6077 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6078 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6079 TLI.getPointerTy()));
6080 AsmNodeOperands.push_back(OpInfo.CallOperand);
6084 // Otherwise, this is a register or register class output.
6086 // Copy the output from the appropriate register. Find a register that
6088 if (OpInfo.AssignedRegs.Regs.empty())
6089 report_fatal_error("Couldn't allocate output reg for constraint '" +
6090 Twine(OpInfo.ConstraintCode) + "'!");
6092 // If this is an indirect operand, store through the pointer after the
6094 if (OpInfo.isIndirect) {
6095 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6096 OpInfo.CallOperandVal));
6098 // This is the result value of the call.
6099 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6100 // Concatenate this output onto the outputs list.
6101 RetValRegs.append(OpInfo.AssignedRegs);
6104 // Add information to the INLINEASM node to know that this register is
6106 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6107 InlineAsm::Kind_RegDefEarlyClobber :
6108 InlineAsm::Kind_RegDef,
6115 case InlineAsm::isInput: {
6116 SDValue InOperandVal = OpInfo.CallOperand;
6118 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6119 // If this is required to match an output register we have already set,
6120 // just use its register.
6121 unsigned OperandNo = OpInfo.getMatchedOperand();
6123 // Scan until we find the definition we already emitted of this operand.
6124 // When we find it, create a RegsForValue operand.
6125 unsigned CurOp = InlineAsm::Op_FirstOperand;
6126 for (; OperandNo; --OperandNo) {
6127 // Advance to the next operand.
6129 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6130 assert((InlineAsm::isRegDefKind(OpFlag) ||
6131 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6132 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6133 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6137 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6138 if (InlineAsm::isRegDefKind(OpFlag) ||
6139 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6140 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6141 if (OpInfo.isIndirect) {
6142 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6143 LLVMContext &Ctx = *DAG.getContext();
6144 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6145 " don't know how to handle tied "
6146 "indirect register inputs");
6149 RegsForValue MatchedRegs;
6150 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6151 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6152 MatchedRegs.RegVTs.push_back(RegVT);
6153 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6154 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6156 MatchedRegs.Regs.push_back
6157 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6159 // Use the produced MatchedRegs object to
6160 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6162 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6163 true, OpInfo.getMatchedOperand(),
6164 DAG, AsmNodeOperands);
6168 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6169 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6170 "Unexpected number of operands");
6171 // Add information to the INLINEASM node to know about this input.
6172 // See InlineAsm.h isUseOperandTiedToDef.
6173 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6174 OpInfo.getMatchedOperand());
6175 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6176 TLI.getPointerTy()));
6177 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6181 // Treat indirect 'X' constraint as memory.
6182 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6184 OpInfo.ConstraintType = TargetLowering::C_Memory;
6186 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6187 std::vector<SDValue> Ops;
6188 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6191 report_fatal_error("Invalid operand for inline asm constraint '" +
6192 Twine(OpInfo.ConstraintCode) + "'!");
6194 // Add information to the INLINEASM node to know about this input.
6195 unsigned ResOpType =
6196 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6197 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6198 TLI.getPointerTy()));
6199 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6203 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6204 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6205 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6206 "Memory operands expect pointer values");
6208 // Add information to the INLINEASM node to know about this input.
6209 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6210 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6211 TLI.getPointerTy()));
6212 AsmNodeOperands.push_back(InOperandVal);
6216 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6217 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6218 "Unknown constraint type!");
6219 assert(!OpInfo.isIndirect &&
6220 "Don't know how to handle indirect register inputs yet!");
6222 // Copy the input into the appropriate registers.
6223 if (OpInfo.AssignedRegs.Regs.empty())
6224 report_fatal_error("Couldn't allocate input reg for constraint '" +
6225 Twine(OpInfo.ConstraintCode) + "'!");
6227 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6230 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6231 DAG, AsmNodeOperands);
6234 case InlineAsm::isClobber: {
6235 // Add the clobbered value to the operand list, so that the register
6236 // allocator is aware that the physreg got clobbered.
6237 if (!OpInfo.AssignedRegs.Regs.empty())
6238 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6246 // Finish up input operands. Set the input chain and add the flag last.
6247 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6248 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6250 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6251 DAG.getVTList(MVT::Other, MVT::Glue),
6252 &AsmNodeOperands[0], AsmNodeOperands.size());
6253 Flag = Chain.getValue(1);
6255 // If this asm returns a register value, copy the result from that register
6256 // and set it as the value of the call.
6257 if (!RetValRegs.Regs.empty()) {
6258 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6261 // FIXME: Why don't we do this for inline asms with MRVs?
6262 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6263 EVT ResultType = TLI.getValueType(CS.getType());
6265 // If any of the results of the inline asm is a vector, it may have the
6266 // wrong width/num elts. This can happen for register classes that can
6267 // contain multiple different value types. The preg or vreg allocated may
6268 // not have the same VT as was expected. Convert it to the right type
6269 // with bit_convert.
6270 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6271 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6274 } else if (ResultType != Val.getValueType() &&
6275 ResultType.isInteger() && Val.getValueType().isInteger()) {
6276 // If a result value was tied to an input value, the computed result may
6277 // have a wider width than the expected result. Extract the relevant
6279 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6282 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6285 setValue(CS.getInstruction(), Val);
6286 // Don't need to use this as a chain in this case.
6287 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6291 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6293 // Process indirect outputs, first output all of the flagged copies out of
6295 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6296 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6297 const Value *Ptr = IndirectStoresToEmit[i].second;
6298 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6300 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6303 // Emit the non-flagged stores from the physregs.
6304 SmallVector<SDValue, 8> OutChains;
6305 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6306 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6307 StoresToEmit[i].first,
6308 getValue(StoresToEmit[i].second),
6309 MachinePointerInfo(StoresToEmit[i].second),
6311 OutChains.push_back(Val);
6314 if (!OutChains.empty())
6315 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6316 &OutChains[0], OutChains.size());
6321 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6322 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6323 MVT::Other, getRoot(),
6324 getValue(I.getArgOperand(0)),
6325 DAG.getSrcValue(I.getArgOperand(0))));
6328 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6329 const TargetData &TD = *TLI.getTargetData();
6330 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6331 getRoot(), getValue(I.getOperand(0)),
6332 DAG.getSrcValue(I.getOperand(0)),
6333 TD.getABITypeAlignment(I.getType()));
6335 DAG.setRoot(V.getValue(1));
6338 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6339 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6340 MVT::Other, getRoot(),
6341 getValue(I.getArgOperand(0)),
6342 DAG.getSrcValue(I.getArgOperand(0))));
6345 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6346 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6347 MVT::Other, getRoot(),
6348 getValue(I.getArgOperand(0)),
6349 getValue(I.getArgOperand(1)),
6350 DAG.getSrcValue(I.getArgOperand(0)),
6351 DAG.getSrcValue(I.getArgOperand(1))));
6354 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6355 /// implementation, which just calls LowerCall.
6356 /// FIXME: When all targets are
6357 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6358 std::pair<SDValue, SDValue>
6359 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6360 bool RetSExt, bool RetZExt, bool isVarArg,
6361 bool isInreg, unsigned NumFixedArgs,
6362 CallingConv::ID CallConv, bool isTailCall,
6363 bool isReturnValueUsed,
6365 ArgListTy &Args, SelectionDAG &DAG,
6366 DebugLoc dl) const {
6367 // Handle all of the outgoing arguments.
6368 SmallVector<ISD::OutputArg, 32> Outs;
6369 SmallVector<SDValue, 32> OutVals;
6370 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6371 SmallVector<EVT, 4> ValueVTs;
6372 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6373 for (unsigned Value = 0, NumValues = ValueVTs.size();
6374 Value != NumValues; ++Value) {
6375 EVT VT = ValueVTs[Value];
6376 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6377 SDValue Op = SDValue(Args[i].Node.getNode(),
6378 Args[i].Node.getResNo() + Value);
6379 ISD::ArgFlagsTy Flags;
6380 unsigned OriginalAlignment =
6381 getTargetData()->getABITypeAlignment(ArgTy);
6387 if (Args[i].isInReg)
6391 if (Args[i].isByVal) {
6393 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6394 Type *ElementTy = Ty->getElementType();
6395 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6396 // For ByVal, alignment should come from FE. BE will guess if this
6397 // info is not there but there are cases it cannot get right.
6398 unsigned FrameAlign;
6399 if (Args[i].Alignment)
6400 FrameAlign = Args[i].Alignment;
6402 FrameAlign = getByValTypeAlignment(ElementTy);
6403 Flags.setByValAlign(FrameAlign);
6407 Flags.setOrigAlign(OriginalAlignment);
6409 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6410 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6411 SmallVector<SDValue, 4> Parts(NumParts);
6412 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6415 ExtendKind = ISD::SIGN_EXTEND;
6416 else if (Args[i].isZExt)
6417 ExtendKind = ISD::ZERO_EXTEND;
6419 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6420 PartVT, ExtendKind);
6422 for (unsigned j = 0; j != NumParts; ++j) {
6423 // if it isn't first piece, alignment must be 1
6424 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6426 if (NumParts > 1 && j == 0)
6427 MyFlags.Flags.setSplit();
6429 MyFlags.Flags.setOrigAlign(1);
6431 Outs.push_back(MyFlags);
6432 OutVals.push_back(Parts[j]);
6437 // Handle the incoming return values from the call.
6438 SmallVector<ISD::InputArg, 32> Ins;
6439 SmallVector<EVT, 4> RetTys;
6440 ComputeValueVTs(*this, RetTy, RetTys);
6441 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6443 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6444 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6445 for (unsigned i = 0; i != NumRegs; ++i) {
6446 ISD::InputArg MyFlags;
6447 MyFlags.VT = RegisterVT.getSimpleVT();
6448 MyFlags.Used = isReturnValueUsed;
6450 MyFlags.Flags.setSExt();
6452 MyFlags.Flags.setZExt();
6454 MyFlags.Flags.setInReg();
6455 Ins.push_back(MyFlags);
6459 SmallVector<SDValue, 4> InVals;
6460 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6461 Outs, OutVals, Ins, dl, DAG, InVals);
6463 // Verify that the target's LowerCall behaved as expected.
6464 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6465 "LowerCall didn't return a valid chain!");
6466 assert((!isTailCall || InVals.empty()) &&
6467 "LowerCall emitted a return value for a tail call!");
6468 assert((isTailCall || InVals.size() == Ins.size()) &&
6469 "LowerCall didn't emit the correct number of values!");
6471 // For a tail call, the return value is merely live-out and there aren't
6472 // any nodes in the DAG representing it. Return a special value to
6473 // indicate that a tail call has been emitted and no more Instructions
6474 // should be processed in the current block.
6477 return std::make_pair(SDValue(), SDValue());
6480 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6481 assert(InVals[i].getNode() &&
6482 "LowerCall emitted a null value!");
6483 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6484 "LowerCall emitted a value with the wrong type!");
6487 // Collect the legal value parts into potentially illegal values
6488 // that correspond to the original function's return values.
6489 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6491 AssertOp = ISD::AssertSext;
6493 AssertOp = ISD::AssertZext;
6494 SmallVector<SDValue, 4> ReturnValues;
6495 unsigned CurReg = 0;
6496 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6498 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6499 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6501 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6502 NumRegs, RegisterVT, VT,
6507 // For a function returning void, there is no return value. We can't create
6508 // such a node, so we just return a null return value in that case. In
6509 // that case, nothing will actually look at the value.
6510 if (ReturnValues.empty())
6511 return std::make_pair(SDValue(), Chain);
6513 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6514 DAG.getVTList(&RetTys[0], RetTys.size()),
6515 &ReturnValues[0], ReturnValues.size());
6516 return std::make_pair(Res, Chain);
6519 void TargetLowering::LowerOperationWrapper(SDNode *N,
6520 SmallVectorImpl<SDValue> &Results,
6521 SelectionDAG &DAG) const {
6522 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6524 Results.push_back(Res);
6527 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6528 llvm_unreachable("LowerOperation not implemented for this target!");
6533 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6534 SDValue Op = getNonRegisterValue(V);
6535 assert((Op.getOpcode() != ISD::CopyFromReg ||
6536 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6537 "Copy from a reg to the same reg!");
6538 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6540 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6541 SDValue Chain = DAG.getEntryNode();
6542 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6543 PendingExports.push_back(Chain);
6546 #include "llvm/CodeGen/SelectionDAGISel.h"
6548 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6549 /// entry block, return true. This includes arguments used by switches, since
6550 /// the switch may expand into multiple basic blocks.
6551 static bool isOnlyUsedInEntryBlock(const Argument *A) {
6552 // With FastISel active, we may be splitting blocks, so force creation
6553 // of virtual registers for all non-dead arguments.
6555 return A->use_empty();
6557 const BasicBlock *Entry = A->getParent()->begin();
6558 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6560 const User *U = *UI;
6561 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6562 return false; // Use not in entry block.
6567 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6568 // If this is the entry block, emit arguments.
6569 const Function &F = *LLVMBB->getParent();
6570 SelectionDAG &DAG = SDB->DAG;
6571 DebugLoc dl = SDB->getCurDebugLoc();
6572 const TargetData *TD = TLI.getTargetData();
6573 SmallVector<ISD::InputArg, 16> Ins;
6575 // Check whether the function can return without sret-demotion.
6576 SmallVector<ISD::OutputArg, 4> Outs;
6577 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6580 if (!FuncInfo->CanLowerReturn) {
6581 // Put in an sret pointer parameter before all the other parameters.
6582 SmallVector<EVT, 1> ValueVTs;
6583 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6585 // NOTE: Assuming that a pointer will never break down to more than one VT
6587 ISD::ArgFlagsTy Flags;
6589 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6590 ISD::InputArg RetArg(Flags, RegisterVT, true);
6591 Ins.push_back(RetArg);
6594 // Set up the incoming argument description vector.
6596 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6597 I != E; ++I, ++Idx) {
6598 SmallVector<EVT, 4> ValueVTs;
6599 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6600 bool isArgValueUsed = !I->use_empty();
6601 for (unsigned Value = 0, NumValues = ValueVTs.size();
6602 Value != NumValues; ++Value) {
6603 EVT VT = ValueVTs[Value];
6604 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6605 ISD::ArgFlagsTy Flags;
6606 unsigned OriginalAlignment =
6607 TD->getABITypeAlignment(ArgTy);
6609 if (F.paramHasAttr(Idx, Attribute::ZExt))
6611 if (F.paramHasAttr(Idx, Attribute::SExt))
6613 if (F.paramHasAttr(Idx, Attribute::InReg))
6615 if (F.paramHasAttr(Idx, Attribute::StructRet))
6617 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6619 PointerType *Ty = cast<PointerType>(I->getType());
6620 Type *ElementTy = Ty->getElementType();
6621 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6622 // For ByVal, alignment should be passed from FE. BE will guess if
6623 // this info is not there but there are cases it cannot get right.
6624 unsigned FrameAlign;
6625 if (F.getParamAlignment(Idx))
6626 FrameAlign = F.getParamAlignment(Idx);
6628 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6629 Flags.setByValAlign(FrameAlign);
6631 if (F.paramHasAttr(Idx, Attribute::Nest))
6633 Flags.setOrigAlign(OriginalAlignment);
6635 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6636 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6637 for (unsigned i = 0; i != NumRegs; ++i) {
6638 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6639 if (NumRegs > 1 && i == 0)
6640 MyFlags.Flags.setSplit();
6641 // if it isn't first piece, alignment must be 1
6643 MyFlags.Flags.setOrigAlign(1);
6644 Ins.push_back(MyFlags);
6649 // Call the target to set up the argument values.
6650 SmallVector<SDValue, 8> InVals;
6651 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6655 // Verify that the target's LowerFormalArguments behaved as expected.
6656 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6657 "LowerFormalArguments didn't return a valid chain!");
6658 assert(InVals.size() == Ins.size() &&
6659 "LowerFormalArguments didn't emit the correct number of values!");
6661 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6662 assert(InVals[i].getNode() &&
6663 "LowerFormalArguments emitted a null value!");
6664 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6665 "LowerFormalArguments emitted a value with the wrong type!");
6669 // Update the DAG with the new chain value resulting from argument lowering.
6670 DAG.setRoot(NewRoot);
6672 // Set up the argument values.
6675 if (!FuncInfo->CanLowerReturn) {
6676 // Create a virtual register for the sret pointer, and put in a copy
6677 // from the sret argument into it.
6678 SmallVector<EVT, 1> ValueVTs;
6679 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6680 EVT VT = ValueVTs[0];
6681 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6682 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6683 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6684 RegVT, VT, AssertOp);
6686 MachineFunction& MF = SDB->DAG.getMachineFunction();
6687 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6688 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6689 FuncInfo->DemoteRegister = SRetReg;
6690 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6692 DAG.setRoot(NewRoot);
6694 // i indexes lowered arguments. Bump it past the hidden sret argument.
6695 // Idx indexes LLVM arguments. Don't touch it.
6699 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6701 SmallVector<SDValue, 4> ArgValues;
6702 SmallVector<EVT, 4> ValueVTs;
6703 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6704 unsigned NumValues = ValueVTs.size();
6706 // If this argument is unused then remember its value. It is used to generate
6707 // debugging information.
6708 if (I->use_empty() && NumValues)
6709 SDB->setUnusedArgValue(I, InVals[i]);
6711 for (unsigned Val = 0; Val != NumValues; ++Val) {
6712 EVT VT = ValueVTs[Val];
6713 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6714 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6716 if (!I->use_empty()) {
6717 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6718 if (F.paramHasAttr(Idx, Attribute::SExt))
6719 AssertOp = ISD::AssertSext;
6720 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6721 AssertOp = ISD::AssertZext;
6723 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6724 NumParts, PartVT, VT,
6731 // We don't need to do anything else for unused arguments.
6732 if (ArgValues.empty())
6735 // Note down frame index for byval arguments.
6736 if (I->hasByValAttr())
6737 if (FrameIndexSDNode *FI =
6738 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6739 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6741 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6742 SDB->getCurDebugLoc());
6743 SDB->setValue(I, Res);
6745 // If this argument is live outside of the entry block, insert a copy from
6746 // wherever we got it to the vreg that other BB's will reference it as.
6747 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6748 // If we can, though, try to skip creating an unnecessary vreg.
6749 // FIXME: This isn't very clean... it would be nice to make this more
6750 // general. It's also subtly incompatible with the hacks FastISel
6752 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6753 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6754 FuncInfo->ValueMap[I] = Reg;
6758 if (!isOnlyUsedInEntryBlock(I)) {
6759 FuncInfo->InitializeRegForValue(I);
6760 SDB->CopyToExportRegsIfNeeded(I);
6764 assert(i == InVals.size() && "Argument register count mismatch!");
6766 // Finally, if the target has anything special to do, allow it to do so.
6767 // FIXME: this should insert code into the DAG!
6768 EmitFunctionEntryCode();
6771 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6772 /// ensure constants are generated when needed. Remember the virtual registers
6773 /// that need to be added to the Machine PHI nodes as input. We cannot just
6774 /// directly add them, because expansion might result in multiple MBB's for one
6775 /// BB. As such, the start of the BB might correspond to a different MBB than
6779 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6780 const TerminatorInst *TI = LLVMBB->getTerminator();
6782 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6784 // Check successor nodes' PHI nodes that expect a constant to be available
6786 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6787 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6788 if (!isa<PHINode>(SuccBB->begin())) continue;
6789 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6791 // If this terminator has multiple identical successors (common for
6792 // switches), only handle each succ once.
6793 if (!SuccsHandled.insert(SuccMBB)) continue;
6795 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6797 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6798 // nodes and Machine PHI nodes, but the incoming operands have not been
6800 for (BasicBlock::const_iterator I = SuccBB->begin();
6801 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6802 // Ignore dead phi's.
6803 if (PN->use_empty()) continue;
6806 if (PN->getType()->isEmptyTy())
6810 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6812 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6813 unsigned &RegOut = ConstantsOut[C];
6815 RegOut = FuncInfo.CreateRegs(C->getType());
6816 CopyValueToVirtualRegister(C, RegOut);
6820 DenseMap<const Value *, unsigned>::iterator I =
6821 FuncInfo.ValueMap.find(PHIOp);
6822 if (I != FuncInfo.ValueMap.end())
6825 assert(isa<AllocaInst>(PHIOp) &&
6826 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6827 "Didn't codegen value into a register!??");
6828 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6829 CopyValueToVirtualRegister(PHIOp, Reg);
6833 // Remember that this register needs to added to the machine PHI node as
6834 // the input for this MBB.
6835 SmallVector<EVT, 4> ValueVTs;
6836 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6837 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6838 EVT VT = ValueVTs[vti];
6839 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6840 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6841 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6842 Reg += NumRegisters;
6846 ConstantsOut.clear();