1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 llvm_unreachable("should never codegen catchpads");
1166 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1167 // Update machine-CFG edge.
1168 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1169 FuncInfo.MBB->addSuccessor(TargetMBB);
1171 // Figure out the funclet membership for the catchret's successor.
1172 // This will be used by the FuncletLayout pass to determine how to order the
1174 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1175 WinEHFuncInfo &EHInfo =
1176 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1177 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1178 assert(SuccessorColor && "No parent funclet for catchret!");
1179 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1180 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1182 // Create the terminator node.
1183 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1184 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1185 DAG.getBasicBlock(SuccessorColorMBB));
1189 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1190 llvm_unreachable("should never codegen catchendpads");
1193 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1194 // Don't emit any special code for the cleanuppad instruction. It just marks
1195 // the start of a funclet.
1196 FuncInfo.MBB->setIsEHFuncletEntry();
1197 FuncInfo.MBB->setIsCleanupFuncletEntry();
1200 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1201 /// many places it could ultimately go. In the IR, we have a single unwind
1202 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1203 /// This function skips over imaginary basic blocks that hold catchpad,
1204 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1205 /// basic block destinations.
1207 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1208 const BasicBlock *EHPadBB,
1209 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1210 EHPersonality Personality =
1211 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1212 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1213 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1215 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1216 if (isa<LandingPadInst>(Pad)) {
1217 // Stop on landingpads. They are not funclets.
1218 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1220 } else if (isa<CleanupPadInst>(Pad)) {
1221 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1223 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1224 UnwindDests.back()->setIsEHFuncletEntry();
1226 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1227 // Add the catchpad handler to the possible destinations.
1228 UnwindDests.push_back(FuncInfo.MBBMap[CPI->getNormalDest()]);
1229 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1230 if (IsMSVCCXX || IsCoreCLR)
1231 UnwindDests.back()->setIsEHFuncletEntry();
1232 EHPadBB = CPI->getUnwindDest();
1233 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1234 EHPadBB = CEPI->getUnwindDest();
1235 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1236 EHPadBB = CEPI->getUnwindDest();
1241 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1242 // Update successor info.
1243 // FIXME: The weights for catchpads will be wrong.
1244 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1245 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1246 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1247 UnwindDest->setIsEHPad();
1248 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1251 // Create the terminator node.
1253 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1257 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1258 report_fatal_error("visitCleanupEndPad not yet implemented!");
1261 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1262 report_fatal_error("visitTerminatePad not yet implemented!");
1265 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1267 auto &DL = DAG.getDataLayout();
1268 SDValue Chain = getControlRoot();
1269 SmallVector<ISD::OutputArg, 8> Outs;
1270 SmallVector<SDValue, 8> OutVals;
1272 if (!FuncInfo.CanLowerReturn) {
1273 unsigned DemoteReg = FuncInfo.DemoteRegister;
1274 const Function *F = I.getParent()->getParent();
1276 // Emit a store of the return value through the virtual register.
1277 // Leave Outs empty so that LowerReturn won't try to load return
1278 // registers the usual way.
1279 SmallVector<EVT, 1> PtrValueVTs;
1280 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1283 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1284 SDValue RetOp = getValue(I.getOperand(0));
1286 SmallVector<EVT, 4> ValueVTs;
1287 SmallVector<uint64_t, 4> Offsets;
1288 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1289 unsigned NumValues = ValueVTs.size();
1291 SmallVector<SDValue, 4> Chains(NumValues);
1292 for (unsigned i = 0; i != NumValues; ++i) {
1293 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1294 RetPtr.getValueType(), RetPtr,
1295 DAG.getIntPtrConstant(Offsets[i],
1298 DAG.getStore(Chain, getCurSDLoc(),
1299 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1300 // FIXME: better loc info would be nice.
1301 Add, MachinePointerInfo(), false, false, 0);
1304 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1305 MVT::Other, Chains);
1306 } else if (I.getNumOperands() != 0) {
1307 SmallVector<EVT, 4> ValueVTs;
1308 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1309 unsigned NumValues = ValueVTs.size();
1311 SDValue RetOp = getValue(I.getOperand(0));
1313 const Function *F = I.getParent()->getParent();
1315 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1316 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1318 ExtendKind = ISD::SIGN_EXTEND;
1319 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1321 ExtendKind = ISD::ZERO_EXTEND;
1323 LLVMContext &Context = F->getContext();
1324 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1327 for (unsigned j = 0; j != NumValues; ++j) {
1328 EVT VT = ValueVTs[j];
1330 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1331 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1333 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1334 MVT PartVT = TLI.getRegisterType(Context, VT);
1335 SmallVector<SDValue, 4> Parts(NumParts);
1336 getCopyToParts(DAG, getCurSDLoc(),
1337 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1338 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1340 // 'inreg' on function refers to return value
1341 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1345 // Propagate extension type if any
1346 if (ExtendKind == ISD::SIGN_EXTEND)
1348 else if (ExtendKind == ISD::ZERO_EXTEND)
1351 for (unsigned i = 0; i < NumParts; ++i) {
1352 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1353 VT, /*isfixed=*/true, 0, 0));
1354 OutVals.push_back(Parts[i]);
1360 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1361 CallingConv::ID CallConv =
1362 DAG.getMachineFunction().getFunction()->getCallingConv();
1363 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1364 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1366 // Verify that the target's LowerReturn behaved as expected.
1367 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1368 "LowerReturn didn't return a valid chain!");
1370 // Update the DAG with the new chain value resulting from return lowering.
1374 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1375 /// created for it, emit nodes to copy the value into the virtual
1377 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1379 if (V->getType()->isEmptyTy())
1382 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1383 if (VMI != FuncInfo.ValueMap.end()) {
1384 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1385 CopyValueToVirtualRegister(V, VMI->second);
1389 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1390 /// the current basic block, add it to ValueMap now so that we'll get a
1392 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1393 // No need to export constants.
1394 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1396 // Already exported?
1397 if (FuncInfo.isExportedInst(V)) return;
1399 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1400 CopyValueToVirtualRegister(V, Reg);
1403 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1404 const BasicBlock *FromBB) {
1405 // The operands of the setcc have to be in this block. We don't know
1406 // how to export them from some other block.
1407 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1408 // Can export from current BB.
1409 if (VI->getParent() == FromBB)
1412 // Is already exported, noop.
1413 return FuncInfo.isExportedInst(V);
1416 // If this is an argument, we can export it if the BB is the entry block or
1417 // if it is already exported.
1418 if (isa<Argument>(V)) {
1419 if (FromBB == &FromBB->getParent()->getEntryBlock())
1422 // Otherwise, can only export this if it is already exported.
1423 return FuncInfo.isExportedInst(V);
1426 // Otherwise, constants can always be exported.
1430 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1431 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1432 const MachineBasicBlock *Dst) const {
1433 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1436 const BasicBlock *SrcBB = Src->getBasicBlock();
1437 const BasicBlock *DstBB = Dst->getBasicBlock();
1438 return BPI->getEdgeWeight(SrcBB, DstBB);
1441 void SelectionDAGBuilder::
1442 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1443 uint32_t Weight /* = 0 */) {
1445 Weight = getEdgeWeight(Src, Dst);
1446 Src->addSuccessor(Dst, Weight);
1450 static bool InBlock(const Value *V, const BasicBlock *BB) {
1451 if (const Instruction *I = dyn_cast<Instruction>(V))
1452 return I->getParent() == BB;
1456 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1457 /// This function emits a branch and is used at the leaves of an OR or an
1458 /// AND operator tree.
1461 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1462 MachineBasicBlock *TBB,
1463 MachineBasicBlock *FBB,
1464 MachineBasicBlock *CurBB,
1465 MachineBasicBlock *SwitchBB,
1468 const BasicBlock *BB = CurBB->getBasicBlock();
1470 // If the leaf of the tree is a comparison, merge the condition into
1472 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1473 // The operands of the cmp have to be in this block. We don't know
1474 // how to export them from some other block. If this is the first block
1475 // of the sequence, no exporting is needed.
1476 if (CurBB == SwitchBB ||
1477 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1478 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1479 ISD::CondCode Condition;
1480 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1481 Condition = getICmpCondCode(IC->getPredicate());
1483 const FCmpInst *FC = cast<FCmpInst>(Cond);
1484 Condition = getFCmpCondCode(FC->getPredicate());
1485 if (TM.Options.NoNaNsFPMath)
1486 Condition = getFCmpCodeWithoutNaN(Condition);
1489 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1490 TBB, FBB, CurBB, TWeight, FWeight);
1491 SwitchCases.push_back(CB);
1496 // Create a CaseBlock record representing this branch.
1497 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1498 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1499 SwitchCases.push_back(CB);
1502 /// Scale down both weights to fit into uint32_t.
1503 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1504 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1505 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1506 NewTrue = NewTrue / Scale;
1507 NewFalse = NewFalse / Scale;
1510 /// FindMergedConditions - If Cond is an expression like
1511 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1512 MachineBasicBlock *TBB,
1513 MachineBasicBlock *FBB,
1514 MachineBasicBlock *CurBB,
1515 MachineBasicBlock *SwitchBB,
1516 Instruction::BinaryOps Opc,
1519 // If this node is not part of the or/and tree, emit it as a branch.
1520 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1521 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1522 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1523 BOp->getParent() != CurBB->getBasicBlock() ||
1524 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1525 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1526 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1531 // Create TmpBB after CurBB.
1532 MachineFunction::iterator BBI = CurBB;
1533 MachineFunction &MF = DAG.getMachineFunction();
1534 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1535 CurBB->getParent()->insert(++BBI, TmpBB);
1537 if (Opc == Instruction::Or) {
1538 // Codegen X | Y as:
1547 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1548 // The requirement is that
1549 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1550 // = TrueProb for original BB.
1551 // Assuming the original weights are A and B, one choice is to set BB1's
1552 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1554 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1555 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1556 // TmpBB, but the math is more complicated.
1558 uint64_t NewTrueWeight = TWeight;
1559 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1560 ScaleWeights(NewTrueWeight, NewFalseWeight);
1561 // Emit the LHS condition.
1562 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1563 NewTrueWeight, NewFalseWeight);
1565 NewTrueWeight = TWeight;
1566 NewFalseWeight = 2 * (uint64_t)FWeight;
1567 ScaleWeights(NewTrueWeight, NewFalseWeight);
1568 // Emit the RHS condition into TmpBB.
1569 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1570 NewTrueWeight, NewFalseWeight);
1572 assert(Opc == Instruction::And && "Unknown merge op!");
1573 // Codegen X & Y as:
1581 // This requires creation of TmpBB after CurBB.
1583 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1584 // The requirement is that
1585 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1586 // = FalseProb for original BB.
1587 // Assuming the original weights are A and B, one choice is to set BB1's
1588 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1590 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1592 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1593 uint64_t NewFalseWeight = FWeight;
1594 ScaleWeights(NewTrueWeight, NewFalseWeight);
1595 // Emit the LHS condition.
1596 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1597 NewTrueWeight, NewFalseWeight);
1599 NewTrueWeight = 2 * (uint64_t)TWeight;
1600 NewFalseWeight = FWeight;
1601 ScaleWeights(NewTrueWeight, NewFalseWeight);
1602 // Emit the RHS condition into TmpBB.
1603 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1604 NewTrueWeight, NewFalseWeight);
1608 /// If the set of cases should be emitted as a series of branches, return true.
1609 /// If we should emit this as a bunch of and/or'd together conditions, return
1612 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1613 if (Cases.size() != 2) return true;
1615 // If this is two comparisons of the same values or'd or and'd together, they
1616 // will get folded into a single comparison, so don't emit two blocks.
1617 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1618 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1619 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1620 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1624 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1625 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1626 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1627 Cases[0].CC == Cases[1].CC &&
1628 isa<Constant>(Cases[0].CmpRHS) &&
1629 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1630 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1632 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1639 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1640 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1642 // Update machine-CFG edges.
1643 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1645 if (I.isUnconditional()) {
1646 // Update machine-CFG edges.
1647 BrMBB->addSuccessor(Succ0MBB);
1649 // If this is not a fall-through branch or optimizations are switched off,
1651 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1652 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1653 MVT::Other, getControlRoot(),
1654 DAG.getBasicBlock(Succ0MBB)));
1659 // If this condition is one of the special cases we handle, do special stuff
1661 const Value *CondVal = I.getCondition();
1662 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1664 // If this is a series of conditions that are or'd or and'd together, emit
1665 // this as a sequence of branches instead of setcc's with and/or operations.
1666 // As long as jumps are not expensive, this should improve performance.
1667 // For example, instead of something like:
1680 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1681 Instruction::BinaryOps Opcode = BOp->getOpcode();
1682 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1683 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1684 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1685 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1686 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1687 getEdgeWeight(BrMBB, Succ1MBB));
1688 // If the compares in later blocks need to use values not currently
1689 // exported from this block, export them now. This block should always
1690 // be the first entry.
1691 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1693 // Allow some cases to be rejected.
1694 if (ShouldEmitAsBranches(SwitchCases)) {
1695 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1696 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1697 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1700 // Emit the branch for this block.
1701 visitSwitchCase(SwitchCases[0], BrMBB);
1702 SwitchCases.erase(SwitchCases.begin());
1706 // Okay, we decided not to do this, remove any inserted MBB's and clear
1708 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1709 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1711 SwitchCases.clear();
1715 // Create a CaseBlock record representing this branch.
1716 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1717 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1719 // Use visitSwitchCase to actually insert the fast branch sequence for this
1721 visitSwitchCase(CB, BrMBB);
1724 /// visitSwitchCase - Emits the necessary code to represent a single node in
1725 /// the binary search tree resulting from lowering a switch instruction.
1726 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1727 MachineBasicBlock *SwitchBB) {
1729 SDValue CondLHS = getValue(CB.CmpLHS);
1730 SDLoc dl = getCurSDLoc();
1732 // Build the setcc now.
1734 // Fold "(X == true)" to X and "(X == false)" to !X to
1735 // handle common cases produced by branch lowering.
1736 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1737 CB.CC == ISD::SETEQ)
1739 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1740 CB.CC == ISD::SETEQ) {
1741 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1742 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1744 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1746 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1748 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1749 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1751 SDValue CmpOp = getValue(CB.CmpMHS);
1752 EVT VT = CmpOp.getValueType();
1754 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1755 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1758 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1759 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1760 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1761 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1765 // Update successor info
1766 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1767 // TrueBB and FalseBB are always different unless the incoming IR is
1768 // degenerate. This only happens when running llc on weird IR.
1769 if (CB.TrueBB != CB.FalseBB)
1770 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1772 // If the lhs block is the next block, invert the condition so that we can
1773 // fall through to the lhs instead of the rhs block.
1774 if (CB.TrueBB == NextBlock(SwitchBB)) {
1775 std::swap(CB.TrueBB, CB.FalseBB);
1776 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1777 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1780 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1781 MVT::Other, getControlRoot(), Cond,
1782 DAG.getBasicBlock(CB.TrueBB));
1784 // Insert the false branch. Do this even if it's a fall through branch,
1785 // this makes it easier to do DAG optimizations which require inverting
1786 // the branch condition.
1787 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1788 DAG.getBasicBlock(CB.FalseBB));
1790 DAG.setRoot(BrCond);
1793 /// visitJumpTable - Emit JumpTable node in the current MBB
1794 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1795 // Emit the code for the jump table
1796 assert(JT.Reg != -1U && "Should lower JT Header first!");
1797 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1798 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1800 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1801 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1802 MVT::Other, Index.getValue(1),
1804 DAG.setRoot(BrJumpTable);
1807 /// visitJumpTableHeader - This function emits necessary code to produce index
1808 /// in the JumpTable from switch case.
1809 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1810 JumpTableHeader &JTH,
1811 MachineBasicBlock *SwitchBB) {
1812 SDLoc dl = getCurSDLoc();
1814 // Subtract the lowest switch case value from the value being switched on and
1815 // conditional branch to default mbb if the result is greater than the
1816 // difference between smallest and largest cases.
1817 SDValue SwitchOp = getValue(JTH.SValue);
1818 EVT VT = SwitchOp.getValueType();
1819 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1820 DAG.getConstant(JTH.First, dl, VT));
1822 // The SDNode we just created, which holds the value being switched on minus
1823 // the smallest case value, needs to be copied to a virtual register so it
1824 // can be used as an index into the jump table in a subsequent basic block.
1825 // This value may be smaller or larger than the target's pointer type, and
1826 // therefore require extension or truncating.
1827 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1828 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1830 unsigned JumpTableReg =
1831 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1832 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1833 JumpTableReg, SwitchOp);
1834 JT.Reg = JumpTableReg;
1836 // Emit the range check for the jump table, and branch to the default block
1837 // for the switch statement if the value being switched on exceeds the largest
1838 // case in the switch.
1839 SDValue CMP = DAG.getSetCC(
1840 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1841 Sub.getValueType()),
1842 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1844 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1845 MVT::Other, CopyTo, CMP,
1846 DAG.getBasicBlock(JT.Default));
1848 // Avoid emitting unnecessary branches to the next block.
1849 if (JT.MBB != NextBlock(SwitchBB))
1850 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1851 DAG.getBasicBlock(JT.MBB));
1853 DAG.setRoot(BrCond);
1856 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1857 /// tail spliced into a stack protector check success bb.
1859 /// For a high level explanation of how this fits into the stack protector
1860 /// generation see the comment on the declaration of class
1861 /// StackProtectorDescriptor.
1862 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1863 MachineBasicBlock *ParentBB) {
1865 // First create the loads to the guard/stack slot for the comparison.
1866 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1867 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1869 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1870 int FI = MFI->getStackProtectorIndex();
1872 const Value *IRGuard = SPD.getGuard();
1873 SDValue GuardPtr = getValue(IRGuard);
1874 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1876 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1879 SDLoc dl = getCurSDLoc();
1881 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1882 // guard value from the virtual register holding the value. Otherwise, emit a
1883 // volatile load to retrieve the stack guard value.
1884 unsigned GuardReg = SPD.getGuardReg();
1886 if (GuardReg && TLI.useLoadStackGuardNode())
1887 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1890 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1891 GuardPtr, MachinePointerInfo(IRGuard, 0),
1892 true, false, false, Align);
1894 SDValue StackSlot = DAG.getLoad(
1895 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1896 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1897 false, false, Align);
1899 // Perform the comparison via a subtract/getsetcc.
1900 EVT VT = Guard.getValueType();
1901 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1903 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1905 Sub.getValueType()),
1906 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1908 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1909 // branch to failure MBB.
1910 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1911 MVT::Other, StackSlot.getOperand(0),
1912 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1913 // Otherwise branch to success MBB.
1914 SDValue Br = DAG.getNode(ISD::BR, dl,
1916 DAG.getBasicBlock(SPD.getSuccessMBB()));
1921 /// Codegen the failure basic block for a stack protector check.
1923 /// A failure stack protector machine basic block consists simply of a call to
1924 /// __stack_chk_fail().
1926 /// For a high level explanation of how this fits into the stack protector
1927 /// generation see the comment on the declaration of class
1928 /// StackProtectorDescriptor.
1930 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1931 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1933 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1934 nullptr, 0, false, getCurSDLoc(), false, false).second;
1938 /// visitBitTestHeader - This function emits necessary code to produce value
1939 /// suitable for "bit tests"
1940 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1941 MachineBasicBlock *SwitchBB) {
1942 SDLoc dl = getCurSDLoc();
1944 // Subtract the minimum value
1945 SDValue SwitchOp = getValue(B.SValue);
1946 EVT VT = SwitchOp.getValueType();
1947 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1948 DAG.getConstant(B.First, dl, VT));
1951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1952 SDValue RangeCmp = DAG.getSetCC(
1953 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1954 Sub.getValueType()),
1955 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1957 // Determine the type of the test operands.
1958 bool UsePtrType = false;
1959 if (!TLI.isTypeLegal(VT))
1962 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1963 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1964 // Switch table case range are encoded into series of masks.
1965 // Just use pointer type, it's guaranteed to fit.
1971 VT = TLI.getPointerTy(DAG.getDataLayout());
1972 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1975 B.RegVT = VT.getSimpleVT();
1976 B.Reg = FuncInfo.CreateReg(B.RegVT);
1977 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1979 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1981 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1982 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1984 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1985 MVT::Other, CopyTo, RangeCmp,
1986 DAG.getBasicBlock(B.Default));
1988 // Avoid emitting unnecessary branches to the next block.
1989 if (MBB != NextBlock(SwitchBB))
1990 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1991 DAG.getBasicBlock(MBB));
1993 DAG.setRoot(BrRange);
1996 /// visitBitTestCase - this function produces one "bit test"
1997 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1998 MachineBasicBlock* NextMBB,
1999 uint32_t BranchWeightToNext,
2002 MachineBasicBlock *SwitchBB) {
2003 SDLoc dl = getCurSDLoc();
2005 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2007 unsigned PopCount = countPopulation(B.Mask);
2008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2009 if (PopCount == 1) {
2010 // Testing for a single bit; just compare the shift count with what it
2011 // would need to be to shift a 1 bit in that position.
2013 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2014 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2016 } else if (PopCount == BB.Range) {
2017 // There is only one zero bit in the range, test for it directly.
2019 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2020 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2023 // Make desired shift
2024 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2025 DAG.getConstant(1, dl, VT), ShiftOp);
2027 // Emit bit tests and jumps
2028 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2029 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2031 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2032 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2035 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2036 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2037 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2038 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2040 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2041 MVT::Other, getControlRoot(),
2042 Cmp, DAG.getBasicBlock(B.TargetBB));
2044 // Avoid emitting unnecessary branches to the next block.
2045 if (NextMBB != NextBlock(SwitchBB))
2046 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2047 DAG.getBasicBlock(NextMBB));
2052 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2053 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2055 // Retrieve successors. Look through artificial IR level blocks like catchpads
2056 // and catchendpads for successors.
2057 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2058 const BasicBlock *EHPadBB = I.getSuccessor(1);
2060 const Value *Callee(I.getCalledValue());
2061 const Function *Fn = dyn_cast<Function>(Callee);
2062 if (isa<InlineAsm>(Callee))
2064 else if (Fn && Fn->isIntrinsic()) {
2065 switch (Fn->getIntrinsicID()) {
2067 llvm_unreachable("Cannot invoke this intrinsic");
2068 case Intrinsic::donothing:
2069 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2071 case Intrinsic::experimental_patchpoint_void:
2072 case Intrinsic::experimental_patchpoint_i64:
2073 visitPatchpoint(&I, EHPadBB);
2075 case Intrinsic::experimental_gc_statepoint:
2076 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2080 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2082 // If the value of the invoke is used outside of its defining block, make it
2083 // available as a virtual register.
2084 // We already took care of the exported value for the statepoint instruction
2085 // during call to the LowerStatepoint.
2086 if (!isStatepoint(I)) {
2087 CopyToExportRegsIfNeeded(&I);
2090 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2091 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2093 // Update successor info.
2094 // FIXME: The weights for catchpads will be wrong.
2095 addSuccessorWithWeight(InvokeMBB, Return);
2096 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2097 UnwindDest->setIsEHPad();
2098 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2101 // Drop into normal successor.
2102 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2103 MVT::Other, getControlRoot(),
2104 DAG.getBasicBlock(Return)));
2107 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2108 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2111 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2112 assert(FuncInfo.MBB->isEHPad() &&
2113 "Call to landingpad not in landing pad!");
2115 MachineBasicBlock *MBB = FuncInfo.MBB;
2116 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2117 AddLandingPadInfo(LP, MMI, MBB);
2119 // If there aren't registers to copy the values into (e.g., during SjLj
2120 // exceptions), then don't bother to create these DAG nodes.
2121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2122 if (TLI.getExceptionPointerRegister() == 0 &&
2123 TLI.getExceptionSelectorRegister() == 0)
2126 SmallVector<EVT, 2> ValueVTs;
2127 SDLoc dl = getCurSDLoc();
2128 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2129 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2131 // Get the two live-in registers as SDValues. The physregs have already been
2132 // copied into virtual registers.
2134 if (FuncInfo.ExceptionPointerVirtReg) {
2135 Ops[0] = DAG.getZExtOrTrunc(
2136 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2137 FuncInfo.ExceptionPointerVirtReg,
2138 TLI.getPointerTy(DAG.getDataLayout())),
2141 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2143 Ops[1] = DAG.getZExtOrTrunc(
2144 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2145 FuncInfo.ExceptionSelectorVirtReg,
2146 TLI.getPointerTy(DAG.getDataLayout())),
2150 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2151 DAG.getVTList(ValueVTs), Ops);
2155 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2157 for (const CaseCluster &CC : Clusters)
2158 assert(CC.Low == CC.High && "Input clusters must be single-case");
2161 std::sort(Clusters.begin(), Clusters.end(),
2162 [](const CaseCluster &a, const CaseCluster &b) {
2163 return a.Low->getValue().slt(b.Low->getValue());
2166 // Merge adjacent clusters with the same destination.
2167 const unsigned N = Clusters.size();
2168 unsigned DstIndex = 0;
2169 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2170 CaseCluster &CC = Clusters[SrcIndex];
2171 const ConstantInt *CaseVal = CC.Low;
2172 MachineBasicBlock *Succ = CC.MBB;
2174 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2175 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2176 // If this case has the same successor and is a neighbour, merge it into
2177 // the previous cluster.
2178 Clusters[DstIndex - 1].High = CaseVal;
2179 Clusters[DstIndex - 1].Weight += CC.Weight;
2180 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2182 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2183 sizeof(Clusters[SrcIndex]));
2186 Clusters.resize(DstIndex);
2189 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2190 MachineBasicBlock *Last) {
2192 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2193 if (JTCases[i].first.HeaderBB == First)
2194 JTCases[i].first.HeaderBB = Last;
2196 // Update BitTestCases.
2197 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2198 if (BitTestCases[i].Parent == First)
2199 BitTestCases[i].Parent = Last;
2202 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2203 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2205 // Update machine-CFG edges with unique successors.
2206 SmallSet<BasicBlock*, 32> Done;
2207 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2208 BasicBlock *BB = I.getSuccessor(i);
2209 bool Inserted = Done.insert(BB).second;
2213 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2214 addSuccessorWithWeight(IndirectBrMBB, Succ);
2217 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2218 MVT::Other, getControlRoot(),
2219 getValue(I.getAddress())));
2222 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2223 if (DAG.getTarget().Options.TrapUnreachable)
2225 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2228 void SelectionDAGBuilder::visitFSub(const User &I) {
2229 // -0.0 - X --> fneg
2230 Type *Ty = I.getType();
2231 if (isa<Constant>(I.getOperand(0)) &&
2232 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2233 SDValue Op2 = getValue(I.getOperand(1));
2234 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2235 Op2.getValueType(), Op2));
2239 visitBinary(I, ISD::FSUB);
2242 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2243 SDValue Op1 = getValue(I.getOperand(0));
2244 SDValue Op2 = getValue(I.getOperand(1));
2251 if (const OverflowingBinaryOperator *OFBinOp =
2252 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2253 nuw = OFBinOp->hasNoUnsignedWrap();
2254 nsw = OFBinOp->hasNoSignedWrap();
2256 if (const PossiblyExactOperator *ExactOp =
2257 dyn_cast<const PossiblyExactOperator>(&I))
2258 exact = ExactOp->isExact();
2259 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2260 FMF = FPOp->getFastMathFlags();
2263 Flags.setExact(exact);
2264 Flags.setNoSignedWrap(nsw);
2265 Flags.setNoUnsignedWrap(nuw);
2266 if (EnableFMFInDAG) {
2267 Flags.setAllowReciprocal(FMF.allowReciprocal());
2268 Flags.setNoInfs(FMF.noInfs());
2269 Flags.setNoNaNs(FMF.noNaNs());
2270 Flags.setNoSignedZeros(FMF.noSignedZeros());
2271 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2273 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2275 setValue(&I, BinNodeValue);
2278 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2279 SDValue Op1 = getValue(I.getOperand(0));
2280 SDValue Op2 = getValue(I.getOperand(1));
2282 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2283 Op2.getValueType(), DAG.getDataLayout());
2285 // Coerce the shift amount to the right type if we can.
2286 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2287 unsigned ShiftSize = ShiftTy.getSizeInBits();
2288 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2289 SDLoc DL = getCurSDLoc();
2291 // If the operand is smaller than the shift count type, promote it.
2292 if (ShiftSize > Op2Size)
2293 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2295 // If the operand is larger than the shift count type but the shift
2296 // count type has enough bits to represent any shift value, truncate
2297 // it now. This is a common case and it exposes the truncate to
2298 // optimization early.
2299 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2300 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2301 // Otherwise we'll need to temporarily settle for some other convenient
2302 // type. Type legalization will make adjustments once the shiftee is split.
2304 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2311 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2313 if (const OverflowingBinaryOperator *OFBinOp =
2314 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2315 nuw = OFBinOp->hasNoUnsignedWrap();
2316 nsw = OFBinOp->hasNoSignedWrap();
2318 if (const PossiblyExactOperator *ExactOp =
2319 dyn_cast<const PossiblyExactOperator>(&I))
2320 exact = ExactOp->isExact();
2323 Flags.setExact(exact);
2324 Flags.setNoSignedWrap(nsw);
2325 Flags.setNoUnsignedWrap(nuw);
2326 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2331 void SelectionDAGBuilder::visitSDiv(const User &I) {
2332 SDValue Op1 = getValue(I.getOperand(0));
2333 SDValue Op2 = getValue(I.getOperand(1));
2336 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2337 cast<PossiblyExactOperator>(&I)->isExact());
2338 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2342 void SelectionDAGBuilder::visitICmp(const User &I) {
2343 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2344 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2345 predicate = IC->getPredicate();
2346 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2347 predicate = ICmpInst::Predicate(IC->getPredicate());
2348 SDValue Op1 = getValue(I.getOperand(0));
2349 SDValue Op2 = getValue(I.getOperand(1));
2350 ISD::CondCode Opcode = getICmpCondCode(predicate);
2352 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2354 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2357 void SelectionDAGBuilder::visitFCmp(const User &I) {
2358 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2359 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2360 predicate = FC->getPredicate();
2361 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2362 predicate = FCmpInst::Predicate(FC->getPredicate());
2363 SDValue Op1 = getValue(I.getOperand(0));
2364 SDValue Op2 = getValue(I.getOperand(1));
2365 ISD::CondCode Condition = getFCmpCondCode(predicate);
2367 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2368 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2369 // further optimization, but currently FMF is only applicable to binary nodes.
2370 if (TM.Options.NoNaNsFPMath)
2371 Condition = getFCmpCodeWithoutNaN(Condition);
2372 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2374 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2377 void SelectionDAGBuilder::visitSelect(const User &I) {
2378 SmallVector<EVT, 4> ValueVTs;
2379 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2381 unsigned NumValues = ValueVTs.size();
2382 if (NumValues == 0) return;
2384 SmallVector<SDValue, 4> Values(NumValues);
2385 SDValue Cond = getValue(I.getOperand(0));
2386 SDValue LHSVal = getValue(I.getOperand(1));
2387 SDValue RHSVal = getValue(I.getOperand(2));
2388 auto BaseOps = {Cond};
2389 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2390 ISD::VSELECT : ISD::SELECT;
2392 // Min/max matching is only viable if all output VTs are the same.
2393 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2394 EVT VT = ValueVTs[0];
2395 LLVMContext &Ctx = *DAG.getContext();
2396 auto &TLI = DAG.getTargetLoweringInfo();
2397 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2398 VT = TLI.getTypeToTransformTo(Ctx, VT);
2401 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2402 ISD::NodeType Opc = ISD::DELETED_NODE;
2403 switch (SPR.Flavor) {
2404 case SPF_UMAX: Opc = ISD::UMAX; break;
2405 case SPF_UMIN: Opc = ISD::UMIN; break;
2406 case SPF_SMAX: Opc = ISD::SMAX; break;
2407 case SPF_SMIN: Opc = ISD::SMIN; break;
2409 switch (SPR.NaNBehavior) {
2410 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2411 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2412 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2413 case SPNB_RETURNS_ANY:
2414 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2420 switch (SPR.NaNBehavior) {
2421 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2422 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2423 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2424 case SPNB_RETURNS_ANY:
2425 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2433 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2434 // If the underlying comparison instruction is used by any other instruction,
2435 // the consumed instructions won't be destroyed, so it is not profitable
2436 // to convert to a min/max.
2437 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2439 LHSVal = getValue(LHS);
2440 RHSVal = getValue(RHS);
2445 for (unsigned i = 0; i != NumValues; ++i) {
2446 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2447 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2448 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2449 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2450 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2454 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2455 DAG.getVTList(ValueVTs), Values));
2458 void SelectionDAGBuilder::visitTrunc(const User &I) {
2459 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2460 SDValue N = getValue(I.getOperand(0));
2461 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2463 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2466 void SelectionDAGBuilder::visitZExt(const User &I) {
2467 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2468 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2469 SDValue N = getValue(I.getOperand(0));
2470 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2472 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2475 void SelectionDAGBuilder::visitSExt(const User &I) {
2476 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2477 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2478 SDValue N = getValue(I.getOperand(0));
2479 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2481 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2484 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2485 // FPTrunc is never a no-op cast, no need to check
2486 SDValue N = getValue(I.getOperand(0));
2487 SDLoc dl = getCurSDLoc();
2488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2489 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2490 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2491 DAG.getTargetConstant(
2492 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2495 void SelectionDAGBuilder::visitFPExt(const User &I) {
2496 // FPExt is never a no-op cast, no need to check
2497 SDValue N = getValue(I.getOperand(0));
2498 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2500 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2503 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2504 // FPToUI is never a no-op cast, no need to check
2505 SDValue N = getValue(I.getOperand(0));
2506 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2508 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2511 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2512 // FPToSI is never a no-op cast, no need to check
2513 SDValue N = getValue(I.getOperand(0));
2514 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2516 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2519 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2520 // UIToFP is never a no-op cast, no need to check
2521 SDValue N = getValue(I.getOperand(0));
2522 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2524 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2527 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2528 // SIToFP is never a no-op cast, no need to check
2529 SDValue N = getValue(I.getOperand(0));
2530 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2532 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2535 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2536 // What to do depends on the size of the integer and the size of the pointer.
2537 // We can either truncate, zero extend, or no-op, accordingly.
2538 SDValue N = getValue(I.getOperand(0));
2539 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2541 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2544 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2545 // What to do depends on the size of the integer and the size of the pointer.
2546 // We can either truncate, zero extend, or no-op, accordingly.
2547 SDValue N = getValue(I.getOperand(0));
2548 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2550 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2553 void SelectionDAGBuilder::visitBitCast(const User &I) {
2554 SDValue N = getValue(I.getOperand(0));
2555 SDLoc dl = getCurSDLoc();
2556 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2559 // BitCast assures us that source and destination are the same size so this is
2560 // either a BITCAST or a no-op.
2561 if (DestVT != N.getValueType())
2562 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2563 DestVT, N)); // convert types.
2564 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2565 // might fold any kind of constant expression to an integer constant and that
2566 // is not what we are looking for. Only regcognize a bitcast of a genuine
2567 // constant integer as an opaque constant.
2568 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2569 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2572 setValue(&I, N); // noop cast.
2575 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2576 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2577 const Value *SV = I.getOperand(0);
2578 SDValue N = getValue(SV);
2579 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2581 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2582 unsigned DestAS = I.getType()->getPointerAddressSpace();
2584 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2585 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2590 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2591 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2592 SDValue InVec = getValue(I.getOperand(0));
2593 SDValue InVal = getValue(I.getOperand(1));
2594 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2595 TLI.getVectorIdxTy(DAG.getDataLayout()));
2596 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2597 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2598 InVec, InVal, InIdx));
2601 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2603 SDValue InVec = getValue(I.getOperand(0));
2604 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2605 TLI.getVectorIdxTy(DAG.getDataLayout()));
2606 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2607 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2611 // Utility for visitShuffleVector - Return true if every element in Mask,
2612 // beginning from position Pos and ending in Pos+Size, falls within the
2613 // specified sequential range [L, L+Pos). or is undef.
2614 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2615 unsigned Pos, unsigned Size, int Low) {
2616 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2617 if (Mask[i] >= 0 && Mask[i] != Low)
2622 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2623 SDValue Src1 = getValue(I.getOperand(0));
2624 SDValue Src2 = getValue(I.getOperand(1));
2626 SmallVector<int, 8> Mask;
2627 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2628 unsigned MaskNumElts = Mask.size();
2630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2631 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2632 EVT SrcVT = Src1.getValueType();
2633 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2635 if (SrcNumElts == MaskNumElts) {
2636 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2641 // Normalize the shuffle vector since mask and vector length don't match.
2642 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2643 // Mask is longer than the source vectors and is a multiple of the source
2644 // vectors. We can use concatenate vector to make the mask and vectors
2646 if (SrcNumElts*2 == MaskNumElts) {
2647 // First check for Src1 in low and Src2 in high
2648 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2649 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2650 // The shuffle is concatenating two vectors together.
2651 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2655 // Then check for Src2 in low and Src1 in high
2656 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2657 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2658 // The shuffle is concatenating two vectors together.
2659 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2665 // Pad both vectors with undefs to make them the same length as the mask.
2666 unsigned NumConcat = MaskNumElts / SrcNumElts;
2667 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2668 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2669 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2671 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2672 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2676 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2677 getCurSDLoc(), VT, MOps1);
2678 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2679 getCurSDLoc(), VT, MOps2);
2681 // Readjust mask for new input vector length.
2682 SmallVector<int, 8> MappedOps;
2683 for (unsigned i = 0; i != MaskNumElts; ++i) {
2685 if (Idx >= (int)SrcNumElts)
2686 Idx -= SrcNumElts - MaskNumElts;
2687 MappedOps.push_back(Idx);
2690 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2695 if (SrcNumElts > MaskNumElts) {
2696 // Analyze the access pattern of the vector to see if we can extract
2697 // two subvectors and do the shuffle. The analysis is done by calculating
2698 // the range of elements the mask access on both vectors.
2699 int MinRange[2] = { static_cast<int>(SrcNumElts),
2700 static_cast<int>(SrcNumElts)};
2701 int MaxRange[2] = {-1, -1};
2703 for (unsigned i = 0; i != MaskNumElts; ++i) {
2709 if (Idx >= (int)SrcNumElts) {
2713 if (Idx > MaxRange[Input])
2714 MaxRange[Input] = Idx;
2715 if (Idx < MinRange[Input])
2716 MinRange[Input] = Idx;
2719 // Check if the access is smaller than the vector size and can we find
2720 // a reasonable extract index.
2721 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2723 int StartIdx[2]; // StartIdx to extract from
2724 for (unsigned Input = 0; Input < 2; ++Input) {
2725 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2726 RangeUse[Input] = 0; // Unused
2727 StartIdx[Input] = 0;
2731 // Find a good start index that is a multiple of the mask length. Then
2732 // see if the rest of the elements are in range.
2733 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2734 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2735 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2736 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2739 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2740 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2743 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2744 // Extract appropriate subvector and generate a vector shuffle
2745 for (unsigned Input = 0; Input < 2; ++Input) {
2746 SDValue &Src = Input == 0 ? Src1 : Src2;
2747 if (RangeUse[Input] == 0)
2748 Src = DAG.getUNDEF(VT);
2750 SDLoc dl = getCurSDLoc();
2752 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2753 DAG.getConstant(StartIdx[Input], dl,
2754 TLI.getVectorIdxTy(DAG.getDataLayout())));
2758 // Calculate new mask.
2759 SmallVector<int, 8> MappedOps;
2760 for (unsigned i = 0; i != MaskNumElts; ++i) {
2763 if (Idx < (int)SrcNumElts)
2766 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2768 MappedOps.push_back(Idx);
2771 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2777 // We can't use either concat vectors or extract subvectors so fall back to
2778 // replacing the shuffle with extract and build vector.
2779 // to insert and build vector.
2780 EVT EltVT = VT.getVectorElementType();
2781 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2782 SDLoc dl = getCurSDLoc();
2783 SmallVector<SDValue,8> Ops;
2784 for (unsigned i = 0; i != MaskNumElts; ++i) {
2789 Res = DAG.getUNDEF(EltVT);
2791 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2792 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2794 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2795 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2801 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2804 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2805 const Value *Op0 = I.getOperand(0);
2806 const Value *Op1 = I.getOperand(1);
2807 Type *AggTy = I.getType();
2808 Type *ValTy = Op1->getType();
2809 bool IntoUndef = isa<UndefValue>(Op0);
2810 bool FromUndef = isa<UndefValue>(Op1);
2812 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2814 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2815 SmallVector<EVT, 4> AggValueVTs;
2816 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2817 SmallVector<EVT, 4> ValValueVTs;
2818 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2820 unsigned NumAggValues = AggValueVTs.size();
2821 unsigned NumValValues = ValValueVTs.size();
2822 SmallVector<SDValue, 4> Values(NumAggValues);
2824 // Ignore an insertvalue that produces an empty object
2825 if (!NumAggValues) {
2826 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2830 SDValue Agg = getValue(Op0);
2832 // Copy the beginning value(s) from the original aggregate.
2833 for (; i != LinearIndex; ++i)
2834 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2835 SDValue(Agg.getNode(), Agg.getResNo() + i);
2836 // Copy values from the inserted value(s).
2838 SDValue Val = getValue(Op1);
2839 for (; i != LinearIndex + NumValValues; ++i)
2840 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2841 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2843 // Copy remaining value(s) from the original aggregate.
2844 for (; i != NumAggValues; ++i)
2845 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2846 SDValue(Agg.getNode(), Agg.getResNo() + i);
2848 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2849 DAG.getVTList(AggValueVTs), Values));
2852 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2853 const Value *Op0 = I.getOperand(0);
2854 Type *AggTy = Op0->getType();
2855 Type *ValTy = I.getType();
2856 bool OutOfUndef = isa<UndefValue>(Op0);
2858 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2861 SmallVector<EVT, 4> ValValueVTs;
2862 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2864 unsigned NumValValues = ValValueVTs.size();
2866 // Ignore a extractvalue that produces an empty object
2867 if (!NumValValues) {
2868 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2872 SmallVector<SDValue, 4> Values(NumValValues);
2874 SDValue Agg = getValue(Op0);
2875 // Copy out the selected value(s).
2876 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2877 Values[i - LinearIndex] =
2879 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2880 SDValue(Agg.getNode(), Agg.getResNo() + i);
2882 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2883 DAG.getVTList(ValValueVTs), Values));
2886 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2887 Value *Op0 = I.getOperand(0);
2888 // Note that the pointer operand may be a vector of pointers. Take the scalar
2889 // element which holds a pointer.
2890 Type *Ty = Op0->getType()->getScalarType();
2891 unsigned AS = Ty->getPointerAddressSpace();
2892 SDValue N = getValue(Op0);
2893 SDLoc dl = getCurSDLoc();
2895 // Normalize Vector GEP - all scalar operands should be converted to the
2897 unsigned VectorWidth = I.getType()->isVectorTy() ?
2898 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2900 if (VectorWidth && !N.getValueType().isVector()) {
2901 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2902 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2903 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2905 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2907 const Value *Idx = *OI;
2908 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2909 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2912 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2913 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2914 DAG.getConstant(Offset, dl, N.getValueType()));
2917 Ty = StTy->getElementType(Field);
2919 Ty = cast<SequentialType>(Ty)->getElementType();
2921 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2922 unsigned PtrSize = PtrTy.getSizeInBits();
2923 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2925 // If this is a scalar constant or a splat vector of constants,
2926 // handle it quickly.
2927 const auto *CI = dyn_cast<ConstantInt>(Idx);
2928 if (!CI && isa<ConstantDataVector>(Idx) &&
2929 cast<ConstantDataVector>(Idx)->getSplatValue())
2930 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2935 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2936 SDValue OffsVal = VectorWidth ?
2937 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2938 DAG.getConstant(Offs, dl, PtrTy);
2939 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2943 // N = N + Idx * ElementSize;
2944 SDValue IdxN = getValue(Idx);
2946 if (!IdxN.getValueType().isVector() && VectorWidth) {
2947 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2948 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2949 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2951 // If the index is smaller or larger than intptr_t, truncate or extend
2953 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2955 // If this is a multiply by a power of two, turn it into a shl
2956 // immediately. This is a very common case.
2957 if (ElementSize != 1) {
2958 if (ElementSize.isPowerOf2()) {
2959 unsigned Amt = ElementSize.logBase2();
2960 IdxN = DAG.getNode(ISD::SHL, dl,
2961 N.getValueType(), IdxN,
2962 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2964 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2965 IdxN = DAG.getNode(ISD::MUL, dl,
2966 N.getValueType(), IdxN, Scale);
2970 N = DAG.getNode(ISD::ADD, dl,
2971 N.getValueType(), N, IdxN);
2978 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2979 // If this is a fixed sized alloca in the entry block of the function,
2980 // allocate it statically on the stack.
2981 if (FuncInfo.StaticAllocaMap.count(&I))
2982 return; // getValue will auto-populate this.
2984 SDLoc dl = getCurSDLoc();
2985 Type *Ty = I.getAllocatedType();
2986 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2987 auto &DL = DAG.getDataLayout();
2988 uint64_t TySize = DL.getTypeAllocSize(Ty);
2990 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2992 SDValue AllocSize = getValue(I.getArraySize());
2994 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2995 if (AllocSize.getValueType() != IntPtr)
2996 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2998 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3000 DAG.getConstant(TySize, dl, IntPtr));
3002 // Handle alignment. If the requested alignment is less than or equal to
3003 // the stack alignment, ignore it. If the size is greater than or equal to
3004 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3005 unsigned StackAlign =
3006 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3007 if (Align <= StackAlign)
3010 // Round the size of the allocation up to the stack alignment size
3011 // by add SA-1 to the size.
3012 AllocSize = DAG.getNode(ISD::ADD, dl,
3013 AllocSize.getValueType(), AllocSize,
3014 DAG.getIntPtrConstant(StackAlign - 1, dl));
3016 // Mask out the low bits for alignment purposes.
3017 AllocSize = DAG.getNode(ISD::AND, dl,
3018 AllocSize.getValueType(), AllocSize,
3019 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3022 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3023 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3024 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3026 DAG.setRoot(DSA.getValue(1));
3028 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3031 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3033 return visitAtomicLoad(I);
3035 const Value *SV = I.getOperand(0);
3036 SDValue Ptr = getValue(SV);
3038 Type *Ty = I.getType();
3040 bool isVolatile = I.isVolatile();
3041 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3043 // The IR notion of invariant_load only guarantees that all *non-faulting*
3044 // invariant loads result in the same value. The MI notion of invariant load
3045 // guarantees that the load can be legally moved to any location within its
3046 // containing function. The MI notion of invariant_load is stronger than the
3047 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3048 // with a guarantee that the location being loaded from is dereferenceable
3049 // throughout the function's lifetime.
3051 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3052 isDereferenceablePointer(SV, DAG.getDataLayout());
3053 unsigned Alignment = I.getAlignment();
3056 I.getAAMetadata(AAInfo);
3057 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3060 SmallVector<EVT, 4> ValueVTs;
3061 SmallVector<uint64_t, 4> Offsets;
3062 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3063 unsigned NumValues = ValueVTs.size();
3068 bool ConstantMemory = false;
3069 if (isVolatile || NumValues > MaxParallelChains)
3070 // Serialize volatile loads with other side effects.
3072 else if (AA->pointsToConstantMemory(MemoryLocation(
3073 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3074 // Do not serialize (non-volatile) loads of constant memory with anything.
3075 Root = DAG.getEntryNode();
3076 ConstantMemory = true;
3078 // Do not serialize non-volatile loads against each other.
3079 Root = DAG.getRoot();
3082 SDLoc dl = getCurSDLoc();
3085 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3087 SmallVector<SDValue, 4> Values(NumValues);
3088 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3089 EVT PtrVT = Ptr.getValueType();
3090 unsigned ChainI = 0;
3091 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3092 // Serializing loads here may result in excessive register pressure, and
3093 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3094 // could recover a bit by hoisting nodes upward in the chain by recognizing
3095 // they are side-effect free or do not alias. The optimizer should really
3096 // avoid this case by converting large object/array copies to llvm.memcpy
3097 // (MaxParallelChains should always remain as failsafe).
3098 if (ChainI == MaxParallelChains) {
3099 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3100 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3101 makeArrayRef(Chains.data(), ChainI));
3105 SDValue A = DAG.getNode(ISD::ADD, dl,
3107 DAG.getConstant(Offsets[i], dl, PtrVT));
3108 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3109 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3110 isNonTemporal, isInvariant, Alignment, AAInfo,
3114 Chains[ChainI] = L.getValue(1);
3117 if (!ConstantMemory) {
3118 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3119 makeArrayRef(Chains.data(), ChainI));
3123 PendingLoads.push_back(Chain);
3126 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3127 DAG.getVTList(ValueVTs), Values));
3130 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3132 return visitAtomicStore(I);
3134 const Value *SrcV = I.getOperand(0);
3135 const Value *PtrV = I.getOperand(1);
3137 SmallVector<EVT, 4> ValueVTs;
3138 SmallVector<uint64_t, 4> Offsets;
3139 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3140 SrcV->getType(), ValueVTs, &Offsets);
3141 unsigned NumValues = ValueVTs.size();
3145 // Get the lowered operands. Note that we do this after
3146 // checking if NumResults is zero, because with zero results
3147 // the operands won't have values in the map.
3148 SDValue Src = getValue(SrcV);
3149 SDValue Ptr = getValue(PtrV);
3151 SDValue Root = getRoot();
3152 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3153 EVT PtrVT = Ptr.getValueType();
3154 bool isVolatile = I.isVolatile();
3155 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3156 unsigned Alignment = I.getAlignment();
3157 SDLoc dl = getCurSDLoc();
3160 I.getAAMetadata(AAInfo);
3162 unsigned ChainI = 0;
3163 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3164 // See visitLoad comments.
3165 if (ChainI == MaxParallelChains) {
3166 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3167 makeArrayRef(Chains.data(), ChainI));
3171 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3172 DAG.getConstant(Offsets[i], dl, PtrVT));
3173 SDValue St = DAG.getStore(Root, dl,
3174 SDValue(Src.getNode(), Src.getResNo() + i),
3175 Add, MachinePointerInfo(PtrV, Offsets[i]),
3176 isVolatile, isNonTemporal, Alignment, AAInfo);
3177 Chains[ChainI] = St;
3180 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3181 makeArrayRef(Chains.data(), ChainI));
3182 DAG.setRoot(StoreNode);
3185 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3186 SDLoc sdl = getCurSDLoc();
3188 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3189 Value *PtrOperand = I.getArgOperand(1);
3190 SDValue Ptr = getValue(PtrOperand);
3191 SDValue Src0 = getValue(I.getArgOperand(0));
3192 SDValue Mask = getValue(I.getArgOperand(3));
3193 EVT VT = Src0.getValueType();
3194 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3196 Alignment = DAG.getEVTAlignment(VT);
3199 I.getAAMetadata(AAInfo);
3201 MachineMemOperand *MMO =
3202 DAG.getMachineFunction().
3203 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3204 MachineMemOperand::MOStore, VT.getStoreSize(),
3206 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3208 DAG.setRoot(StoreNode);
3209 setValue(&I, StoreNode);
3212 // Get a uniform base for the Gather/Scatter intrinsic.
3213 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3214 // We try to represent it as a base pointer + vector of indices.
3215 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3216 // The first operand of the GEP may be a single pointer or a vector of pointers
3218 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3220 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3221 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3223 // When the first GEP operand is a single pointer - it is the uniform base we
3224 // are looking for. If first operand of the GEP is a splat vector - we
3225 // extract the spalt value and use it as a uniform base.
3226 // In all other cases the function returns 'false'.
3228 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3229 SelectionDAGBuilder* SDB) {
3231 SelectionDAG& DAG = SDB->DAG;
3232 LLVMContext &Context = *DAG.getContext();
3234 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3235 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3236 if (!GEP || GEP->getNumOperands() > 2)
3239 Value *GEPPtr = GEP->getPointerOperand();
3240 if (!GEPPtr->getType()->isVectorTy())
3242 else if (!(Ptr = getSplatValue(GEPPtr)))
3245 Value *IndexVal = GEP->getOperand(1);
3247 // The operands of the GEP may be defined in another basic block.
3248 // In this case we'll not find nodes for the operands.
3249 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3252 Base = SDB->getValue(Ptr);
3253 Index = SDB->getValue(IndexVal);
3255 // Suppress sign extension.
3256 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3257 if (SDB->findValue(Sext->getOperand(0))) {
3258 IndexVal = Sext->getOperand(0);
3259 Index = SDB->getValue(IndexVal);
3262 if (!Index.getValueType().isVector()) {
3263 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3264 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3265 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3266 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3271 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3272 SDLoc sdl = getCurSDLoc();
3274 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3275 Value *Ptr = I.getArgOperand(1);
3276 SDValue Src0 = getValue(I.getArgOperand(0));
3277 SDValue Mask = getValue(I.getArgOperand(3));
3278 EVT VT = Src0.getValueType();
3279 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3281 Alignment = DAG.getEVTAlignment(VT);
3282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3285 I.getAAMetadata(AAInfo);
3289 Value *BasePtr = Ptr;
3290 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3292 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3293 MachineMemOperand *MMO = DAG.getMachineFunction().
3294 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3295 MachineMemOperand::MOStore, VT.getStoreSize(),
3298 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3299 Index = getValue(Ptr);
3301 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3302 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3304 DAG.setRoot(Scatter);
3305 setValue(&I, Scatter);
3308 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3309 SDLoc sdl = getCurSDLoc();
3311 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3312 Value *PtrOperand = I.getArgOperand(0);
3313 SDValue Ptr = getValue(PtrOperand);
3314 SDValue Src0 = getValue(I.getArgOperand(3));
3315 SDValue Mask = getValue(I.getArgOperand(2));
3317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3318 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3319 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3321 Alignment = DAG.getEVTAlignment(VT);
3324 I.getAAMetadata(AAInfo);
3325 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3327 SDValue InChain = DAG.getRoot();
3328 if (AA->pointsToConstantMemory(MemoryLocation(
3329 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3331 // Do not serialize (non-volatile) loads of constant memory with anything.
3332 InChain = DAG.getEntryNode();
3335 MachineMemOperand *MMO =
3336 DAG.getMachineFunction().
3337 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3338 MachineMemOperand::MOLoad, VT.getStoreSize(),
3339 Alignment, AAInfo, Ranges);
3341 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3343 SDValue OutChain = Load.getValue(1);
3344 DAG.setRoot(OutChain);
3348 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3349 SDLoc sdl = getCurSDLoc();
3351 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3352 Value *Ptr = I.getArgOperand(0);
3353 SDValue Src0 = getValue(I.getArgOperand(3));
3354 SDValue Mask = getValue(I.getArgOperand(2));
3356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3357 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3358 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3360 Alignment = DAG.getEVTAlignment(VT);
3363 I.getAAMetadata(AAInfo);
3364 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3366 SDValue Root = DAG.getRoot();
3369 Value *BasePtr = Ptr;
3370 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3371 bool ConstantMemory = false;
3373 AA->pointsToConstantMemory(MemoryLocation(
3374 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3376 // Do not serialize (non-volatile) loads of constant memory with anything.
3377 Root = DAG.getEntryNode();
3378 ConstantMemory = true;
3381 MachineMemOperand *MMO =
3382 DAG.getMachineFunction().
3383 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3384 MachineMemOperand::MOLoad, VT.getStoreSize(),
3385 Alignment, AAInfo, Ranges);
3388 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3389 Index = getValue(Ptr);
3391 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3392 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3395 SDValue OutChain = Gather.getValue(1);
3396 if (!ConstantMemory)
3397 PendingLoads.push_back(OutChain);
3398 setValue(&I, Gather);
3401 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3402 SDLoc dl = getCurSDLoc();
3403 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3404 AtomicOrdering FailureOrder = I.getFailureOrdering();
3405 SynchronizationScope Scope = I.getSynchScope();
3407 SDValue InChain = getRoot();
3409 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3410 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3411 SDValue L = DAG.getAtomicCmpSwap(
3412 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3413 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3414 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3415 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3417 SDValue OutChain = L.getValue(2);
3420 DAG.setRoot(OutChain);
3423 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3424 SDLoc dl = getCurSDLoc();
3426 switch (I.getOperation()) {
3427 default: llvm_unreachable("Unknown atomicrmw operation");
3428 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3429 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3430 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3431 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3432 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3433 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3434 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3435 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3436 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3437 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3438 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3440 AtomicOrdering Order = I.getOrdering();
3441 SynchronizationScope Scope = I.getSynchScope();
3443 SDValue InChain = getRoot();
3446 DAG.getAtomic(NT, dl,
3447 getValue(I.getValOperand()).getSimpleValueType(),
3449 getValue(I.getPointerOperand()),
3450 getValue(I.getValOperand()),
3451 I.getPointerOperand(),
3452 /* Alignment=*/ 0, Order, Scope);
3454 SDValue OutChain = L.getValue(1);
3457 DAG.setRoot(OutChain);
3460 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3461 SDLoc dl = getCurSDLoc();
3462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3465 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3466 TLI.getPointerTy(DAG.getDataLayout()));
3467 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3468 TLI.getPointerTy(DAG.getDataLayout()));
3469 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3472 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3473 SDLoc dl = getCurSDLoc();
3474 AtomicOrdering Order = I.getOrdering();
3475 SynchronizationScope Scope = I.getSynchScope();
3477 SDValue InChain = getRoot();
3479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3480 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3482 if (I.getAlignment() < VT.getSizeInBits() / 8)
3483 report_fatal_error("Cannot generate unaligned atomic load");
3485 MachineMemOperand *MMO =
3486 DAG.getMachineFunction().
3487 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3488 MachineMemOperand::MOVolatile |
3489 MachineMemOperand::MOLoad,
3491 I.getAlignment() ? I.getAlignment() :
3492 DAG.getEVTAlignment(VT));
3494 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3496 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3497 getValue(I.getPointerOperand()), MMO,
3500 SDValue OutChain = L.getValue(1);
3503 DAG.setRoot(OutChain);
3506 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3507 SDLoc dl = getCurSDLoc();
3509 AtomicOrdering Order = I.getOrdering();
3510 SynchronizationScope Scope = I.getSynchScope();
3512 SDValue InChain = getRoot();
3514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3516 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3518 if (I.getAlignment() < VT.getSizeInBits() / 8)
3519 report_fatal_error("Cannot generate unaligned atomic store");
3522 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3524 getValue(I.getPointerOperand()),
3525 getValue(I.getValueOperand()),
3526 I.getPointerOperand(), I.getAlignment(),
3529 DAG.setRoot(OutChain);
3532 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3534 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3535 unsigned Intrinsic) {
3536 bool HasChain = !I.doesNotAccessMemory();
3537 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3539 // Build the operand list.
3540 SmallVector<SDValue, 8> Ops;
3541 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3543 // We don't need to serialize loads against other loads.
3544 Ops.push_back(DAG.getRoot());
3546 Ops.push_back(getRoot());
3550 // Info is set by getTgtMemInstrinsic
3551 TargetLowering::IntrinsicInfo Info;
3552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3553 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3555 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3556 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3557 Info.opc == ISD::INTRINSIC_W_CHAIN)
3558 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3559 TLI.getPointerTy(DAG.getDataLayout())));
3561 // Add all operands of the call to the operand list.
3562 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3563 SDValue Op = getValue(I.getArgOperand(i));
3567 SmallVector<EVT, 4> ValueVTs;
3568 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3571 ValueVTs.push_back(MVT::Other);
3573 SDVTList VTs = DAG.getVTList(ValueVTs);
3577 if (IsTgtIntrinsic) {
3578 // This is target intrinsic that touches memory
3579 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3580 VTs, Ops, Info.memVT,
3581 MachinePointerInfo(Info.ptrVal, Info.offset),
3582 Info.align, Info.vol,
3583 Info.readMem, Info.writeMem, Info.size);
3584 } else if (!HasChain) {
3585 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3586 } else if (!I.getType()->isVoidTy()) {
3587 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3589 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3593 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3595 PendingLoads.push_back(Chain);
3600 if (!I.getType()->isVoidTy()) {
3601 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3602 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3603 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3606 setValue(&I, Result);
3610 /// GetSignificand - Get the significand and build it into a floating-point
3611 /// number with exponent of 1:
3613 /// Op = (Op & 0x007fffff) | 0x3f800000;
3615 /// where Op is the hexadecimal representation of floating point value.
3617 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3618 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3619 DAG.getConstant(0x007fffff, dl, MVT::i32));
3620 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3621 DAG.getConstant(0x3f800000, dl, MVT::i32));
3622 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3625 /// GetExponent - Get the exponent:
3627 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3629 /// where Op is the hexadecimal representation of floating point value.
3631 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3633 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3634 DAG.getConstant(0x7f800000, dl, MVT::i32));
3635 SDValue t1 = DAG.getNode(
3636 ISD::SRL, dl, MVT::i32, t0,
3637 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3638 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3639 DAG.getConstant(127, dl, MVT::i32));
3640 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3643 /// getF32Constant - Get 32-bit floating point constant.
3645 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3646 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3650 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3651 SelectionDAG &DAG) {
3652 // TODO: What fast-math-flags should be set on the floating-point nodes?
3654 // IntegerPartOfX = ((int32_t)(t0);
3655 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3657 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3658 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3659 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3661 // IntegerPartOfX <<= 23;
3662 IntegerPartOfX = DAG.getNode(
3663 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3664 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3665 DAG.getDataLayout())));
3667 SDValue TwoToFractionalPartOfX;
3668 if (LimitFloatPrecision <= 6) {
3669 // For floating-point precision of 6:
3671 // TwoToFractionalPartOfX =
3673 // (0.735607626f + 0.252464424f * x) * x;
3675 // error 0.0144103317, which is 6 bits
3676 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3677 getF32Constant(DAG, 0x3e814304, dl));
3678 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3679 getF32Constant(DAG, 0x3f3c50c8, dl));
3680 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3681 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3682 getF32Constant(DAG, 0x3f7f5e7e, dl));
3683 } else if (LimitFloatPrecision <= 12) {
3684 // For floating-point precision of 12:
3686 // TwoToFractionalPartOfX =
3689 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3691 // error 0.000107046256, which is 13 to 14 bits
3692 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3693 getF32Constant(DAG, 0x3da235e3, dl));
3694 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3695 getF32Constant(DAG, 0x3e65b8f3, dl));
3696 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3697 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3698 getF32Constant(DAG, 0x3f324b07, dl));
3699 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3700 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3701 getF32Constant(DAG, 0x3f7ff8fd, dl));
3702 } else { // LimitFloatPrecision <= 18
3703 // For floating-point precision of 18:
3705 // TwoToFractionalPartOfX =
3709 // (0.554906021e-1f +
3710 // (0.961591928e-2f +
3711 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3712 // error 2.47208000*10^(-7), which is better than 18 bits
3713 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3714 getF32Constant(DAG, 0x3924b03e, dl));
3715 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3716 getF32Constant(DAG, 0x3ab24b87, dl));
3717 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3718 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3719 getF32Constant(DAG, 0x3c1d8c17, dl));
3720 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3721 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3722 getF32Constant(DAG, 0x3d634a1d, dl));
3723 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3724 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3725 getF32Constant(DAG, 0x3e75fe14, dl));
3726 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3727 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3728 getF32Constant(DAG, 0x3f317234, dl));
3729 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3730 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3731 getF32Constant(DAG, 0x3f800000, dl));
3734 // Add the exponent into the result in integer domain.
3735 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3736 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3737 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3740 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3741 /// limited-precision mode.
3742 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3743 const TargetLowering &TLI) {
3744 if (Op.getValueType() == MVT::f32 &&
3745 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3747 // Put the exponent in the right bit position for later addition to the
3750 // #define LOG2OFe 1.4426950f
3751 // t0 = Op * LOG2OFe
3753 // TODO: What fast-math-flags should be set here?
3754 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3755 getF32Constant(DAG, 0x3fb8aa3b, dl));
3756 return getLimitedPrecisionExp2(t0, dl, DAG);
3759 // No special expansion.
3760 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3763 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3764 /// limited-precision mode.
3765 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3766 const TargetLowering &TLI) {
3768 // TODO: What fast-math-flags should be set on the floating-point nodes?
3770 if (Op.getValueType() == MVT::f32 &&
3771 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3772 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3774 // Scale the exponent by log(2) [0.69314718f].
3775 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3776 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3777 getF32Constant(DAG, 0x3f317218, dl));
3779 // Get the significand and build it into a floating-point number with
3781 SDValue X = GetSignificand(DAG, Op1, dl);
3783 SDValue LogOfMantissa;
3784 if (LimitFloatPrecision <= 6) {
3785 // For floating-point precision of 6:
3789 // (1.4034025f - 0.23903021f * x) * x;
3791 // error 0.0034276066, which is better than 8 bits
3792 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3793 getF32Constant(DAG, 0xbe74c456, dl));
3794 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3795 getF32Constant(DAG, 0x3fb3a2b1, dl));
3796 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3797 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3798 getF32Constant(DAG, 0x3f949a29, dl));
3799 } else if (LimitFloatPrecision <= 12) {
3800 // For floating-point precision of 12:
3806 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3808 // error 0.000061011436, which is 14 bits
3809 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3810 getF32Constant(DAG, 0xbd67b6d6, dl));
3811 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3812 getF32Constant(DAG, 0x3ee4f4b8, dl));
3813 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3814 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3815 getF32Constant(DAG, 0x3fbc278b, dl));
3816 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3817 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3818 getF32Constant(DAG, 0x40348e95, dl));
3819 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3820 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3821 getF32Constant(DAG, 0x3fdef31a, dl));
3822 } else { // LimitFloatPrecision <= 18
3823 // For floating-point precision of 18:
3831 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3833 // error 0.0000023660568, which is better than 18 bits
3834 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3835 getF32Constant(DAG, 0xbc91e5ac, dl));
3836 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3837 getF32Constant(DAG, 0x3e4350aa, dl));
3838 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3839 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3840 getF32Constant(DAG, 0x3f60d3e3, dl));
3841 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3842 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3843 getF32Constant(DAG, 0x4011cdf0, dl));
3844 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3845 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3846 getF32Constant(DAG, 0x406cfd1c, dl));
3847 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3848 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3849 getF32Constant(DAG, 0x408797cb, dl));
3850 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3851 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3852 getF32Constant(DAG, 0x4006dcab, dl));
3855 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3858 // No special expansion.
3859 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3862 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3863 /// limited-precision mode.
3864 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3865 const TargetLowering &TLI) {
3867 // TODO: What fast-math-flags should be set on the floating-point nodes?
3869 if (Op.getValueType() == MVT::f32 &&
3870 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3871 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3873 // Get the exponent.
3874 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3876 // Get the significand and build it into a floating-point number with
3878 SDValue X = GetSignificand(DAG, Op1, dl);
3880 // Different possible minimax approximations of significand in
3881 // floating-point for various degrees of accuracy over [1,2].
3882 SDValue Log2ofMantissa;
3883 if (LimitFloatPrecision <= 6) {
3884 // For floating-point precision of 6:
3886 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3888 // error 0.0049451742, which is more than 7 bits
3889 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3890 getF32Constant(DAG, 0xbeb08fe0, dl));
3891 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3892 getF32Constant(DAG, 0x40019463, dl));
3893 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3894 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3895 getF32Constant(DAG, 0x3fd6633d, dl));
3896 } else if (LimitFloatPrecision <= 12) {
3897 // For floating-point precision of 12:
3903 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3905 // error 0.0000876136000, which is better than 13 bits
3906 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3907 getF32Constant(DAG, 0xbda7262e, dl));
3908 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3909 getF32Constant(DAG, 0x3f25280b, dl));
3910 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3911 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3912 getF32Constant(DAG, 0x4007b923, dl));
3913 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3914 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3915 getF32Constant(DAG, 0x40823e2f, dl));
3916 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3917 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3918 getF32Constant(DAG, 0x4020d29c, dl));
3919 } else { // LimitFloatPrecision <= 18
3920 // For floating-point precision of 18:
3929 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3931 // error 0.0000018516, which is better than 18 bits
3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0xbcd2769e, dl));
3934 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3935 getF32Constant(DAG, 0x3e8ce0b9, dl));
3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3937 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x3fa22ae7, dl));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x40525723, dl));
3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3943 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3944 getF32Constant(DAG, 0x40aaf200, dl));
3945 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3946 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3947 getF32Constant(DAG, 0x40c39dad, dl));
3948 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3949 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3950 getF32Constant(DAG, 0x4042902c, dl));
3953 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3956 // No special expansion.
3957 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3960 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3961 /// limited-precision mode.
3962 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3963 const TargetLowering &TLI) {
3965 // TODO: What fast-math-flags should be set on the floating-point nodes?
3967 if (Op.getValueType() == MVT::f32 &&
3968 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3969 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3971 // Scale the exponent by log10(2) [0.30102999f].
3972 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3973 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3974 getF32Constant(DAG, 0x3e9a209a, dl));
3976 // Get the significand and build it into a floating-point number with
3978 SDValue X = GetSignificand(DAG, Op1, dl);
3980 SDValue Log10ofMantissa;
3981 if (LimitFloatPrecision <= 6) {
3982 // For floating-point precision of 6:
3984 // Log10ofMantissa =
3986 // (0.60948995f - 0.10380950f * x) * x;
3988 // error 0.0014886165, which is 6 bits
3989 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3990 getF32Constant(DAG, 0xbdd49a13, dl));
3991 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3992 getF32Constant(DAG, 0x3f1c0789, dl));
3993 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3994 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3995 getF32Constant(DAG, 0x3f011300, dl));
3996 } else if (LimitFloatPrecision <= 12) {
3997 // For floating-point precision of 12:
3999 // Log10ofMantissa =
4002 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4004 // error 0.00019228036, which is better than 12 bits
4005 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4006 getF32Constant(DAG, 0x3d431f31, dl));
4007 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4008 getF32Constant(DAG, 0x3ea21fb2, dl));
4009 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4010 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4011 getF32Constant(DAG, 0x3f6ae232, dl));
4012 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4013 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4014 getF32Constant(DAG, 0x3f25f7c3, dl));
4015 } else { // LimitFloatPrecision <= 18
4016 // For floating-point precision of 18:
4018 // Log10ofMantissa =
4023 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4025 // error 0.0000037995730, which is better than 18 bits
4026 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4027 getF32Constant(DAG, 0x3c5d51ce, dl));
4028 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4029 getF32Constant(DAG, 0x3e00685a, dl));
4030 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4031 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4032 getF32Constant(DAG, 0x3efb6798, dl));
4033 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4034 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4035 getF32Constant(DAG, 0x3f88d192, dl));
4036 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4037 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4038 getF32Constant(DAG, 0x3fc4316c, dl));
4039 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4040 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4041 getF32Constant(DAG, 0x3f57ce70, dl));
4044 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4047 // No special expansion.
4048 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4051 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4052 /// limited-precision mode.
4053 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4054 const TargetLowering &TLI) {
4055 if (Op.getValueType() == MVT::f32 &&
4056 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4057 return getLimitedPrecisionExp2(Op, dl, DAG);
4059 // No special expansion.
4060 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4063 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4064 /// limited-precision mode with x == 10.0f.
4065 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4066 SelectionDAG &DAG, const TargetLowering &TLI) {
4067 bool IsExp10 = false;
4068 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4069 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4070 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4072 IsExp10 = LHSC->isExactlyValue(Ten);
4076 // TODO: What fast-math-flags should be set on the FMUL node?
4078 // Put the exponent in the right bit position for later addition to the
4081 // #define LOG2OF10 3.3219281f
4082 // t0 = Op * LOG2OF10;
4083 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4084 getF32Constant(DAG, 0x40549a78, dl));
4085 return getLimitedPrecisionExp2(t0, dl, DAG);
4088 // No special expansion.
4089 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4093 /// ExpandPowI - Expand a llvm.powi intrinsic.
4094 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4095 SelectionDAG &DAG) {
4096 // If RHS is a constant, we can expand this out to a multiplication tree,
4097 // otherwise we end up lowering to a call to __powidf2 (for example). When
4098 // optimizing for size, we only want to do this if the expansion would produce
4099 // a small number of multiplies, otherwise we do the full expansion.
4100 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4101 // Get the exponent as a positive value.
4102 unsigned Val = RHSC->getSExtValue();
4103 if ((int)Val < 0) Val = -Val;
4105 // powi(x, 0) -> 1.0
4107 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4109 const Function *F = DAG.getMachineFunction().getFunction();
4110 if (!F->optForSize() ||
4111 // If optimizing for size, don't insert too many multiplies.
4112 // This inserts up to 5 multiplies.
4113 countPopulation(Val) + Log2_32(Val) < 7) {
4114 // We use the simple binary decomposition method to generate the multiply
4115 // sequence. There are more optimal ways to do this (for example,
4116 // powi(x,15) generates one more multiply than it should), but this has
4117 // the benefit of being both really simple and much better than a libcall.
4118 SDValue Res; // Logically starts equal to 1.0
4119 SDValue CurSquare = LHS;
4120 // TODO: Intrinsics should have fast-math-flags that propagate to these
4125 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4127 Res = CurSquare; // 1.0*CurSquare.
4130 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4131 CurSquare, CurSquare);
4135 // If the original was negative, invert the result, producing 1/(x*x*x).
4136 if (RHSC->getSExtValue() < 0)
4137 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4138 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4143 // Otherwise, expand to a libcall.
4144 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4147 // getTruncatedArgReg - Find underlying register used for an truncated
4149 static unsigned getTruncatedArgReg(const SDValue &N) {
4150 if (N.getOpcode() != ISD::TRUNCATE)
4153 const SDValue &Ext = N.getOperand(0);
4154 if (Ext.getOpcode() == ISD::AssertZext ||
4155 Ext.getOpcode() == ISD::AssertSext) {
4156 const SDValue &CFR = Ext.getOperand(0);
4157 if (CFR.getOpcode() == ISD::CopyFromReg)
4158 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4159 if (CFR.getOpcode() == ISD::TRUNCATE)
4160 return getTruncatedArgReg(CFR);
4165 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4166 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4167 /// At the end of instruction selection, they will be inserted to the entry BB.
4168 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4169 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4170 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4171 const Argument *Arg = dyn_cast<Argument>(V);
4175 MachineFunction &MF = DAG.getMachineFunction();
4176 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4178 // Ignore inlined function arguments here.
4180 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4181 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4184 Optional<MachineOperand> Op;
4185 // Some arguments' frame index is recorded during argument lowering.
4186 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4187 Op = MachineOperand::CreateFI(FI);
4189 if (!Op && N.getNode()) {
4191 if (N.getOpcode() == ISD::CopyFromReg)
4192 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4194 Reg = getTruncatedArgReg(N);
4195 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4196 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4197 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4202 Op = MachineOperand::CreateReg(Reg, false);
4206 // Check if ValueMap has reg number.
4207 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4208 if (VMI != FuncInfo.ValueMap.end())
4209 Op = MachineOperand::CreateReg(VMI->second, false);
4212 if (!Op && N.getNode())
4213 // Check if frame index is available.
4214 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4215 if (FrameIndexSDNode *FINode =
4216 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4217 Op = MachineOperand::CreateFI(FINode->getIndex());
4222 assert(Variable->isValidLocationForIntrinsic(DL) &&
4223 "Expected inlined-at fields to agree");
4225 FuncInfo.ArgDbgValues.push_back(
4226 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4227 Op->getReg(), Offset, Variable, Expr));
4229 FuncInfo.ArgDbgValues.push_back(
4230 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4233 .addMetadata(Variable)
4234 .addMetadata(Expr));
4239 // VisualStudio defines setjmp as _setjmp
4240 #if defined(_MSC_VER) && defined(setjmp) && \
4241 !defined(setjmp_undefined_for_msvc)
4242 # pragma push_macro("setjmp")
4244 # define setjmp_undefined_for_msvc
4247 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4248 /// we want to emit this as a call to a named external function, return the name
4249 /// otherwise lower it and return null.
4251 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4253 SDLoc sdl = getCurSDLoc();
4254 DebugLoc dl = getCurDebugLoc();
4257 switch (Intrinsic) {
4259 // By default, turn this into a target intrinsic node.
4260 visitTargetIntrinsic(I, Intrinsic);
4262 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4263 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4264 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4265 case Intrinsic::returnaddress:
4266 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4267 TLI.getPointerTy(DAG.getDataLayout()),
4268 getValue(I.getArgOperand(0))));
4270 case Intrinsic::frameaddress:
4271 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4272 TLI.getPointerTy(DAG.getDataLayout()),
4273 getValue(I.getArgOperand(0))));
4275 case Intrinsic::read_register: {
4276 Value *Reg = I.getArgOperand(0);
4277 SDValue Chain = getRoot();
4279 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4280 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4281 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4282 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4284 DAG.setRoot(Res.getValue(1));
4287 case Intrinsic::write_register: {
4288 Value *Reg = I.getArgOperand(0);
4289 Value *RegValue = I.getArgOperand(1);
4290 SDValue Chain = getRoot();
4292 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4293 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4294 RegName, getValue(RegValue)));
4297 case Intrinsic::setjmp:
4298 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4299 case Intrinsic::longjmp:
4300 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4301 case Intrinsic::memcpy: {
4302 // FIXME: this definition of "user defined address space" is x86-specific
4303 // Assert for address < 256 since we support only user defined address
4305 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4307 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4309 "Unknown address space");
4310 SDValue Op1 = getValue(I.getArgOperand(0));
4311 SDValue Op2 = getValue(I.getArgOperand(1));
4312 SDValue Op3 = getValue(I.getArgOperand(2));
4313 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4315 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4316 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4317 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4318 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4320 MachinePointerInfo(I.getArgOperand(0)),
4321 MachinePointerInfo(I.getArgOperand(1)));
4322 updateDAGForMaybeTailCall(MC);
4325 case Intrinsic::memset: {
4326 // FIXME: this definition of "user defined address space" is x86-specific
4327 // Assert for address < 256 since we support only user defined address
4329 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4331 "Unknown address space");
4332 SDValue Op1 = getValue(I.getArgOperand(0));
4333 SDValue Op2 = getValue(I.getArgOperand(1));
4334 SDValue Op3 = getValue(I.getArgOperand(2));
4335 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4337 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4338 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4339 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4340 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4341 isTC, MachinePointerInfo(I.getArgOperand(0)));
4342 updateDAGForMaybeTailCall(MS);
4345 case Intrinsic::memmove: {
4346 // FIXME: this definition of "user defined address space" is x86-specific
4347 // Assert for address < 256 since we support only user defined address
4349 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4351 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4353 "Unknown address space");
4354 SDValue Op1 = getValue(I.getArgOperand(0));
4355 SDValue Op2 = getValue(I.getArgOperand(1));
4356 SDValue Op3 = getValue(I.getArgOperand(2));
4357 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4359 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4360 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4361 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4362 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4363 isTC, MachinePointerInfo(I.getArgOperand(0)),
4364 MachinePointerInfo(I.getArgOperand(1)));
4365 updateDAGForMaybeTailCall(MM);
4368 case Intrinsic::dbg_declare: {
4369 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4370 DILocalVariable *Variable = DI.getVariable();
4371 DIExpression *Expression = DI.getExpression();
4372 const Value *Address = DI.getAddress();
4373 assert(Variable && "Missing variable");
4375 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4379 // Check if address has undef value.
4380 if (isa<UndefValue>(Address) ||
4381 (Address->use_empty() && !isa<Argument>(Address))) {
4382 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4386 SDValue &N = NodeMap[Address];
4387 if (!N.getNode() && isa<Argument>(Address))
4388 // Check unused arguments map.
4389 N = UnusedArgNodeMap[Address];
4392 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4393 Address = BCI->getOperand(0);
4394 // Parameters are handled specially.
4395 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4397 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4399 if (isParameter && !AI) {
4400 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4402 // Byval parameter. We have a frame index at this point.
4403 SDV = DAG.getFrameIndexDbgValue(
4404 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4406 // Address is an argument, so try to emit its dbg value using
4407 // virtual register info from the FuncInfo.ValueMap.
4408 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4413 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4414 true, 0, dl, SDNodeOrder);
4416 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4418 // If Address is an argument then try to emit its dbg value using
4419 // virtual register info from the FuncInfo.ValueMap.
4420 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4422 // If variable is pinned by a alloca in dominating bb then
4423 // use StaticAllocaMap.
4424 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4425 if (AI->getParent() != DI.getParent()) {
4426 DenseMap<const AllocaInst*, int>::iterator SI =
4427 FuncInfo.StaticAllocaMap.find(AI);
4428 if (SI != FuncInfo.StaticAllocaMap.end()) {
4429 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4430 0, dl, SDNodeOrder);
4431 DAG.AddDbgValue(SDV, nullptr, false);
4436 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4441 case Intrinsic::dbg_value: {
4442 const DbgValueInst &DI = cast<DbgValueInst>(I);
4443 assert(DI.getVariable() && "Missing variable");
4445 DILocalVariable *Variable = DI.getVariable();
4446 DIExpression *Expression = DI.getExpression();
4447 uint64_t Offset = DI.getOffset();
4448 const Value *V = DI.getValue();
4453 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4454 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4456 DAG.AddDbgValue(SDV, nullptr, false);
4458 // Do not use getValue() in here; we don't want to generate code at
4459 // this point if it hasn't been done yet.
4460 SDValue N = NodeMap[V];
4461 if (!N.getNode() && isa<Argument>(V))
4462 // Check unused arguments map.
4463 N = UnusedArgNodeMap[V];
4465 // A dbg.value for an alloca is always indirect.
4466 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4467 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4469 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4470 IsIndirect, Offset, dl, SDNodeOrder);
4471 DAG.AddDbgValue(SDV, N.getNode(), false);
4473 } else if (!V->use_empty() ) {
4474 // Do not call getValue(V) yet, as we don't want to generate code.
4475 // Remember it for later.
4476 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4477 DanglingDebugInfoMap[V] = DDI;
4479 // We may expand this to cover more cases. One case where we have no
4480 // data available is an unreferenced parameter.
4481 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4485 // Build a debug info table entry.
4486 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4487 V = BCI->getOperand(0);
4488 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4489 // Don't handle byval struct arguments or VLAs, for example.
4491 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4492 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4495 DenseMap<const AllocaInst*, int>::iterator SI =
4496 FuncInfo.StaticAllocaMap.find(AI);
4497 if (SI == FuncInfo.StaticAllocaMap.end())
4498 return nullptr; // VLAs.
4502 case Intrinsic::eh_typeid_for: {
4503 // Find the type id for the given typeinfo.
4504 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4505 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4506 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4511 case Intrinsic::eh_return_i32:
4512 case Intrinsic::eh_return_i64:
4513 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4514 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4517 getValue(I.getArgOperand(0)),
4518 getValue(I.getArgOperand(1))));
4520 case Intrinsic::eh_unwind_init:
4521 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4523 case Intrinsic::eh_dwarf_cfa: {
4524 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4525 TLI.getPointerTy(DAG.getDataLayout()));
4526 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4527 CfaArg.getValueType(),
4528 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4529 CfaArg.getValueType()),
4531 SDValue FA = DAG.getNode(
4532 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4533 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4534 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4538 case Intrinsic::eh_sjlj_callsite: {
4539 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4540 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4541 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4542 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4544 MMI.setCurrentCallSite(CI->getZExtValue());
4547 case Intrinsic::eh_sjlj_functioncontext: {
4548 // Get and store the index of the function context.
4549 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4551 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4552 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4553 MFI->setFunctionContextIndex(FI);
4556 case Intrinsic::eh_sjlj_setjmp: {
4559 Ops[1] = getValue(I.getArgOperand(0));
4560 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4561 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4562 setValue(&I, Op.getValue(0));
4563 DAG.setRoot(Op.getValue(1));
4566 case Intrinsic::eh_sjlj_longjmp: {
4567 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4568 getRoot(), getValue(I.getArgOperand(0))));
4571 case Intrinsic::eh_sjlj_setup_dispatch: {
4572 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4577 case Intrinsic::masked_gather:
4578 visitMaskedGather(I);
4580 case Intrinsic::masked_load:
4583 case Intrinsic::masked_scatter:
4584 visitMaskedScatter(I);
4586 case Intrinsic::masked_store:
4587 visitMaskedStore(I);
4589 case Intrinsic::x86_mmx_pslli_w:
4590 case Intrinsic::x86_mmx_pslli_d:
4591 case Intrinsic::x86_mmx_pslli_q:
4592 case Intrinsic::x86_mmx_psrli_w:
4593 case Intrinsic::x86_mmx_psrli_d:
4594 case Intrinsic::x86_mmx_psrli_q:
4595 case Intrinsic::x86_mmx_psrai_w:
4596 case Intrinsic::x86_mmx_psrai_d: {
4597 SDValue ShAmt = getValue(I.getArgOperand(1));
4598 if (isa<ConstantSDNode>(ShAmt)) {
4599 visitTargetIntrinsic(I, Intrinsic);
4602 unsigned NewIntrinsic = 0;
4603 EVT ShAmtVT = MVT::v2i32;
4604 switch (Intrinsic) {
4605 case Intrinsic::x86_mmx_pslli_w:
4606 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4608 case Intrinsic::x86_mmx_pslli_d:
4609 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4611 case Intrinsic::x86_mmx_pslli_q:
4612 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4614 case Intrinsic::x86_mmx_psrli_w:
4615 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4617 case Intrinsic::x86_mmx_psrli_d:
4618 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4620 case Intrinsic::x86_mmx_psrli_q:
4621 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4623 case Intrinsic::x86_mmx_psrai_w:
4624 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4626 case Intrinsic::x86_mmx_psrai_d:
4627 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4629 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4632 // The vector shift intrinsics with scalars uses 32b shift amounts but
4633 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4635 // We must do this early because v2i32 is not a legal type.
4638 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4639 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4640 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4641 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4642 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4643 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4644 getValue(I.getArgOperand(0)), ShAmt);
4648 case Intrinsic::convertff:
4649 case Intrinsic::convertfsi:
4650 case Intrinsic::convertfui:
4651 case Intrinsic::convertsif:
4652 case Intrinsic::convertuif:
4653 case Intrinsic::convertss:
4654 case Intrinsic::convertsu:
4655 case Intrinsic::convertus:
4656 case Intrinsic::convertuu: {
4657 ISD::CvtCode Code = ISD::CVT_INVALID;
4658 switch (Intrinsic) {
4659 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4660 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4661 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4662 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4663 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4664 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4665 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4666 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4667 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4668 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4670 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4671 const Value *Op1 = I.getArgOperand(0);
4672 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4673 DAG.getValueType(DestVT),
4674 DAG.getValueType(getValue(Op1).getValueType()),
4675 getValue(I.getArgOperand(1)),
4676 getValue(I.getArgOperand(2)),
4681 case Intrinsic::powi:
4682 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4683 getValue(I.getArgOperand(1)), DAG));
4685 case Intrinsic::log:
4686 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4688 case Intrinsic::log2:
4689 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4691 case Intrinsic::log10:
4692 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4694 case Intrinsic::exp:
4695 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4697 case Intrinsic::exp2:
4698 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4700 case Intrinsic::pow:
4701 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4702 getValue(I.getArgOperand(1)), DAG, TLI));
4704 case Intrinsic::sqrt:
4705 case Intrinsic::fabs:
4706 case Intrinsic::sin:
4707 case Intrinsic::cos:
4708 case Intrinsic::floor:
4709 case Intrinsic::ceil:
4710 case Intrinsic::trunc:
4711 case Intrinsic::rint:
4712 case Intrinsic::nearbyint:
4713 case Intrinsic::round: {
4715 switch (Intrinsic) {
4716 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4717 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4718 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4719 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4720 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4721 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4722 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4723 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4724 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4725 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4726 case Intrinsic::round: Opcode = ISD::FROUND; break;
4729 setValue(&I, DAG.getNode(Opcode, sdl,
4730 getValue(I.getArgOperand(0)).getValueType(),
4731 getValue(I.getArgOperand(0))));
4734 case Intrinsic::minnum:
4735 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4736 getValue(I.getArgOperand(0)).getValueType(),
4737 getValue(I.getArgOperand(0)),
4738 getValue(I.getArgOperand(1))));
4740 case Intrinsic::maxnum:
4741 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4742 getValue(I.getArgOperand(0)).getValueType(),
4743 getValue(I.getArgOperand(0)),
4744 getValue(I.getArgOperand(1))));
4746 case Intrinsic::copysign:
4747 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4748 getValue(I.getArgOperand(0)).getValueType(),
4749 getValue(I.getArgOperand(0)),
4750 getValue(I.getArgOperand(1))));
4752 case Intrinsic::fma:
4753 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4754 getValue(I.getArgOperand(0)).getValueType(),
4755 getValue(I.getArgOperand(0)),
4756 getValue(I.getArgOperand(1)),
4757 getValue(I.getArgOperand(2))));
4759 case Intrinsic::fmuladd: {
4760 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4761 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4762 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4763 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4764 getValue(I.getArgOperand(0)).getValueType(),
4765 getValue(I.getArgOperand(0)),
4766 getValue(I.getArgOperand(1)),
4767 getValue(I.getArgOperand(2))));
4769 // TODO: Intrinsic calls should have fast-math-flags.
4770 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4771 getValue(I.getArgOperand(0)).getValueType(),
4772 getValue(I.getArgOperand(0)),
4773 getValue(I.getArgOperand(1)));
4774 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4775 getValue(I.getArgOperand(0)).getValueType(),
4777 getValue(I.getArgOperand(2)));
4782 case Intrinsic::convert_to_fp16:
4783 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4784 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4785 getValue(I.getArgOperand(0)),
4786 DAG.getTargetConstant(0, sdl,
4789 case Intrinsic::convert_from_fp16:
4790 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4791 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4792 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4793 getValue(I.getArgOperand(0)))));
4795 case Intrinsic::pcmarker: {
4796 SDValue Tmp = getValue(I.getArgOperand(0));
4797 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4800 case Intrinsic::readcyclecounter: {
4801 SDValue Op = getRoot();
4802 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4803 DAG.getVTList(MVT::i64, MVT::Other), Op);
4805 DAG.setRoot(Res.getValue(1));
4808 case Intrinsic::bswap:
4809 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4810 getValue(I.getArgOperand(0)).getValueType(),
4811 getValue(I.getArgOperand(0))));
4813 case Intrinsic::uabsdiff:
4814 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4815 getValue(I.getArgOperand(0)).getValueType(),
4816 getValue(I.getArgOperand(0)),
4817 getValue(I.getArgOperand(1))));
4819 case Intrinsic::sabsdiff:
4820 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4821 getValue(I.getArgOperand(0)).getValueType(),
4822 getValue(I.getArgOperand(0)),
4823 getValue(I.getArgOperand(1))));
4825 case Intrinsic::cttz: {
4826 SDValue Arg = getValue(I.getArgOperand(0));
4827 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4828 EVT Ty = Arg.getValueType();
4829 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4833 case Intrinsic::ctlz: {
4834 SDValue Arg = getValue(I.getArgOperand(0));
4835 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4836 EVT Ty = Arg.getValueType();
4837 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4841 case Intrinsic::ctpop: {
4842 SDValue Arg = getValue(I.getArgOperand(0));
4843 EVT Ty = Arg.getValueType();
4844 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4847 case Intrinsic::stacksave: {
4848 SDValue Op = getRoot();
4850 ISD::STACKSAVE, sdl,
4851 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4853 DAG.setRoot(Res.getValue(1));
4856 case Intrinsic::stackrestore: {
4857 Res = getValue(I.getArgOperand(0));
4858 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4861 case Intrinsic::stackprotector: {
4862 // Emit code into the DAG to store the stack guard onto the stack.
4863 MachineFunction &MF = DAG.getMachineFunction();
4864 MachineFrameInfo *MFI = MF.getFrameInfo();
4865 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4866 SDValue Src, Chain = getRoot();
4867 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4868 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4870 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4871 // global variable __stack_chk_guard.
4873 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4874 if (BC->getOpcode() == Instruction::BitCast)
4875 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4877 if (GV && TLI.useLoadStackGuardNode()) {
4878 // Emit a LOAD_STACK_GUARD node.
4879 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4881 MachinePointerInfo MPInfo(GV);
4882 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4883 unsigned Flags = MachineMemOperand::MOLoad |
4884 MachineMemOperand::MOInvariant;
4885 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4886 PtrTy.getSizeInBits() / 8,
4887 DAG.getEVTAlignment(PtrTy));
4888 Node->setMemRefs(MemRefs, MemRefs + 1);
4890 // Copy the guard value to a virtual register so that it can be
4891 // retrieved in the epilogue.
4892 Src = SDValue(Node, 0);
4893 const TargetRegisterClass *RC =
4894 TLI.getRegClassFor(Src.getSimpleValueType());
4895 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4897 SPDescriptor.setGuardReg(Reg);
4898 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4900 Src = getValue(I.getArgOperand(0)); // The guard's value.
4903 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4905 int FI = FuncInfo.StaticAllocaMap[Slot];
4906 MFI->setStackProtectorIndex(FI);
4908 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4910 // Store the stack protector onto the stack.
4911 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4912 DAG.getMachineFunction(), FI),
4918 case Intrinsic::objectsize: {
4919 // If we don't know by now, we're never going to know.
4920 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4922 assert(CI && "Non-constant type in __builtin_object_size?");
4924 SDValue Arg = getValue(I.getCalledValue());
4925 EVT Ty = Arg.getValueType();
4928 Res = DAG.getConstant(-1ULL, sdl, Ty);
4930 Res = DAG.getConstant(0, sdl, Ty);
4935 case Intrinsic::annotation:
4936 case Intrinsic::ptr_annotation:
4937 // Drop the intrinsic, but forward the value
4938 setValue(&I, getValue(I.getOperand(0)));
4940 case Intrinsic::assume:
4941 case Intrinsic::var_annotation:
4942 // Discard annotate attributes and assumptions
4945 case Intrinsic::init_trampoline: {
4946 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4950 Ops[1] = getValue(I.getArgOperand(0));
4951 Ops[2] = getValue(I.getArgOperand(1));
4952 Ops[3] = getValue(I.getArgOperand(2));
4953 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4954 Ops[5] = DAG.getSrcValue(F);
4956 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4961 case Intrinsic::adjust_trampoline: {
4962 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4963 TLI.getPointerTy(DAG.getDataLayout()),
4964 getValue(I.getArgOperand(0))));
4967 case Intrinsic::gcroot:
4969 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4970 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4972 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4973 GFI->addStackRoot(FI->getIndex(), TypeMap);
4976 case Intrinsic::gcread:
4977 case Intrinsic::gcwrite:
4978 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4979 case Intrinsic::flt_rounds:
4980 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4983 case Intrinsic::expect: {
4984 // Just replace __builtin_expect(exp, c) with EXP.
4985 setValue(&I, getValue(I.getArgOperand(0)));
4989 case Intrinsic::debugtrap:
4990 case Intrinsic::trap: {
4991 StringRef TrapFuncName =
4993 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4994 .getValueAsString();
4995 if (TrapFuncName.empty()) {
4996 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4997 ISD::TRAP : ISD::DEBUGTRAP;
4998 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5001 TargetLowering::ArgListTy Args;
5003 TargetLowering::CallLoweringInfo CLI(DAG);
5004 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5005 CallingConv::C, I.getType(),
5006 DAG.getExternalSymbol(TrapFuncName.data(),
5007 TLI.getPointerTy(DAG.getDataLayout())),
5008 std::move(Args), 0);
5010 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5011 DAG.setRoot(Result.second);
5015 case Intrinsic::uadd_with_overflow:
5016 case Intrinsic::sadd_with_overflow:
5017 case Intrinsic::usub_with_overflow:
5018 case Intrinsic::ssub_with_overflow:
5019 case Intrinsic::umul_with_overflow:
5020 case Intrinsic::smul_with_overflow: {
5022 switch (Intrinsic) {
5023 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5024 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5025 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5026 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5027 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5028 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5029 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5031 SDValue Op1 = getValue(I.getArgOperand(0));
5032 SDValue Op2 = getValue(I.getArgOperand(1));
5034 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5035 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5038 case Intrinsic::prefetch: {
5040 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5042 Ops[1] = getValue(I.getArgOperand(0));
5043 Ops[2] = getValue(I.getArgOperand(1));
5044 Ops[3] = getValue(I.getArgOperand(2));
5045 Ops[4] = getValue(I.getArgOperand(3));
5046 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5047 DAG.getVTList(MVT::Other), Ops,
5048 EVT::getIntegerVT(*Context, 8),
5049 MachinePointerInfo(I.getArgOperand(0)),
5051 false, /* volatile */
5053 rw==1)); /* write */
5056 case Intrinsic::lifetime_start:
5057 case Intrinsic::lifetime_end: {
5058 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5059 // Stack coloring is not enabled in O0, discard region information.
5060 if (TM.getOptLevel() == CodeGenOpt::None)
5063 SmallVector<Value *, 4> Allocas;
5064 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5066 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5067 E = Allocas.end(); Object != E; ++Object) {
5068 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5070 // Could not find an Alloca.
5071 if (!LifetimeObject)
5074 // First check that the Alloca is static, otherwise it won't have a
5075 // valid frame index.
5076 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5077 if (SI == FuncInfo.StaticAllocaMap.end())
5080 int FI = SI->second;
5085 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5086 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5088 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5093 case Intrinsic::invariant_start:
5094 // Discard region information.
5095 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5097 case Intrinsic::invariant_end:
5098 // Discard region information.
5100 case Intrinsic::stackprotectorcheck: {
5101 // Do not actually emit anything for this basic block. Instead we initialize
5102 // the stack protector descriptor and export the guard variable so we can
5103 // access it in FinishBasicBlock.
5104 const BasicBlock *BB = I.getParent();
5105 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5106 ExportFromCurrentBlock(SPDescriptor.getGuard());
5108 // Flush our exports since we are going to process a terminator.
5109 (void)getControlRoot();
5112 case Intrinsic::clear_cache:
5113 return TLI.getClearCacheBuiltinName();
5114 case Intrinsic::eh_actions:
5115 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5117 case Intrinsic::donothing:
5120 case Intrinsic::experimental_stackmap: {
5124 case Intrinsic::experimental_patchpoint_void:
5125 case Intrinsic::experimental_patchpoint_i64: {
5126 visitPatchpoint(&I);
5129 case Intrinsic::experimental_gc_statepoint: {
5133 case Intrinsic::experimental_gc_result_int:
5134 case Intrinsic::experimental_gc_result_float:
5135 case Intrinsic::experimental_gc_result_ptr:
5136 case Intrinsic::experimental_gc_result: {
5140 case Intrinsic::experimental_gc_relocate: {
5144 case Intrinsic::instrprof_increment:
5145 llvm_unreachable("instrprof failed to lower an increment");
5147 case Intrinsic::localescape: {
5148 MachineFunction &MF = DAG.getMachineFunction();
5149 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5151 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5152 // is the same on all targets.
5153 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5154 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5155 if (isa<ConstantPointerNull>(Arg))
5156 continue; // Skip null pointers. They represent a hole in index space.
5157 AllocaInst *Slot = cast<AllocaInst>(Arg);
5158 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5159 "can only escape static allocas");
5160 int FI = FuncInfo.StaticAllocaMap[Slot];
5161 MCSymbol *FrameAllocSym =
5162 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5163 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5165 TII->get(TargetOpcode::LOCAL_ESCAPE))
5166 .addSym(FrameAllocSym)
5173 case Intrinsic::localrecover: {
5174 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5175 MachineFunction &MF = DAG.getMachineFunction();
5176 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5178 // Get the symbol that defines the frame offset.
5179 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5180 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5181 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5182 MCSymbol *FrameAllocSym =
5183 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5184 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5186 // Create a MCSymbol for the label to avoid any target lowering
5187 // that would make this PC relative.
5188 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5190 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5192 // Add the offset to the FP.
5193 Value *FP = I.getArgOperand(1);
5194 SDValue FPVal = getValue(FP);
5195 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5200 case Intrinsic::eh_begincatch:
5201 case Intrinsic::eh_endcatch:
5202 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5203 case Intrinsic::eh_exceptioncode: {
5204 unsigned Reg = TLI.getExceptionPointerRegister();
5205 assert(Reg && "cannot get exception code on this platform");
5206 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5207 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5208 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5209 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5211 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5212 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5219 std::pair<SDValue, SDValue>
5220 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5221 const BasicBlock *EHPadBB) {
5222 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5223 MCSymbol *BeginLabel = nullptr;
5226 // Insert a label before the invoke call to mark the try range. This can be
5227 // used to detect deletion of the invoke via the MachineModuleInfo.
5228 BeginLabel = MMI.getContext().createTempSymbol();
5230 // For SjLj, keep track of which landing pads go with which invokes
5231 // so as to maintain the ordering of pads in the LSDA.
5232 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5233 if (CallSiteIndex) {
5234 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5235 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5237 // Now that the call site is handled, stop tracking it.
5238 MMI.setCurrentCallSite(0);
5241 // Both PendingLoads and PendingExports must be flushed here;
5242 // this call might not return.
5244 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5246 CLI.setChain(getRoot());
5248 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5249 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5251 assert((CLI.IsTailCall || Result.second.getNode()) &&
5252 "Non-null chain expected with non-tail call!");
5253 assert((Result.second.getNode() || !Result.first.getNode()) &&
5254 "Null value expected with tail call!");
5256 if (!Result.second.getNode()) {
5257 // As a special case, a null chain means that a tail call has been emitted
5258 // and the DAG root is already updated.
5261 // Since there's no actual continuation from this block, nothing can be
5262 // relying on us setting vregs for them.
5263 PendingExports.clear();
5265 DAG.setRoot(Result.second);
5269 // Insert a label at the end of the invoke call to mark the try range. This
5270 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5271 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5272 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5274 // Inform MachineModuleInfo of range.
5275 if (MMI.hasEHFunclets()) {
5276 WinEHFuncInfo &EHInfo =
5277 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5278 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5280 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5287 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5289 const BasicBlock *EHPadBB) {
5290 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5291 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5292 Type *RetTy = FTy->getReturnType();
5294 TargetLowering::ArgListTy Args;
5295 TargetLowering::ArgListEntry Entry;
5296 Args.reserve(CS.arg_size());
5298 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5300 const Value *V = *i;
5303 if (V->getType()->isEmptyTy())
5306 SDValue ArgNode = getValue(V);
5307 Entry.Node = ArgNode; Entry.Ty = V->getType();
5309 // Skip the first return-type Attribute to get to params.
5310 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5311 Args.push_back(Entry);
5313 // If we have an explicit sret argument that is an Instruction, (i.e., it
5314 // might point to function-local memory), we can't meaningfully tail-call.
5315 if (Entry.isSRet && isa<Instruction>(V))
5319 // Check if target-independent constraints permit a tail call here.
5320 // Target-dependent constraints are checked within TLI->LowerCallTo.
5321 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5324 TargetLowering::CallLoweringInfo CLI(DAG);
5325 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5326 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5327 .setTailCall(isTailCall);
5328 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5330 if (Result.first.getNode())
5331 setValue(CS.getInstruction(), Result.first);
5334 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5335 /// value is equal or not-equal to zero.
5336 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5337 for (const User *U : V->users()) {
5338 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5339 if (IC->isEquality())
5340 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5341 if (C->isNullValue())
5343 // Unknown instruction.
5349 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5351 SelectionDAGBuilder &Builder) {
5353 // Check to see if this load can be trivially constant folded, e.g. if the
5354 // input is from a string literal.
5355 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5356 // Cast pointer to the type we really want to load.
5357 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5358 PointerType::getUnqual(LoadTy));
5360 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5361 const_cast<Constant *>(LoadInput), *Builder.DL))
5362 return Builder.getValue(LoadCst);
5365 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5366 // still constant memory, the input chain can be the entry node.
5368 bool ConstantMemory = false;
5370 // Do not serialize (non-volatile) loads of constant memory with anything.
5371 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5372 Root = Builder.DAG.getEntryNode();
5373 ConstantMemory = true;
5375 // Do not serialize non-volatile loads against each other.
5376 Root = Builder.DAG.getRoot();
5379 SDValue Ptr = Builder.getValue(PtrVal);
5380 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5381 Ptr, MachinePointerInfo(PtrVal),
5383 false /*nontemporal*/,
5384 false /*isinvariant*/, 1 /* align=1 */);
5386 if (!ConstantMemory)
5387 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5391 /// processIntegerCallValue - Record the value for an instruction that
5392 /// produces an integer result, converting the type where necessary.
5393 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5396 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5399 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5401 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5402 setValue(&I, Value);
5405 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5406 /// If so, return true and lower it, otherwise return false and it will be
5407 /// lowered like a normal call.
5408 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5409 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5410 if (I.getNumArgOperands() != 3)
5413 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5414 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5415 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5416 !I.getType()->isIntegerTy())
5419 const Value *Size = I.getArgOperand(2);
5420 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5421 if (CSize && CSize->getZExtValue() == 0) {
5422 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5424 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5428 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5429 std::pair<SDValue, SDValue> Res =
5430 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5431 getValue(LHS), getValue(RHS), getValue(Size),
5432 MachinePointerInfo(LHS),
5433 MachinePointerInfo(RHS));
5434 if (Res.first.getNode()) {
5435 processIntegerCallValue(I, Res.first, true);
5436 PendingLoads.push_back(Res.second);
5440 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5441 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5442 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5443 bool ActuallyDoIt = true;
5446 switch (CSize->getZExtValue()) {
5448 LoadVT = MVT::Other;
5450 ActuallyDoIt = false;
5454 LoadTy = Type::getInt16Ty(CSize->getContext());
5458 LoadTy = Type::getInt32Ty(CSize->getContext());
5462 LoadTy = Type::getInt64Ty(CSize->getContext());
5466 LoadVT = MVT::v4i32;
5467 LoadTy = Type::getInt32Ty(CSize->getContext());
5468 LoadTy = VectorType::get(LoadTy, 4);
5473 // This turns into unaligned loads. We only do this if the target natively
5474 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5475 // we'll only produce a small number of byte loads.
5477 // Require that we can find a legal MVT, and only do this if the target
5478 // supports unaligned loads of that type. Expanding into byte loads would
5480 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5481 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5482 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5483 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5484 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5485 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5486 // TODO: Check alignment of src and dest ptrs.
5487 if (!TLI.isTypeLegal(LoadVT) ||
5488 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5489 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5490 ActuallyDoIt = false;
5494 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5495 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5497 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5499 processIntegerCallValue(I, Res, false);
5508 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5509 /// form. If so, return true and lower it, otherwise return false and it
5510 /// will be lowered like a normal call.
5511 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5512 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5513 if (I.getNumArgOperands() != 3)
5516 const Value *Src = I.getArgOperand(0);
5517 const Value *Char = I.getArgOperand(1);
5518 const Value *Length = I.getArgOperand(2);
5519 if (!Src->getType()->isPointerTy() ||
5520 !Char->getType()->isIntegerTy() ||
5521 !Length->getType()->isIntegerTy() ||
5522 !I.getType()->isPointerTy())
5525 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5526 std::pair<SDValue, SDValue> Res =
5527 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5528 getValue(Src), getValue(Char), getValue(Length),
5529 MachinePointerInfo(Src));
5530 if (Res.first.getNode()) {
5531 setValue(&I, Res.first);
5532 PendingLoads.push_back(Res.second);
5539 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5540 /// optimized form. If so, return true and lower it, otherwise return false
5541 /// and it will be lowered like a normal call.
5542 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5543 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5544 if (I.getNumArgOperands() != 2)
5547 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5548 if (!Arg0->getType()->isPointerTy() ||
5549 !Arg1->getType()->isPointerTy() ||
5550 !I.getType()->isPointerTy())
5553 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5554 std::pair<SDValue, SDValue> Res =
5555 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5556 getValue(Arg0), getValue(Arg1),
5557 MachinePointerInfo(Arg0),
5558 MachinePointerInfo(Arg1), isStpcpy);
5559 if (Res.first.getNode()) {
5560 setValue(&I, Res.first);
5561 DAG.setRoot(Res.second);
5568 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5569 /// If so, return true and lower it, otherwise return false and it will be
5570 /// lowered like a normal call.
5571 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5572 // Verify that the prototype makes sense. int strcmp(void*,void*)
5573 if (I.getNumArgOperands() != 2)
5576 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5577 if (!Arg0->getType()->isPointerTy() ||
5578 !Arg1->getType()->isPointerTy() ||
5579 !I.getType()->isIntegerTy())
5582 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5583 std::pair<SDValue, SDValue> Res =
5584 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5585 getValue(Arg0), getValue(Arg1),
5586 MachinePointerInfo(Arg0),
5587 MachinePointerInfo(Arg1));
5588 if (Res.first.getNode()) {
5589 processIntegerCallValue(I, Res.first, true);
5590 PendingLoads.push_back(Res.second);
5597 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5598 /// form. If so, return true and lower it, otherwise return false and it
5599 /// will be lowered like a normal call.
5600 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5601 // Verify that the prototype makes sense. size_t strlen(char *)
5602 if (I.getNumArgOperands() != 1)
5605 const Value *Arg0 = I.getArgOperand(0);
5606 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5609 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5610 std::pair<SDValue, SDValue> Res =
5611 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5612 getValue(Arg0), MachinePointerInfo(Arg0));
5613 if (Res.first.getNode()) {
5614 processIntegerCallValue(I, Res.first, false);
5615 PendingLoads.push_back(Res.second);
5622 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5623 /// form. If so, return true and lower it, otherwise return false and it
5624 /// will be lowered like a normal call.
5625 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5626 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5627 if (I.getNumArgOperands() != 2)
5630 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5631 if (!Arg0->getType()->isPointerTy() ||
5632 !Arg1->getType()->isIntegerTy() ||
5633 !I.getType()->isIntegerTy())
5636 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5637 std::pair<SDValue, SDValue> Res =
5638 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5639 getValue(Arg0), getValue(Arg1),
5640 MachinePointerInfo(Arg0));
5641 if (Res.first.getNode()) {
5642 processIntegerCallValue(I, Res.first, false);
5643 PendingLoads.push_back(Res.second);
5650 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5651 /// operation (as expected), translate it to an SDNode with the specified opcode
5652 /// and return true.
5653 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5655 // Sanity check that it really is a unary floating-point call.
5656 if (I.getNumArgOperands() != 1 ||
5657 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5658 I.getType() != I.getArgOperand(0)->getType() ||
5659 !I.onlyReadsMemory())
5662 SDValue Tmp = getValue(I.getArgOperand(0));
5663 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5667 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5668 /// operation (as expected), translate it to an SDNode with the specified opcode
5669 /// and return true.
5670 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5672 // Sanity check that it really is a binary floating-point call.
5673 if (I.getNumArgOperands() != 2 ||
5674 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5675 I.getType() != I.getArgOperand(0)->getType() ||
5676 I.getType() != I.getArgOperand(1)->getType() ||
5677 !I.onlyReadsMemory())
5680 SDValue Tmp0 = getValue(I.getArgOperand(0));
5681 SDValue Tmp1 = getValue(I.getArgOperand(1));
5682 EVT VT = Tmp0.getValueType();
5683 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5687 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5688 // Handle inline assembly differently.
5689 if (isa<InlineAsm>(I.getCalledValue())) {
5694 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5695 ComputeUsesVAFloatArgument(I, &MMI);
5697 const char *RenameFn = nullptr;
5698 if (Function *F = I.getCalledFunction()) {
5699 if (F->isDeclaration()) {
5700 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5701 if (unsigned IID = II->getIntrinsicID(F)) {
5702 RenameFn = visitIntrinsicCall(I, IID);
5707 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5708 RenameFn = visitIntrinsicCall(I, IID);
5714 // Check for well-known libc/libm calls. If the function is internal, it
5715 // can't be a library call.
5717 if (!F->hasLocalLinkage() && F->hasName() &&
5718 LibInfo->getLibFunc(F->getName(), Func) &&
5719 LibInfo->hasOptimizedCodeGen(Func)) {
5722 case LibFunc::copysign:
5723 case LibFunc::copysignf:
5724 case LibFunc::copysignl:
5725 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5726 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5727 I.getType() == I.getArgOperand(0)->getType() &&
5728 I.getType() == I.getArgOperand(1)->getType() &&
5729 I.onlyReadsMemory()) {
5730 SDValue LHS = getValue(I.getArgOperand(0));
5731 SDValue RHS = getValue(I.getArgOperand(1));
5732 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5733 LHS.getValueType(), LHS, RHS));
5738 case LibFunc::fabsf:
5739 case LibFunc::fabsl:
5740 if (visitUnaryFloatCall(I, ISD::FABS))
5744 case LibFunc::fminf:
5745 case LibFunc::fminl:
5746 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5750 case LibFunc::fmaxf:
5751 case LibFunc::fmaxl:
5752 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5758 if (visitUnaryFloatCall(I, ISD::FSIN))
5764 if (visitUnaryFloatCall(I, ISD::FCOS))
5768 case LibFunc::sqrtf:
5769 case LibFunc::sqrtl:
5770 case LibFunc::sqrt_finite:
5771 case LibFunc::sqrtf_finite:
5772 case LibFunc::sqrtl_finite:
5773 if (visitUnaryFloatCall(I, ISD::FSQRT))
5776 case LibFunc::floor:
5777 case LibFunc::floorf:
5778 case LibFunc::floorl:
5779 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5782 case LibFunc::nearbyint:
5783 case LibFunc::nearbyintf:
5784 case LibFunc::nearbyintl:
5785 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5789 case LibFunc::ceilf:
5790 case LibFunc::ceill:
5791 if (visitUnaryFloatCall(I, ISD::FCEIL))
5795 case LibFunc::rintf:
5796 case LibFunc::rintl:
5797 if (visitUnaryFloatCall(I, ISD::FRINT))
5800 case LibFunc::round:
5801 case LibFunc::roundf:
5802 case LibFunc::roundl:
5803 if (visitUnaryFloatCall(I, ISD::FROUND))
5806 case LibFunc::trunc:
5807 case LibFunc::truncf:
5808 case LibFunc::truncl:
5809 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5813 case LibFunc::log2f:
5814 case LibFunc::log2l:
5815 if (visitUnaryFloatCall(I, ISD::FLOG2))
5819 case LibFunc::exp2f:
5820 case LibFunc::exp2l:
5821 if (visitUnaryFloatCall(I, ISD::FEXP2))
5824 case LibFunc::memcmp:
5825 if (visitMemCmpCall(I))
5828 case LibFunc::memchr:
5829 if (visitMemChrCall(I))
5832 case LibFunc::strcpy:
5833 if (visitStrCpyCall(I, false))
5836 case LibFunc::stpcpy:
5837 if (visitStrCpyCall(I, true))
5840 case LibFunc::strcmp:
5841 if (visitStrCmpCall(I))
5844 case LibFunc::strlen:
5845 if (visitStrLenCall(I))
5848 case LibFunc::strnlen:
5849 if (visitStrNLenCall(I))
5858 Callee = getValue(I.getCalledValue());
5860 Callee = DAG.getExternalSymbol(
5862 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5864 // Check if we can potentially perform a tail call. More detailed checking is
5865 // be done within LowerCallTo, after more information about the call is known.
5866 LowerCallTo(&I, Callee, I.isTailCall());
5871 /// AsmOperandInfo - This contains information for each constraint that we are
5873 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5875 /// CallOperand - If this is the result output operand or a clobber
5876 /// this is null, otherwise it is the incoming operand to the CallInst.
5877 /// This gets modified as the asm is processed.
5878 SDValue CallOperand;
5880 /// AssignedRegs - If this is a register or register class operand, this
5881 /// contains the set of register corresponding to the operand.
5882 RegsForValue AssignedRegs;
5884 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5885 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5888 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5889 /// corresponds to. If there is no Value* for this operand, it returns
5891 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5892 const DataLayout &DL) const {
5893 if (!CallOperandVal) return MVT::Other;
5895 if (isa<BasicBlock>(CallOperandVal))
5896 return TLI.getPointerTy(DL);
5898 llvm::Type *OpTy = CallOperandVal->getType();
5900 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5901 // If this is an indirect operand, the operand is a pointer to the
5904 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5906 report_fatal_error("Indirect operand for inline asm not a pointer!");
5907 OpTy = PtrTy->getElementType();
5910 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5911 if (StructType *STy = dyn_cast<StructType>(OpTy))
5912 if (STy->getNumElements() == 1)
5913 OpTy = STy->getElementType(0);
5915 // If OpTy is not a single value, it may be a struct/union that we
5916 // can tile with integers.
5917 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5918 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5927 OpTy = IntegerType::get(Context, BitSize);
5932 return TLI.getValueType(DL, OpTy, true);
5936 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5938 } // end anonymous namespace
5940 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5941 /// specified operand. We prefer to assign virtual registers, to allow the
5942 /// register allocator to handle the assignment process. However, if the asm
5943 /// uses features that we can't model on machineinstrs, we have SDISel do the
5944 /// allocation. This produces generally horrible, but correct, code.
5946 /// OpInfo describes the operand.
5948 static void GetRegistersForValue(SelectionDAG &DAG,
5949 const TargetLowering &TLI,
5951 SDISelAsmOperandInfo &OpInfo) {
5952 LLVMContext &Context = *DAG.getContext();
5954 MachineFunction &MF = DAG.getMachineFunction();
5955 SmallVector<unsigned, 4> Regs;
5957 // If this is a constraint for a single physreg, or a constraint for a
5958 // register class, find it.
5959 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5960 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5961 OpInfo.ConstraintCode,
5962 OpInfo.ConstraintVT);
5964 unsigned NumRegs = 1;
5965 if (OpInfo.ConstraintVT != MVT::Other) {
5966 // If this is a FP input in an integer register (or visa versa) insert a bit
5967 // cast of the input value. More generally, handle any case where the input
5968 // value disagrees with the register class we plan to stick this in.
5969 if (OpInfo.Type == InlineAsm::isInput &&
5970 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5971 // Try to convert to the first EVT that the reg class contains. If the
5972 // types are identical size, use a bitcast to convert (e.g. two differing
5974 MVT RegVT = *PhysReg.second->vt_begin();
5975 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5976 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5977 RegVT, OpInfo.CallOperand);
5978 OpInfo.ConstraintVT = RegVT;
5979 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5980 // If the input is a FP value and we want it in FP registers, do a
5981 // bitcast to the corresponding integer type. This turns an f64 value
5982 // into i64, which can be passed with two i32 values on a 32-bit
5984 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5985 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5986 RegVT, OpInfo.CallOperand);
5987 OpInfo.ConstraintVT = RegVT;
5991 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5995 EVT ValueVT = OpInfo.ConstraintVT;
5997 // If this is a constraint for a specific physical register, like {r17},
5999 if (unsigned AssignedReg = PhysReg.first) {
6000 const TargetRegisterClass *RC = PhysReg.second;
6001 if (OpInfo.ConstraintVT == MVT::Other)
6002 ValueVT = *RC->vt_begin();
6004 // Get the actual register value type. This is important, because the user
6005 // may have asked for (e.g.) the AX register in i32 type. We need to
6006 // remember that AX is actually i16 to get the right extension.
6007 RegVT = *RC->vt_begin();
6009 // This is a explicit reference to a physical register.
6010 Regs.push_back(AssignedReg);
6012 // If this is an expanded reference, add the rest of the regs to Regs.
6014 TargetRegisterClass::iterator I = RC->begin();
6015 for (; *I != AssignedReg; ++I)
6016 assert(I != RC->end() && "Didn't find reg!");
6018 // Already added the first reg.
6020 for (; NumRegs; --NumRegs, ++I) {
6021 assert(I != RC->end() && "Ran out of registers to allocate!");
6026 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6030 // Otherwise, if this was a reference to an LLVM register class, create vregs
6031 // for this reference.
6032 if (const TargetRegisterClass *RC = PhysReg.second) {
6033 RegVT = *RC->vt_begin();
6034 if (OpInfo.ConstraintVT == MVT::Other)
6037 // Create the appropriate number of virtual registers.
6038 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6039 for (; NumRegs; --NumRegs)
6040 Regs.push_back(RegInfo.createVirtualRegister(RC));
6042 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6046 // Otherwise, we couldn't allocate enough registers for this.
6049 /// visitInlineAsm - Handle a call to an InlineAsm object.
6051 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6052 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6054 /// ConstraintOperands - Information about all of the constraints.
6055 SDISelAsmOperandInfoVector ConstraintOperands;
6057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6058 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6059 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6061 bool hasMemory = false;
6063 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6064 unsigned ResNo = 0; // ResNo - The result number of the next output.
6065 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6066 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6067 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6069 MVT OpVT = MVT::Other;
6071 // Compute the value type for each operand.
6072 switch (OpInfo.Type) {
6073 case InlineAsm::isOutput:
6074 // Indirect outputs just consume an argument.
6075 if (OpInfo.isIndirect) {
6076 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6080 // The return value of the call is this value. As such, there is no
6081 // corresponding argument.
6082 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6083 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6084 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6085 STy->getElementType(ResNo));
6087 assert(ResNo == 0 && "Asm only has one result!");
6088 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6092 case InlineAsm::isInput:
6093 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6095 case InlineAsm::isClobber:
6100 // If this is an input or an indirect output, process the call argument.
6101 // BasicBlocks are labels, currently appearing only in asm's.
6102 if (OpInfo.CallOperandVal) {
6103 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6104 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6106 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6109 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6110 DAG.getDataLayout()).getSimpleVT();
6113 OpInfo.ConstraintVT = OpVT;
6115 // Indirect operand accesses access memory.
6116 if (OpInfo.isIndirect)
6119 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6120 TargetLowering::ConstraintType
6121 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6122 if (CType == TargetLowering::C_Memory) {
6130 SDValue Chain, Flag;
6132 // We won't need to flush pending loads if this asm doesn't touch
6133 // memory and is nonvolatile.
6134 if (hasMemory || IA->hasSideEffects())
6137 Chain = DAG.getRoot();
6139 // Second pass over the constraints: compute which constraint option to use
6140 // and assign registers to constraints that want a specific physreg.
6141 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6142 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6144 // If this is an output operand with a matching input operand, look up the
6145 // matching input. If their types mismatch, e.g. one is an integer, the
6146 // other is floating point, or their sizes are different, flag it as an
6148 if (OpInfo.hasMatchingInput()) {
6149 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6151 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6153 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6154 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6155 OpInfo.ConstraintVT);
6156 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6157 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6158 Input.ConstraintVT);
6159 if ((OpInfo.ConstraintVT.isInteger() !=
6160 Input.ConstraintVT.isInteger()) ||
6161 (MatchRC.second != InputRC.second)) {
6162 report_fatal_error("Unsupported asm: input constraint"
6163 " with a matching output constraint of"
6164 " incompatible type!");
6166 Input.ConstraintVT = OpInfo.ConstraintVT;
6170 // Compute the constraint code and ConstraintType to use.
6171 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6173 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6174 OpInfo.Type == InlineAsm::isClobber)
6177 // If this is a memory input, and if the operand is not indirect, do what we
6178 // need to to provide an address for the memory input.
6179 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6180 !OpInfo.isIndirect) {
6181 assert((OpInfo.isMultipleAlternative ||
6182 (OpInfo.Type == InlineAsm::isInput)) &&
6183 "Can only indirectify direct input operands!");
6185 // Memory operands really want the address of the value. If we don't have
6186 // an indirect input, put it in the constpool if we can, otherwise spill
6187 // it to a stack slot.
6188 // TODO: This isn't quite right. We need to handle these according to
6189 // the addressing mode that the constraint wants. Also, this may take
6190 // an additional register for the computation and we don't want that
6193 // If the operand is a float, integer, or vector constant, spill to a
6194 // constant pool entry to get its address.
6195 const Value *OpVal = OpInfo.CallOperandVal;
6196 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6197 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6198 OpInfo.CallOperand = DAG.getConstantPool(
6199 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6201 // Otherwise, create a stack slot and emit a store to it before the
6203 Type *Ty = OpVal->getType();
6204 auto &DL = DAG.getDataLayout();
6205 uint64_t TySize = DL.getTypeAllocSize(Ty);
6206 unsigned Align = DL.getPrefTypeAlignment(Ty);
6207 MachineFunction &MF = DAG.getMachineFunction();
6208 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6210 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6211 Chain = DAG.getStore(
6212 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6213 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6215 OpInfo.CallOperand = StackSlot;
6218 // There is no longer a Value* corresponding to this operand.
6219 OpInfo.CallOperandVal = nullptr;
6221 // It is now an indirect operand.
6222 OpInfo.isIndirect = true;
6225 // If this constraint is for a specific register, allocate it before
6227 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6228 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6231 // Second pass - Loop over all of the operands, assigning virtual or physregs
6232 // to register class operands.
6233 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6234 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6236 // C_Register operands have already been allocated, Other/Memory don't need
6238 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6239 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6242 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6243 std::vector<SDValue> AsmNodeOperands;
6244 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6245 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6246 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6248 // If we have a !srcloc metadata node associated with it, we want to attach
6249 // this to the ultimately generated inline asm machineinstr. To do this, we
6250 // pass in the third operand as this (potentially null) inline asm MDNode.
6251 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6252 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6254 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6255 // bits as operand 3.
6256 unsigned ExtraInfo = 0;
6257 if (IA->hasSideEffects())
6258 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6259 if (IA->isAlignStack())
6260 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6261 // Set the asm dialect.
6262 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6264 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6265 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6266 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6268 // Compute the constraint code and ConstraintType to use.
6269 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6271 // Ideally, we would only check against memory constraints. However, the
6272 // meaning of an other constraint can be target-specific and we can't easily
6273 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6274 // for other constriants as well.
6275 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6276 OpInfo.ConstraintType == TargetLowering::C_Other) {
6277 if (OpInfo.Type == InlineAsm::isInput)
6278 ExtraInfo |= InlineAsm::Extra_MayLoad;
6279 else if (OpInfo.Type == InlineAsm::isOutput)
6280 ExtraInfo |= InlineAsm::Extra_MayStore;
6281 else if (OpInfo.Type == InlineAsm::isClobber)
6282 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6286 AsmNodeOperands.push_back(DAG.getTargetConstant(
6287 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6289 // Loop over all of the inputs, copying the operand values into the
6290 // appropriate registers and processing the output regs.
6291 RegsForValue RetValRegs;
6293 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6294 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6296 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6297 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6299 switch (OpInfo.Type) {
6300 case InlineAsm::isOutput: {
6301 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6302 OpInfo.ConstraintType != TargetLowering::C_Register) {
6303 // Memory output, or 'other' output (e.g. 'X' constraint).
6304 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6306 unsigned ConstraintID =
6307 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6308 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6309 "Failed to convert memory constraint code to constraint id.");
6311 // Add information to the INLINEASM node to know about this output.
6312 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6313 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6314 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6316 AsmNodeOperands.push_back(OpInfo.CallOperand);
6320 // Otherwise, this is a register or register class output.
6322 // Copy the output from the appropriate register. Find a register that
6324 if (OpInfo.AssignedRegs.Regs.empty()) {
6325 LLVMContext &Ctx = *DAG.getContext();
6326 Ctx.emitError(CS.getInstruction(),
6327 "couldn't allocate output register for constraint '" +
6328 Twine(OpInfo.ConstraintCode) + "'");
6332 // If this is an indirect operand, store through the pointer after the
6334 if (OpInfo.isIndirect) {
6335 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6336 OpInfo.CallOperandVal));
6338 // This is the result value of the call.
6339 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6340 // Concatenate this output onto the outputs list.
6341 RetValRegs.append(OpInfo.AssignedRegs);
6344 // Add information to the INLINEASM node to know that this register is
6347 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6348 ? InlineAsm::Kind_RegDefEarlyClobber
6349 : InlineAsm::Kind_RegDef,
6350 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6353 case InlineAsm::isInput: {
6354 SDValue InOperandVal = OpInfo.CallOperand;
6356 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6357 // If this is required to match an output register we have already set,
6358 // just use its register.
6359 unsigned OperandNo = OpInfo.getMatchedOperand();
6361 // Scan until we find the definition we already emitted of this operand.
6362 // When we find it, create a RegsForValue operand.
6363 unsigned CurOp = InlineAsm::Op_FirstOperand;
6364 for (; OperandNo; --OperandNo) {
6365 // Advance to the next operand.
6367 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6368 assert((InlineAsm::isRegDefKind(OpFlag) ||
6369 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6370 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6371 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6375 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6376 if (InlineAsm::isRegDefKind(OpFlag) ||
6377 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6378 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6379 if (OpInfo.isIndirect) {
6380 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6381 LLVMContext &Ctx = *DAG.getContext();
6382 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6383 " don't know how to handle tied "
6384 "indirect register inputs");
6388 RegsForValue MatchedRegs;
6389 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6390 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6391 MatchedRegs.RegVTs.push_back(RegVT);
6392 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6393 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6395 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6396 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6398 LLVMContext &Ctx = *DAG.getContext();
6399 Ctx.emitError(CS.getInstruction(),
6400 "inline asm error: This value"
6401 " type register class is not natively supported!");
6405 SDLoc dl = getCurSDLoc();
6406 // Use the produced MatchedRegs object to
6407 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6408 Chain, &Flag, CS.getInstruction());
6409 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6410 true, OpInfo.getMatchedOperand(), dl,
6411 DAG, AsmNodeOperands);
6415 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6416 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6417 "Unexpected number of operands");
6418 // Add information to the INLINEASM node to know about this input.
6419 // See InlineAsm.h isUseOperandTiedToDef.
6420 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6421 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6422 OpInfo.getMatchedOperand());
6423 AsmNodeOperands.push_back(DAG.getTargetConstant(
6424 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6425 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6429 // Treat indirect 'X' constraint as memory.
6430 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6432 OpInfo.ConstraintType = TargetLowering::C_Memory;
6434 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6435 std::vector<SDValue> Ops;
6436 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6439 LLVMContext &Ctx = *DAG.getContext();
6440 Ctx.emitError(CS.getInstruction(),
6441 "invalid operand for inline asm constraint '" +
6442 Twine(OpInfo.ConstraintCode) + "'");
6446 // Add information to the INLINEASM node to know about this input.
6447 unsigned ResOpType =
6448 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6449 AsmNodeOperands.push_back(DAG.getTargetConstant(
6450 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6451 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6455 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6456 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6457 assert(InOperandVal.getValueType() ==
6458 TLI.getPointerTy(DAG.getDataLayout()) &&
6459 "Memory operands expect pointer values");
6461 unsigned ConstraintID =
6462 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6463 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6464 "Failed to convert memory constraint code to constraint id.");
6466 // Add information to the INLINEASM node to know about this input.
6467 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6468 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6469 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6472 AsmNodeOperands.push_back(InOperandVal);
6476 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6477 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6478 "Unknown constraint type!");
6480 // TODO: Support this.
6481 if (OpInfo.isIndirect) {
6482 LLVMContext &Ctx = *DAG.getContext();
6483 Ctx.emitError(CS.getInstruction(),
6484 "Don't know how to handle indirect register inputs yet "
6485 "for constraint '" +
6486 Twine(OpInfo.ConstraintCode) + "'");
6490 // Copy the input into the appropriate registers.
6491 if (OpInfo.AssignedRegs.Regs.empty()) {
6492 LLVMContext &Ctx = *DAG.getContext();
6493 Ctx.emitError(CS.getInstruction(),
6494 "couldn't allocate input reg for constraint '" +
6495 Twine(OpInfo.ConstraintCode) + "'");
6499 SDLoc dl = getCurSDLoc();
6501 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6502 Chain, &Flag, CS.getInstruction());
6504 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6505 dl, DAG, AsmNodeOperands);
6508 case InlineAsm::isClobber: {
6509 // Add the clobbered value to the operand list, so that the register
6510 // allocator is aware that the physreg got clobbered.
6511 if (!OpInfo.AssignedRegs.Regs.empty())
6512 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6513 false, 0, getCurSDLoc(), DAG,
6520 // Finish up input operands. Set the input chain and add the flag last.
6521 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6522 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6524 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6525 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6526 Flag = Chain.getValue(1);
6528 // If this asm returns a register value, copy the result from that register
6529 // and set it as the value of the call.
6530 if (!RetValRegs.Regs.empty()) {
6531 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6532 Chain, &Flag, CS.getInstruction());
6534 // FIXME: Why don't we do this for inline asms with MRVs?
6535 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6536 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6538 // If any of the results of the inline asm is a vector, it may have the
6539 // wrong width/num elts. This can happen for register classes that can
6540 // contain multiple different value types. The preg or vreg allocated may
6541 // not have the same VT as was expected. Convert it to the right type
6542 // with bit_convert.
6543 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6544 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6547 } else if (ResultType != Val.getValueType() &&
6548 ResultType.isInteger() && Val.getValueType().isInteger()) {
6549 // If a result value was tied to an input value, the computed result may
6550 // have a wider width than the expected result. Extract the relevant
6552 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6555 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6558 setValue(CS.getInstruction(), Val);
6559 // Don't need to use this as a chain in this case.
6560 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6564 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6566 // Process indirect outputs, first output all of the flagged copies out of
6568 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6569 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6570 const Value *Ptr = IndirectStoresToEmit[i].second;
6571 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6573 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6576 // Emit the non-flagged stores from the physregs.
6577 SmallVector<SDValue, 8> OutChains;
6578 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6579 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6580 StoresToEmit[i].first,
6581 getValue(StoresToEmit[i].second),
6582 MachinePointerInfo(StoresToEmit[i].second),
6584 OutChains.push_back(Val);
6587 if (!OutChains.empty())
6588 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6593 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6594 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6595 MVT::Other, getRoot(),
6596 getValue(I.getArgOperand(0)),
6597 DAG.getSrcValue(I.getArgOperand(0))));
6600 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6601 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6602 const DataLayout &DL = DAG.getDataLayout();
6603 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6604 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6605 DAG.getSrcValue(I.getOperand(0)),
6606 DL.getABITypeAlignment(I.getType()));
6608 DAG.setRoot(V.getValue(1));
6611 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6612 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6613 MVT::Other, getRoot(),
6614 getValue(I.getArgOperand(0)),
6615 DAG.getSrcValue(I.getArgOperand(0))));
6618 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6619 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6620 MVT::Other, getRoot(),
6621 getValue(I.getArgOperand(0)),
6622 getValue(I.getArgOperand(1)),
6623 DAG.getSrcValue(I.getArgOperand(0)),
6624 DAG.getSrcValue(I.getArgOperand(1))));
6627 /// \brief Lower an argument list according to the target calling convention.
6629 /// \return A tuple of <return-value, token-chain>
6631 /// This is a helper for lowering intrinsics that follow a target calling
6632 /// convention or require stack pointer adjustment. Only a subset of the
6633 /// intrinsic's operands need to participate in the calling convention.
6634 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6635 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6636 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6637 TargetLowering::ArgListTy Args;
6638 Args.reserve(NumArgs);
6640 // Populate the argument list.
6641 // Attributes for args start at offset 1, after the return attribute.
6642 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6643 ArgI != ArgE; ++ArgI) {
6644 const Value *V = CS->getOperand(ArgI);
6646 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6648 TargetLowering::ArgListEntry Entry;
6649 Entry.Node = getValue(V);
6650 Entry.Ty = V->getType();
6651 Entry.setAttributes(&CS, AttrI);
6652 Args.push_back(Entry);
6655 TargetLowering::CallLoweringInfo CLI(DAG);
6656 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6657 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6658 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6660 return lowerInvokable(CLI, EHPadBB);
6663 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6664 /// or patchpoint target node's operand list.
6666 /// Constants are converted to TargetConstants purely as an optimization to
6667 /// avoid constant materialization and register allocation.
6669 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6670 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6671 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6672 /// address materialization and register allocation, but may also be required
6673 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6674 /// alloca in the entry block, then the runtime may assume that the alloca's
6675 /// StackMap location can be read immediately after compilation and that the
6676 /// location is valid at any point during execution (this is similar to the
6677 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6678 /// only available in a register, then the runtime would need to trap when
6679 /// execution reaches the StackMap in order to read the alloca's location.
6680 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6681 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6682 SelectionDAGBuilder &Builder) {
6683 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6684 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6685 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6687 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6689 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6690 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6691 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6692 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6693 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6695 Ops.push_back(OpVal);
6699 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6700 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6701 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6702 // [live variables...])
6704 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6706 SDValue Chain, InFlag, Callee, NullPtr;
6707 SmallVector<SDValue, 32> Ops;
6709 SDLoc DL = getCurSDLoc();
6710 Callee = getValue(CI.getCalledValue());
6711 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6713 // The stackmap intrinsic only records the live variables (the arguemnts
6714 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6715 // intrinsic, this won't be lowered to a function call. This means we don't
6716 // have to worry about calling conventions and target specific lowering code.
6717 // Instead we perform the call lowering right here.
6719 // chain, flag = CALLSEQ_START(chain, 0)
6720 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6721 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6723 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6724 InFlag = Chain.getValue(1);
6726 // Add the <id> and <numBytes> constants.
6727 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6728 Ops.push_back(DAG.getTargetConstant(
6729 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6730 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6731 Ops.push_back(DAG.getTargetConstant(
6732 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6735 // Push live variables for the stack map.
6736 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6738 // We are not pushing any register mask info here on the operands list,
6739 // because the stackmap doesn't clobber anything.
6741 // Push the chain and the glue flag.
6742 Ops.push_back(Chain);
6743 Ops.push_back(InFlag);
6745 // Create the STACKMAP node.
6746 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6747 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6748 Chain = SDValue(SM, 0);
6749 InFlag = Chain.getValue(1);
6751 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6753 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6755 // Set the root to the target-lowered call chain.
6758 // Inform the Frame Information that we have a stackmap in this function.
6759 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6762 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6763 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6764 const BasicBlock *EHPadBB) {
6765 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6770 // [live variables...])
6772 CallingConv::ID CC = CS.getCallingConv();
6773 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6774 bool HasDef = !CS->getType()->isVoidTy();
6775 SDLoc dl = getCurSDLoc();
6776 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6778 // Handle immediate and symbolic callees.
6779 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6780 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6782 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6783 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6784 SDLoc(SymbolicCallee),
6785 SymbolicCallee->getValueType(0));
6787 // Get the real number of arguments participating in the call <numArgs>
6788 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6789 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6791 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6792 // Intrinsics include all meta-operands up to but not including CC.
6793 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6794 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6795 "Not enough arguments provided to the patchpoint intrinsic");
6797 // For AnyRegCC the arguments are lowered later on manually.
6798 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6800 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6801 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6802 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6804 SDNode *CallEnd = Result.second.getNode();
6805 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6806 CallEnd = CallEnd->getOperand(0).getNode();
6808 /// Get a call instruction from the call sequence chain.
6809 /// Tail calls are not allowed.
6810 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6811 "Expected a callseq node.");
6812 SDNode *Call = CallEnd->getOperand(0).getNode();
6813 bool HasGlue = Call->getGluedNode();
6815 // Replace the target specific call node with the patchable intrinsic.
6816 SmallVector<SDValue, 8> Ops;
6818 // Add the <id> and <numBytes> constants.
6819 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6820 Ops.push_back(DAG.getTargetConstant(
6821 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6822 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6823 Ops.push_back(DAG.getTargetConstant(
6824 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6828 Ops.push_back(Callee);
6830 // Adjust <numArgs> to account for any arguments that have been passed on the
6832 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6833 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6834 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6835 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6837 // Add the calling convention
6838 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6840 // Add the arguments we omitted previously. The register allocator should
6841 // place these in any free register.
6843 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6844 Ops.push_back(getValue(CS.getArgument(i)));
6846 // Push the arguments from the call instruction up to the register mask.
6847 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6848 Ops.append(Call->op_begin() + 2, e);
6850 // Push live variables for the stack map.
6851 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6853 // Push the register mask info.
6855 Ops.push_back(*(Call->op_end()-2));
6857 Ops.push_back(*(Call->op_end()-1));
6859 // Push the chain (this is originally the first operand of the call, but
6860 // becomes now the last or second to last operand).
6861 Ops.push_back(*(Call->op_begin()));
6863 // Push the glue flag (last operand).
6865 Ops.push_back(*(Call->op_end()-1));
6868 if (IsAnyRegCC && HasDef) {
6869 // Create the return types based on the intrinsic definition
6870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6871 SmallVector<EVT, 3> ValueVTs;
6872 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6873 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6875 // There is always a chain and a glue type at the end
6876 ValueVTs.push_back(MVT::Other);
6877 ValueVTs.push_back(MVT::Glue);
6878 NodeTys = DAG.getVTList(ValueVTs);
6880 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6882 // Replace the target specific call node with a PATCHPOINT node.
6883 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6886 // Update the NodeMap.
6889 setValue(CS.getInstruction(), SDValue(MN, 0));
6891 setValue(CS.getInstruction(), Result.first);
6894 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6895 // call sequence. Furthermore the location of the chain and glue can change
6896 // when the AnyReg calling convention is used and the intrinsic returns a
6898 if (IsAnyRegCC && HasDef) {
6899 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6900 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6901 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6903 DAG.ReplaceAllUsesWith(Call, MN);
6904 DAG.DeleteNode(Call);
6906 // Inform the Frame Information that we have a patchpoint in this function.
6907 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6910 /// Returns an AttributeSet representing the attributes applied to the return
6911 /// value of the given call.
6912 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6913 SmallVector<Attribute::AttrKind, 2> Attrs;
6915 Attrs.push_back(Attribute::SExt);
6917 Attrs.push_back(Attribute::ZExt);
6919 Attrs.push_back(Attribute::InReg);
6921 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6925 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6926 /// implementation, which just calls LowerCall.
6927 /// FIXME: When all targets are
6928 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6929 std::pair<SDValue, SDValue>
6930 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6931 // Handle the incoming return values from the call.
6933 Type *OrigRetTy = CLI.RetTy;
6934 SmallVector<EVT, 4> RetTys;
6935 SmallVector<uint64_t, 4> Offsets;
6936 auto &DL = CLI.DAG.getDataLayout();
6937 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6939 SmallVector<ISD::OutputArg, 4> Outs;
6940 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6942 bool CanLowerReturn =
6943 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6944 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6946 SDValue DemoteStackSlot;
6947 int DemoteStackIdx = -100;
6948 if (!CanLowerReturn) {
6949 // FIXME: equivalent assert?
6950 // assert(!CS.hasInAllocaArgument() &&
6951 // "sret demotion is incompatible with inalloca");
6952 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6953 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6954 MachineFunction &MF = CLI.DAG.getMachineFunction();
6955 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6956 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6958 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6960 Entry.Node = DemoteStackSlot;
6961 Entry.Ty = StackSlotPtrType;
6962 Entry.isSExt = false;
6963 Entry.isZExt = false;
6964 Entry.isInReg = false;
6965 Entry.isSRet = true;
6966 Entry.isNest = false;
6967 Entry.isByVal = false;
6968 Entry.isReturned = false;
6969 Entry.Alignment = Align;
6970 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6971 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6973 // sret demotion isn't compatible with tail-calls, since the sret argument
6974 // points into the callers stack frame.
6975 CLI.IsTailCall = false;
6977 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6979 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6980 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6981 for (unsigned i = 0; i != NumRegs; ++i) {
6982 ISD::InputArg MyFlags;
6983 MyFlags.VT = RegisterVT;
6985 MyFlags.Used = CLI.IsReturnValueUsed;
6987 MyFlags.Flags.setSExt();
6989 MyFlags.Flags.setZExt();
6991 MyFlags.Flags.setInReg();
6992 CLI.Ins.push_back(MyFlags);
6997 // Handle all of the outgoing arguments.
6999 CLI.OutVals.clear();
7000 ArgListTy &Args = CLI.getArgs();
7001 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7002 SmallVector<EVT, 4> ValueVTs;
7003 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7004 Type *FinalType = Args[i].Ty;
7005 if (Args[i].isByVal)
7006 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7007 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7008 FinalType, CLI.CallConv, CLI.IsVarArg);
7009 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7011 EVT VT = ValueVTs[Value];
7012 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7013 SDValue Op = SDValue(Args[i].Node.getNode(),
7014 Args[i].Node.getResNo() + Value);
7015 ISD::ArgFlagsTy Flags;
7016 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7022 if (Args[i].isInReg)
7026 if (Args[i].isByVal)
7028 if (Args[i].isInAlloca) {
7029 Flags.setInAlloca();
7030 // Set the byval flag for CCAssignFn callbacks that don't know about
7031 // inalloca. This way we can know how many bytes we should've allocated
7032 // and how many bytes a callee cleanup function will pop. If we port
7033 // inalloca to more targets, we'll have to add custom inalloca handling
7034 // in the various CC lowering callbacks.
7037 if (Args[i].isByVal || Args[i].isInAlloca) {
7038 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7039 Type *ElementTy = Ty->getElementType();
7040 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7041 // For ByVal, alignment should come from FE. BE will guess if this
7042 // info is not there but there are cases it cannot get right.
7043 unsigned FrameAlign;
7044 if (Args[i].Alignment)
7045 FrameAlign = Args[i].Alignment;
7047 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7048 Flags.setByValAlign(FrameAlign);
7053 Flags.setInConsecutiveRegs();
7054 Flags.setOrigAlign(OriginalAlignment);
7056 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7057 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7058 SmallVector<SDValue, 4> Parts(NumParts);
7059 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7062 ExtendKind = ISD::SIGN_EXTEND;
7063 else if (Args[i].isZExt)
7064 ExtendKind = ISD::ZERO_EXTEND;
7066 // Conservatively only handle 'returned' on non-vectors for now
7067 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7068 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7069 "unexpected use of 'returned'");
7070 // Before passing 'returned' to the target lowering code, ensure that
7071 // either the register MVT and the actual EVT are the same size or that
7072 // the return value and argument are extended in the same way; in these
7073 // cases it's safe to pass the argument register value unchanged as the
7074 // return register value (although it's at the target's option whether
7076 // TODO: allow code generation to take advantage of partially preserved
7077 // registers rather than clobbering the entire register when the
7078 // parameter extension method is not compatible with the return
7080 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7081 (ExtendKind != ISD::ANY_EXTEND &&
7082 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7083 Flags.setReturned();
7086 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7087 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7089 for (unsigned j = 0; j != NumParts; ++j) {
7090 // if it isn't first piece, alignment must be 1
7091 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7092 i < CLI.NumFixedArgs,
7093 i, j*Parts[j].getValueType().getStoreSize());
7094 if (NumParts > 1 && j == 0)
7095 MyFlags.Flags.setSplit();
7097 MyFlags.Flags.setOrigAlign(1);
7099 CLI.Outs.push_back(MyFlags);
7100 CLI.OutVals.push_back(Parts[j]);
7103 if (NeedsRegBlock && Value == NumValues - 1)
7104 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7108 SmallVector<SDValue, 4> InVals;
7109 CLI.Chain = LowerCall(CLI, InVals);
7111 // Verify that the target's LowerCall behaved as expected.
7112 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7113 "LowerCall didn't return a valid chain!");
7114 assert((!CLI.IsTailCall || InVals.empty()) &&
7115 "LowerCall emitted a return value for a tail call!");
7116 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7117 "LowerCall didn't emit the correct number of values!");
7119 // For a tail call, the return value is merely live-out and there aren't
7120 // any nodes in the DAG representing it. Return a special value to
7121 // indicate that a tail call has been emitted and no more Instructions
7122 // should be processed in the current block.
7123 if (CLI.IsTailCall) {
7124 CLI.DAG.setRoot(CLI.Chain);
7125 return std::make_pair(SDValue(), SDValue());
7128 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7129 assert(InVals[i].getNode() &&
7130 "LowerCall emitted a null value!");
7131 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7132 "LowerCall emitted a value with the wrong type!");
7135 SmallVector<SDValue, 4> ReturnValues;
7136 if (!CanLowerReturn) {
7137 // The instruction result is the result of loading from the
7138 // hidden sret parameter.
7139 SmallVector<EVT, 1> PVTs;
7140 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7142 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7143 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7144 EVT PtrVT = PVTs[0];
7146 unsigned NumValues = RetTys.size();
7147 ReturnValues.resize(NumValues);
7148 SmallVector<SDValue, 4> Chains(NumValues);
7150 for (unsigned i = 0; i < NumValues; ++i) {
7151 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7152 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7154 SDValue L = CLI.DAG.getLoad(
7155 RetTys[i], CLI.DL, CLI.Chain, Add,
7156 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7157 DemoteStackIdx, Offsets[i]),
7158 false, false, false, 1);
7159 ReturnValues[i] = L;
7160 Chains[i] = L.getValue(1);
7163 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7165 // Collect the legal value parts into potentially illegal values
7166 // that correspond to the original function's return values.
7167 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7169 AssertOp = ISD::AssertSext;
7170 else if (CLI.RetZExt)
7171 AssertOp = ISD::AssertZext;
7172 unsigned CurReg = 0;
7173 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7175 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7176 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7178 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7179 NumRegs, RegisterVT, VT, nullptr,
7184 // For a function returning void, there is no return value. We can't create
7185 // such a node, so we just return a null return value in that case. In
7186 // that case, nothing will actually look at the value.
7187 if (ReturnValues.empty())
7188 return std::make_pair(SDValue(), CLI.Chain);
7191 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7192 CLI.DAG.getVTList(RetTys), ReturnValues);
7193 return std::make_pair(Res, CLI.Chain);
7196 void TargetLowering::LowerOperationWrapper(SDNode *N,
7197 SmallVectorImpl<SDValue> &Results,
7198 SelectionDAG &DAG) const {
7199 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7201 Results.push_back(Res);
7204 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7205 llvm_unreachable("LowerOperation not implemented for this target!");
7209 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7210 SDValue Op = getNonRegisterValue(V);
7211 assert((Op.getOpcode() != ISD::CopyFromReg ||
7212 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7213 "Copy from a reg to the same reg!");
7214 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7217 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7219 SDValue Chain = DAG.getEntryNode();
7221 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7222 FuncInfo.PreferredExtendType.end())
7224 : FuncInfo.PreferredExtendType[V];
7225 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7226 PendingExports.push_back(Chain);
7229 #include "llvm/CodeGen/SelectionDAGISel.h"
7231 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7232 /// entry block, return true. This includes arguments used by switches, since
7233 /// the switch may expand into multiple basic blocks.
7234 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7235 // With FastISel active, we may be splitting blocks, so force creation
7236 // of virtual registers for all non-dead arguments.
7238 return A->use_empty();
7240 const BasicBlock *Entry = A->getParent()->begin();
7241 for (const User *U : A->users())
7242 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7243 return false; // Use not in entry block.
7248 void SelectionDAGISel::LowerArguments(const Function &F) {
7249 SelectionDAG &DAG = SDB->DAG;
7250 SDLoc dl = SDB->getCurSDLoc();
7251 const DataLayout &DL = DAG.getDataLayout();
7252 SmallVector<ISD::InputArg, 16> Ins;
7254 if (!FuncInfo->CanLowerReturn) {
7255 // Put in an sret pointer parameter before all the other parameters.
7256 SmallVector<EVT, 1> ValueVTs;
7257 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7258 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7260 // NOTE: Assuming that a pointer will never break down to more than one VT
7262 ISD::ArgFlagsTy Flags;
7264 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7265 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7266 ISD::InputArg::NoArgIndex, 0);
7267 Ins.push_back(RetArg);
7270 // Set up the incoming argument description vector.
7272 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7273 I != E; ++I, ++Idx) {
7274 SmallVector<EVT, 4> ValueVTs;
7275 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7276 bool isArgValueUsed = !I->use_empty();
7277 unsigned PartBase = 0;
7278 Type *FinalType = I->getType();
7279 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7280 FinalType = cast<PointerType>(FinalType)->getElementType();
7281 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7282 FinalType, F.getCallingConv(), F.isVarArg());
7283 for (unsigned Value = 0, NumValues = ValueVTs.size();
7284 Value != NumValues; ++Value) {
7285 EVT VT = ValueVTs[Value];
7286 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7287 ISD::ArgFlagsTy Flags;
7288 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7290 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7292 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7294 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7296 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7298 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7300 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7301 Flags.setInAlloca();
7302 // Set the byval flag for CCAssignFn callbacks that don't know about
7303 // inalloca. This way we can know how many bytes we should've allocated
7304 // and how many bytes a callee cleanup function will pop. If we port
7305 // inalloca to more targets, we'll have to add custom inalloca handling
7306 // in the various CC lowering callbacks.
7309 if (Flags.isByVal() || Flags.isInAlloca()) {
7310 PointerType *Ty = cast<PointerType>(I->getType());
7311 Type *ElementTy = Ty->getElementType();
7312 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7313 // For ByVal, alignment should be passed from FE. BE will guess if
7314 // this info is not there but there are cases it cannot get right.
7315 unsigned FrameAlign;
7316 if (F.getParamAlignment(Idx))
7317 FrameAlign = F.getParamAlignment(Idx);
7319 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7320 Flags.setByValAlign(FrameAlign);
7322 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7325 Flags.setInConsecutiveRegs();
7326 Flags.setOrigAlign(OriginalAlignment);
7328 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7329 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7330 for (unsigned i = 0; i != NumRegs; ++i) {
7331 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7332 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7333 if (NumRegs > 1 && i == 0)
7334 MyFlags.Flags.setSplit();
7335 // if it isn't first piece, alignment must be 1
7337 MyFlags.Flags.setOrigAlign(1);
7338 Ins.push_back(MyFlags);
7340 if (NeedsRegBlock && Value == NumValues - 1)
7341 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7342 PartBase += VT.getStoreSize();
7346 // Call the target to set up the argument values.
7347 SmallVector<SDValue, 8> InVals;
7348 SDValue NewRoot = TLI->LowerFormalArguments(
7349 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7351 // Verify that the target's LowerFormalArguments behaved as expected.
7352 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7353 "LowerFormalArguments didn't return a valid chain!");
7354 assert(InVals.size() == Ins.size() &&
7355 "LowerFormalArguments didn't emit the correct number of values!");
7357 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7358 assert(InVals[i].getNode() &&
7359 "LowerFormalArguments emitted a null value!");
7360 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7361 "LowerFormalArguments emitted a value with the wrong type!");
7365 // Update the DAG with the new chain value resulting from argument lowering.
7366 DAG.setRoot(NewRoot);
7368 // Set up the argument values.
7371 if (!FuncInfo->CanLowerReturn) {
7372 // Create a virtual register for the sret pointer, and put in a copy
7373 // from the sret argument into it.
7374 SmallVector<EVT, 1> ValueVTs;
7375 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7376 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7377 MVT VT = ValueVTs[0].getSimpleVT();
7378 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7379 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7380 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7381 RegVT, VT, nullptr, AssertOp);
7383 MachineFunction& MF = SDB->DAG.getMachineFunction();
7384 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7385 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7386 FuncInfo->DemoteRegister = SRetReg;
7388 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7389 DAG.setRoot(NewRoot);
7391 // i indexes lowered arguments. Bump it past the hidden sret argument.
7392 // Idx indexes LLVM arguments. Don't touch it.
7396 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7398 SmallVector<SDValue, 4> ArgValues;
7399 SmallVector<EVT, 4> ValueVTs;
7400 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7401 unsigned NumValues = ValueVTs.size();
7403 // If this argument is unused then remember its value. It is used to generate
7404 // debugging information.
7405 if (I->use_empty() && NumValues) {
7406 SDB->setUnusedArgValue(I, InVals[i]);
7408 // Also remember any frame index for use in FastISel.
7409 if (FrameIndexSDNode *FI =
7410 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7411 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7414 for (unsigned Val = 0; Val != NumValues; ++Val) {
7415 EVT VT = ValueVTs[Val];
7416 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7417 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7419 if (!I->use_empty()) {
7420 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7421 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7422 AssertOp = ISD::AssertSext;
7423 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7424 AssertOp = ISD::AssertZext;
7426 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7427 NumParts, PartVT, VT,
7428 nullptr, AssertOp));
7434 // We don't need to do anything else for unused arguments.
7435 if (ArgValues.empty())
7438 // Note down frame index.
7439 if (FrameIndexSDNode *FI =
7440 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7441 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7443 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7444 SDB->getCurSDLoc());
7446 SDB->setValue(I, Res);
7447 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7448 if (LoadSDNode *LNode =
7449 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7450 if (FrameIndexSDNode *FI =
7451 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7452 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7455 // If this argument is live outside of the entry block, insert a copy from
7456 // wherever we got it to the vreg that other BB's will reference it as.
7457 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7458 // If we can, though, try to skip creating an unnecessary vreg.
7459 // FIXME: This isn't very clean... it would be nice to make this more
7460 // general. It's also subtly incompatible with the hacks FastISel
7462 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7463 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7464 FuncInfo->ValueMap[I] = Reg;
7468 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7469 FuncInfo->InitializeRegForValue(I);
7470 SDB->CopyToExportRegsIfNeeded(I);
7474 assert(i == InVals.size() && "Argument register count mismatch!");
7476 // Finally, if the target has anything special to do, allow it to do so.
7477 EmitFunctionEntryCode();
7480 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7481 /// ensure constants are generated when needed. Remember the virtual registers
7482 /// that need to be added to the Machine PHI nodes as input. We cannot just
7483 /// directly add them, because expansion might result in multiple MBB's for one
7484 /// BB. As such, the start of the BB might correspond to a different MBB than
7488 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7489 const TerminatorInst *TI = LLVMBB->getTerminator();
7491 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7493 // Check PHI nodes in successors that expect a value to be available from this
7495 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7496 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7497 if (!isa<PHINode>(SuccBB->begin())) continue;
7498 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7500 // If this terminator has multiple identical successors (common for
7501 // switches), only handle each succ once.
7502 if (!SuccsHandled.insert(SuccMBB).second)
7505 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7507 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7508 // nodes and Machine PHI nodes, but the incoming operands have not been
7510 for (BasicBlock::const_iterator I = SuccBB->begin();
7511 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7512 // Ignore dead phi's.
7513 if (PN->use_empty()) continue;
7516 if (PN->getType()->isEmptyTy())
7520 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7522 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7523 unsigned &RegOut = ConstantsOut[C];
7525 RegOut = FuncInfo.CreateRegs(C->getType());
7526 CopyValueToVirtualRegister(C, RegOut);
7530 DenseMap<const Value *, unsigned>::iterator I =
7531 FuncInfo.ValueMap.find(PHIOp);
7532 if (I != FuncInfo.ValueMap.end())
7535 assert(isa<AllocaInst>(PHIOp) &&
7536 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7537 "Didn't codegen value into a register!??");
7538 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7539 CopyValueToVirtualRegister(PHIOp, Reg);
7543 // Remember that this register needs to added to the machine PHI node as
7544 // the input for this MBB.
7545 SmallVector<EVT, 4> ValueVTs;
7546 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7547 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7548 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7549 EVT VT = ValueVTs[vti];
7550 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7551 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7552 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7553 Reg += NumRegisters;
7558 ConstantsOut.clear();
7561 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7564 SelectionDAGBuilder::StackProtectorDescriptor::
7565 AddSuccessorMBB(const BasicBlock *BB,
7566 MachineBasicBlock *ParentMBB,
7568 MachineBasicBlock *SuccMBB) {
7569 // If SuccBB has not been created yet, create it.
7571 MachineFunction *MF = ParentMBB->getParent();
7572 MachineFunction::iterator BBI = ParentMBB;
7573 SuccMBB = MF->CreateMachineBasicBlock(BB);
7574 MF->insert(++BBI, SuccMBB);
7576 // Add it as a successor of ParentMBB.
7577 ParentMBB->addSuccessor(
7578 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7582 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7583 MachineFunction::iterator I = MBB;
7584 if (++I == FuncInfo.MF->end())
7589 /// During lowering new call nodes can be created (such as memset, etc.).
7590 /// Those will become new roots of the current DAG, but complications arise
7591 /// when they are tail calls. In such cases, the call lowering will update
7592 /// the root, but the builder still needs to know that a tail call has been
7593 /// lowered in order to avoid generating an additional return.
7594 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7595 // If the node is null, we do have a tail call.
7596 if (MaybeTC.getNode() != nullptr)
7597 DAG.setRoot(MaybeTC);
7602 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7603 unsigned *TotalCases, unsigned First,
7605 assert(Last >= First);
7606 assert(TotalCases[Last] >= TotalCases[First]);
7608 APInt LowCase = Clusters[First].Low->getValue();
7609 APInt HighCase = Clusters[Last].High->getValue();
7610 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7612 // FIXME: A range of consecutive cases has 100% density, but only requires one
7613 // comparison to lower. We should discriminate against such consecutive ranges
7616 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7617 uint64_t Range = Diff + 1;
7620 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7622 assert(NumCases < UINT64_MAX / 100);
7623 assert(Range >= NumCases);
7625 return NumCases * 100 >= Range * MinJumpTableDensity;
7628 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7629 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7630 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7633 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7634 unsigned First, unsigned Last,
7635 const SwitchInst *SI,
7636 MachineBasicBlock *DefaultMBB,
7637 CaseCluster &JTCluster) {
7638 assert(First <= Last);
7640 uint32_t Weight = 0;
7641 unsigned NumCmps = 0;
7642 std::vector<MachineBasicBlock*> Table;
7643 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7644 for (unsigned I = First; I <= Last; ++I) {
7645 assert(Clusters[I].Kind == CC_Range);
7646 Weight += Clusters[I].Weight;
7647 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7648 APInt Low = Clusters[I].Low->getValue();
7649 APInt High = Clusters[I].High->getValue();
7650 NumCmps += (Low == High) ? 1 : 2;
7652 // Fill the gap between this and the previous cluster.
7653 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7654 assert(PreviousHigh.slt(Low));
7655 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7656 for (uint64_t J = 0; J < Gap; J++)
7657 Table.push_back(DefaultMBB);
7659 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7660 for (uint64_t J = 0; J < ClusterSize; ++J)
7661 Table.push_back(Clusters[I].MBB);
7662 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7665 unsigned NumDests = JTWeights.size();
7666 if (isSuitableForBitTests(NumDests, NumCmps,
7667 Clusters[First].Low->getValue(),
7668 Clusters[Last].High->getValue())) {
7669 // Clusters[First..Last] should be lowered as bit tests instead.
7673 // Create the MBB that will load from and jump through the table.
7674 // Note: We create it here, but it's not inserted into the function yet.
7675 MachineFunction *CurMF = FuncInfo.MF;
7676 MachineBasicBlock *JumpTableMBB =
7677 CurMF->CreateMachineBasicBlock(SI->getParent());
7679 // Add successors. Note: use table order for determinism.
7680 SmallPtrSet<MachineBasicBlock *, 8> Done;
7681 for (MachineBasicBlock *Succ : Table) {
7682 if (Done.count(Succ))
7684 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7688 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7689 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7690 ->createJumpTableIndex(Table);
7692 // Set up the jump table info.
7693 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7694 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7695 Clusters[Last].High->getValue(), SI->getCondition(),
7697 JTCases.emplace_back(std::move(JTH), std::move(JT));
7699 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7700 JTCases.size() - 1, Weight);
7704 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7705 const SwitchInst *SI,
7706 MachineBasicBlock *DefaultMBB) {
7708 // Clusters must be non-empty, sorted, and only contain Range clusters.
7709 assert(!Clusters.empty());
7710 for (CaseCluster &C : Clusters)
7711 assert(C.Kind == CC_Range);
7712 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7713 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7717 if (!areJTsAllowed(TLI))
7720 const int64_t N = Clusters.size();
7721 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7723 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7724 SmallVector<unsigned, 8> TotalCases(N);
7726 for (unsigned i = 0; i < N; ++i) {
7727 APInt Hi = Clusters[i].High->getValue();
7728 APInt Lo = Clusters[i].Low->getValue();
7729 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7731 TotalCases[i] += TotalCases[i - 1];
7734 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7735 // Cheap case: the whole range might be suitable for jump table.
7736 CaseCluster JTCluster;
7737 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7738 Clusters[0] = JTCluster;
7744 // The algorithm below is not suitable for -O0.
7745 if (TM.getOptLevel() == CodeGenOpt::None)
7748 // Split Clusters into minimum number of dense partitions. The algorithm uses
7749 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7750 // for the Case Statement'" (1994), but builds the MinPartitions array in
7751 // reverse order to make it easier to reconstruct the partitions in ascending
7752 // order. In the choice between two optimal partitionings, it picks the one
7753 // which yields more jump tables.
7755 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7756 SmallVector<unsigned, 8> MinPartitions(N);
7757 // LastElement[i] is the last element of the partition starting at i.
7758 SmallVector<unsigned, 8> LastElement(N);
7759 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7760 SmallVector<unsigned, 8> NumTables(N);
7762 // Base case: There is only one way to partition Clusters[N-1].
7763 MinPartitions[N - 1] = 1;
7764 LastElement[N - 1] = N - 1;
7765 assert(MinJumpTableSize > 1);
7766 NumTables[N - 1] = 0;
7768 // Note: loop indexes are signed to avoid underflow.
7769 for (int64_t i = N - 2; i >= 0; i--) {
7770 // Find optimal partitioning of Clusters[i..N-1].
7771 // Baseline: Put Clusters[i] into a partition on its own.
7772 MinPartitions[i] = MinPartitions[i + 1] + 1;
7774 NumTables[i] = NumTables[i + 1];
7776 // Search for a solution that results in fewer partitions.
7777 for (int64_t j = N - 1; j > i; j--) {
7778 // Try building a partition from Clusters[i..j].
7779 if (isDense(Clusters, &TotalCases[0], i, j)) {
7780 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7781 bool IsTable = j - i + 1 >= MinJumpTableSize;
7782 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7784 // If this j leads to fewer partitions, or same number of partitions
7785 // with more lookup tables, it is a better partitioning.
7786 if (NumPartitions < MinPartitions[i] ||
7787 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7788 MinPartitions[i] = NumPartitions;
7790 NumTables[i] = Tables;
7796 // Iterate over the partitions, replacing some with jump tables in-place.
7797 unsigned DstIndex = 0;
7798 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7799 Last = LastElement[First];
7800 assert(Last >= First);
7801 assert(DstIndex <= First);
7802 unsigned NumClusters = Last - First + 1;
7804 CaseCluster JTCluster;
7805 if (NumClusters >= MinJumpTableSize &&
7806 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7807 Clusters[DstIndex++] = JTCluster;
7809 for (unsigned I = First; I <= Last; ++I)
7810 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7813 Clusters.resize(DstIndex);
7816 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7817 // FIXME: Using the pointer type doesn't seem ideal.
7818 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7819 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7823 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7826 const APInt &High) {
7827 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7828 // range of cases both require only one branch to lower. Just looking at the
7829 // number of clusters and destinations should be enough to decide whether to
7832 // To lower a range with bit tests, the range must fit the bitwidth of a
7834 if (!rangeFitsInWord(Low, High))
7837 // Decide whether it's profitable to lower this range with bit tests. Each
7838 // destination requires a bit test and branch, and there is an overall range
7839 // check branch. For a small number of clusters, separate comparisons might be
7840 // cheaper, and for many destinations, splitting the range might be better.
7841 return (NumDests == 1 && NumCmps >= 3) ||
7842 (NumDests == 2 && NumCmps >= 5) ||
7843 (NumDests == 3 && NumCmps >= 6);
7846 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7847 unsigned First, unsigned Last,
7848 const SwitchInst *SI,
7849 CaseCluster &BTCluster) {
7850 assert(First <= Last);
7854 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7855 unsigned NumCmps = 0;
7856 for (int64_t I = First; I <= Last; ++I) {
7857 assert(Clusters[I].Kind == CC_Range);
7858 Dests.set(Clusters[I].MBB->getNumber());
7859 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7861 unsigned NumDests = Dests.count();
7863 APInt Low = Clusters[First].Low->getValue();
7864 APInt High = Clusters[Last].High->getValue();
7865 assert(Low.slt(High));
7867 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7873 const int BitWidth = DAG.getTargetLoweringInfo()
7874 .getPointerTy(DAG.getDataLayout())
7876 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7878 // Check if the clusters cover a contiguous range such that no value in the
7879 // range will jump to the default statement.
7880 bool ContiguousRange = true;
7881 for (int64_t I = First + 1; I <= Last; ++I) {
7882 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7883 ContiguousRange = false;
7888 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7889 // Optimize the case where all the case values fit in a word without having
7890 // to subtract minValue. In this case, we can optimize away the subtraction.
7891 LowBound = APInt::getNullValue(Low.getBitWidth());
7893 ContiguousRange = false;
7896 CmpRange = High - Low;
7900 uint32_t TotalWeight = 0;
7901 for (unsigned i = First; i <= Last; ++i) {
7902 // Find the CaseBits for this destination.
7904 for (j = 0; j < CBV.size(); ++j)
7905 if (CBV[j].BB == Clusters[i].MBB)
7907 if (j == CBV.size())
7908 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7909 CaseBits *CB = &CBV[j];
7911 // Update Mask, Bits and ExtraWeight.
7912 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7913 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7914 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7915 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7916 CB->Bits += Hi - Lo + 1;
7917 CB->ExtraWeight += Clusters[i].Weight;
7918 TotalWeight += Clusters[i].Weight;
7919 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7923 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7924 // Sort by weight first, number of bits second.
7925 if (a.ExtraWeight != b.ExtraWeight)
7926 return a.ExtraWeight > b.ExtraWeight;
7927 return a.Bits > b.Bits;
7930 for (auto &CB : CBV) {
7931 MachineBasicBlock *BitTestBB =
7932 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7933 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7935 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7936 SI->getCondition(), -1U, MVT::Other, false,
7937 ContiguousRange, nullptr, nullptr, std::move(BTI),
7940 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7941 BitTestCases.size() - 1, TotalWeight);
7945 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7946 const SwitchInst *SI) {
7947 // Partition Clusters into as few subsets as possible, where each subset has a
7948 // range that fits in a machine word and has <= 3 unique destinations.
7951 // Clusters must be sorted and contain Range or JumpTable clusters.
7952 assert(!Clusters.empty());
7953 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7954 for (const CaseCluster &C : Clusters)
7955 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7956 for (unsigned i = 1; i < Clusters.size(); ++i)
7957 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7960 // The algorithm below is not suitable for -O0.
7961 if (TM.getOptLevel() == CodeGenOpt::None)
7964 // If target does not have legal shift left, do not emit bit tests at all.
7965 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7966 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7967 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7970 int BitWidth = PTy.getSizeInBits();
7971 const int64_t N = Clusters.size();
7973 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7974 SmallVector<unsigned, 8> MinPartitions(N);
7975 // LastElement[i] is the last element of the partition starting at i.
7976 SmallVector<unsigned, 8> LastElement(N);
7978 // FIXME: This might not be the best algorithm for finding bit test clusters.
7980 // Base case: There is only one way to partition Clusters[N-1].
7981 MinPartitions[N - 1] = 1;
7982 LastElement[N - 1] = N - 1;
7984 // Note: loop indexes are signed to avoid underflow.
7985 for (int64_t i = N - 2; i >= 0; --i) {
7986 // Find optimal partitioning of Clusters[i..N-1].
7987 // Baseline: Put Clusters[i] into a partition on its own.
7988 MinPartitions[i] = MinPartitions[i + 1] + 1;
7991 // Search for a solution that results in fewer partitions.
7992 // Note: the search is limited by BitWidth, reducing time complexity.
7993 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7994 // Try building a partition from Clusters[i..j].
7997 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7998 Clusters[j].High->getValue()))
8001 // Check nbr of destinations and cluster types.
8002 // FIXME: This works, but doesn't seem very efficient.
8003 bool RangesOnly = true;
8004 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8005 for (int64_t k = i; k <= j; k++) {
8006 if (Clusters[k].Kind != CC_Range) {
8010 Dests.set(Clusters[k].MBB->getNumber());
8012 if (!RangesOnly || Dests.count() > 3)
8015 // Check if it's a better partition.
8016 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8017 if (NumPartitions < MinPartitions[i]) {
8018 // Found a better partition.
8019 MinPartitions[i] = NumPartitions;
8025 // Iterate over the partitions, replacing with bit-test clusters in-place.
8026 unsigned DstIndex = 0;
8027 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8028 Last = LastElement[First];
8029 assert(First <= Last);
8030 assert(DstIndex <= First);
8032 CaseCluster BitTestCluster;
8033 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8034 Clusters[DstIndex++] = BitTestCluster;
8036 size_t NumClusters = Last - First + 1;
8037 std::memmove(&Clusters[DstIndex], &Clusters[First],
8038 sizeof(Clusters[0]) * NumClusters);
8039 DstIndex += NumClusters;
8042 Clusters.resize(DstIndex);
8045 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8046 MachineBasicBlock *SwitchMBB,
8047 MachineBasicBlock *DefaultMBB) {
8048 MachineFunction *CurMF = FuncInfo.MF;
8049 MachineBasicBlock *NextMBB = nullptr;
8050 MachineFunction::iterator BBI = W.MBB;
8051 if (++BBI != FuncInfo.MF->end())
8054 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8056 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8058 if (Size == 2 && W.MBB == SwitchMBB) {
8059 // If any two of the cases has the same destination, and if one value
8060 // is the same as the other, but has one bit unset that the other has set,
8061 // use bit manipulation to do two compares at once. For example:
8062 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8063 // TODO: This could be extended to merge any 2 cases in switches with 3
8065 // TODO: Handle cases where W.CaseBB != SwitchBB.
8066 CaseCluster &Small = *W.FirstCluster;
8067 CaseCluster &Big = *W.LastCluster;
8069 if (Small.Low == Small.High && Big.Low == Big.High &&
8070 Small.MBB == Big.MBB) {
8071 const APInt &SmallValue = Small.Low->getValue();
8072 const APInt &BigValue = Big.Low->getValue();
8074 // Check that there is only one bit different.
8075 APInt CommonBit = BigValue ^ SmallValue;
8076 if (CommonBit.isPowerOf2()) {
8077 SDValue CondLHS = getValue(Cond);
8078 EVT VT = CondLHS.getValueType();
8079 SDLoc DL = getCurSDLoc();
8081 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8082 DAG.getConstant(CommonBit, DL, VT));
8083 SDValue Cond = DAG.getSetCC(
8084 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8087 // Update successor info.
8088 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8089 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8090 addSuccessorWithWeight(
8091 SwitchMBB, DefaultMBB,
8092 // The default destination is the first successor in IR.
8093 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8096 // Insert the true branch.
8098 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8099 DAG.getBasicBlock(Small.MBB));
8100 // Insert the false branch.
8101 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8102 DAG.getBasicBlock(DefaultMBB));
8104 DAG.setRoot(BrCond);
8110 if (TM.getOptLevel() != CodeGenOpt::None) {
8111 // Order cases by weight so the most likely case will be checked first.
8112 std::sort(W.FirstCluster, W.LastCluster + 1,
8113 [](const CaseCluster &a, const CaseCluster &b) {
8114 return a.Weight > b.Weight;
8117 // Rearrange the case blocks so that the last one falls through if possible
8118 // without without changing the order of weights.
8119 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8121 if (I->Weight > W.LastCluster->Weight)
8123 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8124 std::swap(*I, *W.LastCluster);
8130 // Compute total weight.
8131 uint32_t DefaultWeight = W.DefaultWeight;
8132 uint32_t UnhandledWeights = DefaultWeight;
8133 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8134 UnhandledWeights += I->Weight;
8135 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8138 MachineBasicBlock *CurMBB = W.MBB;
8139 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8140 MachineBasicBlock *Fallthrough;
8141 if (I == W.LastCluster) {
8142 // For the last cluster, fall through to the default destination.
8143 Fallthrough = DefaultMBB;
8145 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8146 CurMF->insert(BBI, Fallthrough);
8147 // Put Cond in a virtual register to make it available from the new blocks.
8148 ExportFromCurrentBlock(Cond);
8150 UnhandledWeights -= I->Weight;
8153 case CC_JumpTable: {
8154 // FIXME: Optimize away range check based on pivot comparisons.
8155 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8156 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8158 // The jump block hasn't been inserted yet; insert it here.
8159 MachineBasicBlock *JumpMBB = JT->MBB;
8160 CurMF->insert(BBI, JumpMBB);
8162 uint32_t JumpWeight = I->Weight;
8163 uint32_t FallthroughWeight = UnhandledWeights;
8165 // If the default statement is a target of the jump table, we evenly
8166 // distribute the default weight to successors of CurMBB. Also update
8167 // the weight on the edge from JumpMBB to Fallthrough.
8168 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8169 SE = JumpMBB->succ_end();
8171 if (*SI == DefaultMBB) {
8172 JumpWeight += DefaultWeight / 2;
8173 FallthroughWeight -= DefaultWeight / 2;
8174 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8179 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8180 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8182 // The jump table header will be inserted in our current block, do the
8183 // range check, and fall through to our fallthrough block.
8184 JTH->HeaderBB = CurMBB;
8185 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8187 // If we're in the right place, emit the jump table header right now.
8188 if (CurMBB == SwitchMBB) {
8189 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8190 JTH->Emitted = true;
8195 // FIXME: Optimize away range check based on pivot comparisons.
8196 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8198 // The bit test blocks haven't been inserted yet; insert them here.
8199 for (BitTestCase &BTC : BTB->Cases)
8200 CurMF->insert(BBI, BTC.ThisBB);
8202 // Fill in fields of the BitTestBlock.
8203 BTB->Parent = CurMBB;
8204 BTB->Default = Fallthrough;
8206 BTB->DefaultWeight = UnhandledWeights;
8207 // If the cases in bit test don't form a contiguous range, we evenly
8208 // distribute the weight on the edge to Fallthrough to two successors
8210 if (!BTB->ContiguousRange) {
8211 BTB->Weight += DefaultWeight / 2;
8212 BTB->DefaultWeight -= DefaultWeight / 2;
8215 // If we're in the right place, emit the bit test header right now.
8216 if (CurMBB == SwitchMBB) {
8217 visitBitTestHeader(*BTB, SwitchMBB);
8218 BTB->Emitted = true;
8223 const Value *RHS, *LHS, *MHS;
8225 if (I->Low == I->High) {
8226 // Check Cond == I->Low.
8232 // Check I->Low <= Cond <= I->High.
8239 // The false weight is the sum of all unhandled cases.
8240 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8243 if (CurMBB == SwitchMBB)
8244 visitSwitchCase(CB, SwitchMBB);
8246 SwitchCases.push_back(CB);
8251 CurMBB = Fallthrough;
8255 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8256 CaseClusterIt First,
8257 CaseClusterIt Last) {
8258 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8259 if (X.Weight != CC.Weight)
8260 return X.Weight > CC.Weight;
8262 // Ties are broken by comparing the case value.
8263 return X.Low->getValue().slt(CC.Low->getValue());
8267 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8268 const SwitchWorkListItem &W,
8270 MachineBasicBlock *SwitchMBB) {
8271 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8272 "Clusters not sorted?");
8274 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8276 // Balance the tree based on branch weights to create a near-optimal (in terms
8277 // of search time given key frequency) binary search tree. See e.g. Kurt
8278 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8279 CaseClusterIt LastLeft = W.FirstCluster;
8280 CaseClusterIt FirstRight = W.LastCluster;
8281 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8282 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8284 // Move LastLeft and FirstRight towards each other from opposite directions to
8285 // find a partitioning of the clusters which balances the weight on both
8286 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8287 // taken to ensure 0-weight nodes are distributed evenly.
8289 while (LastLeft + 1 < FirstRight) {
8290 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8291 LeftWeight += (++LastLeft)->Weight;
8293 RightWeight += (--FirstRight)->Weight;
8298 // Our binary search tree differs from a typical BST in that ours can have up
8299 // to three values in each leaf. The pivot selection above doesn't take that
8300 // into account, which means the tree might require more nodes and be less
8301 // efficient. We compensate for this here.
8303 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8304 unsigned NumRight = W.LastCluster - FirstRight + 1;
8306 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8307 // If one side has less than 3 clusters, and the other has more than 3,
8308 // consider taking a cluster from the other side.
8310 if (NumLeft < NumRight) {
8311 // Consider moving the first cluster on the right to the left side.
8312 CaseCluster &CC = *FirstRight;
8313 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8314 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8315 if (LeftSideRank <= RightSideRank) {
8316 // Moving the cluster to the left does not demote it.
8322 assert(NumRight < NumLeft);
8323 // Consider moving the last element on the left to the right side.
8324 CaseCluster &CC = *LastLeft;
8325 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8326 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8327 if (RightSideRank <= LeftSideRank) {
8328 // Moving the cluster to the right does not demot it.
8338 assert(LastLeft + 1 == FirstRight);
8339 assert(LastLeft >= W.FirstCluster);
8340 assert(FirstRight <= W.LastCluster);
8342 // Use the first element on the right as pivot since we will make less-than
8343 // comparisons against it.
8344 CaseClusterIt PivotCluster = FirstRight;
8345 assert(PivotCluster > W.FirstCluster);
8346 assert(PivotCluster <= W.LastCluster);
8348 CaseClusterIt FirstLeft = W.FirstCluster;
8349 CaseClusterIt LastRight = W.LastCluster;
8351 const ConstantInt *Pivot = PivotCluster->Low;
8353 // New blocks will be inserted immediately after the current one.
8354 MachineFunction::iterator BBI = W.MBB;
8357 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8358 // we can branch to its destination directly if it's squeezed exactly in
8359 // between the known lower bound and Pivot - 1.
8360 MachineBasicBlock *LeftMBB;
8361 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8362 FirstLeft->Low == W.GE &&
8363 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8364 LeftMBB = FirstLeft->MBB;
8366 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8367 FuncInfo.MF->insert(BBI, LeftMBB);
8369 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8370 // Put Cond in a virtual register to make it available from the new blocks.
8371 ExportFromCurrentBlock(Cond);
8374 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8375 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8376 // directly if RHS.High equals the current upper bound.
8377 MachineBasicBlock *RightMBB;
8378 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8379 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8380 RightMBB = FirstRight->MBB;
8382 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8383 FuncInfo.MF->insert(BBI, RightMBB);
8385 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8386 // Put Cond in a virtual register to make it available from the new blocks.
8387 ExportFromCurrentBlock(Cond);
8390 // Create the CaseBlock record that will be used to lower the branch.
8391 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8392 LeftWeight, RightWeight);
8394 if (W.MBB == SwitchMBB)
8395 visitSwitchCase(CB, SwitchMBB);
8397 SwitchCases.push_back(CB);
8400 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8401 // Extract cases from the switch.
8402 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8403 CaseClusterVector Clusters;
8404 Clusters.reserve(SI.getNumCases());
8405 for (auto I : SI.cases()) {
8406 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8407 const ConstantInt *CaseVal = I.getCaseValue();
8409 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8410 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8413 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8415 // Cluster adjacent cases with the same destination. We do this at all
8416 // optimization levels because it's cheap to do and will make codegen faster
8417 // if there are many clusters.
8418 sortAndRangeify(Clusters);
8420 if (TM.getOptLevel() != CodeGenOpt::None) {
8421 // Replace an unreachable default with the most popular destination.
8422 // FIXME: Exploit unreachable default more aggressively.
8423 bool UnreachableDefault =
8424 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8425 if (UnreachableDefault && !Clusters.empty()) {
8426 DenseMap<const BasicBlock *, unsigned> Popularity;
8427 unsigned MaxPop = 0;
8428 const BasicBlock *MaxBB = nullptr;
8429 for (auto I : SI.cases()) {
8430 const BasicBlock *BB = I.getCaseSuccessor();
8431 if (++Popularity[BB] > MaxPop) {
8432 MaxPop = Popularity[BB];
8437 assert(MaxPop > 0 && MaxBB);
8438 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8440 // Remove cases that were pointing to the destination that is now the
8442 CaseClusterVector New;
8443 New.reserve(Clusters.size());
8444 for (CaseCluster &CC : Clusters) {
8445 if (CC.MBB != DefaultMBB)
8448 Clusters = std::move(New);
8452 // If there is only the default destination, jump there directly.
8453 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8454 if (Clusters.empty()) {
8455 SwitchMBB->addSuccessor(DefaultMBB);
8456 if (DefaultMBB != NextBlock(SwitchMBB)) {
8457 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8458 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8463 findJumpTables(Clusters, &SI, DefaultMBB);
8464 findBitTestClusters(Clusters, &SI);
8467 dbgs() << "Case clusters: ";
8468 for (const CaseCluster &C : Clusters) {
8469 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8470 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8472 C.Low->getValue().print(dbgs(), true);
8473 if (C.Low != C.High) {
8475 C.High->getValue().print(dbgs(), true);
8482 assert(!Clusters.empty());
8483 SwitchWorkList WorkList;
8484 CaseClusterIt First = Clusters.begin();
8485 CaseClusterIt Last = Clusters.end() - 1;
8486 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8487 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8489 while (!WorkList.empty()) {
8490 SwitchWorkListItem W = WorkList.back();
8491 WorkList.pop_back();
8492 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8494 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8495 // For optimized builds, lower large range as a balanced binary tree.
8496 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8500 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);