1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
202 ValueVT.bitsLT(PartEVT)) {
203 // For an FP value in an integer part, we need to truncate to the right
205 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
206 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
209 if (PartEVT.isInteger() && ValueVT.isInteger()) {
210 if (ValueVT.bitsLT(PartEVT)) {
211 // For a truncate, see if we have any information to
212 // indicate whether the truncated bits will always be
213 // zero or sign-extension.
214 if (AssertOp != ISD::DELETED_NODE)
215 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
216 DAG.getValueType(ValueVT));
217 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
219 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
223 // FP_ROUND's are always exact here.
224 if (ValueVT.bitsLT(Val.getValueType()))
226 ISD::FP_ROUND, DL, ValueVT, Val,
227 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
232 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
233 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
235 llvm_unreachable("Unknown mismatch!");
238 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
239 const Twine &ErrMsg) {
240 const Instruction *I = dyn_cast_or_null<Instruction>(V);
242 return Ctx.emitError(ErrMsg);
244 const char *AsmError = ", possible invalid constraint for vector type";
245 if (const CallInst *CI = dyn_cast<CallInst>(I))
246 if (isa<InlineAsm>(CI->getCalledValue()))
247 return Ctx.emitError(I, ErrMsg + AsmError);
249 return Ctx.emitError(I, ErrMsg);
252 /// getCopyFromPartsVector - Create a value that contains the specified legal
253 /// parts combined into the value they represent. If the parts combine to a
254 /// type larger then ValueVT then AssertOp can be used to specify whether the
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
256 /// ValueVT (ISD::AssertSext).
257 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
258 const SDValue *Parts, unsigned NumParts,
259 MVT PartVT, EVT ValueVT, const Value *V) {
260 assert(ValueVT.isVector() && "Not a vector value");
261 assert(NumParts > 0 && "No parts to assemble!");
262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
263 SDValue Val = Parts[0];
265 // Handle a multi-element vector.
269 unsigned NumIntermediates;
271 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
272 NumIntermediates, RegisterVT);
273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
274 NumParts = NumRegs; // Silence a compiler warning.
275 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
276 assert(RegisterVT.getSizeInBits() ==
277 Parts[0].getSimpleValueType().getSizeInBits() &&
278 "Part type sizes don't match!");
280 // Assemble the parts into intermediate operands.
281 SmallVector<SDValue, 8> Ops(NumIntermediates);
282 if (NumIntermediates == NumParts) {
283 // If the register was not expanded, truncate or copy the value,
285 for (unsigned i = 0; i != NumParts; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
287 PartVT, IntermediateVT, V);
288 } else if (NumParts > 0) {
289 // If the intermediate type was expanded, build the intermediate
290 // operands from the parts.
291 assert(NumParts % NumIntermediates == 0 &&
292 "Must expand into a divisible number of parts!");
293 unsigned Factor = NumParts / NumIntermediates;
294 for (unsigned i = 0; i != NumIntermediates; ++i)
295 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
296 PartVT, IntermediateVT, V);
299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
300 // intermediate operands.
301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
306 // There is now one part, held in Val. Correct it to match ValueVT.
307 EVT PartEVT = Val.getValueType();
309 if (PartEVT == ValueVT)
312 if (PartEVT.isVector()) {
313 // If the element type of the source/dest vectors are the same, but the
314 // parts vector has more elements than the value vector, then we have a
315 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
317 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
318 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
319 "Cannot narrow, it would be a lossy transformation");
321 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
322 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
325 // Vector/Vector bitcast.
326 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
327 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
329 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
330 "Cannot handle this kind of promotion");
331 // Promoted vector extract
332 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
336 // Trivial bitcast if the types are the same size and the destination
337 // vector type is legal.
338 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
339 TLI.isTypeLegal(ValueVT))
340 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
342 // Handle cases such as i8 -> <1 x i1>
343 if (ValueVT.getVectorNumElements() != 1) {
344 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
345 "non-trivial scalar-to-vector conversion");
346 return DAG.getUNDEF(ValueVT);
349 if (ValueVT.getVectorNumElements() == 1 &&
350 ValueVT.getVectorElementType() != PartEVT)
351 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
353 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
356 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
357 SDValue Val, SDValue *Parts, unsigned NumParts,
358 MVT PartVT, const Value *V);
360 /// getCopyToParts - Create a series of nodes that contain the specified value
361 /// split into legal parts. If the parts contain more bits than Val, then, for
362 /// integers, ExtendKind can be used to specify how to generate the extra bits.
363 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
364 SDValue Val, SDValue *Parts, unsigned NumParts,
365 MVT PartVT, const Value *V,
366 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
367 EVT ValueVT = Val.getValueType();
369 // Handle the vector case separately.
370 if (ValueVT.isVector())
371 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
373 unsigned PartBits = PartVT.getSizeInBits();
374 unsigned OrigNumParts = NumParts;
375 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
376 "Copying to an illegal type!");
381 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
382 EVT PartEVT = PartVT;
383 if (PartEVT == ValueVT) {
384 assert(NumParts == 1 && "No-op copy with multiple parts!");
389 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
390 // If the parts cover more bits than the value has, promote the value.
391 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
392 assert(NumParts == 1 && "Do not know what to promote to!");
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
395 if (ValueVT.isFloatingPoint()) {
396 // FP values need to be bitcast, then extended if they are being put
397 // into a larger container.
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
399 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 } else if (PartBits == ValueVT.getSizeInBits()) {
410 // Different types of the same size.
411 assert(NumParts == 1 && PartEVT != ValueVT);
412 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
413 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
414 // If the parts cover less bits than value has, truncate the value.
415 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
416 ValueVT.isInteger() &&
417 "Unknown mismatch!");
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
419 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
420 if (PartVT == MVT::x86mmx)
421 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 if (PartEVT != ValueVT)
431 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
432 "scalar-to-vector conversion failed");
438 // Expand the value into multiple parts.
439 if (NumParts & (NumParts - 1)) {
440 // The number of parts is not a power of 2. Split off and copy the tail.
441 assert(PartVT.isInteger() && ValueVT.isInteger() &&
442 "Do not know what to expand to!");
443 unsigned RoundParts = 1 << Log2_32(NumParts);
444 unsigned RoundBits = RoundParts * PartBits;
445 unsigned OddParts = NumParts - RoundParts;
446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
447 DAG.getIntPtrConstant(RoundBits, DL));
448 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
450 if (DAG.getDataLayout().isBigEndian())
451 // The odd parts were reversed by getCopyToParts - unreverse them.
452 std::reverse(Parts + RoundParts, Parts + NumParts);
454 NumParts = RoundParts;
455 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
456 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
459 // The number of parts is a power of 2. Repeatedly bisect the value using
461 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
462 EVT::getIntegerVT(*DAG.getContext(),
463 ValueVT.getSizeInBits()),
466 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
467 for (unsigned i = 0; i < NumParts; i += StepSize) {
468 unsigned ThisBits = StepSize * PartBits / 2;
469 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
470 SDValue &Part0 = Parts[i];
471 SDValue &Part1 = Parts[i+StepSize/2];
473 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
474 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
475 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
476 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
478 if (ThisBits == PartBits && ThisVT != PartVT) {
479 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
480 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
485 if (DAG.getDataLayout().isBigEndian())
486 std::reverse(Parts, Parts + OrigNumParts);
490 /// getCopyToPartsVector - Create a series of nodes that contain the specified
491 /// value split into legal parts.
492 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
493 SDValue Val, SDValue *Parts, unsigned NumParts,
494 MVT PartVT, const Value *V) {
495 EVT ValueVT = Val.getValueType();
496 assert(ValueVT.isVector() && "Not a vector");
497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
500 EVT PartEVT = PartVT;
501 if (PartEVT == ValueVT) {
503 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
504 // Bitconvert vector->vector case.
505 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
508 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
509 EVT ElementVT = PartVT.getVectorElementType();
510 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
512 SmallVector<SDValue, 16> Ops;
513 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
514 Ops.push_back(DAG.getNode(
515 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
516 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
518 for (unsigned i = ValueVT.getVectorNumElements(),
519 e = PartVT.getVectorNumElements(); i != e; ++i)
520 Ops.push_back(DAG.getUNDEF(ElementVT));
522 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
524 // FIXME: Use CONCAT for 2x -> 4x.
526 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType().bitsGE(
530 ValueVT.getVectorElementType()) &&
531 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
533 // Promoted vector extract
534 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Vector -> scalar conversion.
537 assert(ValueVT.getVectorNumElements() == 1 &&
538 "Only trivial vector-to-scalar conversions should get here!");
540 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
541 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
543 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
550 // Handle a multi-element vector.
553 unsigned NumIntermediates;
554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
556 NumIntermediates, RegisterVT);
557 unsigned NumElements = ValueVT.getVectorNumElements();
559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
560 NumParts = NumRegs; // Silence a compiler warning.
561 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
563 // Split the vector into intermediate operands.
564 SmallVector<SDValue, 8> Ops(NumIntermediates);
565 for (unsigned i = 0; i != NumIntermediates; ++i) {
566 if (IntermediateVT.isVector())
568 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
569 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
570 TLI.getVectorIdxTy(DAG.getDataLayout())));
572 Ops[i] = DAG.getNode(
573 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
574 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
577 // Split the intermediate operands into legal parts.
578 if (NumParts == NumIntermediates) {
579 // If the register was not expanded, promote or copy the value,
581 for (unsigned i = 0; i != NumParts; ++i)
582 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
583 } else if (NumParts > 0) {
584 // If the intermediate type was expanded, split each the value into
586 assert(NumIntermediates != 0 && "division by zero");
587 assert(NumParts % NumIntermediates == 0 &&
588 "Must expand into a divisible number of parts!");
589 unsigned Factor = NumParts / NumIntermediates;
590 for (unsigned i = 0; i != NumIntermediates; ++i)
591 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
595 RegsForValue::RegsForValue() {}
597 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
601 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
602 const DataLayout &DL, unsigned Reg, Type *Ty) {
603 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
605 for (EVT ValueVT : ValueVTs) {
606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
607 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
608 for (unsigned i = 0; i != NumRegs; ++i)
609 Regs.push_back(Reg + i);
610 RegVTs.push_back(RegisterVT);
615 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
616 /// this value and returns the result as a ValueVT value. This uses
617 /// Chain/Flag as the input and updates them for the output Chain/Flag.
618 /// If the Flag pointer is NULL, no flag is used.
619 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
620 FunctionLoweringInfo &FuncInfo,
622 SDValue &Chain, SDValue *Flag,
623 const Value *V) const {
624 // A Value with type {} or [0 x %t] needs no registers.
625 if (ValueVTs.empty())
628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
630 // Assemble the legal parts into the final values.
631 SmallVector<SDValue, 4> Values(ValueVTs.size());
632 SmallVector<SDValue, 8> Parts;
633 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
634 // Copy the legal parts from the registers.
635 EVT ValueVT = ValueVTs[Value];
636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
637 MVT RegisterVT = RegVTs[Value];
639 Parts.resize(NumRegs);
640 for (unsigned i = 0; i != NumRegs; ++i) {
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
646 *Flag = P.getValue(2);
649 Chain = P.getValue(1);
652 // If the source register was virtual and if we know something about it,
653 // add an assert node.
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
655 !RegisterVT.isInteger() || RegisterVT.isVector())
658 const FunctionLoweringInfo::LiveOutInfo *LOI =
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
663 unsigned RegSize = RegisterVT.getSizeInBits();
664 unsigned NumSignBits = LOI->NumSignBits;
665 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
667 if (NumZeroBits == RegSize) {
668 // The current value is a zero.
669 // Explicitly express that as it would be easier for
670 // optimizations to kick in.
671 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
675 // FIXME: We capture more information than the dag can represent. For
676 // now, just use the tightest assertzext/assertsext possible.
678 EVT FromVT(MVT::Other);
679 if (NumSignBits == RegSize)
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
681 else if (NumZeroBits >= RegSize-1)
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
683 else if (NumSignBits > RegSize-8)
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
685 else if (NumZeroBits >= RegSize-8)
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
687 else if (NumSignBits > RegSize-16)
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
689 else if (NumZeroBits >= RegSize-16)
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
691 else if (NumSignBits > RegSize-32)
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
693 else if (NumZeroBits >= RegSize-32)
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
698 // Add an assertion node.
699 assert(FromVT != MVT::Other);
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
701 RegisterVT, P, DAG.getValueType(FromVT));
704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
705 NumRegs, RegisterVT, ValueVT, V);
710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
713 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
714 /// specified value into the registers specified by this object. This uses
715 /// Chain/Flag as the input and updates them for the output Chain/Flag.
716 /// If the Flag pointer is NULL, no flag is used.
717 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
718 SDValue &Chain, SDValue *Flag, const Value *V,
719 ISD::NodeType PreferredExtendType) const {
720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
721 ISD::NodeType ExtendKind = PreferredExtendType;
723 // Get the list of the values's legal parts.
724 unsigned NumRegs = Regs.size();
725 SmallVector<SDValue, 8> Parts(NumRegs);
726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
727 EVT ValueVT = ValueVTs[Value];
728 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
729 MVT RegisterVT = RegVTs[Value];
731 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
732 ExtendKind = ISD::ZERO_EXTEND;
734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
735 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
739 // Copy the parts into the registers.
740 SmallVector<SDValue, 8> Chains(NumRegs);
741 for (unsigned i = 0; i != NumRegs; ++i) {
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
747 *Flag = Part.getValue(1);
750 Chains[i] = Part.getValue(0);
753 if (NumRegs == 1 || Flag)
754 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
755 // flagged to it. That is the CopyToReg nodes and the user are considered
756 // a single scheduling unit. If we create a TokenFactor and return it as
757 // chain, then the TokenFactor is both a predecessor (operand) of the
758 // user as well as a successor (the TF operands are flagged to the user).
759 // c1, f1 = CopyToReg
760 // c2, f2 = CopyToReg
761 // c3 = TokenFactor c1, c2
764 Chain = Chains[NumRegs-1];
766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
769 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
770 /// operand list. This adds the code marker and includes the number of
771 /// values added into it.
772 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
773 unsigned MatchingIdx, SDLoc dl,
775 std::vector<SDValue> &Ops) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
780 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
783 // Put the register class of the virtual registers in the flag word. That
784 // way, later passes can recompute register class constraints for inline
785 // assembly as well as normal instructions.
786 // Don't do this for tied operands that can use the regclass information
788 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
790 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
793 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
796 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
797 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
798 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
799 MVT RegisterVT = RegVTs[Value];
800 for (unsigned i = 0; i != NumRegs; ++i) {
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
803 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
805 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
806 // If we clobbered the stack pointer, MFI should know about it.
807 assert(DAG.getMachineFunction().getFrameInfo()->
808 hasOpaqueSPAdjustment());
814 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
815 const TargetLibraryInfo *li) {
819 DL = &DAG.getDataLayout();
820 Context = DAG.getContext();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
837 SDNodeOrder = LowestSDNodeOrder;
838 StatepointLowering.clear();
841 /// clearDanglingDebugInfo - Clear the dangling debug information
842 /// map. This function is separated from the clear so that debug
843 /// information that is dangling in a basic block can be properly
844 /// resolved in a different basic block. This allows the
845 /// SelectionDAG to resolve dangling debug information attached
847 void SelectionDAGBuilder::clearDanglingDebugInfo() {
848 DanglingDebugInfoMap.clear();
851 /// getRoot - Return the current virtual root of the Selection DAG,
852 /// flushing any PendingLoad items. This must be done before emitting
853 /// a store or any other node that may need to be ordered after any
854 /// prior load instructions.
856 SDValue SelectionDAGBuilder::getRoot() {
857 if (PendingLoads.empty())
858 return DAG.getRoot();
860 if (PendingLoads.size() == 1) {
861 SDValue Root = PendingLoads[0];
863 PendingLoads.clear();
867 // Otherwise, we have to make a token factor node.
868 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads.clear();
875 /// getControlRoot - Similar to getRoot, but instead of flushing all the
876 /// PendingLoad items, flush all the PendingExports items. It is necessary
877 /// to do this before emitting a terminator instruction.
879 SDValue SelectionDAGBuilder::getControlRoot() {
880 SDValue Root = DAG.getRoot();
882 if (PendingExports.empty())
885 // Turn all of the CopyToReg chains into one factored node.
886 if (Root.getOpcode() != ISD::EntryToken) {
887 unsigned i = 0, e = PendingExports.size();
888 for (; i != e; ++i) {
889 assert(PendingExports[i].getNode()->getNumOperands() > 1);
890 if (PendingExports[i].getNode()->getOperand(0) == Root)
891 break; // Don't add the root if we already indirectly depend on it.
895 PendingExports.push_back(Root);
898 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
900 PendingExports.clear();
905 void SelectionDAGBuilder::visit(const Instruction &I) {
906 // Set up outgoing PHI node register values before emitting the terminator.
907 if (isa<TerminatorInst>(&I))
908 HandlePHINodesInSuccessorBlocks(I.getParent());
914 visit(I.getOpcode(), I);
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
923 void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
927 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
931 default: llvm_unreachable("Unknown instruction type encountered!");
932 // Build the switch statement using the Instruction.def file.
933 #define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935 #include "llvm/IR/Instruction.def"
939 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940 // generate the debug data structures now that we've seen its definition.
941 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&
951 "Expected inlined-at fields to agree");
952 uint64_t Offset = DI->getOffset();
955 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, false,
957 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
958 false, Offset, dl, DbgSDNodeOrder);
959 DAG.AddDbgValue(SDV, Val.getNode(), false);
962 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
963 DanglingDebugInfoMap[V] = DanglingDebugInfo();
967 /// getCopyFromRegs - If there was virtual register allocated for the value V
968 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
969 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
970 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
973 if (It != FuncInfo.ValueMap.end()) {
974 unsigned InReg = It->second;
975 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
976 DAG.getDataLayout(), InReg, Ty);
977 SDValue Chain = DAG.getEntryNode();
978 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
979 resolveDanglingDebugInfo(V, Result);
985 /// getValue - Return an SDValue for the given Value.
986 SDValue SelectionDAGBuilder::getValue(const Value *V) {
987 // If we already have an SDValue for this value, use it. It's important
988 // to do this first, so that we don't create a CopyFromReg if we already
989 // have a regular SDValue.
990 SDValue &N = NodeMap[V];
991 if (N.getNode()) return N;
993 // If there's a virtual register allocated and initialized for this
995 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
996 if (copyFromReg.getNode()) {
1000 // Otherwise create a new SDValue and remember it.
1001 SDValue Val = getValueImpl(V);
1003 resolveDanglingDebugInfo(V, Val);
1007 // Return true if SDValue exists for the given Value
1008 bool SelectionDAGBuilder::findValue(const Value *V) const {
1009 return (NodeMap.find(V) != NodeMap.end()) ||
1010 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1013 /// getNonRegisterValue - Return an SDValue for the given Value, but
1014 /// don't look in FuncInfo.ValueMap for a virtual register.
1015 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it.
1017 SDValue &N = NodeMap[V];
1019 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1020 // Remove the debug location from the node as the node is about to be used
1021 // in a location which may differ from the original debug location. This
1022 // is relevant to Constant and ConstantFP nodes because they can appear
1023 // as constant expressions inside PHI nodes.
1024 N->setDebugLoc(DebugLoc());
1029 // Otherwise create a new SDValue and remember it.
1030 SDValue Val = getValueImpl(V);
1032 resolveDanglingDebugInfo(V, Val);
1036 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1037 /// Create an SDValue for the given value.
1038 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1041 if (const Constant *C = dyn_cast<Constant>(V)) {
1042 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1044 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1045 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1047 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1048 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1050 if (isa<ConstantPointerNull>(C)) {
1051 unsigned AS = V->getType()->getPointerAddressSpace();
1052 return DAG.getConstant(0, getCurSDLoc(),
1053 TLI.getPointerTy(DAG.getDataLayout(), AS));
1056 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1057 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1059 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1060 return DAG.getUNDEF(VT);
1062 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1063 visit(CE->getOpcode(), *CE);
1064 SDValue N1 = NodeMap[V];
1065 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1069 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1070 SmallVector<SDValue, 4> Constants;
1071 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1073 SDNode *Val = getValue(*OI).getNode();
1074 // If the operand is an empty aggregate, there are no values.
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Constants.push_back(SDValue(Val, i));
1082 return DAG.getMergeValues(Constants, getCurSDLoc());
1085 if (const ConstantDataSequential *CDS =
1086 dyn_cast<ConstantDataSequential>(C)) {
1087 SmallVector<SDValue, 4> Ops;
1088 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1089 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1090 // Add each leaf value from the operand to the Constants list
1091 // to form a flattened list of all the values.
1092 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1093 Ops.push_back(SDValue(Val, i));
1096 if (isa<ArrayType>(CDS->getType()))
1097 return DAG.getMergeValues(Ops, getCurSDLoc());
1098 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1102 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1103 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1104 "Unknown struct or array constant!");
1106 SmallVector<EVT, 4> ValueVTs;
1107 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1108 unsigned NumElts = ValueVTs.size();
1110 return SDValue(); // empty struct
1111 SmallVector<SDValue, 4> Constants(NumElts);
1112 for (unsigned i = 0; i != NumElts; ++i) {
1113 EVT EltVT = ValueVTs[i];
1114 if (isa<UndefValue>(C))
1115 Constants[i] = DAG.getUNDEF(EltVT);
1116 else if (EltVT.isFloatingPoint())
1117 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1119 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1122 return DAG.getMergeValues(Constants, getCurSDLoc());
1125 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1126 return DAG.getBlockAddress(BA, VT);
1128 VectorType *VecTy = cast<VectorType>(V->getType());
1129 unsigned NumElements = VecTy->getNumElements();
1131 // Now that we know the number and type of the elements, get that number of
1132 // elements into the Ops array based on what kind of constant it is.
1133 SmallVector<SDValue, 16> Ops;
1134 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1135 for (unsigned i = 0; i != NumElements; ++i)
1136 Ops.push_back(getValue(CV->getOperand(i)));
1138 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1140 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1143 if (EltVT.isFloatingPoint())
1144 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1146 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1147 Ops.assign(NumElements, Op);
1150 // Create a BUILD_VECTOR node.
1151 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1154 // If this is a static alloca, generate it as the frameindex instead of
1156 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1157 DenseMap<const AllocaInst*, int>::iterator SI =
1158 FuncInfo.StaticAllocaMap.find(AI);
1159 if (SI != FuncInfo.StaticAllocaMap.end())
1160 return DAG.getFrameIndex(SI->second,
1161 TLI.getPointerTy(DAG.getDataLayout()));
1164 // If this is an instruction which fast-isel has deferred, select it now.
1165 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1166 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1167 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1169 SDValue Chain = DAG.getEntryNode();
1170 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1173 llvm_unreachable("Can't get register for value!");
1176 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1177 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1178 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1179 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1180 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1181 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1182 if (IsMSVCCXX || IsCoreCLR)
1183 CatchPadMBB->setIsEHFuncletEntry();
1185 DAG.setRoot(DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot()));
1188 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1189 // Update machine-CFG edge.
1190 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1191 FuncInfo.MBB->addSuccessor(TargetMBB);
1193 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1194 bool IsSEH = isAsynchronousEHPersonality(Pers);
1196 // If this is not a fall-through branch or optimizations are switched off,
1198 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1199 TM.getOptLevel() == CodeGenOpt::None)
1200 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1201 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1205 // Figure out the funclet membership for the catchret's successor.
1206 // This will be used by the FuncletLayout pass to determine how to order the
1208 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
1209 const BasicBlock *SuccessorColor = EHInfo->CatchRetSuccessorColorMap[&I];
1210 assert(SuccessorColor && "No parent funclet for catchret!");
1211 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1212 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1214 // Create the terminator node.
1215 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1216 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1217 DAG.getBasicBlock(SuccessorColorMBB));
1221 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1222 // Don't emit any special code for the cleanuppad instruction. It just marks
1223 // the start of a funclet.
1224 FuncInfo.MBB->setIsEHFuncletEntry();
1225 FuncInfo.MBB->setIsCleanupFuncletEntry();
1228 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1229 /// many places it could ultimately go. In the IR, we have a single unwind
1230 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1231 /// This function skips over imaginary basic blocks that hold catchswitch
1232 /// instructions, and finds all the "real" machine
1233 /// basic block destinations. As those destinations may not be successors of
1234 /// EHPadBB, here we also calculate the edge probability to those destinations.
1235 /// The passed-in Prob is the edge probability to EHPadBB.
1236 static void findUnwindDestinations(
1237 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1238 BranchProbability Prob,
1239 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1241 EHPersonality Personality =
1242 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1243 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1244 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1247 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1248 BasicBlock *NewEHPadBB = nullptr;
1249 if (isa<LandingPadInst>(Pad)) {
1250 // Stop on landingpads. They are not funclets.
1251 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1253 } else if (isa<CleanupPadInst>(Pad)) {
1254 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1256 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1257 UnwindDests.back().first->setIsEHFuncletEntry();
1259 } else if (auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
1260 // Add the catchpad handlers to the possible destinations.
1261 for (const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
1262 UnwindDests.emplace_back(FuncInfo.MBBMap[CatchPadBB], Prob);
1263 // For MSVC++ and the CLR, catchblocks are funclets and need prologues.
1264 if (IsMSVCCXX || IsCoreCLR)
1265 UnwindDests.back().first->setIsEHFuncletEntry();
1267 NewEHPadBB = CatchSwitch->getUnwindDest();
1272 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1273 if (BPI && NewEHPadBB)
1274 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1275 EHPadBB = NewEHPadBB;
1279 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1280 // Update successor info.
1281 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1282 auto UnwindDest = I.getUnwindDest();
1283 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1284 BranchProbability UnwindDestProb =
1286 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1287 : BranchProbability::getZero();
1288 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1289 for (auto &UnwindDest : UnwindDests) {
1290 UnwindDest.first->setIsEHPad();
1291 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1293 FuncInfo.MBB->normalizeSuccProbs();
1295 // Create the terminator node.
1297 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1301 void SelectionDAGBuilder::visitCatchSwitch(const CatchSwitchInst &CSI) {
1302 report_fatal_error("visitCatchSwitch not yet implemented!");
1305 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1307 auto &DL = DAG.getDataLayout();
1308 SDValue Chain = getControlRoot();
1309 SmallVector<ISD::OutputArg, 8> Outs;
1310 SmallVector<SDValue, 8> OutVals;
1312 if (!FuncInfo.CanLowerReturn) {
1313 unsigned DemoteReg = FuncInfo.DemoteRegister;
1314 const Function *F = I.getParent()->getParent();
1316 // Emit a store of the return value through the virtual register.
1317 // Leave Outs empty so that LowerReturn won't try to load return
1318 // registers the usual way.
1319 SmallVector<EVT, 1> PtrValueVTs;
1320 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1323 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1324 DemoteReg, PtrValueVTs[0]);
1325 SDValue RetOp = getValue(I.getOperand(0));
1327 SmallVector<EVT, 4> ValueVTs;
1328 SmallVector<uint64_t, 4> Offsets;
1329 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1330 unsigned NumValues = ValueVTs.size();
1332 // An aggregate return value cannot wrap around the address space, so
1333 // offsets to its parts don't wrap either.
1335 Flags.setNoUnsignedWrap(true);
1337 SmallVector<SDValue, 4> Chains(NumValues);
1338 for (unsigned i = 0; i != NumValues; ++i) {
1339 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1340 RetPtr.getValueType(), RetPtr,
1341 DAG.getIntPtrConstant(Offsets[i],
1345 DAG.getStore(Chain, getCurSDLoc(),
1346 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1347 // FIXME: better loc info would be nice.
1348 Add, MachinePointerInfo(), false, false, 0);
1351 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1352 MVT::Other, Chains);
1353 } else if (I.getNumOperands() != 0) {
1354 SmallVector<EVT, 4> ValueVTs;
1355 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1356 unsigned NumValues = ValueVTs.size();
1358 SDValue RetOp = getValue(I.getOperand(0));
1360 const Function *F = I.getParent()->getParent();
1362 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1363 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1365 ExtendKind = ISD::SIGN_EXTEND;
1366 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1368 ExtendKind = ISD::ZERO_EXTEND;
1370 LLVMContext &Context = F->getContext();
1371 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1374 for (unsigned j = 0; j != NumValues; ++j) {
1375 EVT VT = ValueVTs[j];
1377 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1378 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1380 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1381 MVT PartVT = TLI.getRegisterType(Context, VT);
1382 SmallVector<SDValue, 4> Parts(NumParts);
1383 getCopyToParts(DAG, getCurSDLoc(),
1384 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1385 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1387 // 'inreg' on function refers to return value
1388 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1392 // Propagate extension type if any
1393 if (ExtendKind == ISD::SIGN_EXTEND)
1395 else if (ExtendKind == ISD::ZERO_EXTEND)
1398 for (unsigned i = 0; i < NumParts; ++i) {
1399 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1400 VT, /*isfixed=*/true, 0, 0));
1401 OutVals.push_back(Parts[i]);
1407 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1408 CallingConv::ID CallConv =
1409 DAG.getMachineFunction().getFunction()->getCallingConv();
1410 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1411 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1413 // Verify that the target's LowerReturn behaved as expected.
1414 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1415 "LowerReturn didn't return a valid chain!");
1417 // Update the DAG with the new chain value resulting from return lowering.
1421 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1422 /// created for it, emit nodes to copy the value into the virtual
1424 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1426 if (V->getType()->isEmptyTy())
1429 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1430 if (VMI != FuncInfo.ValueMap.end()) {
1431 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1432 CopyValueToVirtualRegister(V, VMI->second);
1436 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1437 /// the current basic block, add it to ValueMap now so that we'll get a
1439 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1440 // No need to export constants.
1441 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1443 // Already exported?
1444 if (FuncInfo.isExportedInst(V)) return;
1446 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1447 CopyValueToVirtualRegister(V, Reg);
1450 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1451 const BasicBlock *FromBB) {
1452 // The operands of the setcc have to be in this block. We don't know
1453 // how to export them from some other block.
1454 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1455 // Can export from current BB.
1456 if (VI->getParent() == FromBB)
1459 // Is already exported, noop.
1460 return FuncInfo.isExportedInst(V);
1463 // If this is an argument, we can export it if the BB is the entry block or
1464 // if it is already exported.
1465 if (isa<Argument>(V)) {
1466 if (FromBB == &FromBB->getParent()->getEntryBlock())
1469 // Otherwise, can only export this if it is already exported.
1470 return FuncInfo.isExportedInst(V);
1473 // Otherwise, constants can always be exported.
1477 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1479 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1480 const MachineBasicBlock *Dst) const {
1481 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1482 const BasicBlock *SrcBB = Src->getBasicBlock();
1483 const BasicBlock *DstBB = Dst->getBasicBlock();
1485 // If BPI is not available, set the default probability as 1 / N, where N is
1486 // the number of successors.
1487 auto SuccSize = std::max<uint32_t>(
1488 std::distance(succ_begin(SrcBB), succ_end(SrcBB)), 1);
1489 return BranchProbability(1, SuccSize);
1491 return BPI->getEdgeProbability(SrcBB, DstBB);
1494 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1495 MachineBasicBlock *Dst,
1496 BranchProbability Prob) {
1498 Src->addSuccessorWithoutProb(Dst);
1500 if (Prob.isUnknown())
1501 Prob = getEdgeProbability(Src, Dst);
1502 Src->addSuccessor(Dst, Prob);
1506 static bool InBlock(const Value *V, const BasicBlock *BB) {
1507 if (const Instruction *I = dyn_cast<Instruction>(V))
1508 return I->getParent() == BB;
1512 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1513 /// This function emits a branch and is used at the leaves of an OR or an
1514 /// AND operator tree.
1517 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1518 MachineBasicBlock *TBB,
1519 MachineBasicBlock *FBB,
1520 MachineBasicBlock *CurBB,
1521 MachineBasicBlock *SwitchBB,
1522 BranchProbability TProb,
1523 BranchProbability FProb) {
1524 const BasicBlock *BB = CurBB->getBasicBlock();
1526 // If the leaf of the tree is a comparison, merge the condition into
1528 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1529 // The operands of the cmp have to be in this block. We don't know
1530 // how to export them from some other block. If this is the first block
1531 // of the sequence, no exporting is needed.
1532 if (CurBB == SwitchBB ||
1533 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1534 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1535 ISD::CondCode Condition;
1536 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1537 Condition = getICmpCondCode(IC->getPredicate());
1539 const FCmpInst *FC = cast<FCmpInst>(Cond);
1540 Condition = getFCmpCondCode(FC->getPredicate());
1541 if (TM.Options.NoNaNsFPMath)
1542 Condition = getFCmpCodeWithoutNaN(Condition);
1545 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1546 TBB, FBB, CurBB, TProb, FProb);
1547 SwitchCases.push_back(CB);
1552 // Create a CaseBlock record representing this branch.
1553 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1554 nullptr, TBB, FBB, CurBB, TProb, FProb);
1555 SwitchCases.push_back(CB);
1558 /// FindMergedConditions - If Cond is an expression like
1559 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1560 MachineBasicBlock *TBB,
1561 MachineBasicBlock *FBB,
1562 MachineBasicBlock *CurBB,
1563 MachineBasicBlock *SwitchBB,
1564 Instruction::BinaryOps Opc,
1565 BranchProbability TProb,
1566 BranchProbability FProb) {
1567 // If this node is not part of the or/and tree, emit it as a branch.
1568 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1569 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1570 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1571 BOp->getParent() != CurBB->getBasicBlock() ||
1572 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1573 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1574 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1579 // Create TmpBB after CurBB.
1580 MachineFunction::iterator BBI(CurBB);
1581 MachineFunction &MF = DAG.getMachineFunction();
1582 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1583 CurBB->getParent()->insert(++BBI, TmpBB);
1585 if (Opc == Instruction::Or) {
1586 // Codegen X | Y as:
1595 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1596 // The requirement is that
1597 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1598 // = TrueProb for original BB.
1599 // Assuming the original probabilities are A and B, one choice is to set
1600 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
1601 // A/(1+B) and 2B/(1+B). This choice assumes that
1602 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1603 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1604 // TmpBB, but the math is more complicated.
1606 auto NewTrueProb = TProb / 2;
1607 auto NewFalseProb = TProb / 2 + FProb;
1608 // Emit the LHS condition.
1609 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1610 NewTrueProb, NewFalseProb);
1612 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
1613 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
1614 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1615 // Emit the RHS condition into TmpBB.
1616 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1617 Probs[0], Probs[1]);
1619 assert(Opc == Instruction::And && "Unknown merge op!");
1620 // Codegen X & Y as:
1628 // This requires creation of TmpBB after CurBB.
1630 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1631 // The requirement is that
1632 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1633 // = FalseProb for original BB.
1634 // Assuming the original probabilities are A and B, one choice is to set
1635 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
1636 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
1637 // TrueProb for BB1 * FalseProb for TmpBB.
1639 auto NewTrueProb = TProb + FProb / 2;
1640 auto NewFalseProb = FProb / 2;
1641 // Emit the LHS condition.
1642 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1643 NewTrueProb, NewFalseProb);
1645 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
1646 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
1647 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1648 // Emit the RHS condition into TmpBB.
1649 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1650 Probs[0], Probs[1]);
1654 /// If the set of cases should be emitted as a series of branches, return true.
1655 /// If we should emit this as a bunch of and/or'd together conditions, return
1658 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1659 if (Cases.size() != 2) return true;
1661 // If this is two comparisons of the same values or'd or and'd together, they
1662 // will get folded into a single comparison, so don't emit two blocks.
1663 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1664 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1665 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1666 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1670 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1671 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1672 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1673 Cases[0].CC == Cases[1].CC &&
1674 isa<Constant>(Cases[0].CmpRHS) &&
1675 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1676 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1678 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1685 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1686 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1688 // Update machine-CFG edges.
1689 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1691 if (I.isUnconditional()) {
1692 // Update machine-CFG edges.
1693 BrMBB->addSuccessor(Succ0MBB);
1695 // If this is not a fall-through branch or optimizations are switched off,
1697 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1698 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1699 MVT::Other, getControlRoot(),
1700 DAG.getBasicBlock(Succ0MBB)));
1705 // If this condition is one of the special cases we handle, do special stuff
1707 const Value *CondVal = I.getCondition();
1708 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1710 // If this is a series of conditions that are or'd or and'd together, emit
1711 // this as a sequence of branches instead of setcc's with and/or operations.
1712 // As long as jumps are not expensive, this should improve performance.
1713 // For example, instead of something like:
1726 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1727 Instruction::BinaryOps Opcode = BOp->getOpcode();
1728 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1729 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1730 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1731 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1733 getEdgeProbability(BrMBB, Succ0MBB),
1734 getEdgeProbability(BrMBB, Succ1MBB));
1735 // If the compares in later blocks need to use values not currently
1736 // exported from this block, export them now. This block should always
1737 // be the first entry.
1738 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1740 // Allow some cases to be rejected.
1741 if (ShouldEmitAsBranches(SwitchCases)) {
1742 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1743 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1744 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1747 // Emit the branch for this block.
1748 visitSwitchCase(SwitchCases[0], BrMBB);
1749 SwitchCases.erase(SwitchCases.begin());
1753 // Okay, we decided not to do this, remove any inserted MBB's and clear
1755 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1756 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1758 SwitchCases.clear();
1762 // Create a CaseBlock record representing this branch.
1763 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1764 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1766 // Use visitSwitchCase to actually insert the fast branch sequence for this
1768 visitSwitchCase(CB, BrMBB);
1771 /// visitSwitchCase - Emits the necessary code to represent a single node in
1772 /// the binary search tree resulting from lowering a switch instruction.
1773 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1774 MachineBasicBlock *SwitchBB) {
1776 SDValue CondLHS = getValue(CB.CmpLHS);
1777 SDLoc dl = getCurSDLoc();
1779 // Build the setcc now.
1781 // Fold "(X == true)" to X and "(X == false)" to !X to
1782 // handle common cases produced by branch lowering.
1783 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1784 CB.CC == ISD::SETEQ)
1786 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1787 CB.CC == ISD::SETEQ) {
1788 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1789 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1791 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1793 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1795 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1796 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1798 SDValue CmpOp = getValue(CB.CmpMHS);
1799 EVT VT = CmpOp.getValueType();
1801 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1802 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1805 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1806 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1807 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1808 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1812 // Update successor info
1813 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
1814 // TrueBB and FalseBB are always different unless the incoming IR is
1815 // degenerate. This only happens when running llc on weird IR.
1816 if (CB.TrueBB != CB.FalseBB)
1817 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
1818 SwitchBB->normalizeSuccProbs();
1820 // If the lhs block is the next block, invert the condition so that we can
1821 // fall through to the lhs instead of the rhs block.
1822 if (CB.TrueBB == NextBlock(SwitchBB)) {
1823 std::swap(CB.TrueBB, CB.FalseBB);
1824 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1825 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1828 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1829 MVT::Other, getControlRoot(), Cond,
1830 DAG.getBasicBlock(CB.TrueBB));
1832 // Insert the false branch. Do this even if it's a fall through branch,
1833 // this makes it easier to do DAG optimizations which require inverting
1834 // the branch condition.
1835 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1836 DAG.getBasicBlock(CB.FalseBB));
1838 DAG.setRoot(BrCond);
1841 /// visitJumpTable - Emit JumpTable node in the current MBB
1842 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1843 // Emit the code for the jump table
1844 assert(JT.Reg != -1U && "Should lower JT Header first!");
1845 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1846 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1848 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1849 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1850 MVT::Other, Index.getValue(1),
1852 DAG.setRoot(BrJumpTable);
1855 /// visitJumpTableHeader - This function emits necessary code to produce index
1856 /// in the JumpTable from switch case.
1857 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1858 JumpTableHeader &JTH,
1859 MachineBasicBlock *SwitchBB) {
1860 SDLoc dl = getCurSDLoc();
1862 // Subtract the lowest switch case value from the value being switched on and
1863 // conditional branch to default mbb if the result is greater than the
1864 // difference between smallest and largest cases.
1865 SDValue SwitchOp = getValue(JTH.SValue);
1866 EVT VT = SwitchOp.getValueType();
1867 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1868 DAG.getConstant(JTH.First, dl, VT));
1870 // The SDNode we just created, which holds the value being switched on minus
1871 // the smallest case value, needs to be copied to a virtual register so it
1872 // can be used as an index into the jump table in a subsequent basic block.
1873 // This value may be smaller or larger than the target's pointer type, and
1874 // therefore require extension or truncating.
1875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1876 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1878 unsigned JumpTableReg =
1879 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1880 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1881 JumpTableReg, SwitchOp);
1882 JT.Reg = JumpTableReg;
1884 // Emit the range check for the jump table, and branch to the default block
1885 // for the switch statement if the value being switched on exceeds the largest
1886 // case in the switch.
1887 SDValue CMP = DAG.getSetCC(
1888 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1889 Sub.getValueType()),
1890 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1892 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1893 MVT::Other, CopyTo, CMP,
1894 DAG.getBasicBlock(JT.Default));
1896 // Avoid emitting unnecessary branches to the next block.
1897 if (JT.MBB != NextBlock(SwitchBB))
1898 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1899 DAG.getBasicBlock(JT.MBB));
1901 DAG.setRoot(BrCond);
1904 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1905 /// tail spliced into a stack protector check success bb.
1907 /// For a high level explanation of how this fits into the stack protector
1908 /// generation see the comment on the declaration of class
1909 /// StackProtectorDescriptor.
1910 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1911 MachineBasicBlock *ParentBB) {
1913 // First create the loads to the guard/stack slot for the comparison.
1914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1915 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1917 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1918 int FI = MFI->getStackProtectorIndex();
1920 const Value *IRGuard = SPD.getGuard();
1921 SDValue GuardPtr = getValue(IRGuard);
1922 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1924 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1927 SDLoc dl = getCurSDLoc();
1929 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1930 // guard value from the virtual register holding the value. Otherwise, emit a
1931 // volatile load to retrieve the stack guard value.
1932 unsigned GuardReg = SPD.getGuardReg();
1934 if (GuardReg && TLI.useLoadStackGuardNode())
1935 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1938 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1939 GuardPtr, MachinePointerInfo(IRGuard, 0),
1940 true, false, false, Align);
1942 SDValue StackSlot = DAG.getLoad(
1943 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1944 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1945 false, false, Align);
1947 // Perform the comparison via a subtract/getsetcc.
1948 EVT VT = Guard.getValueType();
1949 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1951 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1953 Sub.getValueType()),
1954 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1956 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1957 // branch to failure MBB.
1958 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1959 MVT::Other, StackSlot.getOperand(0),
1960 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1961 // Otherwise branch to success MBB.
1962 SDValue Br = DAG.getNode(ISD::BR, dl,
1964 DAG.getBasicBlock(SPD.getSuccessMBB()));
1969 /// Codegen the failure basic block for a stack protector check.
1971 /// A failure stack protector machine basic block consists simply of a call to
1972 /// __stack_chk_fail().
1974 /// For a high level explanation of how this fits into the stack protector
1975 /// generation see the comment on the declaration of class
1976 /// StackProtectorDescriptor.
1978 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1981 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1982 None, false, getCurSDLoc(), false, false).second;
1986 /// visitBitTestHeader - This function emits necessary code to produce value
1987 /// suitable for "bit tests"
1988 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1989 MachineBasicBlock *SwitchBB) {
1990 SDLoc dl = getCurSDLoc();
1992 // Subtract the minimum value
1993 SDValue SwitchOp = getValue(B.SValue);
1994 EVT VT = SwitchOp.getValueType();
1995 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1996 DAG.getConstant(B.First, dl, VT));
1999 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2000 SDValue RangeCmp = DAG.getSetCC(
2001 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2002 Sub.getValueType()),
2003 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2005 // Determine the type of the test operands.
2006 bool UsePtrType = false;
2007 if (!TLI.isTypeLegal(VT))
2010 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2011 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2012 // Switch table case range are encoded into series of masks.
2013 // Just use pointer type, it's guaranteed to fit.
2019 VT = TLI.getPointerTy(DAG.getDataLayout());
2020 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2023 B.RegVT = VT.getSimpleVT();
2024 B.Reg = FuncInfo.CreateReg(B.RegVT);
2025 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2027 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2029 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2030 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2031 SwitchBB->normalizeSuccProbs();
2033 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2034 MVT::Other, CopyTo, RangeCmp,
2035 DAG.getBasicBlock(B.Default));
2037 // Avoid emitting unnecessary branches to the next block.
2038 if (MBB != NextBlock(SwitchBB))
2039 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2040 DAG.getBasicBlock(MBB));
2042 DAG.setRoot(BrRange);
2045 /// visitBitTestCase - this function produces one "bit test"
2046 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2047 MachineBasicBlock* NextMBB,
2048 BranchProbability BranchProbToNext,
2051 MachineBasicBlock *SwitchBB) {
2052 SDLoc dl = getCurSDLoc();
2054 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2056 unsigned PopCount = countPopulation(B.Mask);
2057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2058 if (PopCount == 1) {
2059 // Testing for a single bit; just compare the shift count with what it
2060 // would need to be to shift a 1 bit in that position.
2062 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2063 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2065 } else if (PopCount == BB.Range) {
2066 // There is only one zero bit in the range, test for it directly.
2068 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2069 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2072 // Make desired shift
2073 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2074 DAG.getConstant(1, dl, VT), ShiftOp);
2076 // Emit bit tests and jumps
2077 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2078 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2080 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2081 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2084 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2085 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2086 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2087 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2088 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2089 // one as they are relative probabilities (and thus work more like weights),
2090 // and hence we need to normalize them to let the sum of them become one.
2091 SwitchBB->normalizeSuccProbs();
2093 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2094 MVT::Other, getControlRoot(),
2095 Cmp, DAG.getBasicBlock(B.TargetBB));
2097 // Avoid emitting unnecessary branches to the next block.
2098 if (NextMBB != NextBlock(SwitchBB))
2099 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2100 DAG.getBasicBlock(NextMBB));
2105 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2106 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2108 // Retrieve successors. Look through artificial IR level blocks like
2109 // catchswitch for successors.
2110 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2111 const BasicBlock *EHPadBB = I.getSuccessor(1);
2113 const Value *Callee(I.getCalledValue());
2114 const Function *Fn = dyn_cast<Function>(Callee);
2115 if (isa<InlineAsm>(Callee))
2117 else if (Fn && Fn->isIntrinsic()) {
2118 switch (Fn->getIntrinsicID()) {
2120 llvm_unreachable("Cannot invoke this intrinsic");
2121 case Intrinsic::donothing:
2122 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2124 case Intrinsic::experimental_patchpoint_void:
2125 case Intrinsic::experimental_patchpoint_i64:
2126 visitPatchpoint(&I, EHPadBB);
2128 case Intrinsic::experimental_gc_statepoint:
2129 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2133 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2135 // If the value of the invoke is used outside of its defining block, make it
2136 // available as a virtual register.
2137 // We already took care of the exported value for the statepoint instruction
2138 // during call to the LowerStatepoint.
2139 if (!isStatepoint(I)) {
2140 CopyToExportRegsIfNeeded(&I);
2143 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2144 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2145 BranchProbability EHPadBBProb =
2146 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2147 : BranchProbability::getZero();
2148 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2150 // Update successor info.
2151 addSuccessorWithProb(InvokeMBB, Return);
2152 for (auto &UnwindDest : UnwindDests) {
2153 UnwindDest.first->setIsEHPad();
2154 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2156 InvokeMBB->normalizeSuccProbs();
2158 // Drop into normal successor.
2159 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2160 MVT::Other, getControlRoot(),
2161 DAG.getBasicBlock(Return)));
2164 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2165 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2168 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2169 assert(FuncInfo.MBB->isEHPad() &&
2170 "Call to landingpad not in landing pad!");
2172 MachineBasicBlock *MBB = FuncInfo.MBB;
2173 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2174 AddLandingPadInfo(LP, MMI, MBB);
2176 // If there aren't registers to copy the values into (e.g., during SjLj
2177 // exceptions), then don't bother to create these DAG nodes.
2178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2179 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2180 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2181 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2184 // If landingpad's return type is token type, we don't create DAG nodes
2185 // for its exception pointer and selector value. The extraction of exception
2186 // pointer or selector value from token type landingpads is not currently
2188 if (LP.getType()->isTokenTy())
2191 SmallVector<EVT, 2> ValueVTs;
2192 SDLoc dl = getCurSDLoc();
2193 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2194 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2196 // Get the two live-in registers as SDValues. The physregs have already been
2197 // copied into virtual registers.
2199 if (FuncInfo.ExceptionPointerVirtReg) {
2200 Ops[0] = DAG.getZExtOrTrunc(
2201 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2202 FuncInfo.ExceptionPointerVirtReg,
2203 TLI.getPointerTy(DAG.getDataLayout())),
2206 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2208 Ops[1] = DAG.getZExtOrTrunc(
2209 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2210 FuncInfo.ExceptionSelectorVirtReg,
2211 TLI.getPointerTy(DAG.getDataLayout())),
2215 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2216 DAG.getVTList(ValueVTs), Ops);
2220 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2222 for (const CaseCluster &CC : Clusters)
2223 assert(CC.Low == CC.High && "Input clusters must be single-case");
2226 std::sort(Clusters.begin(), Clusters.end(),
2227 [](const CaseCluster &a, const CaseCluster &b) {
2228 return a.Low->getValue().slt(b.Low->getValue());
2231 // Merge adjacent clusters with the same destination.
2232 const unsigned N = Clusters.size();
2233 unsigned DstIndex = 0;
2234 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2235 CaseCluster &CC = Clusters[SrcIndex];
2236 const ConstantInt *CaseVal = CC.Low;
2237 MachineBasicBlock *Succ = CC.MBB;
2239 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2240 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2241 // If this case has the same successor and is a neighbour, merge it into
2242 // the previous cluster.
2243 Clusters[DstIndex - 1].High = CaseVal;
2244 Clusters[DstIndex - 1].Prob += CC.Prob;
2246 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2247 sizeof(Clusters[SrcIndex]));
2250 Clusters.resize(DstIndex);
2253 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2254 MachineBasicBlock *Last) {
2256 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2257 if (JTCases[i].first.HeaderBB == First)
2258 JTCases[i].first.HeaderBB = Last;
2260 // Update BitTestCases.
2261 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2262 if (BitTestCases[i].Parent == First)
2263 BitTestCases[i].Parent = Last;
2266 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2267 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2269 // Update machine-CFG edges with unique successors.
2270 SmallSet<BasicBlock*, 32> Done;
2271 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2272 BasicBlock *BB = I.getSuccessor(i);
2273 bool Inserted = Done.insert(BB).second;
2277 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2278 addSuccessorWithProb(IndirectBrMBB, Succ);
2280 IndirectBrMBB->normalizeSuccProbs();
2282 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2283 MVT::Other, getControlRoot(),
2284 getValue(I.getAddress())));
2287 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2288 if (DAG.getTarget().Options.TrapUnreachable)
2290 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2293 void SelectionDAGBuilder::visitFSub(const User &I) {
2294 // -0.0 - X --> fneg
2295 Type *Ty = I.getType();
2296 if (isa<Constant>(I.getOperand(0)) &&
2297 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2298 SDValue Op2 = getValue(I.getOperand(1));
2299 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2300 Op2.getValueType(), Op2));
2304 visitBinary(I, ISD::FSUB);
2307 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2308 SDValue Op1 = getValue(I.getOperand(0));
2309 SDValue Op2 = getValue(I.getOperand(1));
2316 if (const OverflowingBinaryOperator *OFBinOp =
2317 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2318 nuw = OFBinOp->hasNoUnsignedWrap();
2319 nsw = OFBinOp->hasNoSignedWrap();
2321 if (const PossiblyExactOperator *ExactOp =
2322 dyn_cast<const PossiblyExactOperator>(&I))
2323 exact = ExactOp->isExact();
2324 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2325 FMF = FPOp->getFastMathFlags();
2328 Flags.setExact(exact);
2329 Flags.setNoSignedWrap(nsw);
2330 Flags.setNoUnsignedWrap(nuw);
2331 if (EnableFMFInDAG) {
2332 Flags.setAllowReciprocal(FMF.allowReciprocal());
2333 Flags.setNoInfs(FMF.noInfs());
2334 Flags.setNoNaNs(FMF.noNaNs());
2335 Flags.setNoSignedZeros(FMF.noSignedZeros());
2336 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2338 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2340 setValue(&I, BinNodeValue);
2343 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2344 SDValue Op1 = getValue(I.getOperand(0));
2345 SDValue Op2 = getValue(I.getOperand(1));
2347 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2348 Op2.getValueType(), DAG.getDataLayout());
2350 // Coerce the shift amount to the right type if we can.
2351 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2352 unsigned ShiftSize = ShiftTy.getSizeInBits();
2353 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2354 SDLoc DL = getCurSDLoc();
2356 // If the operand is smaller than the shift count type, promote it.
2357 if (ShiftSize > Op2Size)
2358 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2360 // If the operand is larger than the shift count type but the shift
2361 // count type has enough bits to represent any shift value, truncate
2362 // it now. This is a common case and it exposes the truncate to
2363 // optimization early.
2364 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2365 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2366 // Otherwise we'll need to temporarily settle for some other convenient
2367 // type. Type legalization will make adjustments once the shiftee is split.
2369 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2376 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2378 if (const OverflowingBinaryOperator *OFBinOp =
2379 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2380 nuw = OFBinOp->hasNoUnsignedWrap();
2381 nsw = OFBinOp->hasNoSignedWrap();
2383 if (const PossiblyExactOperator *ExactOp =
2384 dyn_cast<const PossiblyExactOperator>(&I))
2385 exact = ExactOp->isExact();
2388 Flags.setExact(exact);
2389 Flags.setNoSignedWrap(nsw);
2390 Flags.setNoUnsignedWrap(nuw);
2391 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2396 void SelectionDAGBuilder::visitSDiv(const User &I) {
2397 SDValue Op1 = getValue(I.getOperand(0));
2398 SDValue Op2 = getValue(I.getOperand(1));
2401 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2402 cast<PossiblyExactOperator>(&I)->isExact());
2403 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2407 void SelectionDAGBuilder::visitICmp(const User &I) {
2408 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2409 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2410 predicate = IC->getPredicate();
2411 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2412 predicate = ICmpInst::Predicate(IC->getPredicate());
2413 SDValue Op1 = getValue(I.getOperand(0));
2414 SDValue Op2 = getValue(I.getOperand(1));
2415 ISD::CondCode Opcode = getICmpCondCode(predicate);
2417 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2419 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2422 void SelectionDAGBuilder::visitFCmp(const User &I) {
2423 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2424 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2425 predicate = FC->getPredicate();
2426 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2427 predicate = FCmpInst::Predicate(FC->getPredicate());
2428 SDValue Op1 = getValue(I.getOperand(0));
2429 SDValue Op2 = getValue(I.getOperand(1));
2430 ISD::CondCode Condition = getFCmpCondCode(predicate);
2432 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2433 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2434 // further optimization, but currently FMF is only applicable to binary nodes.
2435 if (TM.Options.NoNaNsFPMath)
2436 Condition = getFCmpCodeWithoutNaN(Condition);
2437 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2439 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2442 void SelectionDAGBuilder::visitSelect(const User &I) {
2443 SmallVector<EVT, 4> ValueVTs;
2444 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2446 unsigned NumValues = ValueVTs.size();
2447 if (NumValues == 0) return;
2449 SmallVector<SDValue, 4> Values(NumValues);
2450 SDValue Cond = getValue(I.getOperand(0));
2451 SDValue LHSVal = getValue(I.getOperand(1));
2452 SDValue RHSVal = getValue(I.getOperand(2));
2453 auto BaseOps = {Cond};
2454 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2455 ISD::VSELECT : ISD::SELECT;
2457 // Min/max matching is only viable if all output VTs are the same.
2458 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2459 EVT VT = ValueVTs[0];
2460 LLVMContext &Ctx = *DAG.getContext();
2461 auto &TLI = DAG.getTargetLoweringInfo();
2463 // We care about the legality of the operation after it has been type
2465 while (TLI.getTypeAction(Ctx, VT) != TargetLoweringBase::TypeLegal &&
2466 VT != TLI.getTypeToTransformTo(Ctx, VT))
2467 VT = TLI.getTypeToTransformTo(Ctx, VT);
2469 // If the vselect is legal, assume we want to leave this as a vector setcc +
2470 // vselect. Otherwise, if this is going to be scalarized, we want to see if
2471 // min/max is legal on the scalar type.
2472 bool UseScalarMinMax = VT.isVector() &&
2473 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
2476 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2477 ISD::NodeType Opc = ISD::DELETED_NODE;
2478 switch (SPR.Flavor) {
2479 case SPF_UMAX: Opc = ISD::UMAX; break;
2480 case SPF_UMIN: Opc = ISD::UMIN; break;
2481 case SPF_SMAX: Opc = ISD::SMAX; break;
2482 case SPF_SMIN: Opc = ISD::SMIN; break;
2484 switch (SPR.NaNBehavior) {
2485 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2486 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2487 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2488 case SPNB_RETURNS_ANY: {
2489 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT))
2491 else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT))
2493 else if (UseScalarMinMax)
2494 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ?
2495 ISD::FMINNUM : ISD::FMINNAN;
2501 switch (SPR.NaNBehavior) {
2502 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2503 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2504 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2505 case SPNB_RETURNS_ANY:
2507 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT))
2509 else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT))
2511 else if (UseScalarMinMax)
2512 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ?
2513 ISD::FMAXNUM : ISD::FMAXNAN;
2520 if (Opc != ISD::DELETED_NODE &&
2521 (TLI.isOperationLegalOrCustom(Opc, VT) ||
2523 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) &&
2524 // If the underlying comparison instruction is used by any other
2525 // instruction, the consumed instructions won't be destroyed, so it is
2526 // not profitable to convert to a min/max.
2527 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2529 LHSVal = getValue(LHS);
2530 RHSVal = getValue(RHS);
2535 for (unsigned i = 0; i != NumValues; ++i) {
2536 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2537 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2538 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2539 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2540 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2544 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2545 DAG.getVTList(ValueVTs), Values));
2548 void SelectionDAGBuilder::visitTrunc(const User &I) {
2549 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2550 SDValue N = getValue(I.getOperand(0));
2551 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2553 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2556 void SelectionDAGBuilder::visitZExt(const User &I) {
2557 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2558 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2559 SDValue N = getValue(I.getOperand(0));
2560 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2562 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2565 void SelectionDAGBuilder::visitSExt(const User &I) {
2566 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2567 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2568 SDValue N = getValue(I.getOperand(0));
2569 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2571 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2574 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2575 // FPTrunc is never a no-op cast, no need to check
2576 SDValue N = getValue(I.getOperand(0));
2577 SDLoc dl = getCurSDLoc();
2578 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2579 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2580 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2581 DAG.getTargetConstant(
2582 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2585 void SelectionDAGBuilder::visitFPExt(const User &I) {
2586 // FPExt is never a no-op cast, no need to check
2587 SDValue N = getValue(I.getOperand(0));
2588 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2590 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2593 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2594 // FPToUI is never a no-op cast, no need to check
2595 SDValue N = getValue(I.getOperand(0));
2596 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2598 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2601 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2602 // FPToSI is never a no-op cast, no need to check
2603 SDValue N = getValue(I.getOperand(0));
2604 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2606 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2609 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2610 // UIToFP is never a no-op cast, no need to check
2611 SDValue N = getValue(I.getOperand(0));
2612 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2614 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2617 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2618 // SIToFP is never a no-op cast, no need to check
2619 SDValue N = getValue(I.getOperand(0));
2620 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2622 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2625 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2626 // What to do depends on the size of the integer and the size of the pointer.
2627 // We can either truncate, zero extend, or no-op, accordingly.
2628 SDValue N = getValue(I.getOperand(0));
2629 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2631 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2634 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2635 // What to do depends on the size of the integer and the size of the pointer.
2636 // We can either truncate, zero extend, or no-op, accordingly.
2637 SDValue N = getValue(I.getOperand(0));
2638 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2640 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2643 void SelectionDAGBuilder::visitBitCast(const User &I) {
2644 SDValue N = getValue(I.getOperand(0));
2645 SDLoc dl = getCurSDLoc();
2646 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2649 // BitCast assures us that source and destination are the same size so this is
2650 // either a BITCAST or a no-op.
2651 if (DestVT != N.getValueType())
2652 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2653 DestVT, N)); // convert types.
2654 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2655 // might fold any kind of constant expression to an integer constant and that
2656 // is not what we are looking for. Only regcognize a bitcast of a genuine
2657 // constant integer as an opaque constant.
2658 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2659 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2662 setValue(&I, N); // noop cast.
2665 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2667 const Value *SV = I.getOperand(0);
2668 SDValue N = getValue(SV);
2669 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2671 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2672 unsigned DestAS = I.getType()->getPointerAddressSpace();
2674 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2675 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2680 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2682 SDValue InVec = getValue(I.getOperand(0));
2683 SDValue InVal = getValue(I.getOperand(1));
2684 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2685 TLI.getVectorIdxTy(DAG.getDataLayout()));
2686 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2687 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2688 InVec, InVal, InIdx));
2691 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2692 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2693 SDValue InVec = getValue(I.getOperand(0));
2694 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2695 TLI.getVectorIdxTy(DAG.getDataLayout()));
2696 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2697 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2701 // Utility for visitShuffleVector - Return true if every element in Mask,
2702 // beginning from position Pos and ending in Pos+Size, falls within the
2703 // specified sequential range [L, L+Pos). or is undef.
2704 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2705 unsigned Pos, unsigned Size, int Low) {
2706 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2707 if (Mask[i] >= 0 && Mask[i] != Low)
2712 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2713 SDValue Src1 = getValue(I.getOperand(0));
2714 SDValue Src2 = getValue(I.getOperand(1));
2716 SmallVector<int, 8> Mask;
2717 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2718 unsigned MaskNumElts = Mask.size();
2720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2721 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2722 EVT SrcVT = Src1.getValueType();
2723 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2725 if (SrcNumElts == MaskNumElts) {
2726 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2731 // Normalize the shuffle vector since mask and vector length don't match.
2732 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2733 // Mask is longer than the source vectors and is a multiple of the source
2734 // vectors. We can use concatenate vector to make the mask and vectors
2736 if (SrcNumElts*2 == MaskNumElts) {
2737 // First check for Src1 in low and Src2 in high
2738 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2739 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2740 // The shuffle is concatenating two vectors together.
2741 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2745 // Then check for Src2 in low and Src1 in high
2746 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2747 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2748 // The shuffle is concatenating two vectors together.
2749 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2755 // Pad both vectors with undefs to make them the same length as the mask.
2756 unsigned NumConcat = MaskNumElts / SrcNumElts;
2757 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2758 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2759 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2761 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2762 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2766 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2767 getCurSDLoc(), VT, MOps1);
2768 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2769 getCurSDLoc(), VT, MOps2);
2771 // Readjust mask for new input vector length.
2772 SmallVector<int, 8> MappedOps;
2773 for (unsigned i = 0; i != MaskNumElts; ++i) {
2775 if (Idx >= (int)SrcNumElts)
2776 Idx -= SrcNumElts - MaskNumElts;
2777 MappedOps.push_back(Idx);
2780 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2785 if (SrcNumElts > MaskNumElts) {
2786 // Analyze the access pattern of the vector to see if we can extract
2787 // two subvectors and do the shuffle. The analysis is done by calculating
2788 // the range of elements the mask access on both vectors.
2789 int MinRange[2] = { static_cast<int>(SrcNumElts),
2790 static_cast<int>(SrcNumElts)};
2791 int MaxRange[2] = {-1, -1};
2793 for (unsigned i = 0; i != MaskNumElts; ++i) {
2799 if (Idx >= (int)SrcNumElts) {
2803 if (Idx > MaxRange[Input])
2804 MaxRange[Input] = Idx;
2805 if (Idx < MinRange[Input])
2806 MinRange[Input] = Idx;
2809 // Check if the access is smaller than the vector size and can we find
2810 // a reasonable extract index.
2811 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2813 int StartIdx[2]; // StartIdx to extract from
2814 for (unsigned Input = 0; Input < 2; ++Input) {
2815 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2816 RangeUse[Input] = 0; // Unused
2817 StartIdx[Input] = 0;
2821 // Find a good start index that is a multiple of the mask length. Then
2822 // see if the rest of the elements are in range.
2823 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2824 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2825 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2826 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2829 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2830 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2833 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2834 // Extract appropriate subvector and generate a vector shuffle
2835 for (unsigned Input = 0; Input < 2; ++Input) {
2836 SDValue &Src = Input == 0 ? Src1 : Src2;
2837 if (RangeUse[Input] == 0)
2838 Src = DAG.getUNDEF(VT);
2840 SDLoc dl = getCurSDLoc();
2842 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2843 DAG.getConstant(StartIdx[Input], dl,
2844 TLI.getVectorIdxTy(DAG.getDataLayout())));
2848 // Calculate new mask.
2849 SmallVector<int, 8> MappedOps;
2850 for (unsigned i = 0; i != MaskNumElts; ++i) {
2853 if (Idx < (int)SrcNumElts)
2856 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2858 MappedOps.push_back(Idx);
2861 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2867 // We can't use either concat vectors or extract subvectors so fall back to
2868 // replacing the shuffle with extract and build vector.
2869 // to insert and build vector.
2870 EVT EltVT = VT.getVectorElementType();
2871 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2872 SDLoc dl = getCurSDLoc();
2873 SmallVector<SDValue,8> Ops;
2874 for (unsigned i = 0; i != MaskNumElts; ++i) {
2879 Res = DAG.getUNDEF(EltVT);
2881 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2882 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2884 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2885 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2891 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2894 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2895 const Value *Op0 = I.getOperand(0);
2896 const Value *Op1 = I.getOperand(1);
2897 Type *AggTy = I.getType();
2898 Type *ValTy = Op1->getType();
2899 bool IntoUndef = isa<UndefValue>(Op0);
2900 bool FromUndef = isa<UndefValue>(Op1);
2902 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2904 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2905 SmallVector<EVT, 4> AggValueVTs;
2906 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2907 SmallVector<EVT, 4> ValValueVTs;
2908 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2910 unsigned NumAggValues = AggValueVTs.size();
2911 unsigned NumValValues = ValValueVTs.size();
2912 SmallVector<SDValue, 4> Values(NumAggValues);
2914 // Ignore an insertvalue that produces an empty object
2915 if (!NumAggValues) {
2916 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2920 SDValue Agg = getValue(Op0);
2922 // Copy the beginning value(s) from the original aggregate.
2923 for (; i != LinearIndex; ++i)
2924 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2925 SDValue(Agg.getNode(), Agg.getResNo() + i);
2926 // Copy values from the inserted value(s).
2928 SDValue Val = getValue(Op1);
2929 for (; i != LinearIndex + NumValValues; ++i)
2930 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2931 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2933 // Copy remaining value(s) from the original aggregate.
2934 for (; i != NumAggValues; ++i)
2935 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2936 SDValue(Agg.getNode(), Agg.getResNo() + i);
2938 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2939 DAG.getVTList(AggValueVTs), Values));
2942 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2943 const Value *Op0 = I.getOperand(0);
2944 Type *AggTy = Op0->getType();
2945 Type *ValTy = I.getType();
2946 bool OutOfUndef = isa<UndefValue>(Op0);
2948 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2951 SmallVector<EVT, 4> ValValueVTs;
2952 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2954 unsigned NumValValues = ValValueVTs.size();
2956 // Ignore a extractvalue that produces an empty object
2957 if (!NumValValues) {
2958 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2962 SmallVector<SDValue, 4> Values(NumValValues);
2964 SDValue Agg = getValue(Op0);
2965 // Copy out the selected value(s).
2966 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2967 Values[i - LinearIndex] =
2969 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2970 SDValue(Agg.getNode(), Agg.getResNo() + i);
2972 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2973 DAG.getVTList(ValValueVTs), Values));
2976 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2977 Value *Op0 = I.getOperand(0);
2978 // Note that the pointer operand may be a vector of pointers. Take the scalar
2979 // element which holds a pointer.
2980 Type *Ty = Op0->getType()->getScalarType();
2981 unsigned AS = Ty->getPointerAddressSpace();
2982 SDValue N = getValue(Op0);
2983 SDLoc dl = getCurSDLoc();
2985 // Normalize Vector GEP - all scalar operands should be converted to the
2987 unsigned VectorWidth = I.getType()->isVectorTy() ?
2988 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2990 if (VectorWidth && !N.getValueType().isVector()) {
2991 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2992 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2993 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2995 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2997 const Value *Idx = *OI;
2998 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2999 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3002 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3004 // In an inbouds GEP with an offset that is nonnegative even when
3005 // interpreted as signed, assume there is no unsigned overflow.
3007 if (int64_t(Offset) >= 0 && cast<GEPOperator>(I).isInBounds())
3008 Flags.setNoUnsignedWrap(true);
3010 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
3011 DAG.getConstant(Offset, dl, N.getValueType()), &Flags);
3014 Ty = StTy->getElementType(Field);
3016 Ty = cast<SequentialType>(Ty)->getElementType();
3018 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
3019 unsigned PtrSize = PtrTy.getSizeInBits();
3020 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3022 // If this is a scalar constant or a splat vector of constants,
3023 // handle it quickly.
3024 const auto *CI = dyn_cast<ConstantInt>(Idx);
3025 if (!CI && isa<ConstantDataVector>(Idx) &&
3026 cast<ConstantDataVector>(Idx)->getSplatValue())
3027 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3032 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3033 SDValue OffsVal = VectorWidth ?
3034 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3035 DAG.getConstant(Offs, dl, PtrTy);
3037 // In an inbouds GEP with an offset that is nonnegative even when
3038 // interpreted as signed, assume there is no unsigned overflow.
3040 if (Offs.isNonNegative() && cast<GEPOperator>(I).isInBounds())
3041 Flags.setNoUnsignedWrap(true);
3043 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal, &Flags);
3047 // N = N + Idx * ElementSize;
3048 SDValue IdxN = getValue(Idx);
3050 if (!IdxN.getValueType().isVector() && VectorWidth) {
3051 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3052 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3053 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3055 // If the index is smaller or larger than intptr_t, truncate or extend
3057 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3059 // If this is a multiply by a power of two, turn it into a shl
3060 // immediately. This is a very common case.
3061 if (ElementSize != 1) {
3062 if (ElementSize.isPowerOf2()) {
3063 unsigned Amt = ElementSize.logBase2();
3064 IdxN = DAG.getNode(ISD::SHL, dl,
3065 N.getValueType(), IdxN,
3066 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3068 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3069 IdxN = DAG.getNode(ISD::MUL, dl,
3070 N.getValueType(), IdxN, Scale);
3074 N = DAG.getNode(ISD::ADD, dl,
3075 N.getValueType(), N, IdxN);
3082 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3083 // If this is a fixed sized alloca in the entry block of the function,
3084 // allocate it statically on the stack.
3085 if (FuncInfo.StaticAllocaMap.count(&I))
3086 return; // getValue will auto-populate this.
3088 SDLoc dl = getCurSDLoc();
3089 Type *Ty = I.getAllocatedType();
3090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3091 auto &DL = DAG.getDataLayout();
3092 uint64_t TySize = DL.getTypeAllocSize(Ty);
3094 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3096 SDValue AllocSize = getValue(I.getArraySize());
3098 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3099 if (AllocSize.getValueType() != IntPtr)
3100 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3102 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3104 DAG.getConstant(TySize, dl, IntPtr));
3106 // Handle alignment. If the requested alignment is less than or equal to
3107 // the stack alignment, ignore it. If the size is greater than or equal to
3108 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3109 unsigned StackAlign =
3110 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3111 if (Align <= StackAlign)
3114 // Round the size of the allocation up to the stack alignment size
3115 // by add SA-1 to the size. This doesn't overflow because we're computing
3116 // an address inside an alloca.
3118 Flags.setNoUnsignedWrap(true);
3119 AllocSize = DAG.getNode(ISD::ADD, dl,
3120 AllocSize.getValueType(), AllocSize,
3121 DAG.getIntPtrConstant(StackAlign - 1, dl), &Flags);
3123 // Mask out the low bits for alignment purposes.
3124 AllocSize = DAG.getNode(ISD::AND, dl,
3125 AllocSize.getValueType(), AllocSize,
3126 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3129 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3130 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3131 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3133 DAG.setRoot(DSA.getValue(1));
3135 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3138 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3140 return visitAtomicLoad(I);
3142 const Value *SV = I.getOperand(0);
3143 SDValue Ptr = getValue(SV);
3145 Type *Ty = I.getType();
3147 bool isVolatile = I.isVolatile();
3148 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3150 // The IR notion of invariant_load only guarantees that all *non-faulting*
3151 // invariant loads result in the same value. The MI notion of invariant load
3152 // guarantees that the load can be legally moved to any location within its
3153 // containing function. The MI notion of invariant_load is stronger than the
3154 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3155 // with a guarantee that the location being loaded from is dereferenceable
3156 // throughout the function's lifetime.
3158 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3159 isDereferenceablePointer(SV, DAG.getDataLayout());
3160 unsigned Alignment = I.getAlignment();
3163 I.getAAMetadata(AAInfo);
3164 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3166 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3167 SmallVector<EVT, 4> ValueVTs;
3168 SmallVector<uint64_t, 4> Offsets;
3169 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3170 unsigned NumValues = ValueVTs.size();
3175 bool ConstantMemory = false;
3176 if (isVolatile || NumValues > MaxParallelChains)
3177 // Serialize volatile loads with other side effects.
3179 else if (AA->pointsToConstantMemory(MemoryLocation(
3180 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3181 // Do not serialize (non-volatile) loads of constant memory with anything.
3182 Root = DAG.getEntryNode();
3183 ConstantMemory = true;
3185 // Do not serialize non-volatile loads against each other.
3186 Root = DAG.getRoot();
3189 SDLoc dl = getCurSDLoc();
3192 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3194 // An aggregate load cannot wrap around the address space, so offsets to its
3195 // parts don't wrap either.
3197 Flags.setNoUnsignedWrap(true);
3199 SmallVector<SDValue, 4> Values(NumValues);
3200 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3201 EVT PtrVT = Ptr.getValueType();
3202 unsigned ChainI = 0;
3203 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3204 // Serializing loads here may result in excessive register pressure, and
3205 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3206 // could recover a bit by hoisting nodes upward in the chain by recognizing
3207 // they are side-effect free or do not alias. The optimizer should really
3208 // avoid this case by converting large object/array copies to llvm.memcpy
3209 // (MaxParallelChains should always remain as failsafe).
3210 if (ChainI == MaxParallelChains) {
3211 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3212 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3213 makeArrayRef(Chains.data(), ChainI));
3217 SDValue A = DAG.getNode(ISD::ADD, dl,
3219 DAG.getConstant(Offsets[i], dl, PtrVT),
3221 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3222 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3223 isNonTemporal, isInvariant, Alignment, AAInfo,
3227 Chains[ChainI] = L.getValue(1);
3230 if (!ConstantMemory) {
3231 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3232 makeArrayRef(Chains.data(), ChainI));
3236 PendingLoads.push_back(Chain);
3239 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3240 DAG.getVTList(ValueVTs), Values));
3243 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3245 return visitAtomicStore(I);
3247 const Value *SrcV = I.getOperand(0);
3248 const Value *PtrV = I.getOperand(1);
3250 SmallVector<EVT, 4> ValueVTs;
3251 SmallVector<uint64_t, 4> Offsets;
3252 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3253 SrcV->getType(), ValueVTs, &Offsets);
3254 unsigned NumValues = ValueVTs.size();
3258 // Get the lowered operands. Note that we do this after
3259 // checking if NumResults is zero, because with zero results
3260 // the operands won't have values in the map.
3261 SDValue Src = getValue(SrcV);
3262 SDValue Ptr = getValue(PtrV);
3264 SDValue Root = getRoot();
3265 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3266 EVT PtrVT = Ptr.getValueType();
3267 bool isVolatile = I.isVolatile();
3268 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3269 unsigned Alignment = I.getAlignment();
3270 SDLoc dl = getCurSDLoc();
3273 I.getAAMetadata(AAInfo);
3275 // An aggregate load cannot wrap around the address space, so offsets to its
3276 // parts don't wrap either.
3278 Flags.setNoUnsignedWrap(true);
3280 unsigned ChainI = 0;
3281 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3282 // See visitLoad comments.
3283 if (ChainI == MaxParallelChains) {
3284 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3285 makeArrayRef(Chains.data(), ChainI));
3289 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3290 DAG.getConstant(Offsets[i], dl, PtrVT), &Flags);
3291 SDValue St = DAG.getStore(Root, dl,
3292 SDValue(Src.getNode(), Src.getResNo() + i),
3293 Add, MachinePointerInfo(PtrV, Offsets[i]),
3294 isVolatile, isNonTemporal, Alignment, AAInfo);
3295 Chains[ChainI] = St;
3298 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3299 makeArrayRef(Chains.data(), ChainI));
3300 DAG.setRoot(StoreNode);
3303 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3304 SDLoc sdl = getCurSDLoc();
3306 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3307 Value *PtrOperand = I.getArgOperand(1);
3308 SDValue Ptr = getValue(PtrOperand);
3309 SDValue Src0 = getValue(I.getArgOperand(0));
3310 SDValue Mask = getValue(I.getArgOperand(3));
3311 EVT VT = Src0.getValueType();
3312 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3314 Alignment = DAG.getEVTAlignment(VT);
3317 I.getAAMetadata(AAInfo);
3319 MachineMemOperand *MMO =
3320 DAG.getMachineFunction().
3321 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3322 MachineMemOperand::MOStore, VT.getStoreSize(),
3324 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3326 DAG.setRoot(StoreNode);
3327 setValue(&I, StoreNode);
3330 // Get a uniform base for the Gather/Scatter intrinsic.
3331 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3332 // We try to represent it as a base pointer + vector of indices.
3333 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3334 // The first operand of the GEP may be a single pointer or a vector of pointers
3336 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3338 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3339 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3341 // When the first GEP operand is a single pointer - it is the uniform base we
3342 // are looking for. If first operand of the GEP is a splat vector - we
3343 // extract the spalt value and use it as a uniform base.
3344 // In all other cases the function returns 'false'.
3346 static bool getUniformBase(const Value *& Ptr, SDValue& Base, SDValue& Index,
3347 SelectionDAGBuilder* SDB) {
3349 SelectionDAG& DAG = SDB->DAG;
3350 LLVMContext &Context = *DAG.getContext();
3352 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3353 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3354 if (!GEP || GEP->getNumOperands() > 2)
3357 const Value *GEPPtr = GEP->getPointerOperand();
3358 if (!GEPPtr->getType()->isVectorTy())
3360 else if (!(Ptr = getSplatValue(GEPPtr)))
3363 Value *IndexVal = GEP->getOperand(1);
3365 // The operands of the GEP may be defined in another basic block.
3366 // In this case we'll not find nodes for the operands.
3367 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3370 Base = SDB->getValue(Ptr);
3371 Index = SDB->getValue(IndexVal);
3373 // Suppress sign extension.
3374 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3375 if (SDB->findValue(Sext->getOperand(0))) {
3376 IndexVal = Sext->getOperand(0);
3377 Index = SDB->getValue(IndexVal);
3380 if (!Index.getValueType().isVector()) {
3381 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3382 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3383 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3384 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3389 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3390 SDLoc sdl = getCurSDLoc();
3392 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3393 const Value *Ptr = I.getArgOperand(1);
3394 SDValue Src0 = getValue(I.getArgOperand(0));
3395 SDValue Mask = getValue(I.getArgOperand(3));
3396 EVT VT = Src0.getValueType();
3397 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3399 Alignment = DAG.getEVTAlignment(VT);
3400 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3403 I.getAAMetadata(AAInfo);
3407 const Value *BasePtr = Ptr;
3408 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3410 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3411 MachineMemOperand *MMO = DAG.getMachineFunction().
3412 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3413 MachineMemOperand::MOStore, VT.getStoreSize(),
3416 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3417 Index = getValue(Ptr);
3419 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3420 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3422 DAG.setRoot(Scatter);
3423 setValue(&I, Scatter);
3426 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3427 SDLoc sdl = getCurSDLoc();
3429 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3430 Value *PtrOperand = I.getArgOperand(0);
3431 SDValue Ptr = getValue(PtrOperand);
3432 SDValue Src0 = getValue(I.getArgOperand(3));
3433 SDValue Mask = getValue(I.getArgOperand(2));
3435 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3436 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3437 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3439 Alignment = DAG.getEVTAlignment(VT);
3442 I.getAAMetadata(AAInfo);
3443 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3445 SDValue InChain = DAG.getRoot();
3446 if (AA->pointsToConstantMemory(MemoryLocation(
3447 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3449 // Do not serialize (non-volatile) loads of constant memory with anything.
3450 InChain = DAG.getEntryNode();
3453 MachineMemOperand *MMO =
3454 DAG.getMachineFunction().
3455 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3456 MachineMemOperand::MOLoad, VT.getStoreSize(),
3457 Alignment, AAInfo, Ranges);
3459 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3461 SDValue OutChain = Load.getValue(1);
3462 DAG.setRoot(OutChain);
3466 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3467 SDLoc sdl = getCurSDLoc();
3469 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3470 const Value *Ptr = I.getArgOperand(0);
3471 SDValue Src0 = getValue(I.getArgOperand(3));
3472 SDValue Mask = getValue(I.getArgOperand(2));
3474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3475 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3476 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3478 Alignment = DAG.getEVTAlignment(VT);
3481 I.getAAMetadata(AAInfo);
3482 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3484 SDValue Root = DAG.getRoot();
3487 const Value *BasePtr = Ptr;
3488 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3489 bool ConstantMemory = false;
3491 AA->pointsToConstantMemory(MemoryLocation(
3492 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3494 // Do not serialize (non-volatile) loads of constant memory with anything.
3495 Root = DAG.getEntryNode();
3496 ConstantMemory = true;
3499 MachineMemOperand *MMO =
3500 DAG.getMachineFunction().
3501 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3502 MachineMemOperand::MOLoad, VT.getStoreSize(),
3503 Alignment, AAInfo, Ranges);
3506 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3507 Index = getValue(Ptr);
3509 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3510 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3513 SDValue OutChain = Gather.getValue(1);
3514 if (!ConstantMemory)
3515 PendingLoads.push_back(OutChain);
3516 setValue(&I, Gather);
3519 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3520 SDLoc dl = getCurSDLoc();
3521 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3522 AtomicOrdering FailureOrder = I.getFailureOrdering();
3523 SynchronizationScope Scope = I.getSynchScope();
3525 SDValue InChain = getRoot();
3527 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3528 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3529 SDValue L = DAG.getAtomicCmpSwap(
3530 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3531 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3532 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3533 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3535 SDValue OutChain = L.getValue(2);
3538 DAG.setRoot(OutChain);
3541 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3542 SDLoc dl = getCurSDLoc();
3544 switch (I.getOperation()) {
3545 default: llvm_unreachable("Unknown atomicrmw operation");
3546 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3547 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3548 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3549 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3550 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3551 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3552 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3553 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3554 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3555 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3556 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3558 AtomicOrdering Order = I.getOrdering();
3559 SynchronizationScope Scope = I.getSynchScope();
3561 SDValue InChain = getRoot();
3564 DAG.getAtomic(NT, dl,
3565 getValue(I.getValOperand()).getSimpleValueType(),
3567 getValue(I.getPointerOperand()),
3568 getValue(I.getValOperand()),
3569 I.getPointerOperand(),
3570 /* Alignment=*/ 0, Order, Scope);
3572 SDValue OutChain = L.getValue(1);
3575 DAG.setRoot(OutChain);
3578 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3579 SDLoc dl = getCurSDLoc();
3580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3583 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3584 TLI.getPointerTy(DAG.getDataLayout()));
3585 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3586 TLI.getPointerTy(DAG.getDataLayout()));
3587 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3590 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3591 SDLoc dl = getCurSDLoc();
3592 AtomicOrdering Order = I.getOrdering();
3593 SynchronizationScope Scope = I.getSynchScope();
3595 SDValue InChain = getRoot();
3597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3598 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3600 if (I.getAlignment() < VT.getSizeInBits() / 8)
3601 report_fatal_error("Cannot generate unaligned atomic load");
3603 MachineMemOperand *MMO =
3604 DAG.getMachineFunction().
3605 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3606 MachineMemOperand::MOVolatile |
3607 MachineMemOperand::MOLoad,
3609 I.getAlignment() ? I.getAlignment() :
3610 DAG.getEVTAlignment(VT));
3612 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3614 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3615 getValue(I.getPointerOperand()), MMO,
3618 SDValue OutChain = L.getValue(1);
3621 DAG.setRoot(OutChain);
3624 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3625 SDLoc dl = getCurSDLoc();
3627 AtomicOrdering Order = I.getOrdering();
3628 SynchronizationScope Scope = I.getSynchScope();
3630 SDValue InChain = getRoot();
3632 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3634 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3636 if (I.getAlignment() < VT.getSizeInBits() / 8)
3637 report_fatal_error("Cannot generate unaligned atomic store");
3640 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3642 getValue(I.getPointerOperand()),
3643 getValue(I.getValueOperand()),
3644 I.getPointerOperand(), I.getAlignment(),
3647 DAG.setRoot(OutChain);
3650 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3652 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3653 unsigned Intrinsic) {
3654 bool HasChain = !I.doesNotAccessMemory();
3655 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3657 // Build the operand list.
3658 SmallVector<SDValue, 8> Ops;
3659 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3661 // We don't need to serialize loads against other loads.
3662 Ops.push_back(DAG.getRoot());
3664 Ops.push_back(getRoot());
3668 // Info is set by getTgtMemInstrinsic
3669 TargetLowering::IntrinsicInfo Info;
3670 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3671 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3673 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3674 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3675 Info.opc == ISD::INTRINSIC_W_CHAIN)
3676 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3677 TLI.getPointerTy(DAG.getDataLayout())));
3679 // Add all operands of the call to the operand list.
3680 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3681 SDValue Op = getValue(I.getArgOperand(i));
3685 SmallVector<EVT, 4> ValueVTs;
3686 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3689 ValueVTs.push_back(MVT::Other);
3691 SDVTList VTs = DAG.getVTList(ValueVTs);
3695 if (IsTgtIntrinsic) {
3696 // This is target intrinsic that touches memory
3697 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3698 VTs, Ops, Info.memVT,
3699 MachinePointerInfo(Info.ptrVal, Info.offset),
3700 Info.align, Info.vol,
3701 Info.readMem, Info.writeMem, Info.size);
3702 } else if (!HasChain) {
3703 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3704 } else if (!I.getType()->isVoidTy()) {
3705 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3707 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3711 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3713 PendingLoads.push_back(Chain);
3718 if (!I.getType()->isVoidTy()) {
3719 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3720 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3721 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3724 setValue(&I, Result);
3728 /// GetSignificand - Get the significand and build it into a floating-point
3729 /// number with exponent of 1:
3731 /// Op = (Op & 0x007fffff) | 0x3f800000;
3733 /// where Op is the hexadecimal representation of floating point value.
3735 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3736 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3737 DAG.getConstant(0x007fffff, dl, MVT::i32));
3738 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3739 DAG.getConstant(0x3f800000, dl, MVT::i32));
3740 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3743 /// GetExponent - Get the exponent:
3745 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3747 /// where Op is the hexadecimal representation of floating point value.
3749 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3751 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3752 DAG.getConstant(0x7f800000, dl, MVT::i32));
3753 SDValue t1 = DAG.getNode(
3754 ISD::SRL, dl, MVT::i32, t0,
3755 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3756 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3757 DAG.getConstant(127, dl, MVT::i32));
3758 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3761 /// getF32Constant - Get 32-bit floating point constant.
3763 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3764 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3768 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3769 SelectionDAG &DAG) {
3770 // TODO: What fast-math-flags should be set on the floating-point nodes?
3772 // IntegerPartOfX = ((int32_t)(t0);
3773 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3775 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3776 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3777 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3779 // IntegerPartOfX <<= 23;
3780 IntegerPartOfX = DAG.getNode(
3781 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3782 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3783 DAG.getDataLayout())));
3785 SDValue TwoToFractionalPartOfX;
3786 if (LimitFloatPrecision <= 6) {
3787 // For floating-point precision of 6:
3789 // TwoToFractionalPartOfX =
3791 // (0.735607626f + 0.252464424f * x) * x;
3793 // error 0.0144103317, which is 6 bits
3794 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3795 getF32Constant(DAG, 0x3e814304, dl));
3796 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3797 getF32Constant(DAG, 0x3f3c50c8, dl));
3798 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3799 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3800 getF32Constant(DAG, 0x3f7f5e7e, dl));
3801 } else if (LimitFloatPrecision <= 12) {
3802 // For floating-point precision of 12:
3804 // TwoToFractionalPartOfX =
3807 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3809 // error 0.000107046256, which is 13 to 14 bits
3810 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3811 getF32Constant(DAG, 0x3da235e3, dl));
3812 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3813 getF32Constant(DAG, 0x3e65b8f3, dl));
3814 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3815 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3816 getF32Constant(DAG, 0x3f324b07, dl));
3817 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3818 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3819 getF32Constant(DAG, 0x3f7ff8fd, dl));
3820 } else { // LimitFloatPrecision <= 18
3821 // For floating-point precision of 18:
3823 // TwoToFractionalPartOfX =
3827 // (0.554906021e-1f +
3828 // (0.961591928e-2f +
3829 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3830 // error 2.47208000*10^(-7), which is better than 18 bits
3831 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3832 getF32Constant(DAG, 0x3924b03e, dl));
3833 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3834 getF32Constant(DAG, 0x3ab24b87, dl));
3835 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3836 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3837 getF32Constant(DAG, 0x3c1d8c17, dl));
3838 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3839 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3840 getF32Constant(DAG, 0x3d634a1d, dl));
3841 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3842 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3843 getF32Constant(DAG, 0x3e75fe14, dl));
3844 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3845 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3846 getF32Constant(DAG, 0x3f317234, dl));
3847 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3848 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3849 getF32Constant(DAG, 0x3f800000, dl));
3852 // Add the exponent into the result in integer domain.
3853 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3854 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3855 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3858 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3859 /// limited-precision mode.
3860 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3861 const TargetLowering &TLI) {
3862 if (Op.getValueType() == MVT::f32 &&
3863 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3865 // Put the exponent in the right bit position for later addition to the
3868 // #define LOG2OFe 1.4426950f
3869 // t0 = Op * LOG2OFe
3871 // TODO: What fast-math-flags should be set here?
3872 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3873 getF32Constant(DAG, 0x3fb8aa3b, dl));
3874 return getLimitedPrecisionExp2(t0, dl, DAG);
3877 // No special expansion.
3878 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3881 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3882 /// limited-precision mode.
3883 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3884 const TargetLowering &TLI) {
3886 // TODO: What fast-math-flags should be set on the floating-point nodes?
3888 if (Op.getValueType() == MVT::f32 &&
3889 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3890 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3892 // Scale the exponent by log(2) [0.69314718f].
3893 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3894 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3895 getF32Constant(DAG, 0x3f317218, dl));
3897 // Get the significand and build it into a floating-point number with
3899 SDValue X = GetSignificand(DAG, Op1, dl);
3901 SDValue LogOfMantissa;
3902 if (LimitFloatPrecision <= 6) {
3903 // For floating-point precision of 6:
3907 // (1.4034025f - 0.23903021f * x) * x;
3909 // error 0.0034276066, which is better than 8 bits
3910 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3911 getF32Constant(DAG, 0xbe74c456, dl));
3912 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3913 getF32Constant(DAG, 0x3fb3a2b1, dl));
3914 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3915 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3916 getF32Constant(DAG, 0x3f949a29, dl));
3917 } else if (LimitFloatPrecision <= 12) {
3918 // For floating-point precision of 12:
3924 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3926 // error 0.000061011436, which is 14 bits
3927 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3928 getF32Constant(DAG, 0xbd67b6d6, dl));
3929 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3930 getF32Constant(DAG, 0x3ee4f4b8, dl));
3931 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3932 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3933 getF32Constant(DAG, 0x3fbc278b, dl));
3934 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3935 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3936 getF32Constant(DAG, 0x40348e95, dl));
3937 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3938 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3939 getF32Constant(DAG, 0x3fdef31a, dl));
3940 } else { // LimitFloatPrecision <= 18
3941 // For floating-point precision of 18:
3949 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3951 // error 0.0000023660568, which is better than 18 bits
3952 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3953 getF32Constant(DAG, 0xbc91e5ac, dl));
3954 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3955 getF32Constant(DAG, 0x3e4350aa, dl));
3956 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3957 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3958 getF32Constant(DAG, 0x3f60d3e3, dl));
3959 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3960 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3961 getF32Constant(DAG, 0x4011cdf0, dl));
3962 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3963 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3964 getF32Constant(DAG, 0x406cfd1c, dl));
3965 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3966 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3967 getF32Constant(DAG, 0x408797cb, dl));
3968 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3969 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3970 getF32Constant(DAG, 0x4006dcab, dl));
3973 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3976 // No special expansion.
3977 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3980 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3981 /// limited-precision mode.
3982 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3983 const TargetLowering &TLI) {
3985 // TODO: What fast-math-flags should be set on the floating-point nodes?
3987 if (Op.getValueType() == MVT::f32 &&
3988 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3989 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3991 // Get the exponent.
3992 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3994 // Get the significand and build it into a floating-point number with
3996 SDValue X = GetSignificand(DAG, Op1, dl);
3998 // Different possible minimax approximations of significand in
3999 // floating-point for various degrees of accuracy over [1,2].
4000 SDValue Log2ofMantissa;
4001 if (LimitFloatPrecision <= 6) {
4002 // For floating-point precision of 6:
4004 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4006 // error 0.0049451742, which is more than 7 bits
4007 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4008 getF32Constant(DAG, 0xbeb08fe0, dl));
4009 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4010 getF32Constant(DAG, 0x40019463, dl));
4011 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4012 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4013 getF32Constant(DAG, 0x3fd6633d, dl));
4014 } else if (LimitFloatPrecision <= 12) {
4015 // For floating-point precision of 12:
4021 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4023 // error 0.0000876136000, which is better than 13 bits
4024 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4025 getF32Constant(DAG, 0xbda7262e, dl));
4026 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4027 getF32Constant(DAG, 0x3f25280b, dl));
4028 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4029 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4030 getF32Constant(DAG, 0x4007b923, dl));
4031 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4032 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4033 getF32Constant(DAG, 0x40823e2f, dl));
4034 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4035 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4036 getF32Constant(DAG, 0x4020d29c, dl));
4037 } else { // LimitFloatPrecision <= 18
4038 // For floating-point precision of 18:
4047 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4049 // error 0.0000018516, which is better than 18 bits
4050 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4051 getF32Constant(DAG, 0xbcd2769e, dl));
4052 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4053 getF32Constant(DAG, 0x3e8ce0b9, dl));
4054 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4055 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4056 getF32Constant(DAG, 0x3fa22ae7, dl));
4057 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4058 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4059 getF32Constant(DAG, 0x40525723, dl));
4060 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4061 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4062 getF32Constant(DAG, 0x40aaf200, dl));
4063 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4064 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4065 getF32Constant(DAG, 0x40c39dad, dl));
4066 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4067 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4068 getF32Constant(DAG, 0x4042902c, dl));
4071 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4074 // No special expansion.
4075 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4078 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4079 /// limited-precision mode.
4080 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4081 const TargetLowering &TLI) {
4083 // TODO: What fast-math-flags should be set on the floating-point nodes?
4085 if (Op.getValueType() == MVT::f32 &&
4086 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4087 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4089 // Scale the exponent by log10(2) [0.30102999f].
4090 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4091 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4092 getF32Constant(DAG, 0x3e9a209a, dl));
4094 // Get the significand and build it into a floating-point number with
4096 SDValue X = GetSignificand(DAG, Op1, dl);
4098 SDValue Log10ofMantissa;
4099 if (LimitFloatPrecision <= 6) {
4100 // For floating-point precision of 6:
4102 // Log10ofMantissa =
4104 // (0.60948995f - 0.10380950f * x) * x;
4106 // error 0.0014886165, which is 6 bits
4107 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4108 getF32Constant(DAG, 0xbdd49a13, dl));
4109 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4110 getF32Constant(DAG, 0x3f1c0789, dl));
4111 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4112 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4113 getF32Constant(DAG, 0x3f011300, dl));
4114 } else if (LimitFloatPrecision <= 12) {
4115 // For floating-point precision of 12:
4117 // Log10ofMantissa =
4120 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4122 // error 0.00019228036, which is better than 12 bits
4123 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4124 getF32Constant(DAG, 0x3d431f31, dl));
4125 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4126 getF32Constant(DAG, 0x3ea21fb2, dl));
4127 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4128 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4129 getF32Constant(DAG, 0x3f6ae232, dl));
4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4131 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4132 getF32Constant(DAG, 0x3f25f7c3, dl));
4133 } else { // LimitFloatPrecision <= 18
4134 // For floating-point precision of 18:
4136 // Log10ofMantissa =
4141 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4143 // error 0.0000037995730, which is better than 18 bits
4144 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4145 getF32Constant(DAG, 0x3c5d51ce, dl));
4146 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4147 getF32Constant(DAG, 0x3e00685a, dl));
4148 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4149 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4150 getF32Constant(DAG, 0x3efb6798, dl));
4151 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4152 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4153 getF32Constant(DAG, 0x3f88d192, dl));
4154 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4155 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4156 getF32Constant(DAG, 0x3fc4316c, dl));
4157 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4158 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4159 getF32Constant(DAG, 0x3f57ce70, dl));
4162 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4165 // No special expansion.
4166 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4169 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4170 /// limited-precision mode.
4171 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4172 const TargetLowering &TLI) {
4173 if (Op.getValueType() == MVT::f32 &&
4174 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4175 return getLimitedPrecisionExp2(Op, dl, DAG);
4177 // No special expansion.
4178 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4181 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4182 /// limited-precision mode with x == 10.0f.
4183 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4184 SelectionDAG &DAG, const TargetLowering &TLI) {
4185 bool IsExp10 = false;
4186 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4187 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4188 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4190 IsExp10 = LHSC->isExactlyValue(Ten);
4194 // TODO: What fast-math-flags should be set on the FMUL node?
4196 // Put the exponent in the right bit position for later addition to the
4199 // #define LOG2OF10 3.3219281f
4200 // t0 = Op * LOG2OF10;
4201 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4202 getF32Constant(DAG, 0x40549a78, dl));
4203 return getLimitedPrecisionExp2(t0, dl, DAG);
4206 // No special expansion.
4207 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4211 /// ExpandPowI - Expand a llvm.powi intrinsic.
4212 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4213 SelectionDAG &DAG) {
4214 // If RHS is a constant, we can expand this out to a multiplication tree,
4215 // otherwise we end up lowering to a call to __powidf2 (for example). When
4216 // optimizing for size, we only want to do this if the expansion would produce
4217 // a small number of multiplies, otherwise we do the full expansion.
4218 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4219 // Get the exponent as a positive value.
4220 unsigned Val = RHSC->getSExtValue();
4221 if ((int)Val < 0) Val = -Val;
4223 // powi(x, 0) -> 1.0
4225 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4227 const Function *F = DAG.getMachineFunction().getFunction();
4228 if (!F->optForSize() ||
4229 // If optimizing for size, don't insert too many multiplies.
4230 // This inserts up to 5 multiplies.
4231 countPopulation(Val) + Log2_32(Val) < 7) {
4232 // We use the simple binary decomposition method to generate the multiply
4233 // sequence. There are more optimal ways to do this (for example,
4234 // powi(x,15) generates one more multiply than it should), but this has
4235 // the benefit of being both really simple and much better than a libcall.
4236 SDValue Res; // Logically starts equal to 1.0
4237 SDValue CurSquare = LHS;
4238 // TODO: Intrinsics should have fast-math-flags that propagate to these
4243 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4245 Res = CurSquare; // 1.0*CurSquare.
4248 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4249 CurSquare, CurSquare);
4253 // If the original was negative, invert the result, producing 1/(x*x*x).
4254 if (RHSC->getSExtValue() < 0)
4255 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4256 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4261 // Otherwise, expand to a libcall.
4262 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4265 // getUnderlyingArgReg - Find underlying register used for a truncated or
4266 // bitcasted argument.
4267 static unsigned getUnderlyingArgReg(const SDValue &N) {
4268 switch (N.getOpcode()) {
4269 case ISD::CopyFromReg:
4270 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4272 case ISD::AssertZext:
4273 case ISD::AssertSext:
4275 return getUnderlyingArgReg(N.getOperand(0));
4281 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4282 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4283 /// At the end of instruction selection, they will be inserted to the entry BB.
4284 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4285 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4286 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4287 const Argument *Arg = dyn_cast<Argument>(V);
4291 MachineFunction &MF = DAG.getMachineFunction();
4292 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4294 // Ignore inlined function arguments here.
4296 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4297 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4300 Optional<MachineOperand> Op;
4301 // Some arguments' frame index is recorded during argument lowering.
4302 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4303 Op = MachineOperand::CreateFI(FI);
4305 if (!Op && N.getNode()) {
4306 unsigned Reg = getUnderlyingArgReg(N);
4307 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4308 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4309 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4314 Op = MachineOperand::CreateReg(Reg, false);
4318 // Check if ValueMap has reg number.
4319 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4320 if (VMI != FuncInfo.ValueMap.end())
4321 Op = MachineOperand::CreateReg(VMI->second, false);
4324 if (!Op && N.getNode())
4325 // Check if frame index is available.
4326 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4327 if (FrameIndexSDNode *FINode =
4328 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4329 Op = MachineOperand::CreateFI(FINode->getIndex());
4334 assert(Variable->isValidLocationForIntrinsic(DL) &&
4335 "Expected inlined-at fields to agree");
4337 FuncInfo.ArgDbgValues.push_back(
4338 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4339 Op->getReg(), Offset, Variable, Expr));
4341 FuncInfo.ArgDbgValues.push_back(
4342 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4345 .addMetadata(Variable)
4346 .addMetadata(Expr));
4351 // VisualStudio defines setjmp as _setjmp
4352 #if defined(_MSC_VER) && defined(setjmp) && \
4353 !defined(setjmp_undefined_for_msvc)
4354 # pragma push_macro("setjmp")
4356 # define setjmp_undefined_for_msvc
4359 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4360 /// we want to emit this as a call to a named external function, return the name
4361 /// otherwise lower it and return null.
4363 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4365 SDLoc sdl = getCurSDLoc();
4366 DebugLoc dl = getCurDebugLoc();
4369 switch (Intrinsic) {
4371 // By default, turn this into a target intrinsic node.
4372 visitTargetIntrinsic(I, Intrinsic);
4374 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4375 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4376 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4377 case Intrinsic::returnaddress:
4378 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4379 TLI.getPointerTy(DAG.getDataLayout()),
4380 getValue(I.getArgOperand(0))));
4382 case Intrinsic::frameaddress:
4383 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4384 TLI.getPointerTy(DAG.getDataLayout()),
4385 getValue(I.getArgOperand(0))));
4387 case Intrinsic::read_register: {
4388 Value *Reg = I.getArgOperand(0);
4389 SDValue Chain = getRoot();
4391 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4392 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4393 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4394 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4396 DAG.setRoot(Res.getValue(1));
4399 case Intrinsic::write_register: {
4400 Value *Reg = I.getArgOperand(0);
4401 Value *RegValue = I.getArgOperand(1);
4402 SDValue Chain = getRoot();
4404 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4405 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4406 RegName, getValue(RegValue)));
4409 case Intrinsic::setjmp:
4410 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4411 case Intrinsic::longjmp:
4412 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4413 case Intrinsic::memcpy: {
4414 SDValue Op1 = getValue(I.getArgOperand(0));
4415 SDValue Op2 = getValue(I.getArgOperand(1));
4416 SDValue Op3 = getValue(I.getArgOperand(2));
4417 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4419 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4420 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4421 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4422 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4424 MachinePointerInfo(I.getArgOperand(0)),
4425 MachinePointerInfo(I.getArgOperand(1)));
4426 updateDAGForMaybeTailCall(MC);
4429 case Intrinsic::memset: {
4430 SDValue Op1 = getValue(I.getArgOperand(0));
4431 SDValue Op2 = getValue(I.getArgOperand(1));
4432 SDValue Op3 = getValue(I.getArgOperand(2));
4433 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4435 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4436 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4437 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4438 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4439 isTC, MachinePointerInfo(I.getArgOperand(0)));
4440 updateDAGForMaybeTailCall(MS);
4443 case Intrinsic::memmove: {
4444 SDValue Op1 = getValue(I.getArgOperand(0));
4445 SDValue Op2 = getValue(I.getArgOperand(1));
4446 SDValue Op3 = getValue(I.getArgOperand(2));
4447 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4449 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4450 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4451 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4452 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4453 isTC, MachinePointerInfo(I.getArgOperand(0)),
4454 MachinePointerInfo(I.getArgOperand(1)));
4455 updateDAGForMaybeTailCall(MM);
4458 case Intrinsic::dbg_declare: {
4459 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4460 DILocalVariable *Variable = DI.getVariable();
4461 DIExpression *Expression = DI.getExpression();
4462 const Value *Address = DI.getAddress();
4463 assert(Variable && "Missing variable");
4465 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4469 // Check if address has undef value.
4470 if (isa<UndefValue>(Address) ||
4471 (Address->use_empty() && !isa<Argument>(Address))) {
4472 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4476 SDValue &N = NodeMap[Address];
4477 if (!N.getNode() && isa<Argument>(Address))
4478 // Check unused arguments map.
4479 N = UnusedArgNodeMap[Address];
4482 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4483 Address = BCI->getOperand(0);
4484 // Parameters are handled specially.
4485 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4486 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4487 if (isParameter && FINode) {
4488 // Byval parameter. We have a frame index at this point.
4489 SDV = DAG.getFrameIndexDbgValue(Variable, Expression,
4490 FINode->getIndex(), 0, dl, SDNodeOrder);
4491 } else if (isa<Argument>(Address)) {
4492 // Address is an argument, so try to emit its dbg value using
4493 // virtual register info from the FuncInfo.ValueMap.
4494 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4498 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4499 true, 0, dl, SDNodeOrder);
4501 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4503 // If Address is an argument then try to emit its dbg value using
4504 // virtual register info from the FuncInfo.ValueMap.
4505 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4507 // If variable is pinned by a alloca in dominating bb then
4508 // use StaticAllocaMap.
4509 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4510 if (AI->getParent() != DI.getParent()) {
4511 DenseMap<const AllocaInst*, int>::iterator SI =
4512 FuncInfo.StaticAllocaMap.find(AI);
4513 if (SI != FuncInfo.StaticAllocaMap.end()) {
4514 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4515 0, dl, SDNodeOrder);
4516 DAG.AddDbgValue(SDV, nullptr, false);
4521 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4526 case Intrinsic::dbg_value: {
4527 const DbgValueInst &DI = cast<DbgValueInst>(I);
4528 assert(DI.getVariable() && "Missing variable");
4530 DILocalVariable *Variable = DI.getVariable();
4531 DIExpression *Expression = DI.getExpression();
4532 uint64_t Offset = DI.getOffset();
4533 const Value *V = DI.getValue();
4538 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4539 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4541 DAG.AddDbgValue(SDV, nullptr, false);
4543 // Do not use getValue() in here; we don't want to generate code at
4544 // this point if it hasn't been done yet.
4545 SDValue N = NodeMap[V];
4546 if (!N.getNode() && isa<Argument>(V))
4547 // Check unused arguments map.
4548 N = UnusedArgNodeMap[V];
4550 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4552 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4553 false, Offset, dl, SDNodeOrder);
4554 DAG.AddDbgValue(SDV, N.getNode(), false);
4556 } else if (!V->use_empty() ) {
4557 // Do not call getValue(V) yet, as we don't want to generate code.
4558 // Remember it for later.
4559 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4560 DanglingDebugInfoMap[V] = DDI;
4562 // We may expand this to cover more cases. One case where we have no
4563 // data available is an unreferenced parameter.
4564 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4568 // Build a debug info table entry.
4569 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4570 V = BCI->getOperand(0);
4571 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4572 // Don't handle byval struct arguments or VLAs, for example.
4574 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4575 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4578 DenseMap<const AllocaInst*, int>::iterator SI =
4579 FuncInfo.StaticAllocaMap.find(AI);
4580 if (SI == FuncInfo.StaticAllocaMap.end())
4581 return nullptr; // VLAs.
4585 case Intrinsic::eh_typeid_for: {
4586 // Find the type id for the given typeinfo.
4587 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4588 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4589 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4594 case Intrinsic::eh_return_i32:
4595 case Intrinsic::eh_return_i64:
4596 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4597 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4600 getValue(I.getArgOperand(0)),
4601 getValue(I.getArgOperand(1))));
4603 case Intrinsic::eh_unwind_init:
4604 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4606 case Intrinsic::eh_dwarf_cfa: {
4607 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4608 TLI.getPointerTy(DAG.getDataLayout()));
4609 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4610 CfaArg.getValueType(),
4611 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4612 CfaArg.getValueType()),
4614 SDValue FA = DAG.getNode(
4615 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4616 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4617 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4621 case Intrinsic::eh_sjlj_callsite: {
4622 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4623 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4624 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4625 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4627 MMI.setCurrentCallSite(CI->getZExtValue());
4630 case Intrinsic::eh_sjlj_functioncontext: {
4631 // Get and store the index of the function context.
4632 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4634 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4635 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4636 MFI->setFunctionContextIndex(FI);
4639 case Intrinsic::eh_sjlj_setjmp: {
4642 Ops[1] = getValue(I.getArgOperand(0));
4643 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4644 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4645 setValue(&I, Op.getValue(0));
4646 DAG.setRoot(Op.getValue(1));
4649 case Intrinsic::eh_sjlj_longjmp: {
4650 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4651 getRoot(), getValue(I.getArgOperand(0))));
4654 case Intrinsic::eh_sjlj_setup_dispatch: {
4655 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4660 case Intrinsic::masked_gather:
4661 visitMaskedGather(I);
4663 case Intrinsic::masked_load:
4666 case Intrinsic::masked_scatter:
4667 visitMaskedScatter(I);
4669 case Intrinsic::masked_store:
4670 visitMaskedStore(I);
4672 case Intrinsic::x86_mmx_pslli_w:
4673 case Intrinsic::x86_mmx_pslli_d:
4674 case Intrinsic::x86_mmx_pslli_q:
4675 case Intrinsic::x86_mmx_psrli_w:
4676 case Intrinsic::x86_mmx_psrli_d:
4677 case Intrinsic::x86_mmx_psrli_q:
4678 case Intrinsic::x86_mmx_psrai_w:
4679 case Intrinsic::x86_mmx_psrai_d: {
4680 SDValue ShAmt = getValue(I.getArgOperand(1));
4681 if (isa<ConstantSDNode>(ShAmt)) {
4682 visitTargetIntrinsic(I, Intrinsic);
4685 unsigned NewIntrinsic = 0;
4686 EVT ShAmtVT = MVT::v2i32;
4687 switch (Intrinsic) {
4688 case Intrinsic::x86_mmx_pslli_w:
4689 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4691 case Intrinsic::x86_mmx_pslli_d:
4692 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4694 case Intrinsic::x86_mmx_pslli_q:
4695 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4697 case Intrinsic::x86_mmx_psrli_w:
4698 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4700 case Intrinsic::x86_mmx_psrli_d:
4701 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4703 case Intrinsic::x86_mmx_psrli_q:
4704 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4706 case Intrinsic::x86_mmx_psrai_w:
4707 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4709 case Intrinsic::x86_mmx_psrai_d:
4710 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4712 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4715 // The vector shift intrinsics with scalars uses 32b shift amounts but
4716 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4718 // We must do this early because v2i32 is not a legal type.
4721 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4722 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4723 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4724 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4725 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4726 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4727 getValue(I.getArgOperand(0)), ShAmt);
4731 case Intrinsic::convertff:
4732 case Intrinsic::convertfsi:
4733 case Intrinsic::convertfui:
4734 case Intrinsic::convertsif:
4735 case Intrinsic::convertuif:
4736 case Intrinsic::convertss:
4737 case Intrinsic::convertsu:
4738 case Intrinsic::convertus:
4739 case Intrinsic::convertuu: {
4740 ISD::CvtCode Code = ISD::CVT_INVALID;
4741 switch (Intrinsic) {
4742 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4743 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4744 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4745 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4746 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4747 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4748 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4749 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4750 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4751 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4753 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4754 const Value *Op1 = I.getArgOperand(0);
4755 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4756 DAG.getValueType(DestVT),
4757 DAG.getValueType(getValue(Op1).getValueType()),
4758 getValue(I.getArgOperand(1)),
4759 getValue(I.getArgOperand(2)),
4764 case Intrinsic::powi:
4765 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4766 getValue(I.getArgOperand(1)), DAG));
4768 case Intrinsic::log:
4769 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4771 case Intrinsic::log2:
4772 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4774 case Intrinsic::log10:
4775 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4777 case Intrinsic::exp:
4778 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4780 case Intrinsic::exp2:
4781 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4783 case Intrinsic::pow:
4784 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4785 getValue(I.getArgOperand(1)), DAG, TLI));
4787 case Intrinsic::sqrt:
4788 case Intrinsic::fabs:
4789 case Intrinsic::sin:
4790 case Intrinsic::cos:
4791 case Intrinsic::floor:
4792 case Intrinsic::ceil:
4793 case Intrinsic::trunc:
4794 case Intrinsic::rint:
4795 case Intrinsic::nearbyint:
4796 case Intrinsic::round: {
4798 switch (Intrinsic) {
4799 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4800 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4801 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4802 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4803 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4804 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4805 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4806 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4807 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4808 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4809 case Intrinsic::round: Opcode = ISD::FROUND; break;
4812 setValue(&I, DAG.getNode(Opcode, sdl,
4813 getValue(I.getArgOperand(0)).getValueType(),
4814 getValue(I.getArgOperand(0))));
4817 case Intrinsic::minnum:
4818 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4819 getValue(I.getArgOperand(0)).getValueType(),
4820 getValue(I.getArgOperand(0)),
4821 getValue(I.getArgOperand(1))));
4823 case Intrinsic::maxnum:
4824 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4825 getValue(I.getArgOperand(0)).getValueType(),
4826 getValue(I.getArgOperand(0)),
4827 getValue(I.getArgOperand(1))));
4829 case Intrinsic::copysign:
4830 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4831 getValue(I.getArgOperand(0)).getValueType(),
4832 getValue(I.getArgOperand(0)),
4833 getValue(I.getArgOperand(1))));
4835 case Intrinsic::fma:
4836 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4837 getValue(I.getArgOperand(0)).getValueType(),
4838 getValue(I.getArgOperand(0)),
4839 getValue(I.getArgOperand(1)),
4840 getValue(I.getArgOperand(2))));
4842 case Intrinsic::fmuladd: {
4843 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4844 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4845 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4846 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4847 getValue(I.getArgOperand(0)).getValueType(),
4848 getValue(I.getArgOperand(0)),
4849 getValue(I.getArgOperand(1)),
4850 getValue(I.getArgOperand(2))));
4852 // TODO: Intrinsic calls should have fast-math-flags.
4853 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4854 getValue(I.getArgOperand(0)).getValueType(),
4855 getValue(I.getArgOperand(0)),
4856 getValue(I.getArgOperand(1)));
4857 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4858 getValue(I.getArgOperand(0)).getValueType(),
4860 getValue(I.getArgOperand(2)));
4865 case Intrinsic::convert_to_fp16:
4866 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4867 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4868 getValue(I.getArgOperand(0)),
4869 DAG.getTargetConstant(0, sdl,
4872 case Intrinsic::convert_from_fp16:
4873 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4874 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4875 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4876 getValue(I.getArgOperand(0)))));
4878 case Intrinsic::pcmarker: {
4879 SDValue Tmp = getValue(I.getArgOperand(0));
4880 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4883 case Intrinsic::readcyclecounter: {
4884 SDValue Op = getRoot();
4885 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4886 DAG.getVTList(MVT::i64, MVT::Other), Op);
4888 DAG.setRoot(Res.getValue(1));
4891 case Intrinsic::bitreverse:
4892 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
4893 getValue(I.getArgOperand(0)).getValueType(),
4894 getValue(I.getArgOperand(0))));
4896 case Intrinsic::bswap:
4897 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4898 getValue(I.getArgOperand(0)).getValueType(),
4899 getValue(I.getArgOperand(0))));
4901 case Intrinsic::cttz: {
4902 SDValue Arg = getValue(I.getArgOperand(0));
4903 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4904 EVT Ty = Arg.getValueType();
4905 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4909 case Intrinsic::ctlz: {
4910 SDValue Arg = getValue(I.getArgOperand(0));
4911 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4912 EVT Ty = Arg.getValueType();
4913 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4917 case Intrinsic::ctpop: {
4918 SDValue Arg = getValue(I.getArgOperand(0));
4919 EVT Ty = Arg.getValueType();
4920 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4923 case Intrinsic::stacksave: {
4924 SDValue Op = getRoot();
4926 ISD::STACKSAVE, sdl,
4927 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4929 DAG.setRoot(Res.getValue(1));
4932 case Intrinsic::stackrestore: {
4933 Res = getValue(I.getArgOperand(0));
4934 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4937 case Intrinsic::get_dynamic_area_offset: {
4938 SDValue Op = getRoot();
4939 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4940 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
4941 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
4944 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
4946 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
4952 case Intrinsic::stackprotector: {
4953 // Emit code into the DAG to store the stack guard onto the stack.
4954 MachineFunction &MF = DAG.getMachineFunction();
4955 MachineFrameInfo *MFI = MF.getFrameInfo();
4956 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4957 SDValue Src, Chain = getRoot();
4958 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4959 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4961 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4962 // global variable __stack_chk_guard.
4964 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4965 if (BC->getOpcode() == Instruction::BitCast)
4966 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4968 if (GV && TLI.useLoadStackGuardNode()) {
4969 // Emit a LOAD_STACK_GUARD node.
4970 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4972 MachinePointerInfo MPInfo(GV);
4973 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4974 unsigned Flags = MachineMemOperand::MOLoad |
4975 MachineMemOperand::MOInvariant;
4976 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4977 PtrTy.getSizeInBits() / 8,
4978 DAG.getEVTAlignment(PtrTy));
4979 Node->setMemRefs(MemRefs, MemRefs + 1);
4981 // Copy the guard value to a virtual register so that it can be
4982 // retrieved in the epilogue.
4983 Src = SDValue(Node, 0);
4984 const TargetRegisterClass *RC =
4985 TLI.getRegClassFor(Src.getSimpleValueType());
4986 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4988 SPDescriptor.setGuardReg(Reg);
4989 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4991 Src = getValue(I.getArgOperand(0)); // The guard's value.
4994 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4996 int FI = FuncInfo.StaticAllocaMap[Slot];
4997 MFI->setStackProtectorIndex(FI);
4999 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5001 // Store the stack protector onto the stack.
5002 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
5003 DAG.getMachineFunction(), FI),
5009 case Intrinsic::objectsize: {
5010 // If we don't know by now, we're never going to know.
5011 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5013 assert(CI && "Non-constant type in __builtin_object_size?");
5015 SDValue Arg = getValue(I.getCalledValue());
5016 EVT Ty = Arg.getValueType();
5019 Res = DAG.getConstant(-1ULL, sdl, Ty);
5021 Res = DAG.getConstant(0, sdl, Ty);
5026 case Intrinsic::annotation:
5027 case Intrinsic::ptr_annotation:
5028 // Drop the intrinsic, but forward the value
5029 setValue(&I, getValue(I.getOperand(0)));
5031 case Intrinsic::assume:
5032 case Intrinsic::var_annotation:
5033 // Discard annotate attributes and assumptions
5036 case Intrinsic::init_trampoline: {
5037 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5041 Ops[1] = getValue(I.getArgOperand(0));
5042 Ops[2] = getValue(I.getArgOperand(1));
5043 Ops[3] = getValue(I.getArgOperand(2));
5044 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5045 Ops[5] = DAG.getSrcValue(F);
5047 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5052 case Intrinsic::adjust_trampoline: {
5053 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5054 TLI.getPointerTy(DAG.getDataLayout()),
5055 getValue(I.getArgOperand(0))));
5058 case Intrinsic::gcroot:
5060 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5061 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5063 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5064 GFI->addStackRoot(FI->getIndex(), TypeMap);
5067 case Intrinsic::gcread:
5068 case Intrinsic::gcwrite:
5069 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5070 case Intrinsic::flt_rounds:
5071 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5074 case Intrinsic::expect: {
5075 // Just replace __builtin_expect(exp, c) with EXP.
5076 setValue(&I, getValue(I.getArgOperand(0)));
5080 case Intrinsic::debugtrap:
5081 case Intrinsic::trap: {
5082 StringRef TrapFuncName =
5084 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5085 .getValueAsString();
5086 if (TrapFuncName.empty()) {
5087 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5088 ISD::TRAP : ISD::DEBUGTRAP;
5089 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5092 TargetLowering::ArgListTy Args;
5094 TargetLowering::CallLoweringInfo CLI(DAG);
5095 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5096 CallingConv::C, I.getType(),
5097 DAG.getExternalSymbol(TrapFuncName.data(),
5098 TLI.getPointerTy(DAG.getDataLayout())),
5099 std::move(Args), 0);
5101 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5102 DAG.setRoot(Result.second);
5106 case Intrinsic::uadd_with_overflow:
5107 case Intrinsic::sadd_with_overflow:
5108 case Intrinsic::usub_with_overflow:
5109 case Intrinsic::ssub_with_overflow:
5110 case Intrinsic::umul_with_overflow:
5111 case Intrinsic::smul_with_overflow: {
5113 switch (Intrinsic) {
5114 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5115 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5116 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5117 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5118 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5119 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5120 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5122 SDValue Op1 = getValue(I.getArgOperand(0));
5123 SDValue Op2 = getValue(I.getArgOperand(1));
5125 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5126 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5129 case Intrinsic::prefetch: {
5131 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5133 Ops[1] = getValue(I.getArgOperand(0));
5134 Ops[2] = getValue(I.getArgOperand(1));
5135 Ops[3] = getValue(I.getArgOperand(2));
5136 Ops[4] = getValue(I.getArgOperand(3));
5137 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5138 DAG.getVTList(MVT::Other), Ops,
5139 EVT::getIntegerVT(*Context, 8),
5140 MachinePointerInfo(I.getArgOperand(0)),
5142 false, /* volatile */
5144 rw==1)); /* write */
5147 case Intrinsic::lifetime_start:
5148 case Intrinsic::lifetime_end: {
5149 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5150 // Stack coloring is not enabled in O0, discard region information.
5151 if (TM.getOptLevel() == CodeGenOpt::None)
5154 SmallVector<Value *, 4> Allocas;
5155 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5157 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5158 E = Allocas.end(); Object != E; ++Object) {
5159 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5161 // Could not find an Alloca.
5162 if (!LifetimeObject)
5165 // First check that the Alloca is static, otherwise it won't have a
5166 // valid frame index.
5167 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5168 if (SI == FuncInfo.StaticAllocaMap.end())
5171 int FI = SI->second;
5176 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5177 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5179 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5184 case Intrinsic::invariant_start:
5185 // Discard region information.
5186 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5188 case Intrinsic::invariant_end:
5189 // Discard region information.
5191 case Intrinsic::stackprotectorcheck: {
5192 // Do not actually emit anything for this basic block. Instead we initialize
5193 // the stack protector descriptor and export the guard variable so we can
5194 // access it in FinishBasicBlock.
5195 const BasicBlock *BB = I.getParent();
5196 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5197 ExportFromCurrentBlock(SPDescriptor.getGuard());
5199 // Flush our exports since we are going to process a terminator.
5200 (void)getControlRoot();
5203 case Intrinsic::clear_cache:
5204 return TLI.getClearCacheBuiltinName();
5205 case Intrinsic::donothing:
5208 case Intrinsic::experimental_stackmap: {
5212 case Intrinsic::experimental_patchpoint_void:
5213 case Intrinsic::experimental_patchpoint_i64: {
5214 visitPatchpoint(&I);
5217 case Intrinsic::experimental_gc_statepoint: {
5221 case Intrinsic::experimental_gc_result: {
5225 case Intrinsic::experimental_gc_relocate: {
5226 visitGCRelocate(cast<GCRelocateInst>(I));
5229 case Intrinsic::instrprof_increment:
5230 llvm_unreachable("instrprof failed to lower an increment");
5231 case Intrinsic::instrprof_value_profile:
5232 llvm_unreachable("instrprof failed to lower a value profiling call");
5233 case Intrinsic::localescape: {
5234 MachineFunction &MF = DAG.getMachineFunction();
5235 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5237 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5238 // is the same on all targets.
5239 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5240 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5241 if (isa<ConstantPointerNull>(Arg))
5242 continue; // Skip null pointers. They represent a hole in index space.
5243 AllocaInst *Slot = cast<AllocaInst>(Arg);
5244 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5245 "can only escape static allocas");
5246 int FI = FuncInfo.StaticAllocaMap[Slot];
5247 MCSymbol *FrameAllocSym =
5248 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5249 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5250 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5251 TII->get(TargetOpcode::LOCAL_ESCAPE))
5252 .addSym(FrameAllocSym)
5259 case Intrinsic::localrecover: {
5260 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5261 MachineFunction &MF = DAG.getMachineFunction();
5262 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5264 // Get the symbol that defines the frame offset.
5265 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5266 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5267 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5268 MCSymbol *FrameAllocSym =
5269 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5270 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5272 // Create a MCSymbol for the label to avoid any target lowering
5273 // that would make this PC relative.
5274 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5276 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5278 // Add the offset to the FP.
5279 Value *FP = I.getArgOperand(1);
5280 SDValue FPVal = getValue(FP);
5281 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5287 case Intrinsic::eh_exceptionpointer:
5288 case Intrinsic::eh_exceptioncode: {
5289 // Get the exception pointer vreg, copy from it, and resize it to fit.
5290 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5291 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5292 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5293 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5295 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5296 if (Intrinsic == Intrinsic::eh_exceptioncode)
5297 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5304 std::pair<SDValue, SDValue>
5305 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5306 const BasicBlock *EHPadBB) {
5307 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5308 MCSymbol *BeginLabel = nullptr;
5311 // Insert a label before the invoke call to mark the try range. This can be
5312 // used to detect deletion of the invoke via the MachineModuleInfo.
5313 BeginLabel = MMI.getContext().createTempSymbol();
5315 // For SjLj, keep track of which landing pads go with which invokes
5316 // so as to maintain the ordering of pads in the LSDA.
5317 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5318 if (CallSiteIndex) {
5319 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5320 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5322 // Now that the call site is handled, stop tracking it.
5323 MMI.setCurrentCallSite(0);
5326 // Both PendingLoads and PendingExports must be flushed here;
5327 // this call might not return.
5329 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5331 CLI.setChain(getRoot());
5333 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5334 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5336 assert((CLI.IsTailCall || Result.second.getNode()) &&
5337 "Non-null chain expected with non-tail call!");
5338 assert((Result.second.getNode() || !Result.first.getNode()) &&
5339 "Null value expected with tail call!");
5341 if (!Result.second.getNode()) {
5342 // As a special case, a null chain means that a tail call has been emitted
5343 // and the DAG root is already updated.
5346 // Since there's no actual continuation from this block, nothing can be
5347 // relying on us setting vregs for them.
5348 PendingExports.clear();
5350 DAG.setRoot(Result.second);
5354 // Insert a label at the end of the invoke call to mark the try range. This
5355 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5356 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5357 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5359 // Inform MachineModuleInfo of range.
5360 if (MMI.hasEHFunclets()) {
5362 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
5363 EHInfo->addIPToStateRange(cast<InvokeInst>(CLI.CS->getInstruction()),
5364 BeginLabel, EndLabel);
5366 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5373 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5375 const BasicBlock *EHPadBB) {
5376 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5377 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5378 Type *RetTy = FTy->getReturnType();
5380 TargetLowering::ArgListTy Args;
5381 TargetLowering::ArgListEntry Entry;
5382 Args.reserve(CS.arg_size());
5384 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5386 const Value *V = *i;
5389 if (V->getType()->isEmptyTy())
5392 SDValue ArgNode = getValue(V);
5393 Entry.Node = ArgNode; Entry.Ty = V->getType();
5395 // Skip the first return-type Attribute to get to params.
5396 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5397 Args.push_back(Entry);
5399 // If we have an explicit sret argument that is an Instruction, (i.e., it
5400 // might point to function-local memory), we can't meaningfully tail-call.
5401 if (Entry.isSRet && isa<Instruction>(V))
5405 // Check if target-independent constraints permit a tail call here.
5406 // Target-dependent constraints are checked within TLI->LowerCallTo.
5407 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5410 TargetLowering::CallLoweringInfo CLI(DAG);
5411 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5412 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5413 .setTailCall(isTailCall);
5414 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5416 if (Result.first.getNode())
5417 setValue(CS.getInstruction(), Result.first);
5420 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5421 /// value is equal or not-equal to zero.
5422 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5423 for (const User *U : V->users()) {
5424 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5425 if (IC->isEquality())
5426 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5427 if (C->isNullValue())
5429 // Unknown instruction.
5435 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5437 SelectionDAGBuilder &Builder) {
5439 // Check to see if this load can be trivially constant folded, e.g. if the
5440 // input is from a string literal.
5441 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5442 // Cast pointer to the type we really want to load.
5443 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5444 PointerType::getUnqual(LoadTy));
5446 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5447 const_cast<Constant *>(LoadInput), *Builder.DL))
5448 return Builder.getValue(LoadCst);
5451 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5452 // still constant memory, the input chain can be the entry node.
5454 bool ConstantMemory = false;
5456 // Do not serialize (non-volatile) loads of constant memory with anything.
5457 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5458 Root = Builder.DAG.getEntryNode();
5459 ConstantMemory = true;
5461 // Do not serialize non-volatile loads against each other.
5462 Root = Builder.DAG.getRoot();
5465 SDValue Ptr = Builder.getValue(PtrVal);
5466 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5467 Ptr, MachinePointerInfo(PtrVal),
5469 false /*nontemporal*/,
5470 false /*isinvariant*/, 1 /* align=1 */);
5472 if (!ConstantMemory)
5473 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5477 /// processIntegerCallValue - Record the value for an instruction that
5478 /// produces an integer result, converting the type where necessary.
5479 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5482 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5485 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5487 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5488 setValue(&I, Value);
5491 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5492 /// If so, return true and lower it, otherwise return false and it will be
5493 /// lowered like a normal call.
5494 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5495 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5496 if (I.getNumArgOperands() != 3)
5499 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5500 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5501 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5502 !I.getType()->isIntegerTy())
5505 const Value *Size = I.getArgOperand(2);
5506 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5507 if (CSize && CSize->getZExtValue() == 0) {
5508 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5510 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5514 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5515 std::pair<SDValue, SDValue> Res =
5516 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5517 getValue(LHS), getValue(RHS), getValue(Size),
5518 MachinePointerInfo(LHS),
5519 MachinePointerInfo(RHS));
5520 if (Res.first.getNode()) {
5521 processIntegerCallValue(I, Res.first, true);
5522 PendingLoads.push_back(Res.second);
5526 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5527 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5528 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5529 bool ActuallyDoIt = true;
5532 switch (CSize->getZExtValue()) {
5534 LoadVT = MVT::Other;
5536 ActuallyDoIt = false;
5540 LoadTy = Type::getInt16Ty(CSize->getContext());
5544 LoadTy = Type::getInt32Ty(CSize->getContext());
5548 LoadTy = Type::getInt64Ty(CSize->getContext());
5552 LoadVT = MVT::v4i32;
5553 LoadTy = Type::getInt32Ty(CSize->getContext());
5554 LoadTy = VectorType::get(LoadTy, 4);
5559 // This turns into unaligned loads. We only do this if the target natively
5560 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5561 // we'll only produce a small number of byte loads.
5563 // Require that we can find a legal MVT, and only do this if the target
5564 // supports unaligned loads of that type. Expanding into byte loads would
5566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5567 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5568 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5569 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5570 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5571 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5572 // TODO: Check alignment of src and dest ptrs.
5573 if (!TLI.isTypeLegal(LoadVT) ||
5574 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5575 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5576 ActuallyDoIt = false;
5580 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5581 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5583 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5585 processIntegerCallValue(I, Res, false);
5594 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5595 /// form. If so, return true and lower it, otherwise return false and it
5596 /// will be lowered like a normal call.
5597 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5598 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5599 if (I.getNumArgOperands() != 3)
5602 const Value *Src = I.getArgOperand(0);
5603 const Value *Char = I.getArgOperand(1);
5604 const Value *Length = I.getArgOperand(2);
5605 if (!Src->getType()->isPointerTy() ||
5606 !Char->getType()->isIntegerTy() ||
5607 !Length->getType()->isIntegerTy() ||
5608 !I.getType()->isPointerTy())
5611 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5612 std::pair<SDValue, SDValue> Res =
5613 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5614 getValue(Src), getValue(Char), getValue(Length),
5615 MachinePointerInfo(Src));
5616 if (Res.first.getNode()) {
5617 setValue(&I, Res.first);
5618 PendingLoads.push_back(Res.second);
5625 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5626 /// optimized form. If so, return true and lower it, otherwise return false
5627 /// and it will be lowered like a normal call.
5628 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5629 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5630 if (I.getNumArgOperands() != 2)
5633 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5634 if (!Arg0->getType()->isPointerTy() ||
5635 !Arg1->getType()->isPointerTy() ||
5636 !I.getType()->isPointerTy())
5639 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5640 std::pair<SDValue, SDValue> Res =
5641 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5642 getValue(Arg0), getValue(Arg1),
5643 MachinePointerInfo(Arg0),
5644 MachinePointerInfo(Arg1), isStpcpy);
5645 if (Res.first.getNode()) {
5646 setValue(&I, Res.first);
5647 DAG.setRoot(Res.second);
5654 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5655 /// If so, return true and lower it, otherwise return false and it will be
5656 /// lowered like a normal call.
5657 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5658 // Verify that the prototype makes sense. int strcmp(void*,void*)
5659 if (I.getNumArgOperands() != 2)
5662 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5663 if (!Arg0->getType()->isPointerTy() ||
5664 !Arg1->getType()->isPointerTy() ||
5665 !I.getType()->isIntegerTy())
5668 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5669 std::pair<SDValue, SDValue> Res =
5670 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5671 getValue(Arg0), getValue(Arg1),
5672 MachinePointerInfo(Arg0),
5673 MachinePointerInfo(Arg1));
5674 if (Res.first.getNode()) {
5675 processIntegerCallValue(I, Res.first, true);
5676 PendingLoads.push_back(Res.second);
5683 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5684 /// form. If so, return true and lower it, otherwise return false and it
5685 /// will be lowered like a normal call.
5686 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5687 // Verify that the prototype makes sense. size_t strlen(char *)
5688 if (I.getNumArgOperands() != 1)
5691 const Value *Arg0 = I.getArgOperand(0);
5692 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5695 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5696 std::pair<SDValue, SDValue> Res =
5697 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5698 getValue(Arg0), MachinePointerInfo(Arg0));
5699 if (Res.first.getNode()) {
5700 processIntegerCallValue(I, Res.first, false);
5701 PendingLoads.push_back(Res.second);
5708 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5709 /// form. If so, return true and lower it, otherwise return false and it
5710 /// will be lowered like a normal call.
5711 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5712 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5713 if (I.getNumArgOperands() != 2)
5716 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5717 if (!Arg0->getType()->isPointerTy() ||
5718 !Arg1->getType()->isIntegerTy() ||
5719 !I.getType()->isIntegerTy())
5722 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5723 std::pair<SDValue, SDValue> Res =
5724 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5725 getValue(Arg0), getValue(Arg1),
5726 MachinePointerInfo(Arg0));
5727 if (Res.first.getNode()) {
5728 processIntegerCallValue(I, Res.first, false);
5729 PendingLoads.push_back(Res.second);
5736 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5737 /// operation (as expected), translate it to an SDNode with the specified opcode
5738 /// and return true.
5739 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5741 // Sanity check that it really is a unary floating-point call.
5742 if (I.getNumArgOperands() != 1 ||
5743 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5744 I.getType() != I.getArgOperand(0)->getType() ||
5745 !I.onlyReadsMemory())
5748 SDValue Tmp = getValue(I.getArgOperand(0));
5749 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5753 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5754 /// operation (as expected), translate it to an SDNode with the specified opcode
5755 /// and return true.
5756 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5758 // Sanity check that it really is a binary floating-point call.
5759 if (I.getNumArgOperands() != 2 ||
5760 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5761 I.getType() != I.getArgOperand(0)->getType() ||
5762 I.getType() != I.getArgOperand(1)->getType() ||
5763 !I.onlyReadsMemory())
5766 SDValue Tmp0 = getValue(I.getArgOperand(0));
5767 SDValue Tmp1 = getValue(I.getArgOperand(1));
5768 EVT VT = Tmp0.getValueType();
5769 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5773 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5774 // Handle inline assembly differently.
5775 if (isa<InlineAsm>(I.getCalledValue())) {
5780 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5781 ComputeUsesVAFloatArgument(I, &MMI);
5783 const char *RenameFn = nullptr;
5784 if (Function *F = I.getCalledFunction()) {
5785 if (F->isDeclaration()) {
5786 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5787 if (unsigned IID = II->getIntrinsicID(F)) {
5788 RenameFn = visitIntrinsicCall(I, IID);
5793 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5794 RenameFn = visitIntrinsicCall(I, IID);
5800 // Check for well-known libc/libm calls. If the function is internal, it
5801 // can't be a library call.
5803 if (!F->hasLocalLinkage() && F->hasName() &&
5804 LibInfo->getLibFunc(F->getName(), Func) &&
5805 LibInfo->hasOptimizedCodeGen(Func)) {
5808 case LibFunc::copysign:
5809 case LibFunc::copysignf:
5810 case LibFunc::copysignl:
5811 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5812 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5813 I.getType() == I.getArgOperand(0)->getType() &&
5814 I.getType() == I.getArgOperand(1)->getType() &&
5815 I.onlyReadsMemory()) {
5816 SDValue LHS = getValue(I.getArgOperand(0));
5817 SDValue RHS = getValue(I.getArgOperand(1));
5818 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5819 LHS.getValueType(), LHS, RHS));
5824 case LibFunc::fabsf:
5825 case LibFunc::fabsl:
5826 if (visitUnaryFloatCall(I, ISD::FABS))
5830 case LibFunc::fminf:
5831 case LibFunc::fminl:
5832 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5836 case LibFunc::fmaxf:
5837 case LibFunc::fmaxl:
5838 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5844 if (visitUnaryFloatCall(I, ISD::FSIN))
5850 if (visitUnaryFloatCall(I, ISD::FCOS))
5854 case LibFunc::sqrtf:
5855 case LibFunc::sqrtl:
5856 case LibFunc::sqrt_finite:
5857 case LibFunc::sqrtf_finite:
5858 case LibFunc::sqrtl_finite:
5859 if (visitUnaryFloatCall(I, ISD::FSQRT))
5862 case LibFunc::floor:
5863 case LibFunc::floorf:
5864 case LibFunc::floorl:
5865 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5868 case LibFunc::nearbyint:
5869 case LibFunc::nearbyintf:
5870 case LibFunc::nearbyintl:
5871 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5875 case LibFunc::ceilf:
5876 case LibFunc::ceill:
5877 if (visitUnaryFloatCall(I, ISD::FCEIL))
5881 case LibFunc::rintf:
5882 case LibFunc::rintl:
5883 if (visitUnaryFloatCall(I, ISD::FRINT))
5886 case LibFunc::round:
5887 case LibFunc::roundf:
5888 case LibFunc::roundl:
5889 if (visitUnaryFloatCall(I, ISD::FROUND))
5892 case LibFunc::trunc:
5893 case LibFunc::truncf:
5894 case LibFunc::truncl:
5895 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5899 case LibFunc::log2f:
5900 case LibFunc::log2l:
5901 if (visitUnaryFloatCall(I, ISD::FLOG2))
5905 case LibFunc::exp2f:
5906 case LibFunc::exp2l:
5907 if (visitUnaryFloatCall(I, ISD::FEXP2))
5910 case LibFunc::memcmp:
5911 if (visitMemCmpCall(I))
5914 case LibFunc::memchr:
5915 if (visitMemChrCall(I))
5918 case LibFunc::strcpy:
5919 if (visitStrCpyCall(I, false))
5922 case LibFunc::stpcpy:
5923 if (visitStrCpyCall(I, true))
5926 case LibFunc::strcmp:
5927 if (visitStrCmpCall(I))
5930 case LibFunc::strlen:
5931 if (visitStrLenCall(I))
5934 case LibFunc::strnlen:
5935 if (visitStrNLenCall(I))
5944 Callee = getValue(I.getCalledValue());
5946 Callee = DAG.getExternalSymbol(
5948 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5950 // Check if we can potentially perform a tail call. More detailed checking is
5951 // be done within LowerCallTo, after more information about the call is known.
5952 LowerCallTo(&I, Callee, I.isTailCall());
5957 /// AsmOperandInfo - This contains information for each constraint that we are
5959 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5961 /// CallOperand - If this is the result output operand or a clobber
5962 /// this is null, otherwise it is the incoming operand to the CallInst.
5963 /// This gets modified as the asm is processed.
5964 SDValue CallOperand;
5966 /// AssignedRegs - If this is a register or register class operand, this
5967 /// contains the set of register corresponding to the operand.
5968 RegsForValue AssignedRegs;
5970 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5971 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5974 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5975 /// corresponds to. If there is no Value* for this operand, it returns
5977 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5978 const DataLayout &DL) const {
5979 if (!CallOperandVal) return MVT::Other;
5981 if (isa<BasicBlock>(CallOperandVal))
5982 return TLI.getPointerTy(DL);
5984 llvm::Type *OpTy = CallOperandVal->getType();
5986 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5987 // If this is an indirect operand, the operand is a pointer to the
5990 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5992 report_fatal_error("Indirect operand for inline asm not a pointer!");
5993 OpTy = PtrTy->getElementType();
5996 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5997 if (StructType *STy = dyn_cast<StructType>(OpTy))
5998 if (STy->getNumElements() == 1)
5999 OpTy = STy->getElementType(0);
6001 // If OpTy is not a single value, it may be a struct/union that we
6002 // can tile with integers.
6003 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6004 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
6013 OpTy = IntegerType::get(Context, BitSize);
6018 return TLI.getValueType(DL, OpTy, true);
6022 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6024 } // end anonymous namespace
6026 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6027 /// specified operand. We prefer to assign virtual registers, to allow the
6028 /// register allocator to handle the assignment process. However, if the asm
6029 /// uses features that we can't model on machineinstrs, we have SDISel do the
6030 /// allocation. This produces generally horrible, but correct, code.
6032 /// OpInfo describes the operand.
6034 static void GetRegistersForValue(SelectionDAG &DAG,
6035 const TargetLowering &TLI,
6037 SDISelAsmOperandInfo &OpInfo) {
6038 LLVMContext &Context = *DAG.getContext();
6040 MachineFunction &MF = DAG.getMachineFunction();
6041 SmallVector<unsigned, 4> Regs;
6043 // If this is a constraint for a single physreg, or a constraint for a
6044 // register class, find it.
6045 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6046 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6047 OpInfo.ConstraintCode,
6048 OpInfo.ConstraintVT);
6050 unsigned NumRegs = 1;
6051 if (OpInfo.ConstraintVT != MVT::Other) {
6052 // If this is a FP input in an integer register (or visa versa) insert a bit
6053 // cast of the input value. More generally, handle any case where the input
6054 // value disagrees with the register class we plan to stick this in.
6055 if (OpInfo.Type == InlineAsm::isInput &&
6056 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6057 // Try to convert to the first EVT that the reg class contains. If the
6058 // types are identical size, use a bitcast to convert (e.g. two differing
6060 MVT RegVT = *PhysReg.second->vt_begin();
6061 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6062 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6063 RegVT, OpInfo.CallOperand);
6064 OpInfo.ConstraintVT = RegVT;
6065 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6066 // If the input is a FP value and we want it in FP registers, do a
6067 // bitcast to the corresponding integer type. This turns an f64 value
6068 // into i64, which can be passed with two i32 values on a 32-bit
6070 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6071 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6072 RegVT, OpInfo.CallOperand);
6073 OpInfo.ConstraintVT = RegVT;
6077 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6081 EVT ValueVT = OpInfo.ConstraintVT;
6083 // If this is a constraint for a specific physical register, like {r17},
6085 if (unsigned AssignedReg = PhysReg.first) {
6086 const TargetRegisterClass *RC = PhysReg.second;
6087 if (OpInfo.ConstraintVT == MVT::Other)
6088 ValueVT = *RC->vt_begin();
6090 // Get the actual register value type. This is important, because the user
6091 // may have asked for (e.g.) the AX register in i32 type. We need to
6092 // remember that AX is actually i16 to get the right extension.
6093 RegVT = *RC->vt_begin();
6095 // This is a explicit reference to a physical register.
6096 Regs.push_back(AssignedReg);
6098 // If this is an expanded reference, add the rest of the regs to Regs.
6100 TargetRegisterClass::iterator I = RC->begin();
6101 for (; *I != AssignedReg; ++I)
6102 assert(I != RC->end() && "Didn't find reg!");
6104 // Already added the first reg.
6106 for (; NumRegs; --NumRegs, ++I) {
6107 assert(I != RC->end() && "Ran out of registers to allocate!");
6112 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6116 // Otherwise, if this was a reference to an LLVM register class, create vregs
6117 // for this reference.
6118 if (const TargetRegisterClass *RC = PhysReg.second) {
6119 RegVT = *RC->vt_begin();
6120 if (OpInfo.ConstraintVT == MVT::Other)
6123 // Create the appropriate number of virtual registers.
6124 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6125 for (; NumRegs; --NumRegs)
6126 Regs.push_back(RegInfo.createVirtualRegister(RC));
6128 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6132 // Otherwise, we couldn't allocate enough registers for this.
6135 /// visitInlineAsm - Handle a call to an InlineAsm object.
6137 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6138 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6140 /// ConstraintOperands - Information about all of the constraints.
6141 SDISelAsmOperandInfoVector ConstraintOperands;
6143 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6144 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6145 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6147 bool hasMemory = false;
6149 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6150 unsigned ResNo = 0; // ResNo - The result number of the next output.
6151 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6152 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6153 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6155 MVT OpVT = MVT::Other;
6157 // Compute the value type for each operand.
6158 switch (OpInfo.Type) {
6159 case InlineAsm::isOutput:
6160 // Indirect outputs just consume an argument.
6161 if (OpInfo.isIndirect) {
6162 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6166 // The return value of the call is this value. As such, there is no
6167 // corresponding argument.
6168 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6169 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6170 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6171 STy->getElementType(ResNo));
6173 assert(ResNo == 0 && "Asm only has one result!");
6174 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6178 case InlineAsm::isInput:
6179 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6181 case InlineAsm::isClobber:
6186 // If this is an input or an indirect output, process the call argument.
6187 // BasicBlocks are labels, currently appearing only in asm's.
6188 if (OpInfo.CallOperandVal) {
6189 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6190 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6192 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6195 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6196 DAG.getDataLayout()).getSimpleVT();
6199 OpInfo.ConstraintVT = OpVT;
6201 // Indirect operand accesses access memory.
6202 if (OpInfo.isIndirect)
6205 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6206 TargetLowering::ConstraintType
6207 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6208 if (CType == TargetLowering::C_Memory) {
6216 SDValue Chain, Flag;
6218 // We won't need to flush pending loads if this asm doesn't touch
6219 // memory and is nonvolatile.
6220 if (hasMemory || IA->hasSideEffects())
6223 Chain = DAG.getRoot();
6225 // Second pass over the constraints: compute which constraint option to use
6226 // and assign registers to constraints that want a specific physreg.
6227 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6228 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6230 // If this is an output operand with a matching input operand, look up the
6231 // matching input. If their types mismatch, e.g. one is an integer, the
6232 // other is floating point, or their sizes are different, flag it as an
6234 if (OpInfo.hasMatchingInput()) {
6235 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6237 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6238 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6239 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6240 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6241 OpInfo.ConstraintVT);
6242 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6243 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6244 Input.ConstraintVT);
6245 if ((OpInfo.ConstraintVT.isInteger() !=
6246 Input.ConstraintVT.isInteger()) ||
6247 (MatchRC.second != InputRC.second)) {
6248 report_fatal_error("Unsupported asm: input constraint"
6249 " with a matching output constraint of"
6250 " incompatible type!");
6252 Input.ConstraintVT = OpInfo.ConstraintVT;
6256 // Compute the constraint code and ConstraintType to use.
6257 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6259 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6260 OpInfo.Type == InlineAsm::isClobber)
6263 // If this is a memory input, and if the operand is not indirect, do what we
6264 // need to to provide an address for the memory input.
6265 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6266 !OpInfo.isIndirect) {
6267 assert((OpInfo.isMultipleAlternative ||
6268 (OpInfo.Type == InlineAsm::isInput)) &&
6269 "Can only indirectify direct input operands!");
6271 // Memory operands really want the address of the value. If we don't have
6272 // an indirect input, put it in the constpool if we can, otherwise spill
6273 // it to a stack slot.
6274 // TODO: This isn't quite right. We need to handle these according to
6275 // the addressing mode that the constraint wants. Also, this may take
6276 // an additional register for the computation and we don't want that
6279 // If the operand is a float, integer, or vector constant, spill to a
6280 // constant pool entry to get its address.
6281 const Value *OpVal = OpInfo.CallOperandVal;
6282 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6283 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6284 OpInfo.CallOperand = DAG.getConstantPool(
6285 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6287 // Otherwise, create a stack slot and emit a store to it before the
6289 Type *Ty = OpVal->getType();
6290 auto &DL = DAG.getDataLayout();
6291 uint64_t TySize = DL.getTypeAllocSize(Ty);
6292 unsigned Align = DL.getPrefTypeAlignment(Ty);
6293 MachineFunction &MF = DAG.getMachineFunction();
6294 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6296 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6297 Chain = DAG.getStore(
6298 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6299 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6301 OpInfo.CallOperand = StackSlot;
6304 // There is no longer a Value* corresponding to this operand.
6305 OpInfo.CallOperandVal = nullptr;
6307 // It is now an indirect operand.
6308 OpInfo.isIndirect = true;
6311 // If this constraint is for a specific register, allocate it before
6313 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6314 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6317 // Second pass - Loop over all of the operands, assigning virtual or physregs
6318 // to register class operands.
6319 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6320 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6322 // C_Register operands have already been allocated, Other/Memory don't need
6324 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6325 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6328 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6329 std::vector<SDValue> AsmNodeOperands;
6330 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6331 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6332 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6334 // If we have a !srcloc metadata node associated with it, we want to attach
6335 // this to the ultimately generated inline asm machineinstr. To do this, we
6336 // pass in the third operand as this (potentially null) inline asm MDNode.
6337 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6338 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6340 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6341 // bits as operand 3.
6342 unsigned ExtraInfo = 0;
6343 if (IA->hasSideEffects())
6344 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6345 if (IA->isAlignStack())
6346 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6347 // Set the asm dialect.
6348 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6350 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6351 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6352 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6354 // Compute the constraint code and ConstraintType to use.
6355 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6357 // Ideally, we would only check against memory constraints. However, the
6358 // meaning of an other constraint can be target-specific and we can't easily
6359 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6360 // for other constriants as well.
6361 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6362 OpInfo.ConstraintType == TargetLowering::C_Other) {
6363 if (OpInfo.Type == InlineAsm::isInput)
6364 ExtraInfo |= InlineAsm::Extra_MayLoad;
6365 else if (OpInfo.Type == InlineAsm::isOutput)
6366 ExtraInfo |= InlineAsm::Extra_MayStore;
6367 else if (OpInfo.Type == InlineAsm::isClobber)
6368 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6372 AsmNodeOperands.push_back(DAG.getTargetConstant(
6373 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6375 // Loop over all of the inputs, copying the operand values into the
6376 // appropriate registers and processing the output regs.
6377 RegsForValue RetValRegs;
6379 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6380 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6382 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6383 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6385 switch (OpInfo.Type) {
6386 case InlineAsm::isOutput: {
6387 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6388 OpInfo.ConstraintType != TargetLowering::C_Register) {
6389 // Memory output, or 'other' output (e.g. 'X' constraint).
6390 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6392 unsigned ConstraintID =
6393 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6394 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6395 "Failed to convert memory constraint code to constraint id.");
6397 // Add information to the INLINEASM node to know about this output.
6398 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6399 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6400 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6402 AsmNodeOperands.push_back(OpInfo.CallOperand);
6406 // Otherwise, this is a register or register class output.
6408 // Copy the output from the appropriate register. Find a register that
6410 if (OpInfo.AssignedRegs.Regs.empty()) {
6411 LLVMContext &Ctx = *DAG.getContext();
6412 Ctx.emitError(CS.getInstruction(),
6413 "couldn't allocate output register for constraint '" +
6414 Twine(OpInfo.ConstraintCode) + "'");
6418 // If this is an indirect operand, store through the pointer after the
6420 if (OpInfo.isIndirect) {
6421 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6422 OpInfo.CallOperandVal));
6424 // This is the result value of the call.
6425 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6426 // Concatenate this output onto the outputs list.
6427 RetValRegs.append(OpInfo.AssignedRegs);
6430 // Add information to the INLINEASM node to know that this register is
6433 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6434 ? InlineAsm::Kind_RegDefEarlyClobber
6435 : InlineAsm::Kind_RegDef,
6436 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6439 case InlineAsm::isInput: {
6440 SDValue InOperandVal = OpInfo.CallOperand;
6442 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6443 // If this is required to match an output register we have already set,
6444 // just use its register.
6445 unsigned OperandNo = OpInfo.getMatchedOperand();
6447 // Scan until we find the definition we already emitted of this operand.
6448 // When we find it, create a RegsForValue operand.
6449 unsigned CurOp = InlineAsm::Op_FirstOperand;
6450 for (; OperandNo; --OperandNo) {
6451 // Advance to the next operand.
6453 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6454 assert((InlineAsm::isRegDefKind(OpFlag) ||
6455 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6456 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6457 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6461 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6462 if (InlineAsm::isRegDefKind(OpFlag) ||
6463 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6464 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6465 if (OpInfo.isIndirect) {
6466 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6467 LLVMContext &Ctx = *DAG.getContext();
6468 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6469 " don't know how to handle tied "
6470 "indirect register inputs");
6474 RegsForValue MatchedRegs;
6475 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6476 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6477 MatchedRegs.RegVTs.push_back(RegVT);
6478 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6479 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6481 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6482 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6484 LLVMContext &Ctx = *DAG.getContext();
6485 Ctx.emitError(CS.getInstruction(),
6486 "inline asm error: This value"
6487 " type register class is not natively supported!");
6491 SDLoc dl = getCurSDLoc();
6492 // Use the produced MatchedRegs object to
6493 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6494 Chain, &Flag, CS.getInstruction());
6495 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6496 true, OpInfo.getMatchedOperand(), dl,
6497 DAG, AsmNodeOperands);
6501 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6502 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6503 "Unexpected number of operands");
6504 // Add information to the INLINEASM node to know about this input.
6505 // See InlineAsm.h isUseOperandTiedToDef.
6506 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6507 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6508 OpInfo.getMatchedOperand());
6509 AsmNodeOperands.push_back(DAG.getTargetConstant(
6510 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6511 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6515 // Treat indirect 'X' constraint as memory.
6516 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6518 OpInfo.ConstraintType = TargetLowering::C_Memory;
6520 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6521 std::vector<SDValue> Ops;
6522 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6525 LLVMContext &Ctx = *DAG.getContext();
6526 Ctx.emitError(CS.getInstruction(),
6527 "invalid operand for inline asm constraint '" +
6528 Twine(OpInfo.ConstraintCode) + "'");
6532 // Add information to the INLINEASM node to know about this input.
6533 unsigned ResOpType =
6534 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6535 AsmNodeOperands.push_back(DAG.getTargetConstant(
6536 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6537 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6541 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6542 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6543 assert(InOperandVal.getValueType() ==
6544 TLI.getPointerTy(DAG.getDataLayout()) &&
6545 "Memory operands expect pointer values");
6547 unsigned ConstraintID =
6548 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6549 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6550 "Failed to convert memory constraint code to constraint id.");
6552 // Add information to the INLINEASM node to know about this input.
6553 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6554 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6555 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6558 AsmNodeOperands.push_back(InOperandVal);
6562 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6563 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6564 "Unknown constraint type!");
6566 // TODO: Support this.
6567 if (OpInfo.isIndirect) {
6568 LLVMContext &Ctx = *DAG.getContext();
6569 Ctx.emitError(CS.getInstruction(),
6570 "Don't know how to handle indirect register inputs yet "
6571 "for constraint '" +
6572 Twine(OpInfo.ConstraintCode) + "'");
6576 // Copy the input into the appropriate registers.
6577 if (OpInfo.AssignedRegs.Regs.empty()) {
6578 LLVMContext &Ctx = *DAG.getContext();
6579 Ctx.emitError(CS.getInstruction(),
6580 "couldn't allocate input reg for constraint '" +
6581 Twine(OpInfo.ConstraintCode) + "'");
6585 SDLoc dl = getCurSDLoc();
6587 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6588 Chain, &Flag, CS.getInstruction());
6590 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6591 dl, DAG, AsmNodeOperands);
6594 case InlineAsm::isClobber: {
6595 // Add the clobbered value to the operand list, so that the register
6596 // allocator is aware that the physreg got clobbered.
6597 if (!OpInfo.AssignedRegs.Regs.empty())
6598 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6599 false, 0, getCurSDLoc(), DAG,
6606 // Finish up input operands. Set the input chain and add the flag last.
6607 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6608 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6610 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6611 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6612 Flag = Chain.getValue(1);
6614 // If this asm returns a register value, copy the result from that register
6615 // and set it as the value of the call.
6616 if (!RetValRegs.Regs.empty()) {
6617 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6618 Chain, &Flag, CS.getInstruction());
6620 // FIXME: Why don't we do this for inline asms with MRVs?
6621 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6622 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6624 // If any of the results of the inline asm is a vector, it may have the
6625 // wrong width/num elts. This can happen for register classes that can
6626 // contain multiple different value types. The preg or vreg allocated may
6627 // not have the same VT as was expected. Convert it to the right type
6628 // with bit_convert.
6629 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6630 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6633 } else if (ResultType != Val.getValueType() &&
6634 ResultType.isInteger() && Val.getValueType().isInteger()) {
6635 // If a result value was tied to an input value, the computed result may
6636 // have a wider width than the expected result. Extract the relevant
6638 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6641 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6644 setValue(CS.getInstruction(), Val);
6645 // Don't need to use this as a chain in this case.
6646 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6650 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6652 // Process indirect outputs, first output all of the flagged copies out of
6654 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6655 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6656 const Value *Ptr = IndirectStoresToEmit[i].second;
6657 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6659 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6662 // Emit the non-flagged stores from the physregs.
6663 SmallVector<SDValue, 8> OutChains;
6664 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6665 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6666 StoresToEmit[i].first,
6667 getValue(StoresToEmit[i].second),
6668 MachinePointerInfo(StoresToEmit[i].second),
6670 OutChains.push_back(Val);
6673 if (!OutChains.empty())
6674 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6679 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6680 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6681 MVT::Other, getRoot(),
6682 getValue(I.getArgOperand(0)),
6683 DAG.getSrcValue(I.getArgOperand(0))));
6686 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6687 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6688 const DataLayout &DL = DAG.getDataLayout();
6689 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6690 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6691 DAG.getSrcValue(I.getOperand(0)),
6692 DL.getABITypeAlignment(I.getType()));
6694 DAG.setRoot(V.getValue(1));
6697 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6698 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6699 MVT::Other, getRoot(),
6700 getValue(I.getArgOperand(0)),
6701 DAG.getSrcValue(I.getArgOperand(0))));
6704 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6705 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6706 MVT::Other, getRoot(),
6707 getValue(I.getArgOperand(0)),
6708 getValue(I.getArgOperand(1)),
6709 DAG.getSrcValue(I.getArgOperand(0)),
6710 DAG.getSrcValue(I.getArgOperand(1))));
6713 /// \brief Lower an argument list according to the target calling convention.
6715 /// \return A tuple of <return-value, token-chain>
6717 /// This is a helper for lowering intrinsics that follow a target calling
6718 /// convention or require stack pointer adjustment. Only a subset of the
6719 /// intrinsic's operands need to participate in the calling convention.
6720 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6721 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6722 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6723 TargetLowering::ArgListTy Args;
6724 Args.reserve(NumArgs);
6726 // Populate the argument list.
6727 // Attributes for args start at offset 1, after the return attribute.
6728 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6729 ArgI != ArgE; ++ArgI) {
6730 const Value *V = CS->getOperand(ArgI);
6732 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6734 TargetLowering::ArgListEntry Entry;
6735 Entry.Node = getValue(V);
6736 Entry.Ty = V->getType();
6737 Entry.setAttributes(&CS, AttrI);
6738 Args.push_back(Entry);
6741 TargetLowering::CallLoweringInfo CLI(DAG);
6742 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6743 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6744 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6746 return lowerInvokable(CLI, EHPadBB);
6749 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6750 /// or patchpoint target node's operand list.
6752 /// Constants are converted to TargetConstants purely as an optimization to
6753 /// avoid constant materialization and register allocation.
6755 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6756 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6757 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6758 /// address materialization and register allocation, but may also be required
6759 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6760 /// alloca in the entry block, then the runtime may assume that the alloca's
6761 /// StackMap location can be read immediately after compilation and that the
6762 /// location is valid at any point during execution (this is similar to the
6763 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6764 /// only available in a register, then the runtime would need to trap when
6765 /// execution reaches the StackMap in order to read the alloca's location.
6766 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6767 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6768 SelectionDAGBuilder &Builder) {
6769 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6770 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6771 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6773 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6775 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6776 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6777 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6778 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6779 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6781 Ops.push_back(OpVal);
6785 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6786 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6787 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6788 // [live variables...])
6790 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6792 SDValue Chain, InFlag, Callee, NullPtr;
6793 SmallVector<SDValue, 32> Ops;
6795 SDLoc DL = getCurSDLoc();
6796 Callee = getValue(CI.getCalledValue());
6797 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6799 // The stackmap intrinsic only records the live variables (the arguemnts
6800 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6801 // intrinsic, this won't be lowered to a function call. This means we don't
6802 // have to worry about calling conventions and target specific lowering code.
6803 // Instead we perform the call lowering right here.
6805 // chain, flag = CALLSEQ_START(chain, 0)
6806 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6807 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6809 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6810 InFlag = Chain.getValue(1);
6812 // Add the <id> and <numBytes> constants.
6813 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6814 Ops.push_back(DAG.getTargetConstant(
6815 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6816 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6817 Ops.push_back(DAG.getTargetConstant(
6818 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6821 // Push live variables for the stack map.
6822 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6824 // We are not pushing any register mask info here on the operands list,
6825 // because the stackmap doesn't clobber anything.
6827 // Push the chain and the glue flag.
6828 Ops.push_back(Chain);
6829 Ops.push_back(InFlag);
6831 // Create the STACKMAP node.
6832 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6833 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6834 Chain = SDValue(SM, 0);
6835 InFlag = Chain.getValue(1);
6837 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6839 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6841 // Set the root to the target-lowered call chain.
6844 // Inform the Frame Information that we have a stackmap in this function.
6845 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6848 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6849 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6850 const BasicBlock *EHPadBB) {
6851 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6856 // [live variables...])
6858 CallingConv::ID CC = CS.getCallingConv();
6859 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6860 bool HasDef = !CS->getType()->isVoidTy();
6861 SDLoc dl = getCurSDLoc();
6862 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6864 // Handle immediate and symbolic callees.
6865 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6866 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6868 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6869 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6870 SDLoc(SymbolicCallee),
6871 SymbolicCallee->getValueType(0));
6873 // Get the real number of arguments participating in the call <numArgs>
6874 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6875 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6877 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6878 // Intrinsics include all meta-operands up to but not including CC.
6879 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6880 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6881 "Not enough arguments provided to the patchpoint intrinsic");
6883 // For AnyRegCC the arguments are lowered later on manually.
6884 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6886 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6887 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6888 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6890 SDNode *CallEnd = Result.second.getNode();
6891 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6892 CallEnd = CallEnd->getOperand(0).getNode();
6894 /// Get a call instruction from the call sequence chain.
6895 /// Tail calls are not allowed.
6896 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6897 "Expected a callseq node.");
6898 SDNode *Call = CallEnd->getOperand(0).getNode();
6899 bool HasGlue = Call->getGluedNode();
6901 // Replace the target specific call node with the patchable intrinsic.
6902 SmallVector<SDValue, 8> Ops;
6904 // Add the <id> and <numBytes> constants.
6905 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6906 Ops.push_back(DAG.getTargetConstant(
6907 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6908 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6909 Ops.push_back(DAG.getTargetConstant(
6910 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6914 Ops.push_back(Callee);
6916 // Adjust <numArgs> to account for any arguments that have been passed on the
6918 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6919 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6920 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6921 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6923 // Add the calling convention
6924 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6926 // Add the arguments we omitted previously. The register allocator should
6927 // place these in any free register.
6929 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6930 Ops.push_back(getValue(CS.getArgument(i)));
6932 // Push the arguments from the call instruction up to the register mask.
6933 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6934 Ops.append(Call->op_begin() + 2, e);
6936 // Push live variables for the stack map.
6937 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6939 // Push the register mask info.
6941 Ops.push_back(*(Call->op_end()-2));
6943 Ops.push_back(*(Call->op_end()-1));
6945 // Push the chain (this is originally the first operand of the call, but
6946 // becomes now the last or second to last operand).
6947 Ops.push_back(*(Call->op_begin()));
6949 // Push the glue flag (last operand).
6951 Ops.push_back(*(Call->op_end()-1));
6954 if (IsAnyRegCC && HasDef) {
6955 // Create the return types based on the intrinsic definition
6956 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6957 SmallVector<EVT, 3> ValueVTs;
6958 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6959 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6961 // There is always a chain and a glue type at the end
6962 ValueVTs.push_back(MVT::Other);
6963 ValueVTs.push_back(MVT::Glue);
6964 NodeTys = DAG.getVTList(ValueVTs);
6966 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6968 // Replace the target specific call node with a PATCHPOINT node.
6969 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6972 // Update the NodeMap.
6975 setValue(CS.getInstruction(), SDValue(MN, 0));
6977 setValue(CS.getInstruction(), Result.first);
6980 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6981 // call sequence. Furthermore the location of the chain and glue can change
6982 // when the AnyReg calling convention is used and the intrinsic returns a
6984 if (IsAnyRegCC && HasDef) {
6985 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6986 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6987 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6989 DAG.ReplaceAllUsesWith(Call, MN);
6990 DAG.DeleteNode(Call);
6992 // Inform the Frame Information that we have a patchpoint in this function.
6993 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6996 /// Returns an AttributeSet representing the attributes applied to the return
6997 /// value of the given call.
6998 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6999 SmallVector<Attribute::AttrKind, 2> Attrs;
7001 Attrs.push_back(Attribute::SExt);
7003 Attrs.push_back(Attribute::ZExt);
7005 Attrs.push_back(Attribute::InReg);
7007 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7011 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7012 /// implementation, which just calls LowerCall.
7013 /// FIXME: When all targets are
7014 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7015 std::pair<SDValue, SDValue>
7016 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7017 // Handle the incoming return values from the call.
7019 Type *OrigRetTy = CLI.RetTy;
7020 SmallVector<EVT, 4> RetTys;
7021 SmallVector<uint64_t, 4> Offsets;
7022 auto &DL = CLI.DAG.getDataLayout();
7023 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7025 SmallVector<ISD::OutputArg, 4> Outs;
7026 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7028 bool CanLowerReturn =
7029 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7030 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7032 SDValue DemoteStackSlot;
7033 int DemoteStackIdx = -100;
7034 if (!CanLowerReturn) {
7035 // FIXME: equivalent assert?
7036 // assert(!CS.hasInAllocaArgument() &&
7037 // "sret demotion is incompatible with inalloca");
7038 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7039 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7040 MachineFunction &MF = CLI.DAG.getMachineFunction();
7041 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7042 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7044 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7046 Entry.Node = DemoteStackSlot;
7047 Entry.Ty = StackSlotPtrType;
7048 Entry.isSExt = false;
7049 Entry.isZExt = false;
7050 Entry.isInReg = false;
7051 Entry.isSRet = true;
7052 Entry.isNest = false;
7053 Entry.isByVal = false;
7054 Entry.isReturned = false;
7055 Entry.Alignment = Align;
7056 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7057 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7059 // sret demotion isn't compatible with tail-calls, since the sret argument
7060 // points into the callers stack frame.
7061 CLI.IsTailCall = false;
7063 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7065 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7066 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7067 for (unsigned i = 0; i != NumRegs; ++i) {
7068 ISD::InputArg MyFlags;
7069 MyFlags.VT = RegisterVT;
7071 MyFlags.Used = CLI.IsReturnValueUsed;
7073 MyFlags.Flags.setSExt();
7075 MyFlags.Flags.setZExt();
7077 MyFlags.Flags.setInReg();
7078 CLI.Ins.push_back(MyFlags);
7083 // Handle all of the outgoing arguments.
7085 CLI.OutVals.clear();
7086 ArgListTy &Args = CLI.getArgs();
7087 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7088 SmallVector<EVT, 4> ValueVTs;
7089 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7090 Type *FinalType = Args[i].Ty;
7091 if (Args[i].isByVal)
7092 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7093 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7094 FinalType, CLI.CallConv, CLI.IsVarArg);
7095 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7097 EVT VT = ValueVTs[Value];
7098 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7099 SDValue Op = SDValue(Args[i].Node.getNode(),
7100 Args[i].Node.getResNo() + Value);
7101 ISD::ArgFlagsTy Flags;
7102 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7108 if (Args[i].isInReg)
7112 if (Args[i].isByVal)
7114 if (Args[i].isInAlloca) {
7115 Flags.setInAlloca();
7116 // Set the byval flag for CCAssignFn callbacks that don't know about
7117 // inalloca. This way we can know how many bytes we should've allocated
7118 // and how many bytes a callee cleanup function will pop. If we port
7119 // inalloca to more targets, we'll have to add custom inalloca handling
7120 // in the various CC lowering callbacks.
7123 if (Args[i].isByVal || Args[i].isInAlloca) {
7124 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7125 Type *ElementTy = Ty->getElementType();
7126 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7127 // For ByVal, alignment should come from FE. BE will guess if this
7128 // info is not there but there are cases it cannot get right.
7129 unsigned FrameAlign;
7130 if (Args[i].Alignment)
7131 FrameAlign = Args[i].Alignment;
7133 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7134 Flags.setByValAlign(FrameAlign);
7139 Flags.setInConsecutiveRegs();
7140 Flags.setOrigAlign(OriginalAlignment);
7142 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7143 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7144 SmallVector<SDValue, 4> Parts(NumParts);
7145 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7148 ExtendKind = ISD::SIGN_EXTEND;
7149 else if (Args[i].isZExt)
7150 ExtendKind = ISD::ZERO_EXTEND;
7152 // Conservatively only handle 'returned' on non-vectors for now
7153 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7154 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7155 "unexpected use of 'returned'");
7156 // Before passing 'returned' to the target lowering code, ensure that
7157 // either the register MVT and the actual EVT are the same size or that
7158 // the return value and argument are extended in the same way; in these
7159 // cases it's safe to pass the argument register value unchanged as the
7160 // return register value (although it's at the target's option whether
7162 // TODO: allow code generation to take advantage of partially preserved
7163 // registers rather than clobbering the entire register when the
7164 // parameter extension method is not compatible with the return
7166 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7167 (ExtendKind != ISD::ANY_EXTEND &&
7168 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7169 Flags.setReturned();
7172 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7173 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7175 for (unsigned j = 0; j != NumParts; ++j) {
7176 // if it isn't first piece, alignment must be 1
7177 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7178 i < CLI.NumFixedArgs,
7179 i, j*Parts[j].getValueType().getStoreSize());
7180 if (NumParts > 1 && j == 0)
7181 MyFlags.Flags.setSplit();
7183 MyFlags.Flags.setOrigAlign(1);
7184 if (j == NumParts - 1)
7185 MyFlags.Flags.setSplitEnd();
7188 CLI.Outs.push_back(MyFlags);
7189 CLI.OutVals.push_back(Parts[j]);
7192 if (NeedsRegBlock && Value == NumValues - 1)
7193 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7197 SmallVector<SDValue, 4> InVals;
7198 CLI.Chain = LowerCall(CLI, InVals);
7200 // Verify that the target's LowerCall behaved as expected.
7201 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7202 "LowerCall didn't return a valid chain!");
7203 assert((!CLI.IsTailCall || InVals.empty()) &&
7204 "LowerCall emitted a return value for a tail call!");
7205 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7206 "LowerCall didn't emit the correct number of values!");
7208 // For a tail call, the return value is merely live-out and there aren't
7209 // any nodes in the DAG representing it. Return a special value to
7210 // indicate that a tail call has been emitted and no more Instructions
7211 // should be processed in the current block.
7212 if (CLI.IsTailCall) {
7213 CLI.DAG.setRoot(CLI.Chain);
7214 return std::make_pair(SDValue(), SDValue());
7217 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7218 assert(InVals[i].getNode() &&
7219 "LowerCall emitted a null value!");
7220 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7221 "LowerCall emitted a value with the wrong type!");
7224 SmallVector<SDValue, 4> ReturnValues;
7225 if (!CanLowerReturn) {
7226 // The instruction result is the result of loading from the
7227 // hidden sret parameter.
7228 SmallVector<EVT, 1> PVTs;
7229 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7231 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7232 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7233 EVT PtrVT = PVTs[0];
7235 unsigned NumValues = RetTys.size();
7236 ReturnValues.resize(NumValues);
7237 SmallVector<SDValue, 4> Chains(NumValues);
7239 // An aggregate return value cannot wrap around the address space, so
7240 // offsets to its parts don't wrap either.
7242 Flags.setNoUnsignedWrap(true);
7244 for (unsigned i = 0; i < NumValues; ++i) {
7245 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7246 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7248 SDValue L = CLI.DAG.getLoad(
7249 RetTys[i], CLI.DL, CLI.Chain, Add,
7250 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7251 DemoteStackIdx, Offsets[i]),
7252 false, false, false, 1);
7253 ReturnValues[i] = L;
7254 Chains[i] = L.getValue(1);
7257 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7259 // Collect the legal value parts into potentially illegal values
7260 // that correspond to the original function's return values.
7261 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7263 AssertOp = ISD::AssertSext;
7264 else if (CLI.RetZExt)
7265 AssertOp = ISD::AssertZext;
7266 unsigned CurReg = 0;
7267 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7269 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7270 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7272 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7273 NumRegs, RegisterVT, VT, nullptr,
7278 // For a function returning void, there is no return value. We can't create
7279 // such a node, so we just return a null return value in that case. In
7280 // that case, nothing will actually look at the value.
7281 if (ReturnValues.empty())
7282 return std::make_pair(SDValue(), CLI.Chain);
7285 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7286 CLI.DAG.getVTList(RetTys), ReturnValues);
7287 return std::make_pair(Res, CLI.Chain);
7290 void TargetLowering::LowerOperationWrapper(SDNode *N,
7291 SmallVectorImpl<SDValue> &Results,
7292 SelectionDAG &DAG) const {
7293 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7295 Results.push_back(Res);
7298 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7299 llvm_unreachable("LowerOperation not implemented for this target!");
7303 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7304 SDValue Op = getNonRegisterValue(V);
7305 assert((Op.getOpcode() != ISD::CopyFromReg ||
7306 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7307 "Copy from a reg to the same reg!");
7308 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7311 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7313 SDValue Chain = DAG.getEntryNode();
7315 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7316 FuncInfo.PreferredExtendType.end())
7318 : FuncInfo.PreferredExtendType[V];
7319 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7320 PendingExports.push_back(Chain);
7323 #include "llvm/CodeGen/SelectionDAGISel.h"
7325 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7326 /// entry block, return true. This includes arguments used by switches, since
7327 /// the switch may expand into multiple basic blocks.
7328 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7329 // With FastISel active, we may be splitting blocks, so force creation
7330 // of virtual registers for all non-dead arguments.
7332 return A->use_empty();
7334 const BasicBlock &Entry = A->getParent()->front();
7335 for (const User *U : A->users())
7336 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7337 return false; // Use not in entry block.
7342 void SelectionDAGISel::LowerArguments(const Function &F) {
7343 SelectionDAG &DAG = SDB->DAG;
7344 SDLoc dl = SDB->getCurSDLoc();
7345 const DataLayout &DL = DAG.getDataLayout();
7346 SmallVector<ISD::InputArg, 16> Ins;
7348 if (!FuncInfo->CanLowerReturn) {
7349 // Put in an sret pointer parameter before all the other parameters.
7350 SmallVector<EVT, 1> ValueVTs;
7351 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7352 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7354 // NOTE: Assuming that a pointer will never break down to more than one VT
7356 ISD::ArgFlagsTy Flags;
7358 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7359 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7360 ISD::InputArg::NoArgIndex, 0);
7361 Ins.push_back(RetArg);
7364 // Set up the incoming argument description vector.
7366 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7367 I != E; ++I, ++Idx) {
7368 SmallVector<EVT, 4> ValueVTs;
7369 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7370 bool isArgValueUsed = !I->use_empty();
7371 unsigned PartBase = 0;
7372 Type *FinalType = I->getType();
7373 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7374 FinalType = cast<PointerType>(FinalType)->getElementType();
7375 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7376 FinalType, F.getCallingConv(), F.isVarArg());
7377 for (unsigned Value = 0, NumValues = ValueVTs.size();
7378 Value != NumValues; ++Value) {
7379 EVT VT = ValueVTs[Value];
7380 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7381 ISD::ArgFlagsTy Flags;
7382 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7384 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7386 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7388 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7390 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7392 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7394 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7395 Flags.setInAlloca();
7396 // Set the byval flag for CCAssignFn callbacks that don't know about
7397 // inalloca. This way we can know how many bytes we should've allocated
7398 // and how many bytes a callee cleanup function will pop. If we port
7399 // inalloca to more targets, we'll have to add custom inalloca handling
7400 // in the various CC lowering callbacks.
7403 if (F.getCallingConv() == CallingConv::X86_INTR) {
7404 // IA Interrupt passes frame (1st parameter) by value in the stack.
7408 if (Flags.isByVal() || Flags.isInAlloca()) {
7409 PointerType *Ty = cast<PointerType>(I->getType());
7410 Type *ElementTy = Ty->getElementType();
7411 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7412 // For ByVal, alignment should be passed from FE. BE will guess if
7413 // this info is not there but there are cases it cannot get right.
7414 unsigned FrameAlign;
7415 if (F.getParamAlignment(Idx))
7416 FrameAlign = F.getParamAlignment(Idx);
7418 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7419 Flags.setByValAlign(FrameAlign);
7421 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7424 Flags.setInConsecutiveRegs();
7425 Flags.setOrigAlign(OriginalAlignment);
7427 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7428 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7429 for (unsigned i = 0; i != NumRegs; ++i) {
7430 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7431 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7432 if (NumRegs > 1 && i == 0)
7433 MyFlags.Flags.setSplit();
7434 // if it isn't first piece, alignment must be 1
7436 MyFlags.Flags.setOrigAlign(1);
7437 if (i == NumRegs - 1)
7438 MyFlags.Flags.setSplitEnd();
7440 Ins.push_back(MyFlags);
7442 if (NeedsRegBlock && Value == NumValues - 1)
7443 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7444 PartBase += VT.getStoreSize();
7448 // Call the target to set up the argument values.
7449 SmallVector<SDValue, 8> InVals;
7450 SDValue NewRoot = TLI->LowerFormalArguments(
7451 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7453 // Verify that the target's LowerFormalArguments behaved as expected.
7454 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7455 "LowerFormalArguments didn't return a valid chain!");
7456 assert(InVals.size() == Ins.size() &&
7457 "LowerFormalArguments didn't emit the correct number of values!");
7459 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7460 assert(InVals[i].getNode() &&
7461 "LowerFormalArguments emitted a null value!");
7462 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7463 "LowerFormalArguments emitted a value with the wrong type!");
7467 // Update the DAG with the new chain value resulting from argument lowering.
7468 DAG.setRoot(NewRoot);
7470 // Set up the argument values.
7473 if (!FuncInfo->CanLowerReturn) {
7474 // Create a virtual register for the sret pointer, and put in a copy
7475 // from the sret argument into it.
7476 SmallVector<EVT, 1> ValueVTs;
7477 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7478 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7479 MVT VT = ValueVTs[0].getSimpleVT();
7480 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7481 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7482 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7483 RegVT, VT, nullptr, AssertOp);
7485 MachineFunction& MF = SDB->DAG.getMachineFunction();
7486 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7487 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7488 FuncInfo->DemoteRegister = SRetReg;
7490 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7491 DAG.setRoot(NewRoot);
7493 // i indexes lowered arguments. Bump it past the hidden sret argument.
7494 // Idx indexes LLVM arguments. Don't touch it.
7498 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7500 SmallVector<SDValue, 4> ArgValues;
7501 SmallVector<EVT, 4> ValueVTs;
7502 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7503 unsigned NumValues = ValueVTs.size();
7505 // If this argument is unused then remember its value. It is used to generate
7506 // debugging information.
7507 if (I->use_empty() && NumValues) {
7508 SDB->setUnusedArgValue(&*I, InVals[i]);
7510 // Also remember any frame index for use in FastISel.
7511 if (FrameIndexSDNode *FI =
7512 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7513 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7516 for (unsigned Val = 0; Val != NumValues; ++Val) {
7517 EVT VT = ValueVTs[Val];
7518 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7519 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7521 if (!I->use_empty()) {
7522 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7523 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7524 AssertOp = ISD::AssertSext;
7525 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7526 AssertOp = ISD::AssertZext;
7528 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7529 NumParts, PartVT, VT,
7530 nullptr, AssertOp));
7536 // We don't need to do anything else for unused arguments.
7537 if (ArgValues.empty())
7540 // Note down frame index.
7541 if (FrameIndexSDNode *FI =
7542 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7543 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7545 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7546 SDB->getCurSDLoc());
7548 SDB->setValue(&*I, Res);
7549 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7550 if (LoadSDNode *LNode =
7551 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7552 if (FrameIndexSDNode *FI =
7553 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7554 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7557 // If this argument is live outside of the entry block, insert a copy from
7558 // wherever we got it to the vreg that other BB's will reference it as.
7559 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7560 // If we can, though, try to skip creating an unnecessary vreg.
7561 // FIXME: This isn't very clean... it would be nice to make this more
7562 // general. It's also subtly incompatible with the hacks FastISel
7564 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7565 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7566 FuncInfo->ValueMap[&*I] = Reg;
7570 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7571 FuncInfo->InitializeRegForValue(&*I);
7572 SDB->CopyToExportRegsIfNeeded(&*I);
7576 assert(i == InVals.size() && "Argument register count mismatch!");
7578 // Finally, if the target has anything special to do, allow it to do so.
7579 EmitFunctionEntryCode();
7582 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7583 /// ensure constants are generated when needed. Remember the virtual registers
7584 /// that need to be added to the Machine PHI nodes as input. We cannot just
7585 /// directly add them, because expansion might result in multiple MBB's for one
7586 /// BB. As such, the start of the BB might correspond to a different MBB than
7590 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7591 const TerminatorInst *TI = LLVMBB->getTerminator();
7593 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7595 // Check PHI nodes in successors that expect a value to be available from this
7597 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7598 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7599 if (!isa<PHINode>(SuccBB->begin())) continue;
7600 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7602 // If this terminator has multiple identical successors (common for
7603 // switches), only handle each succ once.
7604 if (!SuccsHandled.insert(SuccMBB).second)
7607 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7609 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7610 // nodes and Machine PHI nodes, but the incoming operands have not been
7612 for (BasicBlock::const_iterator I = SuccBB->begin();
7613 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7614 // Ignore dead phi's.
7615 if (PN->use_empty()) continue;
7618 if (PN->getType()->isEmptyTy())
7622 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7624 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7625 unsigned &RegOut = ConstantsOut[C];
7627 RegOut = FuncInfo.CreateRegs(C->getType());
7628 CopyValueToVirtualRegister(C, RegOut);
7632 DenseMap<const Value *, unsigned>::iterator I =
7633 FuncInfo.ValueMap.find(PHIOp);
7634 if (I != FuncInfo.ValueMap.end())
7637 assert(isa<AllocaInst>(PHIOp) &&
7638 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7639 "Didn't codegen value into a register!??");
7640 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7641 CopyValueToVirtualRegister(PHIOp, Reg);
7645 // Remember that this register needs to added to the machine PHI node as
7646 // the input for this MBB.
7647 SmallVector<EVT, 4> ValueVTs;
7648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7649 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7650 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7651 EVT VT = ValueVTs[vti];
7652 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7653 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7654 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7655 Reg += NumRegisters;
7660 ConstantsOut.clear();
7663 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7666 SelectionDAGBuilder::StackProtectorDescriptor::
7667 AddSuccessorMBB(const BasicBlock *BB,
7668 MachineBasicBlock *ParentMBB,
7670 MachineBasicBlock *SuccMBB) {
7671 // If SuccBB has not been created yet, create it.
7673 MachineFunction *MF = ParentMBB->getParent();
7674 MachineFunction::iterator BBI(ParentMBB);
7675 SuccMBB = MF->CreateMachineBasicBlock(BB);
7676 MF->insert(++BBI, SuccMBB);
7678 // Add it as a successor of ParentMBB.
7679 ParentMBB->addSuccessor(
7680 SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
7684 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7685 MachineFunction::iterator I(MBB);
7686 if (++I == FuncInfo.MF->end())
7691 /// During lowering new call nodes can be created (such as memset, etc.).
7692 /// Those will become new roots of the current DAG, but complications arise
7693 /// when they are tail calls. In such cases, the call lowering will update
7694 /// the root, but the builder still needs to know that a tail call has been
7695 /// lowered in order to avoid generating an additional return.
7696 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7697 // If the node is null, we do have a tail call.
7698 if (MaybeTC.getNode() != nullptr)
7699 DAG.setRoot(MaybeTC);
7704 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7705 unsigned *TotalCases, unsigned First,
7707 assert(Last >= First);
7708 assert(TotalCases[Last] >= TotalCases[First]);
7710 APInt LowCase = Clusters[First].Low->getValue();
7711 APInt HighCase = Clusters[Last].High->getValue();
7712 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7714 // FIXME: A range of consecutive cases has 100% density, but only requires one
7715 // comparison to lower. We should discriminate against such consecutive ranges
7718 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7719 uint64_t Range = Diff + 1;
7722 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7724 assert(NumCases < UINT64_MAX / 100);
7725 assert(Range >= NumCases);
7727 return NumCases * 100 >= Range * MinJumpTableDensity;
7730 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7731 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7732 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7735 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7736 unsigned First, unsigned Last,
7737 const SwitchInst *SI,
7738 MachineBasicBlock *DefaultMBB,
7739 CaseCluster &JTCluster) {
7740 assert(First <= Last);
7742 auto Prob = BranchProbability::getZero();
7743 unsigned NumCmps = 0;
7744 std::vector<MachineBasicBlock*> Table;
7745 DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
7747 // Initialize probabilities in JTProbs.
7748 for (unsigned I = First; I <= Last; ++I)
7749 JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
7751 for (unsigned I = First; I <= Last; ++I) {
7752 assert(Clusters[I].Kind == CC_Range);
7753 Prob += Clusters[I].Prob;
7754 APInt Low = Clusters[I].Low->getValue();
7755 APInt High = Clusters[I].High->getValue();
7756 NumCmps += (Low == High) ? 1 : 2;
7758 // Fill the gap between this and the previous cluster.
7759 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7760 assert(PreviousHigh.slt(Low));
7761 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7762 for (uint64_t J = 0; J < Gap; J++)
7763 Table.push_back(DefaultMBB);
7765 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7766 for (uint64_t J = 0; J < ClusterSize; ++J)
7767 Table.push_back(Clusters[I].MBB);
7768 JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
7771 unsigned NumDests = JTProbs.size();
7772 if (isSuitableForBitTests(NumDests, NumCmps,
7773 Clusters[First].Low->getValue(),
7774 Clusters[Last].High->getValue())) {
7775 // Clusters[First..Last] should be lowered as bit tests instead.
7779 // Create the MBB that will load from and jump through the table.
7780 // Note: We create it here, but it's not inserted into the function yet.
7781 MachineFunction *CurMF = FuncInfo.MF;
7782 MachineBasicBlock *JumpTableMBB =
7783 CurMF->CreateMachineBasicBlock(SI->getParent());
7785 // Add successors. Note: use table order for determinism.
7786 SmallPtrSet<MachineBasicBlock *, 8> Done;
7787 for (MachineBasicBlock *Succ : Table) {
7788 if (Done.count(Succ))
7790 addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
7793 JumpTableMBB->normalizeSuccProbs();
7795 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7796 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7797 ->createJumpTableIndex(Table);
7799 // Set up the jump table info.
7800 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7801 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7802 Clusters[Last].High->getValue(), SI->getCondition(),
7804 JTCases.emplace_back(std::move(JTH), std::move(JT));
7806 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7807 JTCases.size() - 1, Prob);
7811 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7812 const SwitchInst *SI,
7813 MachineBasicBlock *DefaultMBB) {
7815 // Clusters must be non-empty, sorted, and only contain Range clusters.
7816 assert(!Clusters.empty());
7817 for (CaseCluster &C : Clusters)
7818 assert(C.Kind == CC_Range);
7819 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7820 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7824 if (!areJTsAllowed(TLI))
7827 const int64_t N = Clusters.size();
7828 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7830 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7831 SmallVector<unsigned, 8> TotalCases(N);
7833 for (unsigned i = 0; i < N; ++i) {
7834 APInt Hi = Clusters[i].High->getValue();
7835 APInt Lo = Clusters[i].Low->getValue();
7836 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7838 TotalCases[i] += TotalCases[i - 1];
7841 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7842 // Cheap case: the whole range might be suitable for jump table.
7843 CaseCluster JTCluster;
7844 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7845 Clusters[0] = JTCluster;
7851 // The algorithm below is not suitable for -O0.
7852 if (TM.getOptLevel() == CodeGenOpt::None)
7855 // Split Clusters into minimum number of dense partitions. The algorithm uses
7856 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7857 // for the Case Statement'" (1994), but builds the MinPartitions array in
7858 // reverse order to make it easier to reconstruct the partitions in ascending
7859 // order. In the choice between two optimal partitionings, it picks the one
7860 // which yields more jump tables.
7862 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7863 SmallVector<unsigned, 8> MinPartitions(N);
7864 // LastElement[i] is the last element of the partition starting at i.
7865 SmallVector<unsigned, 8> LastElement(N);
7866 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7867 SmallVector<unsigned, 8> NumTables(N);
7869 // Base case: There is only one way to partition Clusters[N-1].
7870 MinPartitions[N - 1] = 1;
7871 LastElement[N - 1] = N - 1;
7872 assert(MinJumpTableSize > 1);
7873 NumTables[N - 1] = 0;
7875 // Note: loop indexes are signed to avoid underflow.
7876 for (int64_t i = N - 2; i >= 0; i--) {
7877 // Find optimal partitioning of Clusters[i..N-1].
7878 // Baseline: Put Clusters[i] into a partition on its own.
7879 MinPartitions[i] = MinPartitions[i + 1] + 1;
7881 NumTables[i] = NumTables[i + 1];
7883 // Search for a solution that results in fewer partitions.
7884 for (int64_t j = N - 1; j > i; j--) {
7885 // Try building a partition from Clusters[i..j].
7886 if (isDense(Clusters, &TotalCases[0], i, j)) {
7887 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7888 bool IsTable = j - i + 1 >= MinJumpTableSize;
7889 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7891 // If this j leads to fewer partitions, or same number of partitions
7892 // with more lookup tables, it is a better partitioning.
7893 if (NumPartitions < MinPartitions[i] ||
7894 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7895 MinPartitions[i] = NumPartitions;
7897 NumTables[i] = Tables;
7903 // Iterate over the partitions, replacing some with jump tables in-place.
7904 unsigned DstIndex = 0;
7905 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7906 Last = LastElement[First];
7907 assert(Last >= First);
7908 assert(DstIndex <= First);
7909 unsigned NumClusters = Last - First + 1;
7911 CaseCluster JTCluster;
7912 if (NumClusters >= MinJumpTableSize &&
7913 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7914 Clusters[DstIndex++] = JTCluster;
7916 for (unsigned I = First; I <= Last; ++I)
7917 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7920 Clusters.resize(DstIndex);
7923 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7924 // FIXME: Using the pointer type doesn't seem ideal.
7925 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7926 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7930 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7933 const APInt &High) {
7934 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7935 // range of cases both require only one branch to lower. Just looking at the
7936 // number of clusters and destinations should be enough to decide whether to
7939 // To lower a range with bit tests, the range must fit the bitwidth of a
7941 if (!rangeFitsInWord(Low, High))
7944 // Decide whether it's profitable to lower this range with bit tests. Each
7945 // destination requires a bit test and branch, and there is an overall range
7946 // check branch. For a small number of clusters, separate comparisons might be
7947 // cheaper, and for many destinations, splitting the range might be better.
7948 return (NumDests == 1 && NumCmps >= 3) ||
7949 (NumDests == 2 && NumCmps >= 5) ||
7950 (NumDests == 3 && NumCmps >= 6);
7953 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7954 unsigned First, unsigned Last,
7955 const SwitchInst *SI,
7956 CaseCluster &BTCluster) {
7957 assert(First <= Last);
7961 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7962 unsigned NumCmps = 0;
7963 for (int64_t I = First; I <= Last; ++I) {
7964 assert(Clusters[I].Kind == CC_Range);
7965 Dests.set(Clusters[I].MBB->getNumber());
7966 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7968 unsigned NumDests = Dests.count();
7970 APInt Low = Clusters[First].Low->getValue();
7971 APInt High = Clusters[Last].High->getValue();
7972 assert(Low.slt(High));
7974 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7980 const int BitWidth = DAG.getTargetLoweringInfo()
7981 .getPointerTy(DAG.getDataLayout())
7983 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7985 // Check if the clusters cover a contiguous range such that no value in the
7986 // range will jump to the default statement.
7987 bool ContiguousRange = true;
7988 for (int64_t I = First + 1; I <= Last; ++I) {
7989 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7990 ContiguousRange = false;
7995 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7996 // Optimize the case where all the case values fit in a word without having
7997 // to subtract minValue. In this case, we can optimize away the subtraction.
7998 LowBound = APInt::getNullValue(Low.getBitWidth());
8000 ContiguousRange = false;
8003 CmpRange = High - Low;
8007 auto TotalProb = BranchProbability::getZero();
8008 for (unsigned i = First; i <= Last; ++i) {
8009 // Find the CaseBits for this destination.
8011 for (j = 0; j < CBV.size(); ++j)
8012 if (CBV[j].BB == Clusters[i].MBB)
8014 if (j == CBV.size())
8016 CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero()));
8017 CaseBits *CB = &CBV[j];
8019 // Update Mask, Bits and ExtraProb.
8020 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
8021 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
8022 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
8023 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
8024 CB->Bits += Hi - Lo + 1;
8025 CB->ExtraProb += Clusters[i].Prob;
8026 TotalProb += Clusters[i].Prob;
8030 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
8031 // Sort by probability first, number of bits second.
8032 if (a.ExtraProb != b.ExtraProb)
8033 return a.ExtraProb > b.ExtraProb;
8034 return a.Bits > b.Bits;
8037 for (auto &CB : CBV) {
8038 MachineBasicBlock *BitTestBB =
8039 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
8040 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
8042 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8043 SI->getCondition(), -1U, MVT::Other, false,
8044 ContiguousRange, nullptr, nullptr, std::move(BTI),
8047 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8048 BitTestCases.size() - 1, TotalProb);
8052 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8053 const SwitchInst *SI) {
8054 // Partition Clusters into as few subsets as possible, where each subset has a
8055 // range that fits in a machine word and has <= 3 unique destinations.
8058 // Clusters must be sorted and contain Range or JumpTable clusters.
8059 assert(!Clusters.empty());
8060 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8061 for (const CaseCluster &C : Clusters)
8062 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8063 for (unsigned i = 1; i < Clusters.size(); ++i)
8064 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8067 // The algorithm below is not suitable for -O0.
8068 if (TM.getOptLevel() == CodeGenOpt::None)
8071 // If target does not have legal shift left, do not emit bit tests at all.
8072 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8073 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8074 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8077 int BitWidth = PTy.getSizeInBits();
8078 const int64_t N = Clusters.size();
8080 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8081 SmallVector<unsigned, 8> MinPartitions(N);
8082 // LastElement[i] is the last element of the partition starting at i.
8083 SmallVector<unsigned, 8> LastElement(N);
8085 // FIXME: This might not be the best algorithm for finding bit test clusters.
8087 // Base case: There is only one way to partition Clusters[N-1].
8088 MinPartitions[N - 1] = 1;
8089 LastElement[N - 1] = N - 1;
8091 // Note: loop indexes are signed to avoid underflow.
8092 for (int64_t i = N - 2; i >= 0; --i) {
8093 // Find optimal partitioning of Clusters[i..N-1].
8094 // Baseline: Put Clusters[i] into a partition on its own.
8095 MinPartitions[i] = MinPartitions[i + 1] + 1;
8098 // Search for a solution that results in fewer partitions.
8099 // Note: the search is limited by BitWidth, reducing time complexity.
8100 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8101 // Try building a partition from Clusters[i..j].
8104 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8105 Clusters[j].High->getValue()))
8108 // Check nbr of destinations and cluster types.
8109 // FIXME: This works, but doesn't seem very efficient.
8110 bool RangesOnly = true;
8111 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8112 for (int64_t k = i; k <= j; k++) {
8113 if (Clusters[k].Kind != CC_Range) {
8117 Dests.set(Clusters[k].MBB->getNumber());
8119 if (!RangesOnly || Dests.count() > 3)
8122 // Check if it's a better partition.
8123 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8124 if (NumPartitions < MinPartitions[i]) {
8125 // Found a better partition.
8126 MinPartitions[i] = NumPartitions;
8132 // Iterate over the partitions, replacing with bit-test clusters in-place.
8133 unsigned DstIndex = 0;
8134 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8135 Last = LastElement[First];
8136 assert(First <= Last);
8137 assert(DstIndex <= First);
8139 CaseCluster BitTestCluster;
8140 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8141 Clusters[DstIndex++] = BitTestCluster;
8143 size_t NumClusters = Last - First + 1;
8144 std::memmove(&Clusters[DstIndex], &Clusters[First],
8145 sizeof(Clusters[0]) * NumClusters);
8146 DstIndex += NumClusters;
8149 Clusters.resize(DstIndex);
8152 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8153 MachineBasicBlock *SwitchMBB,
8154 MachineBasicBlock *DefaultMBB) {
8155 MachineFunction *CurMF = FuncInfo.MF;
8156 MachineBasicBlock *NextMBB = nullptr;
8157 MachineFunction::iterator BBI(W.MBB);
8158 if (++BBI != FuncInfo.MF->end())
8161 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8163 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8165 if (Size == 2 && W.MBB == SwitchMBB) {
8166 // If any two of the cases has the same destination, and if one value
8167 // is the same as the other, but has one bit unset that the other has set,
8168 // use bit manipulation to do two compares at once. For example:
8169 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8170 // TODO: This could be extended to merge any 2 cases in switches with 3
8172 // TODO: Handle cases where W.CaseBB != SwitchBB.
8173 CaseCluster &Small = *W.FirstCluster;
8174 CaseCluster &Big = *W.LastCluster;
8176 if (Small.Low == Small.High && Big.Low == Big.High &&
8177 Small.MBB == Big.MBB) {
8178 const APInt &SmallValue = Small.Low->getValue();
8179 const APInt &BigValue = Big.Low->getValue();
8181 // Check that there is only one bit different.
8182 APInt CommonBit = BigValue ^ SmallValue;
8183 if (CommonBit.isPowerOf2()) {
8184 SDValue CondLHS = getValue(Cond);
8185 EVT VT = CondLHS.getValueType();
8186 SDLoc DL = getCurSDLoc();
8188 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8189 DAG.getConstant(CommonBit, DL, VT));
8190 SDValue Cond = DAG.getSetCC(
8191 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8194 // Update successor info.
8195 // Both Small and Big will jump to Small.BB, so we sum up the
8197 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
8199 addSuccessorWithProb(
8200 SwitchMBB, DefaultMBB,
8201 // The default destination is the first successor in IR.
8202 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
8204 addSuccessorWithProb(SwitchMBB, DefaultMBB);
8206 // Insert the true branch.
8208 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8209 DAG.getBasicBlock(Small.MBB));
8210 // Insert the false branch.
8211 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8212 DAG.getBasicBlock(DefaultMBB));
8214 DAG.setRoot(BrCond);
8220 if (TM.getOptLevel() != CodeGenOpt::None) {
8221 // Order cases by probability so the most likely case will be checked first.
8222 std::sort(W.FirstCluster, W.LastCluster + 1,
8223 [](const CaseCluster &a, const CaseCluster &b) {
8224 return a.Prob > b.Prob;
8227 // Rearrange the case blocks so that the last one falls through if possible
8228 // without without changing the order of probabilities.
8229 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8231 if (I->Prob > W.LastCluster->Prob)
8233 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8234 std::swap(*I, *W.LastCluster);
8240 // Compute total probability.
8241 BranchProbability DefaultProb = W.DefaultProb;
8242 BranchProbability UnhandledProbs = DefaultProb;
8243 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
8244 UnhandledProbs += I->Prob;
8246 MachineBasicBlock *CurMBB = W.MBB;
8247 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8248 MachineBasicBlock *Fallthrough;
8249 if (I == W.LastCluster) {
8250 // For the last cluster, fall through to the default destination.
8251 Fallthrough = DefaultMBB;
8253 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8254 CurMF->insert(BBI, Fallthrough);
8255 // Put Cond in a virtual register to make it available from the new blocks.
8256 ExportFromCurrentBlock(Cond);
8258 UnhandledProbs -= I->Prob;
8261 case CC_JumpTable: {
8262 // FIXME: Optimize away range check based on pivot comparisons.
8263 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8264 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8266 // The jump block hasn't been inserted yet; insert it here.
8267 MachineBasicBlock *JumpMBB = JT->MBB;
8268 CurMF->insert(BBI, JumpMBB);
8270 auto JumpProb = I->Prob;
8271 auto FallthroughProb = UnhandledProbs;
8273 // If the default statement is a target of the jump table, we evenly
8274 // distribute the default probability to successors of CurMBB. Also
8275 // update the probability on the edge from JumpMBB to Fallthrough.
8276 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8277 SE = JumpMBB->succ_end();
8279 if (*SI == DefaultMBB) {
8280 JumpProb += DefaultProb / 2;
8281 FallthroughProb -= DefaultProb / 2;
8282 JumpMBB->setSuccProbability(SI, DefaultProb / 2);
8283 JumpMBB->normalizeSuccProbs();
8288 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
8289 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
8290 CurMBB->normalizeSuccProbs();
8292 // The jump table header will be inserted in our current block, do the
8293 // range check, and fall through to our fallthrough block.
8294 JTH->HeaderBB = CurMBB;
8295 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8297 // If we're in the right place, emit the jump table header right now.
8298 if (CurMBB == SwitchMBB) {
8299 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8300 JTH->Emitted = true;
8305 // FIXME: Optimize away range check based on pivot comparisons.
8306 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8308 // The bit test blocks haven't been inserted yet; insert them here.
8309 for (BitTestCase &BTC : BTB->Cases)
8310 CurMF->insert(BBI, BTC.ThisBB);
8312 // Fill in fields of the BitTestBlock.
8313 BTB->Parent = CurMBB;
8314 BTB->Default = Fallthrough;
8316 BTB->DefaultProb = UnhandledProbs;
8317 // If the cases in bit test don't form a contiguous range, we evenly
8318 // distribute the probability on the edge to Fallthrough to two
8319 // successors of CurMBB.
8320 if (!BTB->ContiguousRange) {
8321 BTB->Prob += DefaultProb / 2;
8322 BTB->DefaultProb -= DefaultProb / 2;
8325 // If we're in the right place, emit the bit test header right now.
8326 if (CurMBB == SwitchMBB) {
8327 visitBitTestHeader(*BTB, SwitchMBB);
8328 BTB->Emitted = true;
8333 const Value *RHS, *LHS, *MHS;
8335 if (I->Low == I->High) {
8336 // Check Cond == I->Low.
8342 // Check I->Low <= Cond <= I->High.
8349 // The false probability is the sum of all unhandled cases.
8350 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Prob,
8353 if (CurMBB == SwitchMBB)
8354 visitSwitchCase(CB, SwitchMBB);
8356 SwitchCases.push_back(CB);
8361 CurMBB = Fallthrough;
8365 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8366 CaseClusterIt First,
8367 CaseClusterIt Last) {
8368 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8369 if (X.Prob != CC.Prob)
8370 return X.Prob > CC.Prob;
8372 // Ties are broken by comparing the case value.
8373 return X.Low->getValue().slt(CC.Low->getValue());
8377 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8378 const SwitchWorkListItem &W,
8380 MachineBasicBlock *SwitchMBB) {
8381 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8382 "Clusters not sorted?");
8384 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8386 // Balance the tree based on branch probabilities to create a near-optimal (in
8387 // terms of search time given key frequency) binary search tree. See e.g. Kurt
8388 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8389 CaseClusterIt LastLeft = W.FirstCluster;
8390 CaseClusterIt FirstRight = W.LastCluster;
8391 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
8392 auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
8394 // Move LastLeft and FirstRight towards each other from opposite directions to
8395 // find a partitioning of the clusters which balances the probability on both
8396 // sides. If LeftProb and RightProb are equal, alternate which side is
8397 // taken to ensure 0-probability nodes are distributed evenly.
8399 while (LastLeft + 1 < FirstRight) {
8400 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
8401 LeftProb += (++LastLeft)->Prob;
8403 RightProb += (--FirstRight)->Prob;
8408 // Our binary search tree differs from a typical BST in that ours can have up
8409 // to three values in each leaf. The pivot selection above doesn't take that
8410 // into account, which means the tree might require more nodes and be less
8411 // efficient. We compensate for this here.
8413 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8414 unsigned NumRight = W.LastCluster - FirstRight + 1;
8416 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8417 // If one side has less than 3 clusters, and the other has more than 3,
8418 // consider taking a cluster from the other side.
8420 if (NumLeft < NumRight) {
8421 // Consider moving the first cluster on the right to the left side.
8422 CaseCluster &CC = *FirstRight;
8423 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8424 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8425 if (LeftSideRank <= RightSideRank) {
8426 // Moving the cluster to the left does not demote it.
8432 assert(NumRight < NumLeft);
8433 // Consider moving the last element on the left to the right side.
8434 CaseCluster &CC = *LastLeft;
8435 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8436 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8437 if (RightSideRank <= LeftSideRank) {
8438 // Moving the cluster to the right does not demot it.
8448 assert(LastLeft + 1 == FirstRight);
8449 assert(LastLeft >= W.FirstCluster);
8450 assert(FirstRight <= W.LastCluster);
8452 // Use the first element on the right as pivot since we will make less-than
8453 // comparisons against it.
8454 CaseClusterIt PivotCluster = FirstRight;
8455 assert(PivotCluster > W.FirstCluster);
8456 assert(PivotCluster <= W.LastCluster);
8458 CaseClusterIt FirstLeft = W.FirstCluster;
8459 CaseClusterIt LastRight = W.LastCluster;
8461 const ConstantInt *Pivot = PivotCluster->Low;
8463 // New blocks will be inserted immediately after the current one.
8464 MachineFunction::iterator BBI(W.MBB);
8467 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8468 // we can branch to its destination directly if it's squeezed exactly in
8469 // between the known lower bound and Pivot - 1.
8470 MachineBasicBlock *LeftMBB;
8471 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8472 FirstLeft->Low == W.GE &&
8473 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8474 LeftMBB = FirstLeft->MBB;
8476 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8477 FuncInfo.MF->insert(BBI, LeftMBB);
8479 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
8480 // Put Cond in a virtual register to make it available from the new blocks.
8481 ExportFromCurrentBlock(Cond);
8484 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8485 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8486 // directly if RHS.High equals the current upper bound.
8487 MachineBasicBlock *RightMBB;
8488 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8489 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8490 RightMBB = FirstRight->MBB;
8492 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8493 FuncInfo.MF->insert(BBI, RightMBB);
8495 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
8496 // Put Cond in a virtual register to make it available from the new blocks.
8497 ExportFromCurrentBlock(Cond);
8500 // Create the CaseBlock record that will be used to lower the branch.
8501 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8502 LeftProb, RightProb);
8504 if (W.MBB == SwitchMBB)
8505 visitSwitchCase(CB, SwitchMBB);
8507 SwitchCases.push_back(CB);
8510 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8511 // Extract cases from the switch.
8512 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8513 CaseClusterVector Clusters;
8514 Clusters.reserve(SI.getNumCases());
8515 for (auto I : SI.cases()) {
8516 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8517 const ConstantInt *CaseVal = I.getCaseValue();
8518 BranchProbability Prob =
8519 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
8520 : BranchProbability(1, SI.getNumCases() + 1);
8521 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
8524 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8526 // Cluster adjacent cases with the same destination. We do this at all
8527 // optimization levels because it's cheap to do and will make codegen faster
8528 // if there are many clusters.
8529 sortAndRangeify(Clusters);
8531 if (TM.getOptLevel() != CodeGenOpt::None) {
8532 // Replace an unreachable default with the most popular destination.
8533 // FIXME: Exploit unreachable default more aggressively.
8534 bool UnreachableDefault =
8535 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8536 if (UnreachableDefault && !Clusters.empty()) {
8537 DenseMap<const BasicBlock *, unsigned> Popularity;
8538 unsigned MaxPop = 0;
8539 const BasicBlock *MaxBB = nullptr;
8540 for (auto I : SI.cases()) {
8541 const BasicBlock *BB = I.getCaseSuccessor();
8542 if (++Popularity[BB] > MaxPop) {
8543 MaxPop = Popularity[BB];
8548 assert(MaxPop > 0 && MaxBB);
8549 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8551 // Remove cases that were pointing to the destination that is now the
8553 CaseClusterVector New;
8554 New.reserve(Clusters.size());
8555 for (CaseCluster &CC : Clusters) {
8556 if (CC.MBB != DefaultMBB)
8559 Clusters = std::move(New);
8563 // If there is only the default destination, jump there directly.
8564 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8565 if (Clusters.empty()) {
8566 SwitchMBB->addSuccessor(DefaultMBB);
8567 if (DefaultMBB != NextBlock(SwitchMBB)) {
8568 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8569 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8574 findJumpTables(Clusters, &SI, DefaultMBB);
8575 findBitTestClusters(Clusters, &SI);
8578 dbgs() << "Case clusters: ";
8579 for (const CaseCluster &C : Clusters) {
8580 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8581 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8583 C.Low->getValue().print(dbgs(), true);
8584 if (C.Low != C.High) {
8586 C.High->getValue().print(dbgs(), true);
8593 assert(!Clusters.empty());
8594 SwitchWorkList WorkList;
8595 CaseClusterIt First = Clusters.begin();
8596 CaseClusterIt Last = Clusters.end() - 1;
8597 auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);
8598 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
8600 while (!WorkList.empty()) {
8601 SwitchWorkListItem W = WorkList.back();
8602 WorkList.pop_back();
8603 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8605 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8606 // For optimized builds, lower large range as a balanced binary tree.
8607 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8611 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);