1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getTargetConstant(1, TLI.getPointerTy()));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
211 /// getCopyFromParts - Create a value that contains the specified legal parts
212 /// combined into the value they represent. If the parts combine to a type
213 /// larger then ValueVT then AssertOp can be used to specify whether the extra
214 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
215 /// (ISD::AssertSext).
216 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
217 const SDValue *Parts, unsigned NumParts,
218 EVT PartVT, EVT ValueVT) {
219 assert(ValueVT.isVector() && "Not a vector value");
220 assert(NumParts > 0 && "No parts to assemble!");
221 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
222 SDValue Val = Parts[0];
224 // Handle a multi-element vector.
226 EVT IntermediateVT, RegisterVT;
227 unsigned NumIntermediates;
229 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
230 NumIntermediates, RegisterVT);
231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
232 NumParts = NumRegs; // Silence a compiler warning.
233 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
234 assert(RegisterVT == Parts[0].getValueType() &&
235 "Part type doesn't match part!");
237 // Assemble the parts into intermediate operands.
238 SmallVector<SDValue, 8> Ops(NumIntermediates);
239 if (NumIntermediates == NumParts) {
240 // If the register was not expanded, truncate or copy the value,
242 for (unsigned i = 0; i != NumParts; ++i)
243 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
244 PartVT, IntermediateVT);
245 } else if (NumParts > 0) {
246 // If the intermediate type was expanded, build the intermediate
247 // operands from the parts.
248 assert(NumParts % NumIntermediates == 0 &&
249 "Must expand into a divisible number of parts!");
250 unsigned Factor = NumParts / NumIntermediates;
251 for (unsigned i = 0; i != NumIntermediates; ++i)
252 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
253 PartVT, IntermediateVT);
256 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
257 // intermediate operands.
258 Val = DAG.getNode(IntermediateVT.isVector() ?
259 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
260 ValueVT, &Ops[0], NumIntermediates);
263 // There is now one part, held in Val. Correct it to match ValueVT.
264 PartVT = Val.getValueType();
266 if (PartVT == ValueVT)
269 if (PartVT.isVector()) {
270 // If the element type of the source/dest vectors are the same, but the
271 // parts vector has more elements than the value vector, then we have a
272 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
274 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
275 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
276 "Cannot narrow, it would be a lossy transformation");
277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
278 DAG.getIntPtrConstant(0));
281 // Vector/Vector bitcast.
282 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
285 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
286 "Cannot handle this kind of promotion");
287 // Promoted vector extract
288 bool Smaller = ValueVT.bitsLE(PartVT);
289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
294 // Trivial bitcast if the types are the same size and the destination
295 // vector type is legal.
296 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
297 TLI.isTypeLegal(ValueVT))
298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
300 // Handle cases such as i8 -> <1 x i1>
301 assert(ValueVT.getVectorNumElements() == 1 &&
302 "Only trivial scalar-to-vector conversions should get here!");
304 if (ValueVT.getVectorNumElements() == 1 &&
305 ValueVT.getVectorElementType() != PartVT) {
306 bool Smaller = ValueVT.bitsLE(PartVT);
307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
308 DL, ValueVT.getScalarType(), Val);
311 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
317 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
318 SDValue Val, SDValue *Parts, unsigned NumParts,
321 /// getCopyToParts - Create a series of nodes that contain the specified value
322 /// split into legal parts. If the parts contain more bits than Val, then, for
323 /// integers, ExtendKind can be used to specify how to generate the extra bits.
324 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
325 SDValue Val, SDValue *Parts, unsigned NumParts,
327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
328 EVT ValueVT = Val.getValueType();
330 // Handle the vector case separately.
331 if (ValueVT.isVector())
332 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
334 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
335 unsigned PartBits = PartVT.getSizeInBits();
336 unsigned OrigNumParts = NumParts;
337 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
342 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
343 if (PartVT == ValueVT) {
344 assert(NumParts == 1 && "No-op copy with multiple parts!");
349 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
350 // If the parts cover more bits than the value has, promote the value.
351 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
352 assert(NumParts == 1 && "Do not know what to promote to!");
353 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
355 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
356 ValueVT.isInteger() &&
357 "Unknown mismatch!");
358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
360 if (PartVT == MVT::x86mmx)
361 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
363 } else if (PartBits == ValueVT.getSizeInBits()) {
364 // Different types of the same size.
365 assert(NumParts == 1 && PartVT != ValueVT);
366 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
367 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
368 // If the parts cover less bits than value has, truncate the value.
369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
370 ValueVT.isInteger() &&
371 "Unknown mismatch!");
372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
373 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
374 if (PartVT == MVT::x86mmx)
375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
378 // The value may have changed - recompute ValueVT.
379 ValueVT = Val.getValueType();
380 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
381 "Failed to tile the value with PartVT!");
384 assert(PartVT == ValueVT && "Type conversion failed!");
389 // Expand the value into multiple parts.
390 if (NumParts & (NumParts - 1)) {
391 // The number of parts is not a power of 2. Split off and copy the tail.
392 assert(PartVT.isInteger() && ValueVT.isInteger() &&
393 "Do not know what to expand to!");
394 unsigned RoundParts = 1 << Log2_32(NumParts);
395 unsigned RoundBits = RoundParts * PartBits;
396 unsigned OddParts = NumParts - RoundParts;
397 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
398 DAG.getIntPtrConstant(RoundBits));
399 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
401 if (TLI.isBigEndian())
402 // The odd parts were reversed by getCopyToParts - unreverse them.
403 std::reverse(Parts + RoundParts, Parts + NumParts);
405 NumParts = RoundParts;
406 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
407 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
410 // The number of parts is a power of 2. Repeatedly bisect the value using
412 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
413 EVT::getIntegerVT(*DAG.getContext(),
414 ValueVT.getSizeInBits()),
417 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
418 for (unsigned i = 0; i < NumParts; i += StepSize) {
419 unsigned ThisBits = StepSize * PartBits / 2;
420 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
421 SDValue &Part0 = Parts[i];
422 SDValue &Part1 = Parts[i+StepSize/2];
424 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
425 ThisVT, Part0, DAG.getIntPtrConstant(1));
426 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
427 ThisVT, Part0, DAG.getIntPtrConstant(0));
429 if (ThisBits == PartBits && ThisVT != PartVT) {
430 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
431 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
436 if (TLI.isBigEndian())
437 std::reverse(Parts, Parts + OrigNumParts);
441 /// getCopyToPartsVector - Create a series of nodes that contain the specified
442 /// value split into legal parts.
443 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
444 SDValue Val, SDValue *Parts, unsigned NumParts,
446 EVT ValueVT = Val.getValueType();
447 assert(ValueVT.isVector() && "Not a vector");
448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
451 if (PartVT == ValueVT) {
453 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
454 // Bitconvert vector->vector case.
455 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
456 } else if (PartVT.isVector() &&
457 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
458 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
459 EVT ElementVT = PartVT.getVectorElementType();
460 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
462 SmallVector<SDValue, 16> Ops;
463 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
464 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
465 ElementVT, Val, DAG.getIntPtrConstant(i)));
467 for (unsigned i = ValueVT.getVectorNumElements(),
468 e = PartVT.getVectorNumElements(); i != e; ++i)
469 Ops.push_back(DAG.getUNDEF(ElementVT));
471 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
473 // FIXME: Use CONCAT for 2x -> 4x.
475 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
476 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
477 } else if (PartVT.isVector() &&
478 PartVT.getVectorElementType().bitsGE(
479 ValueVT.getVectorElementType()) &&
480 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
482 // Promoted vector extract
483 bool Smaller = PartVT.bitsLE(ValueVT);
484 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
487 // Vector -> scalar conversion.
488 assert(ValueVT.getVectorNumElements() == 1 &&
489 "Only trivial vector-to-scalar conversions should get here!");
490 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
491 PartVT, Val, DAG.getIntPtrConstant(0));
493 bool Smaller = ValueVT.bitsLE(PartVT);
494 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
502 // Handle a multi-element vector.
503 EVT IntermediateVT, RegisterVT;
504 unsigned NumIntermediates;
505 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
507 NumIntermediates, RegisterVT);
508 unsigned NumElements = ValueVT.getVectorNumElements();
510 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
511 NumParts = NumRegs; // Silence a compiler warning.
512 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
514 // Split the vector into intermediate operands.
515 SmallVector<SDValue, 8> Ops(NumIntermediates);
516 for (unsigned i = 0; i != NumIntermediates; ++i) {
517 if (IntermediateVT.isVector())
518 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
520 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
522 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 IntermediateVT, Val, DAG.getIntPtrConstant(i));
526 // Split the intermediate operands into legal parts.
527 if (NumParts == NumIntermediates) {
528 // If the register was not expanded, promote or copy the value,
530 for (unsigned i = 0; i != NumParts; ++i)
531 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
532 } else if (NumParts > 0) {
533 // If the intermediate type was expanded, split each the value into
535 assert(NumParts % NumIntermediates == 0 &&
536 "Must expand into a divisible number of parts!");
537 unsigned Factor = NumParts / NumIntermediates;
538 for (unsigned i = 0; i != NumIntermediates; ++i)
539 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
547 /// RegsForValue - This struct represents the registers (physical or virtual)
548 /// that a particular set of values is assigned, and the type information
549 /// about the value. The most common situation is to represent one value at a
550 /// time, but struct or array values are handled element-wise as multiple
551 /// values. The splitting of aggregates is performed recursively, so that we
552 /// never have aggregate-typed registers. The values at this point do not
553 /// necessarily have legal types, so each value may require one or more
554 /// registers of some legal type.
556 struct RegsForValue {
557 /// ValueVTs - The value types of the values, which may not be legal, and
558 /// may need be promoted or synthesized from one or more registers.
560 SmallVector<EVT, 4> ValueVTs;
562 /// RegVTs - The value types of the registers. This is the same size as
563 /// ValueVTs and it records, for each value, what the type of the assigned
564 /// register or registers are. (Individual values are never synthesized
565 /// from more than one type of register.)
567 /// With virtual registers, the contents of RegVTs is redundant with TLI's
568 /// getRegisterType member function, however when with physical registers
569 /// it is necessary to have a separate record of the types.
571 SmallVector<EVT, 4> RegVTs;
573 /// Regs - This list holds the registers assigned to the values.
574 /// Each legal or promoted value requires one register, and each
575 /// expanded value requires multiple registers.
577 SmallVector<unsigned, 4> Regs;
581 RegsForValue(const SmallVector<unsigned, 4> ®s,
582 EVT regvt, EVT valuevt)
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
585 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
586 unsigned Reg, Type *Ty) {
587 ComputeValueVTs(tli, Ty, ValueVTs);
589 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
590 EVT ValueVT = ValueVTs[Value];
591 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
592 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// areValueTypesLegal - Return true if types of all the values are legal.
601 bool areValueTypesLegal(const TargetLowering &TLI) {
602 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
603 EVT RegisterVT = RegVTs[Value];
604 if (!TLI.isTypeLegal(RegisterVT))
610 /// append - Add the specified values to this one.
611 void append(const RegsForValue &RHS) {
612 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
613 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
614 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
617 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
618 /// this value and returns the result as a ValueVTs value. This uses
619 /// Chain/Flag as the input and updates them for the output Chain/Flag.
620 /// If the Flag pointer is NULL, no flag is used.
621 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
623 SDValue &Chain, SDValue *Flag) const;
625 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
626 /// specified value into the registers specified by this object. This uses
627 /// Chain/Flag as the input and updates them for the output Chain/Flag.
628 /// If the Flag pointer is NULL, no flag is used.
629 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
630 SDValue &Chain, SDValue *Flag) const;
632 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
633 /// operand list. This adds the code marker, matching input operand index
634 /// (if applicable), and includes the number of values added into it.
635 void AddInlineAsmOperands(unsigned Kind,
636 bool HasMatching, unsigned MatchingIdx,
638 std::vector<SDValue> &Ops) const;
642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
643 /// this value and returns the result as a ValueVT value. This uses
644 /// Chain/Flag as the input and updates them for the output Chain/Flag.
645 /// If the Flag pointer is NULL, no flag is used.
646 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
647 FunctionLoweringInfo &FuncInfo,
649 SDValue &Chain, SDValue *Flag) const {
650 // A Value with type {} or [0 x %t] needs no registers.
651 if (ValueVTs.empty())
654 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
656 // Assemble the legal parts into the final values.
657 SmallVector<SDValue, 4> Values(ValueVTs.size());
658 SmallVector<SDValue, 8> Parts;
659 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
660 // Copy the legal parts from the registers.
661 EVT ValueVT = ValueVTs[Value];
662 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
663 EVT RegisterVT = RegVTs[Value];
665 Parts.resize(NumRegs);
666 for (unsigned i = 0; i != NumRegs; ++i) {
669 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
672 *Flag = P.getValue(2);
675 Chain = P.getValue(1);
678 // If the source register was virtual and if we know something about it,
679 // add an assert node.
680 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
681 !RegisterVT.isInteger() || RegisterVT.isVector())
684 const FunctionLoweringInfo::LiveOutInfo *LOI =
685 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
689 unsigned RegSize = RegisterVT.getSizeInBits();
690 unsigned NumSignBits = LOI->NumSignBits;
691 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
693 // FIXME: We capture more information than the dag can represent. For
694 // now, just use the tightest assertzext/assertsext possible.
696 EVT FromVT(MVT::Other);
697 if (NumSignBits == RegSize)
698 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
699 else if (NumZeroBits >= RegSize-1)
700 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
701 else if (NumSignBits > RegSize-8)
702 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
703 else if (NumZeroBits >= RegSize-8)
704 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
705 else if (NumSignBits > RegSize-16)
706 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
707 else if (NumZeroBits >= RegSize-16)
708 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
709 else if (NumSignBits > RegSize-32)
710 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
711 else if (NumZeroBits >= RegSize-32)
712 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
716 // Add an assertion node.
717 assert(FromVT != MVT::Other);
718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
719 RegisterVT, P, DAG.getValueType(FromVT));
722 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
723 NumRegs, RegisterVT, ValueVT);
728 return DAG.getNode(ISD::MERGE_VALUES, dl,
729 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
730 &Values[0], ValueVTs.size());
733 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
734 /// specified value into the registers specified by this object. This uses
735 /// Chain/Flag as the input and updates them for the output Chain/Flag.
736 /// If the Flag pointer is NULL, no flag is used.
737 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
738 SDValue &Chain, SDValue *Flag) const {
739 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
741 // Get the list of the values's legal parts.
742 unsigned NumRegs = Regs.size();
743 SmallVector<SDValue, 8> Parts(NumRegs);
744 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
745 EVT ValueVT = ValueVTs[Value];
746 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
747 EVT RegisterVT = RegVTs[Value];
749 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
750 &Parts[Part], NumParts, RegisterVT);
754 // Copy the parts into the registers.
755 SmallVector<SDValue, 8> Chains(NumRegs);
756 for (unsigned i = 0; i != NumRegs; ++i) {
759 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
761 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
762 *Flag = Part.getValue(1);
765 Chains[i] = Part.getValue(0);
768 if (NumRegs == 1 || Flag)
769 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
770 // flagged to it. That is the CopyToReg nodes and the user are considered
771 // a single scheduling unit. If we create a TokenFactor and return it as
772 // chain, then the TokenFactor is both a predecessor (operand) of the
773 // user as well as a successor (the TF operands are flagged to the user).
774 // c1, f1 = CopyToReg
775 // c2, f2 = CopyToReg
776 // c3 = TokenFactor c1, c2
779 Chain = Chains[NumRegs-1];
781 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
784 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
785 /// operand list. This adds the code marker and includes the number of
786 /// values added into it.
787 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
788 unsigned MatchingIdx,
790 std::vector<SDValue> &Ops) const {
791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
793 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
795 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
796 else if (!Regs.empty() &&
797 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
798 // Put the register class of the virtual registers in the flag word. That
799 // way, later passes can recompute register class constraints for inline
800 // assembly as well as normal instructions.
801 // Don't do this for tied operands that can use the regclass information
803 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
804 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
805 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
808 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
811 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
812 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
813 EVT RegisterVT = RegVTs[Value];
814 for (unsigned i = 0; i != NumRegs; ++i) {
815 assert(Reg < Regs.size() && "Mismatch in # registers expected");
816 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
821 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
822 const TargetLibraryInfo *li) {
826 TD = DAG.getTarget().getTargetData();
827 LPadToCallSiteMap.clear();
830 /// clear - Clear out the current SelectionDAG and the associated
831 /// state and prepare this SelectionDAGBuilder object to be used
832 /// for a new block. This doesn't clear out information about
833 /// additional blocks that are needed to complete switch lowering
834 /// or PHI node updating; that information is cleared out as it is
836 void SelectionDAGBuilder::clear() {
838 UnusedArgNodeMap.clear();
839 PendingLoads.clear();
840 PendingExports.clear();
841 CurDebugLoc = DebugLoc();
845 /// clearDanglingDebugInfo - Clear the dangling debug information
846 /// map. This function is seperated from the clear so that debug
847 /// information that is dangling in a basic block can be properly
848 /// resolved in a different basic block. This allows the
849 /// SelectionDAG to resolve dangling debug information attached
851 void SelectionDAGBuilder::clearDanglingDebugInfo() {
852 DanglingDebugInfoMap.clear();
855 /// getRoot - Return the current virtual root of the Selection DAG,
856 /// flushing any PendingLoad items. This must be done before emitting
857 /// a store or any other node that may need to be ordered after any
858 /// prior load instructions.
860 SDValue SelectionDAGBuilder::getRoot() {
861 if (PendingLoads.empty())
862 return DAG.getRoot();
864 if (PendingLoads.size() == 1) {
865 SDValue Root = PendingLoads[0];
867 PendingLoads.clear();
871 // Otherwise, we have to make a token factor node.
872 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
873 &PendingLoads[0], PendingLoads.size());
874 PendingLoads.clear();
879 /// getControlRoot - Similar to getRoot, but instead of flushing all the
880 /// PendingLoad items, flush all the PendingExports items. It is necessary
881 /// to do this before emitting a terminator instruction.
883 SDValue SelectionDAGBuilder::getControlRoot() {
884 SDValue Root = DAG.getRoot();
886 if (PendingExports.empty())
889 // Turn all of the CopyToReg chains into one factored node.
890 if (Root.getOpcode() != ISD::EntryToken) {
891 unsigned i = 0, e = PendingExports.size();
892 for (; i != e; ++i) {
893 assert(PendingExports[i].getNode()->getNumOperands() > 1);
894 if (PendingExports[i].getNode()->getOperand(0) == Root)
895 break; // Don't add the root if we already indirectly depend on it.
899 PendingExports.push_back(Root);
902 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
904 PendingExports.size());
905 PendingExports.clear();
910 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
911 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
912 DAG.AssignOrdering(Node, SDNodeOrder);
914 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
915 AssignOrderingToNode(Node->getOperand(I).getNode());
918 void SelectionDAGBuilder::visit(const Instruction &I) {
919 // Set up outgoing PHI node register values before emitting the terminator.
920 if (isa<TerminatorInst>(&I))
921 HandlePHINodesInSuccessorBlocks(I.getParent());
923 CurDebugLoc = I.getDebugLoc();
925 visit(I.getOpcode(), I);
927 if (!isa<TerminatorInst>(&I) && !HasTailCall)
928 CopyToExportRegsIfNeeded(&I);
930 CurDebugLoc = DebugLoc();
933 void SelectionDAGBuilder::visitPHI(const PHINode &) {
934 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
937 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
938 // Note: this doesn't use InstVisitor, because it has to work with
939 // ConstantExpr's in addition to instructions.
941 default: llvm_unreachable("Unknown instruction type encountered!");
942 // Build the switch statement using the Instruction.def file.
943 #define HANDLE_INST(NUM, OPCODE, CLASS) \
944 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
945 #include "llvm/Instruction.def"
948 // Assign the ordering to the freshly created DAG nodes.
949 if (NodeMap.count(&I)) {
951 AssignOrderingToNode(getValue(&I).getNode());
955 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
956 // generate the debug data structures now that we've seen its definition.
957 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
959 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
961 const DbgValueInst *DI = DDI.getDI();
962 DebugLoc dl = DDI.getdl();
963 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
964 MDNode *Variable = DI->getVariable();
965 uint64_t Offset = DI->getOffset();
968 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
969 SDV = DAG.getDbgValue(Variable, Val.getNode(),
970 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
971 DAG.AddDbgValue(SDV, Val.getNode(), false);
974 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
975 DanglingDebugInfoMap[V] = DanglingDebugInfo();
979 /// getValue - Return an SDValue for the given Value.
980 SDValue SelectionDAGBuilder::getValue(const Value *V) {
981 // If we already have an SDValue for this value, use it. It's important
982 // to do this first, so that we don't create a CopyFromReg if we already
983 // have a regular SDValue.
984 SDValue &N = NodeMap[V];
985 if (N.getNode()) return N;
987 // If there's a virtual register allocated and initialized for this
989 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
990 if (It != FuncInfo.ValueMap.end()) {
991 unsigned InReg = It->second;
992 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
993 SDValue Chain = DAG.getEntryNode();
994 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
995 resolveDanglingDebugInfo(V, N);
999 // Otherwise create a new SDValue and remember it.
1000 SDValue Val = getValueImpl(V);
1002 resolveDanglingDebugInfo(V, Val);
1006 /// getNonRegisterValue - Return an SDValue for the given Value, but
1007 /// don't look in FuncInfo.ValueMap for a virtual register.
1008 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1009 // If we already have an SDValue for this value, use it.
1010 SDValue &N = NodeMap[V];
1011 if (N.getNode()) return N;
1013 // Otherwise create a new SDValue and remember it.
1014 SDValue Val = getValueImpl(V);
1016 resolveDanglingDebugInfo(V, Val);
1020 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1021 /// Create an SDValue for the given value.
1022 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1023 if (const Constant *C = dyn_cast<Constant>(V)) {
1024 EVT VT = TLI.getValueType(V->getType(), true);
1026 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1027 return DAG.getConstant(*CI, VT);
1029 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1030 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1032 if (isa<ConstantPointerNull>(C))
1033 return DAG.getConstant(0, TLI.getPointerTy());
1035 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1036 return DAG.getConstantFP(*CFP, VT);
1038 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1039 return DAG.getUNDEF(VT);
1041 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1042 visit(CE->getOpcode(), *CE);
1043 SDValue N1 = NodeMap[V];
1044 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1048 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1049 SmallVector<SDValue, 4> Constants;
1050 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1052 SDNode *Val = getValue(*OI).getNode();
1053 // If the operand is an empty aggregate, there are no values.
1055 // Add each leaf value from the operand to the Constants list
1056 // to form a flattened list of all the values.
1057 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1058 Constants.push_back(SDValue(Val, i));
1061 return DAG.getMergeValues(&Constants[0], Constants.size(),
1065 if (const ConstantDataSequential *CDS =
1066 dyn_cast<ConstantDataSequential>(C)) {
1067 SmallVector<SDValue, 4> Ops;
1068 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1069 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1070 // Add each leaf value from the operand to the Constants list
1071 // to form a flattened list of all the values.
1072 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1073 Ops.push_back(SDValue(Val, i));
1076 if (isa<ArrayType>(CDS->getType()))
1077 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1078 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1079 VT, &Ops[0], Ops.size());
1082 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1083 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1084 "Unknown struct or array constant!");
1086 SmallVector<EVT, 4> ValueVTs;
1087 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1088 unsigned NumElts = ValueVTs.size();
1090 return SDValue(); // empty struct
1091 SmallVector<SDValue, 4> Constants(NumElts);
1092 for (unsigned i = 0; i != NumElts; ++i) {
1093 EVT EltVT = ValueVTs[i];
1094 if (isa<UndefValue>(C))
1095 Constants[i] = DAG.getUNDEF(EltVT);
1096 else if (EltVT.isFloatingPoint())
1097 Constants[i] = DAG.getConstantFP(0, EltVT);
1099 Constants[i] = DAG.getConstant(0, EltVT);
1102 return DAG.getMergeValues(&Constants[0], NumElts,
1106 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1107 return DAG.getBlockAddress(BA, VT);
1109 VectorType *VecTy = cast<VectorType>(V->getType());
1110 unsigned NumElements = VecTy->getNumElements();
1112 // Now that we know the number and type of the elements, get that number of
1113 // elements into the Ops array based on what kind of constant it is.
1114 SmallVector<SDValue, 16> Ops;
1115 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1116 for (unsigned i = 0; i != NumElements; ++i)
1117 Ops.push_back(getValue(CV->getOperand(i)));
1119 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1120 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1123 if (EltVT.isFloatingPoint())
1124 Op = DAG.getConstantFP(0, EltVT);
1126 Op = DAG.getConstant(0, EltVT);
1127 Ops.assign(NumElements, Op);
1130 // Create a BUILD_VECTOR node.
1131 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1132 VT, &Ops[0], Ops.size());
1135 // If this is a static alloca, generate it as the frameindex instead of
1137 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1138 DenseMap<const AllocaInst*, int>::iterator SI =
1139 FuncInfo.StaticAllocaMap.find(AI);
1140 if (SI != FuncInfo.StaticAllocaMap.end())
1141 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1144 // If this is an instruction which fast-isel has deferred, select it now.
1145 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1146 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1147 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1148 SDValue Chain = DAG.getEntryNode();
1149 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1152 llvm_unreachable("Can't get register for value!");
1155 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1156 SDValue Chain = getControlRoot();
1157 SmallVector<ISD::OutputArg, 8> Outs;
1158 SmallVector<SDValue, 8> OutVals;
1160 if (!FuncInfo.CanLowerReturn) {
1161 unsigned DemoteReg = FuncInfo.DemoteRegister;
1162 const Function *F = I.getParent()->getParent();
1164 // Emit a store of the return value through the virtual register.
1165 // Leave Outs empty so that LowerReturn won't try to load return
1166 // registers the usual way.
1167 SmallVector<EVT, 1> PtrValueVTs;
1168 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1171 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1172 SDValue RetOp = getValue(I.getOperand(0));
1174 SmallVector<EVT, 4> ValueVTs;
1175 SmallVector<uint64_t, 4> Offsets;
1176 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1177 unsigned NumValues = ValueVTs.size();
1179 SmallVector<SDValue, 4> Chains(NumValues);
1180 for (unsigned i = 0; i != NumValues; ++i) {
1181 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1182 RetPtr.getValueType(), RetPtr,
1183 DAG.getIntPtrConstant(Offsets[i]));
1185 DAG.getStore(Chain, getCurDebugLoc(),
1186 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1187 // FIXME: better loc info would be nice.
1188 Add, MachinePointerInfo(), false, false, 0);
1191 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1192 MVT::Other, &Chains[0], NumValues);
1193 } else if (I.getNumOperands() != 0) {
1194 SmallVector<EVT, 4> ValueVTs;
1195 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1196 unsigned NumValues = ValueVTs.size();
1198 SDValue RetOp = getValue(I.getOperand(0));
1199 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1200 EVT VT = ValueVTs[j];
1202 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1204 const Function *F = I.getParent()->getParent();
1205 if (F->paramHasAttr(0, Attribute::SExt))
1206 ExtendKind = ISD::SIGN_EXTEND;
1207 else if (F->paramHasAttr(0, Attribute::ZExt))
1208 ExtendKind = ISD::ZERO_EXTEND;
1210 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1211 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1213 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1214 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1215 SmallVector<SDValue, 4> Parts(NumParts);
1216 getCopyToParts(DAG, getCurDebugLoc(),
1217 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1218 &Parts[0], NumParts, PartVT, ExtendKind);
1220 // 'inreg' on function refers to return value
1221 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1222 if (F->paramHasAttr(0, Attribute::InReg))
1225 // Propagate extension type if any
1226 if (ExtendKind == ISD::SIGN_EXTEND)
1228 else if (ExtendKind == ISD::ZERO_EXTEND)
1231 for (unsigned i = 0; i < NumParts; ++i) {
1232 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1234 OutVals.push_back(Parts[i]);
1240 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1241 CallingConv::ID CallConv =
1242 DAG.getMachineFunction().getFunction()->getCallingConv();
1243 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1244 Outs, OutVals, getCurDebugLoc(), DAG);
1246 // Verify that the target's LowerReturn behaved as expected.
1247 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1248 "LowerReturn didn't return a valid chain!");
1250 // Update the DAG with the new chain value resulting from return lowering.
1254 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1255 /// created for it, emit nodes to copy the value into the virtual
1257 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1259 if (V->getType()->isEmptyTy())
1262 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1263 if (VMI != FuncInfo.ValueMap.end()) {
1264 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1265 CopyValueToVirtualRegister(V, VMI->second);
1269 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1270 /// the current basic block, add it to ValueMap now so that we'll get a
1272 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1273 // No need to export constants.
1274 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1276 // Already exported?
1277 if (FuncInfo.isExportedInst(V)) return;
1279 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1280 CopyValueToVirtualRegister(V, Reg);
1283 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1284 const BasicBlock *FromBB) {
1285 // The operands of the setcc have to be in this block. We don't know
1286 // how to export them from some other block.
1287 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1288 // Can export from current BB.
1289 if (VI->getParent() == FromBB)
1292 // Is already exported, noop.
1293 return FuncInfo.isExportedInst(V);
1296 // If this is an argument, we can export it if the BB is the entry block or
1297 // if it is already exported.
1298 if (isa<Argument>(V)) {
1299 if (FromBB == &FromBB->getParent()->getEntryBlock())
1302 // Otherwise, can only export this if it is already exported.
1303 return FuncInfo.isExportedInst(V);
1306 // Otherwise, constants can always be exported.
1310 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1311 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1312 const MachineBasicBlock *Dst) const {
1313 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1316 const BasicBlock *SrcBB = Src->getBasicBlock();
1317 const BasicBlock *DstBB = Dst->getBasicBlock();
1318 return BPI->getEdgeWeight(SrcBB, DstBB);
1321 void SelectionDAGBuilder::
1322 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1323 uint32_t Weight /* = 0 */) {
1325 Weight = getEdgeWeight(Src, Dst);
1326 Src->addSuccessor(Dst, Weight);
1330 static bool InBlock(const Value *V, const BasicBlock *BB) {
1331 if (const Instruction *I = dyn_cast<Instruction>(V))
1332 return I->getParent() == BB;
1336 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1337 /// This function emits a branch and is used at the leaves of an OR or an
1338 /// AND operator tree.
1341 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1342 MachineBasicBlock *TBB,
1343 MachineBasicBlock *FBB,
1344 MachineBasicBlock *CurBB,
1345 MachineBasicBlock *SwitchBB) {
1346 const BasicBlock *BB = CurBB->getBasicBlock();
1348 // If the leaf of the tree is a comparison, merge the condition into
1350 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1351 // The operands of the cmp have to be in this block. We don't know
1352 // how to export them from some other block. If this is the first block
1353 // of the sequence, no exporting is needed.
1354 if (CurBB == SwitchBB ||
1355 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1356 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1357 ISD::CondCode Condition;
1358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1359 Condition = getICmpCondCode(IC->getPredicate());
1360 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1361 Condition = getFCmpCondCode(FC->getPredicate());
1362 if (TM.Options.NoNaNsFPMath)
1363 Condition = getFCmpCodeWithoutNaN(Condition);
1365 Condition = ISD::SETEQ; // silence warning.
1366 llvm_unreachable("Unknown compare instruction");
1369 CaseBlock CB(Condition, BOp->getOperand(0),
1370 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1371 SwitchCases.push_back(CB);
1376 // Create a CaseBlock record representing this branch.
1377 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1378 NULL, TBB, FBB, CurBB);
1379 SwitchCases.push_back(CB);
1382 /// FindMergedConditions - If Cond is an expression like
1383 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1384 MachineBasicBlock *TBB,
1385 MachineBasicBlock *FBB,
1386 MachineBasicBlock *CurBB,
1387 MachineBasicBlock *SwitchBB,
1389 // If this node is not part of the or/and tree, emit it as a branch.
1390 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1391 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1392 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1393 BOp->getParent() != CurBB->getBasicBlock() ||
1394 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1395 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1396 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1400 // Create TmpBB after CurBB.
1401 MachineFunction::iterator BBI = CurBB;
1402 MachineFunction &MF = DAG.getMachineFunction();
1403 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1404 CurBB->getParent()->insert(++BBI, TmpBB);
1406 if (Opc == Instruction::Or) {
1407 // Codegen X | Y as:
1415 // Emit the LHS condition.
1416 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1418 // Emit the RHS condition into TmpBB.
1419 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1421 assert(Opc == Instruction::And && "Unknown merge op!");
1422 // Codegen X & Y as:
1429 // This requires creation of TmpBB after CurBB.
1431 // Emit the LHS condition.
1432 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1434 // Emit the RHS condition into TmpBB.
1435 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1439 /// If the set of cases should be emitted as a series of branches, return true.
1440 /// If we should emit this as a bunch of and/or'd together conditions, return
1443 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1444 if (Cases.size() != 2) return true;
1446 // If this is two comparisons of the same values or'd or and'd together, they
1447 // will get folded into a single comparison, so don't emit two blocks.
1448 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1449 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1450 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1451 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1455 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1456 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1457 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1458 Cases[0].CC == Cases[1].CC &&
1459 isa<Constant>(Cases[0].CmpRHS) &&
1460 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1461 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1463 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1470 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1471 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1473 // Update machine-CFG edges.
1474 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1476 // Figure out which block is immediately after the current one.
1477 MachineBasicBlock *NextBlock = 0;
1478 MachineFunction::iterator BBI = BrMBB;
1479 if (++BBI != FuncInfo.MF->end())
1482 if (I.isUnconditional()) {
1483 // Update machine-CFG edges.
1484 BrMBB->addSuccessor(Succ0MBB);
1486 // If this is not a fall-through branch, emit the branch.
1487 if (Succ0MBB != NextBlock)
1488 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1489 MVT::Other, getControlRoot(),
1490 DAG.getBasicBlock(Succ0MBB)));
1495 // If this condition is one of the special cases we handle, do special stuff
1497 const Value *CondVal = I.getCondition();
1498 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1500 // If this is a series of conditions that are or'd or and'd together, emit
1501 // this as a sequence of branches instead of setcc's with and/or operations.
1502 // As long as jumps are not expensive, this should improve performance.
1503 // For example, instead of something like:
1516 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1517 if (!TLI.isJumpExpensive() &&
1519 (BOp->getOpcode() == Instruction::And ||
1520 BOp->getOpcode() == Instruction::Or)) {
1521 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1523 // If the compares in later blocks need to use values not currently
1524 // exported from this block, export them now. This block should always
1525 // be the first entry.
1526 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1528 // Allow some cases to be rejected.
1529 if (ShouldEmitAsBranches(SwitchCases)) {
1530 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1531 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1532 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1535 // Emit the branch for this block.
1536 visitSwitchCase(SwitchCases[0], BrMBB);
1537 SwitchCases.erase(SwitchCases.begin());
1541 // Okay, we decided not to do this, remove any inserted MBB's and clear
1543 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1544 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1546 SwitchCases.clear();
1550 // Create a CaseBlock record representing this branch.
1551 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1552 NULL, Succ0MBB, Succ1MBB, BrMBB);
1554 // Use visitSwitchCase to actually insert the fast branch sequence for this
1556 visitSwitchCase(CB, BrMBB);
1559 /// visitSwitchCase - Emits the necessary code to represent a single node in
1560 /// the binary search tree resulting from lowering a switch instruction.
1561 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1562 MachineBasicBlock *SwitchBB) {
1564 SDValue CondLHS = getValue(CB.CmpLHS);
1565 DebugLoc dl = getCurDebugLoc();
1567 // Build the setcc now.
1568 if (CB.CmpMHS == NULL) {
1569 // Fold "(X == true)" to X and "(X == false)" to !X to
1570 // handle common cases produced by branch lowering.
1571 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1572 CB.CC == ISD::SETEQ)
1574 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1575 CB.CC == ISD::SETEQ) {
1576 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1577 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1579 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1581 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1583 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1584 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1586 SDValue CmpOp = getValue(CB.CmpMHS);
1587 EVT VT = CmpOp.getValueType();
1589 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1590 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1593 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1594 VT, CmpOp, DAG.getConstant(Low, VT));
1595 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1596 DAG.getConstant(High-Low, VT), ISD::SETULE);
1600 // Update successor info
1601 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1602 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1604 // Set NextBlock to be the MBB immediately after the current one, if any.
1605 // This is used to avoid emitting unnecessary branches to the next block.
1606 MachineBasicBlock *NextBlock = 0;
1607 MachineFunction::iterator BBI = SwitchBB;
1608 if (++BBI != FuncInfo.MF->end())
1611 // If the lhs block is the next block, invert the condition so that we can
1612 // fall through to the lhs instead of the rhs block.
1613 if (CB.TrueBB == NextBlock) {
1614 std::swap(CB.TrueBB, CB.FalseBB);
1615 SDValue True = DAG.getConstant(1, Cond.getValueType());
1616 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1619 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1620 MVT::Other, getControlRoot(), Cond,
1621 DAG.getBasicBlock(CB.TrueBB));
1623 // Insert the false branch. Do this even if it's a fall through branch,
1624 // this makes it easier to do DAG optimizations which require inverting
1625 // the branch condition.
1626 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1627 DAG.getBasicBlock(CB.FalseBB));
1629 DAG.setRoot(BrCond);
1632 /// visitJumpTable - Emit JumpTable node in the current MBB
1633 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1634 // Emit the code for the jump table
1635 assert(JT.Reg != -1U && "Should lower JT Header first!");
1636 EVT PTy = TLI.getPointerTy();
1637 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1639 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1640 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1641 MVT::Other, Index.getValue(1),
1643 DAG.setRoot(BrJumpTable);
1646 /// visitJumpTableHeader - This function emits necessary code to produce index
1647 /// in the JumpTable from switch case.
1648 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1649 JumpTableHeader &JTH,
1650 MachineBasicBlock *SwitchBB) {
1651 // Subtract the lowest switch case value from the value being switched on and
1652 // conditional branch to default mbb if the result is greater than the
1653 // difference between smallest and largest cases.
1654 SDValue SwitchOp = getValue(JTH.SValue);
1655 EVT VT = SwitchOp.getValueType();
1656 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1657 DAG.getConstant(JTH.First, VT));
1659 // The SDNode we just created, which holds the value being switched on minus
1660 // the smallest case value, needs to be copied to a virtual register so it
1661 // can be used as an index into the jump table in a subsequent basic block.
1662 // This value may be smaller or larger than the target's pointer type, and
1663 // therefore require extension or truncating.
1664 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1666 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1667 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1668 JumpTableReg, SwitchOp);
1669 JT.Reg = JumpTableReg;
1671 // Emit the range check for the jump table, and branch to the default block
1672 // for the switch statement if the value being switched on exceeds the largest
1673 // case in the switch.
1674 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1675 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1676 DAG.getConstant(JTH.Last-JTH.First,VT),
1679 // Set NextBlock to be the MBB immediately after the current one, if any.
1680 // This is used to avoid emitting unnecessary branches to the next block.
1681 MachineBasicBlock *NextBlock = 0;
1682 MachineFunction::iterator BBI = SwitchBB;
1684 if (++BBI != FuncInfo.MF->end())
1687 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1688 MVT::Other, CopyTo, CMP,
1689 DAG.getBasicBlock(JT.Default));
1691 if (JT.MBB != NextBlock)
1692 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1693 DAG.getBasicBlock(JT.MBB));
1695 DAG.setRoot(BrCond);
1698 /// visitBitTestHeader - This function emits necessary code to produce value
1699 /// suitable for "bit tests"
1700 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1701 MachineBasicBlock *SwitchBB) {
1702 // Subtract the minimum value
1703 SDValue SwitchOp = getValue(B.SValue);
1704 EVT VT = SwitchOp.getValueType();
1705 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1706 DAG.getConstant(B.First, VT));
1709 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1710 TLI.getSetCCResultType(Sub.getValueType()),
1711 Sub, DAG.getConstant(B.Range, VT),
1714 // Determine the type of the test operands.
1715 bool UsePtrType = false;
1716 if (!TLI.isTypeLegal(VT))
1719 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1720 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1721 // Switch table case range are encoded into series of masks.
1722 // Just use pointer type, it's guaranteed to fit.
1728 VT = TLI.getPointerTy();
1729 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1733 B.Reg = FuncInfo.CreateReg(VT);
1734 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1737 // Set NextBlock to be the MBB immediately after the current one, if any.
1738 // This is used to avoid emitting unnecessary branches to the next block.
1739 MachineBasicBlock *NextBlock = 0;
1740 MachineFunction::iterator BBI = SwitchBB;
1741 if (++BBI != FuncInfo.MF->end())
1744 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1746 addSuccessorWithWeight(SwitchBB, B.Default);
1747 addSuccessorWithWeight(SwitchBB, MBB);
1749 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1750 MVT::Other, CopyTo, RangeCmp,
1751 DAG.getBasicBlock(B.Default));
1753 if (MBB != NextBlock)
1754 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1755 DAG.getBasicBlock(MBB));
1757 DAG.setRoot(BrRange);
1760 /// visitBitTestCase - this function produces one "bit test"
1761 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1762 MachineBasicBlock* NextMBB,
1765 MachineBasicBlock *SwitchBB) {
1767 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1770 unsigned PopCount = CountPopulation_64(B.Mask);
1771 if (PopCount == 1) {
1772 // Testing for a single bit; just compare the shift count with what it
1773 // would need to be to shift a 1 bit in that position.
1774 Cmp = DAG.getSetCC(getCurDebugLoc(),
1775 TLI.getSetCCResultType(VT),
1777 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1779 } else if (PopCount == BB.Range) {
1780 // There is only one zero bit in the range, test for it directly.
1781 Cmp = DAG.getSetCC(getCurDebugLoc(),
1782 TLI.getSetCCResultType(VT),
1784 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1787 // Make desired shift
1788 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1789 DAG.getConstant(1, VT), ShiftOp);
1791 // Emit bit tests and jumps
1792 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1793 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1794 Cmp = DAG.getSetCC(getCurDebugLoc(),
1795 TLI.getSetCCResultType(VT),
1796 AndOp, DAG.getConstant(0, VT),
1800 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1801 addSuccessorWithWeight(SwitchBB, NextMBB);
1803 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1804 MVT::Other, getControlRoot(),
1805 Cmp, DAG.getBasicBlock(B.TargetBB));
1807 // Set NextBlock to be the MBB immediately after the current one, if any.
1808 // This is used to avoid emitting unnecessary branches to the next block.
1809 MachineBasicBlock *NextBlock = 0;
1810 MachineFunction::iterator BBI = SwitchBB;
1811 if (++BBI != FuncInfo.MF->end())
1814 if (NextMBB != NextBlock)
1815 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1816 DAG.getBasicBlock(NextMBB));
1821 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1822 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1824 // Retrieve successors.
1825 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1826 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1828 const Value *Callee(I.getCalledValue());
1829 if (isa<InlineAsm>(Callee))
1832 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1834 // If the value of the invoke is used outside of its defining block, make it
1835 // available as a virtual register.
1836 CopyToExportRegsIfNeeded(&I);
1838 // Update successor info
1839 addSuccessorWithWeight(InvokeMBB, Return);
1840 addSuccessorWithWeight(InvokeMBB, LandingPad);
1842 // Drop into normal successor.
1843 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1844 MVT::Other, getControlRoot(),
1845 DAG.getBasicBlock(Return)));
1848 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1849 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1852 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1853 assert(FuncInfo.MBB->isLandingPad() &&
1854 "Call to landingpad not in landing pad!");
1856 MachineBasicBlock *MBB = FuncInfo.MBB;
1857 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1858 AddLandingPadInfo(LP, MMI, MBB);
1860 // If there aren't registers to copy the values into (e.g., during SjLj
1861 // exceptions), then don't bother to create these DAG nodes.
1862 if (TLI.getExceptionPointerRegister() == 0 &&
1863 TLI.getExceptionSelectorRegister() == 0)
1866 SmallVector<EVT, 2> ValueVTs;
1867 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1869 // Insert the EXCEPTIONADDR instruction.
1870 assert(FuncInfo.MBB->isLandingPad() &&
1871 "Call to eh.exception not in landing pad!");
1872 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1874 Ops[0] = DAG.getRoot();
1875 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1876 SDValue Chain = Op1.getValue(1);
1878 // Insert the EHSELECTION instruction.
1879 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1882 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1883 Chain = Op2.getValue(1);
1884 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1888 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1889 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1892 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1893 setValue(&LP, RetPair.first);
1894 DAG.setRoot(RetPair.second);
1897 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1898 /// small case ranges).
1899 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1900 CaseRecVector& WorkList,
1902 MachineBasicBlock *Default,
1903 MachineBasicBlock *SwitchBB) {
1904 Case& BackCase = *(CR.Range.second-1);
1906 // Size is the number of Cases represented by this range.
1907 size_t Size = CR.Range.second - CR.Range.first;
1911 // Get the MachineFunction which holds the current MBB. This is used when
1912 // inserting any additional MBBs necessary to represent the switch.
1913 MachineFunction *CurMF = FuncInfo.MF;
1915 // Figure out which block is immediately after the current one.
1916 MachineBasicBlock *NextBlock = 0;
1917 MachineFunction::iterator BBI = CR.CaseBB;
1919 if (++BBI != FuncInfo.MF->end())
1922 // If any two of the cases has the same destination, and if one value
1923 // is the same as the other, but has one bit unset that the other has set,
1924 // use bit manipulation to do two compares at once. For example:
1925 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1926 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1927 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1928 if (Size == 2 && CR.CaseBB == SwitchBB) {
1929 Case &Small = *CR.Range.first;
1930 Case &Big = *(CR.Range.second-1);
1932 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1933 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1934 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1936 // Check that there is only one bit different.
1937 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1938 (SmallValue | BigValue) == BigValue) {
1939 // Isolate the common bit.
1940 APInt CommonBit = BigValue & ~SmallValue;
1941 assert((SmallValue | CommonBit) == BigValue &&
1942 CommonBit.countPopulation() == 1 && "Not a common bit?");
1944 SDValue CondLHS = getValue(SV);
1945 EVT VT = CondLHS.getValueType();
1946 DebugLoc DL = getCurDebugLoc();
1948 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1949 DAG.getConstant(CommonBit, VT));
1950 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1951 Or, DAG.getConstant(BigValue, VT),
1954 // Update successor info.
1955 addSuccessorWithWeight(SwitchBB, Small.BB);
1956 addSuccessorWithWeight(SwitchBB, Default);
1958 // Insert the true branch.
1959 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1960 getControlRoot(), Cond,
1961 DAG.getBasicBlock(Small.BB));
1963 // Insert the false branch.
1964 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1965 DAG.getBasicBlock(Default));
1967 DAG.setRoot(BrCond);
1973 // Rearrange the case blocks so that the last one falls through if possible.
1974 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1975 // The last case block won't fall through into 'NextBlock' if we emit the
1976 // branches in this order. See if rearranging a case value would help.
1977 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1978 if (I->BB == NextBlock) {
1979 std::swap(*I, BackCase);
1985 // Create a CaseBlock record representing a conditional branch to
1986 // the Case's target mbb if the value being switched on SV is equal
1988 MachineBasicBlock *CurBlock = CR.CaseBB;
1989 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1990 MachineBasicBlock *FallThrough;
1992 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1993 CurMF->insert(BBI, FallThrough);
1995 // Put SV in a virtual register to make it available from the new blocks.
1996 ExportFromCurrentBlock(SV);
1998 // If the last case doesn't match, go to the default block.
1999 FallThrough = Default;
2002 const Value *RHS, *LHS, *MHS;
2004 if (I->High == I->Low) {
2005 // This is just small small case range :) containing exactly 1 case
2007 LHS = SV; RHS = I->High; MHS = NULL;
2010 LHS = I->Low; MHS = SV; RHS = I->High;
2013 uint32_t ExtraWeight = I->ExtraWeight;
2014 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2016 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
2018 // If emitting the first comparison, just call visitSwitchCase to emit the
2019 // code into the current block. Otherwise, push the CaseBlock onto the
2020 // vector to be later processed by SDISel, and insert the node's MBB
2021 // before the next MBB.
2022 if (CurBlock == SwitchBB)
2023 visitSwitchCase(CB, SwitchBB);
2025 SwitchCases.push_back(CB);
2027 CurBlock = FallThrough;
2033 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2034 return !TLI.getTargetMachine().Options.DisableJumpTables &&
2035 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2036 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2039 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2040 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2041 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2042 return (LastExt - FirstExt + 1ULL);
2045 /// handleJTSwitchCase - Emit jumptable for current switch case range
2046 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2047 CaseRecVector &WorkList,
2049 MachineBasicBlock *Default,
2050 MachineBasicBlock *SwitchBB) {
2051 Case& FrontCase = *CR.Range.first;
2052 Case& BackCase = *(CR.Range.second-1);
2054 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2055 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2057 APInt TSize(First.getBitWidth(), 0);
2058 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2061 if (!areJTsAllowed(TLI) || TSize.ult(4))
2064 APInt Range = ComputeRange(First, Last);
2065 // The density is TSize / Range. Require at least 40%.
2066 // It should not be possible for IntTSize to saturate for sane code, but make
2067 // sure we handle Range saturation correctly.
2068 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2069 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2070 if (IntTSize * 10 < IntRange * 4)
2073 DEBUG(dbgs() << "Lowering jump table\n"
2074 << "First entry: " << First << ". Last entry: " << Last << '\n'
2075 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2077 // Get the MachineFunction which holds the current MBB. This is used when
2078 // inserting any additional MBBs necessary to represent the switch.
2079 MachineFunction *CurMF = FuncInfo.MF;
2081 // Figure out which block is immediately after the current one.
2082 MachineFunction::iterator BBI = CR.CaseBB;
2085 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2087 // Create a new basic block to hold the code for loading the address
2088 // of the jump table, and jumping to it. Update successor information;
2089 // we will either branch to the default case for the switch, or the jump
2091 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2092 CurMF->insert(BBI, JumpTableBB);
2094 addSuccessorWithWeight(CR.CaseBB, Default);
2095 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2097 // Build a vector of destination BBs, corresponding to each target
2098 // of the jump table. If the value of the jump table slot corresponds to
2099 // a case statement, push the case's BB onto the vector, otherwise, push
2101 std::vector<MachineBasicBlock*> DestBBs;
2103 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2104 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2105 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2107 if (Low.sle(TEI) && TEI.sle(High)) {
2108 DestBBs.push_back(I->BB);
2112 DestBBs.push_back(Default);
2116 // Update successor info. Add one edge to each unique successor.
2117 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2118 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2119 E = DestBBs.end(); I != E; ++I) {
2120 if (!SuccsHandled[(*I)->getNumber()]) {
2121 SuccsHandled[(*I)->getNumber()] = true;
2122 addSuccessorWithWeight(JumpTableBB, *I);
2126 // Create a jump table index for this jump table.
2127 unsigned JTEncoding = TLI.getJumpTableEncoding();
2128 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2129 ->createJumpTableIndex(DestBBs);
2131 // Set the jump table information so that we can codegen it as a second
2132 // MachineBasicBlock
2133 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2134 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2135 if (CR.CaseBB == SwitchBB)
2136 visitJumpTableHeader(JT, JTH, SwitchBB);
2138 JTCases.push_back(JumpTableBlock(JTH, JT));
2142 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2144 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2145 CaseRecVector& WorkList,
2147 MachineBasicBlock *Default,
2148 MachineBasicBlock *SwitchBB) {
2149 // Get the MachineFunction which holds the current MBB. This is used when
2150 // inserting any additional MBBs necessary to represent the switch.
2151 MachineFunction *CurMF = FuncInfo.MF;
2153 // Figure out which block is immediately after the current one.
2154 MachineFunction::iterator BBI = CR.CaseBB;
2157 Case& FrontCase = *CR.Range.first;
2158 Case& BackCase = *(CR.Range.second-1);
2159 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2161 // Size is the number of Cases represented by this range.
2162 unsigned Size = CR.Range.second - CR.Range.first;
2164 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2165 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2167 CaseItr Pivot = CR.Range.first + Size/2;
2169 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2170 // (heuristically) allow us to emit JumpTable's later.
2171 APInt TSize(First.getBitWidth(), 0);
2172 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2176 APInt LSize = FrontCase.size();
2177 APInt RSize = TSize-LSize;
2178 DEBUG(dbgs() << "Selecting best pivot: \n"
2179 << "First: " << First << ", Last: " << Last <<'\n'
2180 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2181 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2183 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2184 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2185 APInt Range = ComputeRange(LEnd, RBegin);
2186 assert((Range - 2ULL).isNonNegative() &&
2187 "Invalid case distance");
2188 // Use volatile double here to avoid excess precision issues on some hosts,
2189 // e.g. that use 80-bit X87 registers.
2190 volatile double LDensity =
2191 (double)LSize.roundToDouble() /
2192 (LEnd - First + 1ULL).roundToDouble();
2193 volatile double RDensity =
2194 (double)RSize.roundToDouble() /
2195 (Last - RBegin + 1ULL).roundToDouble();
2196 double Metric = Range.logBase2()*(LDensity+RDensity);
2197 // Should always split in some non-trivial place
2198 DEBUG(dbgs() <<"=>Step\n"
2199 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2200 << "LDensity: " << LDensity
2201 << ", RDensity: " << RDensity << '\n'
2202 << "Metric: " << Metric << '\n');
2203 if (FMetric < Metric) {
2206 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2212 if (areJTsAllowed(TLI)) {
2213 // If our case is dense we *really* should handle it earlier!
2214 assert((FMetric > 0) && "Should handle dense range earlier!");
2216 Pivot = CR.Range.first + Size/2;
2219 CaseRange LHSR(CR.Range.first, Pivot);
2220 CaseRange RHSR(Pivot, CR.Range.second);
2221 const Constant *C = Pivot->Low;
2222 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2224 // We know that we branch to the LHS if the Value being switched on is
2225 // less than the Pivot value, C. We use this to optimize our binary
2226 // tree a bit, by recognizing that if SV is greater than or equal to the
2227 // LHS's Case Value, and that Case Value is exactly one less than the
2228 // Pivot's Value, then we can branch directly to the LHS's Target,
2229 // rather than creating a leaf node for it.
2230 if ((LHSR.second - LHSR.first) == 1 &&
2231 LHSR.first->High == CR.GE &&
2232 cast<ConstantInt>(C)->getValue() ==
2233 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2234 TrueBB = LHSR.first->BB;
2236 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2237 CurMF->insert(BBI, TrueBB);
2238 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2240 // Put SV in a virtual register to make it available from the new blocks.
2241 ExportFromCurrentBlock(SV);
2244 // Similar to the optimization above, if the Value being switched on is
2245 // known to be less than the Constant CR.LT, and the current Case Value
2246 // is CR.LT - 1, then we can branch directly to the target block for
2247 // the current Case Value, rather than emitting a RHS leaf node for it.
2248 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2249 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2250 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2251 FalseBB = RHSR.first->BB;
2253 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2254 CurMF->insert(BBI, FalseBB);
2255 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2257 // Put SV in a virtual register to make it available from the new blocks.
2258 ExportFromCurrentBlock(SV);
2261 // Create a CaseBlock record representing a conditional branch to
2262 // the LHS node if the value being switched on SV is less than C.
2263 // Otherwise, branch to LHS.
2264 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2266 if (CR.CaseBB == SwitchBB)
2267 visitSwitchCase(CB, SwitchBB);
2269 SwitchCases.push_back(CB);
2274 /// handleBitTestsSwitchCase - if current case range has few destination and
2275 /// range span less, than machine word bitwidth, encode case range into series
2276 /// of masks and emit bit tests with these masks.
2277 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2278 CaseRecVector& WorkList,
2280 MachineBasicBlock* Default,
2281 MachineBasicBlock *SwitchBB){
2282 EVT PTy = TLI.getPointerTy();
2283 unsigned IntPtrBits = PTy.getSizeInBits();
2285 Case& FrontCase = *CR.Range.first;
2286 Case& BackCase = *(CR.Range.second-1);
2288 // Get the MachineFunction which holds the current MBB. This is used when
2289 // inserting any additional MBBs necessary to represent the switch.
2290 MachineFunction *CurMF = FuncInfo.MF;
2292 // If target does not have legal shift left, do not emit bit tests at all.
2293 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2297 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2299 // Single case counts one, case range - two.
2300 numCmps += (I->Low == I->High ? 1 : 2);
2303 // Count unique destinations
2304 SmallSet<MachineBasicBlock*, 4> Dests;
2305 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2306 Dests.insert(I->BB);
2307 if (Dests.size() > 3)
2308 // Don't bother the code below, if there are too much unique destinations
2311 DEBUG(dbgs() << "Total number of unique destinations: "
2312 << Dests.size() << '\n'
2313 << "Total number of comparisons: " << numCmps << '\n');
2315 // Compute span of values.
2316 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2317 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2318 APInt cmpRange = maxValue - minValue;
2320 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2321 << "Low bound: " << minValue << '\n'
2322 << "High bound: " << maxValue << '\n');
2324 if (cmpRange.uge(IntPtrBits) ||
2325 (!(Dests.size() == 1 && numCmps >= 3) &&
2326 !(Dests.size() == 2 && numCmps >= 5) &&
2327 !(Dests.size() >= 3 && numCmps >= 6)))
2330 DEBUG(dbgs() << "Emitting bit tests\n");
2331 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2333 // Optimize the case where all the case values fit in a
2334 // word without having to subtract minValue. In this case,
2335 // we can optimize away the subtraction.
2336 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2337 cmpRange = maxValue;
2339 lowBound = minValue;
2342 CaseBitsVector CasesBits;
2343 unsigned i, count = 0;
2345 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2346 MachineBasicBlock* Dest = I->BB;
2347 for (i = 0; i < count; ++i)
2348 if (Dest == CasesBits[i].BB)
2352 assert((count < 3) && "Too much destinations to test!");
2353 CasesBits.push_back(CaseBits(0, Dest, 0));
2357 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2358 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2360 uint64_t lo = (lowValue - lowBound).getZExtValue();
2361 uint64_t hi = (highValue - lowBound).getZExtValue();
2363 for (uint64_t j = lo; j <= hi; j++) {
2364 CasesBits[i].Mask |= 1ULL << j;
2365 CasesBits[i].Bits++;
2369 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2373 // Figure out which block is immediately after the current one.
2374 MachineFunction::iterator BBI = CR.CaseBB;
2377 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2379 DEBUG(dbgs() << "Cases:\n");
2380 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2381 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2382 << ", Bits: " << CasesBits[i].Bits
2383 << ", BB: " << CasesBits[i].BB << '\n');
2385 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2386 CurMF->insert(BBI, CaseBB);
2387 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2391 // Put SV in a virtual register to make it available from the new blocks.
2392 ExportFromCurrentBlock(SV);
2395 BitTestBlock BTB(lowBound, cmpRange, SV,
2396 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2397 CR.CaseBB, Default, BTC);
2399 if (CR.CaseBB == SwitchBB)
2400 visitBitTestHeader(BTB, SwitchBB);
2402 BitTestCases.push_back(BTB);
2407 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2408 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2409 const SwitchInst& SI) {
2412 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2413 // Start with "simple" cases
2414 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2416 const BasicBlock *SuccBB = i.getCaseSuccessor();
2417 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2419 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0;
2421 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2422 SMBB, ExtraWeight));
2424 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2426 // Merge case into clusters
2427 if (Cases.size() >= 2)
2428 // Must recompute end() each iteration because it may be
2429 // invalidated by erase if we hold on to it
2430 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2431 J != Cases.end(); ) {
2432 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2433 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2434 MachineBasicBlock* nextBB = J->BB;
2435 MachineBasicBlock* currentBB = I->BB;
2437 // If the two neighboring cases go to the same destination, merge them
2438 // into a single case.
2439 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2443 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) {
2444 uint32_t CurWeight = currentBB->getBasicBlock() ?
2445 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16;
2446 uint32_t NextWeight = nextBB->getBasicBlock() ?
2447 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16;
2449 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(),
2450 CurWeight + NextWeight);
2457 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2458 if (I->Low != I->High)
2459 // A range counts double, since it requires two compares.
2466 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2467 MachineBasicBlock *Last) {
2469 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2470 if (JTCases[i].first.HeaderBB == First)
2471 JTCases[i].first.HeaderBB = Last;
2473 // Update BitTestCases.
2474 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2475 if (BitTestCases[i].Parent == First)
2476 BitTestCases[i].Parent = Last;
2479 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2480 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2482 // Figure out which block is immediately after the current one.
2483 MachineBasicBlock *NextBlock = 0;
2484 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2486 // If there is only the default destination, branch to it if it is not the
2487 // next basic block. Otherwise, just fall through.
2488 if (!SI.getNumCases()) {
2489 // Update machine-CFG edges.
2491 // If this is not a fall-through branch, emit the branch.
2492 SwitchMBB->addSuccessor(Default);
2493 if (Default != NextBlock)
2494 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2495 MVT::Other, getControlRoot(),
2496 DAG.getBasicBlock(Default)));
2501 // If there are any non-default case statements, create a vector of Cases
2502 // representing each one, and sort the vector so that we can efficiently
2503 // create a binary search tree from them.
2505 size_t numCmps = Clusterify(Cases, SI);
2506 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2507 << ". Total compares: " << numCmps << '\n');
2510 // Get the Value to be switched on and default basic blocks, which will be
2511 // inserted into CaseBlock records, representing basic blocks in the binary
2513 const Value *SV = SI.getCondition();
2515 // Push the initial CaseRec onto the worklist
2516 CaseRecVector WorkList;
2517 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2518 CaseRange(Cases.begin(),Cases.end())));
2520 while (!WorkList.empty()) {
2521 // Grab a record representing a case range to process off the worklist
2522 CaseRec CR = WorkList.back();
2523 WorkList.pop_back();
2525 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2528 // If the range has few cases (two or less) emit a series of specific
2530 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2533 // If the switch has more than 5 blocks, and at least 40% dense, and the
2534 // target supports indirect branches, then emit a jump table rather than
2535 // lowering the switch to a binary tree of conditional branches.
2536 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2539 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2540 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2541 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2545 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2546 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2548 // Update machine-CFG edges with unique successors.
2549 SmallVector<BasicBlock*, 32> succs;
2550 succs.reserve(I.getNumSuccessors());
2551 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2552 succs.push_back(I.getSuccessor(i));
2553 array_pod_sort(succs.begin(), succs.end());
2554 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2555 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2556 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2557 addSuccessorWithWeight(IndirectBrMBB, Succ);
2560 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2561 MVT::Other, getControlRoot(),
2562 getValue(I.getAddress())));
2565 void SelectionDAGBuilder::visitFSub(const User &I) {
2566 // -0.0 - X --> fneg
2567 Type *Ty = I.getType();
2568 if (isa<Constant>(I.getOperand(0)) &&
2569 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2570 SDValue Op2 = getValue(I.getOperand(1));
2571 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2572 Op2.getValueType(), Op2));
2576 visitBinary(I, ISD::FSUB);
2579 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2580 SDValue Op1 = getValue(I.getOperand(0));
2581 SDValue Op2 = getValue(I.getOperand(1));
2582 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2583 Op1.getValueType(), Op1, Op2));
2586 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2587 SDValue Op1 = getValue(I.getOperand(0));
2588 SDValue Op2 = getValue(I.getOperand(1));
2590 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2592 // Coerce the shift amount to the right type if we can.
2593 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2594 unsigned ShiftSize = ShiftTy.getSizeInBits();
2595 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2596 DebugLoc DL = getCurDebugLoc();
2598 // If the operand is smaller than the shift count type, promote it.
2599 if (ShiftSize > Op2Size)
2600 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2602 // If the operand is larger than the shift count type but the shift
2603 // count type has enough bits to represent any shift value, truncate
2604 // it now. This is a common case and it exposes the truncate to
2605 // optimization early.
2606 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2607 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2608 // Otherwise we'll need to temporarily settle for some other convenient
2609 // type. Type legalization will make adjustments once the shiftee is split.
2611 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2614 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2615 Op1.getValueType(), Op1, Op2));
2618 void SelectionDAGBuilder::visitSDiv(const User &I) {
2619 SDValue Op1 = getValue(I.getOperand(0));
2620 SDValue Op2 = getValue(I.getOperand(1));
2622 // Turn exact SDivs into multiplications.
2623 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2625 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2626 !isa<ConstantSDNode>(Op1) &&
2627 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2628 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2630 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2634 void SelectionDAGBuilder::visitICmp(const User &I) {
2635 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2636 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2637 predicate = IC->getPredicate();
2638 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2639 predicate = ICmpInst::Predicate(IC->getPredicate());
2640 SDValue Op1 = getValue(I.getOperand(0));
2641 SDValue Op2 = getValue(I.getOperand(1));
2642 ISD::CondCode Opcode = getICmpCondCode(predicate);
2644 EVT DestVT = TLI.getValueType(I.getType());
2645 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2648 void SelectionDAGBuilder::visitFCmp(const User &I) {
2649 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2650 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2651 predicate = FC->getPredicate();
2652 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2653 predicate = FCmpInst::Predicate(FC->getPredicate());
2654 SDValue Op1 = getValue(I.getOperand(0));
2655 SDValue Op2 = getValue(I.getOperand(1));
2656 ISD::CondCode Condition = getFCmpCondCode(predicate);
2657 if (TM.Options.NoNaNsFPMath)
2658 Condition = getFCmpCodeWithoutNaN(Condition);
2659 EVT DestVT = TLI.getValueType(I.getType());
2660 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2663 void SelectionDAGBuilder::visitSelect(const User &I) {
2664 SmallVector<EVT, 4> ValueVTs;
2665 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2666 unsigned NumValues = ValueVTs.size();
2667 if (NumValues == 0) return;
2669 SmallVector<SDValue, 4> Values(NumValues);
2670 SDValue Cond = getValue(I.getOperand(0));
2671 SDValue TrueVal = getValue(I.getOperand(1));
2672 SDValue FalseVal = getValue(I.getOperand(2));
2673 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2674 ISD::VSELECT : ISD::SELECT;
2676 for (unsigned i = 0; i != NumValues; ++i)
2677 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2678 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2680 SDValue(TrueVal.getNode(),
2681 TrueVal.getResNo() + i),
2682 SDValue(FalseVal.getNode(),
2683 FalseVal.getResNo() + i));
2685 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2686 DAG.getVTList(&ValueVTs[0], NumValues),
2687 &Values[0], NumValues));
2690 void SelectionDAGBuilder::visitTrunc(const User &I) {
2691 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2692 SDValue N = getValue(I.getOperand(0));
2693 EVT DestVT = TLI.getValueType(I.getType());
2694 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2697 void SelectionDAGBuilder::visitZExt(const User &I) {
2698 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2699 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2700 SDValue N = getValue(I.getOperand(0));
2701 EVT DestVT = TLI.getValueType(I.getType());
2702 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2705 void SelectionDAGBuilder::visitSExt(const User &I) {
2706 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2707 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2708 SDValue N = getValue(I.getOperand(0));
2709 EVT DestVT = TLI.getValueType(I.getType());
2710 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2713 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2714 // FPTrunc is never a no-op cast, no need to check
2715 SDValue N = getValue(I.getOperand(0));
2716 EVT DestVT = TLI.getValueType(I.getType());
2717 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2719 DAG.getTargetConstant(0, TLI.getPointerTy())));
2722 void SelectionDAGBuilder::visitFPExt(const User &I){
2723 // FPExt is never a no-op cast, no need to check
2724 SDValue N = getValue(I.getOperand(0));
2725 EVT DestVT = TLI.getValueType(I.getType());
2726 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2729 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2730 // FPToUI is never a no-op cast, no need to check
2731 SDValue N = getValue(I.getOperand(0));
2732 EVT DestVT = TLI.getValueType(I.getType());
2733 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2736 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2737 // FPToSI is never a no-op cast, no need to check
2738 SDValue N = getValue(I.getOperand(0));
2739 EVT DestVT = TLI.getValueType(I.getType());
2740 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2743 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2744 // UIToFP is never a no-op cast, no need to check
2745 SDValue N = getValue(I.getOperand(0));
2746 EVT DestVT = TLI.getValueType(I.getType());
2747 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2750 void SelectionDAGBuilder::visitSIToFP(const User &I){
2751 // SIToFP is never a no-op cast, no need to check
2752 SDValue N = getValue(I.getOperand(0));
2753 EVT DestVT = TLI.getValueType(I.getType());
2754 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2757 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2758 // What to do depends on the size of the integer and the size of the pointer.
2759 // We can either truncate, zero extend, or no-op, accordingly.
2760 SDValue N = getValue(I.getOperand(0));
2761 EVT DestVT = TLI.getValueType(I.getType());
2762 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2765 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2766 // What to do depends on the size of the integer and the size of the pointer.
2767 // We can either truncate, zero extend, or no-op, accordingly.
2768 SDValue N = getValue(I.getOperand(0));
2769 EVT DestVT = TLI.getValueType(I.getType());
2770 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2773 void SelectionDAGBuilder::visitBitCast(const User &I) {
2774 SDValue N = getValue(I.getOperand(0));
2775 EVT DestVT = TLI.getValueType(I.getType());
2777 // BitCast assures us that source and destination are the same size so this is
2778 // either a BITCAST or a no-op.
2779 if (DestVT != N.getValueType())
2780 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2781 DestVT, N)); // convert types.
2783 setValue(&I, N); // noop cast.
2786 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2787 SDValue InVec = getValue(I.getOperand(0));
2788 SDValue InVal = getValue(I.getOperand(1));
2789 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2791 getValue(I.getOperand(2)));
2792 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2793 TLI.getValueType(I.getType()),
2794 InVec, InVal, InIdx));
2797 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2798 SDValue InVec = getValue(I.getOperand(0));
2799 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2801 getValue(I.getOperand(1)));
2802 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2803 TLI.getValueType(I.getType()), InVec, InIdx));
2806 // Utility for visitShuffleVector - Return true if every element in Mask,
2807 // begining from position Pos and ending in Pos+Size, falls within the
2808 // specified sequential range [L, L+Pos). or is undef.
2809 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2810 unsigned Pos, unsigned Size, int Low) {
2811 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2812 if (Mask[i] >= 0 && Mask[i] != Low)
2817 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2818 SDValue Src1 = getValue(I.getOperand(0));
2819 SDValue Src2 = getValue(I.getOperand(1));
2821 SmallVector<int, 8> Mask;
2822 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2823 unsigned MaskNumElts = Mask.size();
2825 EVT VT = TLI.getValueType(I.getType());
2826 EVT SrcVT = Src1.getValueType();
2827 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2829 if (SrcNumElts == MaskNumElts) {
2830 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2835 // Normalize the shuffle vector since mask and vector length don't match.
2836 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2837 // Mask is longer than the source vectors and is a multiple of the source
2838 // vectors. We can use concatenate vector to make the mask and vectors
2840 if (SrcNumElts*2 == MaskNumElts) {
2841 // First check for Src1 in low and Src2 in high
2842 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2843 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2844 // The shuffle is concatenating two vectors together.
2845 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2849 // Then check for Src2 in low and Src1 in high
2850 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2851 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2852 // The shuffle is concatenating two vectors together.
2853 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2859 // Pad both vectors with undefs to make them the same length as the mask.
2860 unsigned NumConcat = MaskNumElts / SrcNumElts;
2861 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2862 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2863 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2865 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2866 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2870 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2871 getCurDebugLoc(), VT,
2872 &MOps1[0], NumConcat);
2873 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2874 getCurDebugLoc(), VT,
2875 &MOps2[0], NumConcat);
2877 // Readjust mask for new input vector length.
2878 SmallVector<int, 8> MappedOps;
2879 for (unsigned i = 0; i != MaskNumElts; ++i) {
2881 if (Idx >= (int)SrcNumElts)
2882 Idx -= SrcNumElts - MaskNumElts;
2883 MappedOps.push_back(Idx);
2886 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2891 if (SrcNumElts > MaskNumElts) {
2892 // Analyze the access pattern of the vector to see if we can extract
2893 // two subvectors and do the shuffle. The analysis is done by calculating
2894 // the range of elements the mask access on both vectors.
2895 int MinRange[2] = { static_cast<int>(SrcNumElts),
2896 static_cast<int>(SrcNumElts)};
2897 int MaxRange[2] = {-1, -1};
2899 for (unsigned i = 0; i != MaskNumElts; ++i) {
2905 if (Idx >= (int)SrcNumElts) {
2909 if (Idx > MaxRange[Input])
2910 MaxRange[Input] = Idx;
2911 if (Idx < MinRange[Input])
2912 MinRange[Input] = Idx;
2915 // Check if the access is smaller than the vector size and can we find
2916 // a reasonable extract index.
2917 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2919 int StartIdx[2]; // StartIdx to extract from
2920 for (unsigned Input = 0; Input < 2; ++Input) {
2921 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2922 RangeUse[Input] = 0; // Unused
2923 StartIdx[Input] = 0;
2927 // Find a good start index that is a multiple of the mask length. Then
2928 // see if the rest of the elements are in range.
2929 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2930 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2931 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2932 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2935 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2936 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2939 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2940 // Extract appropriate subvector and generate a vector shuffle
2941 for (unsigned Input = 0; Input < 2; ++Input) {
2942 SDValue &Src = Input == 0 ? Src1 : Src2;
2943 if (RangeUse[Input] == 0)
2944 Src = DAG.getUNDEF(VT);
2946 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2947 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2950 // Calculate new mask.
2951 SmallVector<int, 8> MappedOps;
2952 for (unsigned i = 0; i != MaskNumElts; ++i) {
2955 if (Idx < (int)SrcNumElts)
2958 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2960 MappedOps.push_back(Idx);
2963 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2969 // We can't use either concat vectors or extract subvectors so fall back to
2970 // replacing the shuffle with extract and build vector.
2971 // to insert and build vector.
2972 EVT EltVT = VT.getVectorElementType();
2973 EVT PtrVT = TLI.getPointerTy();
2974 SmallVector<SDValue,8> Ops;
2975 for (unsigned i = 0; i != MaskNumElts; ++i) {
2980 Res = DAG.getUNDEF(EltVT);
2982 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2983 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2985 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2986 EltVT, Src, DAG.getConstant(Idx, PtrVT));
2992 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2993 VT, &Ops[0], Ops.size()));
2996 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2997 const Value *Op0 = I.getOperand(0);
2998 const Value *Op1 = I.getOperand(1);
2999 Type *AggTy = I.getType();
3000 Type *ValTy = Op1->getType();
3001 bool IntoUndef = isa<UndefValue>(Op0);
3002 bool FromUndef = isa<UndefValue>(Op1);
3004 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3006 SmallVector<EVT, 4> AggValueVTs;
3007 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3008 SmallVector<EVT, 4> ValValueVTs;
3009 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3011 unsigned NumAggValues = AggValueVTs.size();
3012 unsigned NumValValues = ValValueVTs.size();
3013 SmallVector<SDValue, 4> Values(NumAggValues);
3015 SDValue Agg = getValue(Op0);
3017 // Copy the beginning value(s) from the original aggregate.
3018 for (; i != LinearIndex; ++i)
3019 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3020 SDValue(Agg.getNode(), Agg.getResNo() + i);
3021 // Copy values from the inserted value(s).
3023 SDValue Val = getValue(Op1);
3024 for (; i != LinearIndex + NumValValues; ++i)
3025 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3026 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3028 // Copy remaining value(s) from the original aggregate.
3029 for (; i != NumAggValues; ++i)
3030 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3031 SDValue(Agg.getNode(), Agg.getResNo() + i);
3033 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3034 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3035 &Values[0], NumAggValues));
3038 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3039 const Value *Op0 = I.getOperand(0);
3040 Type *AggTy = Op0->getType();
3041 Type *ValTy = I.getType();
3042 bool OutOfUndef = isa<UndefValue>(Op0);
3044 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3046 SmallVector<EVT, 4> ValValueVTs;
3047 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3049 unsigned NumValValues = ValValueVTs.size();
3051 // Ignore a extractvalue that produces an empty object
3052 if (!NumValValues) {
3053 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3057 SmallVector<SDValue, 4> Values(NumValValues);
3059 SDValue Agg = getValue(Op0);
3060 // Copy out the selected value(s).
3061 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3062 Values[i - LinearIndex] =
3064 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3065 SDValue(Agg.getNode(), Agg.getResNo() + i);
3067 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3068 DAG.getVTList(&ValValueVTs[0], NumValValues),
3069 &Values[0], NumValValues));
3072 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3073 SDValue N = getValue(I.getOperand(0));
3074 // Note that the pointer operand may be a vector of pointers. Take the scalar
3075 // element which holds a pointer.
3076 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3078 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3080 const Value *Idx = *OI;
3081 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3082 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3085 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3086 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3087 DAG.getIntPtrConstant(Offset));
3090 Ty = StTy->getElementType(Field);
3092 Ty = cast<SequentialType>(Ty)->getElementType();
3094 // If this is a constant subscript, handle it quickly.
3095 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3096 if (CI->isZero()) continue;
3098 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3100 EVT PTy = TLI.getPointerTy();
3101 unsigned PtrBits = PTy.getSizeInBits();
3103 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3105 DAG.getConstant(Offs, MVT::i64));
3107 OffsVal = DAG.getIntPtrConstant(Offs);
3109 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3114 // N = N + Idx * ElementSize;
3115 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3116 TD->getTypeAllocSize(Ty));
3117 SDValue IdxN = getValue(Idx);
3119 // If the index is smaller or larger than intptr_t, truncate or extend
3121 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3123 // If this is a multiply by a power of two, turn it into a shl
3124 // immediately. This is a very common case.
3125 if (ElementSize != 1) {
3126 if (ElementSize.isPowerOf2()) {
3127 unsigned Amt = ElementSize.logBase2();
3128 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3129 N.getValueType(), IdxN,
3130 DAG.getConstant(Amt, IdxN.getValueType()));
3132 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3133 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3134 N.getValueType(), IdxN, Scale);
3138 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3139 N.getValueType(), N, IdxN);
3146 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3147 // If this is a fixed sized alloca in the entry block of the function,
3148 // allocate it statically on the stack.
3149 if (FuncInfo.StaticAllocaMap.count(&I))
3150 return; // getValue will auto-populate this.
3152 Type *Ty = I.getAllocatedType();
3153 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3155 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3158 SDValue AllocSize = getValue(I.getArraySize());
3160 EVT IntPtr = TLI.getPointerTy();
3161 if (AllocSize.getValueType() != IntPtr)
3162 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3164 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3166 DAG.getConstant(TySize, IntPtr));
3168 // Handle alignment. If the requested alignment is less than or equal to
3169 // the stack alignment, ignore it. If the size is greater than or equal to
3170 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3171 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3172 if (Align <= StackAlign)
3175 // Round the size of the allocation up to the stack alignment size
3176 // by add SA-1 to the size.
3177 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3178 AllocSize.getValueType(), AllocSize,
3179 DAG.getIntPtrConstant(StackAlign-1));
3181 // Mask out the low bits for alignment purposes.
3182 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3183 AllocSize.getValueType(), AllocSize,
3184 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3186 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3187 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3188 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3191 DAG.setRoot(DSA.getValue(1));
3193 // Inform the Frame Information that we have just allocated a variable-sized
3195 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3198 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3200 return visitAtomicLoad(I);
3202 const Value *SV = I.getOperand(0);
3203 SDValue Ptr = getValue(SV);
3205 Type *Ty = I.getType();
3207 bool isVolatile = I.isVolatile();
3208 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3209 bool isInvariant = I.getMetadata("invariant.load") != 0;
3210 unsigned Alignment = I.getAlignment();
3211 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3212 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3214 SmallVector<EVT, 4> ValueVTs;
3215 SmallVector<uint64_t, 4> Offsets;
3216 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3217 unsigned NumValues = ValueVTs.size();
3222 bool ConstantMemory = false;
3223 if (I.isVolatile() || NumValues > MaxParallelChains)
3224 // Serialize volatile loads with other side effects.
3226 else if (AA->pointsToConstantMemory(
3227 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3228 // Do not serialize (non-volatile) loads of constant memory with anything.
3229 Root = DAG.getEntryNode();
3230 ConstantMemory = true;
3232 // Do not serialize non-volatile loads against each other.
3233 Root = DAG.getRoot();
3236 SmallVector<SDValue, 4> Values(NumValues);
3237 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3239 EVT PtrVT = Ptr.getValueType();
3240 unsigned ChainI = 0;
3241 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3242 // Serializing loads here may result in excessive register pressure, and
3243 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3244 // could recover a bit by hoisting nodes upward in the chain by recognizing
3245 // they are side-effect free or do not alias. The optimizer should really
3246 // avoid this case by converting large object/array copies to llvm.memcpy
3247 // (MaxParallelChains should always remain as failsafe).
3248 if (ChainI == MaxParallelChains) {
3249 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3250 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3251 MVT::Other, &Chains[0], ChainI);
3255 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3257 DAG.getConstant(Offsets[i], PtrVT));
3258 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3259 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3260 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3264 Chains[ChainI] = L.getValue(1);
3267 if (!ConstantMemory) {
3268 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3269 MVT::Other, &Chains[0], ChainI);
3273 PendingLoads.push_back(Chain);
3276 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3277 DAG.getVTList(&ValueVTs[0], NumValues),
3278 &Values[0], NumValues));
3281 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3283 return visitAtomicStore(I);
3285 const Value *SrcV = I.getOperand(0);
3286 const Value *PtrV = I.getOperand(1);
3288 SmallVector<EVT, 4> ValueVTs;
3289 SmallVector<uint64_t, 4> Offsets;
3290 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3291 unsigned NumValues = ValueVTs.size();
3295 // Get the lowered operands. Note that we do this after
3296 // checking if NumResults is zero, because with zero results
3297 // the operands won't have values in the map.
3298 SDValue Src = getValue(SrcV);
3299 SDValue Ptr = getValue(PtrV);
3301 SDValue Root = getRoot();
3302 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3304 EVT PtrVT = Ptr.getValueType();
3305 bool isVolatile = I.isVolatile();
3306 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3307 unsigned Alignment = I.getAlignment();
3308 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3310 unsigned ChainI = 0;
3311 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3312 // See visitLoad comments.
3313 if (ChainI == MaxParallelChains) {
3314 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3315 MVT::Other, &Chains[0], ChainI);
3319 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3320 DAG.getConstant(Offsets[i], PtrVT));
3321 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3322 SDValue(Src.getNode(), Src.getResNo() + i),
3323 Add, MachinePointerInfo(PtrV, Offsets[i]),
3324 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3325 Chains[ChainI] = St;
3328 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3329 MVT::Other, &Chains[0], ChainI);
3331 AssignOrderingToNode(StoreNode.getNode());
3332 DAG.setRoot(StoreNode);
3335 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3336 SynchronizationScope Scope,
3337 bool Before, DebugLoc dl,
3339 const TargetLowering &TLI) {
3340 // Fence, if necessary
3342 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3344 else if (Order == Acquire || Order == Monotonic)
3347 if (Order == AcquireRelease)
3349 else if (Order == Release || Order == Monotonic)
3354 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3355 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3356 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3359 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3360 DebugLoc dl = getCurDebugLoc();
3361 AtomicOrdering Order = I.getOrdering();
3362 SynchronizationScope Scope = I.getSynchScope();
3364 SDValue InChain = getRoot();
3366 if (TLI.getInsertFencesForAtomic())
3367 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3371 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3372 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3374 getValue(I.getPointerOperand()),
3375 getValue(I.getCompareOperand()),
3376 getValue(I.getNewValOperand()),
3377 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3378 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3381 SDValue OutChain = L.getValue(1);
3383 if (TLI.getInsertFencesForAtomic())
3384 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3388 DAG.setRoot(OutChain);
3391 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3392 DebugLoc dl = getCurDebugLoc();
3394 switch (I.getOperation()) {
3395 default: llvm_unreachable("Unknown atomicrmw operation");
3396 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3397 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3398 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3399 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3400 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3401 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3402 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3403 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3404 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3405 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3406 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3408 AtomicOrdering Order = I.getOrdering();
3409 SynchronizationScope Scope = I.getSynchScope();
3411 SDValue InChain = getRoot();
3413 if (TLI.getInsertFencesForAtomic())
3414 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3418 DAG.getAtomic(NT, dl,
3419 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3421 getValue(I.getPointerOperand()),
3422 getValue(I.getValOperand()),
3423 I.getPointerOperand(), 0 /* Alignment */,
3424 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3427 SDValue OutChain = L.getValue(1);
3429 if (TLI.getInsertFencesForAtomic())
3430 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3434 DAG.setRoot(OutChain);
3437 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3438 DebugLoc dl = getCurDebugLoc();
3441 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3442 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3443 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3446 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3447 DebugLoc dl = getCurDebugLoc();
3448 AtomicOrdering Order = I.getOrdering();
3449 SynchronizationScope Scope = I.getSynchScope();
3451 SDValue InChain = getRoot();
3453 EVT VT = EVT::getEVT(I.getType());
3455 if (I.getAlignment() * 8 < VT.getSizeInBits())
3456 report_fatal_error("Cannot generate unaligned atomic load");
3459 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3460 getValue(I.getPointerOperand()),
3461 I.getPointerOperand(), I.getAlignment(),
3462 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3465 SDValue OutChain = L.getValue(1);
3467 if (TLI.getInsertFencesForAtomic())
3468 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3472 DAG.setRoot(OutChain);
3475 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3476 DebugLoc dl = getCurDebugLoc();
3478 AtomicOrdering Order = I.getOrdering();
3479 SynchronizationScope Scope = I.getSynchScope();
3481 SDValue InChain = getRoot();
3483 EVT VT = EVT::getEVT(I.getValueOperand()->getType());
3485 if (I.getAlignment() * 8 < VT.getSizeInBits())
3486 report_fatal_error("Cannot generate unaligned atomic store");
3488 if (TLI.getInsertFencesForAtomic())
3489 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3493 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3495 getValue(I.getPointerOperand()),
3496 getValue(I.getValueOperand()),
3497 I.getPointerOperand(), I.getAlignment(),
3498 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3501 if (TLI.getInsertFencesForAtomic())
3502 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3505 DAG.setRoot(OutChain);
3508 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3510 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3511 unsigned Intrinsic) {
3512 bool HasChain = !I.doesNotAccessMemory();
3513 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3515 // Build the operand list.
3516 SmallVector<SDValue, 8> Ops;
3517 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3519 // We don't need to serialize loads against other loads.
3520 Ops.push_back(DAG.getRoot());
3522 Ops.push_back(getRoot());
3526 // Info is set by getTgtMemInstrinsic
3527 TargetLowering::IntrinsicInfo Info;
3528 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3530 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3531 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3532 Info.opc == ISD::INTRINSIC_W_CHAIN)
3533 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3535 // Add all operands of the call to the operand list.
3536 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3537 SDValue Op = getValue(I.getArgOperand(i));
3541 SmallVector<EVT, 4> ValueVTs;
3542 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3545 ValueVTs.push_back(MVT::Other);
3547 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3551 if (IsTgtIntrinsic) {
3552 // This is target intrinsic that touches memory
3553 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3554 VTs, &Ops[0], Ops.size(),
3556 MachinePointerInfo(Info.ptrVal, Info.offset),
3557 Info.align, Info.vol,
3558 Info.readMem, Info.writeMem);
3559 } else if (!HasChain) {
3560 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3561 VTs, &Ops[0], Ops.size());
3562 } else if (!I.getType()->isVoidTy()) {
3563 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3564 VTs, &Ops[0], Ops.size());
3566 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3567 VTs, &Ops[0], Ops.size());
3571 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3573 PendingLoads.push_back(Chain);
3578 if (!I.getType()->isVoidTy()) {
3579 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3580 EVT VT = TLI.getValueType(PTy);
3581 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3584 setValue(&I, Result);
3586 // Assign order to result here. If the intrinsic does not produce a result,
3587 // it won't be mapped to a SDNode and visit() will not assign it an order
3590 AssignOrderingToNode(Result.getNode());
3594 /// GetSignificand - Get the significand and build it into a floating-point
3595 /// number with exponent of 1:
3597 /// Op = (Op & 0x007fffff) | 0x3f800000;
3599 /// where Op is the hexidecimal representation of floating point value.
3601 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3602 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3603 DAG.getConstant(0x007fffff, MVT::i32));
3604 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3605 DAG.getConstant(0x3f800000, MVT::i32));
3606 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3609 /// GetExponent - Get the exponent:
3611 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3613 /// where Op is the hexidecimal representation of floating point value.
3615 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3617 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3618 DAG.getConstant(0x7f800000, MVT::i32));
3619 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3620 DAG.getConstant(23, TLI.getPointerTy()));
3621 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3622 DAG.getConstant(127, MVT::i32));
3623 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3626 /// getF32Constant - Get 32-bit floating point constant.
3628 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3629 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3632 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3633 /// limited-precision mode.
3635 SelectionDAGBuilder::visitExp(const CallInst &I) {
3637 DebugLoc dl = getCurDebugLoc();
3639 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3640 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3641 SDValue Op = getValue(I.getArgOperand(0));
3643 // Put the exponent in the right bit position for later addition to the
3646 // #define LOG2OFe 1.4426950f
3647 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3648 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3649 getF32Constant(DAG, 0x3fb8aa3b));
3650 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3652 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3653 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3654 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3656 // IntegerPartOfX <<= 23;
3657 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3658 DAG.getConstant(23, TLI.getPointerTy()));
3660 if (LimitFloatPrecision <= 6) {
3661 // For floating-point precision of 6:
3663 // TwoToFractionalPartOfX =
3665 // (0.735607626f + 0.252464424f * x) * x;
3667 // error 0.0144103317, which is 6 bits
3668 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3669 getF32Constant(DAG, 0x3e814304));
3670 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3671 getF32Constant(DAG, 0x3f3c50c8));
3672 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3673 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3674 getF32Constant(DAG, 0x3f7f5e7e));
3675 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3677 // Add the exponent into the result in integer domain.
3678 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3679 TwoToFracPartOfX, IntegerPartOfX);
3681 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3682 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3683 // For floating-point precision of 12:
3685 // TwoToFractionalPartOfX =
3688 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3690 // 0.000107046256 error, which is 13 to 14 bits
3691 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3692 getF32Constant(DAG, 0x3da235e3));
3693 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3694 getF32Constant(DAG, 0x3e65b8f3));
3695 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3696 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3697 getF32Constant(DAG, 0x3f324b07));
3698 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3699 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3700 getF32Constant(DAG, 0x3f7ff8fd));
3701 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3703 // Add the exponent into the result in integer domain.
3704 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3705 TwoToFracPartOfX, IntegerPartOfX);
3707 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3708 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3709 // For floating-point precision of 18:
3711 // TwoToFractionalPartOfX =
3715 // (0.554906021e-1f +
3716 // (0.961591928e-2f +
3717 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3719 // error 2.47208000*10^(-7), which is better than 18 bits
3720 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3721 getF32Constant(DAG, 0x3924b03e));
3722 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3723 getF32Constant(DAG, 0x3ab24b87));
3724 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3725 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3726 getF32Constant(DAG, 0x3c1d8c17));
3727 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3728 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3729 getF32Constant(DAG, 0x3d634a1d));
3730 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3731 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3732 getF32Constant(DAG, 0x3e75fe14));
3733 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3734 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3735 getF32Constant(DAG, 0x3f317234));
3736 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3737 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3738 getF32Constant(DAG, 0x3f800000));
3739 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3742 // Add the exponent into the result in integer domain.
3743 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3744 TwoToFracPartOfX, IntegerPartOfX);
3746 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3749 // No special expansion.
3750 result = DAG.getNode(ISD::FEXP, dl,
3751 getValue(I.getArgOperand(0)).getValueType(),
3752 getValue(I.getArgOperand(0)));
3755 setValue(&I, result);
3758 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3759 /// limited-precision mode.
3761 SelectionDAGBuilder::visitLog(const CallInst &I) {
3763 DebugLoc dl = getCurDebugLoc();
3765 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3766 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3767 SDValue Op = getValue(I.getArgOperand(0));
3768 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3770 // Scale the exponent by log(2) [0.69314718f].
3771 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3772 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3773 getF32Constant(DAG, 0x3f317218));
3775 // Get the significand and build it into a floating-point number with
3777 SDValue X = GetSignificand(DAG, Op1, dl);
3779 if (LimitFloatPrecision <= 6) {
3780 // For floating-point precision of 6:
3784 // (1.4034025f - 0.23903021f * x) * x;
3786 // error 0.0034276066, which is better than 8 bits
3787 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3788 getF32Constant(DAG, 0xbe74c456));
3789 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3790 getF32Constant(DAG, 0x3fb3a2b1));
3791 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3792 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3793 getF32Constant(DAG, 0x3f949a29));
3795 result = DAG.getNode(ISD::FADD, dl,
3796 MVT::f32, LogOfExponent, LogOfMantissa);
3797 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3798 // For floating-point precision of 12:
3804 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3806 // error 0.000061011436, which is 14 bits
3807 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3808 getF32Constant(DAG, 0xbd67b6d6));
3809 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3810 getF32Constant(DAG, 0x3ee4f4b8));
3811 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3812 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3813 getF32Constant(DAG, 0x3fbc278b));
3814 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3815 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3816 getF32Constant(DAG, 0x40348e95));
3817 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3818 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3819 getF32Constant(DAG, 0x3fdef31a));
3821 result = DAG.getNode(ISD::FADD, dl,
3822 MVT::f32, LogOfExponent, LogOfMantissa);
3823 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3824 // For floating-point precision of 18:
3832 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3834 // error 0.0000023660568, which is better than 18 bits
3835 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3836 getF32Constant(DAG, 0xbc91e5ac));
3837 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3838 getF32Constant(DAG, 0x3e4350aa));
3839 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3840 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3841 getF32Constant(DAG, 0x3f60d3e3));
3842 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3843 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3844 getF32Constant(DAG, 0x4011cdf0));
3845 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3846 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3847 getF32Constant(DAG, 0x406cfd1c));
3848 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3849 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3850 getF32Constant(DAG, 0x408797cb));
3851 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3852 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3853 getF32Constant(DAG, 0x4006dcab));
3855 result = DAG.getNode(ISD::FADD, dl,
3856 MVT::f32, LogOfExponent, LogOfMantissa);
3859 // No special expansion.
3860 result = DAG.getNode(ISD::FLOG, dl,
3861 getValue(I.getArgOperand(0)).getValueType(),
3862 getValue(I.getArgOperand(0)));
3865 setValue(&I, result);
3868 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3869 /// limited-precision mode.
3871 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3873 DebugLoc dl = getCurDebugLoc();
3875 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3876 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3877 SDValue Op = getValue(I.getArgOperand(0));
3878 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3880 // Get the exponent.
3881 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3883 // Get the significand and build it into a floating-point number with
3885 SDValue X = GetSignificand(DAG, Op1, dl);
3887 // Different possible minimax approximations of significand in
3888 // floating-point for various degrees of accuracy over [1,2].
3889 if (LimitFloatPrecision <= 6) {
3890 // For floating-point precision of 6:
3892 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3894 // error 0.0049451742, which is more than 7 bits
3895 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3896 getF32Constant(DAG, 0xbeb08fe0));
3897 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3898 getF32Constant(DAG, 0x40019463));
3899 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3900 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3901 getF32Constant(DAG, 0x3fd6633d));
3903 result = DAG.getNode(ISD::FADD, dl,
3904 MVT::f32, LogOfExponent, Log2ofMantissa);
3905 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3906 // For floating-point precision of 12:
3912 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3914 // error 0.0000876136000, which is better than 13 bits
3915 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3916 getF32Constant(DAG, 0xbda7262e));
3917 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3918 getF32Constant(DAG, 0x3f25280b));
3919 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3920 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3921 getF32Constant(DAG, 0x4007b923));
3922 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3923 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3924 getF32Constant(DAG, 0x40823e2f));
3925 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3926 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3927 getF32Constant(DAG, 0x4020d29c));
3929 result = DAG.getNode(ISD::FADD, dl,
3930 MVT::f32, LogOfExponent, Log2ofMantissa);
3931 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3932 // For floating-point precision of 18:
3941 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3943 // error 0.0000018516, which is better than 18 bits
3944 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3945 getF32Constant(DAG, 0xbcd2769e));
3946 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3947 getF32Constant(DAG, 0x3e8ce0b9));
3948 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3949 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3950 getF32Constant(DAG, 0x3fa22ae7));
3951 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3952 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3953 getF32Constant(DAG, 0x40525723));
3954 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3955 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3956 getF32Constant(DAG, 0x40aaf200));
3957 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3958 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3959 getF32Constant(DAG, 0x40c39dad));
3960 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3961 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3962 getF32Constant(DAG, 0x4042902c));
3964 result = DAG.getNode(ISD::FADD, dl,
3965 MVT::f32, LogOfExponent, Log2ofMantissa);
3968 // No special expansion.
3969 result = DAG.getNode(ISD::FLOG2, dl,
3970 getValue(I.getArgOperand(0)).getValueType(),
3971 getValue(I.getArgOperand(0)));
3974 setValue(&I, result);
3977 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3978 /// limited-precision mode.
3980 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3982 DebugLoc dl = getCurDebugLoc();
3984 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3985 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3986 SDValue Op = getValue(I.getArgOperand(0));
3987 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3989 // Scale the exponent by log10(2) [0.30102999f].
3990 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3991 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3992 getF32Constant(DAG, 0x3e9a209a));
3994 // Get the significand and build it into a floating-point number with
3996 SDValue X = GetSignificand(DAG, Op1, dl);
3998 if (LimitFloatPrecision <= 6) {
3999 // For floating-point precision of 6:
4001 // Log10ofMantissa =
4003 // (0.60948995f - 0.10380950f * x) * x;
4005 // error 0.0014886165, which is 6 bits
4006 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4007 getF32Constant(DAG, 0xbdd49a13));
4008 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4009 getF32Constant(DAG, 0x3f1c0789));
4010 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4011 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4012 getF32Constant(DAG, 0x3f011300));
4014 result = DAG.getNode(ISD::FADD, dl,
4015 MVT::f32, LogOfExponent, Log10ofMantissa);
4016 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4017 // For floating-point precision of 12:
4019 // Log10ofMantissa =
4022 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4024 // error 0.00019228036, which is better than 12 bits
4025 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4026 getF32Constant(DAG, 0x3d431f31));
4027 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4028 getF32Constant(DAG, 0x3ea21fb2));
4029 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4030 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4031 getF32Constant(DAG, 0x3f6ae232));
4032 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4033 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4034 getF32Constant(DAG, 0x3f25f7c3));
4036 result = DAG.getNode(ISD::FADD, dl,
4037 MVT::f32, LogOfExponent, Log10ofMantissa);
4038 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4039 // For floating-point precision of 18:
4041 // Log10ofMantissa =
4046 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4048 // error 0.0000037995730, which is better than 18 bits
4049 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4050 getF32Constant(DAG, 0x3c5d51ce));
4051 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4052 getF32Constant(DAG, 0x3e00685a));
4053 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4054 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4055 getF32Constant(DAG, 0x3efb6798));
4056 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4057 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4058 getF32Constant(DAG, 0x3f88d192));
4059 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4060 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4061 getF32Constant(DAG, 0x3fc4316c));
4062 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4063 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4064 getF32Constant(DAG, 0x3f57ce70));
4066 result = DAG.getNode(ISD::FADD, dl,
4067 MVT::f32, LogOfExponent, Log10ofMantissa);
4070 // No special expansion.
4071 result = DAG.getNode(ISD::FLOG10, dl,
4072 getValue(I.getArgOperand(0)).getValueType(),
4073 getValue(I.getArgOperand(0)));
4076 setValue(&I, result);
4079 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4080 /// limited-precision mode.
4082 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4084 DebugLoc dl = getCurDebugLoc();
4086 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4087 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4088 SDValue Op = getValue(I.getArgOperand(0));
4090 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4092 // FractionalPartOfX = x - (float)IntegerPartOfX;
4093 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4094 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4096 // IntegerPartOfX <<= 23;
4097 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4098 DAG.getConstant(23, TLI.getPointerTy()));
4100 if (LimitFloatPrecision <= 6) {
4101 // For floating-point precision of 6:
4103 // TwoToFractionalPartOfX =
4105 // (0.735607626f + 0.252464424f * x) * x;
4107 // error 0.0144103317, which is 6 bits
4108 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4109 getF32Constant(DAG, 0x3e814304));
4110 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4111 getF32Constant(DAG, 0x3f3c50c8));
4112 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4113 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4114 getF32Constant(DAG, 0x3f7f5e7e));
4115 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4116 SDValue TwoToFractionalPartOfX =
4117 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4119 result = DAG.getNode(ISD::BITCAST, dl,
4120 MVT::f32, TwoToFractionalPartOfX);
4121 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4122 // For floating-point precision of 12:
4124 // TwoToFractionalPartOfX =
4127 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4129 // error 0.000107046256, which is 13 to 14 bits
4130 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4131 getF32Constant(DAG, 0x3da235e3));
4132 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4133 getF32Constant(DAG, 0x3e65b8f3));
4134 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4135 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4136 getF32Constant(DAG, 0x3f324b07));
4137 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4138 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4139 getF32Constant(DAG, 0x3f7ff8fd));
4140 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4141 SDValue TwoToFractionalPartOfX =
4142 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4144 result = DAG.getNode(ISD::BITCAST, dl,
4145 MVT::f32, TwoToFractionalPartOfX);
4146 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4147 // For floating-point precision of 18:
4149 // TwoToFractionalPartOfX =
4153 // (0.554906021e-1f +
4154 // (0.961591928e-2f +
4155 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4156 // error 2.47208000*10^(-7), which is better than 18 bits
4157 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4158 getF32Constant(DAG, 0x3924b03e));
4159 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4160 getF32Constant(DAG, 0x3ab24b87));
4161 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4162 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4163 getF32Constant(DAG, 0x3c1d8c17));
4164 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4165 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4166 getF32Constant(DAG, 0x3d634a1d));
4167 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4168 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4169 getF32Constant(DAG, 0x3e75fe14));
4170 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4171 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4172 getF32Constant(DAG, 0x3f317234));
4173 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4174 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4175 getF32Constant(DAG, 0x3f800000));
4176 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4177 SDValue TwoToFractionalPartOfX =
4178 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4180 result = DAG.getNode(ISD::BITCAST, dl,
4181 MVT::f32, TwoToFractionalPartOfX);
4184 // No special expansion.
4185 result = DAG.getNode(ISD::FEXP2, dl,
4186 getValue(I.getArgOperand(0)).getValueType(),
4187 getValue(I.getArgOperand(0)));
4190 setValue(&I, result);
4193 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4194 /// limited-precision mode with x == 10.0f.
4196 SelectionDAGBuilder::visitPow(const CallInst &I) {
4198 const Value *Val = I.getArgOperand(0);
4199 DebugLoc dl = getCurDebugLoc();
4200 bool IsExp10 = false;
4202 if (getValue(Val).getValueType() == MVT::f32 &&
4203 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4204 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4205 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4206 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4208 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4213 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4214 SDValue Op = getValue(I.getArgOperand(1));
4216 // Put the exponent in the right bit position for later addition to the
4219 // #define LOG2OF10 3.3219281f
4220 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4221 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4222 getF32Constant(DAG, 0x40549a78));
4223 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4225 // FractionalPartOfX = x - (float)IntegerPartOfX;
4226 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4227 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4229 // IntegerPartOfX <<= 23;
4230 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4231 DAG.getConstant(23, TLI.getPointerTy()));
4233 if (LimitFloatPrecision <= 6) {
4234 // For floating-point precision of 6:
4236 // twoToFractionalPartOfX =
4238 // (0.735607626f + 0.252464424f * x) * x;
4240 // error 0.0144103317, which is 6 bits
4241 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4242 getF32Constant(DAG, 0x3e814304));
4243 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4244 getF32Constant(DAG, 0x3f3c50c8));
4245 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4246 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4247 getF32Constant(DAG, 0x3f7f5e7e));
4248 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4249 SDValue TwoToFractionalPartOfX =
4250 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4252 result = DAG.getNode(ISD::BITCAST, dl,
4253 MVT::f32, TwoToFractionalPartOfX);
4254 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4255 // For floating-point precision of 12:
4257 // TwoToFractionalPartOfX =
4260 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4262 // error 0.000107046256, which is 13 to 14 bits
4263 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4264 getF32Constant(DAG, 0x3da235e3));
4265 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4266 getF32Constant(DAG, 0x3e65b8f3));
4267 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4268 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4269 getF32Constant(DAG, 0x3f324b07));
4270 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4271 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4272 getF32Constant(DAG, 0x3f7ff8fd));
4273 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4274 SDValue TwoToFractionalPartOfX =
4275 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4277 result = DAG.getNode(ISD::BITCAST, dl,
4278 MVT::f32, TwoToFractionalPartOfX);
4279 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4280 // For floating-point precision of 18:
4282 // TwoToFractionalPartOfX =
4286 // (0.554906021e-1f +
4287 // (0.961591928e-2f +
4288 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4289 // error 2.47208000*10^(-7), which is better than 18 bits
4290 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4291 getF32Constant(DAG, 0x3924b03e));
4292 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4293 getF32Constant(DAG, 0x3ab24b87));
4294 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4295 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4296 getF32Constant(DAG, 0x3c1d8c17));
4297 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4298 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4299 getF32Constant(DAG, 0x3d634a1d));
4300 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4301 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4302 getF32Constant(DAG, 0x3e75fe14));
4303 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4304 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4305 getF32Constant(DAG, 0x3f317234));
4306 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4307 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4308 getF32Constant(DAG, 0x3f800000));
4309 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4310 SDValue TwoToFractionalPartOfX =
4311 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4313 result = DAG.getNode(ISD::BITCAST, dl,
4314 MVT::f32, TwoToFractionalPartOfX);
4317 // No special expansion.
4318 result = DAG.getNode(ISD::FPOW, dl,
4319 getValue(I.getArgOperand(0)).getValueType(),
4320 getValue(I.getArgOperand(0)),
4321 getValue(I.getArgOperand(1)));
4324 setValue(&I, result);
4328 /// ExpandPowI - Expand a llvm.powi intrinsic.
4329 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4330 SelectionDAG &DAG) {
4331 // If RHS is a constant, we can expand this out to a multiplication tree,
4332 // otherwise we end up lowering to a call to __powidf2 (for example). When
4333 // optimizing for size, we only want to do this if the expansion would produce
4334 // a small number of multiplies, otherwise we do the full expansion.
4335 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4336 // Get the exponent as a positive value.
4337 unsigned Val = RHSC->getSExtValue();
4338 if ((int)Val < 0) Val = -Val;
4340 // powi(x, 0) -> 1.0
4342 return DAG.getConstantFP(1.0, LHS.getValueType());
4344 const Function *F = DAG.getMachineFunction().getFunction();
4345 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4346 // If optimizing for size, don't insert too many multiplies. This
4347 // inserts up to 5 multiplies.
4348 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4349 // We use the simple binary decomposition method to generate the multiply
4350 // sequence. There are more optimal ways to do this (for example,
4351 // powi(x,15) generates one more multiply than it should), but this has
4352 // the benefit of being both really simple and much better than a libcall.
4353 SDValue Res; // Logically starts equal to 1.0
4354 SDValue CurSquare = LHS;
4358 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4360 Res = CurSquare; // 1.0*CurSquare.
4363 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4364 CurSquare, CurSquare);
4368 // If the original was negative, invert the result, producing 1/(x*x*x).
4369 if (RHSC->getSExtValue() < 0)
4370 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4371 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4376 // Otherwise, expand to a libcall.
4377 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4380 // getTruncatedArgReg - Find underlying register used for an truncated
4382 static unsigned getTruncatedArgReg(const SDValue &N) {
4383 if (N.getOpcode() != ISD::TRUNCATE)
4386 const SDValue &Ext = N.getOperand(0);
4387 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4388 const SDValue &CFR = Ext.getOperand(0);
4389 if (CFR.getOpcode() == ISD::CopyFromReg)
4390 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4391 if (CFR.getOpcode() == ISD::TRUNCATE)
4392 return getTruncatedArgReg(CFR);
4397 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4398 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4399 /// At the end of instruction selection, they will be inserted to the entry BB.
4401 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4404 const Argument *Arg = dyn_cast<Argument>(V);
4408 MachineFunction &MF = DAG.getMachineFunction();
4409 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4410 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4412 // Ignore inlined function arguments here.
4413 DIVariable DV(Variable);
4414 if (DV.isInlinedFnArgument(MF.getFunction()))
4418 // Some arguments' frame index is recorded during argument lowering.
4419 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4421 Reg = TRI->getFrameRegister(MF);
4423 if (!Reg && N.getNode()) {
4424 if (N.getOpcode() == ISD::CopyFromReg)
4425 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4427 Reg = getTruncatedArgReg(N);
4428 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4429 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4430 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4437 // Check if ValueMap has reg number.
4438 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4439 if (VMI != FuncInfo.ValueMap.end())
4443 if (!Reg && N.getNode()) {
4444 // Check if frame index is available.
4445 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4446 if (FrameIndexSDNode *FINode =
4447 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4448 Reg = TRI->getFrameRegister(MF);
4449 Offset = FINode->getIndex();
4456 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4457 TII->get(TargetOpcode::DBG_VALUE))
4458 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4459 FuncInfo.ArgDbgValues.push_back(&*MIB);
4463 // VisualStudio defines setjmp as _setjmp
4464 #if defined(_MSC_VER) && defined(setjmp) && \
4465 !defined(setjmp_undefined_for_msvc)
4466 # pragma push_macro("setjmp")
4468 # define setjmp_undefined_for_msvc
4471 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4472 /// we want to emit this as a call to a named external function, return the name
4473 /// otherwise lower it and return null.
4475 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4476 DebugLoc dl = getCurDebugLoc();
4479 switch (Intrinsic) {
4481 // By default, turn this into a target intrinsic node.
4482 visitTargetIntrinsic(I, Intrinsic);
4484 case Intrinsic::vastart: visitVAStart(I); return 0;
4485 case Intrinsic::vaend: visitVAEnd(I); return 0;
4486 case Intrinsic::vacopy: visitVACopy(I); return 0;
4487 case Intrinsic::returnaddress:
4488 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4489 getValue(I.getArgOperand(0))));
4491 case Intrinsic::frameaddress:
4492 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4493 getValue(I.getArgOperand(0))));
4495 case Intrinsic::setjmp:
4496 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4497 case Intrinsic::longjmp:
4498 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4499 case Intrinsic::memcpy: {
4500 // Assert for address < 256 since we support only user defined address
4502 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4504 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4506 "Unknown address space");
4507 SDValue Op1 = getValue(I.getArgOperand(0));
4508 SDValue Op2 = getValue(I.getArgOperand(1));
4509 SDValue Op3 = getValue(I.getArgOperand(2));
4510 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4511 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4512 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4513 MachinePointerInfo(I.getArgOperand(0)),
4514 MachinePointerInfo(I.getArgOperand(1))));
4517 case Intrinsic::memset: {
4518 // Assert for address < 256 since we support only user defined address
4520 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4522 "Unknown address space");
4523 SDValue Op1 = getValue(I.getArgOperand(0));
4524 SDValue Op2 = getValue(I.getArgOperand(1));
4525 SDValue Op3 = getValue(I.getArgOperand(2));
4526 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4527 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4528 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4529 MachinePointerInfo(I.getArgOperand(0))));
4532 case Intrinsic::memmove: {
4533 // Assert for address < 256 since we support only user defined address
4535 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4537 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4539 "Unknown address space");
4540 SDValue Op1 = getValue(I.getArgOperand(0));
4541 SDValue Op2 = getValue(I.getArgOperand(1));
4542 SDValue Op3 = getValue(I.getArgOperand(2));
4543 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4544 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4545 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4546 MachinePointerInfo(I.getArgOperand(0)),
4547 MachinePointerInfo(I.getArgOperand(1))));
4550 case Intrinsic::dbg_declare: {
4551 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4552 MDNode *Variable = DI.getVariable();
4553 const Value *Address = DI.getAddress();
4554 if (!Address || !DIVariable(Variable).Verify()) {
4555 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4559 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4560 // but do not always have a corresponding SDNode built. The SDNodeOrder
4561 // absolute, but not relative, values are different depending on whether
4562 // debug info exists.
4565 // Check if address has undef value.
4566 if (isa<UndefValue>(Address) ||
4567 (Address->use_empty() && !isa<Argument>(Address))) {
4568 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4572 SDValue &N = NodeMap[Address];
4573 if (!N.getNode() && isa<Argument>(Address))
4574 // Check unused arguments map.
4575 N = UnusedArgNodeMap[Address];
4578 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4579 Address = BCI->getOperand(0);
4580 // Parameters are handled specially.
4582 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4583 isa<Argument>(Address));
4585 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4587 if (isParameter && !AI) {
4588 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4590 // Byval parameter. We have a frame index at this point.
4591 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4592 0, dl, SDNodeOrder);
4594 // Address is an argument, so try to emit its dbg value using
4595 // virtual register info from the FuncInfo.ValueMap.
4596 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4600 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4601 0, dl, SDNodeOrder);
4603 // Can't do anything with other non-AI cases yet.
4604 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4605 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4606 DEBUG(Address->dump());
4609 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4611 // If Address is an argument then try to emit its dbg value using
4612 // virtual register info from the FuncInfo.ValueMap.
4613 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4614 // If variable is pinned by a alloca in dominating bb then
4615 // use StaticAllocaMap.
4616 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4617 if (AI->getParent() != DI.getParent()) {
4618 DenseMap<const AllocaInst*, int>::iterator SI =
4619 FuncInfo.StaticAllocaMap.find(AI);
4620 if (SI != FuncInfo.StaticAllocaMap.end()) {
4621 SDV = DAG.getDbgValue(Variable, SI->second,
4622 0, dl, SDNodeOrder);
4623 DAG.AddDbgValue(SDV, 0, false);
4628 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4633 case Intrinsic::dbg_value: {
4634 const DbgValueInst &DI = cast<DbgValueInst>(I);
4635 if (!DIVariable(DI.getVariable()).Verify())
4638 MDNode *Variable = DI.getVariable();
4639 uint64_t Offset = DI.getOffset();
4640 const Value *V = DI.getValue();
4644 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4645 // but do not always have a corresponding SDNode built. The SDNodeOrder
4646 // absolute, but not relative, values are different depending on whether
4647 // debug info exists.
4650 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4651 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4652 DAG.AddDbgValue(SDV, 0, false);
4654 // Do not use getValue() in here; we don't want to generate code at
4655 // this point if it hasn't been done yet.
4656 SDValue N = NodeMap[V];
4657 if (!N.getNode() && isa<Argument>(V))
4658 // Check unused arguments map.
4659 N = UnusedArgNodeMap[V];
4661 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4662 SDV = DAG.getDbgValue(Variable, N.getNode(),
4663 N.getResNo(), Offset, dl, SDNodeOrder);
4664 DAG.AddDbgValue(SDV, N.getNode(), false);
4666 } else if (!V->use_empty() ) {
4667 // Do not call getValue(V) yet, as we don't want to generate code.
4668 // Remember it for later.
4669 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4670 DanglingDebugInfoMap[V] = DDI;
4672 // We may expand this to cover more cases. One case where we have no
4673 // data available is an unreferenced parameter.
4674 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4678 // Build a debug info table entry.
4679 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4680 V = BCI->getOperand(0);
4681 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4682 // Don't handle byval struct arguments or VLAs, for example.
4684 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4685 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4688 DenseMap<const AllocaInst*, int>::iterator SI =
4689 FuncInfo.StaticAllocaMap.find(AI);
4690 if (SI == FuncInfo.StaticAllocaMap.end())
4692 int FI = SI->second;
4694 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4695 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4696 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4700 case Intrinsic::eh_typeid_for: {
4701 // Find the type id for the given typeinfo.
4702 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4703 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4704 Res = DAG.getConstant(TypeID, MVT::i32);
4709 case Intrinsic::eh_return_i32:
4710 case Intrinsic::eh_return_i64:
4711 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4712 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4715 getValue(I.getArgOperand(0)),
4716 getValue(I.getArgOperand(1))));
4718 case Intrinsic::eh_unwind_init:
4719 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4721 case Intrinsic::eh_dwarf_cfa: {
4722 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4723 TLI.getPointerTy());
4724 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4726 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4727 TLI.getPointerTy()),
4729 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4731 DAG.getConstant(0, TLI.getPointerTy()));
4732 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4736 case Intrinsic::eh_sjlj_callsite: {
4737 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4738 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4739 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4740 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4742 MMI.setCurrentCallSite(CI->getZExtValue());
4745 case Intrinsic::eh_sjlj_functioncontext: {
4746 // Get and store the index of the function context.
4747 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4749 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4750 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4751 MFI->setFunctionContextIndex(FI);
4754 case Intrinsic::eh_sjlj_setjmp: {
4757 Ops[1] = getValue(I.getArgOperand(0));
4758 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4759 DAG.getVTList(MVT::i32, MVT::Other),
4761 setValue(&I, Op.getValue(0));
4762 DAG.setRoot(Op.getValue(1));
4765 case Intrinsic::eh_sjlj_longjmp: {
4766 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4767 getRoot(), getValue(I.getArgOperand(0))));
4771 case Intrinsic::x86_mmx_pslli_w:
4772 case Intrinsic::x86_mmx_pslli_d:
4773 case Intrinsic::x86_mmx_pslli_q:
4774 case Intrinsic::x86_mmx_psrli_w:
4775 case Intrinsic::x86_mmx_psrli_d:
4776 case Intrinsic::x86_mmx_psrli_q:
4777 case Intrinsic::x86_mmx_psrai_w:
4778 case Intrinsic::x86_mmx_psrai_d: {
4779 SDValue ShAmt = getValue(I.getArgOperand(1));
4780 if (isa<ConstantSDNode>(ShAmt)) {
4781 visitTargetIntrinsic(I, Intrinsic);
4784 unsigned NewIntrinsic = 0;
4785 EVT ShAmtVT = MVT::v2i32;
4786 switch (Intrinsic) {
4787 case Intrinsic::x86_mmx_pslli_w:
4788 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4790 case Intrinsic::x86_mmx_pslli_d:
4791 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4793 case Intrinsic::x86_mmx_pslli_q:
4794 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4796 case Intrinsic::x86_mmx_psrli_w:
4797 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4799 case Intrinsic::x86_mmx_psrli_d:
4800 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4802 case Intrinsic::x86_mmx_psrli_q:
4803 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4805 case Intrinsic::x86_mmx_psrai_w:
4806 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4808 case Intrinsic::x86_mmx_psrai_d:
4809 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4811 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4814 // The vector shift intrinsics with scalars uses 32b shift amounts but
4815 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4817 // We must do this early because v2i32 is not a legal type.
4818 DebugLoc dl = getCurDebugLoc();
4821 ShOps[1] = DAG.getConstant(0, MVT::i32);
4822 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4823 EVT DestVT = TLI.getValueType(I.getType());
4824 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4825 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4826 DAG.getConstant(NewIntrinsic, MVT::i32),
4827 getValue(I.getArgOperand(0)), ShAmt);
4831 case Intrinsic::x86_avx_vinsertf128_pd_256:
4832 case Intrinsic::x86_avx_vinsertf128_ps_256:
4833 case Intrinsic::x86_avx_vinsertf128_si_256:
4834 case Intrinsic::x86_avx2_vinserti128: {
4835 DebugLoc dl = getCurDebugLoc();
4836 EVT DestVT = TLI.getValueType(I.getType());
4837 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4838 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4839 ElVT.getVectorNumElements();
4840 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4841 getValue(I.getArgOperand(0)),
4842 getValue(I.getArgOperand(1)),
4843 DAG.getConstant(Idx, MVT::i32));
4847 case Intrinsic::convertff:
4848 case Intrinsic::convertfsi:
4849 case Intrinsic::convertfui:
4850 case Intrinsic::convertsif:
4851 case Intrinsic::convertuif:
4852 case Intrinsic::convertss:
4853 case Intrinsic::convertsu:
4854 case Intrinsic::convertus:
4855 case Intrinsic::convertuu: {
4856 ISD::CvtCode Code = ISD::CVT_INVALID;
4857 switch (Intrinsic) {
4858 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4859 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4860 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4861 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4862 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4863 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4864 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4865 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4866 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4867 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4869 EVT DestVT = TLI.getValueType(I.getType());
4870 const Value *Op1 = I.getArgOperand(0);
4871 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4872 DAG.getValueType(DestVT),
4873 DAG.getValueType(getValue(Op1).getValueType()),
4874 getValue(I.getArgOperand(1)),
4875 getValue(I.getArgOperand(2)),
4880 case Intrinsic::sqrt:
4881 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4882 getValue(I.getArgOperand(0)).getValueType(),
4883 getValue(I.getArgOperand(0))));
4885 case Intrinsic::powi:
4886 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4887 getValue(I.getArgOperand(1)), DAG));
4889 case Intrinsic::sin:
4890 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4891 getValue(I.getArgOperand(0)).getValueType(),
4892 getValue(I.getArgOperand(0))));
4894 case Intrinsic::cos:
4895 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4896 getValue(I.getArgOperand(0)).getValueType(),
4897 getValue(I.getArgOperand(0))));
4899 case Intrinsic::log:
4902 case Intrinsic::log2:
4905 case Intrinsic::log10:
4908 case Intrinsic::exp:
4911 case Intrinsic::exp2:
4914 case Intrinsic::pow:
4917 case Intrinsic::fma:
4918 setValue(&I, DAG.getNode(ISD::FMA, dl,
4919 getValue(I.getArgOperand(0)).getValueType(),
4920 getValue(I.getArgOperand(0)),
4921 getValue(I.getArgOperand(1)),
4922 getValue(I.getArgOperand(2))));
4924 case Intrinsic::convert_to_fp16:
4925 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4926 MVT::i16, getValue(I.getArgOperand(0))));
4928 case Intrinsic::convert_from_fp16:
4929 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4930 MVT::f32, getValue(I.getArgOperand(0))));
4932 case Intrinsic::pcmarker: {
4933 SDValue Tmp = getValue(I.getArgOperand(0));
4934 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4937 case Intrinsic::readcyclecounter: {
4938 SDValue Op = getRoot();
4939 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4940 DAG.getVTList(MVT::i64, MVT::Other),
4943 DAG.setRoot(Res.getValue(1));
4946 case Intrinsic::bswap:
4947 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4948 getValue(I.getArgOperand(0)).getValueType(),
4949 getValue(I.getArgOperand(0))));
4951 case Intrinsic::cttz: {
4952 SDValue Arg = getValue(I.getArgOperand(0));
4953 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4954 EVT Ty = Arg.getValueType();
4955 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4959 case Intrinsic::ctlz: {
4960 SDValue Arg = getValue(I.getArgOperand(0));
4961 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4962 EVT Ty = Arg.getValueType();
4963 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4967 case Intrinsic::ctpop: {
4968 SDValue Arg = getValue(I.getArgOperand(0));
4969 EVT Ty = Arg.getValueType();
4970 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4973 case Intrinsic::stacksave: {
4974 SDValue Op = getRoot();
4975 Res = DAG.getNode(ISD::STACKSAVE, dl,
4976 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4978 DAG.setRoot(Res.getValue(1));
4981 case Intrinsic::stackrestore: {
4982 Res = getValue(I.getArgOperand(0));
4983 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4986 case Intrinsic::stackprotector: {
4987 // Emit code into the DAG to store the stack guard onto the stack.
4988 MachineFunction &MF = DAG.getMachineFunction();
4989 MachineFrameInfo *MFI = MF.getFrameInfo();
4990 EVT PtrTy = TLI.getPointerTy();
4992 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4993 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4995 int FI = FuncInfo.StaticAllocaMap[Slot];
4996 MFI->setStackProtectorIndex(FI);
4998 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5000 // Store the stack protector onto the stack.
5001 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
5002 MachinePointerInfo::getFixedStack(FI),
5008 case Intrinsic::objectsize: {
5009 // If we don't know by now, we're never going to know.
5010 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5012 assert(CI && "Non-constant type in __builtin_object_size?");
5014 SDValue Arg = getValue(I.getCalledValue());
5015 EVT Ty = Arg.getValueType();
5018 Res = DAG.getConstant(-1ULL, Ty);
5020 Res = DAG.getConstant(0, Ty);
5025 case Intrinsic::var_annotation:
5026 // Discard annotate attributes
5029 case Intrinsic::init_trampoline: {
5030 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5034 Ops[1] = getValue(I.getArgOperand(0));
5035 Ops[2] = getValue(I.getArgOperand(1));
5036 Ops[3] = getValue(I.getArgOperand(2));
5037 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5038 Ops[5] = DAG.getSrcValue(F);
5040 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5045 case Intrinsic::adjust_trampoline: {
5046 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5048 getValue(I.getArgOperand(0))));
5051 case Intrinsic::gcroot:
5053 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5054 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5056 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5057 GFI->addStackRoot(FI->getIndex(), TypeMap);
5060 case Intrinsic::gcread:
5061 case Intrinsic::gcwrite:
5062 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5063 case Intrinsic::flt_rounds:
5064 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5067 case Intrinsic::expect: {
5068 // Just replace __builtin_expect(exp, c) with EXP.
5069 setValue(&I, getValue(I.getArgOperand(0)));
5073 case Intrinsic::trap: {
5074 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5075 if (TrapFuncName.empty()) {
5076 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5079 TargetLowering::ArgListTy Args;
5080 std::pair<SDValue, SDValue> Result =
5081 TLI.LowerCallTo(getRoot(), I.getType(),
5082 false, false, false, false, 0, CallingConv::C,
5083 /*isTailCall=*/false,
5084 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5085 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5086 Args, DAG, getCurDebugLoc());
5087 DAG.setRoot(Result.second);
5090 case Intrinsic::debugger: {
5091 DAG.setRoot(DAG.getNode(ISD::DEBUGGER, dl,MVT::Other, getRoot()));
5094 case Intrinsic::uadd_with_overflow:
5095 case Intrinsic::sadd_with_overflow:
5096 case Intrinsic::usub_with_overflow:
5097 case Intrinsic::ssub_with_overflow:
5098 case Intrinsic::umul_with_overflow:
5099 case Intrinsic::smul_with_overflow: {
5101 switch (Intrinsic) {
5102 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5103 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5104 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5105 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5106 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5107 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5108 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5110 SDValue Op1 = getValue(I.getArgOperand(0));
5111 SDValue Op2 = getValue(I.getArgOperand(1));
5113 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5114 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
5117 case Intrinsic::prefetch: {
5119 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5121 Ops[1] = getValue(I.getArgOperand(0));
5122 Ops[2] = getValue(I.getArgOperand(1));
5123 Ops[3] = getValue(I.getArgOperand(2));
5124 Ops[4] = getValue(I.getArgOperand(3));
5125 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5126 DAG.getVTList(MVT::Other),
5128 EVT::getIntegerVT(*Context, 8),
5129 MachinePointerInfo(I.getArgOperand(0)),
5131 false, /* volatile */
5133 rw==1)); /* write */
5137 case Intrinsic::invariant_start:
5138 case Intrinsic::lifetime_start:
5139 // Discard region information.
5140 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5142 case Intrinsic::invariant_end:
5143 case Intrinsic::lifetime_end:
5144 // Discard region information.
5149 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5151 MachineBasicBlock *LandingPad) {
5152 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5153 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5154 Type *RetTy = FTy->getReturnType();
5155 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5156 MCSymbol *BeginLabel = 0;
5158 TargetLowering::ArgListTy Args;
5159 TargetLowering::ArgListEntry Entry;
5160 Args.reserve(CS.arg_size());
5162 // Check whether the function can return without sret-demotion.
5163 SmallVector<ISD::OutputArg, 4> Outs;
5164 SmallVector<uint64_t, 4> Offsets;
5165 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5166 Outs, TLI, &Offsets);
5168 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5169 DAG.getMachineFunction(),
5170 FTy->isVarArg(), Outs,
5173 SDValue DemoteStackSlot;
5174 int DemoteStackIdx = -100;
5176 if (!CanLowerReturn) {
5177 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5178 FTy->getReturnType());
5179 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5180 FTy->getReturnType());
5181 MachineFunction &MF = DAG.getMachineFunction();
5182 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5183 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5185 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5186 Entry.Node = DemoteStackSlot;
5187 Entry.Ty = StackSlotPtrType;
5188 Entry.isSExt = false;
5189 Entry.isZExt = false;
5190 Entry.isInReg = false;
5191 Entry.isSRet = true;
5192 Entry.isNest = false;
5193 Entry.isByVal = false;
5194 Entry.Alignment = Align;
5195 Args.push_back(Entry);
5196 RetTy = Type::getVoidTy(FTy->getContext());
5199 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5201 const Value *V = *i;
5204 if (V->getType()->isEmptyTy())
5207 SDValue ArgNode = getValue(V);
5208 Entry.Node = ArgNode; Entry.Ty = V->getType();
5210 unsigned attrInd = i - CS.arg_begin() + 1;
5211 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5212 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5213 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5214 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5215 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5216 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5217 Entry.Alignment = CS.getParamAlignment(attrInd);
5218 Args.push_back(Entry);
5222 // Insert a label before the invoke call to mark the try range. This can be
5223 // used to detect deletion of the invoke via the MachineModuleInfo.
5224 BeginLabel = MMI.getContext().CreateTempSymbol();
5226 // For SjLj, keep track of which landing pads go with which invokes
5227 // so as to maintain the ordering of pads in the LSDA.
5228 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5229 if (CallSiteIndex) {
5230 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5231 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5233 // Now that the call site is handled, stop tracking it.
5234 MMI.setCurrentCallSite(0);
5237 // Both PendingLoads and PendingExports must be flushed here;
5238 // this call might not return.
5240 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5243 // Check if target-independent constraints permit a tail call here.
5244 // Target-dependent constraints are checked within TLI.LowerCallTo.
5246 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5249 // If there's a possibility that fast-isel has already selected some amount
5250 // of the current basic block, don't emit a tail call.
5251 if (isTailCall && TM.Options.EnableFastISel)
5254 std::pair<SDValue,SDValue> Result =
5255 TLI.LowerCallTo(getRoot(), RetTy,
5256 CS.paramHasAttr(0, Attribute::SExt),
5257 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5258 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5259 CS.getCallingConv(),
5262 !CS.getInstruction()->use_empty(),
5263 Callee, Args, DAG, getCurDebugLoc());
5264 assert((isTailCall || Result.second.getNode()) &&
5265 "Non-null chain expected with non-tail call!");
5266 assert((Result.second.getNode() || !Result.first.getNode()) &&
5267 "Null value expected with tail call!");
5268 if (Result.first.getNode()) {
5269 setValue(CS.getInstruction(), Result.first);
5270 } else if (!CanLowerReturn && Result.second.getNode()) {
5271 // The instruction result is the result of loading from the
5272 // hidden sret parameter.
5273 SmallVector<EVT, 1> PVTs;
5274 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5276 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5277 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5278 EVT PtrVT = PVTs[0];
5279 unsigned NumValues = Outs.size();
5280 SmallVector<SDValue, 4> Values(NumValues);
5281 SmallVector<SDValue, 4> Chains(NumValues);
5283 for (unsigned i = 0; i < NumValues; ++i) {
5284 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5286 DAG.getConstant(Offsets[i], PtrVT));
5287 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5289 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5290 false, false, false, 1);
5292 Chains[i] = L.getValue(1);
5295 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5296 MVT::Other, &Chains[0], NumValues);
5297 PendingLoads.push_back(Chain);
5299 // Collect the legal value parts into potentially illegal values
5300 // that correspond to the original function's return values.
5301 SmallVector<EVT, 4> RetTys;
5302 RetTy = FTy->getReturnType();
5303 ComputeValueVTs(TLI, RetTy, RetTys);
5304 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5305 SmallVector<SDValue, 4> ReturnValues;
5306 unsigned CurReg = 0;
5307 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5309 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5310 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5312 SDValue ReturnValue =
5313 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5314 RegisterVT, VT, AssertOp);
5315 ReturnValues.push_back(ReturnValue);
5319 setValue(CS.getInstruction(),
5320 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5321 DAG.getVTList(&RetTys[0], RetTys.size()),
5322 &ReturnValues[0], ReturnValues.size()));
5325 // Assign order to nodes here. If the call does not produce a result, it won't
5326 // be mapped to a SDNode and visit() will not assign it an order number.
5327 if (!Result.second.getNode()) {
5328 // As a special case, a null chain means that a tail call has been emitted and
5329 // the DAG root is already updated.
5332 AssignOrderingToNode(DAG.getRoot().getNode());
5334 DAG.setRoot(Result.second);
5336 AssignOrderingToNode(Result.second.getNode());
5340 // Insert a label at the end of the invoke call to mark the try range. This
5341 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5342 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5343 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5345 // Inform MachineModuleInfo of range.
5346 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5350 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5351 /// value is equal or not-equal to zero.
5352 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5353 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5355 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5356 if (IC->isEquality())
5357 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5358 if (C->isNullValue())
5360 // Unknown instruction.
5366 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5368 SelectionDAGBuilder &Builder) {
5370 // Check to see if this load can be trivially constant folded, e.g. if the
5371 // input is from a string literal.
5372 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5373 // Cast pointer to the type we really want to load.
5374 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5375 PointerType::getUnqual(LoadTy));
5377 if (const Constant *LoadCst =
5378 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5380 return Builder.getValue(LoadCst);
5383 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5384 // still constant memory, the input chain can be the entry node.
5386 bool ConstantMemory = false;
5388 // Do not serialize (non-volatile) loads of constant memory with anything.
5389 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5390 Root = Builder.DAG.getEntryNode();
5391 ConstantMemory = true;
5393 // Do not serialize non-volatile loads against each other.
5394 Root = Builder.DAG.getRoot();
5397 SDValue Ptr = Builder.getValue(PtrVal);
5398 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5399 Ptr, MachinePointerInfo(PtrVal),
5401 false /*nontemporal*/,
5402 false /*isinvariant*/, 1 /* align=1 */);
5404 if (!ConstantMemory)
5405 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5410 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5411 /// If so, return true and lower it, otherwise return false and it will be
5412 /// lowered like a normal call.
5413 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5414 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5415 if (I.getNumArgOperands() != 3)
5418 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5419 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5420 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5421 !I.getType()->isIntegerTy())
5424 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5426 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5427 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5428 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5429 bool ActuallyDoIt = true;
5432 switch (Size->getZExtValue()) {
5434 LoadVT = MVT::Other;
5436 ActuallyDoIt = false;
5440 LoadTy = Type::getInt16Ty(Size->getContext());
5444 LoadTy = Type::getInt32Ty(Size->getContext());
5448 LoadTy = Type::getInt64Ty(Size->getContext());
5452 LoadVT = MVT::v4i32;
5453 LoadTy = Type::getInt32Ty(Size->getContext());
5454 LoadTy = VectorType::get(LoadTy, 4);
5459 // This turns into unaligned loads. We only do this if the target natively
5460 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5461 // we'll only produce a small number of byte loads.
5463 // Require that we can find a legal MVT, and only do this if the target
5464 // supports unaligned loads of that type. Expanding into byte loads would
5466 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5467 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5468 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5469 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5470 ActuallyDoIt = false;
5474 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5475 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5477 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5479 EVT CallVT = TLI.getValueType(I.getType(), true);
5480 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5490 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5491 // Handle inline assembly differently.
5492 if (isa<InlineAsm>(I.getCalledValue())) {
5497 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5498 ComputeUsesVAFloatArgument(I, &MMI);
5500 const char *RenameFn = 0;
5501 if (Function *F = I.getCalledFunction()) {
5502 if (F->isDeclaration()) {
5503 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5504 if (unsigned IID = II->getIntrinsicID(F)) {
5505 RenameFn = visitIntrinsicCall(I, IID);
5510 if (unsigned IID = F->getIntrinsicID()) {
5511 RenameFn = visitIntrinsicCall(I, IID);
5517 // Check for well-known libc/libm calls. If the function is internal, it
5518 // can't be a library call.
5519 if (!F->hasLocalLinkage() && F->hasName()) {
5520 StringRef Name = F->getName();
5521 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") ||
5522 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") ||
5523 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) {
5524 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5525 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5526 I.getType() == I.getArgOperand(0)->getType() &&
5527 I.getType() == I.getArgOperand(1)->getType()) {
5528 SDValue LHS = getValue(I.getArgOperand(0));
5529 SDValue RHS = getValue(I.getArgOperand(1));
5530 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5531 LHS.getValueType(), LHS, RHS));
5534 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") ||
5535 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") ||
5536 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) {
5537 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5538 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5539 I.getType() == I.getArgOperand(0)->getType()) {
5540 SDValue Tmp = getValue(I.getArgOperand(0));
5541 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5542 Tmp.getValueType(), Tmp));
5545 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") ||
5546 (LibInfo->has(LibFunc::sinf) && Name == "sinf") ||
5547 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) {
5548 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5549 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5550 I.getType() == I.getArgOperand(0)->getType() &&
5551 I.onlyReadsMemory()) {
5552 SDValue Tmp = getValue(I.getArgOperand(0));
5553 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5554 Tmp.getValueType(), Tmp));
5557 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") ||
5558 (LibInfo->has(LibFunc::cosf) && Name == "cosf") ||
5559 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) {
5560 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5561 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5562 I.getType() == I.getArgOperand(0)->getType() &&
5563 I.onlyReadsMemory()) {
5564 SDValue Tmp = getValue(I.getArgOperand(0));
5565 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5566 Tmp.getValueType(), Tmp));
5569 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") ||
5570 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") ||
5571 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) {
5572 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5573 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5574 I.getType() == I.getArgOperand(0)->getType() &&
5575 I.onlyReadsMemory()) {
5576 SDValue Tmp = getValue(I.getArgOperand(0));
5577 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5578 Tmp.getValueType(), Tmp));
5581 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") ||
5582 (LibInfo->has(LibFunc::floorf) && Name == "floorf") ||
5583 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) {
5584 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5585 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5586 I.getType() == I.getArgOperand(0)->getType()) {
5587 SDValue Tmp = getValue(I.getArgOperand(0));
5588 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(),
5589 Tmp.getValueType(), Tmp));
5592 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") ||
5593 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") ||
5594 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) {
5595 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5596 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5597 I.getType() == I.getArgOperand(0)->getType()) {
5598 SDValue Tmp = getValue(I.getArgOperand(0));
5599 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(),
5600 Tmp.getValueType(), Tmp));
5603 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") ||
5604 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") ||
5605 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) {
5606 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5607 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5608 I.getType() == I.getArgOperand(0)->getType()) {
5609 SDValue Tmp = getValue(I.getArgOperand(0));
5610 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(),
5611 Tmp.getValueType(), Tmp));
5614 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") ||
5615 (LibInfo->has(LibFunc::rintf) && Name == "rintf") ||
5616 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) {
5617 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5618 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5619 I.getType() == I.getArgOperand(0)->getType()) {
5620 SDValue Tmp = getValue(I.getArgOperand(0));
5621 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(),
5622 Tmp.getValueType(), Tmp));
5625 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") ||
5626 (LibInfo->has(LibFunc::truncf) && Name == "truncf") ||
5627 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) {
5628 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5629 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5630 I.getType() == I.getArgOperand(0)->getType()) {
5631 SDValue Tmp = getValue(I.getArgOperand(0));
5632 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(),
5633 Tmp.getValueType(), Tmp));
5636 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") ||
5637 (LibInfo->has(LibFunc::log2f) && Name == "log2f") ||
5638 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) {
5639 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5640 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5641 I.getType() == I.getArgOperand(0)->getType() &&
5642 I.onlyReadsMemory()) {
5643 SDValue Tmp = getValue(I.getArgOperand(0));
5644 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(),
5645 Tmp.getValueType(), Tmp));
5648 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") ||
5649 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") ||
5650 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) {
5651 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5652 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5653 I.getType() == I.getArgOperand(0)->getType() &&
5654 I.onlyReadsMemory()) {
5655 SDValue Tmp = getValue(I.getArgOperand(0));
5656 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(),
5657 Tmp.getValueType(), Tmp));
5660 } else if (Name == "memcmp") {
5661 if (visitMemCmpCall(I))
5669 Callee = getValue(I.getCalledValue());
5671 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5673 // Check if we can potentially perform a tail call. More detailed checking is
5674 // be done within LowerCallTo, after more information about the call is known.
5675 LowerCallTo(&I, Callee, I.isTailCall());
5680 /// AsmOperandInfo - This contains information for each constraint that we are
5682 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5684 /// CallOperand - If this is the result output operand or a clobber
5685 /// this is null, otherwise it is the incoming operand to the CallInst.
5686 /// This gets modified as the asm is processed.
5687 SDValue CallOperand;
5689 /// AssignedRegs - If this is a register or register class operand, this
5690 /// contains the set of register corresponding to the operand.
5691 RegsForValue AssignedRegs;
5693 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5694 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5697 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5698 /// corresponds to. If there is no Value* for this operand, it returns
5700 EVT getCallOperandValEVT(LLVMContext &Context,
5701 const TargetLowering &TLI,
5702 const TargetData *TD) const {
5703 if (CallOperandVal == 0) return MVT::Other;
5705 if (isa<BasicBlock>(CallOperandVal))
5706 return TLI.getPointerTy();
5708 llvm::Type *OpTy = CallOperandVal->getType();
5710 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5711 // If this is an indirect operand, the operand is a pointer to the
5714 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5716 report_fatal_error("Indirect operand for inline asm not a pointer!");
5717 OpTy = PtrTy->getElementType();
5720 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5721 if (StructType *STy = dyn_cast<StructType>(OpTy))
5722 if (STy->getNumElements() == 1)
5723 OpTy = STy->getElementType(0);
5725 // If OpTy is not a single value, it may be a struct/union that we
5726 // can tile with integers.
5727 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5728 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5737 OpTy = IntegerType::get(Context, BitSize);
5742 return TLI.getValueType(OpTy, true);
5746 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5748 } // end anonymous namespace
5750 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5751 /// specified operand. We prefer to assign virtual registers, to allow the
5752 /// register allocator to handle the assignment process. However, if the asm
5753 /// uses features that we can't model on machineinstrs, we have SDISel do the
5754 /// allocation. This produces generally horrible, but correct, code.
5756 /// OpInfo describes the operand.
5758 static void GetRegistersForValue(SelectionDAG &DAG,
5759 const TargetLowering &TLI,
5761 SDISelAsmOperandInfo &OpInfo) {
5762 LLVMContext &Context = *DAG.getContext();
5764 MachineFunction &MF = DAG.getMachineFunction();
5765 SmallVector<unsigned, 4> Regs;
5767 // If this is a constraint for a single physreg, or a constraint for a
5768 // register class, find it.
5769 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5770 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5771 OpInfo.ConstraintVT);
5773 unsigned NumRegs = 1;
5774 if (OpInfo.ConstraintVT != MVT::Other) {
5775 // If this is a FP input in an integer register (or visa versa) insert a bit
5776 // cast of the input value. More generally, handle any case where the input
5777 // value disagrees with the register class we plan to stick this in.
5778 if (OpInfo.Type == InlineAsm::isInput &&
5779 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5780 // Try to convert to the first EVT that the reg class contains. If the
5781 // types are identical size, use a bitcast to convert (e.g. two differing
5783 EVT RegVT = *PhysReg.second->vt_begin();
5784 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5785 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5786 RegVT, OpInfo.CallOperand);
5787 OpInfo.ConstraintVT = RegVT;
5788 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5789 // If the input is a FP value and we want it in FP registers, do a
5790 // bitcast to the corresponding integer type. This turns an f64 value
5791 // into i64, which can be passed with two i32 values on a 32-bit
5793 RegVT = EVT::getIntegerVT(Context,
5794 OpInfo.ConstraintVT.getSizeInBits());
5795 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5796 RegVT, OpInfo.CallOperand);
5797 OpInfo.ConstraintVT = RegVT;
5801 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5805 EVT ValueVT = OpInfo.ConstraintVT;
5807 // If this is a constraint for a specific physical register, like {r17},
5809 if (unsigned AssignedReg = PhysReg.first) {
5810 const TargetRegisterClass *RC = PhysReg.second;
5811 if (OpInfo.ConstraintVT == MVT::Other)
5812 ValueVT = *RC->vt_begin();
5814 // Get the actual register value type. This is important, because the user
5815 // may have asked for (e.g.) the AX register in i32 type. We need to
5816 // remember that AX is actually i16 to get the right extension.
5817 RegVT = *RC->vt_begin();
5819 // This is a explicit reference to a physical register.
5820 Regs.push_back(AssignedReg);
5822 // If this is an expanded reference, add the rest of the regs to Regs.
5824 TargetRegisterClass::iterator I = RC->begin();
5825 for (; *I != AssignedReg; ++I)
5826 assert(I != RC->end() && "Didn't find reg!");
5828 // Already added the first reg.
5830 for (; NumRegs; --NumRegs, ++I) {
5831 assert(I != RC->end() && "Ran out of registers to allocate!");
5836 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5840 // Otherwise, if this was a reference to an LLVM register class, create vregs
5841 // for this reference.
5842 if (const TargetRegisterClass *RC = PhysReg.second) {
5843 RegVT = *RC->vt_begin();
5844 if (OpInfo.ConstraintVT == MVT::Other)
5847 // Create the appropriate number of virtual registers.
5848 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5849 for (; NumRegs; --NumRegs)
5850 Regs.push_back(RegInfo.createVirtualRegister(RC));
5852 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5856 // Otherwise, we couldn't allocate enough registers for this.
5859 /// visitInlineAsm - Handle a call to an InlineAsm object.
5861 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5862 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5864 /// ConstraintOperands - Information about all of the constraints.
5865 SDISelAsmOperandInfoVector ConstraintOperands;
5867 TargetLowering::AsmOperandInfoVector
5868 TargetConstraints = TLI.ParseConstraints(CS);
5870 bool hasMemory = false;
5872 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5873 unsigned ResNo = 0; // ResNo - The result number of the next output.
5874 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5875 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5876 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5878 EVT OpVT = MVT::Other;
5880 // Compute the value type for each operand.
5881 switch (OpInfo.Type) {
5882 case InlineAsm::isOutput:
5883 // Indirect outputs just consume an argument.
5884 if (OpInfo.isIndirect) {
5885 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5889 // The return value of the call is this value. As such, there is no
5890 // corresponding argument.
5891 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5892 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5893 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5895 assert(ResNo == 0 && "Asm only has one result!");
5896 OpVT = TLI.getValueType(CS.getType());
5900 case InlineAsm::isInput:
5901 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5903 case InlineAsm::isClobber:
5908 // If this is an input or an indirect output, process the call argument.
5909 // BasicBlocks are labels, currently appearing only in asm's.
5910 if (OpInfo.CallOperandVal) {
5911 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5912 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5914 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5917 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5920 OpInfo.ConstraintVT = OpVT;
5922 // Indirect operand accesses access memory.
5923 if (OpInfo.isIndirect)
5926 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5927 TargetLowering::ConstraintType
5928 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5929 if (CType == TargetLowering::C_Memory) {
5937 SDValue Chain, Flag;
5939 // We won't need to flush pending loads if this asm doesn't touch
5940 // memory and is nonvolatile.
5941 if (hasMemory || IA->hasSideEffects())
5944 Chain = DAG.getRoot();
5946 // Second pass over the constraints: compute which constraint option to use
5947 // and assign registers to constraints that want a specific physreg.
5948 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5949 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5951 // If this is an output operand with a matching input operand, look up the
5952 // matching input. If their types mismatch, e.g. one is an integer, the
5953 // other is floating point, or their sizes are different, flag it as an
5955 if (OpInfo.hasMatchingInput()) {
5956 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5958 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5959 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5960 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5961 OpInfo.ConstraintVT);
5962 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5963 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5964 Input.ConstraintVT);
5965 if ((OpInfo.ConstraintVT.isInteger() !=
5966 Input.ConstraintVT.isInteger()) ||
5967 (MatchRC.second != InputRC.second)) {
5968 report_fatal_error("Unsupported asm: input constraint"
5969 " with a matching output constraint of"
5970 " incompatible type!");
5972 Input.ConstraintVT = OpInfo.ConstraintVT;
5976 // Compute the constraint code and ConstraintType to use.
5977 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5979 // If this is a memory input, and if the operand is not indirect, do what we
5980 // need to to provide an address for the memory input.
5981 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5982 !OpInfo.isIndirect) {
5983 assert((OpInfo.isMultipleAlternative ||
5984 (OpInfo.Type == InlineAsm::isInput)) &&
5985 "Can only indirectify direct input operands!");
5987 // Memory operands really want the address of the value. If we don't have
5988 // an indirect input, put it in the constpool if we can, otherwise spill
5989 // it to a stack slot.
5990 // TODO: This isn't quite right. We need to handle these according to
5991 // the addressing mode that the constraint wants. Also, this may take
5992 // an additional register for the computation and we don't want that
5995 // If the operand is a float, integer, or vector constant, spill to a
5996 // constant pool entry to get its address.
5997 const Value *OpVal = OpInfo.CallOperandVal;
5998 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5999 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6000 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6001 TLI.getPointerTy());
6003 // Otherwise, create a stack slot and emit a store to it before the
6005 Type *Ty = OpVal->getType();
6006 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
6007 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
6008 MachineFunction &MF = DAG.getMachineFunction();
6009 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6010 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6011 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6012 OpInfo.CallOperand, StackSlot,
6013 MachinePointerInfo::getFixedStack(SSFI),
6015 OpInfo.CallOperand = StackSlot;
6018 // There is no longer a Value* corresponding to this operand.
6019 OpInfo.CallOperandVal = 0;
6021 // It is now an indirect operand.
6022 OpInfo.isIndirect = true;
6025 // If this constraint is for a specific register, allocate it before
6027 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6028 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6031 // Second pass - Loop over all of the operands, assigning virtual or physregs
6032 // to register class operands.
6033 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6034 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6036 // C_Register operands have already been allocated, Other/Memory don't need
6038 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6039 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6042 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6043 std::vector<SDValue> AsmNodeOperands;
6044 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6045 AsmNodeOperands.push_back(
6046 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6047 TLI.getPointerTy()));
6049 // If we have a !srcloc metadata node associated with it, we want to attach
6050 // this to the ultimately generated inline asm machineinstr. To do this, we
6051 // pass in the third operand as this (potentially null) inline asm MDNode.
6052 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6053 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6055 // Remember the HasSideEffect and AlignStack bits as operand 3.
6056 unsigned ExtraInfo = 0;
6057 if (IA->hasSideEffects())
6058 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6059 if (IA->isAlignStack())
6060 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6061 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6062 TLI.getPointerTy()));
6064 // Loop over all of the inputs, copying the operand values into the
6065 // appropriate registers and processing the output regs.
6066 RegsForValue RetValRegs;
6068 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6069 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6071 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6072 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6074 switch (OpInfo.Type) {
6075 case InlineAsm::isOutput: {
6076 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6077 OpInfo.ConstraintType != TargetLowering::C_Register) {
6078 // Memory output, or 'other' output (e.g. 'X' constraint).
6079 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6081 // Add information to the INLINEASM node to know about this output.
6082 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6083 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6084 TLI.getPointerTy()));
6085 AsmNodeOperands.push_back(OpInfo.CallOperand);
6089 // Otherwise, this is a register or register class output.
6091 // Copy the output from the appropriate register. Find a register that
6093 if (OpInfo.AssignedRegs.Regs.empty()) {
6094 LLVMContext &Ctx = *DAG.getContext();
6095 Ctx.emitError(CS.getInstruction(),
6096 "couldn't allocate output register for constraint '" +
6097 Twine(OpInfo.ConstraintCode) + "'");
6101 // If this is an indirect operand, store through the pointer after the
6103 if (OpInfo.isIndirect) {
6104 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6105 OpInfo.CallOperandVal));
6107 // This is the result value of the call.
6108 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6109 // Concatenate this output onto the outputs list.
6110 RetValRegs.append(OpInfo.AssignedRegs);
6113 // Add information to the INLINEASM node to know that this register is
6115 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6116 InlineAsm::Kind_RegDefEarlyClobber :
6117 InlineAsm::Kind_RegDef,
6124 case InlineAsm::isInput: {
6125 SDValue InOperandVal = OpInfo.CallOperand;
6127 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6128 // If this is required to match an output register we have already set,
6129 // just use its register.
6130 unsigned OperandNo = OpInfo.getMatchedOperand();
6132 // Scan until we find the definition we already emitted of this operand.
6133 // When we find it, create a RegsForValue operand.
6134 unsigned CurOp = InlineAsm::Op_FirstOperand;
6135 for (; OperandNo; --OperandNo) {
6136 // Advance to the next operand.
6138 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6139 assert((InlineAsm::isRegDefKind(OpFlag) ||
6140 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6141 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6142 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6146 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6147 if (InlineAsm::isRegDefKind(OpFlag) ||
6148 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6149 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6150 if (OpInfo.isIndirect) {
6151 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6152 LLVMContext &Ctx = *DAG.getContext();
6153 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6154 " don't know how to handle tied "
6155 "indirect register inputs");
6158 RegsForValue MatchedRegs;
6159 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6160 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6161 MatchedRegs.RegVTs.push_back(RegVT);
6162 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6163 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6165 MatchedRegs.Regs.push_back
6166 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6168 // Use the produced MatchedRegs object to
6169 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6171 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6172 true, OpInfo.getMatchedOperand(),
6173 DAG, AsmNodeOperands);
6177 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6178 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6179 "Unexpected number of operands");
6180 // Add information to the INLINEASM node to know about this input.
6181 // See InlineAsm.h isUseOperandTiedToDef.
6182 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6183 OpInfo.getMatchedOperand());
6184 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6185 TLI.getPointerTy()));
6186 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6190 // Treat indirect 'X' constraint as memory.
6191 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6193 OpInfo.ConstraintType = TargetLowering::C_Memory;
6195 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6196 std::vector<SDValue> Ops;
6197 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6200 LLVMContext &Ctx = *DAG.getContext();
6201 Ctx.emitError(CS.getInstruction(),
6202 "invalid operand for inline asm constraint '" +
6203 Twine(OpInfo.ConstraintCode) + "'");
6207 // Add information to the INLINEASM node to know about this input.
6208 unsigned ResOpType =
6209 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6210 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6211 TLI.getPointerTy()));
6212 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6216 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6217 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6218 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6219 "Memory operands expect pointer values");
6221 // Add information to the INLINEASM node to know about this input.
6222 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6223 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6224 TLI.getPointerTy()));
6225 AsmNodeOperands.push_back(InOperandVal);
6229 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6230 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6231 "Unknown constraint type!");
6232 assert(!OpInfo.isIndirect &&
6233 "Don't know how to handle indirect register inputs yet!");
6235 // Copy the input into the appropriate registers.
6236 if (OpInfo.AssignedRegs.Regs.empty()) {
6237 LLVMContext &Ctx = *DAG.getContext();
6238 Ctx.emitError(CS.getInstruction(),
6239 "couldn't allocate input reg for constraint '" +
6240 Twine(OpInfo.ConstraintCode) + "'");
6244 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6247 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6248 DAG, AsmNodeOperands);
6251 case InlineAsm::isClobber: {
6252 // Add the clobbered value to the operand list, so that the register
6253 // allocator is aware that the physreg got clobbered.
6254 if (!OpInfo.AssignedRegs.Regs.empty())
6255 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6263 // Finish up input operands. Set the input chain and add the flag last.
6264 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6265 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6267 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6268 DAG.getVTList(MVT::Other, MVT::Glue),
6269 &AsmNodeOperands[0], AsmNodeOperands.size());
6270 Flag = Chain.getValue(1);
6272 // If this asm returns a register value, copy the result from that register
6273 // and set it as the value of the call.
6274 if (!RetValRegs.Regs.empty()) {
6275 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6278 // FIXME: Why don't we do this for inline asms with MRVs?
6279 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6280 EVT ResultType = TLI.getValueType(CS.getType());
6282 // If any of the results of the inline asm is a vector, it may have the
6283 // wrong width/num elts. This can happen for register classes that can
6284 // contain multiple different value types. The preg or vreg allocated may
6285 // not have the same VT as was expected. Convert it to the right type
6286 // with bit_convert.
6287 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6288 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6291 } else if (ResultType != Val.getValueType() &&
6292 ResultType.isInteger() && Val.getValueType().isInteger()) {
6293 // If a result value was tied to an input value, the computed result may
6294 // have a wider width than the expected result. Extract the relevant
6296 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6299 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6302 setValue(CS.getInstruction(), Val);
6303 // Don't need to use this as a chain in this case.
6304 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6308 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6310 // Process indirect outputs, first output all of the flagged copies out of
6312 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6313 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6314 const Value *Ptr = IndirectStoresToEmit[i].second;
6315 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6317 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6320 // Emit the non-flagged stores from the physregs.
6321 SmallVector<SDValue, 8> OutChains;
6322 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6323 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6324 StoresToEmit[i].first,
6325 getValue(StoresToEmit[i].second),
6326 MachinePointerInfo(StoresToEmit[i].second),
6328 OutChains.push_back(Val);
6331 if (!OutChains.empty())
6332 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6333 &OutChains[0], OutChains.size());
6338 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6339 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6340 MVT::Other, getRoot(),
6341 getValue(I.getArgOperand(0)),
6342 DAG.getSrcValue(I.getArgOperand(0))));
6345 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6346 const TargetData &TD = *TLI.getTargetData();
6347 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6348 getRoot(), getValue(I.getOperand(0)),
6349 DAG.getSrcValue(I.getOperand(0)),
6350 TD.getABITypeAlignment(I.getType()));
6352 DAG.setRoot(V.getValue(1));
6355 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6356 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6357 MVT::Other, getRoot(),
6358 getValue(I.getArgOperand(0)),
6359 DAG.getSrcValue(I.getArgOperand(0))));
6362 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6363 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6364 MVT::Other, getRoot(),
6365 getValue(I.getArgOperand(0)),
6366 getValue(I.getArgOperand(1)),
6367 DAG.getSrcValue(I.getArgOperand(0)),
6368 DAG.getSrcValue(I.getArgOperand(1))));
6371 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6372 /// implementation, which just calls LowerCall.
6373 /// FIXME: When all targets are
6374 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6375 std::pair<SDValue, SDValue>
6376 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6377 bool RetSExt, bool RetZExt, bool isVarArg,
6378 bool isInreg, unsigned NumFixedArgs,
6379 CallingConv::ID CallConv, bool isTailCall,
6380 bool doesNotRet, bool isReturnValueUsed,
6382 ArgListTy &Args, SelectionDAG &DAG,
6383 DebugLoc dl) const {
6384 // Handle all of the outgoing arguments.
6385 SmallVector<ISD::OutputArg, 32> Outs;
6386 SmallVector<SDValue, 32> OutVals;
6387 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6388 SmallVector<EVT, 4> ValueVTs;
6389 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6390 for (unsigned Value = 0, NumValues = ValueVTs.size();
6391 Value != NumValues; ++Value) {
6392 EVT VT = ValueVTs[Value];
6393 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6394 SDValue Op = SDValue(Args[i].Node.getNode(),
6395 Args[i].Node.getResNo() + Value);
6396 ISD::ArgFlagsTy Flags;
6397 unsigned OriginalAlignment =
6398 getTargetData()->getABITypeAlignment(ArgTy);
6404 if (Args[i].isInReg)
6408 if (Args[i].isByVal) {
6410 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6411 Type *ElementTy = Ty->getElementType();
6412 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6413 // For ByVal, alignment should come from FE. BE will guess if this
6414 // info is not there but there are cases it cannot get right.
6415 unsigned FrameAlign;
6416 if (Args[i].Alignment)
6417 FrameAlign = Args[i].Alignment;
6419 FrameAlign = getByValTypeAlignment(ElementTy);
6420 Flags.setByValAlign(FrameAlign);
6424 Flags.setOrigAlign(OriginalAlignment);
6426 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6427 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6428 SmallVector<SDValue, 4> Parts(NumParts);
6429 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6432 ExtendKind = ISD::SIGN_EXTEND;
6433 else if (Args[i].isZExt)
6434 ExtendKind = ISD::ZERO_EXTEND;
6436 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6437 PartVT, ExtendKind);
6439 for (unsigned j = 0; j != NumParts; ++j) {
6440 // if it isn't first piece, alignment must be 1
6441 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6443 if (NumParts > 1 && j == 0)
6444 MyFlags.Flags.setSplit();
6446 MyFlags.Flags.setOrigAlign(1);
6448 Outs.push_back(MyFlags);
6449 OutVals.push_back(Parts[j]);
6454 // Handle the incoming return values from the call.
6455 SmallVector<ISD::InputArg, 32> Ins;
6456 SmallVector<EVT, 4> RetTys;
6457 ComputeValueVTs(*this, RetTy, RetTys);
6458 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6460 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6461 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6462 for (unsigned i = 0; i != NumRegs; ++i) {
6463 ISD::InputArg MyFlags;
6464 MyFlags.VT = RegisterVT.getSimpleVT();
6465 MyFlags.Used = isReturnValueUsed;
6467 MyFlags.Flags.setSExt();
6469 MyFlags.Flags.setZExt();
6471 MyFlags.Flags.setInReg();
6472 Ins.push_back(MyFlags);
6476 SmallVector<SDValue, 4> InVals;
6477 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall,
6478 Outs, OutVals, Ins, dl, DAG, InVals);
6480 // Verify that the target's LowerCall behaved as expected.
6481 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6482 "LowerCall didn't return a valid chain!");
6483 assert((!isTailCall || InVals.empty()) &&
6484 "LowerCall emitted a return value for a tail call!");
6485 assert((isTailCall || InVals.size() == Ins.size()) &&
6486 "LowerCall didn't emit the correct number of values!");
6488 // For a tail call, the return value is merely live-out and there aren't
6489 // any nodes in the DAG representing it. Return a special value to
6490 // indicate that a tail call has been emitted and no more Instructions
6491 // should be processed in the current block.
6494 return std::make_pair(SDValue(), SDValue());
6497 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6498 assert(InVals[i].getNode() &&
6499 "LowerCall emitted a null value!");
6500 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6501 "LowerCall emitted a value with the wrong type!");
6504 // Collect the legal value parts into potentially illegal values
6505 // that correspond to the original function's return values.
6506 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6508 AssertOp = ISD::AssertSext;
6510 AssertOp = ISD::AssertZext;
6511 SmallVector<SDValue, 4> ReturnValues;
6512 unsigned CurReg = 0;
6513 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6515 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6516 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6518 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6519 NumRegs, RegisterVT, VT,
6524 // For a function returning void, there is no return value. We can't create
6525 // such a node, so we just return a null return value in that case. In
6526 // that case, nothing will actually look at the value.
6527 if (ReturnValues.empty())
6528 return std::make_pair(SDValue(), Chain);
6530 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6531 DAG.getVTList(&RetTys[0], RetTys.size()),
6532 &ReturnValues[0], ReturnValues.size());
6533 return std::make_pair(Res, Chain);
6536 void TargetLowering::LowerOperationWrapper(SDNode *N,
6537 SmallVectorImpl<SDValue> &Results,
6538 SelectionDAG &DAG) const {
6539 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6541 Results.push_back(Res);
6544 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6545 llvm_unreachable("LowerOperation not implemented for this target!");
6549 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6550 SDValue Op = getNonRegisterValue(V);
6551 assert((Op.getOpcode() != ISD::CopyFromReg ||
6552 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6553 "Copy from a reg to the same reg!");
6554 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6556 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6557 SDValue Chain = DAG.getEntryNode();
6558 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6559 PendingExports.push_back(Chain);
6562 #include "llvm/CodeGen/SelectionDAGISel.h"
6564 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6565 /// entry block, return true. This includes arguments used by switches, since
6566 /// the switch may expand into multiple basic blocks.
6567 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6568 // With FastISel active, we may be splitting blocks, so force creation
6569 // of virtual registers for all non-dead arguments.
6571 return A->use_empty();
6573 const BasicBlock *Entry = A->getParent()->begin();
6574 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6576 const User *U = *UI;
6577 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6578 return false; // Use not in entry block.
6583 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6584 // If this is the entry block, emit arguments.
6585 const Function &F = *LLVMBB->getParent();
6586 SelectionDAG &DAG = SDB->DAG;
6587 DebugLoc dl = SDB->getCurDebugLoc();
6588 const TargetData *TD = TLI.getTargetData();
6589 SmallVector<ISD::InputArg, 16> Ins;
6591 // Check whether the function can return without sret-demotion.
6592 SmallVector<ISD::OutputArg, 4> Outs;
6593 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6596 if (!FuncInfo->CanLowerReturn) {
6597 // Put in an sret pointer parameter before all the other parameters.
6598 SmallVector<EVT, 1> ValueVTs;
6599 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6601 // NOTE: Assuming that a pointer will never break down to more than one VT
6603 ISD::ArgFlagsTy Flags;
6605 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6606 ISD::InputArg RetArg(Flags, RegisterVT, true);
6607 Ins.push_back(RetArg);
6610 // Set up the incoming argument description vector.
6612 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6613 I != E; ++I, ++Idx) {
6614 SmallVector<EVT, 4> ValueVTs;
6615 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6616 bool isArgValueUsed = !I->use_empty();
6617 for (unsigned Value = 0, NumValues = ValueVTs.size();
6618 Value != NumValues; ++Value) {
6619 EVT VT = ValueVTs[Value];
6620 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6621 ISD::ArgFlagsTy Flags;
6622 unsigned OriginalAlignment =
6623 TD->getABITypeAlignment(ArgTy);
6625 if (F.paramHasAttr(Idx, Attribute::ZExt))
6627 if (F.paramHasAttr(Idx, Attribute::SExt))
6629 if (F.paramHasAttr(Idx, Attribute::InReg))
6631 if (F.paramHasAttr(Idx, Attribute::StructRet))
6633 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6635 PointerType *Ty = cast<PointerType>(I->getType());
6636 Type *ElementTy = Ty->getElementType();
6637 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6638 // For ByVal, alignment should be passed from FE. BE will guess if
6639 // this info is not there but there are cases it cannot get right.
6640 unsigned FrameAlign;
6641 if (F.getParamAlignment(Idx))
6642 FrameAlign = F.getParamAlignment(Idx);
6644 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6645 Flags.setByValAlign(FrameAlign);
6647 if (F.paramHasAttr(Idx, Attribute::Nest))
6649 Flags.setOrigAlign(OriginalAlignment);
6651 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6652 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6653 for (unsigned i = 0; i != NumRegs; ++i) {
6654 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6655 if (NumRegs > 1 && i == 0)
6656 MyFlags.Flags.setSplit();
6657 // if it isn't first piece, alignment must be 1
6659 MyFlags.Flags.setOrigAlign(1);
6660 Ins.push_back(MyFlags);
6665 // Call the target to set up the argument values.
6666 SmallVector<SDValue, 8> InVals;
6667 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6671 // Verify that the target's LowerFormalArguments behaved as expected.
6672 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6673 "LowerFormalArguments didn't return a valid chain!");
6674 assert(InVals.size() == Ins.size() &&
6675 "LowerFormalArguments didn't emit the correct number of values!");
6677 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6678 assert(InVals[i].getNode() &&
6679 "LowerFormalArguments emitted a null value!");
6680 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6681 "LowerFormalArguments emitted a value with the wrong type!");
6685 // Update the DAG with the new chain value resulting from argument lowering.
6686 DAG.setRoot(NewRoot);
6688 // Set up the argument values.
6691 if (!FuncInfo->CanLowerReturn) {
6692 // Create a virtual register for the sret pointer, and put in a copy
6693 // from the sret argument into it.
6694 SmallVector<EVT, 1> ValueVTs;
6695 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6696 EVT VT = ValueVTs[0];
6697 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6698 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6699 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6700 RegVT, VT, AssertOp);
6702 MachineFunction& MF = SDB->DAG.getMachineFunction();
6703 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6704 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6705 FuncInfo->DemoteRegister = SRetReg;
6706 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6708 DAG.setRoot(NewRoot);
6710 // i indexes lowered arguments. Bump it past the hidden sret argument.
6711 // Idx indexes LLVM arguments. Don't touch it.
6715 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6717 SmallVector<SDValue, 4> ArgValues;
6718 SmallVector<EVT, 4> ValueVTs;
6719 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6720 unsigned NumValues = ValueVTs.size();
6722 // If this argument is unused then remember its value. It is used to generate
6723 // debugging information.
6724 if (I->use_empty() && NumValues)
6725 SDB->setUnusedArgValue(I, InVals[i]);
6727 for (unsigned Val = 0; Val != NumValues; ++Val) {
6728 EVT VT = ValueVTs[Val];
6729 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6730 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6732 if (!I->use_empty()) {
6733 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6734 if (F.paramHasAttr(Idx, Attribute::SExt))
6735 AssertOp = ISD::AssertSext;
6736 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6737 AssertOp = ISD::AssertZext;
6739 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6740 NumParts, PartVT, VT,
6747 // We don't need to do anything else for unused arguments.
6748 if (ArgValues.empty())
6751 // Note down frame index.
6752 if (FrameIndexSDNode *FI =
6753 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6754 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6756 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6757 SDB->getCurDebugLoc());
6759 SDB->setValue(I, Res);
6760 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6761 if (LoadSDNode *LNode =
6762 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6763 if (FrameIndexSDNode *FI =
6764 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6765 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6768 // If this argument is live outside of the entry block, insert a copy from
6769 // wherever we got it to the vreg that other BB's will reference it as.
6770 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6771 // If we can, though, try to skip creating an unnecessary vreg.
6772 // FIXME: This isn't very clean... it would be nice to make this more
6773 // general. It's also subtly incompatible with the hacks FastISel
6775 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6776 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6777 FuncInfo->ValueMap[I] = Reg;
6781 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6782 FuncInfo->InitializeRegForValue(I);
6783 SDB->CopyToExportRegsIfNeeded(I);
6787 assert(i == InVals.size() && "Argument register count mismatch!");
6789 // Finally, if the target has anything special to do, allow it to do so.
6790 // FIXME: this should insert code into the DAG!
6791 EmitFunctionEntryCode();
6794 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6795 /// ensure constants are generated when needed. Remember the virtual registers
6796 /// that need to be added to the Machine PHI nodes as input. We cannot just
6797 /// directly add them, because expansion might result in multiple MBB's for one
6798 /// BB. As such, the start of the BB might correspond to a different MBB than
6802 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6803 const TerminatorInst *TI = LLVMBB->getTerminator();
6805 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6807 // Check successor nodes' PHI nodes that expect a constant to be available
6809 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6810 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6811 if (!isa<PHINode>(SuccBB->begin())) continue;
6812 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6814 // If this terminator has multiple identical successors (common for
6815 // switches), only handle each succ once.
6816 if (!SuccsHandled.insert(SuccMBB)) continue;
6818 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6820 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6821 // nodes and Machine PHI nodes, but the incoming operands have not been
6823 for (BasicBlock::const_iterator I = SuccBB->begin();
6824 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6825 // Ignore dead phi's.
6826 if (PN->use_empty()) continue;
6829 if (PN->getType()->isEmptyTy())
6833 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6835 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6836 unsigned &RegOut = ConstantsOut[C];
6838 RegOut = FuncInfo.CreateRegs(C->getType());
6839 CopyValueToVirtualRegister(C, RegOut);
6843 DenseMap<const Value *, unsigned>::iterator I =
6844 FuncInfo.ValueMap.find(PHIOp);
6845 if (I != FuncInfo.ValueMap.end())
6848 assert(isa<AllocaInst>(PHIOp) &&
6849 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6850 "Didn't codegen value into a register!??");
6851 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6852 CopyValueToVirtualRegister(PHIOp, Reg);
6856 // Remember that this register needs to added to the machine PHI node as
6857 // the input for this MBB.
6858 SmallVector<EVT, 4> ValueVTs;
6859 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6860 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6861 EVT VT = ValueVTs[vti];
6862 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6863 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6864 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6865 Reg += NumRegisters;
6869 ConstantsOut.clear();