1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/DebugInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetIntrinsicInfo.h"
58 #include "llvm/Target/TargetLibraryInfo.h"
59 #include "llvm/Target/TargetLowering.h"
60 #include "llvm/Target/TargetOptions.h"
61 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 /// LimitFloatPrecision - Generate low-precision inline sequences for
66 /// some float libcalls (6, 8 or 12 bits).
67 static unsigned LimitFloatPrecision;
69 static cl::opt<unsigned, true>
70 LimitFPPrecision("limit-float-precision",
71 cl::desc("Generate low-precision inline sequences "
72 "for some float libcalls"),
73 cl::location(LimitFloatPrecision),
76 // Limit the width of DAG chains. This is important in general to prevent
77 // prevent DAG-based analysis from blowing up. For example, alias analysis and
78 // load clustering may not complete in reasonable time. It is difficult to
79 // recognize and avoid this situation within each individual analysis, and
80 // future analyses are likely to have the same behavior. Limiting DAG width is
81 // the safe approach, and will be especially important with global DAGs.
83 // MaxParallelChains default is arbitrarily high to avoid affecting
84 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
85 // sequence over this should have been converted to llvm.memcpy by the
86 // frontend. It easy to induce this behavior with .ll code such as:
87 // %buffer = alloca [4096 x i8]
88 // %data = load [4096 x i8]* %argPtr
89 // store [4096 x i8] %data, [4096 x i8]* %buffer
90 static const unsigned MaxParallelChains = 64;
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
93 const SDValue *Parts, unsigned NumParts,
94 MVT PartVT, EVT ValueVT, const Value *V);
96 /// getCopyFromParts - Create a value that contains the specified legal parts
97 /// combined into the value they represent. If the parts combine to a type
98 /// larger then ValueVT then AssertOp can be used to specify whether the extra
99 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
100 /// (ISD::AssertSext).
101 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts,
103 unsigned NumParts, MVT PartVT, EVT ValueVT,
105 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
106 if (ValueVT.isVector())
107 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
110 assert(NumParts > 0 && "No parts to assemble!");
111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
112 SDValue Val = Parts[0];
115 // Assemble the value from multiple parts.
116 if (ValueVT.isInteger()) {
117 unsigned PartBits = PartVT.getSizeInBits();
118 unsigned ValueBits = ValueVT.getSizeInBits();
120 // Assemble the power of 2 part.
121 unsigned RoundParts = NumParts & (NumParts - 1) ?
122 1 << Log2_32(NumParts) : NumParts;
123 unsigned RoundBits = PartBits * RoundParts;
124 EVT RoundVT = RoundBits == ValueBits ?
125 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
128 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
130 if (RoundParts > 2) {
131 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
133 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
134 RoundParts / 2, PartVT, HalfVT, V);
136 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
137 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
140 if (TLI.isBigEndian())
143 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
145 if (RoundParts < NumParts) {
146 // Assemble the trailing non-power-of-2 part.
147 unsigned OddParts = NumParts - RoundParts;
148 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
149 Hi = getCopyFromParts(DAG, DL,
150 Parts + RoundParts, OddParts, PartVT, OddVT, V);
152 // Combine the round and odd parts.
154 if (TLI.isBigEndian())
156 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
157 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
158 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
159 DAG.getConstant(Lo.getValueType().getSizeInBits(),
160 TLI.getPointerTy()));
161 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
162 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
164 } else if (PartVT.isFloatingPoint()) {
165 // FP split into multiple FP parts (for ppcf128)
166 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
171 if (TLI.isBigEndian())
173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
175 // FP split into integer parts (soft fp)
176 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
177 !PartVT.isVector() && "Unexpected split");
178 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
179 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
183 // There is now one part, held in Val. Correct it to match ValueVT.
184 EVT PartEVT = Val.getValueType();
186 if (PartEVT == ValueVT)
189 if (PartEVT.isInteger() && ValueVT.isInteger()) {
190 if (ValueVT.bitsLT(PartEVT)) {
191 // For a truncate, see if we have any information to
192 // indicate whether the truncated bits will always be
193 // zero or sign-extension.
194 if (AssertOp != ISD::DELETED_NODE)
195 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
196 DAG.getValueType(ValueVT));
197 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
199 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
202 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
203 // FP_ROUND's are always exact here.
204 if (ValueVT.bitsLT(Val.getValueType()))
205 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
206 DAG.getTargetConstant(1, TLI.getPointerTy()));
208 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
211 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
212 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
214 llvm_unreachable("Unknown mismatch!");
217 /// getCopyFromPartsVector - Create a value that contains the specified legal
218 /// parts combined into the value they represent. If the parts combine to a
219 /// type larger then ValueVT then AssertOp can be used to specify whether the
220 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
221 /// ValueVT (ISD::AssertSext).
222 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
223 const SDValue *Parts, unsigned NumParts,
224 MVT PartVT, EVT ValueVT, const Value *V) {
225 assert(ValueVT.isVector() && "Not a vector value");
226 assert(NumParts > 0 && "No parts to assemble!");
227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
228 SDValue Val = Parts[0];
230 // Handle a multi-element vector.
234 unsigned NumIntermediates;
236 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
237 NumIntermediates, RegisterVT);
238 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
239 NumParts = NumRegs; // Silence a compiler warning.
240 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
241 assert(RegisterVT == Parts[0].getSimpleValueType() &&
242 "Part type doesn't match part!");
244 // Assemble the parts into intermediate operands.
245 SmallVector<SDValue, 8> Ops(NumIntermediates);
246 if (NumIntermediates == NumParts) {
247 // If the register was not expanded, truncate or copy the value,
249 for (unsigned i = 0; i != NumParts; ++i)
250 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
251 PartVT, IntermediateVT, V);
252 } else if (NumParts > 0) {
253 // If the intermediate type was expanded, build the intermediate
254 // operands from the parts.
255 assert(NumParts % NumIntermediates == 0 &&
256 "Must expand into a divisible number of parts!");
257 unsigned Factor = NumParts / NumIntermediates;
258 for (unsigned i = 0; i != NumIntermediates; ++i)
259 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
260 PartVT, IntermediateVT, V);
263 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
264 // intermediate operands.
265 Val = DAG.getNode(IntermediateVT.isVector() ?
266 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
267 ValueVT, &Ops[0], NumIntermediates);
270 // There is now one part, held in Val. Correct it to match ValueVT.
271 EVT PartEVT = Val.getValueType();
273 if (PartEVT == ValueVT)
276 if (PartEVT.isVector()) {
277 // If the element type of the source/dest vectors are the same, but the
278 // parts vector has more elements than the value vector, then we have a
279 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
281 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
282 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
283 "Cannot narrow, it would be a lossy transformation");
284 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
285 DAG.getConstant(0, TLI.getVectorIdxTy()));
288 // Vector/Vector bitcast.
289 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
290 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
292 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
293 "Cannot handle this kind of promotion");
294 // Promoted vector extract
295 bool Smaller = ValueVT.bitsLE(PartEVT);
296 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
301 // Trivial bitcast if the types are the same size and the destination
302 // vector type is legal.
303 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
304 TLI.isTypeLegal(ValueVT))
305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
307 // Handle cases such as i8 -> <1 x i1>
308 if (ValueVT.getVectorNumElements() != 1) {
309 LLVMContext &Ctx = *DAG.getContext();
310 Twine ErrMsg("non-trivial scalar-to-vector conversion");
311 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
312 if (const CallInst *CI = dyn_cast<CallInst>(I))
313 if (isa<InlineAsm>(CI->getCalledValue()))
314 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
315 Ctx.emitError(I, ErrMsg);
317 Ctx.emitError(ErrMsg);
319 return DAG.getUNDEF(ValueVT);
322 if (ValueVT.getVectorNumElements() == 1 &&
323 ValueVT.getVectorElementType() != PartEVT) {
324 bool Smaller = ValueVT.bitsLE(PartEVT);
325 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
326 DL, ValueVT.getScalarType(), Val);
329 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
332 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
333 SDValue Val, SDValue *Parts, unsigned NumParts,
334 MVT PartVT, const Value *V);
336 /// getCopyToParts - Create a series of nodes that contain the specified value
337 /// split into legal parts. If the parts contain more bits than Val, then, for
338 /// integers, ExtendKind can be used to specify how to generate the extra bits.
339 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
340 SDValue Val, SDValue *Parts, unsigned NumParts,
341 MVT PartVT, const Value *V,
342 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
343 EVT ValueVT = Val.getValueType();
345 // Handle the vector case separately.
346 if (ValueVT.isVector())
347 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
350 unsigned PartBits = PartVT.getSizeInBits();
351 unsigned OrigNumParts = NumParts;
352 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
357 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
358 EVT PartEVT = PartVT;
359 if (PartEVT == ValueVT) {
360 assert(NumParts == 1 && "No-op copy with multiple parts!");
365 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
366 // If the parts cover more bits than the value has, promote the value.
367 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
368 assert(NumParts == 1 && "Do not know what to promote to!");
369 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
371 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
372 ValueVT.isInteger() &&
373 "Unknown mismatch!");
374 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
375 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
376 if (PartVT == MVT::x86mmx)
377 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 } else if (PartBits == ValueVT.getSizeInBits()) {
380 // Different types of the same size.
381 assert(NumParts == 1 && PartEVT != ValueVT);
382 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
383 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
384 // If the parts cover less bits than value has, truncate the value.
385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
386 ValueVT.isInteger() &&
387 "Unknown mismatch!");
388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
389 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
390 if (PartVT == MVT::x86mmx)
391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 // The value may have changed - recompute ValueVT.
395 ValueVT = Val.getValueType();
396 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
397 "Failed to tile the value with PartVT!");
400 if (PartEVT != ValueVT) {
401 LLVMContext &Ctx = *DAG.getContext();
402 Twine ErrMsg("scalar-to-vector conversion failed");
403 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) {
404 if (const CallInst *CI = dyn_cast<CallInst>(I))
405 if (isa<InlineAsm>(CI->getCalledValue()))
406 ErrMsg = ErrMsg + ", possible invalid constraint for vector type";
407 Ctx.emitError(I, ErrMsg);
409 Ctx.emitError(ErrMsg);
417 // Expand the value into multiple parts.
418 if (NumParts & (NumParts - 1)) {
419 // The number of parts is not a power of 2. Split off and copy the tail.
420 assert(PartVT.isInteger() && ValueVT.isInteger() &&
421 "Do not know what to expand to!");
422 unsigned RoundParts = 1 << Log2_32(NumParts);
423 unsigned RoundBits = RoundParts * PartBits;
424 unsigned OddParts = NumParts - RoundParts;
425 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
426 DAG.getIntPtrConstant(RoundBits));
427 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
429 if (TLI.isBigEndian())
430 // The odd parts were reversed by getCopyToParts - unreverse them.
431 std::reverse(Parts + RoundParts, Parts + NumParts);
433 NumParts = RoundParts;
434 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
435 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
438 // The number of parts is a power of 2. Repeatedly bisect the value using
440 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
441 EVT::getIntegerVT(*DAG.getContext(),
442 ValueVT.getSizeInBits()),
445 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
446 for (unsigned i = 0; i < NumParts; i += StepSize) {
447 unsigned ThisBits = StepSize * PartBits / 2;
448 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
449 SDValue &Part0 = Parts[i];
450 SDValue &Part1 = Parts[i+StepSize/2];
452 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(1));
454 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(0));
457 if (ThisBits == PartBits && ThisVT != PartVT) {
458 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
459 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
464 if (TLI.isBigEndian())
465 std::reverse(Parts, Parts + OrigNumParts);
469 /// getCopyToPartsVector - Create a series of nodes that contain the specified
470 /// value split into legal parts.
471 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
472 SDValue Val, SDValue *Parts, unsigned NumParts,
473 MVT PartVT, const Value *V) {
474 EVT ValueVT = Val.getValueType();
475 assert(ValueVT.isVector() && "Not a vector");
476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
479 EVT PartEVT = PartVT;
480 if (PartEVT == ValueVT) {
482 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
483 // Bitconvert vector->vector case.
484 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
485 } else if (PartVT.isVector() &&
486 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
487 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
488 EVT ElementVT = PartVT.getVectorElementType();
489 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
491 SmallVector<SDValue, 16> Ops;
492 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
493 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
494 ElementVT, Val, DAG.getConstant(i,
495 TLI.getVectorIdxTy())));
497 for (unsigned i = ValueVT.getVectorNumElements(),
498 e = PartVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getUNDEF(ElementVT));
501 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
503 // FIXME: Use CONCAT for 2x -> 4x.
505 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
506 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
507 } else if (PartVT.isVector() &&
508 PartEVT.getVectorElementType().bitsGE(
509 ValueVT.getVectorElementType()) &&
510 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
512 // Promoted vector extract
513 bool Smaller = PartEVT.bitsLE(ValueVT);
514 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
517 // Vector -> scalar conversion.
518 assert(ValueVT.getVectorNumElements() == 1 &&
519 "Only trivial vector-to-scalar conversions should get here!");
520 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
521 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
523 bool Smaller = ValueVT.bitsLE(PartVT);
524 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
532 // Handle a multi-element vector.
535 unsigned NumIntermediates;
536 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
538 NumIntermediates, RegisterVT);
539 unsigned NumElements = ValueVT.getVectorNumElements();
541 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
542 NumParts = NumRegs; // Silence a compiler warning.
543 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
545 // Split the vector into intermediate operands.
546 SmallVector<SDValue, 8> Ops(NumIntermediates);
547 for (unsigned i = 0; i != NumIntermediates; ++i) {
548 if (IntermediateVT.isVector())
549 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
551 DAG.getConstant(i * (NumElements / NumIntermediates),
552 TLI.getVectorIdxTy()));
554 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
556 DAG.getConstant(i, TLI.getVectorIdxTy()));
559 // Split the intermediate operands into legal parts.
560 if (NumParts == NumIntermediates) {
561 // If the register was not expanded, promote or copy the value,
563 for (unsigned i = 0; i != NumParts; ++i)
564 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
565 } else if (NumParts > 0) {
566 // If the intermediate type was expanded, split each the value into
568 assert(NumParts % NumIntermediates == 0 &&
569 "Must expand into a divisible number of parts!");
570 unsigned Factor = NumParts / NumIntermediates;
571 for (unsigned i = 0; i != NumIntermediates; ++i)
572 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
577 /// RegsForValue - This struct represents the registers (physical or virtual)
578 /// that a particular set of values is assigned, and the type information
579 /// about the value. The most common situation is to represent one value at a
580 /// time, but struct or array values are handled element-wise as multiple
581 /// values. The splitting of aggregates is performed recursively, so that we
582 /// never have aggregate-typed registers. The values at this point do not
583 /// necessarily have legal types, so each value may require one or more
584 /// registers of some legal type.
586 struct RegsForValue {
587 /// ValueVTs - The value types of the values, which may not be legal, and
588 /// may need be promoted or synthesized from one or more registers.
590 SmallVector<EVT, 4> ValueVTs;
592 /// RegVTs - The value types of the registers. This is the same size as
593 /// ValueVTs and it records, for each value, what the type of the assigned
594 /// register or registers are. (Individual values are never synthesized
595 /// from more than one type of register.)
597 /// With virtual registers, the contents of RegVTs is redundant with TLI's
598 /// getRegisterType member function, however when with physical registers
599 /// it is necessary to have a separate record of the types.
601 SmallVector<MVT, 4> RegVTs;
603 /// Regs - This list holds the registers assigned to the values.
604 /// Each legal or promoted value requires one register, and each
605 /// expanded value requires multiple registers.
607 SmallVector<unsigned, 4> Regs;
611 RegsForValue(const SmallVector<unsigned, 4> ®s,
612 MVT regvt, EVT valuevt)
613 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
615 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
616 unsigned Reg, Type *Ty) {
617 ComputeValueVTs(tli, Ty, ValueVTs);
619 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
622 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
623 for (unsigned i = 0; i != NumRegs; ++i)
624 Regs.push_back(Reg + i);
625 RegVTs.push_back(RegisterVT);
630 /// areValueTypesLegal - Return true if types of all the values are legal.
631 bool areValueTypesLegal(const TargetLowering &TLI) {
632 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
633 MVT RegisterVT = RegVTs[Value];
634 if (!TLI.isTypeLegal(RegisterVT))
640 /// append - Add the specified values to this one.
641 void append(const RegsForValue &RHS) {
642 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
643 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
644 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
647 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
648 /// this value and returns the result as a ValueVTs value. This uses
649 /// Chain/Flag as the input and updates them for the output Chain/Flag.
650 /// If the Flag pointer is NULL, no flag is used.
651 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
653 SDValue &Chain, SDValue *Flag,
654 const Value *V = 0) const;
656 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
657 /// specified value into the registers specified by this object. This uses
658 /// Chain/Flag as the input and updates them for the output Chain/Flag.
659 /// If the Flag pointer is NULL, no flag is used.
660 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
661 SDValue &Chain, SDValue *Flag, const Value *V) const;
663 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
664 /// operand list. This adds the code marker, matching input operand index
665 /// (if applicable), and includes the number of values added into it.
666 void AddInlineAsmOperands(unsigned Kind,
667 bool HasMatching, unsigned MatchingIdx,
669 std::vector<SDValue> &Ops) const;
673 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
674 /// this value and returns the result as a ValueVT value. This uses
675 /// Chain/Flag as the input and updates them for the output Chain/Flag.
676 /// If the Flag pointer is NULL, no flag is used.
677 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
678 FunctionLoweringInfo &FuncInfo,
680 SDValue &Chain, SDValue *Flag,
681 const Value *V) const {
682 // A Value with type {} or [0 x %t] needs no registers.
683 if (ValueVTs.empty())
686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
688 // Assemble the legal parts into the final values.
689 SmallVector<SDValue, 4> Values(ValueVTs.size());
690 SmallVector<SDValue, 8> Parts;
691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
692 // Copy the legal parts from the registers.
693 EVT ValueVT = ValueVTs[Value];
694 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
695 MVT RegisterVT = RegVTs[Value];
697 Parts.resize(NumRegs);
698 for (unsigned i = 0; i != NumRegs; ++i) {
701 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
703 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
704 *Flag = P.getValue(2);
707 Chain = P.getValue(1);
710 // If the source register was virtual and if we know something about it,
711 // add an assert node.
712 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
713 !RegisterVT.isInteger() || RegisterVT.isVector())
716 const FunctionLoweringInfo::LiveOutInfo *LOI =
717 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
721 unsigned RegSize = RegisterVT.getSizeInBits();
722 unsigned NumSignBits = LOI->NumSignBits;
723 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
725 if (NumZeroBits == RegSize) {
726 // The current value is a zero.
727 // Explicitly express that as it would be easier for
728 // optimizations to kick in.
729 Parts[i] = DAG.getConstant(0, RegisterVT);
733 // FIXME: We capture more information than the dag can represent. For
734 // now, just use the tightest assertzext/assertsext possible.
736 EVT FromVT(MVT::Other);
737 if (NumSignBits == RegSize)
738 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
739 else if (NumZeroBits >= RegSize-1)
740 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
741 else if (NumSignBits > RegSize-8)
742 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
743 else if (NumZeroBits >= RegSize-8)
744 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
745 else if (NumSignBits > RegSize-16)
746 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
747 else if (NumZeroBits >= RegSize-16)
748 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
749 else if (NumSignBits > RegSize-32)
750 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
751 else if (NumZeroBits >= RegSize-32)
752 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
756 // Add an assertion node.
757 assert(FromVT != MVT::Other);
758 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
759 RegisterVT, P, DAG.getValueType(FromVT));
762 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
763 NumRegs, RegisterVT, ValueVT, V);
768 return DAG.getNode(ISD::MERGE_VALUES, dl,
769 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
770 &Values[0], ValueVTs.size());
773 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
774 /// specified value into the registers specified by this object. This uses
775 /// Chain/Flag as the input and updates them for the output Chain/Flag.
776 /// If the Flag pointer is NULL, no flag is used.
777 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
778 SDValue &Chain, SDValue *Flag,
779 const Value *V) const {
780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
782 // Get the list of the values's legal parts.
783 unsigned NumRegs = Regs.size();
784 SmallVector<SDValue, 8> Parts(NumRegs);
785 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
786 EVT ValueVT = ValueVTs[Value];
787 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
788 MVT RegisterVT = RegVTs[Value];
789 ISD::NodeType ExtendKind =
790 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
792 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
793 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
797 // Copy the parts into the registers.
798 SmallVector<SDValue, 8> Chains(NumRegs);
799 for (unsigned i = 0; i != NumRegs; ++i) {
802 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
804 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
805 *Flag = Part.getValue(1);
808 Chains[i] = Part.getValue(0);
811 if (NumRegs == 1 || Flag)
812 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
813 // flagged to it. That is the CopyToReg nodes and the user are considered
814 // a single scheduling unit. If we create a TokenFactor and return it as
815 // chain, then the TokenFactor is both a predecessor (operand) of the
816 // user as well as a successor (the TF operands are flagged to the user).
817 // c1, f1 = CopyToReg
818 // c2, f2 = CopyToReg
819 // c3 = TokenFactor c1, c2
822 Chain = Chains[NumRegs-1];
824 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
827 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
828 /// operand list. This adds the code marker and includes the number of
829 /// values added into it.
830 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
831 unsigned MatchingIdx,
833 std::vector<SDValue> &Ops) const {
834 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
836 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
838 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
839 else if (!Regs.empty() &&
840 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
841 // Put the register class of the virtual registers in the flag word. That
842 // way, later passes can recompute register class constraints for inline
843 // assembly as well as normal instructions.
844 // Don't do this for tied operands that can use the regclass information
846 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
847 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
848 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
851 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
854 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
855 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
856 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
857 MVT RegisterVT = RegVTs[Value];
858 for (unsigned i = 0; i != NumRegs; ++i) {
859 assert(Reg < Regs.size() && "Mismatch in # registers expected");
860 unsigned TheReg = Regs[Reg++];
861 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
863 // Notice if we clobbered the stack pointer. Yes, inline asm can do this.
864 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
865 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
866 MFI->setHasInlineAsmWithSPAdjust(true);
872 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
873 const TargetLibraryInfo *li) {
877 TD = DAG.getTarget().getDataLayout();
878 Context = DAG.getContext();
879 LPadToCallSiteMap.clear();
882 /// clear - Clear out the current SelectionDAG and the associated
883 /// state and prepare this SelectionDAGBuilder object to be used
884 /// for a new block. This doesn't clear out information about
885 /// additional blocks that are needed to complete switch lowering
886 /// or PHI node updating; that information is cleared out as it is
888 void SelectionDAGBuilder::clear() {
890 UnusedArgNodeMap.clear();
891 PendingLoads.clear();
892 PendingExports.clear();
895 SDNodeOrder = LowestSDNodeOrder;
898 /// clearDanglingDebugInfo - Clear the dangling debug information
899 /// map. This function is separated from the clear so that debug
900 /// information that is dangling in a basic block can be properly
901 /// resolved in a different basic block. This allows the
902 /// SelectionDAG to resolve dangling debug information attached
904 void SelectionDAGBuilder::clearDanglingDebugInfo() {
905 DanglingDebugInfoMap.clear();
908 /// getRoot - Return the current virtual root of the Selection DAG,
909 /// flushing any PendingLoad items. This must be done before emitting
910 /// a store or any other node that may need to be ordered after any
911 /// prior load instructions.
913 SDValue SelectionDAGBuilder::getRoot() {
914 if (PendingLoads.empty())
915 return DAG.getRoot();
917 if (PendingLoads.size() == 1) {
918 SDValue Root = PendingLoads[0];
920 PendingLoads.clear();
924 // Otherwise, we have to make a token factor node.
925 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
926 &PendingLoads[0], PendingLoads.size());
927 PendingLoads.clear();
932 /// getControlRoot - Similar to getRoot, but instead of flushing all the
933 /// PendingLoad items, flush all the PendingExports items. It is necessary
934 /// to do this before emitting a terminator instruction.
936 SDValue SelectionDAGBuilder::getControlRoot() {
937 SDValue Root = DAG.getRoot();
939 if (PendingExports.empty())
942 // Turn all of the CopyToReg chains into one factored node.
943 if (Root.getOpcode() != ISD::EntryToken) {
944 unsigned i = 0, e = PendingExports.size();
945 for (; i != e; ++i) {
946 assert(PendingExports[i].getNode()->getNumOperands() > 1);
947 if (PendingExports[i].getNode()->getOperand(0) == Root)
948 break; // Don't add the root if we already indirectly depend on it.
952 PendingExports.push_back(Root);
955 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
957 PendingExports.size());
958 PendingExports.clear();
963 void SelectionDAGBuilder::visit(const Instruction &I) {
964 // Set up outgoing PHI node register values before emitting the terminator.
965 if (isa<TerminatorInst>(&I))
966 HandlePHINodesInSuccessorBlocks(I.getParent());
972 visit(I.getOpcode(), I);
974 if (!isa<TerminatorInst>(&I) && !HasTailCall)
975 CopyToExportRegsIfNeeded(&I);
980 void SelectionDAGBuilder::visitPHI(const PHINode &) {
981 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
984 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
985 // Note: this doesn't use InstVisitor, because it has to work with
986 // ConstantExpr's in addition to instructions.
988 default: llvm_unreachable("Unknown instruction type encountered!");
989 // Build the switch statement using the Instruction.def file.
990 #define HANDLE_INST(NUM, OPCODE, CLASS) \
991 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
992 #include "llvm/IR/Instruction.def"
996 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
997 // generate the debug data structures now that we've seen its definition.
998 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
1000 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
1002 const DbgValueInst *DI = DDI.getDI();
1003 DebugLoc dl = DDI.getdl();
1004 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1005 MDNode *Variable = DI->getVariable();
1006 uint64_t Offset = DI->getOffset();
1008 if (Val.getNode()) {
1009 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
1010 SDV = DAG.getDbgValue(Variable, Val.getNode(),
1011 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
1012 DAG.AddDbgValue(SDV, Val.getNode(), false);
1015 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1016 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1020 /// getValue - Return an SDValue for the given Value.
1021 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1022 // If we already have an SDValue for this value, use it. It's important
1023 // to do this first, so that we don't create a CopyFromReg if we already
1024 // have a regular SDValue.
1025 SDValue &N = NodeMap[V];
1026 if (N.getNode()) return N;
1028 // If there's a virtual register allocated and initialized for this
1030 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1031 if (It != FuncInfo.ValueMap.end()) {
1032 unsigned InReg = It->second;
1033 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1034 InReg, V->getType());
1035 SDValue Chain = DAG.getEntryNode();
1036 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1037 resolveDanglingDebugInfo(V, N);
1041 // Otherwise create a new SDValue and remember it.
1042 SDValue Val = getValueImpl(V);
1044 resolveDanglingDebugInfo(V, Val);
1048 /// getNonRegisterValue - Return an SDValue for the given Value, but
1049 /// don't look in FuncInfo.ValueMap for a virtual register.
1050 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1051 // If we already have an SDValue for this value, use it.
1052 SDValue &N = NodeMap[V];
1053 if (N.getNode()) return N;
1055 // Otherwise create a new SDValue and remember it.
1056 SDValue Val = getValueImpl(V);
1058 resolveDanglingDebugInfo(V, Val);
1062 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1063 /// Create an SDValue for the given value.
1064 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1065 const TargetLowering *TLI = TM.getTargetLowering();
1067 if (const Constant *C = dyn_cast<Constant>(V)) {
1068 EVT VT = TLI->getValueType(V->getType(), true);
1070 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1071 return DAG.getConstant(*CI, VT);
1073 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1074 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1076 if (isa<ConstantPointerNull>(C)) {
1077 unsigned AS = V->getType()->getPointerAddressSpace();
1078 return DAG.getConstant(0, TLI->getPointerTy(AS));
1081 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1082 return DAG.getConstantFP(*CFP, VT);
1084 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1085 return DAG.getUNDEF(VT);
1087 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1088 visit(CE->getOpcode(), *CE);
1089 SDValue N1 = NodeMap[V];
1090 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1094 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1095 SmallVector<SDValue, 4> Constants;
1096 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1098 SDNode *Val = getValue(*OI).getNode();
1099 // If the operand is an empty aggregate, there are no values.
1101 // Add each leaf value from the operand to the Constants list
1102 // to form a flattened list of all the values.
1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1104 Constants.push_back(SDValue(Val, i));
1107 return DAG.getMergeValues(&Constants[0], Constants.size(),
1111 if (const ConstantDataSequential *CDS =
1112 dyn_cast<ConstantDataSequential>(C)) {
1113 SmallVector<SDValue, 4> Ops;
1114 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1115 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1116 // Add each leaf value from the operand to the Constants list
1117 // to form a flattened list of all the values.
1118 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1119 Ops.push_back(SDValue(Val, i));
1122 if (isa<ArrayType>(CDS->getType()))
1123 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1124 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1125 VT, &Ops[0], Ops.size());
1128 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1129 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1130 "Unknown struct or array constant!");
1132 SmallVector<EVT, 4> ValueVTs;
1133 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1134 unsigned NumElts = ValueVTs.size();
1136 return SDValue(); // empty struct
1137 SmallVector<SDValue, 4> Constants(NumElts);
1138 for (unsigned i = 0; i != NumElts; ++i) {
1139 EVT EltVT = ValueVTs[i];
1140 if (isa<UndefValue>(C))
1141 Constants[i] = DAG.getUNDEF(EltVT);
1142 else if (EltVT.isFloatingPoint())
1143 Constants[i] = DAG.getConstantFP(0, EltVT);
1145 Constants[i] = DAG.getConstant(0, EltVT);
1148 return DAG.getMergeValues(&Constants[0], NumElts,
1152 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1153 return DAG.getBlockAddress(BA, VT);
1155 VectorType *VecTy = cast<VectorType>(V->getType());
1156 unsigned NumElements = VecTy->getNumElements();
1158 // Now that we know the number and type of the elements, get that number of
1159 // elements into the Ops array based on what kind of constant it is.
1160 SmallVector<SDValue, 16> Ops;
1161 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1162 for (unsigned i = 0; i != NumElements; ++i)
1163 Ops.push_back(getValue(CV->getOperand(i)));
1165 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1166 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1169 if (EltVT.isFloatingPoint())
1170 Op = DAG.getConstantFP(0, EltVT);
1172 Op = DAG.getConstant(0, EltVT);
1173 Ops.assign(NumElements, Op);
1176 // Create a BUILD_VECTOR node.
1177 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1178 VT, &Ops[0], Ops.size());
1181 // If this is a static alloca, generate it as the frameindex instead of
1183 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1184 DenseMap<const AllocaInst*, int>::iterator SI =
1185 FuncInfo.StaticAllocaMap.find(AI);
1186 if (SI != FuncInfo.StaticAllocaMap.end())
1187 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1190 // If this is an instruction which fast-isel has deferred, select it now.
1191 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1192 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1193 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1194 SDValue Chain = DAG.getEntryNode();
1195 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V);
1198 llvm_unreachable("Can't get register for value!");
1201 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1202 const TargetLowering *TLI = TM.getTargetLowering();
1203 SDValue Chain = getControlRoot();
1204 SmallVector<ISD::OutputArg, 8> Outs;
1205 SmallVector<SDValue, 8> OutVals;
1207 if (!FuncInfo.CanLowerReturn) {
1208 unsigned DemoteReg = FuncInfo.DemoteRegister;
1209 const Function *F = I.getParent()->getParent();
1211 // Emit a store of the return value through the virtual register.
1212 // Leave Outs empty so that LowerReturn won't try to load return
1213 // registers the usual way.
1214 SmallVector<EVT, 1> PtrValueVTs;
1215 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1218 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1219 SDValue RetOp = getValue(I.getOperand(0));
1221 SmallVector<EVT, 4> ValueVTs;
1222 SmallVector<uint64_t, 4> Offsets;
1223 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1224 unsigned NumValues = ValueVTs.size();
1226 SmallVector<SDValue, 4> Chains(NumValues);
1227 for (unsigned i = 0; i != NumValues; ++i) {
1228 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1229 RetPtr.getValueType(), RetPtr,
1230 DAG.getIntPtrConstant(Offsets[i]));
1232 DAG.getStore(Chain, getCurSDLoc(),
1233 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1234 // FIXME: better loc info would be nice.
1235 Add, MachinePointerInfo(), false, false, 0);
1238 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1239 MVT::Other, &Chains[0], NumValues);
1240 } else if (I.getNumOperands() != 0) {
1241 SmallVector<EVT, 4> ValueVTs;
1242 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1243 unsigned NumValues = ValueVTs.size();
1245 SDValue RetOp = getValue(I.getOperand(0));
1246 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1247 EVT VT = ValueVTs[j];
1249 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1251 const Function *F = I.getParent()->getParent();
1252 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1254 ExtendKind = ISD::SIGN_EXTEND;
1255 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1257 ExtendKind = ISD::ZERO_EXTEND;
1259 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1260 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1262 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1263 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1264 SmallVector<SDValue, 4> Parts(NumParts);
1265 getCopyToParts(DAG, getCurSDLoc(),
1266 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1267 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1269 // 'inreg' on function refers to return value
1270 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1271 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1275 // Propagate extension type if any
1276 if (ExtendKind == ISD::SIGN_EXTEND)
1278 else if (ExtendKind == ISD::ZERO_EXTEND)
1281 for (unsigned i = 0; i < NumParts; ++i) {
1282 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1283 VT, /*isfixed=*/true, 0, 0));
1284 OutVals.push_back(Parts[i]);
1290 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1291 CallingConv::ID CallConv =
1292 DAG.getMachineFunction().getFunction()->getCallingConv();
1293 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1294 Outs, OutVals, getCurSDLoc(),
1297 // Verify that the target's LowerReturn behaved as expected.
1298 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1299 "LowerReturn didn't return a valid chain!");
1301 // Update the DAG with the new chain value resulting from return lowering.
1305 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1306 /// created for it, emit nodes to copy the value into the virtual
1308 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1310 if (V->getType()->isEmptyTy())
1313 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1314 if (VMI != FuncInfo.ValueMap.end()) {
1315 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1316 CopyValueToVirtualRegister(V, VMI->second);
1320 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1321 /// the current basic block, add it to ValueMap now so that we'll get a
1323 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1324 // No need to export constants.
1325 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1327 // Already exported?
1328 if (FuncInfo.isExportedInst(V)) return;
1330 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1331 CopyValueToVirtualRegister(V, Reg);
1334 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1335 const BasicBlock *FromBB) {
1336 // The operands of the setcc have to be in this block. We don't know
1337 // how to export them from some other block.
1338 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1339 // Can export from current BB.
1340 if (VI->getParent() == FromBB)
1343 // Is already exported, noop.
1344 return FuncInfo.isExportedInst(V);
1347 // If this is an argument, we can export it if the BB is the entry block or
1348 // if it is already exported.
1349 if (isa<Argument>(V)) {
1350 if (FromBB == &FromBB->getParent()->getEntryBlock())
1353 // Otherwise, can only export this if it is already exported.
1354 return FuncInfo.isExportedInst(V);
1357 // Otherwise, constants can always be exported.
1361 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1362 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1363 const MachineBasicBlock *Dst) const {
1364 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1367 const BasicBlock *SrcBB = Src->getBasicBlock();
1368 const BasicBlock *DstBB = Dst->getBasicBlock();
1369 return BPI->getEdgeWeight(SrcBB, DstBB);
1372 void SelectionDAGBuilder::
1373 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1374 uint32_t Weight /* = 0 */) {
1376 Weight = getEdgeWeight(Src, Dst);
1377 Src->addSuccessor(Dst, Weight);
1381 static bool InBlock(const Value *V, const BasicBlock *BB) {
1382 if (const Instruction *I = dyn_cast<Instruction>(V))
1383 return I->getParent() == BB;
1387 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1388 /// This function emits a branch and is used at the leaves of an OR or an
1389 /// AND operator tree.
1392 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1393 MachineBasicBlock *TBB,
1394 MachineBasicBlock *FBB,
1395 MachineBasicBlock *CurBB,
1396 MachineBasicBlock *SwitchBB,
1399 const BasicBlock *BB = CurBB->getBasicBlock();
1401 // If the leaf of the tree is a comparison, merge the condition into
1403 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1404 // The operands of the cmp have to be in this block. We don't know
1405 // how to export them from some other block. If this is the first block
1406 // of the sequence, no exporting is needed.
1407 if (CurBB == SwitchBB ||
1408 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1409 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1410 ISD::CondCode Condition;
1411 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1412 Condition = getICmpCondCode(IC->getPredicate());
1413 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1414 Condition = getFCmpCondCode(FC->getPredicate());
1415 if (TM.Options.NoNaNsFPMath)
1416 Condition = getFCmpCodeWithoutNaN(Condition);
1418 Condition = ISD::SETEQ; // silence warning.
1419 llvm_unreachable("Unknown compare instruction");
1422 CaseBlock CB(Condition, BOp->getOperand(0),
1423 BOp->getOperand(1), NULL, TBB, FBB, CurBB, TWeight, FWeight);
1424 SwitchCases.push_back(CB);
1429 // Create a CaseBlock record representing this branch.
1430 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1431 NULL, TBB, FBB, CurBB, TWeight, FWeight);
1432 SwitchCases.push_back(CB);
1435 /// Scale down both weights to fit into uint32_t.
1436 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1437 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1438 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1439 NewTrue = NewTrue / Scale;
1440 NewFalse = NewFalse / Scale;
1443 /// FindMergedConditions - If Cond is an expression like
1444 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1445 MachineBasicBlock *TBB,
1446 MachineBasicBlock *FBB,
1447 MachineBasicBlock *CurBB,
1448 MachineBasicBlock *SwitchBB,
1449 unsigned Opc, uint32_t TWeight,
1451 // If this node is not part of the or/and tree, emit it as a branch.
1452 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1453 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1454 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1455 BOp->getParent() != CurBB->getBasicBlock() ||
1456 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1457 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1458 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1463 // Create TmpBB after CurBB.
1464 MachineFunction::iterator BBI = CurBB;
1465 MachineFunction &MF = DAG.getMachineFunction();
1466 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1467 CurBB->getParent()->insert(++BBI, TmpBB);
1469 if (Opc == Instruction::Or) {
1470 // Codegen X | Y as:
1479 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1480 // The requirement is that
1481 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1482 // = TrueProb for orignal BB.
1483 // Assuming the orignal weights are A and B, one choice is to set BB1's
1484 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1486 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1487 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1488 // TmpBB, but the math is more complicated.
1490 uint64_t NewTrueWeight = TWeight;
1491 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1492 ScaleWeights(NewTrueWeight, NewFalseWeight);
1493 // Emit the LHS condition.
1494 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1495 NewTrueWeight, NewFalseWeight);
1497 NewTrueWeight = TWeight;
1498 NewFalseWeight = 2 * (uint64_t)FWeight;
1499 ScaleWeights(NewTrueWeight, NewFalseWeight);
1500 // Emit the RHS condition into TmpBB.
1501 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1502 NewTrueWeight, NewFalseWeight);
1504 assert(Opc == Instruction::And && "Unknown merge op!");
1505 // Codegen X & Y as:
1513 // This requires creation of TmpBB after CurBB.
1515 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1516 // The requirement is that
1517 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1518 // = FalseProb for orignal BB.
1519 // Assuming the orignal weights are A and B, one choice is to set BB1's
1520 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1522 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1524 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1525 uint64_t NewFalseWeight = FWeight;
1526 ScaleWeights(NewTrueWeight, NewFalseWeight);
1527 // Emit the LHS condition.
1528 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1529 NewTrueWeight, NewFalseWeight);
1531 NewTrueWeight = 2 * (uint64_t)TWeight;
1532 NewFalseWeight = FWeight;
1533 ScaleWeights(NewTrueWeight, NewFalseWeight);
1534 // Emit the RHS condition into TmpBB.
1535 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1536 NewTrueWeight, NewFalseWeight);
1540 /// If the set of cases should be emitted as a series of branches, return true.
1541 /// If we should emit this as a bunch of and/or'd together conditions, return
1544 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1545 if (Cases.size() != 2) return true;
1547 // If this is two comparisons of the same values or'd or and'd together, they
1548 // will get folded into a single comparison, so don't emit two blocks.
1549 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1550 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1551 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1552 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1556 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1557 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1558 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1559 Cases[0].CC == Cases[1].CC &&
1560 isa<Constant>(Cases[0].CmpRHS) &&
1561 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1562 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1564 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1571 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1572 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1574 // Update machine-CFG edges.
1575 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1577 // Figure out which block is immediately after the current one.
1578 MachineBasicBlock *NextBlock = 0;
1579 MachineFunction::iterator BBI = BrMBB;
1580 if (++BBI != FuncInfo.MF->end())
1583 if (I.isUnconditional()) {
1584 // Update machine-CFG edges.
1585 BrMBB->addSuccessor(Succ0MBB);
1587 // If this is not a fall-through branch, emit the branch.
1588 if (Succ0MBB != NextBlock)
1589 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1590 MVT::Other, getControlRoot(),
1591 DAG.getBasicBlock(Succ0MBB)));
1596 // If this condition is one of the special cases we handle, do special stuff
1598 const Value *CondVal = I.getCondition();
1599 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1601 // If this is a series of conditions that are or'd or and'd together, emit
1602 // this as a sequence of branches instead of setcc's with and/or operations.
1603 // As long as jumps are not expensive, this should improve performance.
1604 // For example, instead of something like:
1617 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1618 if (!TM.getTargetLowering()->isJumpExpensive() &&
1620 (BOp->getOpcode() == Instruction::And ||
1621 BOp->getOpcode() == Instruction::Or)) {
1622 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1623 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1624 getEdgeWeight(BrMBB, Succ1MBB));
1625 // If the compares in later blocks need to use values not currently
1626 // exported from this block, export them now. This block should always
1627 // be the first entry.
1628 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1630 // Allow some cases to be rejected.
1631 if (ShouldEmitAsBranches(SwitchCases)) {
1632 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1633 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1634 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1637 // Emit the branch for this block.
1638 visitSwitchCase(SwitchCases[0], BrMBB);
1639 SwitchCases.erase(SwitchCases.begin());
1643 // Okay, we decided not to do this, remove any inserted MBB's and clear
1645 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1646 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1648 SwitchCases.clear();
1652 // Create a CaseBlock record representing this branch.
1653 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1654 NULL, Succ0MBB, Succ1MBB, BrMBB);
1656 // Use visitSwitchCase to actually insert the fast branch sequence for this
1658 visitSwitchCase(CB, BrMBB);
1661 /// visitSwitchCase - Emits the necessary code to represent a single node in
1662 /// the binary search tree resulting from lowering a switch instruction.
1663 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1664 MachineBasicBlock *SwitchBB) {
1666 SDValue CondLHS = getValue(CB.CmpLHS);
1667 SDLoc dl = getCurSDLoc();
1669 // Build the setcc now.
1670 if (CB.CmpMHS == NULL) {
1671 // Fold "(X == true)" to X and "(X == false)" to !X to
1672 // handle common cases produced by branch lowering.
1673 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1674 CB.CC == ISD::SETEQ)
1676 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1677 CB.CC == ISD::SETEQ) {
1678 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1679 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1681 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1683 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1685 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1686 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1688 SDValue CmpOp = getValue(CB.CmpMHS);
1689 EVT VT = CmpOp.getValueType();
1691 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1692 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1695 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1696 VT, CmpOp, DAG.getConstant(Low, VT));
1697 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1698 DAG.getConstant(High-Low, VT), ISD::SETULE);
1702 // Update successor info
1703 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1704 // TrueBB and FalseBB are always different unless the incoming IR is
1705 // degenerate. This only happens when running llc on weird IR.
1706 if (CB.TrueBB != CB.FalseBB)
1707 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1709 // Set NextBlock to be the MBB immediately after the current one, if any.
1710 // This is used to avoid emitting unnecessary branches to the next block.
1711 MachineBasicBlock *NextBlock = 0;
1712 MachineFunction::iterator BBI = SwitchBB;
1713 if (++BBI != FuncInfo.MF->end())
1716 // If the lhs block is the next block, invert the condition so that we can
1717 // fall through to the lhs instead of the rhs block.
1718 if (CB.TrueBB == NextBlock) {
1719 std::swap(CB.TrueBB, CB.FalseBB);
1720 SDValue True = DAG.getConstant(1, Cond.getValueType());
1721 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1724 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1725 MVT::Other, getControlRoot(), Cond,
1726 DAG.getBasicBlock(CB.TrueBB));
1728 // Insert the false branch. Do this even if it's a fall through branch,
1729 // this makes it easier to do DAG optimizations which require inverting
1730 // the branch condition.
1731 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1732 DAG.getBasicBlock(CB.FalseBB));
1734 DAG.setRoot(BrCond);
1737 /// visitJumpTable - Emit JumpTable node in the current MBB
1738 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1739 // Emit the code for the jump table
1740 assert(JT.Reg != -1U && "Should lower JT Header first!");
1741 EVT PTy = TM.getTargetLowering()->getPointerTy();
1742 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1744 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1745 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1746 MVT::Other, Index.getValue(1),
1748 DAG.setRoot(BrJumpTable);
1751 /// visitJumpTableHeader - This function emits necessary code to produce index
1752 /// in the JumpTable from switch case.
1753 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1754 JumpTableHeader &JTH,
1755 MachineBasicBlock *SwitchBB) {
1756 // Subtract the lowest switch case value from the value being switched on and
1757 // conditional branch to default mbb if the result is greater than the
1758 // difference between smallest and largest cases.
1759 SDValue SwitchOp = getValue(JTH.SValue);
1760 EVT VT = SwitchOp.getValueType();
1761 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1762 DAG.getConstant(JTH.First, VT));
1764 // The SDNode we just created, which holds the value being switched on minus
1765 // the smallest case value, needs to be copied to a virtual register so it
1766 // can be used as an index into the jump table in a subsequent basic block.
1767 // This value may be smaller or larger than the target's pointer type, and
1768 // therefore require extension or truncating.
1769 const TargetLowering *TLI = TM.getTargetLowering();
1770 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1772 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1773 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1774 JumpTableReg, SwitchOp);
1775 JT.Reg = JumpTableReg;
1777 // Emit the range check for the jump table, and branch to the default block
1778 // for the switch statement if the value being switched on exceeds the largest
1779 // case in the switch.
1780 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1781 TLI->getSetCCResultType(*DAG.getContext(),
1782 Sub.getValueType()),
1784 DAG.getConstant(JTH.Last - JTH.First,VT),
1787 // Set NextBlock to be the MBB immediately after the current one, if any.
1788 // This is used to avoid emitting unnecessary branches to the next block.
1789 MachineBasicBlock *NextBlock = 0;
1790 MachineFunction::iterator BBI = SwitchBB;
1792 if (++BBI != FuncInfo.MF->end())
1795 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1796 MVT::Other, CopyTo, CMP,
1797 DAG.getBasicBlock(JT.Default));
1799 if (JT.MBB != NextBlock)
1800 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1801 DAG.getBasicBlock(JT.MBB));
1803 DAG.setRoot(BrCond);
1806 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1807 /// tail spliced into a stack protector check success bb.
1809 /// For a high level explanation of how this fits into the stack protector
1810 /// generation see the comment on the declaration of class
1811 /// StackProtectorDescriptor.
1812 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1813 MachineBasicBlock *ParentBB) {
1815 // First create the loads to the guard/stack slot for the comparison.
1816 const TargetLowering *TLI = TM.getTargetLowering();
1817 EVT PtrTy = TLI->getPointerTy();
1819 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1820 int FI = MFI->getStackProtectorIndex();
1822 const Value *IRGuard = SPD.getGuard();
1823 SDValue GuardPtr = getValue(IRGuard);
1824 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1827 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1828 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1829 GuardPtr, MachinePointerInfo(IRGuard, 0),
1830 true, false, false, Align);
1832 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1834 MachinePointerInfo::getFixedStack(FI),
1835 true, false, false, Align);
1837 // Perform the comparison via a subtract/getsetcc.
1838 EVT VT = Guard.getValueType();
1839 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1841 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1842 TLI->getSetCCResultType(*DAG.getContext(),
1843 Sub.getValueType()),
1844 Sub, DAG.getConstant(0, VT),
1847 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1848 // branch to failure MBB.
1849 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1850 MVT::Other, StackSlot.getOperand(0),
1851 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1852 // Otherwise branch to success MBB.
1853 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1855 DAG.getBasicBlock(SPD.getSuccessMBB()));
1860 /// Codegen the failure basic block for a stack protector check.
1862 /// A failure stack protector machine basic block consists simply of a call to
1863 /// __stack_chk_fail().
1865 /// For a high level explanation of how this fits into the stack protector
1866 /// generation see the comment on the declaration of class
1867 /// StackProtectorDescriptor.
1869 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1870 const TargetLowering *TLI = TM.getTargetLowering();
1871 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1872 MVT::isVoid, 0, 0, false, getCurSDLoc(),
1873 false, false).second;
1877 /// visitBitTestHeader - This function emits necessary code to produce value
1878 /// suitable for "bit tests"
1879 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1880 MachineBasicBlock *SwitchBB) {
1881 // Subtract the minimum value
1882 SDValue SwitchOp = getValue(B.SValue);
1883 EVT VT = SwitchOp.getValueType();
1884 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1885 DAG.getConstant(B.First, VT));
1888 const TargetLowering *TLI = TM.getTargetLowering();
1889 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1890 TLI->getSetCCResultType(*DAG.getContext(),
1891 Sub.getValueType()),
1892 Sub, DAG.getConstant(B.Range, VT),
1895 // Determine the type of the test operands.
1896 bool UsePtrType = false;
1897 if (!TLI->isTypeLegal(VT))
1900 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1901 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1902 // Switch table case range are encoded into series of masks.
1903 // Just use pointer type, it's guaranteed to fit.
1909 VT = TLI->getPointerTy();
1910 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1913 B.RegVT = VT.getSimpleVT();
1914 B.Reg = FuncInfo.CreateReg(B.RegVT);
1915 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1918 // Set NextBlock to be the MBB immediately after the current one, if any.
1919 // This is used to avoid emitting unnecessary branches to the next block.
1920 MachineBasicBlock *NextBlock = 0;
1921 MachineFunction::iterator BBI = SwitchBB;
1922 if (++BBI != FuncInfo.MF->end())
1925 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1927 addSuccessorWithWeight(SwitchBB, B.Default);
1928 addSuccessorWithWeight(SwitchBB, MBB);
1930 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1931 MVT::Other, CopyTo, RangeCmp,
1932 DAG.getBasicBlock(B.Default));
1934 if (MBB != NextBlock)
1935 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1936 DAG.getBasicBlock(MBB));
1938 DAG.setRoot(BrRange);
1941 /// visitBitTestCase - this function produces one "bit test"
1942 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1943 MachineBasicBlock* NextMBB,
1944 uint32_t BranchWeightToNext,
1947 MachineBasicBlock *SwitchBB) {
1949 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1952 unsigned PopCount = CountPopulation_64(B.Mask);
1953 const TargetLowering *TLI = TM.getTargetLowering();
1954 if (PopCount == 1) {
1955 // Testing for a single bit; just compare the shift count with what it
1956 // would need to be to shift a 1 bit in that position.
1957 Cmp = DAG.getSetCC(getCurSDLoc(),
1958 TLI->getSetCCResultType(*DAG.getContext(), VT),
1960 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1962 } else if (PopCount == BB.Range) {
1963 // There is only one zero bit in the range, test for it directly.
1964 Cmp = DAG.getSetCC(getCurSDLoc(),
1965 TLI->getSetCCResultType(*DAG.getContext(), VT),
1967 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1970 // Make desired shift
1971 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1972 DAG.getConstant(1, VT), ShiftOp);
1974 // Emit bit tests and jumps
1975 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1976 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1977 Cmp = DAG.getSetCC(getCurSDLoc(),
1978 TLI->getSetCCResultType(*DAG.getContext(), VT),
1979 AndOp, DAG.getConstant(0, VT),
1983 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1984 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1985 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1986 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1988 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1989 MVT::Other, getControlRoot(),
1990 Cmp, DAG.getBasicBlock(B.TargetBB));
1992 // Set NextBlock to be the MBB immediately after the current one, if any.
1993 // This is used to avoid emitting unnecessary branches to the next block.
1994 MachineBasicBlock *NextBlock = 0;
1995 MachineFunction::iterator BBI = SwitchBB;
1996 if (++BBI != FuncInfo.MF->end())
1999 if (NextMBB != NextBlock)
2000 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
2001 DAG.getBasicBlock(NextMBB));
2006 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2007 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2009 // Retrieve successors.
2010 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2011 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2013 const Value *Callee(I.getCalledValue());
2014 const Function *Fn = dyn_cast<Function>(Callee);
2015 if (isa<InlineAsm>(Callee))
2017 else if (Fn && Fn->isIntrinsic()) {
2018 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2019 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2021 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2023 // If the value of the invoke is used outside of its defining block, make it
2024 // available as a virtual register.
2025 CopyToExportRegsIfNeeded(&I);
2027 // Update successor info
2028 addSuccessorWithWeight(InvokeMBB, Return);
2029 addSuccessorWithWeight(InvokeMBB, LandingPad);
2031 // Drop into normal successor.
2032 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2033 MVT::Other, getControlRoot(),
2034 DAG.getBasicBlock(Return)));
2037 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2038 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2041 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2042 assert(FuncInfo.MBB->isLandingPad() &&
2043 "Call to landingpad not in landing pad!");
2045 MachineBasicBlock *MBB = FuncInfo.MBB;
2046 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2047 AddLandingPadInfo(LP, MMI, MBB);
2049 // If there aren't registers to copy the values into (e.g., during SjLj
2050 // exceptions), then don't bother to create these DAG nodes.
2051 const TargetLowering *TLI = TM.getTargetLowering();
2052 if (TLI->getExceptionPointerRegister() == 0 &&
2053 TLI->getExceptionSelectorRegister() == 0)
2056 SmallVector<EVT, 2> ValueVTs;
2057 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2058 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2060 // Get the two live-in registers as SDValues. The physregs have already been
2061 // copied into virtual registers.
2063 Ops[0] = DAG.getZExtOrTrunc(
2064 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2065 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2066 getCurSDLoc(), ValueVTs[0]);
2067 Ops[1] = DAG.getZExtOrTrunc(
2068 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2069 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2070 getCurSDLoc(), ValueVTs[1]);
2073 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2074 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
2079 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2080 /// small case ranges).
2081 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2082 CaseRecVector& WorkList,
2084 MachineBasicBlock *Default,
2085 MachineBasicBlock *SwitchBB) {
2086 // Size is the number of Cases represented by this range.
2087 size_t Size = CR.Range.second - CR.Range.first;
2091 // Get the MachineFunction which holds the current MBB. This is used when
2092 // inserting any additional MBBs necessary to represent the switch.
2093 MachineFunction *CurMF = FuncInfo.MF;
2095 // Figure out which block is immediately after the current one.
2096 MachineBasicBlock *NextBlock = 0;
2097 MachineFunction::iterator BBI = CR.CaseBB;
2099 if (++BBI != FuncInfo.MF->end())
2102 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2103 // If any two of the cases has the same destination, and if one value
2104 // is the same as the other, but has one bit unset that the other has set,
2105 // use bit manipulation to do two compares at once. For example:
2106 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2107 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2108 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2109 if (Size == 2 && CR.CaseBB == SwitchBB) {
2110 Case &Small = *CR.Range.first;
2111 Case &Big = *(CR.Range.second-1);
2113 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2114 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2115 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2117 // Check that there is only one bit different.
2118 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2119 (SmallValue | BigValue) == BigValue) {
2120 // Isolate the common bit.
2121 APInt CommonBit = BigValue & ~SmallValue;
2122 assert((SmallValue | CommonBit) == BigValue &&
2123 CommonBit.countPopulation() == 1 && "Not a common bit?");
2125 SDValue CondLHS = getValue(SV);
2126 EVT VT = CondLHS.getValueType();
2127 SDLoc DL = getCurSDLoc();
2129 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2130 DAG.getConstant(CommonBit, VT));
2131 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2132 Or, DAG.getConstant(BigValue, VT),
2135 // Update successor info.
2136 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2137 addSuccessorWithWeight(SwitchBB, Small.BB,
2138 Small.ExtraWeight + Big.ExtraWeight);
2139 addSuccessorWithWeight(SwitchBB, Default,
2140 // The default destination is the first successor in IR.
2141 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2143 // Insert the true branch.
2144 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2145 getControlRoot(), Cond,
2146 DAG.getBasicBlock(Small.BB));
2148 // Insert the false branch.
2149 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2150 DAG.getBasicBlock(Default));
2152 DAG.setRoot(BrCond);
2158 // Order cases by weight so the most likely case will be checked first.
2159 uint32_t UnhandledWeights = 0;
2161 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2162 uint32_t IWeight = I->ExtraWeight;
2163 UnhandledWeights += IWeight;
2164 for (CaseItr J = CR.Range.first; J < I; ++J) {
2165 uint32_t JWeight = J->ExtraWeight;
2166 if (IWeight > JWeight)
2171 // Rearrange the case blocks so that the last one falls through if possible.
2172 Case &BackCase = *(CR.Range.second-1);
2174 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2175 // The last case block won't fall through into 'NextBlock' if we emit the
2176 // branches in this order. See if rearranging a case value would help.
2177 // We start at the bottom as it's the case with the least weight.
2178 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2179 if (I->BB == NextBlock) {
2180 std::swap(*I, BackCase);
2185 // Create a CaseBlock record representing a conditional branch to
2186 // the Case's target mbb if the value being switched on SV is equal
2188 MachineBasicBlock *CurBlock = CR.CaseBB;
2189 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2190 MachineBasicBlock *FallThrough;
2192 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2193 CurMF->insert(BBI, FallThrough);
2195 // Put SV in a virtual register to make it available from the new blocks.
2196 ExportFromCurrentBlock(SV);
2198 // If the last case doesn't match, go to the default block.
2199 FallThrough = Default;
2202 const Value *RHS, *LHS, *MHS;
2204 if (I->High == I->Low) {
2205 // This is just small small case range :) containing exactly 1 case
2207 LHS = SV; RHS = I->High; MHS = NULL;
2210 LHS = I->Low; MHS = SV; RHS = I->High;
2213 // The false weight should be sum of all un-handled cases.
2214 UnhandledWeights -= I->ExtraWeight;
2215 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2217 /* trueweight */ I->ExtraWeight,
2218 /* falseweight */ UnhandledWeights);
2220 // If emitting the first comparison, just call visitSwitchCase to emit the
2221 // code into the current block. Otherwise, push the CaseBlock onto the
2222 // vector to be later processed by SDISel, and insert the node's MBB
2223 // before the next MBB.
2224 if (CurBlock == SwitchBB)
2225 visitSwitchCase(CB, SwitchBB);
2227 SwitchCases.push_back(CB);
2229 CurBlock = FallThrough;
2235 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2236 return TLI.supportJumpTables() &&
2237 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2238 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2241 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2242 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2243 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2244 return (LastExt - FirstExt + 1ULL);
2247 /// handleJTSwitchCase - Emit jumptable for current switch case range
2248 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2249 CaseRecVector &WorkList,
2251 MachineBasicBlock *Default,
2252 MachineBasicBlock *SwitchBB) {
2253 Case& FrontCase = *CR.Range.first;
2254 Case& BackCase = *(CR.Range.second-1);
2256 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2257 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2259 APInt TSize(First.getBitWidth(), 0);
2260 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2263 const TargetLowering *TLI = TM.getTargetLowering();
2264 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2267 APInt Range = ComputeRange(First, Last);
2268 // The density is TSize / Range. Require at least 40%.
2269 // It should not be possible for IntTSize to saturate for sane code, but make
2270 // sure we handle Range saturation correctly.
2271 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2272 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2273 if (IntTSize * 10 < IntRange * 4)
2276 DEBUG(dbgs() << "Lowering jump table\n"
2277 << "First entry: " << First << ". Last entry: " << Last << '\n'
2278 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2280 // Get the MachineFunction which holds the current MBB. This is used when
2281 // inserting any additional MBBs necessary to represent the switch.
2282 MachineFunction *CurMF = FuncInfo.MF;
2284 // Figure out which block is immediately after the current one.
2285 MachineFunction::iterator BBI = CR.CaseBB;
2288 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2290 // Create a new basic block to hold the code for loading the address
2291 // of the jump table, and jumping to it. Update successor information;
2292 // we will either branch to the default case for the switch, or the jump
2294 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2295 CurMF->insert(BBI, JumpTableBB);
2297 addSuccessorWithWeight(CR.CaseBB, Default);
2298 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2300 // Build a vector of destination BBs, corresponding to each target
2301 // of the jump table. If the value of the jump table slot corresponds to
2302 // a case statement, push the case's BB onto the vector, otherwise, push
2304 std::vector<MachineBasicBlock*> DestBBs;
2306 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2307 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2308 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2310 if (Low.sle(TEI) && TEI.sle(High)) {
2311 DestBBs.push_back(I->BB);
2315 DestBBs.push_back(Default);
2319 // Calculate weight for each unique destination in CR.
2320 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2322 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2323 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2324 DestWeights.find(I->BB);
2325 if (Itr != DestWeights.end())
2326 Itr->second += I->ExtraWeight;
2328 DestWeights[I->BB] = I->ExtraWeight;
2331 // Update successor info. Add one edge to each unique successor.
2332 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2333 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2334 E = DestBBs.end(); I != E; ++I) {
2335 if (!SuccsHandled[(*I)->getNumber()]) {
2336 SuccsHandled[(*I)->getNumber()] = true;
2337 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2338 DestWeights.find(*I);
2339 addSuccessorWithWeight(JumpTableBB, *I,
2340 Itr != DestWeights.end() ? Itr->second : 0);
2344 // Create a jump table index for this jump table.
2345 unsigned JTEncoding = TLI->getJumpTableEncoding();
2346 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2347 ->createJumpTableIndex(DestBBs);
2349 // Set the jump table information so that we can codegen it as a second
2350 // MachineBasicBlock
2351 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2352 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2353 if (CR.CaseBB == SwitchBB)
2354 visitJumpTableHeader(JT, JTH, SwitchBB);
2356 JTCases.push_back(JumpTableBlock(JTH, JT));
2360 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2362 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2363 CaseRecVector& WorkList,
2365 MachineBasicBlock* Default,
2366 MachineBasicBlock* SwitchBB) {
2367 // Get the MachineFunction which holds the current MBB. This is used when
2368 // inserting any additional MBBs necessary to represent the switch.
2369 MachineFunction *CurMF = FuncInfo.MF;
2371 // Figure out which block is immediately after the current one.
2372 MachineFunction::iterator BBI = CR.CaseBB;
2375 Case& FrontCase = *CR.Range.first;
2376 Case& BackCase = *(CR.Range.second-1);
2377 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2379 // Size is the number of Cases represented by this range.
2380 unsigned Size = CR.Range.second - CR.Range.first;
2382 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2383 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2385 CaseItr Pivot = CR.Range.first + Size/2;
2387 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2388 // (heuristically) allow us to emit JumpTable's later.
2389 APInt TSize(First.getBitWidth(), 0);
2390 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2394 APInt LSize = FrontCase.size();
2395 APInt RSize = TSize-LSize;
2396 DEBUG(dbgs() << "Selecting best pivot: \n"
2397 << "First: " << First << ", Last: " << Last <<'\n'
2398 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2399 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2401 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2402 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2403 APInt Range = ComputeRange(LEnd, RBegin);
2404 assert((Range - 2ULL).isNonNegative() &&
2405 "Invalid case distance");
2406 // Use volatile double here to avoid excess precision issues on some hosts,
2407 // e.g. that use 80-bit X87 registers.
2408 volatile double LDensity =
2409 (double)LSize.roundToDouble() /
2410 (LEnd - First + 1ULL).roundToDouble();
2411 volatile double RDensity =
2412 (double)RSize.roundToDouble() /
2413 (Last - RBegin + 1ULL).roundToDouble();
2414 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2415 // Should always split in some non-trivial place
2416 DEBUG(dbgs() <<"=>Step\n"
2417 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2418 << "LDensity: " << LDensity
2419 << ", RDensity: " << RDensity << '\n'
2420 << "Metric: " << Metric << '\n');
2421 if (FMetric < Metric) {
2424 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2431 const TargetLowering *TLI = TM.getTargetLowering();
2432 if (areJTsAllowed(*TLI)) {
2433 // If our case is dense we *really* should handle it earlier!
2434 assert((FMetric > 0) && "Should handle dense range earlier!");
2436 Pivot = CR.Range.first + Size/2;
2439 CaseRange LHSR(CR.Range.first, Pivot);
2440 CaseRange RHSR(Pivot, CR.Range.second);
2441 const Constant *C = Pivot->Low;
2442 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2444 // We know that we branch to the LHS if the Value being switched on is
2445 // less than the Pivot value, C. We use this to optimize our binary
2446 // tree a bit, by recognizing that if SV is greater than or equal to the
2447 // LHS's Case Value, and that Case Value is exactly one less than the
2448 // Pivot's Value, then we can branch directly to the LHS's Target,
2449 // rather than creating a leaf node for it.
2450 if ((LHSR.second - LHSR.first) == 1 &&
2451 LHSR.first->High == CR.GE &&
2452 cast<ConstantInt>(C)->getValue() ==
2453 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2454 TrueBB = LHSR.first->BB;
2456 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2457 CurMF->insert(BBI, TrueBB);
2458 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2460 // Put SV in a virtual register to make it available from the new blocks.
2461 ExportFromCurrentBlock(SV);
2464 // Similar to the optimization above, if the Value being switched on is
2465 // known to be less than the Constant CR.LT, and the current Case Value
2466 // is CR.LT - 1, then we can branch directly to the target block for
2467 // the current Case Value, rather than emitting a RHS leaf node for it.
2468 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2469 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2470 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2471 FalseBB = RHSR.first->BB;
2473 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2474 CurMF->insert(BBI, FalseBB);
2475 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2477 // Put SV in a virtual register to make it available from the new blocks.
2478 ExportFromCurrentBlock(SV);
2481 // Create a CaseBlock record representing a conditional branch to
2482 // the LHS node if the value being switched on SV is less than C.
2483 // Otherwise, branch to LHS.
2484 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2486 if (CR.CaseBB == SwitchBB)
2487 visitSwitchCase(CB, SwitchBB);
2489 SwitchCases.push_back(CB);
2494 /// handleBitTestsSwitchCase - if current case range has few destination and
2495 /// range span less, than machine word bitwidth, encode case range into series
2496 /// of masks and emit bit tests with these masks.
2497 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2498 CaseRecVector& WorkList,
2500 MachineBasicBlock* Default,
2501 MachineBasicBlock* SwitchBB) {
2502 const TargetLowering *TLI = TM.getTargetLowering();
2503 EVT PTy = TLI->getPointerTy();
2504 unsigned IntPtrBits = PTy.getSizeInBits();
2506 Case& FrontCase = *CR.Range.first;
2507 Case& BackCase = *(CR.Range.second-1);
2509 // Get the MachineFunction which holds the current MBB. This is used when
2510 // inserting any additional MBBs necessary to represent the switch.
2511 MachineFunction *CurMF = FuncInfo.MF;
2513 // If target does not have legal shift left, do not emit bit tests at all.
2514 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2518 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2520 // Single case counts one, case range - two.
2521 numCmps += (I->Low == I->High ? 1 : 2);
2524 // Count unique destinations
2525 SmallSet<MachineBasicBlock*, 4> Dests;
2526 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2527 Dests.insert(I->BB);
2528 if (Dests.size() > 3)
2529 // Don't bother the code below, if there are too much unique destinations
2532 DEBUG(dbgs() << "Total number of unique destinations: "
2533 << Dests.size() << '\n'
2534 << "Total number of comparisons: " << numCmps << '\n');
2536 // Compute span of values.
2537 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2538 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2539 APInt cmpRange = maxValue - minValue;
2541 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2542 << "Low bound: " << minValue << '\n'
2543 << "High bound: " << maxValue << '\n');
2545 if (cmpRange.uge(IntPtrBits) ||
2546 (!(Dests.size() == 1 && numCmps >= 3) &&
2547 !(Dests.size() == 2 && numCmps >= 5) &&
2548 !(Dests.size() >= 3 && numCmps >= 6)))
2551 DEBUG(dbgs() << "Emitting bit tests\n");
2552 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2554 // Optimize the case where all the case values fit in a
2555 // word without having to subtract minValue. In this case,
2556 // we can optimize away the subtraction.
2557 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2558 cmpRange = maxValue;
2560 lowBound = minValue;
2563 CaseBitsVector CasesBits;
2564 unsigned i, count = 0;
2566 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2567 MachineBasicBlock* Dest = I->BB;
2568 for (i = 0; i < count; ++i)
2569 if (Dest == CasesBits[i].BB)
2573 assert((count < 3) && "Too much destinations to test!");
2574 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2578 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2579 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2581 uint64_t lo = (lowValue - lowBound).getZExtValue();
2582 uint64_t hi = (highValue - lowBound).getZExtValue();
2583 CasesBits[i].ExtraWeight += I->ExtraWeight;
2585 for (uint64_t j = lo; j <= hi; j++) {
2586 CasesBits[i].Mask |= 1ULL << j;
2587 CasesBits[i].Bits++;
2591 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2595 // Figure out which block is immediately after the current one.
2596 MachineFunction::iterator BBI = CR.CaseBB;
2599 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2601 DEBUG(dbgs() << "Cases:\n");
2602 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2603 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2604 << ", Bits: " << CasesBits[i].Bits
2605 << ", BB: " << CasesBits[i].BB << '\n');
2607 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2608 CurMF->insert(BBI, CaseBB);
2609 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2611 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2613 // Put SV in a virtual register to make it available from the new blocks.
2614 ExportFromCurrentBlock(SV);
2617 BitTestBlock BTB(lowBound, cmpRange, SV,
2618 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2619 CR.CaseBB, Default, BTC);
2621 if (CR.CaseBB == SwitchBB)
2622 visitBitTestHeader(BTB, SwitchBB);
2624 BitTestCases.push_back(BTB);
2629 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2630 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2631 const SwitchInst& SI) {
2634 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2635 // Start with "simple" cases
2636 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2638 const BasicBlock *SuccBB = i.getCaseSuccessor();
2639 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2641 uint32_t ExtraWeight =
2642 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2644 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2645 SMBB, ExtraWeight));
2647 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2649 // Merge case into clusters
2650 if (Cases.size() >= 2)
2651 // Must recompute end() each iteration because it may be
2652 // invalidated by erase if we hold on to it
2653 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2654 J != Cases.end(); ) {
2655 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2656 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2657 MachineBasicBlock* nextBB = J->BB;
2658 MachineBasicBlock* currentBB = I->BB;
2660 // If the two neighboring cases go to the same destination, merge them
2661 // into a single case.
2662 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2664 I->ExtraWeight += J->ExtraWeight;
2671 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2672 if (I->Low != I->High)
2673 // A range counts double, since it requires two compares.
2680 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2681 MachineBasicBlock *Last) {
2683 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2684 if (JTCases[i].first.HeaderBB == First)
2685 JTCases[i].first.HeaderBB = Last;
2687 // Update BitTestCases.
2688 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2689 if (BitTestCases[i].Parent == First)
2690 BitTestCases[i].Parent = Last;
2693 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2694 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2696 // Figure out which block is immediately after the current one.
2697 MachineBasicBlock *NextBlock = 0;
2698 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2700 // If there is only the default destination, branch to it if it is not the
2701 // next basic block. Otherwise, just fall through.
2702 if (!SI.getNumCases()) {
2703 // Update machine-CFG edges.
2705 // If this is not a fall-through branch, emit the branch.
2706 SwitchMBB->addSuccessor(Default);
2707 if (Default != NextBlock)
2708 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2709 MVT::Other, getControlRoot(),
2710 DAG.getBasicBlock(Default)));
2715 // If there are any non-default case statements, create a vector of Cases
2716 // representing each one, and sort the vector so that we can efficiently
2717 // create a binary search tree from them.
2719 size_t numCmps = Clusterify(Cases, SI);
2720 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2721 << ". Total compares: " << numCmps << '\n');
2724 // Get the Value to be switched on and default basic blocks, which will be
2725 // inserted into CaseBlock records, representing basic blocks in the binary
2727 const Value *SV = SI.getCondition();
2729 // Push the initial CaseRec onto the worklist
2730 CaseRecVector WorkList;
2731 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2732 CaseRange(Cases.begin(),Cases.end())));
2734 while (!WorkList.empty()) {
2735 // Grab a record representing a case range to process off the worklist
2736 CaseRec CR = WorkList.back();
2737 WorkList.pop_back();
2739 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2742 // If the range has few cases (two or less) emit a series of specific
2744 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2747 // If the switch has more than N blocks, and is at least 40% dense, and the
2748 // target supports indirect branches, then emit a jump table rather than
2749 // lowering the switch to a binary tree of conditional branches.
2750 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2751 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2754 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2755 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2756 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2760 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2761 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2763 // Update machine-CFG edges with unique successors.
2764 SmallSet<BasicBlock*, 32> Done;
2765 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2766 BasicBlock *BB = I.getSuccessor(i);
2767 bool Inserted = Done.insert(BB);
2771 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2772 addSuccessorWithWeight(IndirectBrMBB, Succ);
2775 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2776 MVT::Other, getControlRoot(),
2777 getValue(I.getAddress())));
2780 void SelectionDAGBuilder::visitFSub(const User &I) {
2781 // -0.0 - X --> fneg
2782 Type *Ty = I.getType();
2783 if (isa<Constant>(I.getOperand(0)) &&
2784 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2785 SDValue Op2 = getValue(I.getOperand(1));
2786 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2787 Op2.getValueType(), Op2));
2791 visitBinary(I, ISD::FSUB);
2794 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2795 SDValue Op1 = getValue(I.getOperand(0));
2796 SDValue Op2 = getValue(I.getOperand(1));
2797 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2798 Op1.getValueType(), Op1, Op2));
2801 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2802 SDValue Op1 = getValue(I.getOperand(0));
2803 SDValue Op2 = getValue(I.getOperand(1));
2805 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2807 // Coerce the shift amount to the right type if we can.
2808 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2809 unsigned ShiftSize = ShiftTy.getSizeInBits();
2810 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2811 SDLoc DL = getCurSDLoc();
2813 // If the operand is smaller than the shift count type, promote it.
2814 if (ShiftSize > Op2Size)
2815 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2817 // If the operand is larger than the shift count type but the shift
2818 // count type has enough bits to represent any shift value, truncate
2819 // it now. This is a common case and it exposes the truncate to
2820 // optimization early.
2821 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2822 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2823 // Otherwise we'll need to temporarily settle for some other convenient
2824 // type. Type legalization will make adjustments once the shiftee is split.
2826 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2829 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2830 Op1.getValueType(), Op1, Op2));
2833 void SelectionDAGBuilder::visitSDiv(const User &I) {
2834 SDValue Op1 = getValue(I.getOperand(0));
2835 SDValue Op2 = getValue(I.getOperand(1));
2837 // Turn exact SDivs into multiplications.
2838 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2840 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2841 !isa<ConstantSDNode>(Op1) &&
2842 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2843 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2844 getCurSDLoc(), DAG));
2846 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2850 void SelectionDAGBuilder::visitICmp(const User &I) {
2851 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2852 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2853 predicate = IC->getPredicate();
2854 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2855 predicate = ICmpInst::Predicate(IC->getPredicate());
2856 SDValue Op1 = getValue(I.getOperand(0));
2857 SDValue Op2 = getValue(I.getOperand(1));
2858 ISD::CondCode Opcode = getICmpCondCode(predicate);
2860 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2861 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2864 void SelectionDAGBuilder::visitFCmp(const User &I) {
2865 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2866 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2867 predicate = FC->getPredicate();
2868 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2869 predicate = FCmpInst::Predicate(FC->getPredicate());
2870 SDValue Op1 = getValue(I.getOperand(0));
2871 SDValue Op2 = getValue(I.getOperand(1));
2872 ISD::CondCode Condition = getFCmpCondCode(predicate);
2873 if (TM.Options.NoNaNsFPMath)
2874 Condition = getFCmpCodeWithoutNaN(Condition);
2875 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2876 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2879 void SelectionDAGBuilder::visitSelect(const User &I) {
2880 SmallVector<EVT, 4> ValueVTs;
2881 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2882 unsigned NumValues = ValueVTs.size();
2883 if (NumValues == 0) return;
2885 SmallVector<SDValue, 4> Values(NumValues);
2886 SDValue Cond = getValue(I.getOperand(0));
2887 SDValue TrueVal = getValue(I.getOperand(1));
2888 SDValue FalseVal = getValue(I.getOperand(2));
2889 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2890 ISD::VSELECT : ISD::SELECT;
2892 for (unsigned i = 0; i != NumValues; ++i)
2893 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2894 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2896 SDValue(TrueVal.getNode(),
2897 TrueVal.getResNo() + i),
2898 SDValue(FalseVal.getNode(),
2899 FalseVal.getResNo() + i));
2901 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2902 DAG.getVTList(&ValueVTs[0], NumValues),
2903 &Values[0], NumValues));
2906 void SelectionDAGBuilder::visitTrunc(const User &I) {
2907 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2908 SDValue N = getValue(I.getOperand(0));
2909 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2910 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2913 void SelectionDAGBuilder::visitZExt(const User &I) {
2914 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2915 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2916 SDValue N = getValue(I.getOperand(0));
2917 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2918 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2921 void SelectionDAGBuilder::visitSExt(const User &I) {
2922 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2923 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2924 SDValue N = getValue(I.getOperand(0));
2925 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2926 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2929 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2930 // FPTrunc is never a no-op cast, no need to check
2931 SDValue N = getValue(I.getOperand(0));
2932 const TargetLowering *TLI = TM.getTargetLowering();
2933 EVT DestVT = TLI->getValueType(I.getType());
2934 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2936 DAG.getTargetConstant(0, TLI->getPointerTy())));
2939 void SelectionDAGBuilder::visitFPExt(const User &I) {
2940 // FPExt is never a no-op cast, no need to check
2941 SDValue N = getValue(I.getOperand(0));
2942 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2943 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2946 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2947 // FPToUI is never a no-op cast, no need to check
2948 SDValue N = getValue(I.getOperand(0));
2949 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2950 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2953 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2954 // FPToSI is never a no-op cast, no need to check
2955 SDValue N = getValue(I.getOperand(0));
2956 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2957 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2960 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2961 // UIToFP is never a no-op cast, no need to check
2962 SDValue N = getValue(I.getOperand(0));
2963 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2964 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2967 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2968 // SIToFP is never a no-op cast, no need to check
2969 SDValue N = getValue(I.getOperand(0));
2970 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2971 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2974 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2975 // What to do depends on the size of the integer and the size of the pointer.
2976 // We can either truncate, zero extend, or no-op, accordingly.
2977 SDValue N = getValue(I.getOperand(0));
2978 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2979 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2982 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2983 // What to do depends on the size of the integer and the size of the pointer.
2984 // We can either truncate, zero extend, or no-op, accordingly.
2985 SDValue N = getValue(I.getOperand(0));
2986 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2987 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2990 void SelectionDAGBuilder::visitBitCast(const User &I) {
2991 SDValue N = getValue(I.getOperand(0));
2992 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2994 // BitCast assures us that source and destination are the same size so this is
2995 // either a BITCAST or a no-op.
2996 if (DestVT != N.getValueType())
2997 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2998 DestVT, N)); // convert types.
2999 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3000 // might fold any kind of constant expression to an integer constant and that
3001 // is not what we are looking for. Only regcognize a bitcast of a genuine
3002 // constant integer as an opaque constant.
3003 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3004 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3007 setValue(&I, N); // noop cast.
3010 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3011 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3012 const Value *SV = I.getOperand(0);
3013 SDValue N = getValue(SV);
3014 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3016 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3017 unsigned DestAS = I.getType()->getPointerAddressSpace();
3019 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3020 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3025 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3027 SDValue InVec = getValue(I.getOperand(0));
3028 SDValue InVal = getValue(I.getOperand(1));
3029 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3030 getCurSDLoc(), TLI.getVectorIdxTy());
3031 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3032 TM.getTargetLowering()->getValueType(I.getType()),
3033 InVec, InVal, InIdx));
3036 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3038 SDValue InVec = getValue(I.getOperand(0));
3039 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3040 getCurSDLoc(), TLI.getVectorIdxTy());
3041 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3042 TM.getTargetLowering()->getValueType(I.getType()),
3046 // Utility for visitShuffleVector - Return true if every element in Mask,
3047 // beginning from position Pos and ending in Pos+Size, falls within the
3048 // specified sequential range [L, L+Pos). or is undef.
3049 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3050 unsigned Pos, unsigned Size, int Low) {
3051 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3052 if (Mask[i] >= 0 && Mask[i] != Low)
3057 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3058 SDValue Src1 = getValue(I.getOperand(0));
3059 SDValue Src2 = getValue(I.getOperand(1));
3061 SmallVector<int, 8> Mask;
3062 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3063 unsigned MaskNumElts = Mask.size();
3065 const TargetLowering *TLI = TM.getTargetLowering();
3066 EVT VT = TLI->getValueType(I.getType());
3067 EVT SrcVT = Src1.getValueType();
3068 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3070 if (SrcNumElts == MaskNumElts) {
3071 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3076 // Normalize the shuffle vector since mask and vector length don't match.
3077 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3078 // Mask is longer than the source vectors and is a multiple of the source
3079 // vectors. We can use concatenate vector to make the mask and vectors
3081 if (SrcNumElts*2 == MaskNumElts) {
3082 // First check for Src1 in low and Src2 in high
3083 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3084 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3085 // The shuffle is concatenating two vectors together.
3086 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3090 // Then check for Src2 in low and Src1 in high
3091 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3092 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3093 // The shuffle is concatenating two vectors together.
3094 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3100 // Pad both vectors with undefs to make them the same length as the mask.
3101 unsigned NumConcat = MaskNumElts / SrcNumElts;
3102 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3103 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3104 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3106 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3107 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3111 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3113 &MOps1[0], NumConcat);
3114 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3116 &MOps2[0], NumConcat);
3118 // Readjust mask for new input vector length.
3119 SmallVector<int, 8> MappedOps;
3120 for (unsigned i = 0; i != MaskNumElts; ++i) {
3122 if (Idx >= (int)SrcNumElts)
3123 Idx -= SrcNumElts - MaskNumElts;
3124 MappedOps.push_back(Idx);
3127 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3132 if (SrcNumElts > MaskNumElts) {
3133 // Analyze the access pattern of the vector to see if we can extract
3134 // two subvectors and do the shuffle. The analysis is done by calculating
3135 // the range of elements the mask access on both vectors.
3136 int MinRange[2] = { static_cast<int>(SrcNumElts),
3137 static_cast<int>(SrcNumElts)};
3138 int MaxRange[2] = {-1, -1};
3140 for (unsigned i = 0; i != MaskNumElts; ++i) {
3146 if (Idx >= (int)SrcNumElts) {
3150 if (Idx > MaxRange[Input])
3151 MaxRange[Input] = Idx;
3152 if (Idx < MinRange[Input])
3153 MinRange[Input] = Idx;
3156 // Check if the access is smaller than the vector size and can we find
3157 // a reasonable extract index.
3158 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3160 int StartIdx[2]; // StartIdx to extract from
3161 for (unsigned Input = 0; Input < 2; ++Input) {
3162 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3163 RangeUse[Input] = 0; // Unused
3164 StartIdx[Input] = 0;
3168 // Find a good start index that is a multiple of the mask length. Then
3169 // see if the rest of the elements are in range.
3170 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3171 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3172 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3173 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3176 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3177 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3180 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3181 // Extract appropriate subvector and generate a vector shuffle
3182 for (unsigned Input = 0; Input < 2; ++Input) {
3183 SDValue &Src = Input == 0 ? Src1 : Src2;
3184 if (RangeUse[Input] == 0)
3185 Src = DAG.getUNDEF(VT);
3187 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3188 Src, DAG.getConstant(StartIdx[Input],
3189 TLI->getVectorIdxTy()));
3192 // Calculate new mask.
3193 SmallVector<int, 8> MappedOps;
3194 for (unsigned i = 0; i != MaskNumElts; ++i) {
3197 if (Idx < (int)SrcNumElts)
3200 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3202 MappedOps.push_back(Idx);
3205 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3211 // We can't use either concat vectors or extract subvectors so fall back to
3212 // replacing the shuffle with extract and build vector.
3213 // to insert and build vector.
3214 EVT EltVT = VT.getVectorElementType();
3215 EVT IdxVT = TLI->getVectorIdxTy();
3216 SmallVector<SDValue,8> Ops;
3217 for (unsigned i = 0; i != MaskNumElts; ++i) {
3222 Res = DAG.getUNDEF(EltVT);
3224 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3225 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3227 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3228 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3234 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3235 VT, &Ops[0], Ops.size()));
3238 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3239 const Value *Op0 = I.getOperand(0);
3240 const Value *Op1 = I.getOperand(1);
3241 Type *AggTy = I.getType();
3242 Type *ValTy = Op1->getType();
3243 bool IntoUndef = isa<UndefValue>(Op0);
3244 bool FromUndef = isa<UndefValue>(Op1);
3246 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3248 const TargetLowering *TLI = TM.getTargetLowering();
3249 SmallVector<EVT, 4> AggValueVTs;
3250 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3251 SmallVector<EVT, 4> ValValueVTs;
3252 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3254 unsigned NumAggValues = AggValueVTs.size();
3255 unsigned NumValValues = ValValueVTs.size();
3256 SmallVector<SDValue, 4> Values(NumAggValues);
3258 SDValue Agg = getValue(Op0);
3260 // Copy the beginning value(s) from the original aggregate.
3261 for (; i != LinearIndex; ++i)
3262 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3263 SDValue(Agg.getNode(), Agg.getResNo() + i);
3264 // Copy values from the inserted value(s).
3266 SDValue Val = getValue(Op1);
3267 for (; i != LinearIndex + NumValValues; ++i)
3268 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3269 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3271 // Copy remaining value(s) from the original aggregate.
3272 for (; i != NumAggValues; ++i)
3273 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3274 SDValue(Agg.getNode(), Agg.getResNo() + i);
3276 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3277 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3278 &Values[0], NumAggValues));
3281 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3282 const Value *Op0 = I.getOperand(0);
3283 Type *AggTy = Op0->getType();
3284 Type *ValTy = I.getType();
3285 bool OutOfUndef = isa<UndefValue>(Op0);
3287 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3289 const TargetLowering *TLI = TM.getTargetLowering();
3290 SmallVector<EVT, 4> ValValueVTs;
3291 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3293 unsigned NumValValues = ValValueVTs.size();
3295 // Ignore a extractvalue that produces an empty object
3296 if (!NumValValues) {
3297 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3301 SmallVector<SDValue, 4> Values(NumValValues);
3303 SDValue Agg = getValue(Op0);
3304 // Copy out the selected value(s).
3305 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3306 Values[i - LinearIndex] =
3308 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3309 SDValue(Agg.getNode(), Agg.getResNo() + i);
3311 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3312 DAG.getVTList(&ValValueVTs[0], NumValValues),
3313 &Values[0], NumValValues));
3316 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3317 Value *Op0 = I.getOperand(0);
3318 // Note that the pointer operand may be a vector of pointers. Take the scalar
3319 // element which holds a pointer.
3320 Type *Ty = Op0->getType()->getScalarType();
3321 unsigned AS = Ty->getPointerAddressSpace();
3322 SDValue N = getValue(Op0);
3324 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3326 const Value *Idx = *OI;
3327 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3328 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3331 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3332 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3333 DAG.getConstant(Offset, N.getValueType()));
3336 Ty = StTy->getElementType(Field);
3338 Ty = cast<SequentialType>(Ty)->getElementType();
3340 // If this is a constant subscript, handle it quickly.
3341 const TargetLowering *TLI = TM.getTargetLowering();
3342 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3343 if (CI->isZero()) continue;
3345 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3347 EVT PTy = TLI->getPointerTy(AS);
3348 unsigned PtrBits = PTy.getSizeInBits();
3350 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3351 DAG.getConstant(Offs, MVT::i64));
3353 OffsVal = DAG.getConstant(Offs, PTy);
3355 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3360 // N = N + Idx * ElementSize;
3361 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3362 TD->getTypeAllocSize(Ty));
3363 SDValue IdxN = getValue(Idx);
3365 // If the index is smaller or larger than intptr_t, truncate or extend
3367 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3369 // If this is a multiply by a power of two, turn it into a shl
3370 // immediately. This is a very common case.
3371 if (ElementSize != 1) {
3372 if (ElementSize.isPowerOf2()) {
3373 unsigned Amt = ElementSize.logBase2();
3374 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3375 N.getValueType(), IdxN,
3376 DAG.getConstant(Amt, IdxN.getValueType()));
3378 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3379 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3380 N.getValueType(), IdxN, Scale);
3384 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3385 N.getValueType(), N, IdxN);
3392 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3393 // If this is a fixed sized alloca in the entry block of the function,
3394 // allocate it statically on the stack.
3395 if (FuncInfo.StaticAllocaMap.count(&I))
3396 return; // getValue will auto-populate this.
3398 Type *Ty = I.getAllocatedType();
3399 const TargetLowering *TLI = TM.getTargetLowering();
3400 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3402 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3405 SDValue AllocSize = getValue(I.getArraySize());
3407 EVT IntPtr = TLI->getPointerTy();
3408 if (AllocSize.getValueType() != IntPtr)
3409 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3411 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3413 DAG.getConstant(TySize, IntPtr));
3415 // Handle alignment. If the requested alignment is less than or equal to
3416 // the stack alignment, ignore it. If the size is greater than or equal to
3417 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3418 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3419 if (Align <= StackAlign)
3422 // Round the size of the allocation up to the stack alignment size
3423 // by add SA-1 to the size.
3424 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3425 AllocSize.getValueType(), AllocSize,
3426 DAG.getIntPtrConstant(StackAlign-1));
3428 // Mask out the low bits for alignment purposes.
3429 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3430 AllocSize.getValueType(), AllocSize,
3431 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3433 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3434 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3435 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3438 DAG.setRoot(DSA.getValue(1));
3440 // Inform the Frame Information that we have just allocated a variable-sized
3442 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, &I);
3445 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3447 return visitAtomicLoad(I);
3449 const Value *SV = I.getOperand(0);
3450 SDValue Ptr = getValue(SV);
3452 Type *Ty = I.getType();
3454 bool isVolatile = I.isVolatile();
3455 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3456 bool isInvariant = I.getMetadata("invariant.load") != 0;
3457 unsigned Alignment = I.getAlignment();
3458 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3459 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3461 SmallVector<EVT, 4> ValueVTs;
3462 SmallVector<uint64_t, 4> Offsets;
3463 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3464 unsigned NumValues = ValueVTs.size();
3469 bool ConstantMemory = false;
3470 if (isVolatile || NumValues > MaxParallelChains)
3471 // Serialize volatile loads with other side effects.
3473 else if (AA->pointsToConstantMemory(
3474 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3475 // Do not serialize (non-volatile) loads of constant memory with anything.
3476 Root = DAG.getEntryNode();
3477 ConstantMemory = true;
3479 // Do not serialize non-volatile loads against each other.
3480 Root = DAG.getRoot();
3483 const TargetLowering *TLI = TM.getTargetLowering();
3485 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3487 SmallVector<SDValue, 4> Values(NumValues);
3488 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3490 EVT PtrVT = Ptr.getValueType();
3491 unsigned ChainI = 0;
3492 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3493 // Serializing loads here may result in excessive register pressure, and
3494 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3495 // could recover a bit by hoisting nodes upward in the chain by recognizing
3496 // they are side-effect free or do not alias. The optimizer should really
3497 // avoid this case by converting large object/array copies to llvm.memcpy
3498 // (MaxParallelChains should always remain as failsafe).
3499 if (ChainI == MaxParallelChains) {
3500 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3501 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3502 MVT::Other, &Chains[0], ChainI);
3506 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3508 DAG.getConstant(Offsets[i], PtrVT));
3509 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3510 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3511 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3515 Chains[ChainI] = L.getValue(1);
3518 if (!ConstantMemory) {
3519 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3520 MVT::Other, &Chains[0], ChainI);
3524 PendingLoads.push_back(Chain);
3527 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3528 DAG.getVTList(&ValueVTs[0], NumValues),
3529 &Values[0], NumValues));
3532 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3534 return visitAtomicStore(I);
3536 const Value *SrcV = I.getOperand(0);
3537 const Value *PtrV = I.getOperand(1);
3539 SmallVector<EVT, 4> ValueVTs;
3540 SmallVector<uint64_t, 4> Offsets;
3541 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3542 unsigned NumValues = ValueVTs.size();
3546 // Get the lowered operands. Note that we do this after
3547 // checking if NumResults is zero, because with zero results
3548 // the operands won't have values in the map.
3549 SDValue Src = getValue(SrcV);
3550 SDValue Ptr = getValue(PtrV);
3552 SDValue Root = getRoot();
3553 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3555 EVT PtrVT = Ptr.getValueType();
3556 bool isVolatile = I.isVolatile();
3557 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3558 unsigned Alignment = I.getAlignment();
3559 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3561 unsigned ChainI = 0;
3562 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3563 // See visitLoad comments.
3564 if (ChainI == MaxParallelChains) {
3565 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3566 MVT::Other, &Chains[0], ChainI);
3570 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3571 DAG.getConstant(Offsets[i], PtrVT));
3572 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3573 SDValue(Src.getNode(), Src.getResNo() + i),
3574 Add, MachinePointerInfo(PtrV, Offsets[i]),
3575 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3576 Chains[ChainI] = St;
3579 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3580 MVT::Other, &Chains[0], ChainI);
3581 DAG.setRoot(StoreNode);
3584 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3585 SynchronizationScope Scope,
3586 bool Before, SDLoc dl,
3588 const TargetLowering &TLI) {
3589 // Fence, if necessary
3591 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3593 else if (Order == Acquire || Order == Monotonic)
3596 if (Order == AcquireRelease)
3598 else if (Order == Release || Order == Monotonic)
3603 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3604 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3605 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3608 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3609 SDLoc dl = getCurSDLoc();
3610 AtomicOrdering Order = I.getOrdering();
3611 SynchronizationScope Scope = I.getSynchScope();
3613 SDValue InChain = getRoot();
3615 const TargetLowering *TLI = TM.getTargetLowering();
3616 if (TLI->getInsertFencesForAtomic())
3617 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3621 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3622 getValue(I.getCompareOperand()).getSimpleValueType(),
3624 getValue(I.getPointerOperand()),
3625 getValue(I.getCompareOperand()),
3626 getValue(I.getNewValOperand()),
3627 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3628 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3631 SDValue OutChain = L.getValue(1);
3633 if (TLI->getInsertFencesForAtomic())
3634 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3638 DAG.setRoot(OutChain);
3641 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3642 SDLoc dl = getCurSDLoc();
3644 switch (I.getOperation()) {
3645 default: llvm_unreachable("Unknown atomicrmw operation");
3646 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3647 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3648 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3649 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3650 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3651 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3652 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3653 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3654 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3655 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3656 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3658 AtomicOrdering Order = I.getOrdering();
3659 SynchronizationScope Scope = I.getSynchScope();
3661 SDValue InChain = getRoot();
3663 const TargetLowering *TLI = TM.getTargetLowering();
3664 if (TLI->getInsertFencesForAtomic())
3665 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3669 DAG.getAtomic(NT, dl,
3670 getValue(I.getValOperand()).getSimpleValueType(),
3672 getValue(I.getPointerOperand()),
3673 getValue(I.getValOperand()),
3674 I.getPointerOperand(), 0 /* Alignment */,
3675 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3678 SDValue OutChain = L.getValue(1);
3680 if (TLI->getInsertFencesForAtomic())
3681 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3685 DAG.setRoot(OutChain);
3688 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3689 SDLoc dl = getCurSDLoc();
3690 const TargetLowering *TLI = TM.getTargetLowering();
3693 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3694 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3695 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3698 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3699 SDLoc dl = getCurSDLoc();
3700 AtomicOrdering Order = I.getOrdering();
3701 SynchronizationScope Scope = I.getSynchScope();
3703 SDValue InChain = getRoot();
3705 const TargetLowering *TLI = TM.getTargetLowering();
3706 EVT VT = TLI->getValueType(I.getType());
3708 if (I.getAlignment() < VT.getSizeInBits() / 8)
3709 report_fatal_error("Cannot generate unaligned atomic load");
3711 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3713 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3714 getValue(I.getPointerOperand()),
3715 I.getPointerOperand(), I.getAlignment(),
3716 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3719 SDValue OutChain = L.getValue(1);
3721 if (TLI->getInsertFencesForAtomic())
3722 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3726 DAG.setRoot(OutChain);
3729 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3730 SDLoc dl = getCurSDLoc();
3732 AtomicOrdering Order = I.getOrdering();
3733 SynchronizationScope Scope = I.getSynchScope();
3735 SDValue InChain = getRoot();
3737 const TargetLowering *TLI = TM.getTargetLowering();
3738 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3740 if (I.getAlignment() < VT.getSizeInBits() / 8)
3741 report_fatal_error("Cannot generate unaligned atomic store");
3743 if (TLI->getInsertFencesForAtomic())
3744 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3748 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3750 getValue(I.getPointerOperand()),
3751 getValue(I.getValueOperand()),
3752 I.getPointerOperand(), I.getAlignment(),
3753 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3756 if (TLI->getInsertFencesForAtomic())
3757 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3760 DAG.setRoot(OutChain);
3763 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3765 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3766 unsigned Intrinsic) {
3767 bool HasChain = !I.doesNotAccessMemory();
3768 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3770 // Build the operand list.
3771 SmallVector<SDValue, 8> Ops;
3772 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3774 // We don't need to serialize loads against other loads.
3775 Ops.push_back(DAG.getRoot());
3777 Ops.push_back(getRoot());
3781 // Info is set by getTgtMemInstrinsic
3782 TargetLowering::IntrinsicInfo Info;
3783 const TargetLowering *TLI = TM.getTargetLowering();
3784 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3786 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3787 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3788 Info.opc == ISD::INTRINSIC_W_CHAIN)
3789 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3791 // Add all operands of the call to the operand list.
3792 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3793 SDValue Op = getValue(I.getArgOperand(i));
3797 SmallVector<EVT, 4> ValueVTs;
3798 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3801 ValueVTs.push_back(MVT::Other);
3803 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3807 if (IsTgtIntrinsic) {
3808 // This is target intrinsic that touches memory
3809 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3810 VTs, &Ops[0], Ops.size(),
3812 MachinePointerInfo(Info.ptrVal, Info.offset),
3813 Info.align, Info.vol,
3814 Info.readMem, Info.writeMem);
3815 } else if (!HasChain) {
3816 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3817 VTs, &Ops[0], Ops.size());
3818 } else if (!I.getType()->isVoidTy()) {
3819 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3820 VTs, &Ops[0], Ops.size());
3822 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3823 VTs, &Ops[0], Ops.size());
3827 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3829 PendingLoads.push_back(Chain);
3834 if (!I.getType()->isVoidTy()) {
3835 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3836 EVT VT = TLI->getValueType(PTy);
3837 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3840 setValue(&I, Result);
3844 /// GetSignificand - Get the significand and build it into a floating-point
3845 /// number with exponent of 1:
3847 /// Op = (Op & 0x007fffff) | 0x3f800000;
3849 /// where Op is the hexadecimal representation of floating point value.
3851 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3852 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3853 DAG.getConstant(0x007fffff, MVT::i32));
3854 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3855 DAG.getConstant(0x3f800000, MVT::i32));
3856 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3859 /// GetExponent - Get the exponent:
3861 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3863 /// where Op is the hexadecimal representation of floating point value.
3865 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3867 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3868 DAG.getConstant(0x7f800000, MVT::i32));
3869 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3870 DAG.getConstant(23, TLI.getPointerTy()));
3871 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3872 DAG.getConstant(127, MVT::i32));
3873 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3876 /// getF32Constant - Get 32-bit floating point constant.
3878 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3879 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3883 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3884 /// limited-precision mode.
3885 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3886 const TargetLowering &TLI) {
3887 if (Op.getValueType() == MVT::f32 &&
3888 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3890 // Put the exponent in the right bit position for later addition to the
3893 // #define LOG2OFe 1.4426950f
3894 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3895 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3896 getF32Constant(DAG, 0x3fb8aa3b));
3897 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3899 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3900 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3901 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3903 // IntegerPartOfX <<= 23;
3904 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3905 DAG.getConstant(23, TLI.getPointerTy()));
3907 SDValue TwoToFracPartOfX;
3908 if (LimitFloatPrecision <= 6) {
3909 // For floating-point precision of 6:
3911 // TwoToFractionalPartOfX =
3913 // (0.735607626f + 0.252464424f * x) * x;
3915 // error 0.0144103317, which is 6 bits
3916 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3917 getF32Constant(DAG, 0x3e814304));
3918 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3919 getF32Constant(DAG, 0x3f3c50c8));
3920 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3921 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3922 getF32Constant(DAG, 0x3f7f5e7e));
3923 } else if (LimitFloatPrecision <= 12) {
3924 // For floating-point precision of 12:
3926 // TwoToFractionalPartOfX =
3929 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3931 // 0.000107046256 error, which is 13 to 14 bits
3932 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0x3da235e3));
3934 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3935 getF32Constant(DAG, 0x3e65b8f3));
3936 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3937 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3938 getF32Constant(DAG, 0x3f324b07));
3939 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3940 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3941 getF32Constant(DAG, 0x3f7ff8fd));
3942 } else { // LimitFloatPrecision <= 18
3943 // For floating-point precision of 18:
3945 // TwoToFractionalPartOfX =
3949 // (0.554906021e-1f +
3950 // (0.961591928e-2f +
3951 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3953 // error 2.47208000*10^(-7), which is better than 18 bits
3954 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3955 getF32Constant(DAG, 0x3924b03e));
3956 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3957 getF32Constant(DAG, 0x3ab24b87));
3958 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3959 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3960 getF32Constant(DAG, 0x3c1d8c17));
3961 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3962 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3963 getF32Constant(DAG, 0x3d634a1d));
3964 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3965 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3966 getF32Constant(DAG, 0x3e75fe14));
3967 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3968 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3969 getF32Constant(DAG, 0x3f317234));
3970 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3971 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3972 getF32Constant(DAG, 0x3f800000));
3975 // Add the exponent into the result in integer domain.
3976 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3977 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3978 DAG.getNode(ISD::ADD, dl, MVT::i32,
3979 t13, IntegerPartOfX));
3982 // No special expansion.
3983 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3986 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3987 /// limited-precision mode.
3988 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3989 const TargetLowering &TLI) {
3990 if (Op.getValueType() == MVT::f32 &&
3991 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3992 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3994 // Scale the exponent by log(2) [0.69314718f].
3995 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3996 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3997 getF32Constant(DAG, 0x3f317218));
3999 // Get the significand and build it into a floating-point number with
4001 SDValue X = GetSignificand(DAG, Op1, dl);
4003 SDValue LogOfMantissa;
4004 if (LimitFloatPrecision <= 6) {
4005 // For floating-point precision of 6:
4009 // (1.4034025f - 0.23903021f * x) * x;
4011 // error 0.0034276066, which is better than 8 bits
4012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4013 getF32Constant(DAG, 0xbe74c456));
4014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4015 getF32Constant(DAG, 0x3fb3a2b1));
4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4017 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4018 getF32Constant(DAG, 0x3f949a29));
4019 } else if (LimitFloatPrecision <= 12) {
4020 // For floating-point precision of 12:
4026 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4028 // error 0.000061011436, which is 14 bits
4029 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4030 getF32Constant(DAG, 0xbd67b6d6));
4031 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4032 getF32Constant(DAG, 0x3ee4f4b8));
4033 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4034 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4035 getF32Constant(DAG, 0x3fbc278b));
4036 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4037 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4038 getF32Constant(DAG, 0x40348e95));
4039 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4040 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4041 getF32Constant(DAG, 0x3fdef31a));
4042 } else { // LimitFloatPrecision <= 18
4043 // For floating-point precision of 18:
4051 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4053 // error 0.0000023660568, which is better than 18 bits
4054 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4055 getF32Constant(DAG, 0xbc91e5ac));
4056 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4057 getF32Constant(DAG, 0x3e4350aa));
4058 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4059 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4060 getF32Constant(DAG, 0x3f60d3e3));
4061 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4062 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4063 getF32Constant(DAG, 0x4011cdf0));
4064 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4065 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4066 getF32Constant(DAG, 0x406cfd1c));
4067 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4068 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4069 getF32Constant(DAG, 0x408797cb));
4070 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4071 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4072 getF32Constant(DAG, 0x4006dcab));
4075 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4078 // No special expansion.
4079 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4082 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4083 /// limited-precision mode.
4084 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4085 const TargetLowering &TLI) {
4086 if (Op.getValueType() == MVT::f32 &&
4087 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4088 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4090 // Get the exponent.
4091 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4093 // Get the significand and build it into a floating-point number with
4095 SDValue X = GetSignificand(DAG, Op1, dl);
4097 // Different possible minimax approximations of significand in
4098 // floating-point for various degrees of accuracy over [1,2].
4099 SDValue Log2ofMantissa;
4100 if (LimitFloatPrecision <= 6) {
4101 // For floating-point precision of 6:
4103 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4105 // error 0.0049451742, which is more than 7 bits
4106 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4107 getF32Constant(DAG, 0xbeb08fe0));
4108 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4109 getF32Constant(DAG, 0x40019463));
4110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4111 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4112 getF32Constant(DAG, 0x3fd6633d));
4113 } else if (LimitFloatPrecision <= 12) {
4114 // For floating-point precision of 12:
4120 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4122 // error 0.0000876136000, which is better than 13 bits
4123 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4124 getF32Constant(DAG, 0xbda7262e));
4125 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4126 getF32Constant(DAG, 0x3f25280b));
4127 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4128 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4129 getF32Constant(DAG, 0x4007b923));
4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4131 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4132 getF32Constant(DAG, 0x40823e2f));
4133 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4134 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4135 getF32Constant(DAG, 0x4020d29c));
4136 } else { // LimitFloatPrecision <= 18
4137 // For floating-point precision of 18:
4146 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4148 // error 0.0000018516, which is better than 18 bits
4149 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4150 getF32Constant(DAG, 0xbcd2769e));
4151 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4152 getF32Constant(DAG, 0x3e8ce0b9));
4153 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4154 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4155 getF32Constant(DAG, 0x3fa22ae7));
4156 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4157 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4158 getF32Constant(DAG, 0x40525723));
4159 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4160 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4161 getF32Constant(DAG, 0x40aaf200));
4162 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4163 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4164 getF32Constant(DAG, 0x40c39dad));
4165 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4166 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4167 getF32Constant(DAG, 0x4042902c));
4170 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4173 // No special expansion.
4174 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4177 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4178 /// limited-precision mode.
4179 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4180 const TargetLowering &TLI) {
4181 if (Op.getValueType() == MVT::f32 &&
4182 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4183 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4185 // Scale the exponent by log10(2) [0.30102999f].
4186 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4187 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4188 getF32Constant(DAG, 0x3e9a209a));
4190 // Get the significand and build it into a floating-point number with
4192 SDValue X = GetSignificand(DAG, Op1, dl);
4194 SDValue Log10ofMantissa;
4195 if (LimitFloatPrecision <= 6) {
4196 // For floating-point precision of 6:
4198 // Log10ofMantissa =
4200 // (0.60948995f - 0.10380950f * x) * x;
4202 // error 0.0014886165, which is 6 bits
4203 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4204 getF32Constant(DAG, 0xbdd49a13));
4205 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4206 getF32Constant(DAG, 0x3f1c0789));
4207 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4208 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4209 getF32Constant(DAG, 0x3f011300));
4210 } else if (LimitFloatPrecision <= 12) {
4211 // For floating-point precision of 12:
4213 // Log10ofMantissa =
4216 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4218 // error 0.00019228036, which is better than 12 bits
4219 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4220 getF32Constant(DAG, 0x3d431f31));
4221 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4222 getF32Constant(DAG, 0x3ea21fb2));
4223 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4224 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4225 getF32Constant(DAG, 0x3f6ae232));
4226 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4227 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4228 getF32Constant(DAG, 0x3f25f7c3));
4229 } else { // LimitFloatPrecision <= 18
4230 // For floating-point precision of 18:
4232 // Log10ofMantissa =
4237 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4239 // error 0.0000037995730, which is better than 18 bits
4240 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4241 getF32Constant(DAG, 0x3c5d51ce));
4242 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4243 getF32Constant(DAG, 0x3e00685a));
4244 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4245 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4246 getF32Constant(DAG, 0x3efb6798));
4247 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4248 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4249 getF32Constant(DAG, 0x3f88d192));
4250 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4251 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4252 getF32Constant(DAG, 0x3fc4316c));
4253 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4254 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4255 getF32Constant(DAG, 0x3f57ce70));
4258 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4261 // No special expansion.
4262 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4265 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4266 /// limited-precision mode.
4267 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4268 const TargetLowering &TLI) {
4269 if (Op.getValueType() == MVT::f32 &&
4270 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4271 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4273 // FractionalPartOfX = x - (float)IntegerPartOfX;
4274 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4275 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4277 // IntegerPartOfX <<= 23;
4278 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4279 DAG.getConstant(23, TLI.getPointerTy()));
4281 SDValue TwoToFractionalPartOfX;
4282 if (LimitFloatPrecision <= 6) {
4283 // For floating-point precision of 6:
4285 // TwoToFractionalPartOfX =
4287 // (0.735607626f + 0.252464424f * x) * x;
4289 // error 0.0144103317, which is 6 bits
4290 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4291 getF32Constant(DAG, 0x3e814304));
4292 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4293 getF32Constant(DAG, 0x3f3c50c8));
4294 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4295 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4296 getF32Constant(DAG, 0x3f7f5e7e));
4297 } else if (LimitFloatPrecision <= 12) {
4298 // For floating-point precision of 12:
4300 // TwoToFractionalPartOfX =
4303 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4305 // error 0.000107046256, which is 13 to 14 bits
4306 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4307 getF32Constant(DAG, 0x3da235e3));
4308 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4309 getF32Constant(DAG, 0x3e65b8f3));
4310 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4311 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4312 getF32Constant(DAG, 0x3f324b07));
4313 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4314 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4315 getF32Constant(DAG, 0x3f7ff8fd));
4316 } else { // LimitFloatPrecision <= 18
4317 // For floating-point precision of 18:
4319 // TwoToFractionalPartOfX =
4323 // (0.554906021e-1f +
4324 // (0.961591928e-2f +
4325 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4326 // error 2.47208000*10^(-7), which is better than 18 bits
4327 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4328 getF32Constant(DAG, 0x3924b03e));
4329 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4330 getF32Constant(DAG, 0x3ab24b87));
4331 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4332 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4333 getF32Constant(DAG, 0x3c1d8c17));
4334 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4335 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4336 getF32Constant(DAG, 0x3d634a1d));
4337 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4338 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4339 getF32Constant(DAG, 0x3e75fe14));
4340 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4341 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4342 getF32Constant(DAG, 0x3f317234));
4343 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4344 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4345 getF32Constant(DAG, 0x3f800000));
4348 // Add the exponent into the result in integer domain.
4349 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4350 TwoToFractionalPartOfX);
4351 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4352 DAG.getNode(ISD::ADD, dl, MVT::i32,
4353 t13, IntegerPartOfX));
4356 // No special expansion.
4357 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4360 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4361 /// limited-precision mode with x == 10.0f.
4362 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4363 SelectionDAG &DAG, const TargetLowering &TLI) {
4364 bool IsExp10 = false;
4365 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4366 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4367 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4369 IsExp10 = LHSC->isExactlyValue(Ten);
4374 // Put the exponent in the right bit position for later addition to the
4377 // #define LOG2OF10 3.3219281f
4378 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4379 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4380 getF32Constant(DAG, 0x40549a78));
4381 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4383 // FractionalPartOfX = x - (float)IntegerPartOfX;
4384 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4385 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4387 // IntegerPartOfX <<= 23;
4388 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4389 DAG.getConstant(23, TLI.getPointerTy()));
4391 SDValue TwoToFractionalPartOfX;
4392 if (LimitFloatPrecision <= 6) {
4393 // For floating-point precision of 6:
4395 // twoToFractionalPartOfX =
4397 // (0.735607626f + 0.252464424f * x) * x;
4399 // error 0.0144103317, which is 6 bits
4400 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4401 getF32Constant(DAG, 0x3e814304));
4402 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4403 getF32Constant(DAG, 0x3f3c50c8));
4404 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4405 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4406 getF32Constant(DAG, 0x3f7f5e7e));
4407 } else if (LimitFloatPrecision <= 12) {
4408 // For floating-point precision of 12:
4410 // TwoToFractionalPartOfX =
4413 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4415 // error 0.000107046256, which is 13 to 14 bits
4416 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4417 getF32Constant(DAG, 0x3da235e3));
4418 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4419 getF32Constant(DAG, 0x3e65b8f3));
4420 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4421 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4422 getF32Constant(DAG, 0x3f324b07));
4423 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4424 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4425 getF32Constant(DAG, 0x3f7ff8fd));
4426 } else { // LimitFloatPrecision <= 18
4427 // For floating-point precision of 18:
4429 // TwoToFractionalPartOfX =
4433 // (0.554906021e-1f +
4434 // (0.961591928e-2f +
4435 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4436 // error 2.47208000*10^(-7), which is better than 18 bits
4437 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4438 getF32Constant(DAG, 0x3924b03e));
4439 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4440 getF32Constant(DAG, 0x3ab24b87));
4441 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4442 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4443 getF32Constant(DAG, 0x3c1d8c17));
4444 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4445 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4446 getF32Constant(DAG, 0x3d634a1d));
4447 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4448 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4449 getF32Constant(DAG, 0x3e75fe14));
4450 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4451 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4452 getF32Constant(DAG, 0x3f317234));
4453 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4454 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4455 getF32Constant(DAG, 0x3f800000));
4458 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4459 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4460 DAG.getNode(ISD::ADD, dl, MVT::i32,
4461 t13, IntegerPartOfX));
4464 // No special expansion.
4465 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4469 /// ExpandPowI - Expand a llvm.powi intrinsic.
4470 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4471 SelectionDAG &DAG) {
4472 // If RHS is a constant, we can expand this out to a multiplication tree,
4473 // otherwise we end up lowering to a call to __powidf2 (for example). When
4474 // optimizing for size, we only want to do this if the expansion would produce
4475 // a small number of multiplies, otherwise we do the full expansion.
4476 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4477 // Get the exponent as a positive value.
4478 unsigned Val = RHSC->getSExtValue();
4479 if ((int)Val < 0) Val = -Val;
4481 // powi(x, 0) -> 1.0
4483 return DAG.getConstantFP(1.0, LHS.getValueType());
4485 const Function *F = DAG.getMachineFunction().getFunction();
4486 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4487 Attribute::OptimizeForSize) ||
4488 // If optimizing for size, don't insert too many multiplies. This
4489 // inserts up to 5 multiplies.
4490 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4491 // We use the simple binary decomposition method to generate the multiply
4492 // sequence. There are more optimal ways to do this (for example,
4493 // powi(x,15) generates one more multiply than it should), but this has
4494 // the benefit of being both really simple and much better than a libcall.
4495 SDValue Res; // Logically starts equal to 1.0
4496 SDValue CurSquare = LHS;
4500 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4502 Res = CurSquare; // 1.0*CurSquare.
4505 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4506 CurSquare, CurSquare);
4510 // If the original was negative, invert the result, producing 1/(x*x*x).
4511 if (RHSC->getSExtValue() < 0)
4512 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4513 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4518 // Otherwise, expand to a libcall.
4519 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4522 // getTruncatedArgReg - Find underlying register used for an truncated
4524 static unsigned getTruncatedArgReg(const SDValue &N) {
4525 if (N.getOpcode() != ISD::TRUNCATE)
4528 const SDValue &Ext = N.getOperand(0);
4529 if (Ext.getOpcode() == ISD::AssertZext ||
4530 Ext.getOpcode() == ISD::AssertSext) {
4531 const SDValue &CFR = Ext.getOperand(0);
4532 if (CFR.getOpcode() == ISD::CopyFromReg)
4533 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4534 if (CFR.getOpcode() == ISD::TRUNCATE)
4535 return getTruncatedArgReg(CFR);
4540 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4541 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4542 /// At the end of instruction selection, they will be inserted to the entry BB.
4544 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4547 const Argument *Arg = dyn_cast<Argument>(V);
4551 MachineFunction &MF = DAG.getMachineFunction();
4552 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4554 // Ignore inlined function arguments here.
4555 DIVariable DV(Variable);
4556 if (DV.isInlinedFnArgument(MF.getFunction()))
4559 Optional<MachineOperand> Op;
4560 // Some arguments' frame index is recorded during argument lowering.
4561 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4562 Op = MachineOperand::CreateFI(FI);
4564 if (!Op && N.getNode()) {
4566 if (N.getOpcode() == ISD::CopyFromReg)
4567 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4569 Reg = getTruncatedArgReg(N);
4570 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4571 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4572 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4577 Op = MachineOperand::CreateReg(Reg, false);
4581 // Check if ValueMap has reg number.
4582 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4583 if (VMI != FuncInfo.ValueMap.end())
4584 Op = MachineOperand::CreateReg(VMI->second, false);
4587 if (!Op && N.getNode())
4588 // Check if frame index is available.
4589 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4590 if (FrameIndexSDNode *FINode =
4591 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4592 Op = MachineOperand::CreateFI(FINode->getIndex());
4597 // FIXME: This does not handle register-indirect values at offset 0.
4598 bool IsIndirect = Offset != 0;
4600 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4601 TII->get(TargetOpcode::DBG_VALUE),
4603 Op->getReg(), Offset, Variable));
4605 FuncInfo.ArgDbgValues.push_back(
4606 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4607 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4612 // VisualStudio defines setjmp as _setjmp
4613 #if defined(_MSC_VER) && defined(setjmp) && \
4614 !defined(setjmp_undefined_for_msvc)
4615 # pragma push_macro("setjmp")
4617 # define setjmp_undefined_for_msvc
4620 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4621 /// we want to emit this as a call to a named external function, return the name
4622 /// otherwise lower it and return null.
4624 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4625 const TargetLowering *TLI = TM.getTargetLowering();
4626 SDLoc sdl = getCurSDLoc();
4627 DebugLoc dl = getCurDebugLoc();
4630 switch (Intrinsic) {
4632 // By default, turn this into a target intrinsic node.
4633 visitTargetIntrinsic(I, Intrinsic);
4635 case Intrinsic::vastart: visitVAStart(I); return 0;
4636 case Intrinsic::vaend: visitVAEnd(I); return 0;
4637 case Intrinsic::vacopy: visitVACopy(I); return 0;
4638 case Intrinsic::returnaddress:
4639 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4640 getValue(I.getArgOperand(0))));
4642 case Intrinsic::frameaddress:
4643 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4644 getValue(I.getArgOperand(0))));
4646 case Intrinsic::setjmp:
4647 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4648 case Intrinsic::longjmp:
4649 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4650 case Intrinsic::memcpy: {
4651 // Assert for address < 256 since we support only user defined address
4653 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4655 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4657 "Unknown address space");
4658 SDValue Op1 = getValue(I.getArgOperand(0));
4659 SDValue Op2 = getValue(I.getArgOperand(1));
4660 SDValue Op3 = getValue(I.getArgOperand(2));
4661 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4663 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4664 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4665 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4666 MachinePointerInfo(I.getArgOperand(0)),
4667 MachinePointerInfo(I.getArgOperand(1))));
4670 case Intrinsic::memset: {
4671 // Assert for address < 256 since we support only user defined address
4673 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4675 "Unknown address space");
4676 SDValue Op1 = getValue(I.getArgOperand(0));
4677 SDValue Op2 = getValue(I.getArgOperand(1));
4678 SDValue Op3 = getValue(I.getArgOperand(2));
4679 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4681 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4682 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4683 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4684 MachinePointerInfo(I.getArgOperand(0))));
4687 case Intrinsic::memmove: {
4688 // Assert for address < 256 since we support only user defined address
4690 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4692 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4694 "Unknown address space");
4695 SDValue Op1 = getValue(I.getArgOperand(0));
4696 SDValue Op2 = getValue(I.getArgOperand(1));
4697 SDValue Op3 = getValue(I.getArgOperand(2));
4698 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4700 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4701 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4702 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4703 MachinePointerInfo(I.getArgOperand(0)),
4704 MachinePointerInfo(I.getArgOperand(1))));
4707 case Intrinsic::dbg_declare: {
4708 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4709 MDNode *Variable = DI.getVariable();
4710 const Value *Address = DI.getAddress();
4711 DIVariable DIVar(Variable);
4712 assert((!DIVar || DIVar.isVariable()) &&
4713 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4714 if (!Address || !DIVar) {
4715 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4719 // Check if address has undef value.
4720 if (isa<UndefValue>(Address) ||
4721 (Address->use_empty() && !isa<Argument>(Address))) {
4722 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4726 SDValue &N = NodeMap[Address];
4727 if (!N.getNode() && isa<Argument>(Address))
4728 // Check unused arguments map.
4729 N = UnusedArgNodeMap[Address];
4732 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4733 Address = BCI->getOperand(0);
4734 // Parameters are handled specially.
4736 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4737 isa<Argument>(Address));
4739 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4741 if (isParameter && !AI) {
4742 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4744 // Byval parameter. We have a frame index at this point.
4745 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4746 0, dl, SDNodeOrder);
4748 // Address is an argument, so try to emit its dbg value using
4749 // virtual register info from the FuncInfo.ValueMap.
4750 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4754 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4755 0, dl, SDNodeOrder);
4757 // Can't do anything with other non-AI cases yet.
4758 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4759 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4760 DEBUG(Address->dump());
4763 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4765 // If Address is an argument then try to emit its dbg value using
4766 // virtual register info from the FuncInfo.ValueMap.
4767 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4768 // If variable is pinned by a alloca in dominating bb then
4769 // use StaticAllocaMap.
4770 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4771 if (AI->getParent() != DI.getParent()) {
4772 DenseMap<const AllocaInst*, int>::iterator SI =
4773 FuncInfo.StaticAllocaMap.find(AI);
4774 if (SI != FuncInfo.StaticAllocaMap.end()) {
4775 SDV = DAG.getDbgValue(Variable, SI->second,
4776 0, dl, SDNodeOrder);
4777 DAG.AddDbgValue(SDV, 0, false);
4782 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4787 case Intrinsic::dbg_value: {
4788 const DbgValueInst &DI = cast<DbgValueInst>(I);
4789 DIVariable DIVar(DI.getVariable());
4790 assert((!DIVar || DIVar.isVariable()) &&
4791 "Variable in DbgValueInst should be either null or a DIVariable.");
4795 MDNode *Variable = DI.getVariable();
4796 uint64_t Offset = DI.getOffset();
4797 const Value *V = DI.getValue();
4802 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4803 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4804 DAG.AddDbgValue(SDV, 0, false);
4806 // Do not use getValue() in here; we don't want to generate code at
4807 // this point if it hasn't been done yet.
4808 SDValue N = NodeMap[V];
4809 if (!N.getNode() && isa<Argument>(V))
4810 // Check unused arguments map.
4811 N = UnusedArgNodeMap[V];
4813 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4814 SDV = DAG.getDbgValue(Variable, N.getNode(),
4815 N.getResNo(), Offset, dl, SDNodeOrder);
4816 DAG.AddDbgValue(SDV, N.getNode(), false);
4818 } else if (!V->use_empty() ) {
4819 // Do not call getValue(V) yet, as we don't want to generate code.
4820 // Remember it for later.
4821 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4822 DanglingDebugInfoMap[V] = DDI;
4824 // We may expand this to cover more cases. One case where we have no
4825 // data available is an unreferenced parameter.
4826 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4830 // Build a debug info table entry.
4831 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4832 V = BCI->getOperand(0);
4833 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4834 // Don't handle byval struct arguments or VLAs, for example.
4836 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4837 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4840 DenseMap<const AllocaInst*, int>::iterator SI =
4841 FuncInfo.StaticAllocaMap.find(AI);
4842 if (SI == FuncInfo.StaticAllocaMap.end())
4844 int FI = SI->second;
4846 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4847 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4848 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4852 case Intrinsic::eh_typeid_for: {
4853 // Find the type id for the given typeinfo.
4854 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4855 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4856 Res = DAG.getConstant(TypeID, MVT::i32);
4861 case Intrinsic::eh_return_i32:
4862 case Intrinsic::eh_return_i64:
4863 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4864 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4867 getValue(I.getArgOperand(0)),
4868 getValue(I.getArgOperand(1))));
4870 case Intrinsic::eh_unwind_init:
4871 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4873 case Intrinsic::eh_dwarf_cfa: {
4874 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4875 TLI->getPointerTy());
4876 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4877 CfaArg.getValueType(),
4878 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4879 CfaArg.getValueType()),
4881 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4882 TLI->getPointerTy(),
4883 DAG.getConstant(0, TLI->getPointerTy()));
4884 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4888 case Intrinsic::eh_sjlj_callsite: {
4889 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4890 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4891 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4892 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4894 MMI.setCurrentCallSite(CI->getZExtValue());
4897 case Intrinsic::eh_sjlj_functioncontext: {
4898 // Get and store the index of the function context.
4899 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4901 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4902 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4903 MFI->setFunctionContextIndex(FI);
4906 case Intrinsic::eh_sjlj_setjmp: {
4909 Ops[1] = getValue(I.getArgOperand(0));
4910 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4911 DAG.getVTList(MVT::i32, MVT::Other),
4913 setValue(&I, Op.getValue(0));
4914 DAG.setRoot(Op.getValue(1));
4917 case Intrinsic::eh_sjlj_longjmp: {
4918 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4919 getRoot(), getValue(I.getArgOperand(0))));
4923 case Intrinsic::x86_mmx_pslli_w:
4924 case Intrinsic::x86_mmx_pslli_d:
4925 case Intrinsic::x86_mmx_pslli_q:
4926 case Intrinsic::x86_mmx_psrli_w:
4927 case Intrinsic::x86_mmx_psrli_d:
4928 case Intrinsic::x86_mmx_psrli_q:
4929 case Intrinsic::x86_mmx_psrai_w:
4930 case Intrinsic::x86_mmx_psrai_d: {
4931 SDValue ShAmt = getValue(I.getArgOperand(1));
4932 if (isa<ConstantSDNode>(ShAmt)) {
4933 visitTargetIntrinsic(I, Intrinsic);
4936 unsigned NewIntrinsic = 0;
4937 EVT ShAmtVT = MVT::v2i32;
4938 switch (Intrinsic) {
4939 case Intrinsic::x86_mmx_pslli_w:
4940 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4942 case Intrinsic::x86_mmx_pslli_d:
4943 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4945 case Intrinsic::x86_mmx_pslli_q:
4946 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4948 case Intrinsic::x86_mmx_psrli_w:
4949 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4951 case Intrinsic::x86_mmx_psrli_d:
4952 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4954 case Intrinsic::x86_mmx_psrli_q:
4955 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4957 case Intrinsic::x86_mmx_psrai_w:
4958 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4960 case Intrinsic::x86_mmx_psrai_d:
4961 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4963 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4966 // The vector shift intrinsics with scalars uses 32b shift amounts but
4967 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4969 // We must do this early because v2i32 is not a legal type.
4972 ShOps[1] = DAG.getConstant(0, MVT::i32);
4973 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4974 EVT DestVT = TLI->getValueType(I.getType());
4975 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4976 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4977 DAG.getConstant(NewIntrinsic, MVT::i32),
4978 getValue(I.getArgOperand(0)), ShAmt);
4982 case Intrinsic::x86_avx_vinsertf128_pd_256:
4983 case Intrinsic::x86_avx_vinsertf128_ps_256:
4984 case Intrinsic::x86_avx_vinsertf128_si_256:
4985 case Intrinsic::x86_avx2_vinserti128: {
4986 EVT DestVT = TLI->getValueType(I.getType());
4987 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4988 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4989 ElVT.getVectorNumElements();
4990 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4991 getValue(I.getArgOperand(0)),
4992 getValue(I.getArgOperand(1)),
4993 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4997 case Intrinsic::x86_avx_vextractf128_pd_256:
4998 case Intrinsic::x86_avx_vextractf128_ps_256:
4999 case Intrinsic::x86_avx_vextractf128_si_256:
5000 case Intrinsic::x86_avx2_vextracti128: {
5001 EVT DestVT = TLI->getValueType(I.getType());
5002 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5003 DestVT.getVectorNumElements();
5004 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5005 getValue(I.getArgOperand(0)),
5006 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5010 case Intrinsic::convertff:
5011 case Intrinsic::convertfsi:
5012 case Intrinsic::convertfui:
5013 case Intrinsic::convertsif:
5014 case Intrinsic::convertuif:
5015 case Intrinsic::convertss:
5016 case Intrinsic::convertsu:
5017 case Intrinsic::convertus:
5018 case Intrinsic::convertuu: {
5019 ISD::CvtCode Code = ISD::CVT_INVALID;
5020 switch (Intrinsic) {
5021 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5022 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5023 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5024 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5025 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5026 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5027 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5028 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5029 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5030 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5032 EVT DestVT = TLI->getValueType(I.getType());
5033 const Value *Op1 = I.getArgOperand(0);
5034 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5035 DAG.getValueType(DestVT),
5036 DAG.getValueType(getValue(Op1).getValueType()),
5037 getValue(I.getArgOperand(1)),
5038 getValue(I.getArgOperand(2)),
5043 case Intrinsic::powi:
5044 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5045 getValue(I.getArgOperand(1)), DAG));
5047 case Intrinsic::log:
5048 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5050 case Intrinsic::log2:
5051 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5053 case Intrinsic::log10:
5054 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5056 case Intrinsic::exp:
5057 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5059 case Intrinsic::exp2:
5060 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5062 case Intrinsic::pow:
5063 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5064 getValue(I.getArgOperand(1)), DAG, *TLI));
5066 case Intrinsic::sqrt:
5067 case Intrinsic::fabs:
5068 case Intrinsic::sin:
5069 case Intrinsic::cos:
5070 case Intrinsic::floor:
5071 case Intrinsic::ceil:
5072 case Intrinsic::trunc:
5073 case Intrinsic::rint:
5074 case Intrinsic::nearbyint:
5075 case Intrinsic::round: {
5077 switch (Intrinsic) {
5078 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5079 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5080 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5081 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5082 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5083 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5084 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5085 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5086 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5087 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5088 case Intrinsic::round: Opcode = ISD::FROUND; break;
5091 setValue(&I, DAG.getNode(Opcode, sdl,
5092 getValue(I.getArgOperand(0)).getValueType(),
5093 getValue(I.getArgOperand(0))));
5096 case Intrinsic::copysign:
5097 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5098 getValue(I.getArgOperand(0)).getValueType(),
5099 getValue(I.getArgOperand(0)),
5100 getValue(I.getArgOperand(1))));
5102 case Intrinsic::fma:
5103 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5104 getValue(I.getArgOperand(0)).getValueType(),
5105 getValue(I.getArgOperand(0)),
5106 getValue(I.getArgOperand(1)),
5107 getValue(I.getArgOperand(2))));
5109 case Intrinsic::fmuladd: {
5110 EVT VT = TLI->getValueType(I.getType());
5111 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5112 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5113 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5114 getValue(I.getArgOperand(0)).getValueType(),
5115 getValue(I.getArgOperand(0)),
5116 getValue(I.getArgOperand(1)),
5117 getValue(I.getArgOperand(2))));
5119 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5120 getValue(I.getArgOperand(0)).getValueType(),
5121 getValue(I.getArgOperand(0)),
5122 getValue(I.getArgOperand(1)));
5123 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5124 getValue(I.getArgOperand(0)).getValueType(),
5126 getValue(I.getArgOperand(2)));
5131 case Intrinsic::convert_to_fp16:
5132 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
5133 MVT::i16, getValue(I.getArgOperand(0))));
5135 case Intrinsic::convert_from_fp16:
5136 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
5137 MVT::f32, getValue(I.getArgOperand(0))));
5139 case Intrinsic::pcmarker: {
5140 SDValue Tmp = getValue(I.getArgOperand(0));
5141 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5144 case Intrinsic::readcyclecounter: {
5145 SDValue Op = getRoot();
5146 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5147 DAG.getVTList(MVT::i64, MVT::Other),
5150 DAG.setRoot(Res.getValue(1));
5153 case Intrinsic::bswap:
5154 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5155 getValue(I.getArgOperand(0)).getValueType(),
5156 getValue(I.getArgOperand(0))));
5158 case Intrinsic::cttz: {
5159 SDValue Arg = getValue(I.getArgOperand(0));
5160 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5161 EVT Ty = Arg.getValueType();
5162 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5166 case Intrinsic::ctlz: {
5167 SDValue Arg = getValue(I.getArgOperand(0));
5168 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5169 EVT Ty = Arg.getValueType();
5170 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5174 case Intrinsic::ctpop: {
5175 SDValue Arg = getValue(I.getArgOperand(0));
5176 EVT Ty = Arg.getValueType();
5177 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5180 case Intrinsic::stacksave: {
5181 SDValue Op = getRoot();
5182 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5183 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5185 DAG.setRoot(Res.getValue(1));
5188 case Intrinsic::stackrestore: {
5189 Res = getValue(I.getArgOperand(0));
5190 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5193 case Intrinsic::stackprotector: {
5194 // Emit code into the DAG to store the stack guard onto the stack.
5195 MachineFunction &MF = DAG.getMachineFunction();
5196 MachineFrameInfo *MFI = MF.getFrameInfo();
5197 EVT PtrTy = TLI->getPointerTy();
5199 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5200 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5202 int FI = FuncInfo.StaticAllocaMap[Slot];
5203 MFI->setStackProtectorIndex(FI);
5205 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5207 // Store the stack protector onto the stack.
5208 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5209 MachinePointerInfo::getFixedStack(FI),
5215 case Intrinsic::objectsize: {
5216 // If we don't know by now, we're never going to know.
5217 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5219 assert(CI && "Non-constant type in __builtin_object_size?");
5221 SDValue Arg = getValue(I.getCalledValue());
5222 EVT Ty = Arg.getValueType();
5225 Res = DAG.getConstant(-1ULL, Ty);
5227 Res = DAG.getConstant(0, Ty);
5232 case Intrinsic::annotation:
5233 case Intrinsic::ptr_annotation:
5234 // Drop the intrinsic, but forward the value
5235 setValue(&I, getValue(I.getOperand(0)));
5237 case Intrinsic::var_annotation:
5238 // Discard annotate attributes
5241 case Intrinsic::init_trampoline: {
5242 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5246 Ops[1] = getValue(I.getArgOperand(0));
5247 Ops[2] = getValue(I.getArgOperand(1));
5248 Ops[3] = getValue(I.getArgOperand(2));
5249 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5250 Ops[5] = DAG.getSrcValue(F);
5252 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5257 case Intrinsic::adjust_trampoline: {
5258 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5259 TLI->getPointerTy(),
5260 getValue(I.getArgOperand(0))));
5263 case Intrinsic::gcroot:
5265 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5266 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5268 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5269 GFI->addStackRoot(FI->getIndex(), TypeMap);
5272 case Intrinsic::gcread:
5273 case Intrinsic::gcwrite:
5274 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5275 case Intrinsic::flt_rounds:
5276 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5279 case Intrinsic::expect: {
5280 // Just replace __builtin_expect(exp, c) with EXP.
5281 setValue(&I, getValue(I.getArgOperand(0)));
5285 case Intrinsic::debugtrap:
5286 case Intrinsic::trap: {
5287 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5288 if (TrapFuncName.empty()) {
5289 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5290 ISD::TRAP : ISD::DEBUGTRAP;
5291 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5294 TargetLowering::ArgListTy Args;
5296 CallLoweringInfo CLI(getRoot(), I.getType(),
5297 false, false, false, false, 0, CallingConv::C,
5298 /*isTailCall=*/false,
5299 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5300 DAG.getExternalSymbol(TrapFuncName.data(),
5301 TLI->getPointerTy()),
5303 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5304 DAG.setRoot(Result.second);
5308 case Intrinsic::uadd_with_overflow:
5309 case Intrinsic::sadd_with_overflow:
5310 case Intrinsic::usub_with_overflow:
5311 case Intrinsic::ssub_with_overflow:
5312 case Intrinsic::umul_with_overflow:
5313 case Intrinsic::smul_with_overflow: {
5315 switch (Intrinsic) {
5316 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5317 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5318 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5319 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5320 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5321 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5322 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5324 SDValue Op1 = getValue(I.getArgOperand(0));
5325 SDValue Op2 = getValue(I.getArgOperand(1));
5327 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5328 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5331 case Intrinsic::prefetch: {
5333 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5335 Ops[1] = getValue(I.getArgOperand(0));
5336 Ops[2] = getValue(I.getArgOperand(1));
5337 Ops[3] = getValue(I.getArgOperand(2));
5338 Ops[4] = getValue(I.getArgOperand(3));
5339 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5340 DAG.getVTList(MVT::Other),
5342 EVT::getIntegerVT(*Context, 8),
5343 MachinePointerInfo(I.getArgOperand(0)),
5345 false, /* volatile */
5347 rw==1)); /* write */
5350 case Intrinsic::lifetime_start:
5351 case Intrinsic::lifetime_end: {
5352 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5353 // Stack coloring is not enabled in O0, discard region information.
5354 if (TM.getOptLevel() == CodeGenOpt::None)
5357 SmallVector<Value *, 4> Allocas;
5358 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD);
5360 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5361 E = Allocas.end(); Object != E; ++Object) {
5362 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5364 // Could not find an Alloca.
5365 if (!LifetimeObject)
5368 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5372 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5373 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5375 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5380 case Intrinsic::invariant_start:
5381 // Discard region information.
5382 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5384 case Intrinsic::invariant_end:
5385 // Discard region information.
5387 case Intrinsic::stackprotectorcheck: {
5388 // Do not actually emit anything for this basic block. Instead we initialize
5389 // the stack protector descriptor and export the guard variable so we can
5390 // access it in FinishBasicBlock.
5391 const BasicBlock *BB = I.getParent();
5392 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5393 ExportFromCurrentBlock(SPDescriptor.getGuard());
5395 // Flush our exports since we are going to process a terminator.
5396 (void)getControlRoot();
5399 case Intrinsic::donothing:
5402 case Intrinsic::experimental_stackmap: {
5406 case Intrinsic::experimental_patchpoint_void:
5407 case Intrinsic::experimental_patchpoint_i64: {
5414 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5416 MachineBasicBlock *LandingPad) {
5417 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5418 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5419 Type *RetTy = FTy->getReturnType();
5420 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5421 MCSymbol *BeginLabel = 0;
5423 TargetLowering::ArgListTy Args;
5424 TargetLowering::ArgListEntry Entry;
5425 Args.reserve(CS.arg_size());
5427 // Check whether the function can return without sret-demotion.
5428 SmallVector<ISD::OutputArg, 4> Outs;
5429 const TargetLowering *TLI = TM.getTargetLowering();
5430 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5432 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5433 DAG.getMachineFunction(),
5434 FTy->isVarArg(), Outs,
5437 SDValue DemoteStackSlot;
5438 int DemoteStackIdx = -100;
5440 if (!CanLowerReturn) {
5441 assert(!CS.hasInAllocaArgument() &&
5442 "sret demotion is incompatible with inalloca");
5443 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5444 FTy->getReturnType());
5445 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5446 FTy->getReturnType());
5447 MachineFunction &MF = DAG.getMachineFunction();
5448 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5449 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5451 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5452 Entry.Node = DemoteStackSlot;
5453 Entry.Ty = StackSlotPtrType;
5454 Entry.isSExt = false;
5455 Entry.isZExt = false;
5456 Entry.isInReg = false;
5457 Entry.isSRet = true;
5458 Entry.isNest = false;
5459 Entry.isByVal = false;
5460 Entry.isReturned = false;
5461 Entry.Alignment = Align;
5462 Args.push_back(Entry);
5463 RetTy = Type::getVoidTy(FTy->getContext());
5466 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5468 const Value *V = *i;
5471 if (V->getType()->isEmptyTy())
5474 SDValue ArgNode = getValue(V);
5475 Entry.Node = ArgNode; Entry.Ty = V->getType();
5477 // Skip the first return-type Attribute to get to params.
5478 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5479 Args.push_back(Entry);
5483 // Insert a label before the invoke call to mark the try range. This can be
5484 // used to detect deletion of the invoke via the MachineModuleInfo.
5485 BeginLabel = MMI.getContext().CreateTempSymbol();
5487 // For SjLj, keep track of which landing pads go with which invokes
5488 // so as to maintain the ordering of pads in the LSDA.
5489 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5490 if (CallSiteIndex) {
5491 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5492 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5494 // Now that the call site is handled, stop tracking it.
5495 MMI.setCurrentCallSite(0);
5498 // Both PendingLoads and PendingExports must be flushed here;
5499 // this call might not return.
5501 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5504 // Check if target-independent constraints permit a tail call here.
5505 // Target-dependent constraints are checked within TLI->LowerCallTo.
5506 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5510 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5512 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5513 assert((isTailCall || Result.second.getNode()) &&
5514 "Non-null chain expected with non-tail call!");
5515 assert((Result.second.getNode() || !Result.first.getNode()) &&
5516 "Null value expected with tail call!");
5517 if (Result.first.getNode()) {
5518 setValue(CS.getInstruction(), Result.first);
5519 } else if (!CanLowerReturn && Result.second.getNode()) {
5520 // The instruction result is the result of loading from the
5521 // hidden sret parameter.
5522 SmallVector<EVT, 1> PVTs;
5523 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5525 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5526 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5527 EVT PtrVT = PVTs[0];
5529 SmallVector<EVT, 4> RetTys;
5530 SmallVector<uint64_t, 4> Offsets;
5531 RetTy = FTy->getReturnType();
5532 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5534 unsigned NumValues = RetTys.size();
5535 SmallVector<SDValue, 4> Values(NumValues);
5536 SmallVector<SDValue, 4> Chains(NumValues);
5538 for (unsigned i = 0; i < NumValues; ++i) {
5539 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5541 DAG.getConstant(Offsets[i], PtrVT));
5542 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5543 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5544 false, false, false, 1);
5546 Chains[i] = L.getValue(1);
5549 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5550 MVT::Other, &Chains[0], NumValues);
5551 PendingLoads.push_back(Chain);
5553 setValue(CS.getInstruction(),
5554 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5555 DAG.getVTList(&RetTys[0], RetTys.size()),
5556 &Values[0], Values.size()));
5559 if (!Result.second.getNode()) {
5560 // As a special case, a null chain means that a tail call has been emitted
5561 // and the DAG root is already updated.
5564 // Since there's no actual continuation from this block, nothing can be
5565 // relying on us setting vregs for them.
5566 PendingExports.clear();
5568 DAG.setRoot(Result.second);
5572 // Insert a label at the end of the invoke call to mark the try range. This
5573 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5574 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5575 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5577 // Inform MachineModuleInfo of range.
5578 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5582 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5583 /// value is equal or not-equal to zero.
5584 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5585 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5587 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5588 if (IC->isEquality())
5589 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5590 if (C->isNullValue())
5592 // Unknown instruction.
5598 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5600 SelectionDAGBuilder &Builder) {
5602 // Check to see if this load can be trivially constant folded, e.g. if the
5603 // input is from a string literal.
5604 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5605 // Cast pointer to the type we really want to load.
5606 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5607 PointerType::getUnqual(LoadTy));
5609 if (const Constant *LoadCst =
5610 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5612 return Builder.getValue(LoadCst);
5615 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5616 // still constant memory, the input chain can be the entry node.
5618 bool ConstantMemory = false;
5620 // Do not serialize (non-volatile) loads of constant memory with anything.
5621 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5622 Root = Builder.DAG.getEntryNode();
5623 ConstantMemory = true;
5625 // Do not serialize non-volatile loads against each other.
5626 Root = Builder.DAG.getRoot();
5629 SDValue Ptr = Builder.getValue(PtrVal);
5630 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5631 Ptr, MachinePointerInfo(PtrVal),
5633 false /*nontemporal*/,
5634 false /*isinvariant*/, 1 /* align=1 */);
5636 if (!ConstantMemory)
5637 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5641 /// processIntegerCallValue - Record the value for an instruction that
5642 /// produces an integer result, converting the type where necessary.
5643 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5646 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true);
5648 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5650 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5651 setValue(&I, Value);
5654 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5655 /// If so, return true and lower it, otherwise return false and it will be
5656 /// lowered like a normal call.
5657 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5658 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5659 if (I.getNumArgOperands() != 3)
5662 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5663 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5664 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5665 !I.getType()->isIntegerTy())
5668 const Value *Size = I.getArgOperand(2);
5669 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5670 if (CSize && CSize->getZExtValue() == 0) {
5671 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true);
5672 setValue(&I, DAG.getConstant(0, CallVT));
5676 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5677 std::pair<SDValue, SDValue> Res =
5678 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5679 getValue(LHS), getValue(RHS), getValue(Size),
5680 MachinePointerInfo(LHS),
5681 MachinePointerInfo(RHS));
5682 if (Res.first.getNode()) {
5683 processIntegerCallValue(I, Res.first, true);
5684 PendingLoads.push_back(Res.second);
5688 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5689 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5690 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5691 bool ActuallyDoIt = true;
5694 switch (CSize->getZExtValue()) {
5696 LoadVT = MVT::Other;
5698 ActuallyDoIt = false;
5702 LoadTy = Type::getInt16Ty(CSize->getContext());
5706 LoadTy = Type::getInt32Ty(CSize->getContext());
5710 LoadTy = Type::getInt64Ty(CSize->getContext());
5714 LoadVT = MVT::v4i32;
5715 LoadTy = Type::getInt32Ty(CSize->getContext());
5716 LoadTy = VectorType::get(LoadTy, 4);
5721 // This turns into unaligned loads. We only do this if the target natively
5722 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5723 // we'll only produce a small number of byte loads.
5725 // Require that we can find a legal MVT, and only do this if the target
5726 // supports unaligned loads of that type. Expanding into byte loads would
5728 const TargetLowering *TLI = TM.getTargetLowering();
5729 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5730 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5731 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5732 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5733 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5734 if (!TLI->isTypeLegal(LoadVT) ||
5735 !TLI->allowsUnalignedMemoryAccesses(LoadVT, SrcAS) ||
5736 !TLI->allowsUnalignedMemoryAccesses(LoadVT, DstAS))
5737 ActuallyDoIt = false;
5741 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5742 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5744 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5746 processIntegerCallValue(I, Res, false);
5755 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5756 /// form. If so, return true and lower it, otherwise return false and it
5757 /// will be lowered like a normal call.
5758 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5759 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5760 if (I.getNumArgOperands() != 3)
5763 const Value *Src = I.getArgOperand(0);
5764 const Value *Char = I.getArgOperand(1);
5765 const Value *Length = I.getArgOperand(2);
5766 if (!Src->getType()->isPointerTy() ||
5767 !Char->getType()->isIntegerTy() ||
5768 !Length->getType()->isIntegerTy() ||
5769 !I.getType()->isPointerTy())
5772 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5773 std::pair<SDValue, SDValue> Res =
5774 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5775 getValue(Src), getValue(Char), getValue(Length),
5776 MachinePointerInfo(Src));
5777 if (Res.first.getNode()) {
5778 setValue(&I, Res.first);
5779 PendingLoads.push_back(Res.second);
5786 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5787 /// optimized form. If so, return true and lower it, otherwise return false
5788 /// and it will be lowered like a normal call.
5789 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5790 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5791 if (I.getNumArgOperands() != 2)
5794 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5795 if (!Arg0->getType()->isPointerTy() ||
5796 !Arg1->getType()->isPointerTy() ||
5797 !I.getType()->isPointerTy())
5800 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5801 std::pair<SDValue, SDValue> Res =
5802 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5803 getValue(Arg0), getValue(Arg1),
5804 MachinePointerInfo(Arg0),
5805 MachinePointerInfo(Arg1), isStpcpy);
5806 if (Res.first.getNode()) {
5807 setValue(&I, Res.first);
5808 DAG.setRoot(Res.second);
5815 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5816 /// If so, return true and lower it, otherwise return false and it will be
5817 /// lowered like a normal call.
5818 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5819 // Verify that the prototype makes sense. int strcmp(void*,void*)
5820 if (I.getNumArgOperands() != 2)
5823 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5824 if (!Arg0->getType()->isPointerTy() ||
5825 !Arg1->getType()->isPointerTy() ||
5826 !I.getType()->isIntegerTy())
5829 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5830 std::pair<SDValue, SDValue> Res =
5831 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5832 getValue(Arg0), getValue(Arg1),
5833 MachinePointerInfo(Arg0),
5834 MachinePointerInfo(Arg1));
5835 if (Res.first.getNode()) {
5836 processIntegerCallValue(I, Res.first, true);
5837 PendingLoads.push_back(Res.second);
5844 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5845 /// form. If so, return true and lower it, otherwise return false and it
5846 /// will be lowered like a normal call.
5847 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5848 // Verify that the prototype makes sense. size_t strlen(char *)
5849 if (I.getNumArgOperands() != 1)
5852 const Value *Arg0 = I.getArgOperand(0);
5853 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5856 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5857 std::pair<SDValue, SDValue> Res =
5858 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5859 getValue(Arg0), MachinePointerInfo(Arg0));
5860 if (Res.first.getNode()) {
5861 processIntegerCallValue(I, Res.first, false);
5862 PendingLoads.push_back(Res.second);
5869 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5870 /// form. If so, return true and lower it, otherwise return false and it
5871 /// will be lowered like a normal call.
5872 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5873 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5874 if (I.getNumArgOperands() != 2)
5877 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5878 if (!Arg0->getType()->isPointerTy() ||
5879 !Arg1->getType()->isIntegerTy() ||
5880 !I.getType()->isIntegerTy())
5883 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5884 std::pair<SDValue, SDValue> Res =
5885 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5886 getValue(Arg0), getValue(Arg1),
5887 MachinePointerInfo(Arg0));
5888 if (Res.first.getNode()) {
5889 processIntegerCallValue(I, Res.first, false);
5890 PendingLoads.push_back(Res.second);
5897 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5898 /// operation (as expected), translate it to an SDNode with the specified opcode
5899 /// and return true.
5900 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5902 // Sanity check that it really is a unary floating-point call.
5903 if (I.getNumArgOperands() != 1 ||
5904 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5905 I.getType() != I.getArgOperand(0)->getType() ||
5906 !I.onlyReadsMemory())
5909 SDValue Tmp = getValue(I.getArgOperand(0));
5910 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5914 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5915 // Handle inline assembly differently.
5916 if (isa<InlineAsm>(I.getCalledValue())) {
5921 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5922 ComputeUsesVAFloatArgument(I, &MMI);
5924 const char *RenameFn = 0;
5925 if (Function *F = I.getCalledFunction()) {
5926 if (F->isDeclaration()) {
5927 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5928 if (unsigned IID = II->getIntrinsicID(F)) {
5929 RenameFn = visitIntrinsicCall(I, IID);
5934 if (unsigned IID = F->getIntrinsicID()) {
5935 RenameFn = visitIntrinsicCall(I, IID);
5941 // Check for well-known libc/libm calls. If the function is internal, it
5942 // can't be a library call.
5944 if (!F->hasLocalLinkage() && F->hasName() &&
5945 LibInfo->getLibFunc(F->getName(), Func) &&
5946 LibInfo->hasOptimizedCodeGen(Func)) {
5949 case LibFunc::copysign:
5950 case LibFunc::copysignf:
5951 case LibFunc::copysignl:
5952 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5953 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5954 I.getType() == I.getArgOperand(0)->getType() &&
5955 I.getType() == I.getArgOperand(1)->getType() &&
5956 I.onlyReadsMemory()) {
5957 SDValue LHS = getValue(I.getArgOperand(0));
5958 SDValue RHS = getValue(I.getArgOperand(1));
5959 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5960 LHS.getValueType(), LHS, RHS));
5965 case LibFunc::fabsf:
5966 case LibFunc::fabsl:
5967 if (visitUnaryFloatCall(I, ISD::FABS))
5973 if (visitUnaryFloatCall(I, ISD::FSIN))
5979 if (visitUnaryFloatCall(I, ISD::FCOS))
5983 case LibFunc::sqrtf:
5984 case LibFunc::sqrtl:
5985 case LibFunc::sqrt_finite:
5986 case LibFunc::sqrtf_finite:
5987 case LibFunc::sqrtl_finite:
5988 if (visitUnaryFloatCall(I, ISD::FSQRT))
5991 case LibFunc::floor:
5992 case LibFunc::floorf:
5993 case LibFunc::floorl:
5994 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5997 case LibFunc::nearbyint:
5998 case LibFunc::nearbyintf:
5999 case LibFunc::nearbyintl:
6000 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6004 case LibFunc::ceilf:
6005 case LibFunc::ceill:
6006 if (visitUnaryFloatCall(I, ISD::FCEIL))
6010 case LibFunc::rintf:
6011 case LibFunc::rintl:
6012 if (visitUnaryFloatCall(I, ISD::FRINT))
6015 case LibFunc::round:
6016 case LibFunc::roundf:
6017 case LibFunc::roundl:
6018 if (visitUnaryFloatCall(I, ISD::FROUND))
6021 case LibFunc::trunc:
6022 case LibFunc::truncf:
6023 case LibFunc::truncl:
6024 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6028 case LibFunc::log2f:
6029 case LibFunc::log2l:
6030 if (visitUnaryFloatCall(I, ISD::FLOG2))
6034 case LibFunc::exp2f:
6035 case LibFunc::exp2l:
6036 if (visitUnaryFloatCall(I, ISD::FEXP2))
6039 case LibFunc::memcmp:
6040 if (visitMemCmpCall(I))
6043 case LibFunc::memchr:
6044 if (visitMemChrCall(I))
6047 case LibFunc::strcpy:
6048 if (visitStrCpyCall(I, false))
6051 case LibFunc::stpcpy:
6052 if (visitStrCpyCall(I, true))
6055 case LibFunc::strcmp:
6056 if (visitStrCmpCall(I))
6059 case LibFunc::strlen:
6060 if (visitStrLenCall(I))
6063 case LibFunc::strnlen:
6064 if (visitStrNLenCall(I))
6073 Callee = getValue(I.getCalledValue());
6075 Callee = DAG.getExternalSymbol(RenameFn,
6076 TM.getTargetLowering()->getPointerTy());
6078 // Check if we can potentially perform a tail call. More detailed checking is
6079 // be done within LowerCallTo, after more information about the call is known.
6080 LowerCallTo(&I, Callee, I.isTailCall());
6085 /// AsmOperandInfo - This contains information for each constraint that we are
6087 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6089 /// CallOperand - If this is the result output operand or a clobber
6090 /// this is null, otherwise it is the incoming operand to the CallInst.
6091 /// This gets modified as the asm is processed.
6092 SDValue CallOperand;
6094 /// AssignedRegs - If this is a register or register class operand, this
6095 /// contains the set of register corresponding to the operand.
6096 RegsForValue AssignedRegs;
6098 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6099 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
6102 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6103 /// corresponds to. If there is no Value* for this operand, it returns
6105 EVT getCallOperandValEVT(LLVMContext &Context,
6106 const TargetLowering &TLI,
6107 const DataLayout *TD) const {
6108 if (CallOperandVal == 0) return MVT::Other;
6110 if (isa<BasicBlock>(CallOperandVal))
6111 return TLI.getPointerTy();
6113 llvm::Type *OpTy = CallOperandVal->getType();
6115 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6116 // If this is an indirect operand, the operand is a pointer to the
6119 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6121 report_fatal_error("Indirect operand for inline asm not a pointer!");
6122 OpTy = PtrTy->getElementType();
6125 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6126 if (StructType *STy = dyn_cast<StructType>(OpTy))
6127 if (STy->getNumElements() == 1)
6128 OpTy = STy->getElementType(0);
6130 // If OpTy is not a single value, it may be a struct/union that we
6131 // can tile with integers.
6132 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6133 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
6142 OpTy = IntegerType::get(Context, BitSize);
6147 return TLI.getValueType(OpTy, true);
6151 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6153 } // end anonymous namespace
6155 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6156 /// specified operand. We prefer to assign virtual registers, to allow the
6157 /// register allocator to handle the assignment process. However, if the asm
6158 /// uses features that we can't model on machineinstrs, we have SDISel do the
6159 /// allocation. This produces generally horrible, but correct, code.
6161 /// OpInfo describes the operand.
6163 static void GetRegistersForValue(SelectionDAG &DAG,
6164 const TargetLowering &TLI,
6166 SDISelAsmOperandInfo &OpInfo) {
6167 LLVMContext &Context = *DAG.getContext();
6169 MachineFunction &MF = DAG.getMachineFunction();
6170 SmallVector<unsigned, 4> Regs;
6172 // If this is a constraint for a single physreg, or a constraint for a
6173 // register class, find it.
6174 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6175 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6176 OpInfo.ConstraintVT);
6178 unsigned NumRegs = 1;
6179 if (OpInfo.ConstraintVT != MVT::Other) {
6180 // If this is a FP input in an integer register (or visa versa) insert a bit
6181 // cast of the input value. More generally, handle any case where the input
6182 // value disagrees with the register class we plan to stick this in.
6183 if (OpInfo.Type == InlineAsm::isInput &&
6184 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6185 // Try to convert to the first EVT that the reg class contains. If the
6186 // types are identical size, use a bitcast to convert (e.g. two differing
6188 MVT RegVT = *PhysReg.second->vt_begin();
6189 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
6190 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6191 RegVT, OpInfo.CallOperand);
6192 OpInfo.ConstraintVT = RegVT;
6193 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6194 // If the input is a FP value and we want it in FP registers, do a
6195 // bitcast to the corresponding integer type. This turns an f64 value
6196 // into i64, which can be passed with two i32 values on a 32-bit
6198 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6199 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6200 RegVT, OpInfo.CallOperand);
6201 OpInfo.ConstraintVT = RegVT;
6205 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6209 EVT ValueVT = OpInfo.ConstraintVT;
6211 // If this is a constraint for a specific physical register, like {r17},
6213 if (unsigned AssignedReg = PhysReg.first) {
6214 const TargetRegisterClass *RC = PhysReg.second;
6215 if (OpInfo.ConstraintVT == MVT::Other)
6216 ValueVT = *RC->vt_begin();
6218 // Get the actual register value type. This is important, because the user
6219 // may have asked for (e.g.) the AX register in i32 type. We need to
6220 // remember that AX is actually i16 to get the right extension.
6221 RegVT = *RC->vt_begin();
6223 // This is a explicit reference to a physical register.
6224 Regs.push_back(AssignedReg);
6226 // If this is an expanded reference, add the rest of the regs to Regs.
6228 TargetRegisterClass::iterator I = RC->begin();
6229 for (; *I != AssignedReg; ++I)
6230 assert(I != RC->end() && "Didn't find reg!");
6232 // Already added the first reg.
6234 for (; NumRegs; --NumRegs, ++I) {
6235 assert(I != RC->end() && "Ran out of registers to allocate!");
6240 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6244 // Otherwise, if this was a reference to an LLVM register class, create vregs
6245 // for this reference.
6246 if (const TargetRegisterClass *RC = PhysReg.second) {
6247 RegVT = *RC->vt_begin();
6248 if (OpInfo.ConstraintVT == MVT::Other)
6251 // Create the appropriate number of virtual registers.
6252 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6253 for (; NumRegs; --NumRegs)
6254 Regs.push_back(RegInfo.createVirtualRegister(RC));
6256 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6260 // Otherwise, we couldn't allocate enough registers for this.
6263 /// visitInlineAsm - Handle a call to an InlineAsm object.
6265 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6266 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6268 /// ConstraintOperands - Information about all of the constraints.
6269 SDISelAsmOperandInfoVector ConstraintOperands;
6271 const TargetLowering *TLI = TM.getTargetLowering();
6272 TargetLowering::AsmOperandInfoVector
6273 TargetConstraints = TLI->ParseConstraints(CS);
6275 bool hasMemory = false;
6277 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6278 unsigned ResNo = 0; // ResNo - The result number of the next output.
6279 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6280 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6281 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6283 MVT OpVT = MVT::Other;
6285 // Compute the value type for each operand.
6286 switch (OpInfo.Type) {
6287 case InlineAsm::isOutput:
6288 // Indirect outputs just consume an argument.
6289 if (OpInfo.isIndirect) {
6290 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6294 // The return value of the call is this value. As such, there is no
6295 // corresponding argument.
6296 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6297 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6298 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6300 assert(ResNo == 0 && "Asm only has one result!");
6301 OpVT = TLI->getSimpleValueType(CS.getType());
6305 case InlineAsm::isInput:
6306 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6308 case InlineAsm::isClobber:
6313 // If this is an input or an indirect output, process the call argument.
6314 // BasicBlocks are labels, currently appearing only in asm's.
6315 if (OpInfo.CallOperandVal) {
6316 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6317 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6319 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6322 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD).
6326 OpInfo.ConstraintVT = OpVT;
6328 // Indirect operand accesses access memory.
6329 if (OpInfo.isIndirect)
6332 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6333 TargetLowering::ConstraintType
6334 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6335 if (CType == TargetLowering::C_Memory) {
6343 SDValue Chain, Flag;
6345 // We won't need to flush pending loads if this asm doesn't touch
6346 // memory and is nonvolatile.
6347 if (hasMemory || IA->hasSideEffects())
6350 Chain = DAG.getRoot();
6352 // Second pass over the constraints: compute which constraint option to use
6353 // and assign registers to constraints that want a specific physreg.
6354 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6355 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6357 // If this is an output operand with a matching input operand, look up the
6358 // matching input. If their types mismatch, e.g. one is an integer, the
6359 // other is floating point, or their sizes are different, flag it as an
6361 if (OpInfo.hasMatchingInput()) {
6362 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6364 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6365 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6366 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6367 OpInfo.ConstraintVT);
6368 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6369 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6370 Input.ConstraintVT);
6371 if ((OpInfo.ConstraintVT.isInteger() !=
6372 Input.ConstraintVT.isInteger()) ||
6373 (MatchRC.second != InputRC.second)) {
6374 report_fatal_error("Unsupported asm: input constraint"
6375 " with a matching output constraint of"
6376 " incompatible type!");
6378 Input.ConstraintVT = OpInfo.ConstraintVT;
6382 // Compute the constraint code and ConstraintType to use.
6383 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6385 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6386 OpInfo.Type == InlineAsm::isClobber)
6389 // If this is a memory input, and if the operand is not indirect, do what we
6390 // need to to provide an address for the memory input.
6391 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6392 !OpInfo.isIndirect) {
6393 assert((OpInfo.isMultipleAlternative ||
6394 (OpInfo.Type == InlineAsm::isInput)) &&
6395 "Can only indirectify direct input operands!");
6397 // Memory operands really want the address of the value. If we don't have
6398 // an indirect input, put it in the constpool if we can, otherwise spill
6399 // it to a stack slot.
6400 // TODO: This isn't quite right. We need to handle these according to
6401 // the addressing mode that the constraint wants. Also, this may take
6402 // an additional register for the computation and we don't want that
6405 // If the operand is a float, integer, or vector constant, spill to a
6406 // constant pool entry to get its address.
6407 const Value *OpVal = OpInfo.CallOperandVal;
6408 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6409 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6410 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6411 TLI->getPointerTy());
6413 // Otherwise, create a stack slot and emit a store to it before the
6415 Type *Ty = OpVal->getType();
6416 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6417 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6418 MachineFunction &MF = DAG.getMachineFunction();
6419 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6420 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6421 Chain = DAG.getStore(Chain, getCurSDLoc(),
6422 OpInfo.CallOperand, StackSlot,
6423 MachinePointerInfo::getFixedStack(SSFI),
6425 OpInfo.CallOperand = StackSlot;
6428 // There is no longer a Value* corresponding to this operand.
6429 OpInfo.CallOperandVal = 0;
6431 // It is now an indirect operand.
6432 OpInfo.isIndirect = true;
6435 // If this constraint is for a specific register, allocate it before
6437 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6438 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6441 // Second pass - Loop over all of the operands, assigning virtual or physregs
6442 // to register class operands.
6443 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6444 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6446 // C_Register operands have already been allocated, Other/Memory don't need
6448 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6449 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6452 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6453 std::vector<SDValue> AsmNodeOperands;
6454 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6455 AsmNodeOperands.push_back(
6456 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6457 TLI->getPointerTy()));
6459 // If we have a !srcloc metadata node associated with it, we want to attach
6460 // this to the ultimately generated inline asm machineinstr. To do this, we
6461 // pass in the third operand as this (potentially null) inline asm MDNode.
6462 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6463 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6465 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6466 // bits as operand 3.
6467 unsigned ExtraInfo = 0;
6468 if (IA->hasSideEffects())
6469 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6470 if (IA->isAlignStack())
6471 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6472 // Set the asm dialect.
6473 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6475 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6476 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6477 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6479 // Compute the constraint code and ConstraintType to use.
6480 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6482 // Ideally, we would only check against memory constraints. However, the
6483 // meaning of an other constraint can be target-specific and we can't easily
6484 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6485 // for other constriants as well.
6486 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6487 OpInfo.ConstraintType == TargetLowering::C_Other) {
6488 if (OpInfo.Type == InlineAsm::isInput)
6489 ExtraInfo |= InlineAsm::Extra_MayLoad;
6490 else if (OpInfo.Type == InlineAsm::isOutput)
6491 ExtraInfo |= InlineAsm::Extra_MayStore;
6492 else if (OpInfo.Type == InlineAsm::isClobber)
6493 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6497 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6498 TLI->getPointerTy()));
6500 // Loop over all of the inputs, copying the operand values into the
6501 // appropriate registers and processing the output regs.
6502 RegsForValue RetValRegs;
6504 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6505 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6507 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6508 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6510 switch (OpInfo.Type) {
6511 case InlineAsm::isOutput: {
6512 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6513 OpInfo.ConstraintType != TargetLowering::C_Register) {
6514 // Memory output, or 'other' output (e.g. 'X' constraint).
6515 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6517 // Add information to the INLINEASM node to know about this output.
6518 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6519 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6520 TLI->getPointerTy()));
6521 AsmNodeOperands.push_back(OpInfo.CallOperand);
6525 // Otherwise, this is a register or register class output.
6527 // Copy the output from the appropriate register. Find a register that
6529 if (OpInfo.AssignedRegs.Regs.empty()) {
6530 LLVMContext &Ctx = *DAG.getContext();
6531 Ctx.emitError(CS.getInstruction(),
6532 "couldn't allocate output register for constraint '" +
6533 Twine(OpInfo.ConstraintCode) + "'");
6537 // If this is an indirect operand, store through the pointer after the
6539 if (OpInfo.isIndirect) {
6540 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6541 OpInfo.CallOperandVal));
6543 // This is the result value of the call.
6544 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6545 // Concatenate this output onto the outputs list.
6546 RetValRegs.append(OpInfo.AssignedRegs);
6549 // Add information to the INLINEASM node to know that this register is
6552 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6553 ? InlineAsm::Kind_RegDefEarlyClobber
6554 : InlineAsm::Kind_RegDef,
6555 false, 0, DAG, AsmNodeOperands);
6558 case InlineAsm::isInput: {
6559 SDValue InOperandVal = OpInfo.CallOperand;
6561 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6562 // If this is required to match an output register we have already set,
6563 // just use its register.
6564 unsigned OperandNo = OpInfo.getMatchedOperand();
6566 // Scan until we find the definition we already emitted of this operand.
6567 // When we find it, create a RegsForValue operand.
6568 unsigned CurOp = InlineAsm::Op_FirstOperand;
6569 for (; OperandNo; --OperandNo) {
6570 // Advance to the next operand.
6572 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6573 assert((InlineAsm::isRegDefKind(OpFlag) ||
6574 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6575 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6576 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6580 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6581 if (InlineAsm::isRegDefKind(OpFlag) ||
6582 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6583 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6584 if (OpInfo.isIndirect) {
6585 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6586 LLVMContext &Ctx = *DAG.getContext();
6587 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6588 " don't know how to handle tied "
6589 "indirect register inputs");
6593 RegsForValue MatchedRegs;
6594 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6595 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6596 MatchedRegs.RegVTs.push_back(RegVT);
6597 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6598 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6600 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6601 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6603 LLVMContext &Ctx = *DAG.getContext();
6604 Ctx.emitError(CS.getInstruction(),
6605 "inline asm error: This value"
6606 " type register class is not natively supported!");
6610 // Use the produced MatchedRegs object to
6611 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6612 Chain, &Flag, CS.getInstruction());
6613 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6614 true, OpInfo.getMatchedOperand(),
6615 DAG, AsmNodeOperands);
6619 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6620 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6621 "Unexpected number of operands");
6622 // Add information to the INLINEASM node to know about this input.
6623 // See InlineAsm.h isUseOperandTiedToDef.
6624 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6625 OpInfo.getMatchedOperand());
6626 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6627 TLI->getPointerTy()));
6628 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6632 // Treat indirect 'X' constraint as memory.
6633 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6635 OpInfo.ConstraintType = TargetLowering::C_Memory;
6637 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6638 std::vector<SDValue> Ops;
6639 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6642 LLVMContext &Ctx = *DAG.getContext();
6643 Ctx.emitError(CS.getInstruction(),
6644 "invalid operand for inline asm constraint '" +
6645 Twine(OpInfo.ConstraintCode) + "'");
6649 // Add information to the INLINEASM node to know about this input.
6650 unsigned ResOpType =
6651 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6652 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6653 TLI->getPointerTy()));
6654 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6658 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6659 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6660 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6661 "Memory operands expect pointer values");
6663 // Add information to the INLINEASM node to know about this input.
6664 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6665 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6666 TLI->getPointerTy()));
6667 AsmNodeOperands.push_back(InOperandVal);
6671 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6672 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6673 "Unknown constraint type!");
6675 // TODO: Support this.
6676 if (OpInfo.isIndirect) {
6677 LLVMContext &Ctx = *DAG.getContext();
6678 Ctx.emitError(CS.getInstruction(),
6679 "Don't know how to handle indirect register inputs yet "
6680 "for constraint '" +
6681 Twine(OpInfo.ConstraintCode) + "'");
6685 // Copy the input into the appropriate registers.
6686 if (OpInfo.AssignedRegs.Regs.empty()) {
6687 LLVMContext &Ctx = *DAG.getContext();
6688 Ctx.emitError(CS.getInstruction(),
6689 "couldn't allocate input reg for constraint '" +
6690 Twine(OpInfo.ConstraintCode) + "'");
6694 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6695 Chain, &Flag, CS.getInstruction());
6697 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6698 DAG, AsmNodeOperands);
6701 case InlineAsm::isClobber: {
6702 // Add the clobbered value to the operand list, so that the register
6703 // allocator is aware that the physreg got clobbered.
6704 if (!OpInfo.AssignedRegs.Regs.empty())
6705 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6713 // Finish up input operands. Set the input chain and add the flag last.
6714 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6715 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6717 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6718 DAG.getVTList(MVT::Other, MVT::Glue),
6719 &AsmNodeOperands[0], AsmNodeOperands.size());
6720 Flag = Chain.getValue(1);
6722 // If this asm returns a register value, copy the result from that register
6723 // and set it as the value of the call.
6724 if (!RetValRegs.Regs.empty()) {
6725 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6726 Chain, &Flag, CS.getInstruction());
6728 // FIXME: Why don't we do this for inline asms with MRVs?
6729 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6730 EVT ResultType = TLI->getValueType(CS.getType());
6732 // If any of the results of the inline asm is a vector, it may have the
6733 // wrong width/num elts. This can happen for register classes that can
6734 // contain multiple different value types. The preg or vreg allocated may
6735 // not have the same VT as was expected. Convert it to the right type
6736 // with bit_convert.
6737 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6738 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6741 } else if (ResultType != Val.getValueType() &&
6742 ResultType.isInteger() && Val.getValueType().isInteger()) {
6743 // If a result value was tied to an input value, the computed result may
6744 // have a wider width than the expected result. Extract the relevant
6746 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6749 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6752 setValue(CS.getInstruction(), Val);
6753 // Don't need to use this as a chain in this case.
6754 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6758 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6760 // Process indirect outputs, first output all of the flagged copies out of
6762 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6763 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6764 const Value *Ptr = IndirectStoresToEmit[i].second;
6765 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6767 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6770 // Emit the non-flagged stores from the physregs.
6771 SmallVector<SDValue, 8> OutChains;
6772 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6773 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6774 StoresToEmit[i].first,
6775 getValue(StoresToEmit[i].second),
6776 MachinePointerInfo(StoresToEmit[i].second),
6778 OutChains.push_back(Val);
6781 if (!OutChains.empty())
6782 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6783 &OutChains[0], OutChains.size());
6788 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6789 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6790 MVT::Other, getRoot(),
6791 getValue(I.getArgOperand(0)),
6792 DAG.getSrcValue(I.getArgOperand(0))));
6795 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6796 const TargetLowering *TLI = TM.getTargetLowering();
6797 const DataLayout &TD = *TLI->getDataLayout();
6798 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6799 getRoot(), getValue(I.getOperand(0)),
6800 DAG.getSrcValue(I.getOperand(0)),
6801 TD.getABITypeAlignment(I.getType()));
6803 DAG.setRoot(V.getValue(1));
6806 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6807 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6808 MVT::Other, getRoot(),
6809 getValue(I.getArgOperand(0)),
6810 DAG.getSrcValue(I.getArgOperand(0))));
6813 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6814 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6815 MVT::Other, getRoot(),
6816 getValue(I.getArgOperand(0)),
6817 getValue(I.getArgOperand(1)),
6818 DAG.getSrcValue(I.getArgOperand(0)),
6819 DAG.getSrcValue(I.getArgOperand(1))));
6822 /// \brief Lower an argument list according to the target calling convention.
6824 /// \return A tuple of <return-value, token-chain>
6826 /// This is a helper for lowering intrinsics that follow a target calling
6827 /// convention or require stack pointer adjustment. Only a subset of the
6828 /// intrinsic's operands need to participate in the calling convention.
6829 std::pair<SDValue, SDValue>
6830 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6831 unsigned NumArgs, SDValue Callee,
6833 TargetLowering::ArgListTy Args;
6834 Args.reserve(NumArgs);
6836 // Populate the argument list.
6837 // Attributes for args start at offset 1, after the return attribute.
6838 ImmutableCallSite CS(&CI);
6839 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6840 ArgI != ArgE; ++ArgI) {
6841 const Value *V = CI.getOperand(ArgI);
6843 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6845 TargetLowering::ArgListEntry Entry;
6846 Entry.Node = getValue(V);
6847 Entry.Ty = V->getType();
6848 Entry.setAttributes(&CS, AttrI);
6849 Args.push_back(Entry);
6852 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6853 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false,
6854 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs,
6855 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false,
6856 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc());
6858 const TargetLowering *TLI = TM.getTargetLowering();
6859 return TLI->LowerCallTo(CLI);
6862 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6863 /// or patchpoint target node's operand list.
6865 /// Constants are converted to TargetConstants purely as an optimization to
6866 /// avoid constant materialization and register allocation.
6868 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6869 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6870 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6871 /// address materialization and register allocation, but may also be required
6872 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6873 /// alloca in the entry block, then the runtime may assume that the alloca's
6874 /// StackMap location can be read immediately after compilation and that the
6875 /// location is valid at any point during execution (this is similar to the
6876 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6877 /// only available in a register, then the runtime would need to trap when
6878 /// execution reaches the StackMap in order to read the alloca's location.
6879 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6880 SmallVectorImpl<SDValue> &Ops,
6881 SelectionDAGBuilder &Builder) {
6882 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6883 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6886 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6888 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6889 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6890 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6892 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6894 Ops.push_back(OpVal);
6898 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6899 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6900 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6901 // [live variables...])
6903 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6905 SDValue Chain, InFlag, Callee, NullPtr;
6906 SmallVector<SDValue, 32> Ops;
6908 SDLoc DL = getCurSDLoc();
6909 Callee = getValue(CI.getCalledValue());
6910 NullPtr = DAG.getIntPtrConstant(0, true);
6912 // The stackmap intrinsic only records the live variables (the arguemnts
6913 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6914 // intrinsic, this won't be lowered to a function call. This means we don't
6915 // have to worry about calling conventions and target specific lowering code.
6916 // Instead we perform the call lowering right here.
6918 // chain, flag = CALLSEQ_START(chain, 0)
6919 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6920 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6922 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6923 InFlag = Chain.getValue(1);
6925 // Add the <id> and <numBytes> constants.
6926 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6927 Ops.push_back(DAG.getTargetConstant(
6928 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6929 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6930 Ops.push_back(DAG.getTargetConstant(
6931 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6933 // Push live variables for the stack map.
6934 addStackMapLiveVars(CI, 2, Ops, *this);
6936 // We are not pushing any register mask info here on the operands list,
6937 // because the stackmap doesn't clobber anything.
6939 // Push the chain and the glue flag.
6940 Ops.push_back(Chain);
6941 Ops.push_back(InFlag);
6943 // Create the STACKMAP node.
6944 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6945 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6946 Chain = SDValue(SM, 0);
6947 InFlag = Chain.getValue(1);
6949 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6951 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6953 // Set the root to the target-lowered call chain.
6956 // Inform the Frame Information that we have a stackmap in this function.
6957 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6960 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6961 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6962 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6967 // [live variables...])
6969 CallingConv::ID CC = CI.getCallingConv();
6970 bool isAnyRegCC = CC == CallingConv::AnyReg;
6971 bool hasDef = !CI.getType()->isVoidTy();
6972 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6974 // Get the real number of arguments participating in the call <numArgs>
6975 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6976 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6978 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6979 // Intrinsics include all meta-operands up to but not including CC.
6980 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6981 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6982 "Not enough arguments provided to the patchpoint intrinsic");
6984 // For AnyRegCC the arguments are lowered later on manually.
6985 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6986 std::pair<SDValue, SDValue> Result =
6987 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6989 // Set the root to the target-lowered call chain.
6990 SDValue Chain = Result.second;
6993 SDNode *CallEnd = Chain.getNode();
6994 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6995 CallEnd = CallEnd->getOperand(0).getNode();
6997 /// Get a call instruction from the call sequence chain.
6998 /// Tail calls are not allowed.
6999 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7000 "Expected a callseq node.");
7001 SDNode *Call = CallEnd->getOperand(0).getNode();
7002 bool hasGlue = Call->getGluedNode();
7004 // Replace the target specific call node with the patchable intrinsic.
7005 SmallVector<SDValue, 8> Ops;
7007 // Add the <id> and <numBytes> constants.
7008 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7009 Ops.push_back(DAG.getTargetConstant(
7010 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7011 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7012 Ops.push_back(DAG.getTargetConstant(
7013 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7015 // Assume that the Callee is a constant address.
7016 // FIXME: handle function symbols in the future.
7018 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7019 /*isTarget=*/true));
7021 // Adjust <numArgs> to account for any arguments that have been passed on the
7023 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7024 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7025 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7026 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7028 // Add the calling convention
7029 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7031 // Add the arguments we omitted previously. The register allocator should
7032 // place these in any free register.
7034 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7035 Ops.push_back(getValue(CI.getArgOperand(i)));
7037 // Push the arguments from the call instruction up to the register mask.
7038 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7039 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7042 // Push live variables for the stack map.
7043 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7045 // Push the register mask info.
7047 Ops.push_back(*(Call->op_end()-2));
7049 Ops.push_back(*(Call->op_end()-1));
7051 // Push the chain (this is originally the first operand of the call, but
7052 // becomes now the last or second to last operand).
7053 Ops.push_back(*(Call->op_begin()));
7055 // Push the glue flag (last operand).
7057 Ops.push_back(*(Call->op_end()-1));
7060 if (isAnyRegCC && hasDef) {
7061 // Create the return types based on the intrinsic definition
7062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7063 SmallVector<EVT, 3> ValueVTs;
7064 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7065 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7067 // There is always a chain and a glue type at the end
7068 ValueVTs.push_back(MVT::Other);
7069 ValueVTs.push_back(MVT::Glue);
7070 NodeTys = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
7072 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7074 // Replace the target specific call node with a PATCHPOINT node.
7075 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7076 getCurSDLoc(), NodeTys, Ops);
7078 // Update the NodeMap.
7081 setValue(&CI, SDValue(MN, 0));
7083 setValue(&CI, Result.first);
7086 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7087 // call sequence. Furthermore the location of the chain and glue can change
7088 // when the AnyReg calling convention is used and the intrinsic returns a
7090 if (isAnyRegCC && hasDef) {
7091 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7092 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7093 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7095 DAG.ReplaceAllUsesWith(Call, MN);
7096 DAG.DeleteNode(Call);
7098 // Inform the Frame Information that we have a patchpoint in this function.
7099 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7102 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7103 /// implementation, which just calls LowerCall.
7104 /// FIXME: When all targets are
7105 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7106 std::pair<SDValue, SDValue>
7107 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7108 // Handle the incoming return values from the call.
7110 SmallVector<EVT, 4> RetTys;
7111 ComputeValueVTs(*this, CLI.RetTy, RetTys);
7112 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7114 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7115 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7116 for (unsigned i = 0; i != NumRegs; ++i) {
7117 ISD::InputArg MyFlags;
7118 MyFlags.VT = RegisterVT;
7120 MyFlags.Used = CLI.IsReturnValueUsed;
7122 MyFlags.Flags.setSExt();
7124 MyFlags.Flags.setZExt();
7126 MyFlags.Flags.setInReg();
7127 CLI.Ins.push_back(MyFlags);
7131 // Handle all of the outgoing arguments.
7133 CLI.OutVals.clear();
7134 ArgListTy &Args = CLI.Args;
7135 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7136 SmallVector<EVT, 4> ValueVTs;
7137 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7138 for (unsigned Value = 0, NumValues = ValueVTs.size();
7139 Value != NumValues; ++Value) {
7140 EVT VT = ValueVTs[Value];
7141 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7142 SDValue Op = SDValue(Args[i].Node.getNode(),
7143 Args[i].Node.getResNo() + Value);
7144 ISD::ArgFlagsTy Flags;
7145 unsigned OriginalAlignment =
7146 getDataLayout()->getABITypeAlignment(ArgTy);
7152 if (Args[i].isInReg)
7156 if (Args[i].isByVal)
7158 if (Args[i].isInAlloca) {
7159 Flags.setInAlloca();
7160 // Set the byval flag for CCAssignFn callbacks that don't know about
7161 // inalloca. This way we can know how many bytes we should've allocated
7162 // and how many bytes a callee cleanup function will pop. If we port
7163 // inalloca to more targets, we'll have to add custom inalloca handling
7164 // in the various CC lowering callbacks.
7167 if (Args[i].isByVal || Args[i].isInAlloca) {
7168 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7169 Type *ElementTy = Ty->getElementType();
7170 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7171 // For ByVal, alignment should come from FE. BE will guess if this
7172 // info is not there but there are cases it cannot get right.
7173 unsigned FrameAlign;
7174 if (Args[i].Alignment)
7175 FrameAlign = Args[i].Alignment;
7177 FrameAlign = getByValTypeAlignment(ElementTy);
7178 Flags.setByValAlign(FrameAlign);
7182 Flags.setOrigAlign(OriginalAlignment);
7184 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7185 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7186 SmallVector<SDValue, 4> Parts(NumParts);
7187 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7190 ExtendKind = ISD::SIGN_EXTEND;
7191 else if (Args[i].isZExt)
7192 ExtendKind = ISD::ZERO_EXTEND;
7194 // Conservatively only handle 'returned' on non-vectors for now
7195 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7196 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7197 "unexpected use of 'returned'");
7198 // Before passing 'returned' to the target lowering code, ensure that
7199 // either the register MVT and the actual EVT are the same size or that
7200 // the return value and argument are extended in the same way; in these
7201 // cases it's safe to pass the argument register value unchanged as the
7202 // return register value (although it's at the target's option whether
7204 // TODO: allow code generation to take advantage of partially preserved
7205 // registers rather than clobbering the entire register when the
7206 // parameter extension method is not compatible with the return
7208 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7209 (ExtendKind != ISD::ANY_EXTEND &&
7210 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7211 Flags.setReturned();
7214 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
7215 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind);
7217 for (unsigned j = 0; j != NumParts; ++j) {
7218 // if it isn't first piece, alignment must be 1
7219 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7220 i < CLI.NumFixedArgs,
7221 i, j*Parts[j].getValueType().getStoreSize());
7222 if (NumParts > 1 && j == 0)
7223 MyFlags.Flags.setSplit();
7225 MyFlags.Flags.setOrigAlign(1);
7227 CLI.Outs.push_back(MyFlags);
7228 CLI.OutVals.push_back(Parts[j]);
7233 SmallVector<SDValue, 4> InVals;
7234 CLI.Chain = LowerCall(CLI, InVals);
7236 // Verify that the target's LowerCall behaved as expected.
7237 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7238 "LowerCall didn't return a valid chain!");
7239 assert((!CLI.IsTailCall || InVals.empty()) &&
7240 "LowerCall emitted a return value for a tail call!");
7241 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7242 "LowerCall didn't emit the correct number of values!");
7244 // For a tail call, the return value is merely live-out and there aren't
7245 // any nodes in the DAG representing it. Return a special value to
7246 // indicate that a tail call has been emitted and no more Instructions
7247 // should be processed in the current block.
7248 if (CLI.IsTailCall) {
7249 CLI.DAG.setRoot(CLI.Chain);
7250 return std::make_pair(SDValue(), SDValue());
7253 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7254 assert(InVals[i].getNode() &&
7255 "LowerCall emitted a null value!");
7256 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7257 "LowerCall emitted a value with the wrong type!");
7260 // Collect the legal value parts into potentially illegal values
7261 // that correspond to the original function's return values.
7262 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7264 AssertOp = ISD::AssertSext;
7265 else if (CLI.RetZExt)
7266 AssertOp = ISD::AssertZext;
7267 SmallVector<SDValue, 4> ReturnValues;
7268 unsigned CurReg = 0;
7269 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7271 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7272 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7274 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7275 NumRegs, RegisterVT, VT, NULL,
7280 // For a function returning void, there is no return value. We can't create
7281 // such a node, so we just return a null return value in that case. In
7282 // that case, nothing will actually look at the value.
7283 if (ReturnValues.empty())
7284 return std::make_pair(SDValue(), CLI.Chain);
7286 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7287 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
7288 &ReturnValues[0], ReturnValues.size());
7289 return std::make_pair(Res, CLI.Chain);
7292 void TargetLowering::LowerOperationWrapper(SDNode *N,
7293 SmallVectorImpl<SDValue> &Results,
7294 SelectionDAG &DAG) const {
7295 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7297 Results.push_back(Res);
7300 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7301 llvm_unreachable("LowerOperation not implemented for this target!");
7305 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7306 SDValue Op = getNonRegisterValue(V);
7307 assert((Op.getOpcode() != ISD::CopyFromReg ||
7308 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7309 "Copy from a reg to the same reg!");
7310 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7312 const TargetLowering *TLI = TM.getTargetLowering();
7313 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7314 SDValue Chain = DAG.getEntryNode();
7315 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V);
7316 PendingExports.push_back(Chain);
7319 #include "llvm/CodeGen/SelectionDAGISel.h"
7321 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7322 /// entry block, return true. This includes arguments used by switches, since
7323 /// the switch may expand into multiple basic blocks.
7324 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7325 // With FastISel active, we may be splitting blocks, so force creation
7326 // of virtual registers for all non-dead arguments.
7328 return A->use_empty();
7330 const BasicBlock *Entry = A->getParent()->begin();
7331 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
7333 const User *U = *UI;
7334 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7335 return false; // Use not in entry block.
7340 void SelectionDAGISel::LowerArguments(const Function &F) {
7341 SelectionDAG &DAG = SDB->DAG;
7342 SDLoc dl = SDB->getCurSDLoc();
7343 const TargetLowering *TLI = getTargetLowering();
7344 const DataLayout *TD = TLI->getDataLayout();
7345 SmallVector<ISD::InputArg, 16> Ins;
7347 if (!FuncInfo->CanLowerReturn) {
7348 // Put in an sret pointer parameter before all the other parameters.
7349 SmallVector<EVT, 1> ValueVTs;
7350 ComputeValueVTs(*getTargetLowering(),
7351 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7353 // NOTE: Assuming that a pointer will never break down to more than one VT
7355 ISD::ArgFlagsTy Flags;
7357 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7358 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7359 Ins.push_back(RetArg);
7362 // Set up the incoming argument description vector.
7364 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7365 I != E; ++I, ++Idx) {
7366 SmallVector<EVT, 4> ValueVTs;
7367 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7368 bool isArgValueUsed = !I->use_empty();
7369 unsigned PartBase = 0;
7370 for (unsigned Value = 0, NumValues = ValueVTs.size();
7371 Value != NumValues; ++Value) {
7372 EVT VT = ValueVTs[Value];
7373 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7374 ISD::ArgFlagsTy Flags;
7375 unsigned OriginalAlignment =
7376 TD->getABITypeAlignment(ArgTy);
7378 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7380 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7382 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7384 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7386 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7388 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7389 Flags.setInAlloca();
7390 // Set the byval flag for CCAssignFn callbacks that don't know about
7391 // inalloca. This way we can know how many bytes we should've allocated
7392 // and how many bytes a callee cleanup function will pop. If we port
7393 // inalloca to more targets, we'll have to add custom inalloca handling
7394 // in the various CC lowering callbacks.
7397 if (Flags.isByVal() || Flags.isInAlloca()) {
7398 PointerType *Ty = cast<PointerType>(I->getType());
7399 Type *ElementTy = Ty->getElementType();
7400 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
7401 // For ByVal, alignment should be passed from FE. BE will guess if
7402 // this info is not there but there are cases it cannot get right.
7403 unsigned FrameAlign;
7404 if (F.getParamAlignment(Idx))
7405 FrameAlign = F.getParamAlignment(Idx);
7407 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7408 Flags.setByValAlign(FrameAlign);
7410 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7412 Flags.setOrigAlign(OriginalAlignment);
7414 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7415 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7416 for (unsigned i = 0; i != NumRegs; ++i) {
7417 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7418 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7419 if (NumRegs > 1 && i == 0)
7420 MyFlags.Flags.setSplit();
7421 // if it isn't first piece, alignment must be 1
7423 MyFlags.Flags.setOrigAlign(1);
7424 Ins.push_back(MyFlags);
7426 PartBase += VT.getStoreSize();
7430 // Call the target to set up the argument values.
7431 SmallVector<SDValue, 8> InVals;
7432 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7436 // Verify that the target's LowerFormalArguments behaved as expected.
7437 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7438 "LowerFormalArguments didn't return a valid chain!");
7439 assert(InVals.size() == Ins.size() &&
7440 "LowerFormalArguments didn't emit the correct number of values!");
7442 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7443 assert(InVals[i].getNode() &&
7444 "LowerFormalArguments emitted a null value!");
7445 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7446 "LowerFormalArguments emitted a value with the wrong type!");
7450 // Update the DAG with the new chain value resulting from argument lowering.
7451 DAG.setRoot(NewRoot);
7453 // Set up the argument values.
7456 if (!FuncInfo->CanLowerReturn) {
7457 // Create a virtual register for the sret pointer, and put in a copy
7458 // from the sret argument into it.
7459 SmallVector<EVT, 1> ValueVTs;
7460 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7461 MVT VT = ValueVTs[0].getSimpleVT();
7462 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7463 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7464 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7465 RegVT, VT, NULL, AssertOp);
7467 MachineFunction& MF = SDB->DAG.getMachineFunction();
7468 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7469 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7470 FuncInfo->DemoteRegister = SRetReg;
7471 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7473 DAG.setRoot(NewRoot);
7475 // i indexes lowered arguments. Bump it past the hidden sret argument.
7476 // Idx indexes LLVM arguments. Don't touch it.
7480 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7482 SmallVector<SDValue, 4> ArgValues;
7483 SmallVector<EVT, 4> ValueVTs;
7484 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7485 unsigned NumValues = ValueVTs.size();
7487 // If this argument is unused then remember its value. It is used to generate
7488 // debugging information.
7489 if (I->use_empty() && NumValues) {
7490 SDB->setUnusedArgValue(I, InVals[i]);
7492 // Also remember any frame index for use in FastISel.
7493 if (FrameIndexSDNode *FI =
7494 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7495 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7498 for (unsigned Val = 0; Val != NumValues; ++Val) {
7499 EVT VT = ValueVTs[Val];
7500 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7501 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7503 if (!I->use_empty()) {
7504 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7505 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7506 AssertOp = ISD::AssertSext;
7507 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7508 AssertOp = ISD::AssertZext;
7510 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7511 NumParts, PartVT, VT,
7518 // We don't need to do anything else for unused arguments.
7519 if (ArgValues.empty())
7522 // Note down frame index.
7523 if (FrameIndexSDNode *FI =
7524 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7525 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7527 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7528 SDB->getCurSDLoc());
7530 SDB->setValue(I, Res);
7531 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7532 if (LoadSDNode *LNode =
7533 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7534 if (FrameIndexSDNode *FI =
7535 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7536 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7539 // If this argument is live outside of the entry block, insert a copy from
7540 // wherever we got it to the vreg that other BB's will reference it as.
7541 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7542 // If we can, though, try to skip creating an unnecessary vreg.
7543 // FIXME: This isn't very clean... it would be nice to make this more
7544 // general. It's also subtly incompatible with the hacks FastISel
7546 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7547 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7548 FuncInfo->ValueMap[I] = Reg;
7552 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7553 FuncInfo->InitializeRegForValue(I);
7554 SDB->CopyToExportRegsIfNeeded(I);
7558 assert(i == InVals.size() && "Argument register count mismatch!");
7560 // Finally, if the target has anything special to do, allow it to do so.
7561 // FIXME: this should insert code into the DAG!
7562 EmitFunctionEntryCode();
7565 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7566 /// ensure constants are generated when needed. Remember the virtual registers
7567 /// that need to be added to the Machine PHI nodes as input. We cannot just
7568 /// directly add them, because expansion might result in multiple MBB's for one
7569 /// BB. As such, the start of the BB might correspond to a different MBB than
7573 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7574 const TerminatorInst *TI = LLVMBB->getTerminator();
7576 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7578 // Check successor nodes' PHI nodes that expect a constant to be available
7580 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7581 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7582 if (!isa<PHINode>(SuccBB->begin())) continue;
7583 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7585 // If this terminator has multiple identical successors (common for
7586 // switches), only handle each succ once.
7587 if (!SuccsHandled.insert(SuccMBB)) continue;
7589 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7591 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7592 // nodes and Machine PHI nodes, but the incoming operands have not been
7594 for (BasicBlock::const_iterator I = SuccBB->begin();
7595 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7596 // Ignore dead phi's.
7597 if (PN->use_empty()) continue;
7600 if (PN->getType()->isEmptyTy())
7604 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7606 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7607 unsigned &RegOut = ConstantsOut[C];
7609 RegOut = FuncInfo.CreateRegs(C->getType());
7610 CopyValueToVirtualRegister(C, RegOut);
7614 DenseMap<const Value *, unsigned>::iterator I =
7615 FuncInfo.ValueMap.find(PHIOp);
7616 if (I != FuncInfo.ValueMap.end())
7619 assert(isa<AllocaInst>(PHIOp) &&
7620 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7621 "Didn't codegen value into a register!??");
7622 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7623 CopyValueToVirtualRegister(PHIOp, Reg);
7627 // Remember that this register needs to added to the machine PHI node as
7628 // the input for this MBB.
7629 SmallVector<EVT, 4> ValueVTs;
7630 const TargetLowering *TLI = TM.getTargetLowering();
7631 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7632 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7633 EVT VT = ValueVTs[vti];
7634 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7635 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7636 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7637 Reg += NumRegisters;
7642 ConstantsOut.clear();
7645 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7648 SelectionDAGBuilder::StackProtectorDescriptor::
7649 AddSuccessorMBB(const BasicBlock *BB,
7650 MachineBasicBlock *ParentMBB,
7651 MachineBasicBlock *SuccMBB) {
7652 // If SuccBB has not been created yet, create it.
7654 MachineFunction *MF = ParentMBB->getParent();
7655 MachineFunction::iterator BBI = ParentMBB;
7656 SuccMBB = MF->CreateMachineBasicBlock(BB);
7657 MF->insert(++BBI, SuccMBB);
7659 // Add it as a successor of ParentMBB.
7660 ParentMBB->addSuccessor(SuccMBB);