1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 // Update machine-CFG edges.
1164 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1165 MachineBasicBlock *CatchingMBB = FuncInfo.MBBMap[I.getNormalDest()];
1166 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1167 PadMBB->addSuccessor(CatchingMBB);
1168 PadMBB->addSuccessor(UnwindMBB);
1170 CatchingMBB->setIsEHFuncletEntry();
1171 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1172 MMI.setHasEHFunclets(true);
1175 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1176 // Update machine-CFG edge.
1177 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1178 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1179 PadMBB->addSuccessor(TargetMBB);
1181 // Create the terminator node.
1182 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1183 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1187 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1188 // If this unwinds to caller, we don't need a DAG node hanging around.
1189 if (!I.hasUnwindDest())
1192 // Update machine-CFG edge.
1193 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1194 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1195 PadMBB->addSuccessor(UnwindMBB);
1198 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1199 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1200 MMI.setHasEHFunclets(true);
1201 report_fatal_error("visitCleanupPad not yet implemented!");
1204 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1205 report_fatal_error("visitCleanupRet not yet implemented!");
1208 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1209 report_fatal_error("visitCleanupEndPad not yet implemented!");
1212 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1213 report_fatal_error("visitTerminatePad not yet implemented!");
1216 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1217 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1218 auto &DL = DAG.getDataLayout();
1219 SDValue Chain = getControlRoot();
1220 SmallVector<ISD::OutputArg, 8> Outs;
1221 SmallVector<SDValue, 8> OutVals;
1223 if (!FuncInfo.CanLowerReturn) {
1224 unsigned DemoteReg = FuncInfo.DemoteRegister;
1225 const Function *F = I.getParent()->getParent();
1227 // Emit a store of the return value through the virtual register.
1228 // Leave Outs empty so that LowerReturn won't try to load return
1229 // registers the usual way.
1230 SmallVector<EVT, 1> PtrValueVTs;
1231 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1234 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1235 SDValue RetOp = getValue(I.getOperand(0));
1237 SmallVector<EVT, 4> ValueVTs;
1238 SmallVector<uint64_t, 4> Offsets;
1239 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1240 unsigned NumValues = ValueVTs.size();
1242 SmallVector<SDValue, 4> Chains(NumValues);
1243 for (unsigned i = 0; i != NumValues; ++i) {
1244 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1245 RetPtr.getValueType(), RetPtr,
1246 DAG.getIntPtrConstant(Offsets[i],
1249 DAG.getStore(Chain, getCurSDLoc(),
1250 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1251 // FIXME: better loc info would be nice.
1252 Add, MachinePointerInfo(), false, false, 0);
1255 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1256 MVT::Other, Chains);
1257 } else if (I.getNumOperands() != 0) {
1258 SmallVector<EVT, 4> ValueVTs;
1259 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1260 unsigned NumValues = ValueVTs.size();
1262 SDValue RetOp = getValue(I.getOperand(0));
1264 const Function *F = I.getParent()->getParent();
1266 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1267 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1269 ExtendKind = ISD::SIGN_EXTEND;
1270 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1272 ExtendKind = ISD::ZERO_EXTEND;
1274 LLVMContext &Context = F->getContext();
1275 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1278 for (unsigned j = 0; j != NumValues; ++j) {
1279 EVT VT = ValueVTs[j];
1281 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1282 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1284 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1285 MVT PartVT = TLI.getRegisterType(Context, VT);
1286 SmallVector<SDValue, 4> Parts(NumParts);
1287 getCopyToParts(DAG, getCurSDLoc(),
1288 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1289 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1291 // 'inreg' on function refers to return value
1292 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1296 // Propagate extension type if any
1297 if (ExtendKind == ISD::SIGN_EXTEND)
1299 else if (ExtendKind == ISD::ZERO_EXTEND)
1302 for (unsigned i = 0; i < NumParts; ++i) {
1303 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1304 VT, /*isfixed=*/true, 0, 0));
1305 OutVals.push_back(Parts[i]);
1311 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1312 CallingConv::ID CallConv =
1313 DAG.getMachineFunction().getFunction()->getCallingConv();
1314 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1315 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1317 // Verify that the target's LowerReturn behaved as expected.
1318 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1319 "LowerReturn didn't return a valid chain!");
1321 // Update the DAG with the new chain value resulting from return lowering.
1325 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1326 /// created for it, emit nodes to copy the value into the virtual
1328 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1330 if (V->getType()->isEmptyTy())
1333 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1334 if (VMI != FuncInfo.ValueMap.end()) {
1335 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1336 CopyValueToVirtualRegister(V, VMI->second);
1340 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1341 /// the current basic block, add it to ValueMap now so that we'll get a
1343 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1344 // No need to export constants.
1345 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1347 // Already exported?
1348 if (FuncInfo.isExportedInst(V)) return;
1350 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1351 CopyValueToVirtualRegister(V, Reg);
1354 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1355 const BasicBlock *FromBB) {
1356 // The operands of the setcc have to be in this block. We don't know
1357 // how to export them from some other block.
1358 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1359 // Can export from current BB.
1360 if (VI->getParent() == FromBB)
1363 // Is already exported, noop.
1364 return FuncInfo.isExportedInst(V);
1367 // If this is an argument, we can export it if the BB is the entry block or
1368 // if it is already exported.
1369 if (isa<Argument>(V)) {
1370 if (FromBB == &FromBB->getParent()->getEntryBlock())
1373 // Otherwise, can only export this if it is already exported.
1374 return FuncInfo.isExportedInst(V);
1377 // Otherwise, constants can always be exported.
1381 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1382 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1383 const MachineBasicBlock *Dst) const {
1384 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1387 const BasicBlock *SrcBB = Src->getBasicBlock();
1388 const BasicBlock *DstBB = Dst->getBasicBlock();
1389 return BPI->getEdgeWeight(SrcBB, DstBB);
1392 void SelectionDAGBuilder::
1393 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1394 uint32_t Weight /* = 0 */) {
1396 Weight = getEdgeWeight(Src, Dst);
1397 Src->addSuccessor(Dst, Weight);
1401 static bool InBlock(const Value *V, const BasicBlock *BB) {
1402 if (const Instruction *I = dyn_cast<Instruction>(V))
1403 return I->getParent() == BB;
1407 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1408 /// This function emits a branch and is used at the leaves of an OR or an
1409 /// AND operator tree.
1412 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1413 MachineBasicBlock *TBB,
1414 MachineBasicBlock *FBB,
1415 MachineBasicBlock *CurBB,
1416 MachineBasicBlock *SwitchBB,
1419 const BasicBlock *BB = CurBB->getBasicBlock();
1421 // If the leaf of the tree is a comparison, merge the condition into
1423 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1424 // The operands of the cmp have to be in this block. We don't know
1425 // how to export them from some other block. If this is the first block
1426 // of the sequence, no exporting is needed.
1427 if (CurBB == SwitchBB ||
1428 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1429 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1430 ISD::CondCode Condition;
1431 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1432 Condition = getICmpCondCode(IC->getPredicate());
1434 const FCmpInst *FC = cast<FCmpInst>(Cond);
1435 Condition = getFCmpCondCode(FC->getPredicate());
1436 if (TM.Options.NoNaNsFPMath)
1437 Condition = getFCmpCodeWithoutNaN(Condition);
1440 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1441 TBB, FBB, CurBB, TWeight, FWeight);
1442 SwitchCases.push_back(CB);
1447 // Create a CaseBlock record representing this branch.
1448 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1449 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1450 SwitchCases.push_back(CB);
1453 /// Scale down both weights to fit into uint32_t.
1454 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1455 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1456 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1457 NewTrue = NewTrue / Scale;
1458 NewFalse = NewFalse / Scale;
1461 /// FindMergedConditions - If Cond is an expression like
1462 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1463 MachineBasicBlock *TBB,
1464 MachineBasicBlock *FBB,
1465 MachineBasicBlock *CurBB,
1466 MachineBasicBlock *SwitchBB,
1467 Instruction::BinaryOps Opc,
1470 // If this node is not part of the or/and tree, emit it as a branch.
1471 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1472 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1473 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1474 BOp->getParent() != CurBB->getBasicBlock() ||
1475 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1476 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1477 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1482 // Create TmpBB after CurBB.
1483 MachineFunction::iterator BBI = CurBB;
1484 MachineFunction &MF = DAG.getMachineFunction();
1485 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1486 CurBB->getParent()->insert(++BBI, TmpBB);
1488 if (Opc == Instruction::Or) {
1489 // Codegen X | Y as:
1498 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1499 // The requirement is that
1500 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1501 // = TrueProb for original BB.
1502 // Assuming the original weights are A and B, one choice is to set BB1's
1503 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1505 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1506 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1507 // TmpBB, but the math is more complicated.
1509 uint64_t NewTrueWeight = TWeight;
1510 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1511 ScaleWeights(NewTrueWeight, NewFalseWeight);
1512 // Emit the LHS condition.
1513 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1514 NewTrueWeight, NewFalseWeight);
1516 NewTrueWeight = TWeight;
1517 NewFalseWeight = 2 * (uint64_t)FWeight;
1518 ScaleWeights(NewTrueWeight, NewFalseWeight);
1519 // Emit the RHS condition into TmpBB.
1520 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1521 NewTrueWeight, NewFalseWeight);
1523 assert(Opc == Instruction::And && "Unknown merge op!");
1524 // Codegen X & Y as:
1532 // This requires creation of TmpBB after CurBB.
1534 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1535 // The requirement is that
1536 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1537 // = FalseProb for original BB.
1538 // Assuming the original weights are A and B, one choice is to set BB1's
1539 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1541 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1543 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1544 uint64_t NewFalseWeight = FWeight;
1545 ScaleWeights(NewTrueWeight, NewFalseWeight);
1546 // Emit the LHS condition.
1547 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1548 NewTrueWeight, NewFalseWeight);
1550 NewTrueWeight = 2 * (uint64_t)TWeight;
1551 NewFalseWeight = FWeight;
1552 ScaleWeights(NewTrueWeight, NewFalseWeight);
1553 // Emit the RHS condition into TmpBB.
1554 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1555 NewTrueWeight, NewFalseWeight);
1559 /// If the set of cases should be emitted as a series of branches, return true.
1560 /// If we should emit this as a bunch of and/or'd together conditions, return
1563 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1564 if (Cases.size() != 2) return true;
1566 // If this is two comparisons of the same values or'd or and'd together, they
1567 // will get folded into a single comparison, so don't emit two blocks.
1568 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1569 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1570 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1571 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1575 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1576 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1577 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1578 Cases[0].CC == Cases[1].CC &&
1579 isa<Constant>(Cases[0].CmpRHS) &&
1580 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1581 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1583 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1590 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1591 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1593 // Update machine-CFG edges.
1594 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1596 if (I.isUnconditional()) {
1597 // Update machine-CFG edges.
1598 BrMBB->addSuccessor(Succ0MBB);
1600 // If this is not a fall-through branch or optimizations are switched off,
1602 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1603 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1604 MVT::Other, getControlRoot(),
1605 DAG.getBasicBlock(Succ0MBB)));
1610 // If this condition is one of the special cases we handle, do special stuff
1612 const Value *CondVal = I.getCondition();
1613 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1615 // If this is a series of conditions that are or'd or and'd together, emit
1616 // this as a sequence of branches instead of setcc's with and/or operations.
1617 // As long as jumps are not expensive, this should improve performance.
1618 // For example, instead of something like:
1631 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1632 Instruction::BinaryOps Opcode = BOp->getOpcode();
1633 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1634 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1635 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1636 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1637 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1638 getEdgeWeight(BrMBB, Succ1MBB));
1639 // If the compares in later blocks need to use values not currently
1640 // exported from this block, export them now. This block should always
1641 // be the first entry.
1642 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1644 // Allow some cases to be rejected.
1645 if (ShouldEmitAsBranches(SwitchCases)) {
1646 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1647 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1648 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1651 // Emit the branch for this block.
1652 visitSwitchCase(SwitchCases[0], BrMBB);
1653 SwitchCases.erase(SwitchCases.begin());
1657 // Okay, we decided not to do this, remove any inserted MBB's and clear
1659 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1660 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1662 SwitchCases.clear();
1666 // Create a CaseBlock record representing this branch.
1667 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1668 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1670 // Use visitSwitchCase to actually insert the fast branch sequence for this
1672 visitSwitchCase(CB, BrMBB);
1675 /// visitSwitchCase - Emits the necessary code to represent a single node in
1676 /// the binary search tree resulting from lowering a switch instruction.
1677 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1678 MachineBasicBlock *SwitchBB) {
1680 SDValue CondLHS = getValue(CB.CmpLHS);
1681 SDLoc dl = getCurSDLoc();
1683 // Build the setcc now.
1685 // Fold "(X == true)" to X and "(X == false)" to !X to
1686 // handle common cases produced by branch lowering.
1687 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1688 CB.CC == ISD::SETEQ)
1690 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1691 CB.CC == ISD::SETEQ) {
1692 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1693 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1695 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1697 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1699 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1700 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1702 SDValue CmpOp = getValue(CB.CmpMHS);
1703 EVT VT = CmpOp.getValueType();
1705 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1706 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1709 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1710 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1711 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1712 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1716 // Update successor info
1717 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1718 // TrueBB and FalseBB are always different unless the incoming IR is
1719 // degenerate. This only happens when running llc on weird IR.
1720 if (CB.TrueBB != CB.FalseBB)
1721 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1723 // If the lhs block is the next block, invert the condition so that we can
1724 // fall through to the lhs instead of the rhs block.
1725 if (CB.TrueBB == NextBlock(SwitchBB)) {
1726 std::swap(CB.TrueBB, CB.FalseBB);
1727 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1728 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1731 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1732 MVT::Other, getControlRoot(), Cond,
1733 DAG.getBasicBlock(CB.TrueBB));
1735 // Insert the false branch. Do this even if it's a fall through branch,
1736 // this makes it easier to do DAG optimizations which require inverting
1737 // the branch condition.
1738 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1739 DAG.getBasicBlock(CB.FalseBB));
1741 DAG.setRoot(BrCond);
1744 /// visitJumpTable - Emit JumpTable node in the current MBB
1745 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1746 // Emit the code for the jump table
1747 assert(JT.Reg != -1U && "Should lower JT Header first!");
1748 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1749 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1751 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1752 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1753 MVT::Other, Index.getValue(1),
1755 DAG.setRoot(BrJumpTable);
1758 /// visitJumpTableHeader - This function emits necessary code to produce index
1759 /// in the JumpTable from switch case.
1760 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1761 JumpTableHeader &JTH,
1762 MachineBasicBlock *SwitchBB) {
1763 SDLoc dl = getCurSDLoc();
1765 // Subtract the lowest switch case value from the value being switched on and
1766 // conditional branch to default mbb if the result is greater than the
1767 // difference between smallest and largest cases.
1768 SDValue SwitchOp = getValue(JTH.SValue);
1769 EVT VT = SwitchOp.getValueType();
1770 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1771 DAG.getConstant(JTH.First, dl, VT));
1773 // The SDNode we just created, which holds the value being switched on minus
1774 // the smallest case value, needs to be copied to a virtual register so it
1775 // can be used as an index into the jump table in a subsequent basic block.
1776 // This value may be smaller or larger than the target's pointer type, and
1777 // therefore require extension or truncating.
1778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1779 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1781 unsigned JumpTableReg =
1782 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1783 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1784 JumpTableReg, SwitchOp);
1785 JT.Reg = JumpTableReg;
1787 // Emit the range check for the jump table, and branch to the default block
1788 // for the switch statement if the value being switched on exceeds the largest
1789 // case in the switch.
1790 SDValue CMP = DAG.getSetCC(
1791 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1792 Sub.getValueType()),
1793 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1795 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1796 MVT::Other, CopyTo, CMP,
1797 DAG.getBasicBlock(JT.Default));
1799 // Avoid emitting unnecessary branches to the next block.
1800 if (JT.MBB != NextBlock(SwitchBB))
1801 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1802 DAG.getBasicBlock(JT.MBB));
1804 DAG.setRoot(BrCond);
1807 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1808 /// tail spliced into a stack protector check success bb.
1810 /// For a high level explanation of how this fits into the stack protector
1811 /// generation see the comment on the declaration of class
1812 /// StackProtectorDescriptor.
1813 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1814 MachineBasicBlock *ParentBB) {
1816 // First create the loads to the guard/stack slot for the comparison.
1817 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1818 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1820 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1821 int FI = MFI->getStackProtectorIndex();
1823 const Value *IRGuard = SPD.getGuard();
1824 SDValue GuardPtr = getValue(IRGuard);
1825 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1827 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1830 SDLoc dl = getCurSDLoc();
1832 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1833 // guard value from the virtual register holding the value. Otherwise, emit a
1834 // volatile load to retrieve the stack guard value.
1835 unsigned GuardReg = SPD.getGuardReg();
1837 if (GuardReg && TLI.useLoadStackGuardNode())
1838 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1841 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1842 GuardPtr, MachinePointerInfo(IRGuard, 0),
1843 true, false, false, Align);
1845 SDValue StackSlot = DAG.getLoad(
1846 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1847 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1848 false, false, Align);
1850 // Perform the comparison via a subtract/getsetcc.
1851 EVT VT = Guard.getValueType();
1852 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1854 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1856 Sub.getValueType()),
1857 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1859 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1860 // branch to failure MBB.
1861 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1862 MVT::Other, StackSlot.getOperand(0),
1863 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1864 // Otherwise branch to success MBB.
1865 SDValue Br = DAG.getNode(ISD::BR, dl,
1867 DAG.getBasicBlock(SPD.getSuccessMBB()));
1872 /// Codegen the failure basic block for a stack protector check.
1874 /// A failure stack protector machine basic block consists simply of a call to
1875 /// __stack_chk_fail().
1877 /// For a high level explanation of how this fits into the stack protector
1878 /// generation see the comment on the declaration of class
1879 /// StackProtectorDescriptor.
1881 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1882 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1884 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1885 nullptr, 0, false, getCurSDLoc(), false, false).second;
1889 /// visitBitTestHeader - This function emits necessary code to produce value
1890 /// suitable for "bit tests"
1891 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1892 MachineBasicBlock *SwitchBB) {
1893 SDLoc dl = getCurSDLoc();
1895 // Subtract the minimum value
1896 SDValue SwitchOp = getValue(B.SValue);
1897 EVT VT = SwitchOp.getValueType();
1898 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1899 DAG.getConstant(B.First, dl, VT));
1902 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1903 SDValue RangeCmp = DAG.getSetCC(
1904 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1905 Sub.getValueType()),
1906 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1908 // Determine the type of the test operands.
1909 bool UsePtrType = false;
1910 if (!TLI.isTypeLegal(VT))
1913 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1914 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1915 // Switch table case range are encoded into series of masks.
1916 // Just use pointer type, it's guaranteed to fit.
1922 VT = TLI.getPointerTy(DAG.getDataLayout());
1923 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1926 B.RegVT = VT.getSimpleVT();
1927 B.Reg = FuncInfo.CreateReg(B.RegVT);
1928 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1930 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1932 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1933 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1935 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1936 MVT::Other, CopyTo, RangeCmp,
1937 DAG.getBasicBlock(B.Default));
1939 // Avoid emitting unnecessary branches to the next block.
1940 if (MBB != NextBlock(SwitchBB))
1941 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1942 DAG.getBasicBlock(MBB));
1944 DAG.setRoot(BrRange);
1947 /// visitBitTestCase - this function produces one "bit test"
1948 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1949 MachineBasicBlock* NextMBB,
1950 uint32_t BranchWeightToNext,
1953 MachineBasicBlock *SwitchBB) {
1954 SDLoc dl = getCurSDLoc();
1956 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1958 unsigned PopCount = countPopulation(B.Mask);
1959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1960 if (PopCount == 1) {
1961 // Testing for a single bit; just compare the shift count with what it
1962 // would need to be to shift a 1 bit in that position.
1964 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1965 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1967 } else if (PopCount == BB.Range) {
1968 // There is only one zero bit in the range, test for it directly.
1970 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1971 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1974 // Make desired shift
1975 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1976 DAG.getConstant(1, dl, VT), ShiftOp);
1978 // Emit bit tests and jumps
1979 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1980 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1982 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1983 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1986 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1987 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1988 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1989 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1991 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1992 MVT::Other, getControlRoot(),
1993 Cmp, DAG.getBasicBlock(B.TargetBB));
1995 // Avoid emitting unnecessary branches to the next block.
1996 if (NextMBB != NextBlock(SwitchBB))
1997 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1998 DAG.getBasicBlock(NextMBB));
2003 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2004 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2006 // Retrieve successors.
2007 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2008 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2010 const Value *Callee(I.getCalledValue());
2011 const Function *Fn = dyn_cast<Function>(Callee);
2012 if (isa<InlineAsm>(Callee))
2014 else if (Fn && Fn->isIntrinsic()) {
2015 switch (Fn->getIntrinsicID()) {
2017 llvm_unreachable("Cannot invoke this intrinsic");
2018 case Intrinsic::donothing:
2019 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2021 case Intrinsic::experimental_patchpoint_void:
2022 case Intrinsic::experimental_patchpoint_i64:
2023 visitPatchpoint(&I, LandingPad);
2025 case Intrinsic::experimental_gc_statepoint:
2026 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2030 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2032 // If the value of the invoke is used outside of its defining block, make it
2033 // available as a virtual register.
2034 // We already took care of the exported value for the statepoint instruction
2035 // during call to the LowerStatepoint.
2036 if (!isStatepoint(I)) {
2037 CopyToExportRegsIfNeeded(&I);
2040 // Update successor info
2041 addSuccessorWithWeight(InvokeMBB, Return);
2042 addSuccessorWithWeight(InvokeMBB, LandingPad);
2044 // Drop into normal successor.
2045 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2046 MVT::Other, getControlRoot(),
2047 DAG.getBasicBlock(Return)));
2050 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2051 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2054 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2055 assert(FuncInfo.MBB->isEHPad() &&
2056 "Call to landingpad not in landing pad!");
2058 MachineBasicBlock *MBB = FuncInfo.MBB;
2059 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2060 AddLandingPadInfo(LP, MMI, MBB);
2062 // If there aren't registers to copy the values into (e.g., during SjLj
2063 // exceptions), then don't bother to create these DAG nodes.
2064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2065 if (TLI.getExceptionPointerRegister() == 0 &&
2066 TLI.getExceptionSelectorRegister() == 0)
2069 SmallVector<EVT, 2> ValueVTs;
2070 SDLoc dl = getCurSDLoc();
2071 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2072 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2074 // Get the two live-in registers as SDValues. The physregs have already been
2075 // copied into virtual registers.
2077 if (FuncInfo.ExceptionPointerVirtReg) {
2078 Ops[0] = DAG.getZExtOrTrunc(
2079 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2080 FuncInfo.ExceptionPointerVirtReg,
2081 TLI.getPointerTy(DAG.getDataLayout())),
2084 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2086 Ops[1] = DAG.getZExtOrTrunc(
2087 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2088 FuncInfo.ExceptionSelectorVirtReg,
2089 TLI.getPointerTy(DAG.getDataLayout())),
2093 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2094 DAG.getVTList(ValueVTs), Ops);
2098 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2100 for (const CaseCluster &CC : Clusters)
2101 assert(CC.Low == CC.High && "Input clusters must be single-case");
2104 std::sort(Clusters.begin(), Clusters.end(),
2105 [](const CaseCluster &a, const CaseCluster &b) {
2106 return a.Low->getValue().slt(b.Low->getValue());
2109 // Merge adjacent clusters with the same destination.
2110 const unsigned N = Clusters.size();
2111 unsigned DstIndex = 0;
2112 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2113 CaseCluster &CC = Clusters[SrcIndex];
2114 const ConstantInt *CaseVal = CC.Low;
2115 MachineBasicBlock *Succ = CC.MBB;
2117 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2118 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2119 // If this case has the same successor and is a neighbour, merge it into
2120 // the previous cluster.
2121 Clusters[DstIndex - 1].High = CaseVal;
2122 Clusters[DstIndex - 1].Weight += CC.Weight;
2123 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2125 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2126 sizeof(Clusters[SrcIndex]));
2129 Clusters.resize(DstIndex);
2132 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2133 MachineBasicBlock *Last) {
2135 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2136 if (JTCases[i].first.HeaderBB == First)
2137 JTCases[i].first.HeaderBB = Last;
2139 // Update BitTestCases.
2140 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2141 if (BitTestCases[i].Parent == First)
2142 BitTestCases[i].Parent = Last;
2145 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2146 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2148 // Update machine-CFG edges with unique successors.
2149 SmallSet<BasicBlock*, 32> Done;
2150 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2151 BasicBlock *BB = I.getSuccessor(i);
2152 bool Inserted = Done.insert(BB).second;
2156 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2157 addSuccessorWithWeight(IndirectBrMBB, Succ);
2160 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2161 MVT::Other, getControlRoot(),
2162 getValue(I.getAddress())));
2165 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2166 if (DAG.getTarget().Options.TrapUnreachable)
2167 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2170 void SelectionDAGBuilder::visitFSub(const User &I) {
2171 // -0.0 - X --> fneg
2172 Type *Ty = I.getType();
2173 if (isa<Constant>(I.getOperand(0)) &&
2174 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2175 SDValue Op2 = getValue(I.getOperand(1));
2176 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2177 Op2.getValueType(), Op2));
2181 visitBinary(I, ISD::FSUB);
2184 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2185 SDValue Op1 = getValue(I.getOperand(0));
2186 SDValue Op2 = getValue(I.getOperand(1));
2193 if (const OverflowingBinaryOperator *OFBinOp =
2194 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2195 nuw = OFBinOp->hasNoUnsignedWrap();
2196 nsw = OFBinOp->hasNoSignedWrap();
2198 if (const PossiblyExactOperator *ExactOp =
2199 dyn_cast<const PossiblyExactOperator>(&I))
2200 exact = ExactOp->isExact();
2201 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2202 FMF = FPOp->getFastMathFlags();
2205 Flags.setExact(exact);
2206 Flags.setNoSignedWrap(nsw);
2207 Flags.setNoUnsignedWrap(nuw);
2208 if (EnableFMFInDAG) {
2209 Flags.setAllowReciprocal(FMF.allowReciprocal());
2210 Flags.setNoInfs(FMF.noInfs());
2211 Flags.setNoNaNs(FMF.noNaNs());
2212 Flags.setNoSignedZeros(FMF.noSignedZeros());
2213 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2215 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2217 setValue(&I, BinNodeValue);
2220 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2221 SDValue Op1 = getValue(I.getOperand(0));
2222 SDValue Op2 = getValue(I.getOperand(1));
2224 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2225 Op2.getValueType(), DAG.getDataLayout());
2227 // Coerce the shift amount to the right type if we can.
2228 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2229 unsigned ShiftSize = ShiftTy.getSizeInBits();
2230 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2231 SDLoc DL = getCurSDLoc();
2233 // If the operand is smaller than the shift count type, promote it.
2234 if (ShiftSize > Op2Size)
2235 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2237 // If the operand is larger than the shift count type but the shift
2238 // count type has enough bits to represent any shift value, truncate
2239 // it now. This is a common case and it exposes the truncate to
2240 // optimization early.
2241 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2242 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2243 // Otherwise we'll need to temporarily settle for some other convenient
2244 // type. Type legalization will make adjustments once the shiftee is split.
2246 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2253 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2255 if (const OverflowingBinaryOperator *OFBinOp =
2256 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2257 nuw = OFBinOp->hasNoUnsignedWrap();
2258 nsw = OFBinOp->hasNoSignedWrap();
2260 if (const PossiblyExactOperator *ExactOp =
2261 dyn_cast<const PossiblyExactOperator>(&I))
2262 exact = ExactOp->isExact();
2265 Flags.setExact(exact);
2266 Flags.setNoSignedWrap(nsw);
2267 Flags.setNoUnsignedWrap(nuw);
2268 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2273 void SelectionDAGBuilder::visitSDiv(const User &I) {
2274 SDValue Op1 = getValue(I.getOperand(0));
2275 SDValue Op2 = getValue(I.getOperand(1));
2278 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2279 cast<PossiblyExactOperator>(&I)->isExact());
2280 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2284 void SelectionDAGBuilder::visitICmp(const User &I) {
2285 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2286 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2287 predicate = IC->getPredicate();
2288 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2289 predicate = ICmpInst::Predicate(IC->getPredicate());
2290 SDValue Op1 = getValue(I.getOperand(0));
2291 SDValue Op2 = getValue(I.getOperand(1));
2292 ISD::CondCode Opcode = getICmpCondCode(predicate);
2294 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2296 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2299 void SelectionDAGBuilder::visitFCmp(const User &I) {
2300 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2301 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2302 predicate = FC->getPredicate();
2303 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2304 predicate = FCmpInst::Predicate(FC->getPredicate());
2305 SDValue Op1 = getValue(I.getOperand(0));
2306 SDValue Op2 = getValue(I.getOperand(1));
2307 ISD::CondCode Condition = getFCmpCondCode(predicate);
2308 if (TM.Options.NoNaNsFPMath)
2309 Condition = getFCmpCodeWithoutNaN(Condition);
2310 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2312 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2315 void SelectionDAGBuilder::visitSelect(const User &I) {
2316 SmallVector<EVT, 4> ValueVTs;
2317 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2319 unsigned NumValues = ValueVTs.size();
2320 if (NumValues == 0) return;
2322 SmallVector<SDValue, 4> Values(NumValues);
2323 SDValue Cond = getValue(I.getOperand(0));
2324 SDValue LHSVal = getValue(I.getOperand(1));
2325 SDValue RHSVal = getValue(I.getOperand(2));
2326 auto BaseOps = {Cond};
2327 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2328 ISD::VSELECT : ISD::SELECT;
2330 // Min/max matching is only viable if all output VTs are the same.
2331 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2332 EVT VT = ValueVTs[0];
2333 LLVMContext &Ctx = *DAG.getContext();
2334 auto &TLI = DAG.getTargetLoweringInfo();
2335 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2336 VT = TLI.getTypeToTransformTo(Ctx, VT);
2339 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2340 ISD::NodeType Opc = ISD::DELETED_NODE;
2341 switch (SPR.Flavor) {
2342 case SPF_UMAX: Opc = ISD::UMAX; break;
2343 case SPF_UMIN: Opc = ISD::UMIN; break;
2344 case SPF_SMAX: Opc = ISD::SMAX; break;
2345 case SPF_SMIN: Opc = ISD::SMIN; break;
2347 switch (SPR.NaNBehavior) {
2348 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2349 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2350 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2351 case SPNB_RETURNS_ANY:
2352 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2358 switch (SPR.NaNBehavior) {
2359 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2360 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2361 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2362 case SPNB_RETURNS_ANY:
2363 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2371 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2372 // If the underlying comparison instruction is used by any other instruction,
2373 // the consumed instructions won't be destroyed, so it is not profitable
2374 // to convert to a min/max.
2375 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2377 LHSVal = getValue(LHS);
2378 RHSVal = getValue(RHS);
2383 for (unsigned i = 0; i != NumValues; ++i) {
2384 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2385 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2386 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2387 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2388 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2392 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2393 DAG.getVTList(ValueVTs), Values));
2396 void SelectionDAGBuilder::visitTrunc(const User &I) {
2397 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2398 SDValue N = getValue(I.getOperand(0));
2399 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2401 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2404 void SelectionDAGBuilder::visitZExt(const User &I) {
2405 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2406 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2407 SDValue N = getValue(I.getOperand(0));
2408 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2410 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2413 void SelectionDAGBuilder::visitSExt(const User &I) {
2414 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2415 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2416 SDValue N = getValue(I.getOperand(0));
2417 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2419 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2422 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2423 // FPTrunc is never a no-op cast, no need to check
2424 SDValue N = getValue(I.getOperand(0));
2425 SDLoc dl = getCurSDLoc();
2426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2427 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2428 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2429 DAG.getTargetConstant(
2430 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2433 void SelectionDAGBuilder::visitFPExt(const User &I) {
2434 // FPExt is never a no-op cast, no need to check
2435 SDValue N = getValue(I.getOperand(0));
2436 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2438 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2441 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2442 // FPToUI is never a no-op cast, no need to check
2443 SDValue N = getValue(I.getOperand(0));
2444 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2446 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2449 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2450 // FPToSI is never a no-op cast, no need to check
2451 SDValue N = getValue(I.getOperand(0));
2452 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2454 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2457 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2458 // UIToFP is never a no-op cast, no need to check
2459 SDValue N = getValue(I.getOperand(0));
2460 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2462 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2465 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2466 // SIToFP is never a no-op cast, no need to check
2467 SDValue N = getValue(I.getOperand(0));
2468 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2470 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2473 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2474 // What to do depends on the size of the integer and the size of the pointer.
2475 // We can either truncate, zero extend, or no-op, accordingly.
2476 SDValue N = getValue(I.getOperand(0));
2477 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2479 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2482 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2483 // What to do depends on the size of the integer and the size of the pointer.
2484 // We can either truncate, zero extend, or no-op, accordingly.
2485 SDValue N = getValue(I.getOperand(0));
2486 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2488 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2491 void SelectionDAGBuilder::visitBitCast(const User &I) {
2492 SDValue N = getValue(I.getOperand(0));
2493 SDLoc dl = getCurSDLoc();
2494 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2497 // BitCast assures us that source and destination are the same size so this is
2498 // either a BITCAST or a no-op.
2499 if (DestVT != N.getValueType())
2500 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2501 DestVT, N)); // convert types.
2502 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2503 // might fold any kind of constant expression to an integer constant and that
2504 // is not what we are looking for. Only regcognize a bitcast of a genuine
2505 // constant integer as an opaque constant.
2506 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2507 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2510 setValue(&I, N); // noop cast.
2513 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2515 const Value *SV = I.getOperand(0);
2516 SDValue N = getValue(SV);
2517 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2519 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2520 unsigned DestAS = I.getType()->getPointerAddressSpace();
2522 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2523 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2528 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2530 SDValue InVec = getValue(I.getOperand(0));
2531 SDValue InVal = getValue(I.getOperand(1));
2532 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2533 TLI.getVectorIdxTy(DAG.getDataLayout()));
2534 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2535 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2536 InVec, InVal, InIdx));
2539 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2540 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2541 SDValue InVec = getValue(I.getOperand(0));
2542 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2543 TLI.getVectorIdxTy(DAG.getDataLayout()));
2544 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2545 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2549 // Utility for visitShuffleVector - Return true if every element in Mask,
2550 // beginning from position Pos and ending in Pos+Size, falls within the
2551 // specified sequential range [L, L+Pos). or is undef.
2552 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2553 unsigned Pos, unsigned Size, int Low) {
2554 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2555 if (Mask[i] >= 0 && Mask[i] != Low)
2560 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2561 SDValue Src1 = getValue(I.getOperand(0));
2562 SDValue Src2 = getValue(I.getOperand(1));
2564 SmallVector<int, 8> Mask;
2565 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2566 unsigned MaskNumElts = Mask.size();
2568 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2569 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2570 EVT SrcVT = Src1.getValueType();
2571 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2573 if (SrcNumElts == MaskNumElts) {
2574 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2579 // Normalize the shuffle vector since mask and vector length don't match.
2580 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2581 // Mask is longer than the source vectors and is a multiple of the source
2582 // vectors. We can use concatenate vector to make the mask and vectors
2584 if (SrcNumElts*2 == MaskNumElts) {
2585 // First check for Src1 in low and Src2 in high
2586 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2587 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2588 // The shuffle is concatenating two vectors together.
2589 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2593 // Then check for Src2 in low and Src1 in high
2594 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2595 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2596 // The shuffle is concatenating two vectors together.
2597 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2603 // Pad both vectors with undefs to make them the same length as the mask.
2604 unsigned NumConcat = MaskNumElts / SrcNumElts;
2605 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2606 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2607 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2609 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2610 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2614 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2615 getCurSDLoc(), VT, MOps1);
2616 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2617 getCurSDLoc(), VT, MOps2);
2619 // Readjust mask for new input vector length.
2620 SmallVector<int, 8> MappedOps;
2621 for (unsigned i = 0; i != MaskNumElts; ++i) {
2623 if (Idx >= (int)SrcNumElts)
2624 Idx -= SrcNumElts - MaskNumElts;
2625 MappedOps.push_back(Idx);
2628 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2633 if (SrcNumElts > MaskNumElts) {
2634 // Analyze the access pattern of the vector to see if we can extract
2635 // two subvectors and do the shuffle. The analysis is done by calculating
2636 // the range of elements the mask access on both vectors.
2637 int MinRange[2] = { static_cast<int>(SrcNumElts),
2638 static_cast<int>(SrcNumElts)};
2639 int MaxRange[2] = {-1, -1};
2641 for (unsigned i = 0; i != MaskNumElts; ++i) {
2647 if (Idx >= (int)SrcNumElts) {
2651 if (Idx > MaxRange[Input])
2652 MaxRange[Input] = Idx;
2653 if (Idx < MinRange[Input])
2654 MinRange[Input] = Idx;
2657 // Check if the access is smaller than the vector size and can we find
2658 // a reasonable extract index.
2659 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2661 int StartIdx[2]; // StartIdx to extract from
2662 for (unsigned Input = 0; Input < 2; ++Input) {
2663 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2664 RangeUse[Input] = 0; // Unused
2665 StartIdx[Input] = 0;
2669 // Find a good start index that is a multiple of the mask length. Then
2670 // see if the rest of the elements are in range.
2671 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2672 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2673 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2674 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2677 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2678 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2681 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2682 // Extract appropriate subvector and generate a vector shuffle
2683 for (unsigned Input = 0; Input < 2; ++Input) {
2684 SDValue &Src = Input == 0 ? Src1 : Src2;
2685 if (RangeUse[Input] == 0)
2686 Src = DAG.getUNDEF(VT);
2688 SDLoc dl = getCurSDLoc();
2690 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2691 DAG.getConstant(StartIdx[Input], dl,
2692 TLI.getVectorIdxTy(DAG.getDataLayout())));
2696 // Calculate new mask.
2697 SmallVector<int, 8> MappedOps;
2698 for (unsigned i = 0; i != MaskNumElts; ++i) {
2701 if (Idx < (int)SrcNumElts)
2704 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2706 MappedOps.push_back(Idx);
2709 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2715 // We can't use either concat vectors or extract subvectors so fall back to
2716 // replacing the shuffle with extract and build vector.
2717 // to insert and build vector.
2718 EVT EltVT = VT.getVectorElementType();
2719 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2720 SDLoc dl = getCurSDLoc();
2721 SmallVector<SDValue,8> Ops;
2722 for (unsigned i = 0; i != MaskNumElts; ++i) {
2727 Res = DAG.getUNDEF(EltVT);
2729 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2730 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2732 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2733 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2739 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2742 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2743 const Value *Op0 = I.getOperand(0);
2744 const Value *Op1 = I.getOperand(1);
2745 Type *AggTy = I.getType();
2746 Type *ValTy = Op1->getType();
2747 bool IntoUndef = isa<UndefValue>(Op0);
2748 bool FromUndef = isa<UndefValue>(Op1);
2750 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2752 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2753 SmallVector<EVT, 4> AggValueVTs;
2754 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2755 SmallVector<EVT, 4> ValValueVTs;
2756 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2758 unsigned NumAggValues = AggValueVTs.size();
2759 unsigned NumValValues = ValValueVTs.size();
2760 SmallVector<SDValue, 4> Values(NumAggValues);
2762 // Ignore an insertvalue that produces an empty object
2763 if (!NumAggValues) {
2764 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2768 SDValue Agg = getValue(Op0);
2770 // Copy the beginning value(s) from the original aggregate.
2771 for (; i != LinearIndex; ++i)
2772 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2773 SDValue(Agg.getNode(), Agg.getResNo() + i);
2774 // Copy values from the inserted value(s).
2776 SDValue Val = getValue(Op1);
2777 for (; i != LinearIndex + NumValValues; ++i)
2778 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2779 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2781 // Copy remaining value(s) from the original aggregate.
2782 for (; i != NumAggValues; ++i)
2783 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2784 SDValue(Agg.getNode(), Agg.getResNo() + i);
2786 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2787 DAG.getVTList(AggValueVTs), Values));
2790 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2791 const Value *Op0 = I.getOperand(0);
2792 Type *AggTy = Op0->getType();
2793 Type *ValTy = I.getType();
2794 bool OutOfUndef = isa<UndefValue>(Op0);
2796 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2799 SmallVector<EVT, 4> ValValueVTs;
2800 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2802 unsigned NumValValues = ValValueVTs.size();
2804 // Ignore a extractvalue that produces an empty object
2805 if (!NumValValues) {
2806 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2810 SmallVector<SDValue, 4> Values(NumValValues);
2812 SDValue Agg = getValue(Op0);
2813 // Copy out the selected value(s).
2814 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2815 Values[i - LinearIndex] =
2817 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2818 SDValue(Agg.getNode(), Agg.getResNo() + i);
2820 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2821 DAG.getVTList(ValValueVTs), Values));
2824 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2825 Value *Op0 = I.getOperand(0);
2826 // Note that the pointer operand may be a vector of pointers. Take the scalar
2827 // element which holds a pointer.
2828 Type *Ty = Op0->getType()->getScalarType();
2829 unsigned AS = Ty->getPointerAddressSpace();
2830 SDValue N = getValue(Op0);
2831 SDLoc dl = getCurSDLoc();
2833 // Normalize Vector GEP - all scalar operands should be converted to the
2835 unsigned VectorWidth = I.getType()->isVectorTy() ?
2836 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2838 if (VectorWidth && !N.getValueType().isVector()) {
2839 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2840 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2841 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2843 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2845 const Value *Idx = *OI;
2846 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2847 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2850 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2851 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2852 DAG.getConstant(Offset, dl, N.getValueType()));
2855 Ty = StTy->getElementType(Field);
2857 Ty = cast<SequentialType>(Ty)->getElementType();
2859 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2860 unsigned PtrSize = PtrTy.getSizeInBits();
2861 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2863 // If this is a scalar constant or a splat vector of constants,
2864 // handle it quickly.
2865 const auto *CI = dyn_cast<ConstantInt>(Idx);
2866 if (!CI && isa<ConstantDataVector>(Idx) &&
2867 cast<ConstantDataVector>(Idx)->getSplatValue())
2868 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2873 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2874 SDValue OffsVal = VectorWidth ?
2875 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2876 DAG.getConstant(Offs, dl, PtrTy);
2877 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2881 // N = N + Idx * ElementSize;
2882 SDValue IdxN = getValue(Idx);
2884 if (!IdxN.getValueType().isVector() && VectorWidth) {
2885 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2886 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2887 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2889 // If the index is smaller or larger than intptr_t, truncate or extend
2891 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2893 // If this is a multiply by a power of two, turn it into a shl
2894 // immediately. This is a very common case.
2895 if (ElementSize != 1) {
2896 if (ElementSize.isPowerOf2()) {
2897 unsigned Amt = ElementSize.logBase2();
2898 IdxN = DAG.getNode(ISD::SHL, dl,
2899 N.getValueType(), IdxN,
2900 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2902 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2903 IdxN = DAG.getNode(ISD::MUL, dl,
2904 N.getValueType(), IdxN, Scale);
2908 N = DAG.getNode(ISD::ADD, dl,
2909 N.getValueType(), N, IdxN);
2916 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2917 // If this is a fixed sized alloca in the entry block of the function,
2918 // allocate it statically on the stack.
2919 if (FuncInfo.StaticAllocaMap.count(&I))
2920 return; // getValue will auto-populate this.
2922 SDLoc dl = getCurSDLoc();
2923 Type *Ty = I.getAllocatedType();
2924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2925 auto &DL = DAG.getDataLayout();
2926 uint64_t TySize = DL.getTypeAllocSize(Ty);
2928 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2930 SDValue AllocSize = getValue(I.getArraySize());
2932 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2933 if (AllocSize.getValueType() != IntPtr)
2934 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2936 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2938 DAG.getConstant(TySize, dl, IntPtr));
2940 // Handle alignment. If the requested alignment is less than or equal to
2941 // the stack alignment, ignore it. If the size is greater than or equal to
2942 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2943 unsigned StackAlign =
2944 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2945 if (Align <= StackAlign)
2948 // Round the size of the allocation up to the stack alignment size
2949 // by add SA-1 to the size.
2950 AllocSize = DAG.getNode(ISD::ADD, dl,
2951 AllocSize.getValueType(), AllocSize,
2952 DAG.getIntPtrConstant(StackAlign - 1, dl));
2954 // Mask out the low bits for alignment purposes.
2955 AllocSize = DAG.getNode(ISD::AND, dl,
2956 AllocSize.getValueType(), AllocSize,
2957 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2960 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2961 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2962 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2964 DAG.setRoot(DSA.getValue(1));
2966 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2969 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2971 return visitAtomicLoad(I);
2973 const Value *SV = I.getOperand(0);
2974 SDValue Ptr = getValue(SV);
2976 Type *Ty = I.getType();
2978 bool isVolatile = I.isVolatile();
2979 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2981 // The IR notion of invariant_load only guarantees that all *non-faulting*
2982 // invariant loads result in the same value. The MI notion of invariant load
2983 // guarantees that the load can be legally moved to any location within its
2984 // containing function. The MI notion of invariant_load is stronger than the
2985 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2986 // with a guarantee that the location being loaded from is dereferenceable
2987 // throughout the function's lifetime.
2989 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2990 isDereferenceablePointer(SV, DAG.getDataLayout());
2991 unsigned Alignment = I.getAlignment();
2994 I.getAAMetadata(AAInfo);
2995 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2998 SmallVector<EVT, 4> ValueVTs;
2999 SmallVector<uint64_t, 4> Offsets;
3000 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3001 unsigned NumValues = ValueVTs.size();
3006 bool ConstantMemory = false;
3007 if (isVolatile || NumValues > MaxParallelChains)
3008 // Serialize volatile loads with other side effects.
3010 else if (AA->pointsToConstantMemory(MemoryLocation(
3011 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3012 // Do not serialize (non-volatile) loads of constant memory with anything.
3013 Root = DAG.getEntryNode();
3014 ConstantMemory = true;
3016 // Do not serialize non-volatile loads against each other.
3017 Root = DAG.getRoot();
3020 SDLoc dl = getCurSDLoc();
3023 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3025 SmallVector<SDValue, 4> Values(NumValues);
3026 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3027 EVT PtrVT = Ptr.getValueType();
3028 unsigned ChainI = 0;
3029 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3030 // Serializing loads here may result in excessive register pressure, and
3031 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3032 // could recover a bit by hoisting nodes upward in the chain by recognizing
3033 // they are side-effect free or do not alias. The optimizer should really
3034 // avoid this case by converting large object/array copies to llvm.memcpy
3035 // (MaxParallelChains should always remain as failsafe).
3036 if (ChainI == MaxParallelChains) {
3037 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3038 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3039 makeArrayRef(Chains.data(), ChainI));
3043 SDValue A = DAG.getNode(ISD::ADD, dl,
3045 DAG.getConstant(Offsets[i], dl, PtrVT));
3046 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3047 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3048 isNonTemporal, isInvariant, Alignment, AAInfo,
3052 Chains[ChainI] = L.getValue(1);
3055 if (!ConstantMemory) {
3056 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3057 makeArrayRef(Chains.data(), ChainI));
3061 PendingLoads.push_back(Chain);
3064 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3065 DAG.getVTList(ValueVTs), Values));
3068 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3070 return visitAtomicStore(I);
3072 const Value *SrcV = I.getOperand(0);
3073 const Value *PtrV = I.getOperand(1);
3075 SmallVector<EVT, 4> ValueVTs;
3076 SmallVector<uint64_t, 4> Offsets;
3077 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3078 SrcV->getType(), ValueVTs, &Offsets);
3079 unsigned NumValues = ValueVTs.size();
3083 // Get the lowered operands. Note that we do this after
3084 // checking if NumResults is zero, because with zero results
3085 // the operands won't have values in the map.
3086 SDValue Src = getValue(SrcV);
3087 SDValue Ptr = getValue(PtrV);
3089 SDValue Root = getRoot();
3090 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3091 EVT PtrVT = Ptr.getValueType();
3092 bool isVolatile = I.isVolatile();
3093 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3094 unsigned Alignment = I.getAlignment();
3095 SDLoc dl = getCurSDLoc();
3098 I.getAAMetadata(AAInfo);
3100 unsigned ChainI = 0;
3101 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3102 // See visitLoad comments.
3103 if (ChainI == MaxParallelChains) {
3104 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3105 makeArrayRef(Chains.data(), ChainI));
3109 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3110 DAG.getConstant(Offsets[i], dl, PtrVT));
3111 SDValue St = DAG.getStore(Root, dl,
3112 SDValue(Src.getNode(), Src.getResNo() + i),
3113 Add, MachinePointerInfo(PtrV, Offsets[i]),
3114 isVolatile, isNonTemporal, Alignment, AAInfo);
3115 Chains[ChainI] = St;
3118 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3119 makeArrayRef(Chains.data(), ChainI));
3120 DAG.setRoot(StoreNode);
3123 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3124 SDLoc sdl = getCurSDLoc();
3126 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3127 Value *PtrOperand = I.getArgOperand(1);
3128 SDValue Ptr = getValue(PtrOperand);
3129 SDValue Src0 = getValue(I.getArgOperand(0));
3130 SDValue Mask = getValue(I.getArgOperand(3));
3131 EVT VT = Src0.getValueType();
3132 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3134 Alignment = DAG.getEVTAlignment(VT);
3137 I.getAAMetadata(AAInfo);
3139 MachineMemOperand *MMO =
3140 DAG.getMachineFunction().
3141 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3142 MachineMemOperand::MOStore, VT.getStoreSize(),
3144 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3146 DAG.setRoot(StoreNode);
3147 setValue(&I, StoreNode);
3150 // Get a uniform base for the Gather/Scatter intrinsic.
3151 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3152 // We try to represent it as a base pointer + vector of indices.
3153 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3154 // The first operand of the GEP may be a single pointer or a vector of pointers
3156 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3158 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3159 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3161 // When the first GEP operand is a single pointer - it is the uniform base we
3162 // are looking for. If first operand of the GEP is a splat vector - we
3163 // extract the spalt value and use it as a uniform base.
3164 // In all other cases the function returns 'false'.
3166 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3167 SelectionDAGBuilder* SDB) {
3169 SelectionDAG& DAG = SDB->DAG;
3170 LLVMContext &Context = *DAG.getContext();
3172 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3173 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3174 if (!GEP || GEP->getNumOperands() > 2)
3177 Value *GEPPtr = GEP->getPointerOperand();
3178 if (!GEPPtr->getType()->isVectorTy())
3180 else if (!(Ptr = getSplatValue(GEPPtr)))
3183 Value *IndexVal = GEP->getOperand(1);
3185 // The operands of the GEP may be defined in another basic block.
3186 // In this case we'll not find nodes for the operands.
3187 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3190 Base = SDB->getValue(Ptr);
3191 Index = SDB->getValue(IndexVal);
3193 // Suppress sign extension.
3194 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3195 if (SDB->findValue(Sext->getOperand(0))) {
3196 IndexVal = Sext->getOperand(0);
3197 Index = SDB->getValue(IndexVal);
3200 if (!Index.getValueType().isVector()) {
3201 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3202 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3203 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3204 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3209 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3210 SDLoc sdl = getCurSDLoc();
3212 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3213 Value *Ptr = I.getArgOperand(1);
3214 SDValue Src0 = getValue(I.getArgOperand(0));
3215 SDValue Mask = getValue(I.getArgOperand(3));
3216 EVT VT = Src0.getValueType();
3217 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3219 Alignment = DAG.getEVTAlignment(VT);
3220 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3223 I.getAAMetadata(AAInfo);
3227 Value *BasePtr = Ptr;
3228 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3230 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3231 MachineMemOperand *MMO = DAG.getMachineFunction().
3232 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3233 MachineMemOperand::MOStore, VT.getStoreSize(),
3236 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3237 Index = getValue(Ptr);
3239 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3240 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3242 DAG.setRoot(Scatter);
3243 setValue(&I, Scatter);
3246 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3247 SDLoc sdl = getCurSDLoc();
3249 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3250 Value *PtrOperand = I.getArgOperand(0);
3251 SDValue Ptr = getValue(PtrOperand);
3252 SDValue Src0 = getValue(I.getArgOperand(3));
3253 SDValue Mask = getValue(I.getArgOperand(2));
3255 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3256 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3257 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3259 Alignment = DAG.getEVTAlignment(VT);
3262 I.getAAMetadata(AAInfo);
3263 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3265 SDValue InChain = DAG.getRoot();
3266 if (AA->pointsToConstantMemory(MemoryLocation(
3267 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3269 // Do not serialize (non-volatile) loads of constant memory with anything.
3270 InChain = DAG.getEntryNode();
3273 MachineMemOperand *MMO =
3274 DAG.getMachineFunction().
3275 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3276 MachineMemOperand::MOLoad, VT.getStoreSize(),
3277 Alignment, AAInfo, Ranges);
3279 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3281 SDValue OutChain = Load.getValue(1);
3282 DAG.setRoot(OutChain);
3286 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3287 SDLoc sdl = getCurSDLoc();
3289 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3290 Value *Ptr = I.getArgOperand(0);
3291 SDValue Src0 = getValue(I.getArgOperand(3));
3292 SDValue Mask = getValue(I.getArgOperand(2));
3294 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3295 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3296 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3298 Alignment = DAG.getEVTAlignment(VT);
3301 I.getAAMetadata(AAInfo);
3302 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3304 SDValue Root = DAG.getRoot();
3307 Value *BasePtr = Ptr;
3308 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3309 bool ConstantMemory = false;
3311 AA->pointsToConstantMemory(MemoryLocation(
3312 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3314 // Do not serialize (non-volatile) loads of constant memory with anything.
3315 Root = DAG.getEntryNode();
3316 ConstantMemory = true;
3319 MachineMemOperand *MMO =
3320 DAG.getMachineFunction().
3321 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3322 MachineMemOperand::MOLoad, VT.getStoreSize(),
3323 Alignment, AAInfo, Ranges);
3326 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3327 Index = getValue(Ptr);
3329 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3330 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3333 SDValue OutChain = Gather.getValue(1);
3334 if (!ConstantMemory)
3335 PendingLoads.push_back(OutChain);
3336 setValue(&I, Gather);
3339 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3340 SDLoc dl = getCurSDLoc();
3341 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3342 AtomicOrdering FailureOrder = I.getFailureOrdering();
3343 SynchronizationScope Scope = I.getSynchScope();
3345 SDValue InChain = getRoot();
3347 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3348 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3349 SDValue L = DAG.getAtomicCmpSwap(
3350 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3351 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3352 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3353 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3355 SDValue OutChain = L.getValue(2);
3358 DAG.setRoot(OutChain);
3361 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3362 SDLoc dl = getCurSDLoc();
3364 switch (I.getOperation()) {
3365 default: llvm_unreachable("Unknown atomicrmw operation");
3366 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3367 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3368 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3369 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3370 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3371 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3372 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3373 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3374 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3375 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3376 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3378 AtomicOrdering Order = I.getOrdering();
3379 SynchronizationScope Scope = I.getSynchScope();
3381 SDValue InChain = getRoot();
3384 DAG.getAtomic(NT, dl,
3385 getValue(I.getValOperand()).getSimpleValueType(),
3387 getValue(I.getPointerOperand()),
3388 getValue(I.getValOperand()),
3389 I.getPointerOperand(),
3390 /* Alignment=*/ 0, Order, Scope);
3392 SDValue OutChain = L.getValue(1);
3395 DAG.setRoot(OutChain);
3398 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3399 SDLoc dl = getCurSDLoc();
3400 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3403 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3404 TLI.getPointerTy(DAG.getDataLayout()));
3405 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3406 TLI.getPointerTy(DAG.getDataLayout()));
3407 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3410 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3411 SDLoc dl = getCurSDLoc();
3412 AtomicOrdering Order = I.getOrdering();
3413 SynchronizationScope Scope = I.getSynchScope();
3415 SDValue InChain = getRoot();
3417 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3418 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3420 if (I.getAlignment() < VT.getSizeInBits() / 8)
3421 report_fatal_error("Cannot generate unaligned atomic load");
3423 MachineMemOperand *MMO =
3424 DAG.getMachineFunction().
3425 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3426 MachineMemOperand::MOVolatile |
3427 MachineMemOperand::MOLoad,
3429 I.getAlignment() ? I.getAlignment() :
3430 DAG.getEVTAlignment(VT));
3432 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3434 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3435 getValue(I.getPointerOperand()), MMO,
3438 SDValue OutChain = L.getValue(1);
3441 DAG.setRoot(OutChain);
3444 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3445 SDLoc dl = getCurSDLoc();
3447 AtomicOrdering Order = I.getOrdering();
3448 SynchronizationScope Scope = I.getSynchScope();
3450 SDValue InChain = getRoot();
3452 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3454 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3456 if (I.getAlignment() < VT.getSizeInBits() / 8)
3457 report_fatal_error("Cannot generate unaligned atomic store");
3460 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3462 getValue(I.getPointerOperand()),
3463 getValue(I.getValueOperand()),
3464 I.getPointerOperand(), I.getAlignment(),
3467 DAG.setRoot(OutChain);
3470 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3472 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3473 unsigned Intrinsic) {
3474 bool HasChain = !I.doesNotAccessMemory();
3475 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3477 // Build the operand list.
3478 SmallVector<SDValue, 8> Ops;
3479 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3481 // We don't need to serialize loads against other loads.
3482 Ops.push_back(DAG.getRoot());
3484 Ops.push_back(getRoot());
3488 // Info is set by getTgtMemInstrinsic
3489 TargetLowering::IntrinsicInfo Info;
3490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3491 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3493 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3494 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3495 Info.opc == ISD::INTRINSIC_W_CHAIN)
3496 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3497 TLI.getPointerTy(DAG.getDataLayout())));
3499 // Add all operands of the call to the operand list.
3500 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3501 SDValue Op = getValue(I.getArgOperand(i));
3505 SmallVector<EVT, 4> ValueVTs;
3506 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3509 ValueVTs.push_back(MVT::Other);
3511 SDVTList VTs = DAG.getVTList(ValueVTs);
3515 if (IsTgtIntrinsic) {
3516 // This is target intrinsic that touches memory
3517 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3518 VTs, Ops, Info.memVT,
3519 MachinePointerInfo(Info.ptrVal, Info.offset),
3520 Info.align, Info.vol,
3521 Info.readMem, Info.writeMem, Info.size);
3522 } else if (!HasChain) {
3523 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3524 } else if (!I.getType()->isVoidTy()) {
3525 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3527 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3531 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3533 PendingLoads.push_back(Chain);
3538 if (!I.getType()->isVoidTy()) {
3539 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3540 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3541 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3544 setValue(&I, Result);
3548 /// GetSignificand - Get the significand and build it into a floating-point
3549 /// number with exponent of 1:
3551 /// Op = (Op & 0x007fffff) | 0x3f800000;
3553 /// where Op is the hexadecimal representation of floating point value.
3555 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3556 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3557 DAG.getConstant(0x007fffff, dl, MVT::i32));
3558 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3559 DAG.getConstant(0x3f800000, dl, MVT::i32));
3560 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3563 /// GetExponent - Get the exponent:
3565 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3567 /// where Op is the hexadecimal representation of floating point value.
3569 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3571 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3572 DAG.getConstant(0x7f800000, dl, MVT::i32));
3573 SDValue t1 = DAG.getNode(
3574 ISD::SRL, dl, MVT::i32, t0,
3575 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3576 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3577 DAG.getConstant(127, dl, MVT::i32));
3578 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3581 /// getF32Constant - Get 32-bit floating point constant.
3583 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3584 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3588 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3589 SelectionDAG &DAG) {
3590 // IntegerPartOfX = ((int32_t)(t0);
3591 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3593 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3594 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3595 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3597 // IntegerPartOfX <<= 23;
3598 IntegerPartOfX = DAG.getNode(
3599 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3600 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3601 DAG.getDataLayout())));
3603 SDValue TwoToFractionalPartOfX;
3604 if (LimitFloatPrecision <= 6) {
3605 // For floating-point precision of 6:
3607 // TwoToFractionalPartOfX =
3609 // (0.735607626f + 0.252464424f * x) * x;
3611 // error 0.0144103317, which is 6 bits
3612 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3613 getF32Constant(DAG, 0x3e814304, dl));
3614 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3615 getF32Constant(DAG, 0x3f3c50c8, dl));
3616 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3617 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3618 getF32Constant(DAG, 0x3f7f5e7e, dl));
3619 } else if (LimitFloatPrecision <= 12) {
3620 // For floating-point precision of 12:
3622 // TwoToFractionalPartOfX =
3625 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3627 // error 0.000107046256, which is 13 to 14 bits
3628 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3629 getF32Constant(DAG, 0x3da235e3, dl));
3630 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3631 getF32Constant(DAG, 0x3e65b8f3, dl));
3632 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3633 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3634 getF32Constant(DAG, 0x3f324b07, dl));
3635 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3636 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3637 getF32Constant(DAG, 0x3f7ff8fd, dl));
3638 } else { // LimitFloatPrecision <= 18
3639 // For floating-point precision of 18:
3641 // TwoToFractionalPartOfX =
3645 // (0.554906021e-1f +
3646 // (0.961591928e-2f +
3647 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3648 // error 2.47208000*10^(-7), which is better than 18 bits
3649 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3650 getF32Constant(DAG, 0x3924b03e, dl));
3651 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3652 getF32Constant(DAG, 0x3ab24b87, dl));
3653 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3654 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3655 getF32Constant(DAG, 0x3c1d8c17, dl));
3656 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3657 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3658 getF32Constant(DAG, 0x3d634a1d, dl));
3659 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3660 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3661 getF32Constant(DAG, 0x3e75fe14, dl));
3662 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3663 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3664 getF32Constant(DAG, 0x3f317234, dl));
3665 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3666 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3667 getF32Constant(DAG, 0x3f800000, dl));
3670 // Add the exponent into the result in integer domain.
3671 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3672 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3673 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3676 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3677 /// limited-precision mode.
3678 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3679 const TargetLowering &TLI) {
3680 if (Op.getValueType() == MVT::f32 &&
3681 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3683 // Put the exponent in the right bit position for later addition to the
3686 // #define LOG2OFe 1.4426950f
3687 // t0 = Op * LOG2OFe
3688 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3689 getF32Constant(DAG, 0x3fb8aa3b, dl));
3690 return getLimitedPrecisionExp2(t0, dl, DAG);
3693 // No special expansion.
3694 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3697 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3698 /// limited-precision mode.
3699 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3700 const TargetLowering &TLI) {
3701 if (Op.getValueType() == MVT::f32 &&
3702 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3703 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3705 // Scale the exponent by log(2) [0.69314718f].
3706 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3707 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3708 getF32Constant(DAG, 0x3f317218, dl));
3710 // Get the significand and build it into a floating-point number with
3712 SDValue X = GetSignificand(DAG, Op1, dl);
3714 SDValue LogOfMantissa;
3715 if (LimitFloatPrecision <= 6) {
3716 // For floating-point precision of 6:
3720 // (1.4034025f - 0.23903021f * x) * x;
3722 // error 0.0034276066, which is better than 8 bits
3723 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3724 getF32Constant(DAG, 0xbe74c456, dl));
3725 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3726 getF32Constant(DAG, 0x3fb3a2b1, dl));
3727 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3728 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3729 getF32Constant(DAG, 0x3f949a29, dl));
3730 } else if (LimitFloatPrecision <= 12) {
3731 // For floating-point precision of 12:
3737 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3739 // error 0.000061011436, which is 14 bits
3740 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3741 getF32Constant(DAG, 0xbd67b6d6, dl));
3742 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3743 getF32Constant(DAG, 0x3ee4f4b8, dl));
3744 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3745 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3746 getF32Constant(DAG, 0x3fbc278b, dl));
3747 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3748 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3749 getF32Constant(DAG, 0x40348e95, dl));
3750 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3751 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3752 getF32Constant(DAG, 0x3fdef31a, dl));
3753 } else { // LimitFloatPrecision <= 18
3754 // For floating-point precision of 18:
3762 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3764 // error 0.0000023660568, which is better than 18 bits
3765 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3766 getF32Constant(DAG, 0xbc91e5ac, dl));
3767 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3768 getF32Constant(DAG, 0x3e4350aa, dl));
3769 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3770 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3771 getF32Constant(DAG, 0x3f60d3e3, dl));
3772 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3773 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3774 getF32Constant(DAG, 0x4011cdf0, dl));
3775 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3776 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3777 getF32Constant(DAG, 0x406cfd1c, dl));
3778 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3779 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3780 getF32Constant(DAG, 0x408797cb, dl));
3781 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3782 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3783 getF32Constant(DAG, 0x4006dcab, dl));
3786 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3789 // No special expansion.
3790 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3793 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3794 /// limited-precision mode.
3795 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3796 const TargetLowering &TLI) {
3797 if (Op.getValueType() == MVT::f32 &&
3798 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3799 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3801 // Get the exponent.
3802 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3804 // Get the significand and build it into a floating-point number with
3806 SDValue X = GetSignificand(DAG, Op1, dl);
3808 // Different possible minimax approximations of significand in
3809 // floating-point for various degrees of accuracy over [1,2].
3810 SDValue Log2ofMantissa;
3811 if (LimitFloatPrecision <= 6) {
3812 // For floating-point precision of 6:
3814 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3816 // error 0.0049451742, which is more than 7 bits
3817 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3818 getF32Constant(DAG, 0xbeb08fe0, dl));
3819 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3820 getF32Constant(DAG, 0x40019463, dl));
3821 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3822 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3823 getF32Constant(DAG, 0x3fd6633d, dl));
3824 } else if (LimitFloatPrecision <= 12) {
3825 // For floating-point precision of 12:
3831 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3833 // error 0.0000876136000, which is better than 13 bits
3834 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3835 getF32Constant(DAG, 0xbda7262e, dl));
3836 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3837 getF32Constant(DAG, 0x3f25280b, dl));
3838 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3839 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3840 getF32Constant(DAG, 0x4007b923, dl));
3841 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3842 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3843 getF32Constant(DAG, 0x40823e2f, dl));
3844 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3845 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3846 getF32Constant(DAG, 0x4020d29c, dl));
3847 } else { // LimitFloatPrecision <= 18
3848 // For floating-point precision of 18:
3857 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3859 // error 0.0000018516, which is better than 18 bits
3860 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3861 getF32Constant(DAG, 0xbcd2769e, dl));
3862 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3863 getF32Constant(DAG, 0x3e8ce0b9, dl));
3864 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3865 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3866 getF32Constant(DAG, 0x3fa22ae7, dl));
3867 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3868 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3869 getF32Constant(DAG, 0x40525723, dl));
3870 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3871 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3872 getF32Constant(DAG, 0x40aaf200, dl));
3873 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3874 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3875 getF32Constant(DAG, 0x40c39dad, dl));
3876 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3877 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3878 getF32Constant(DAG, 0x4042902c, dl));
3881 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3884 // No special expansion.
3885 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3888 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3889 /// limited-precision mode.
3890 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3891 const TargetLowering &TLI) {
3892 if (Op.getValueType() == MVT::f32 &&
3893 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3894 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3896 // Scale the exponent by log10(2) [0.30102999f].
3897 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3898 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3899 getF32Constant(DAG, 0x3e9a209a, dl));
3901 // Get the significand and build it into a floating-point number with
3903 SDValue X = GetSignificand(DAG, Op1, dl);
3905 SDValue Log10ofMantissa;
3906 if (LimitFloatPrecision <= 6) {
3907 // For floating-point precision of 6:
3909 // Log10ofMantissa =
3911 // (0.60948995f - 0.10380950f * x) * x;
3913 // error 0.0014886165, which is 6 bits
3914 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3915 getF32Constant(DAG, 0xbdd49a13, dl));
3916 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3917 getF32Constant(DAG, 0x3f1c0789, dl));
3918 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3919 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3920 getF32Constant(DAG, 0x3f011300, dl));
3921 } else if (LimitFloatPrecision <= 12) {
3922 // For floating-point precision of 12:
3924 // Log10ofMantissa =
3927 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3929 // error 0.00019228036, which is better than 12 bits
3930 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3931 getF32Constant(DAG, 0x3d431f31, dl));
3932 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3933 getF32Constant(DAG, 0x3ea21fb2, dl));
3934 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3935 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3936 getF32Constant(DAG, 0x3f6ae232, dl));
3937 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3938 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3939 getF32Constant(DAG, 0x3f25f7c3, dl));
3940 } else { // LimitFloatPrecision <= 18
3941 // For floating-point precision of 18:
3943 // Log10ofMantissa =
3948 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3950 // error 0.0000037995730, which is better than 18 bits
3951 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3952 getF32Constant(DAG, 0x3c5d51ce, dl));
3953 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3954 getF32Constant(DAG, 0x3e00685a, dl));
3955 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3956 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3957 getF32Constant(DAG, 0x3efb6798, dl));
3958 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3959 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3960 getF32Constant(DAG, 0x3f88d192, dl));
3961 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3962 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3963 getF32Constant(DAG, 0x3fc4316c, dl));
3964 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3965 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3966 getF32Constant(DAG, 0x3f57ce70, dl));
3969 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3972 // No special expansion.
3973 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3976 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3977 /// limited-precision mode.
3978 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3979 const TargetLowering &TLI) {
3980 if (Op.getValueType() == MVT::f32 &&
3981 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3982 return getLimitedPrecisionExp2(Op, dl, DAG);
3984 // No special expansion.
3985 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3988 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3989 /// limited-precision mode with x == 10.0f.
3990 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3991 SelectionDAG &DAG, const TargetLowering &TLI) {
3992 bool IsExp10 = false;
3993 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3994 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3995 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3997 IsExp10 = LHSC->isExactlyValue(Ten);
4002 // Put the exponent in the right bit position for later addition to the
4005 // #define LOG2OF10 3.3219281f
4006 // t0 = Op * LOG2OF10;
4007 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4008 getF32Constant(DAG, 0x40549a78, dl));
4009 return getLimitedPrecisionExp2(t0, dl, DAG);
4012 // No special expansion.
4013 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4017 /// ExpandPowI - Expand a llvm.powi intrinsic.
4018 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4019 SelectionDAG &DAG) {
4020 // If RHS is a constant, we can expand this out to a multiplication tree,
4021 // otherwise we end up lowering to a call to __powidf2 (for example). When
4022 // optimizing for size, we only want to do this if the expansion would produce
4023 // a small number of multiplies, otherwise we do the full expansion.
4024 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4025 // Get the exponent as a positive value.
4026 unsigned Val = RHSC->getSExtValue();
4027 if ((int)Val < 0) Val = -Val;
4029 // powi(x, 0) -> 1.0
4031 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4033 const Function *F = DAG.getMachineFunction().getFunction();
4034 if (!F->optForSize() ||
4035 // If optimizing for size, don't insert too many multiplies.
4036 // This inserts up to 5 multiplies.
4037 countPopulation(Val) + Log2_32(Val) < 7) {
4038 // We use the simple binary decomposition method to generate the multiply
4039 // sequence. There are more optimal ways to do this (for example,
4040 // powi(x,15) generates one more multiply than it should), but this has
4041 // the benefit of being both really simple and much better than a libcall.
4042 SDValue Res; // Logically starts equal to 1.0
4043 SDValue CurSquare = LHS;
4047 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4049 Res = CurSquare; // 1.0*CurSquare.
4052 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4053 CurSquare, CurSquare);
4057 // If the original was negative, invert the result, producing 1/(x*x*x).
4058 if (RHSC->getSExtValue() < 0)
4059 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4060 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4065 // Otherwise, expand to a libcall.
4066 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4069 // getTruncatedArgReg - Find underlying register used for an truncated
4071 static unsigned getTruncatedArgReg(const SDValue &N) {
4072 if (N.getOpcode() != ISD::TRUNCATE)
4075 const SDValue &Ext = N.getOperand(0);
4076 if (Ext.getOpcode() == ISD::AssertZext ||
4077 Ext.getOpcode() == ISD::AssertSext) {
4078 const SDValue &CFR = Ext.getOperand(0);
4079 if (CFR.getOpcode() == ISD::CopyFromReg)
4080 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4081 if (CFR.getOpcode() == ISD::TRUNCATE)
4082 return getTruncatedArgReg(CFR);
4087 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4088 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4089 /// At the end of instruction selection, they will be inserted to the entry BB.
4090 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4091 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4092 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4093 const Argument *Arg = dyn_cast<Argument>(V);
4097 MachineFunction &MF = DAG.getMachineFunction();
4098 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4100 // Ignore inlined function arguments here.
4102 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4103 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4106 Optional<MachineOperand> Op;
4107 // Some arguments' frame index is recorded during argument lowering.
4108 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4109 Op = MachineOperand::CreateFI(FI);
4111 if (!Op && N.getNode()) {
4113 if (N.getOpcode() == ISD::CopyFromReg)
4114 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4116 Reg = getTruncatedArgReg(N);
4117 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4118 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4119 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4124 Op = MachineOperand::CreateReg(Reg, false);
4128 // Check if ValueMap has reg number.
4129 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4130 if (VMI != FuncInfo.ValueMap.end())
4131 Op = MachineOperand::CreateReg(VMI->second, false);
4134 if (!Op && N.getNode())
4135 // Check if frame index is available.
4136 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4137 if (FrameIndexSDNode *FINode =
4138 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4139 Op = MachineOperand::CreateFI(FINode->getIndex());
4144 assert(Variable->isValidLocationForIntrinsic(DL) &&
4145 "Expected inlined-at fields to agree");
4147 FuncInfo.ArgDbgValues.push_back(
4148 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4149 Op->getReg(), Offset, Variable, Expr));
4151 FuncInfo.ArgDbgValues.push_back(
4152 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4155 .addMetadata(Variable)
4156 .addMetadata(Expr));
4161 // VisualStudio defines setjmp as _setjmp
4162 #if defined(_MSC_VER) && defined(setjmp) && \
4163 !defined(setjmp_undefined_for_msvc)
4164 # pragma push_macro("setjmp")
4166 # define setjmp_undefined_for_msvc
4169 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4170 /// we want to emit this as a call to a named external function, return the name
4171 /// otherwise lower it and return null.
4173 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4174 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4175 SDLoc sdl = getCurSDLoc();
4176 DebugLoc dl = getCurDebugLoc();
4179 switch (Intrinsic) {
4181 // By default, turn this into a target intrinsic node.
4182 visitTargetIntrinsic(I, Intrinsic);
4184 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4185 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4186 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4187 case Intrinsic::returnaddress:
4188 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4189 TLI.getPointerTy(DAG.getDataLayout()),
4190 getValue(I.getArgOperand(0))));
4192 case Intrinsic::frameaddress:
4193 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4194 TLI.getPointerTy(DAG.getDataLayout()),
4195 getValue(I.getArgOperand(0))));
4197 case Intrinsic::read_register: {
4198 Value *Reg = I.getArgOperand(0);
4199 SDValue Chain = getRoot();
4201 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4202 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4203 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4204 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4206 DAG.setRoot(Res.getValue(1));
4209 case Intrinsic::write_register: {
4210 Value *Reg = I.getArgOperand(0);
4211 Value *RegValue = I.getArgOperand(1);
4212 SDValue Chain = getRoot();
4214 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4215 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4216 RegName, getValue(RegValue)));
4219 case Intrinsic::setjmp:
4220 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4221 case Intrinsic::longjmp:
4222 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4223 case Intrinsic::memcpy: {
4224 // FIXME: this definition of "user defined address space" is x86-specific
4225 // Assert for address < 256 since we support only user defined address
4227 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4229 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4231 "Unknown address space");
4232 SDValue Op1 = getValue(I.getArgOperand(0));
4233 SDValue Op2 = getValue(I.getArgOperand(1));
4234 SDValue Op3 = getValue(I.getArgOperand(2));
4235 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4237 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4238 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4239 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4240 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4242 MachinePointerInfo(I.getArgOperand(0)),
4243 MachinePointerInfo(I.getArgOperand(1)));
4244 updateDAGForMaybeTailCall(MC);
4247 case Intrinsic::memset: {
4248 // FIXME: this definition of "user defined address space" is x86-specific
4249 // Assert for address < 256 since we support only user defined address
4251 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4253 "Unknown address space");
4254 SDValue Op1 = getValue(I.getArgOperand(0));
4255 SDValue Op2 = getValue(I.getArgOperand(1));
4256 SDValue Op3 = getValue(I.getArgOperand(2));
4257 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4259 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4260 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4261 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4262 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4263 isTC, MachinePointerInfo(I.getArgOperand(0)));
4264 updateDAGForMaybeTailCall(MS);
4267 case Intrinsic::memmove: {
4268 // FIXME: this definition of "user defined address space" is x86-specific
4269 // Assert for address < 256 since we support only user defined address
4271 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4273 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4275 "Unknown address space");
4276 SDValue Op1 = getValue(I.getArgOperand(0));
4277 SDValue Op2 = getValue(I.getArgOperand(1));
4278 SDValue Op3 = getValue(I.getArgOperand(2));
4279 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4281 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4282 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4283 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4284 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4285 isTC, MachinePointerInfo(I.getArgOperand(0)),
4286 MachinePointerInfo(I.getArgOperand(1)));
4287 updateDAGForMaybeTailCall(MM);
4290 case Intrinsic::dbg_declare: {
4291 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4292 DILocalVariable *Variable = DI.getVariable();
4293 DIExpression *Expression = DI.getExpression();
4294 const Value *Address = DI.getAddress();
4295 assert(Variable && "Missing variable");
4297 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4301 // Check if address has undef value.
4302 if (isa<UndefValue>(Address) ||
4303 (Address->use_empty() && !isa<Argument>(Address))) {
4304 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4308 SDValue &N = NodeMap[Address];
4309 if (!N.getNode() && isa<Argument>(Address))
4310 // Check unused arguments map.
4311 N = UnusedArgNodeMap[Address];
4314 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4315 Address = BCI->getOperand(0);
4316 // Parameters are handled specially.
4317 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4319 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4321 if (isParameter && !AI) {
4322 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4324 // Byval parameter. We have a frame index at this point.
4325 SDV = DAG.getFrameIndexDbgValue(
4326 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4328 // Address is an argument, so try to emit its dbg value using
4329 // virtual register info from the FuncInfo.ValueMap.
4330 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4335 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4336 true, 0, dl, SDNodeOrder);
4338 // Can't do anything with other non-AI cases yet.
4339 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4340 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4341 DEBUG(Address->dump());
4344 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4346 // If Address is an argument then try to emit its dbg value using
4347 // virtual register info from the FuncInfo.ValueMap.
4348 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4350 // If variable is pinned by a alloca in dominating bb then
4351 // use StaticAllocaMap.
4352 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4353 if (AI->getParent() != DI.getParent()) {
4354 DenseMap<const AllocaInst*, int>::iterator SI =
4355 FuncInfo.StaticAllocaMap.find(AI);
4356 if (SI != FuncInfo.StaticAllocaMap.end()) {
4357 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4358 0, dl, SDNodeOrder);
4359 DAG.AddDbgValue(SDV, nullptr, false);
4364 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4369 case Intrinsic::dbg_value: {
4370 const DbgValueInst &DI = cast<DbgValueInst>(I);
4371 assert(DI.getVariable() && "Missing variable");
4373 DILocalVariable *Variable = DI.getVariable();
4374 DIExpression *Expression = DI.getExpression();
4375 uint64_t Offset = DI.getOffset();
4376 const Value *V = DI.getValue();
4381 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4382 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4384 DAG.AddDbgValue(SDV, nullptr, false);
4386 // Do not use getValue() in here; we don't want to generate code at
4387 // this point if it hasn't been done yet.
4388 SDValue N = NodeMap[V];
4389 if (!N.getNode() && isa<Argument>(V))
4390 // Check unused arguments map.
4391 N = UnusedArgNodeMap[V];
4393 // A dbg.value for an alloca is always indirect.
4394 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4395 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4397 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4398 IsIndirect, Offset, dl, SDNodeOrder);
4399 DAG.AddDbgValue(SDV, N.getNode(), false);
4401 } else if (!V->use_empty() ) {
4402 // Do not call getValue(V) yet, as we don't want to generate code.
4403 // Remember it for later.
4404 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4405 DanglingDebugInfoMap[V] = DDI;
4407 // We may expand this to cover more cases. One case where we have no
4408 // data available is an unreferenced parameter.
4409 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4413 // Build a debug info table entry.
4414 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4415 V = BCI->getOperand(0);
4416 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4417 // Don't handle byval struct arguments or VLAs, for example.
4419 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4420 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4423 DenseMap<const AllocaInst*, int>::iterator SI =
4424 FuncInfo.StaticAllocaMap.find(AI);
4425 if (SI == FuncInfo.StaticAllocaMap.end())
4426 return nullptr; // VLAs.
4430 case Intrinsic::eh_typeid_for: {
4431 // Find the type id for the given typeinfo.
4432 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4433 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4434 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4439 case Intrinsic::eh_return_i32:
4440 case Intrinsic::eh_return_i64:
4441 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4442 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4445 getValue(I.getArgOperand(0)),
4446 getValue(I.getArgOperand(1))));
4448 case Intrinsic::eh_unwind_init:
4449 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4451 case Intrinsic::eh_dwarf_cfa: {
4452 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4453 TLI.getPointerTy(DAG.getDataLayout()));
4454 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4455 CfaArg.getValueType(),
4456 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4457 CfaArg.getValueType()),
4459 SDValue FA = DAG.getNode(
4460 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4461 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4462 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4466 case Intrinsic::eh_sjlj_callsite: {
4467 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4468 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4469 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4470 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4472 MMI.setCurrentCallSite(CI->getZExtValue());
4475 case Intrinsic::eh_sjlj_functioncontext: {
4476 // Get and store the index of the function context.
4477 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4479 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4480 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4481 MFI->setFunctionContextIndex(FI);
4484 case Intrinsic::eh_sjlj_setjmp: {
4487 Ops[1] = getValue(I.getArgOperand(0));
4488 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4489 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4490 setValue(&I, Op.getValue(0));
4491 DAG.setRoot(Op.getValue(1));
4494 case Intrinsic::eh_sjlj_longjmp: {
4495 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4496 getRoot(), getValue(I.getArgOperand(0))));
4499 case Intrinsic::eh_sjlj_setup_dispatch: {
4500 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4505 case Intrinsic::masked_gather:
4506 visitMaskedGather(I);
4508 case Intrinsic::masked_load:
4511 case Intrinsic::masked_scatter:
4512 visitMaskedScatter(I);
4514 case Intrinsic::masked_store:
4515 visitMaskedStore(I);
4517 case Intrinsic::x86_mmx_pslli_w:
4518 case Intrinsic::x86_mmx_pslli_d:
4519 case Intrinsic::x86_mmx_pslli_q:
4520 case Intrinsic::x86_mmx_psrli_w:
4521 case Intrinsic::x86_mmx_psrli_d:
4522 case Intrinsic::x86_mmx_psrli_q:
4523 case Intrinsic::x86_mmx_psrai_w:
4524 case Intrinsic::x86_mmx_psrai_d: {
4525 SDValue ShAmt = getValue(I.getArgOperand(1));
4526 if (isa<ConstantSDNode>(ShAmt)) {
4527 visitTargetIntrinsic(I, Intrinsic);
4530 unsigned NewIntrinsic = 0;
4531 EVT ShAmtVT = MVT::v2i32;
4532 switch (Intrinsic) {
4533 case Intrinsic::x86_mmx_pslli_w:
4534 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4536 case Intrinsic::x86_mmx_pslli_d:
4537 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4539 case Intrinsic::x86_mmx_pslli_q:
4540 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4542 case Intrinsic::x86_mmx_psrli_w:
4543 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4545 case Intrinsic::x86_mmx_psrli_d:
4546 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4548 case Intrinsic::x86_mmx_psrli_q:
4549 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4551 case Intrinsic::x86_mmx_psrai_w:
4552 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4554 case Intrinsic::x86_mmx_psrai_d:
4555 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4557 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4560 // The vector shift intrinsics with scalars uses 32b shift amounts but
4561 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4563 // We must do this early because v2i32 is not a legal type.
4566 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4567 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4568 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4569 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4570 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4571 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4572 getValue(I.getArgOperand(0)), ShAmt);
4576 case Intrinsic::convertff:
4577 case Intrinsic::convertfsi:
4578 case Intrinsic::convertfui:
4579 case Intrinsic::convertsif:
4580 case Intrinsic::convertuif:
4581 case Intrinsic::convertss:
4582 case Intrinsic::convertsu:
4583 case Intrinsic::convertus:
4584 case Intrinsic::convertuu: {
4585 ISD::CvtCode Code = ISD::CVT_INVALID;
4586 switch (Intrinsic) {
4587 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4588 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4589 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4590 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4591 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4592 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4593 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4594 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4595 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4596 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4598 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4599 const Value *Op1 = I.getArgOperand(0);
4600 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4601 DAG.getValueType(DestVT),
4602 DAG.getValueType(getValue(Op1).getValueType()),
4603 getValue(I.getArgOperand(1)),
4604 getValue(I.getArgOperand(2)),
4609 case Intrinsic::powi:
4610 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4611 getValue(I.getArgOperand(1)), DAG));
4613 case Intrinsic::log:
4614 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4616 case Intrinsic::log2:
4617 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4619 case Intrinsic::log10:
4620 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4622 case Intrinsic::exp:
4623 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4625 case Intrinsic::exp2:
4626 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4628 case Intrinsic::pow:
4629 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4630 getValue(I.getArgOperand(1)), DAG, TLI));
4632 case Intrinsic::sqrt:
4633 case Intrinsic::fabs:
4634 case Intrinsic::sin:
4635 case Intrinsic::cos:
4636 case Intrinsic::floor:
4637 case Intrinsic::ceil:
4638 case Intrinsic::trunc:
4639 case Intrinsic::rint:
4640 case Intrinsic::nearbyint:
4641 case Intrinsic::round: {
4643 switch (Intrinsic) {
4644 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4645 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4646 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4647 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4648 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4649 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4650 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4651 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4652 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4653 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4654 case Intrinsic::round: Opcode = ISD::FROUND; break;
4657 setValue(&I, DAG.getNode(Opcode, sdl,
4658 getValue(I.getArgOperand(0)).getValueType(),
4659 getValue(I.getArgOperand(0))));
4662 case Intrinsic::minnum:
4663 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4664 getValue(I.getArgOperand(0)).getValueType(),
4665 getValue(I.getArgOperand(0)),
4666 getValue(I.getArgOperand(1))));
4668 case Intrinsic::maxnum:
4669 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4670 getValue(I.getArgOperand(0)).getValueType(),
4671 getValue(I.getArgOperand(0)),
4672 getValue(I.getArgOperand(1))));
4674 case Intrinsic::copysign:
4675 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4676 getValue(I.getArgOperand(0)).getValueType(),
4677 getValue(I.getArgOperand(0)),
4678 getValue(I.getArgOperand(1))));
4680 case Intrinsic::fma:
4681 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4682 getValue(I.getArgOperand(0)).getValueType(),
4683 getValue(I.getArgOperand(0)),
4684 getValue(I.getArgOperand(1)),
4685 getValue(I.getArgOperand(2))));
4687 case Intrinsic::fmuladd: {
4688 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4689 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4690 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4691 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4692 getValue(I.getArgOperand(0)).getValueType(),
4693 getValue(I.getArgOperand(0)),
4694 getValue(I.getArgOperand(1)),
4695 getValue(I.getArgOperand(2))));
4697 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4698 getValue(I.getArgOperand(0)).getValueType(),
4699 getValue(I.getArgOperand(0)),
4700 getValue(I.getArgOperand(1)));
4701 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4702 getValue(I.getArgOperand(0)).getValueType(),
4704 getValue(I.getArgOperand(2)));
4709 case Intrinsic::convert_to_fp16:
4710 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4711 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4712 getValue(I.getArgOperand(0)),
4713 DAG.getTargetConstant(0, sdl,
4716 case Intrinsic::convert_from_fp16:
4717 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4718 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4719 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4720 getValue(I.getArgOperand(0)))));
4722 case Intrinsic::pcmarker: {
4723 SDValue Tmp = getValue(I.getArgOperand(0));
4724 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4727 case Intrinsic::readcyclecounter: {
4728 SDValue Op = getRoot();
4729 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4730 DAG.getVTList(MVT::i64, MVT::Other), Op);
4732 DAG.setRoot(Res.getValue(1));
4735 case Intrinsic::bswap:
4736 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4737 getValue(I.getArgOperand(0)).getValueType(),
4738 getValue(I.getArgOperand(0))));
4740 case Intrinsic::uabsdiff:
4741 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4742 getValue(I.getArgOperand(0)).getValueType(),
4743 getValue(I.getArgOperand(0)),
4744 getValue(I.getArgOperand(1))));
4746 case Intrinsic::sabsdiff:
4747 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4748 getValue(I.getArgOperand(0)).getValueType(),
4749 getValue(I.getArgOperand(0)),
4750 getValue(I.getArgOperand(1))));
4752 case Intrinsic::cttz: {
4753 SDValue Arg = getValue(I.getArgOperand(0));
4754 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4755 EVT Ty = Arg.getValueType();
4756 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4760 case Intrinsic::ctlz: {
4761 SDValue Arg = getValue(I.getArgOperand(0));
4762 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4763 EVT Ty = Arg.getValueType();
4764 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4768 case Intrinsic::ctpop: {
4769 SDValue Arg = getValue(I.getArgOperand(0));
4770 EVT Ty = Arg.getValueType();
4771 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4774 case Intrinsic::stacksave: {
4775 SDValue Op = getRoot();
4777 ISD::STACKSAVE, sdl,
4778 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4780 DAG.setRoot(Res.getValue(1));
4783 case Intrinsic::stackrestore: {
4784 Res = getValue(I.getArgOperand(0));
4785 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4788 case Intrinsic::stackprotector: {
4789 // Emit code into the DAG to store the stack guard onto the stack.
4790 MachineFunction &MF = DAG.getMachineFunction();
4791 MachineFrameInfo *MFI = MF.getFrameInfo();
4792 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4793 SDValue Src, Chain = getRoot();
4794 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4795 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4797 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4798 // global variable __stack_chk_guard.
4800 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4801 if (BC->getOpcode() == Instruction::BitCast)
4802 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4804 if (GV && TLI.useLoadStackGuardNode()) {
4805 // Emit a LOAD_STACK_GUARD node.
4806 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4808 MachinePointerInfo MPInfo(GV);
4809 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4810 unsigned Flags = MachineMemOperand::MOLoad |
4811 MachineMemOperand::MOInvariant;
4812 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4813 PtrTy.getSizeInBits() / 8,
4814 DAG.getEVTAlignment(PtrTy));
4815 Node->setMemRefs(MemRefs, MemRefs + 1);
4817 // Copy the guard value to a virtual register so that it can be
4818 // retrieved in the epilogue.
4819 Src = SDValue(Node, 0);
4820 const TargetRegisterClass *RC =
4821 TLI.getRegClassFor(Src.getSimpleValueType());
4822 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4824 SPDescriptor.setGuardReg(Reg);
4825 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4827 Src = getValue(I.getArgOperand(0)); // The guard's value.
4830 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4832 int FI = FuncInfo.StaticAllocaMap[Slot];
4833 MFI->setStackProtectorIndex(FI);
4835 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4837 // Store the stack protector onto the stack.
4838 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4839 DAG.getMachineFunction(), FI),
4845 case Intrinsic::objectsize: {
4846 // If we don't know by now, we're never going to know.
4847 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4849 assert(CI && "Non-constant type in __builtin_object_size?");
4851 SDValue Arg = getValue(I.getCalledValue());
4852 EVT Ty = Arg.getValueType();
4855 Res = DAG.getConstant(-1ULL, sdl, Ty);
4857 Res = DAG.getConstant(0, sdl, Ty);
4862 case Intrinsic::annotation:
4863 case Intrinsic::ptr_annotation:
4864 // Drop the intrinsic, but forward the value
4865 setValue(&I, getValue(I.getOperand(0)));
4867 case Intrinsic::assume:
4868 case Intrinsic::var_annotation:
4869 // Discard annotate attributes and assumptions
4872 case Intrinsic::init_trampoline: {
4873 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4877 Ops[1] = getValue(I.getArgOperand(0));
4878 Ops[2] = getValue(I.getArgOperand(1));
4879 Ops[3] = getValue(I.getArgOperand(2));
4880 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4881 Ops[5] = DAG.getSrcValue(F);
4883 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4888 case Intrinsic::adjust_trampoline: {
4889 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4890 TLI.getPointerTy(DAG.getDataLayout()),
4891 getValue(I.getArgOperand(0))));
4894 case Intrinsic::gcroot:
4896 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4897 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4899 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4900 GFI->addStackRoot(FI->getIndex(), TypeMap);
4903 case Intrinsic::gcread:
4904 case Intrinsic::gcwrite:
4905 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4906 case Intrinsic::flt_rounds:
4907 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4910 case Intrinsic::expect: {
4911 // Just replace __builtin_expect(exp, c) with EXP.
4912 setValue(&I, getValue(I.getArgOperand(0)));
4916 case Intrinsic::debugtrap:
4917 case Intrinsic::trap: {
4918 StringRef TrapFuncName =
4920 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4921 .getValueAsString();
4922 if (TrapFuncName.empty()) {
4923 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4924 ISD::TRAP : ISD::DEBUGTRAP;
4925 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4928 TargetLowering::ArgListTy Args;
4930 TargetLowering::CallLoweringInfo CLI(DAG);
4931 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4932 CallingConv::C, I.getType(),
4933 DAG.getExternalSymbol(TrapFuncName.data(),
4934 TLI.getPointerTy(DAG.getDataLayout())),
4935 std::move(Args), 0);
4937 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4938 DAG.setRoot(Result.second);
4942 case Intrinsic::uadd_with_overflow:
4943 case Intrinsic::sadd_with_overflow:
4944 case Intrinsic::usub_with_overflow:
4945 case Intrinsic::ssub_with_overflow:
4946 case Intrinsic::umul_with_overflow:
4947 case Intrinsic::smul_with_overflow: {
4949 switch (Intrinsic) {
4950 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4951 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4952 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4953 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4954 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4955 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4956 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4958 SDValue Op1 = getValue(I.getArgOperand(0));
4959 SDValue Op2 = getValue(I.getArgOperand(1));
4961 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4962 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4965 case Intrinsic::prefetch: {
4967 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4969 Ops[1] = getValue(I.getArgOperand(0));
4970 Ops[2] = getValue(I.getArgOperand(1));
4971 Ops[3] = getValue(I.getArgOperand(2));
4972 Ops[4] = getValue(I.getArgOperand(3));
4973 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4974 DAG.getVTList(MVT::Other), Ops,
4975 EVT::getIntegerVT(*Context, 8),
4976 MachinePointerInfo(I.getArgOperand(0)),
4978 false, /* volatile */
4980 rw==1)); /* write */
4983 case Intrinsic::lifetime_start:
4984 case Intrinsic::lifetime_end: {
4985 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4986 // Stack coloring is not enabled in O0, discard region information.
4987 if (TM.getOptLevel() == CodeGenOpt::None)
4990 SmallVector<Value *, 4> Allocas;
4991 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4993 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4994 E = Allocas.end(); Object != E; ++Object) {
4995 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4997 // Could not find an Alloca.
4998 if (!LifetimeObject)
5001 // First check that the Alloca is static, otherwise it won't have a
5002 // valid frame index.
5003 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5004 if (SI == FuncInfo.StaticAllocaMap.end())
5007 int FI = SI->second;
5012 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5013 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5015 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5020 case Intrinsic::invariant_start:
5021 // Discard region information.
5022 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5024 case Intrinsic::invariant_end:
5025 // Discard region information.
5027 case Intrinsic::stackprotectorcheck: {
5028 // Do not actually emit anything for this basic block. Instead we initialize
5029 // the stack protector descriptor and export the guard variable so we can
5030 // access it in FinishBasicBlock.
5031 const BasicBlock *BB = I.getParent();
5032 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5033 ExportFromCurrentBlock(SPDescriptor.getGuard());
5035 // Flush our exports since we are going to process a terminator.
5036 (void)getControlRoot();
5039 case Intrinsic::clear_cache:
5040 return TLI.getClearCacheBuiltinName();
5041 case Intrinsic::eh_actions:
5042 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5044 case Intrinsic::donothing:
5047 case Intrinsic::experimental_stackmap: {
5051 case Intrinsic::experimental_patchpoint_void:
5052 case Intrinsic::experimental_patchpoint_i64: {
5053 visitPatchpoint(&I);
5056 case Intrinsic::experimental_gc_statepoint: {
5060 case Intrinsic::experimental_gc_result_int:
5061 case Intrinsic::experimental_gc_result_float:
5062 case Intrinsic::experimental_gc_result_ptr:
5063 case Intrinsic::experimental_gc_result: {
5067 case Intrinsic::experimental_gc_relocate: {
5071 case Intrinsic::instrprof_increment:
5072 llvm_unreachable("instrprof failed to lower an increment");
5074 case Intrinsic::localescape: {
5075 MachineFunction &MF = DAG.getMachineFunction();
5076 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5078 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5079 // is the same on all targets.
5080 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5081 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5082 if (isa<ConstantPointerNull>(Arg))
5083 continue; // Skip null pointers. They represent a hole in index space.
5084 AllocaInst *Slot = cast<AllocaInst>(Arg);
5085 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5086 "can only escape static allocas");
5087 int FI = FuncInfo.StaticAllocaMap[Slot];
5088 MCSymbol *FrameAllocSym =
5089 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5090 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5091 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5092 TII->get(TargetOpcode::LOCAL_ESCAPE))
5093 .addSym(FrameAllocSym)
5100 case Intrinsic::localrecover: {
5101 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5102 MachineFunction &MF = DAG.getMachineFunction();
5103 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5105 // Get the symbol that defines the frame offset.
5106 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5107 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5108 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5109 MCSymbol *FrameAllocSym =
5110 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5111 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5113 // Create a MCSymbol for the label to avoid any target lowering
5114 // that would make this PC relative.
5115 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5117 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5119 // Add the offset to the FP.
5120 Value *FP = I.getArgOperand(1);
5121 SDValue FPVal = getValue(FP);
5122 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5127 case Intrinsic::eh_begincatch:
5128 case Intrinsic::eh_endcatch:
5129 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5130 case Intrinsic::eh_exceptioncode: {
5131 unsigned Reg = TLI.getExceptionPointerRegister();
5132 assert(Reg && "cannot get exception code on this platform");
5133 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5134 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5135 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5136 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5138 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5139 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5146 std::pair<SDValue, SDValue>
5147 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5148 MachineBasicBlock *LandingPad) {
5149 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5150 MCSymbol *BeginLabel = nullptr;
5153 // Insert a label before the invoke call to mark the try range. This can be
5154 // used to detect deletion of the invoke via the MachineModuleInfo.
5155 BeginLabel = MMI.getContext().createTempSymbol();
5157 // For SjLj, keep track of which landing pads go with which invokes
5158 // so as to maintain the ordering of pads in the LSDA.
5159 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5160 if (CallSiteIndex) {
5161 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5162 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5164 // Now that the call site is handled, stop tracking it.
5165 MMI.setCurrentCallSite(0);
5168 // Both PendingLoads and PendingExports must be flushed here;
5169 // this call might not return.
5171 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5173 CLI.setChain(getRoot());
5175 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5176 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5178 assert((CLI.IsTailCall || Result.second.getNode()) &&
5179 "Non-null chain expected with non-tail call!");
5180 assert((Result.second.getNode() || !Result.first.getNode()) &&
5181 "Null value expected with tail call!");
5183 if (!Result.second.getNode()) {
5184 // As a special case, a null chain means that a tail call has been emitted
5185 // and the DAG root is already updated.
5188 // Since there's no actual continuation from this block, nothing can be
5189 // relying on us setting vregs for them.
5190 PendingExports.clear();
5192 DAG.setRoot(Result.second);
5196 // Insert a label at the end of the invoke call to mark the try range. This
5197 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5198 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5199 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5201 // Inform MachineModuleInfo of range.
5202 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5208 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5210 MachineBasicBlock *LandingPad) {
5211 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5212 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5213 Type *RetTy = FTy->getReturnType();
5215 TargetLowering::ArgListTy Args;
5216 TargetLowering::ArgListEntry Entry;
5217 Args.reserve(CS.arg_size());
5219 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5221 const Value *V = *i;
5224 if (V->getType()->isEmptyTy())
5227 SDValue ArgNode = getValue(V);
5228 Entry.Node = ArgNode; Entry.Ty = V->getType();
5230 // Skip the first return-type Attribute to get to params.
5231 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5232 Args.push_back(Entry);
5234 // If we have an explicit sret argument that is an Instruction, (i.e., it
5235 // might point to function-local memory), we can't meaningfully tail-call.
5236 if (Entry.isSRet && isa<Instruction>(V))
5240 // Check if target-independent constraints permit a tail call here.
5241 // Target-dependent constraints are checked within TLI->LowerCallTo.
5242 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5245 TargetLowering::CallLoweringInfo CLI(DAG);
5246 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5247 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5248 .setTailCall(isTailCall);
5249 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5251 if (Result.first.getNode())
5252 setValue(CS.getInstruction(), Result.first);
5255 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5256 /// value is equal or not-equal to zero.
5257 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5258 for (const User *U : V->users()) {
5259 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5260 if (IC->isEquality())
5261 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5262 if (C->isNullValue())
5264 // Unknown instruction.
5270 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5272 SelectionDAGBuilder &Builder) {
5274 // Check to see if this load can be trivially constant folded, e.g. if the
5275 // input is from a string literal.
5276 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5277 // Cast pointer to the type we really want to load.
5278 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5279 PointerType::getUnqual(LoadTy));
5281 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5282 const_cast<Constant *>(LoadInput), *Builder.DL))
5283 return Builder.getValue(LoadCst);
5286 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5287 // still constant memory, the input chain can be the entry node.
5289 bool ConstantMemory = false;
5291 // Do not serialize (non-volatile) loads of constant memory with anything.
5292 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5293 Root = Builder.DAG.getEntryNode();
5294 ConstantMemory = true;
5296 // Do not serialize non-volatile loads against each other.
5297 Root = Builder.DAG.getRoot();
5300 SDValue Ptr = Builder.getValue(PtrVal);
5301 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5302 Ptr, MachinePointerInfo(PtrVal),
5304 false /*nontemporal*/,
5305 false /*isinvariant*/, 1 /* align=1 */);
5307 if (!ConstantMemory)
5308 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5312 /// processIntegerCallValue - Record the value for an instruction that
5313 /// produces an integer result, converting the type where necessary.
5314 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5317 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5320 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5322 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5323 setValue(&I, Value);
5326 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5327 /// If so, return true and lower it, otherwise return false and it will be
5328 /// lowered like a normal call.
5329 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5330 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5331 if (I.getNumArgOperands() != 3)
5334 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5335 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5336 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5337 !I.getType()->isIntegerTy())
5340 const Value *Size = I.getArgOperand(2);
5341 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5342 if (CSize && CSize->getZExtValue() == 0) {
5343 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5345 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5349 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5350 std::pair<SDValue, SDValue> Res =
5351 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5352 getValue(LHS), getValue(RHS), getValue(Size),
5353 MachinePointerInfo(LHS),
5354 MachinePointerInfo(RHS));
5355 if (Res.first.getNode()) {
5356 processIntegerCallValue(I, Res.first, true);
5357 PendingLoads.push_back(Res.second);
5361 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5362 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5363 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5364 bool ActuallyDoIt = true;
5367 switch (CSize->getZExtValue()) {
5369 LoadVT = MVT::Other;
5371 ActuallyDoIt = false;
5375 LoadTy = Type::getInt16Ty(CSize->getContext());
5379 LoadTy = Type::getInt32Ty(CSize->getContext());
5383 LoadTy = Type::getInt64Ty(CSize->getContext());
5387 LoadVT = MVT::v4i32;
5388 LoadTy = Type::getInt32Ty(CSize->getContext());
5389 LoadTy = VectorType::get(LoadTy, 4);
5394 // This turns into unaligned loads. We only do this if the target natively
5395 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5396 // we'll only produce a small number of byte loads.
5398 // Require that we can find a legal MVT, and only do this if the target
5399 // supports unaligned loads of that type. Expanding into byte loads would
5401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5402 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5403 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5404 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5405 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5406 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5407 // TODO: Check alignment of src and dest ptrs.
5408 if (!TLI.isTypeLegal(LoadVT) ||
5409 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5410 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5411 ActuallyDoIt = false;
5415 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5416 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5418 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5420 processIntegerCallValue(I, Res, false);
5429 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5430 /// form. If so, return true and lower it, otherwise return false and it
5431 /// will be lowered like a normal call.
5432 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5433 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5434 if (I.getNumArgOperands() != 3)
5437 const Value *Src = I.getArgOperand(0);
5438 const Value *Char = I.getArgOperand(1);
5439 const Value *Length = I.getArgOperand(2);
5440 if (!Src->getType()->isPointerTy() ||
5441 !Char->getType()->isIntegerTy() ||
5442 !Length->getType()->isIntegerTy() ||
5443 !I.getType()->isPointerTy())
5446 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5447 std::pair<SDValue, SDValue> Res =
5448 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5449 getValue(Src), getValue(Char), getValue(Length),
5450 MachinePointerInfo(Src));
5451 if (Res.first.getNode()) {
5452 setValue(&I, Res.first);
5453 PendingLoads.push_back(Res.second);
5460 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5461 /// optimized form. If so, return true and lower it, otherwise return false
5462 /// and it will be lowered like a normal call.
5463 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5464 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5465 if (I.getNumArgOperands() != 2)
5468 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5469 if (!Arg0->getType()->isPointerTy() ||
5470 !Arg1->getType()->isPointerTy() ||
5471 !I.getType()->isPointerTy())
5474 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5475 std::pair<SDValue, SDValue> Res =
5476 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5477 getValue(Arg0), getValue(Arg1),
5478 MachinePointerInfo(Arg0),
5479 MachinePointerInfo(Arg1), isStpcpy);
5480 if (Res.first.getNode()) {
5481 setValue(&I, Res.first);
5482 DAG.setRoot(Res.second);
5489 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5490 /// If so, return true and lower it, otherwise return false and it will be
5491 /// lowered like a normal call.
5492 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5493 // Verify that the prototype makes sense. int strcmp(void*,void*)
5494 if (I.getNumArgOperands() != 2)
5497 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5498 if (!Arg0->getType()->isPointerTy() ||
5499 !Arg1->getType()->isPointerTy() ||
5500 !I.getType()->isIntegerTy())
5503 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5504 std::pair<SDValue, SDValue> Res =
5505 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5506 getValue(Arg0), getValue(Arg1),
5507 MachinePointerInfo(Arg0),
5508 MachinePointerInfo(Arg1));
5509 if (Res.first.getNode()) {
5510 processIntegerCallValue(I, Res.first, true);
5511 PendingLoads.push_back(Res.second);
5518 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5519 /// form. If so, return true and lower it, otherwise return false and it
5520 /// will be lowered like a normal call.
5521 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5522 // Verify that the prototype makes sense. size_t strlen(char *)
5523 if (I.getNumArgOperands() != 1)
5526 const Value *Arg0 = I.getArgOperand(0);
5527 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5530 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5531 std::pair<SDValue, SDValue> Res =
5532 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5533 getValue(Arg0), MachinePointerInfo(Arg0));
5534 if (Res.first.getNode()) {
5535 processIntegerCallValue(I, Res.first, false);
5536 PendingLoads.push_back(Res.second);
5543 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5544 /// form. If so, return true and lower it, otherwise return false and it
5545 /// will be lowered like a normal call.
5546 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5547 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5548 if (I.getNumArgOperands() != 2)
5551 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5552 if (!Arg0->getType()->isPointerTy() ||
5553 !Arg1->getType()->isIntegerTy() ||
5554 !I.getType()->isIntegerTy())
5557 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5558 std::pair<SDValue, SDValue> Res =
5559 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5560 getValue(Arg0), getValue(Arg1),
5561 MachinePointerInfo(Arg0));
5562 if (Res.first.getNode()) {
5563 processIntegerCallValue(I, Res.first, false);
5564 PendingLoads.push_back(Res.second);
5571 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5572 /// operation (as expected), translate it to an SDNode with the specified opcode
5573 /// and return true.
5574 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5576 // Sanity check that it really is a unary floating-point call.
5577 if (I.getNumArgOperands() != 1 ||
5578 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5579 I.getType() != I.getArgOperand(0)->getType() ||
5580 !I.onlyReadsMemory())
5583 SDValue Tmp = getValue(I.getArgOperand(0));
5584 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5588 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5589 /// operation (as expected), translate it to an SDNode with the specified opcode
5590 /// and return true.
5591 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5593 // Sanity check that it really is a binary floating-point call.
5594 if (I.getNumArgOperands() != 2 ||
5595 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5596 I.getType() != I.getArgOperand(0)->getType() ||
5597 I.getType() != I.getArgOperand(1)->getType() ||
5598 !I.onlyReadsMemory())
5601 SDValue Tmp0 = getValue(I.getArgOperand(0));
5602 SDValue Tmp1 = getValue(I.getArgOperand(1));
5603 EVT VT = Tmp0.getValueType();
5604 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5608 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5609 // Handle inline assembly differently.
5610 if (isa<InlineAsm>(I.getCalledValue())) {
5615 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5616 ComputeUsesVAFloatArgument(I, &MMI);
5618 const char *RenameFn = nullptr;
5619 if (Function *F = I.getCalledFunction()) {
5620 if (F->isDeclaration()) {
5621 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5622 if (unsigned IID = II->getIntrinsicID(F)) {
5623 RenameFn = visitIntrinsicCall(I, IID);
5628 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5629 RenameFn = visitIntrinsicCall(I, IID);
5635 // Check for well-known libc/libm calls. If the function is internal, it
5636 // can't be a library call.
5638 if (!F->hasLocalLinkage() && F->hasName() &&
5639 LibInfo->getLibFunc(F->getName(), Func) &&
5640 LibInfo->hasOptimizedCodeGen(Func)) {
5643 case LibFunc::copysign:
5644 case LibFunc::copysignf:
5645 case LibFunc::copysignl:
5646 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5647 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5648 I.getType() == I.getArgOperand(0)->getType() &&
5649 I.getType() == I.getArgOperand(1)->getType() &&
5650 I.onlyReadsMemory()) {
5651 SDValue LHS = getValue(I.getArgOperand(0));
5652 SDValue RHS = getValue(I.getArgOperand(1));
5653 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5654 LHS.getValueType(), LHS, RHS));
5659 case LibFunc::fabsf:
5660 case LibFunc::fabsl:
5661 if (visitUnaryFloatCall(I, ISD::FABS))
5665 case LibFunc::fminf:
5666 case LibFunc::fminl:
5667 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5671 case LibFunc::fmaxf:
5672 case LibFunc::fmaxl:
5673 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5679 if (visitUnaryFloatCall(I, ISD::FSIN))
5685 if (visitUnaryFloatCall(I, ISD::FCOS))
5689 case LibFunc::sqrtf:
5690 case LibFunc::sqrtl:
5691 case LibFunc::sqrt_finite:
5692 case LibFunc::sqrtf_finite:
5693 case LibFunc::sqrtl_finite:
5694 if (visitUnaryFloatCall(I, ISD::FSQRT))
5697 case LibFunc::floor:
5698 case LibFunc::floorf:
5699 case LibFunc::floorl:
5700 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5703 case LibFunc::nearbyint:
5704 case LibFunc::nearbyintf:
5705 case LibFunc::nearbyintl:
5706 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5710 case LibFunc::ceilf:
5711 case LibFunc::ceill:
5712 if (visitUnaryFloatCall(I, ISD::FCEIL))
5716 case LibFunc::rintf:
5717 case LibFunc::rintl:
5718 if (visitUnaryFloatCall(I, ISD::FRINT))
5721 case LibFunc::round:
5722 case LibFunc::roundf:
5723 case LibFunc::roundl:
5724 if (visitUnaryFloatCall(I, ISD::FROUND))
5727 case LibFunc::trunc:
5728 case LibFunc::truncf:
5729 case LibFunc::truncl:
5730 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5734 case LibFunc::log2f:
5735 case LibFunc::log2l:
5736 if (visitUnaryFloatCall(I, ISD::FLOG2))
5740 case LibFunc::exp2f:
5741 case LibFunc::exp2l:
5742 if (visitUnaryFloatCall(I, ISD::FEXP2))
5745 case LibFunc::memcmp:
5746 if (visitMemCmpCall(I))
5749 case LibFunc::memchr:
5750 if (visitMemChrCall(I))
5753 case LibFunc::strcpy:
5754 if (visitStrCpyCall(I, false))
5757 case LibFunc::stpcpy:
5758 if (visitStrCpyCall(I, true))
5761 case LibFunc::strcmp:
5762 if (visitStrCmpCall(I))
5765 case LibFunc::strlen:
5766 if (visitStrLenCall(I))
5769 case LibFunc::strnlen:
5770 if (visitStrNLenCall(I))
5779 Callee = getValue(I.getCalledValue());
5781 Callee = DAG.getExternalSymbol(
5783 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5785 // Check if we can potentially perform a tail call. More detailed checking is
5786 // be done within LowerCallTo, after more information about the call is known.
5787 LowerCallTo(&I, Callee, I.isTailCall());
5792 /// AsmOperandInfo - This contains information for each constraint that we are
5794 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5796 /// CallOperand - If this is the result output operand or a clobber
5797 /// this is null, otherwise it is the incoming operand to the CallInst.
5798 /// This gets modified as the asm is processed.
5799 SDValue CallOperand;
5801 /// AssignedRegs - If this is a register or register class operand, this
5802 /// contains the set of register corresponding to the operand.
5803 RegsForValue AssignedRegs;
5805 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5806 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5809 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5810 /// corresponds to. If there is no Value* for this operand, it returns
5812 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5813 const DataLayout &DL) const {
5814 if (!CallOperandVal) return MVT::Other;
5816 if (isa<BasicBlock>(CallOperandVal))
5817 return TLI.getPointerTy(DL);
5819 llvm::Type *OpTy = CallOperandVal->getType();
5821 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5822 // If this is an indirect operand, the operand is a pointer to the
5825 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5827 report_fatal_error("Indirect operand for inline asm not a pointer!");
5828 OpTy = PtrTy->getElementType();
5831 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5832 if (StructType *STy = dyn_cast<StructType>(OpTy))
5833 if (STy->getNumElements() == 1)
5834 OpTy = STy->getElementType(0);
5836 // If OpTy is not a single value, it may be a struct/union that we
5837 // can tile with integers.
5838 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5839 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5848 OpTy = IntegerType::get(Context, BitSize);
5853 return TLI.getValueType(DL, OpTy, true);
5857 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5859 } // end anonymous namespace
5861 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5862 /// specified operand. We prefer to assign virtual registers, to allow the
5863 /// register allocator to handle the assignment process. However, if the asm
5864 /// uses features that we can't model on machineinstrs, we have SDISel do the
5865 /// allocation. This produces generally horrible, but correct, code.
5867 /// OpInfo describes the operand.
5869 static void GetRegistersForValue(SelectionDAG &DAG,
5870 const TargetLowering &TLI,
5872 SDISelAsmOperandInfo &OpInfo) {
5873 LLVMContext &Context = *DAG.getContext();
5875 MachineFunction &MF = DAG.getMachineFunction();
5876 SmallVector<unsigned, 4> Regs;
5878 // If this is a constraint for a single physreg, or a constraint for a
5879 // register class, find it.
5880 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5881 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5882 OpInfo.ConstraintCode,
5883 OpInfo.ConstraintVT);
5885 unsigned NumRegs = 1;
5886 if (OpInfo.ConstraintVT != MVT::Other) {
5887 // If this is a FP input in an integer register (or visa versa) insert a bit
5888 // cast of the input value. More generally, handle any case where the input
5889 // value disagrees with the register class we plan to stick this in.
5890 if (OpInfo.Type == InlineAsm::isInput &&
5891 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5892 // Try to convert to the first EVT that the reg class contains. If the
5893 // types are identical size, use a bitcast to convert (e.g. two differing
5895 MVT RegVT = *PhysReg.second->vt_begin();
5896 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5897 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5898 RegVT, OpInfo.CallOperand);
5899 OpInfo.ConstraintVT = RegVT;
5900 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5901 // If the input is a FP value and we want it in FP registers, do a
5902 // bitcast to the corresponding integer type. This turns an f64 value
5903 // into i64, which can be passed with two i32 values on a 32-bit
5905 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5906 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5907 RegVT, OpInfo.CallOperand);
5908 OpInfo.ConstraintVT = RegVT;
5912 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5916 EVT ValueVT = OpInfo.ConstraintVT;
5918 // If this is a constraint for a specific physical register, like {r17},
5920 if (unsigned AssignedReg = PhysReg.first) {
5921 const TargetRegisterClass *RC = PhysReg.second;
5922 if (OpInfo.ConstraintVT == MVT::Other)
5923 ValueVT = *RC->vt_begin();
5925 // Get the actual register value type. This is important, because the user
5926 // may have asked for (e.g.) the AX register in i32 type. We need to
5927 // remember that AX is actually i16 to get the right extension.
5928 RegVT = *RC->vt_begin();
5930 // This is a explicit reference to a physical register.
5931 Regs.push_back(AssignedReg);
5933 // If this is an expanded reference, add the rest of the regs to Regs.
5935 TargetRegisterClass::iterator I = RC->begin();
5936 for (; *I != AssignedReg; ++I)
5937 assert(I != RC->end() && "Didn't find reg!");
5939 // Already added the first reg.
5941 for (; NumRegs; --NumRegs, ++I) {
5942 assert(I != RC->end() && "Ran out of registers to allocate!");
5947 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5951 // Otherwise, if this was a reference to an LLVM register class, create vregs
5952 // for this reference.
5953 if (const TargetRegisterClass *RC = PhysReg.second) {
5954 RegVT = *RC->vt_begin();
5955 if (OpInfo.ConstraintVT == MVT::Other)
5958 // Create the appropriate number of virtual registers.
5959 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5960 for (; NumRegs; --NumRegs)
5961 Regs.push_back(RegInfo.createVirtualRegister(RC));
5963 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5967 // Otherwise, we couldn't allocate enough registers for this.
5970 /// visitInlineAsm - Handle a call to an InlineAsm object.
5972 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5973 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5975 /// ConstraintOperands - Information about all of the constraints.
5976 SDISelAsmOperandInfoVector ConstraintOperands;
5978 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5979 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5980 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5982 bool hasMemory = false;
5984 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5985 unsigned ResNo = 0; // ResNo - The result number of the next output.
5986 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5987 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5988 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5990 MVT OpVT = MVT::Other;
5992 // Compute the value type for each operand.
5993 switch (OpInfo.Type) {
5994 case InlineAsm::isOutput:
5995 // Indirect outputs just consume an argument.
5996 if (OpInfo.isIndirect) {
5997 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6001 // The return value of the call is this value. As such, there is no
6002 // corresponding argument.
6003 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6004 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6005 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6006 STy->getElementType(ResNo));
6008 assert(ResNo == 0 && "Asm only has one result!");
6009 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6013 case InlineAsm::isInput:
6014 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6016 case InlineAsm::isClobber:
6021 // If this is an input or an indirect output, process the call argument.
6022 // BasicBlocks are labels, currently appearing only in asm's.
6023 if (OpInfo.CallOperandVal) {
6024 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6025 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6027 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6030 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6031 DAG.getDataLayout()).getSimpleVT();
6034 OpInfo.ConstraintVT = OpVT;
6036 // Indirect operand accesses access memory.
6037 if (OpInfo.isIndirect)
6040 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6041 TargetLowering::ConstraintType
6042 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6043 if (CType == TargetLowering::C_Memory) {
6051 SDValue Chain, Flag;
6053 // We won't need to flush pending loads if this asm doesn't touch
6054 // memory and is nonvolatile.
6055 if (hasMemory || IA->hasSideEffects())
6058 Chain = DAG.getRoot();
6060 // Second pass over the constraints: compute which constraint option to use
6061 // and assign registers to constraints that want a specific physreg.
6062 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6063 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6065 // If this is an output operand with a matching input operand, look up the
6066 // matching input. If their types mismatch, e.g. one is an integer, the
6067 // other is floating point, or their sizes are different, flag it as an
6069 if (OpInfo.hasMatchingInput()) {
6070 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6072 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6073 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6074 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6075 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6076 OpInfo.ConstraintVT);
6077 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6078 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6079 Input.ConstraintVT);
6080 if ((OpInfo.ConstraintVT.isInteger() !=
6081 Input.ConstraintVT.isInteger()) ||
6082 (MatchRC.second != InputRC.second)) {
6083 report_fatal_error("Unsupported asm: input constraint"
6084 " with a matching output constraint of"
6085 " incompatible type!");
6087 Input.ConstraintVT = OpInfo.ConstraintVT;
6091 // Compute the constraint code and ConstraintType to use.
6092 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6094 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6095 OpInfo.Type == InlineAsm::isClobber)
6098 // If this is a memory input, and if the operand is not indirect, do what we
6099 // need to to provide an address for the memory input.
6100 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6101 !OpInfo.isIndirect) {
6102 assert((OpInfo.isMultipleAlternative ||
6103 (OpInfo.Type == InlineAsm::isInput)) &&
6104 "Can only indirectify direct input operands!");
6106 // Memory operands really want the address of the value. If we don't have
6107 // an indirect input, put it in the constpool if we can, otherwise spill
6108 // it to a stack slot.
6109 // TODO: This isn't quite right. We need to handle these according to
6110 // the addressing mode that the constraint wants. Also, this may take
6111 // an additional register for the computation and we don't want that
6114 // If the operand is a float, integer, or vector constant, spill to a
6115 // constant pool entry to get its address.
6116 const Value *OpVal = OpInfo.CallOperandVal;
6117 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6118 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6119 OpInfo.CallOperand = DAG.getConstantPool(
6120 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6122 // Otherwise, create a stack slot and emit a store to it before the
6124 Type *Ty = OpVal->getType();
6125 auto &DL = DAG.getDataLayout();
6126 uint64_t TySize = DL.getTypeAllocSize(Ty);
6127 unsigned Align = DL.getPrefTypeAlignment(Ty);
6128 MachineFunction &MF = DAG.getMachineFunction();
6129 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6131 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6132 Chain = DAG.getStore(
6133 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6134 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6136 OpInfo.CallOperand = StackSlot;
6139 // There is no longer a Value* corresponding to this operand.
6140 OpInfo.CallOperandVal = nullptr;
6142 // It is now an indirect operand.
6143 OpInfo.isIndirect = true;
6146 // If this constraint is for a specific register, allocate it before
6148 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6149 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6152 // Second pass - Loop over all of the operands, assigning virtual or physregs
6153 // to register class operands.
6154 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6155 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6157 // C_Register operands have already been allocated, Other/Memory don't need
6159 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6160 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6163 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6164 std::vector<SDValue> AsmNodeOperands;
6165 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6166 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6167 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6169 // If we have a !srcloc metadata node associated with it, we want to attach
6170 // this to the ultimately generated inline asm machineinstr. To do this, we
6171 // pass in the third operand as this (potentially null) inline asm MDNode.
6172 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6173 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6175 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6176 // bits as operand 3.
6177 unsigned ExtraInfo = 0;
6178 if (IA->hasSideEffects())
6179 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6180 if (IA->isAlignStack())
6181 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6182 // Set the asm dialect.
6183 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6185 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6186 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6187 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6189 // Compute the constraint code and ConstraintType to use.
6190 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6192 // Ideally, we would only check against memory constraints. However, the
6193 // meaning of an other constraint can be target-specific and we can't easily
6194 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6195 // for other constriants as well.
6196 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6197 OpInfo.ConstraintType == TargetLowering::C_Other) {
6198 if (OpInfo.Type == InlineAsm::isInput)
6199 ExtraInfo |= InlineAsm::Extra_MayLoad;
6200 else if (OpInfo.Type == InlineAsm::isOutput)
6201 ExtraInfo |= InlineAsm::Extra_MayStore;
6202 else if (OpInfo.Type == InlineAsm::isClobber)
6203 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6207 AsmNodeOperands.push_back(DAG.getTargetConstant(
6208 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6210 // Loop over all of the inputs, copying the operand values into the
6211 // appropriate registers and processing the output regs.
6212 RegsForValue RetValRegs;
6214 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6215 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6217 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6218 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6220 switch (OpInfo.Type) {
6221 case InlineAsm::isOutput: {
6222 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6223 OpInfo.ConstraintType != TargetLowering::C_Register) {
6224 // Memory output, or 'other' output (e.g. 'X' constraint).
6225 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6227 unsigned ConstraintID =
6228 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6229 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6230 "Failed to convert memory constraint code to constraint id.");
6232 // Add information to the INLINEASM node to know about this output.
6233 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6234 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6235 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6237 AsmNodeOperands.push_back(OpInfo.CallOperand);
6241 // Otherwise, this is a register or register class output.
6243 // Copy the output from the appropriate register. Find a register that
6245 if (OpInfo.AssignedRegs.Regs.empty()) {
6246 LLVMContext &Ctx = *DAG.getContext();
6247 Ctx.emitError(CS.getInstruction(),
6248 "couldn't allocate output register for constraint '" +
6249 Twine(OpInfo.ConstraintCode) + "'");
6253 // If this is an indirect operand, store through the pointer after the
6255 if (OpInfo.isIndirect) {
6256 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6257 OpInfo.CallOperandVal));
6259 // This is the result value of the call.
6260 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6261 // Concatenate this output onto the outputs list.
6262 RetValRegs.append(OpInfo.AssignedRegs);
6265 // Add information to the INLINEASM node to know that this register is
6268 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6269 ? InlineAsm::Kind_RegDefEarlyClobber
6270 : InlineAsm::Kind_RegDef,
6271 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6274 case InlineAsm::isInput: {
6275 SDValue InOperandVal = OpInfo.CallOperand;
6277 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6278 // If this is required to match an output register we have already set,
6279 // just use its register.
6280 unsigned OperandNo = OpInfo.getMatchedOperand();
6282 // Scan until we find the definition we already emitted of this operand.
6283 // When we find it, create a RegsForValue operand.
6284 unsigned CurOp = InlineAsm::Op_FirstOperand;
6285 for (; OperandNo; --OperandNo) {
6286 // Advance to the next operand.
6288 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6289 assert((InlineAsm::isRegDefKind(OpFlag) ||
6290 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6291 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6292 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6296 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6297 if (InlineAsm::isRegDefKind(OpFlag) ||
6298 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6299 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6300 if (OpInfo.isIndirect) {
6301 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6302 LLVMContext &Ctx = *DAG.getContext();
6303 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6304 " don't know how to handle tied "
6305 "indirect register inputs");
6309 RegsForValue MatchedRegs;
6310 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6311 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6312 MatchedRegs.RegVTs.push_back(RegVT);
6313 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6314 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6316 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6317 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6319 LLVMContext &Ctx = *DAG.getContext();
6320 Ctx.emitError(CS.getInstruction(),
6321 "inline asm error: This value"
6322 " type register class is not natively supported!");
6326 SDLoc dl = getCurSDLoc();
6327 // Use the produced MatchedRegs object to
6328 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6329 Chain, &Flag, CS.getInstruction());
6330 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6331 true, OpInfo.getMatchedOperand(), dl,
6332 DAG, AsmNodeOperands);
6336 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6337 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6338 "Unexpected number of operands");
6339 // Add information to the INLINEASM node to know about this input.
6340 // See InlineAsm.h isUseOperandTiedToDef.
6341 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6342 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6343 OpInfo.getMatchedOperand());
6344 AsmNodeOperands.push_back(DAG.getTargetConstant(
6345 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6346 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6350 // Treat indirect 'X' constraint as memory.
6351 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6353 OpInfo.ConstraintType = TargetLowering::C_Memory;
6355 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6356 std::vector<SDValue> Ops;
6357 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6360 LLVMContext &Ctx = *DAG.getContext();
6361 Ctx.emitError(CS.getInstruction(),
6362 "invalid operand for inline asm constraint '" +
6363 Twine(OpInfo.ConstraintCode) + "'");
6367 // Add information to the INLINEASM node to know about this input.
6368 unsigned ResOpType =
6369 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6370 AsmNodeOperands.push_back(DAG.getTargetConstant(
6371 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6372 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6376 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6377 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6378 assert(InOperandVal.getValueType() ==
6379 TLI.getPointerTy(DAG.getDataLayout()) &&
6380 "Memory operands expect pointer values");
6382 unsigned ConstraintID =
6383 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6384 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6385 "Failed to convert memory constraint code to constraint id.");
6387 // Add information to the INLINEASM node to know about this input.
6388 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6389 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6390 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6393 AsmNodeOperands.push_back(InOperandVal);
6397 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6398 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6399 "Unknown constraint type!");
6401 // TODO: Support this.
6402 if (OpInfo.isIndirect) {
6403 LLVMContext &Ctx = *DAG.getContext();
6404 Ctx.emitError(CS.getInstruction(),
6405 "Don't know how to handle indirect register inputs yet "
6406 "for constraint '" +
6407 Twine(OpInfo.ConstraintCode) + "'");
6411 // Copy the input into the appropriate registers.
6412 if (OpInfo.AssignedRegs.Regs.empty()) {
6413 LLVMContext &Ctx = *DAG.getContext();
6414 Ctx.emitError(CS.getInstruction(),
6415 "couldn't allocate input reg for constraint '" +
6416 Twine(OpInfo.ConstraintCode) + "'");
6420 SDLoc dl = getCurSDLoc();
6422 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6423 Chain, &Flag, CS.getInstruction());
6425 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6426 dl, DAG, AsmNodeOperands);
6429 case InlineAsm::isClobber: {
6430 // Add the clobbered value to the operand list, so that the register
6431 // allocator is aware that the physreg got clobbered.
6432 if (!OpInfo.AssignedRegs.Regs.empty())
6433 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6434 false, 0, getCurSDLoc(), DAG,
6441 // Finish up input operands. Set the input chain and add the flag last.
6442 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6443 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6445 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6446 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6447 Flag = Chain.getValue(1);
6449 // If this asm returns a register value, copy the result from that register
6450 // and set it as the value of the call.
6451 if (!RetValRegs.Regs.empty()) {
6452 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6453 Chain, &Flag, CS.getInstruction());
6455 // FIXME: Why don't we do this for inline asms with MRVs?
6456 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6457 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6459 // If any of the results of the inline asm is a vector, it may have the
6460 // wrong width/num elts. This can happen for register classes that can
6461 // contain multiple different value types. The preg or vreg allocated may
6462 // not have the same VT as was expected. Convert it to the right type
6463 // with bit_convert.
6464 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6465 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6468 } else if (ResultType != Val.getValueType() &&
6469 ResultType.isInteger() && Val.getValueType().isInteger()) {
6470 // If a result value was tied to an input value, the computed result may
6471 // have a wider width than the expected result. Extract the relevant
6473 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6476 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6479 setValue(CS.getInstruction(), Val);
6480 // Don't need to use this as a chain in this case.
6481 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6485 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6487 // Process indirect outputs, first output all of the flagged copies out of
6489 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6490 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6491 const Value *Ptr = IndirectStoresToEmit[i].second;
6492 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6494 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6497 // Emit the non-flagged stores from the physregs.
6498 SmallVector<SDValue, 8> OutChains;
6499 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6500 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6501 StoresToEmit[i].first,
6502 getValue(StoresToEmit[i].second),
6503 MachinePointerInfo(StoresToEmit[i].second),
6505 OutChains.push_back(Val);
6508 if (!OutChains.empty())
6509 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6514 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6515 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6516 MVT::Other, getRoot(),
6517 getValue(I.getArgOperand(0)),
6518 DAG.getSrcValue(I.getArgOperand(0))));
6521 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6523 const DataLayout &DL = DAG.getDataLayout();
6524 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6525 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6526 DAG.getSrcValue(I.getOperand(0)),
6527 DL.getABITypeAlignment(I.getType()));
6529 DAG.setRoot(V.getValue(1));
6532 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6533 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6534 MVT::Other, getRoot(),
6535 getValue(I.getArgOperand(0)),
6536 DAG.getSrcValue(I.getArgOperand(0))));
6539 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6540 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6541 MVT::Other, getRoot(),
6542 getValue(I.getArgOperand(0)),
6543 getValue(I.getArgOperand(1)),
6544 DAG.getSrcValue(I.getArgOperand(0)),
6545 DAG.getSrcValue(I.getArgOperand(1))));
6548 /// \brief Lower an argument list according to the target calling convention.
6550 /// \return A tuple of <return-value, token-chain>
6552 /// This is a helper for lowering intrinsics that follow a target calling
6553 /// convention or require stack pointer adjustment. Only a subset of the
6554 /// intrinsic's operands need to participate in the calling convention.
6555 std::pair<SDValue, SDValue>
6556 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6557 unsigned NumArgs, SDValue Callee,
6559 MachineBasicBlock *LandingPad,
6560 bool IsPatchPoint) {
6561 TargetLowering::ArgListTy Args;
6562 Args.reserve(NumArgs);
6564 // Populate the argument list.
6565 // Attributes for args start at offset 1, after the return attribute.
6566 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6567 ArgI != ArgE; ++ArgI) {
6568 const Value *V = CS->getOperand(ArgI);
6570 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6572 TargetLowering::ArgListEntry Entry;
6573 Entry.Node = getValue(V);
6574 Entry.Ty = V->getType();
6575 Entry.setAttributes(&CS, AttrI);
6576 Args.push_back(Entry);
6579 TargetLowering::CallLoweringInfo CLI(DAG);
6580 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6581 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6582 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6584 return lowerInvokable(CLI, LandingPad);
6587 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6588 /// or patchpoint target node's operand list.
6590 /// Constants are converted to TargetConstants purely as an optimization to
6591 /// avoid constant materialization and register allocation.
6593 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6594 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6595 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6596 /// address materialization and register allocation, but may also be required
6597 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6598 /// alloca in the entry block, then the runtime may assume that the alloca's
6599 /// StackMap location can be read immediately after compilation and that the
6600 /// location is valid at any point during execution (this is similar to the
6601 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6602 /// only available in a register, then the runtime would need to trap when
6603 /// execution reaches the StackMap in order to read the alloca's location.
6604 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6605 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6606 SelectionDAGBuilder &Builder) {
6607 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6608 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6609 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6611 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6613 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6614 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6615 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6616 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6617 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6619 Ops.push_back(OpVal);
6623 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6624 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6625 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6626 // [live variables...])
6628 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6630 SDValue Chain, InFlag, Callee, NullPtr;
6631 SmallVector<SDValue, 32> Ops;
6633 SDLoc DL = getCurSDLoc();
6634 Callee = getValue(CI.getCalledValue());
6635 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6637 // The stackmap intrinsic only records the live variables (the arguemnts
6638 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6639 // intrinsic, this won't be lowered to a function call. This means we don't
6640 // have to worry about calling conventions and target specific lowering code.
6641 // Instead we perform the call lowering right here.
6643 // chain, flag = CALLSEQ_START(chain, 0)
6644 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6645 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6647 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6648 InFlag = Chain.getValue(1);
6650 // Add the <id> and <numBytes> constants.
6651 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6652 Ops.push_back(DAG.getTargetConstant(
6653 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6654 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6655 Ops.push_back(DAG.getTargetConstant(
6656 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6659 // Push live variables for the stack map.
6660 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6662 // We are not pushing any register mask info here on the operands list,
6663 // because the stackmap doesn't clobber anything.
6665 // Push the chain and the glue flag.
6666 Ops.push_back(Chain);
6667 Ops.push_back(InFlag);
6669 // Create the STACKMAP node.
6670 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6671 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6672 Chain = SDValue(SM, 0);
6673 InFlag = Chain.getValue(1);
6675 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6677 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6679 // Set the root to the target-lowered call chain.
6682 // Inform the Frame Information that we have a stackmap in this function.
6683 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6686 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6687 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6688 MachineBasicBlock *LandingPad) {
6689 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6694 // [live variables...])
6696 CallingConv::ID CC = CS.getCallingConv();
6697 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6698 bool HasDef = !CS->getType()->isVoidTy();
6699 SDLoc dl = getCurSDLoc();
6700 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6702 // Handle immediate and symbolic callees.
6703 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6704 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6706 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6707 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6708 SDLoc(SymbolicCallee),
6709 SymbolicCallee->getValueType(0));
6711 // Get the real number of arguments participating in the call <numArgs>
6712 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6713 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6715 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6716 // Intrinsics include all meta-operands up to but not including CC.
6717 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6718 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6719 "Not enough arguments provided to the patchpoint intrinsic");
6721 // For AnyRegCC the arguments are lowered later on manually.
6722 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6724 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6725 std::pair<SDValue, SDValue> Result =
6726 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6729 SDNode *CallEnd = Result.second.getNode();
6730 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6731 CallEnd = CallEnd->getOperand(0).getNode();
6733 /// Get a call instruction from the call sequence chain.
6734 /// Tail calls are not allowed.
6735 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6736 "Expected a callseq node.");
6737 SDNode *Call = CallEnd->getOperand(0).getNode();
6738 bool HasGlue = Call->getGluedNode();
6740 // Replace the target specific call node with the patchable intrinsic.
6741 SmallVector<SDValue, 8> Ops;
6743 // Add the <id> and <numBytes> constants.
6744 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6745 Ops.push_back(DAG.getTargetConstant(
6746 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6747 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6748 Ops.push_back(DAG.getTargetConstant(
6749 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6753 Ops.push_back(Callee);
6755 // Adjust <numArgs> to account for any arguments that have been passed on the
6757 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6758 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6759 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6760 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6762 // Add the calling convention
6763 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6765 // Add the arguments we omitted previously. The register allocator should
6766 // place these in any free register.
6768 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6769 Ops.push_back(getValue(CS.getArgument(i)));
6771 // Push the arguments from the call instruction up to the register mask.
6772 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6773 Ops.append(Call->op_begin() + 2, e);
6775 // Push live variables for the stack map.
6776 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6778 // Push the register mask info.
6780 Ops.push_back(*(Call->op_end()-2));
6782 Ops.push_back(*(Call->op_end()-1));
6784 // Push the chain (this is originally the first operand of the call, but
6785 // becomes now the last or second to last operand).
6786 Ops.push_back(*(Call->op_begin()));
6788 // Push the glue flag (last operand).
6790 Ops.push_back(*(Call->op_end()-1));
6793 if (IsAnyRegCC && HasDef) {
6794 // Create the return types based on the intrinsic definition
6795 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6796 SmallVector<EVT, 3> ValueVTs;
6797 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6798 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6800 // There is always a chain and a glue type at the end
6801 ValueVTs.push_back(MVT::Other);
6802 ValueVTs.push_back(MVT::Glue);
6803 NodeTys = DAG.getVTList(ValueVTs);
6805 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6807 // Replace the target specific call node with a PATCHPOINT node.
6808 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6811 // Update the NodeMap.
6814 setValue(CS.getInstruction(), SDValue(MN, 0));
6816 setValue(CS.getInstruction(), Result.first);
6819 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6820 // call sequence. Furthermore the location of the chain and glue can change
6821 // when the AnyReg calling convention is used and the intrinsic returns a
6823 if (IsAnyRegCC && HasDef) {
6824 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6825 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6826 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6828 DAG.ReplaceAllUsesWith(Call, MN);
6829 DAG.DeleteNode(Call);
6831 // Inform the Frame Information that we have a patchpoint in this function.
6832 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6835 /// Returns an AttributeSet representing the attributes applied to the return
6836 /// value of the given call.
6837 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6838 SmallVector<Attribute::AttrKind, 2> Attrs;
6840 Attrs.push_back(Attribute::SExt);
6842 Attrs.push_back(Attribute::ZExt);
6844 Attrs.push_back(Attribute::InReg);
6846 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6850 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6851 /// implementation, which just calls LowerCall.
6852 /// FIXME: When all targets are
6853 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6854 std::pair<SDValue, SDValue>
6855 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6856 // Handle the incoming return values from the call.
6858 Type *OrigRetTy = CLI.RetTy;
6859 SmallVector<EVT, 4> RetTys;
6860 SmallVector<uint64_t, 4> Offsets;
6861 auto &DL = CLI.DAG.getDataLayout();
6862 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6864 SmallVector<ISD::OutputArg, 4> Outs;
6865 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6867 bool CanLowerReturn =
6868 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6869 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6871 SDValue DemoteStackSlot;
6872 int DemoteStackIdx = -100;
6873 if (!CanLowerReturn) {
6874 // FIXME: equivalent assert?
6875 // assert(!CS.hasInAllocaArgument() &&
6876 // "sret demotion is incompatible with inalloca");
6877 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6878 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6879 MachineFunction &MF = CLI.DAG.getMachineFunction();
6880 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6881 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6883 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6885 Entry.Node = DemoteStackSlot;
6886 Entry.Ty = StackSlotPtrType;
6887 Entry.isSExt = false;
6888 Entry.isZExt = false;
6889 Entry.isInReg = false;
6890 Entry.isSRet = true;
6891 Entry.isNest = false;
6892 Entry.isByVal = false;
6893 Entry.isReturned = false;
6894 Entry.Alignment = Align;
6895 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6896 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6898 // sret demotion isn't compatible with tail-calls, since the sret argument
6899 // points into the callers stack frame.
6900 CLI.IsTailCall = false;
6902 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6904 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6905 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6906 for (unsigned i = 0; i != NumRegs; ++i) {
6907 ISD::InputArg MyFlags;
6908 MyFlags.VT = RegisterVT;
6910 MyFlags.Used = CLI.IsReturnValueUsed;
6912 MyFlags.Flags.setSExt();
6914 MyFlags.Flags.setZExt();
6916 MyFlags.Flags.setInReg();
6917 CLI.Ins.push_back(MyFlags);
6922 // Handle all of the outgoing arguments.
6924 CLI.OutVals.clear();
6925 ArgListTy &Args = CLI.getArgs();
6926 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6927 SmallVector<EVT, 4> ValueVTs;
6928 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6929 Type *FinalType = Args[i].Ty;
6930 if (Args[i].isByVal)
6931 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6932 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6933 FinalType, CLI.CallConv, CLI.IsVarArg);
6934 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6936 EVT VT = ValueVTs[Value];
6937 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6938 SDValue Op = SDValue(Args[i].Node.getNode(),
6939 Args[i].Node.getResNo() + Value);
6940 ISD::ArgFlagsTy Flags;
6941 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6947 if (Args[i].isInReg)
6951 if (Args[i].isByVal)
6953 if (Args[i].isInAlloca) {
6954 Flags.setInAlloca();
6955 // Set the byval flag for CCAssignFn callbacks that don't know about
6956 // inalloca. This way we can know how many bytes we should've allocated
6957 // and how many bytes a callee cleanup function will pop. If we port
6958 // inalloca to more targets, we'll have to add custom inalloca handling
6959 // in the various CC lowering callbacks.
6962 if (Args[i].isByVal || Args[i].isInAlloca) {
6963 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6964 Type *ElementTy = Ty->getElementType();
6965 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6966 // For ByVal, alignment should come from FE. BE will guess if this
6967 // info is not there but there are cases it cannot get right.
6968 unsigned FrameAlign;
6969 if (Args[i].Alignment)
6970 FrameAlign = Args[i].Alignment;
6972 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6973 Flags.setByValAlign(FrameAlign);
6978 Flags.setInConsecutiveRegs();
6979 Flags.setOrigAlign(OriginalAlignment);
6981 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6982 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6983 SmallVector<SDValue, 4> Parts(NumParts);
6984 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6987 ExtendKind = ISD::SIGN_EXTEND;
6988 else if (Args[i].isZExt)
6989 ExtendKind = ISD::ZERO_EXTEND;
6991 // Conservatively only handle 'returned' on non-vectors for now
6992 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6993 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6994 "unexpected use of 'returned'");
6995 // Before passing 'returned' to the target lowering code, ensure that
6996 // either the register MVT and the actual EVT are the same size or that
6997 // the return value and argument are extended in the same way; in these
6998 // cases it's safe to pass the argument register value unchanged as the
6999 // return register value (although it's at the target's option whether
7001 // TODO: allow code generation to take advantage of partially preserved
7002 // registers rather than clobbering the entire register when the
7003 // parameter extension method is not compatible with the return
7005 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7006 (ExtendKind != ISD::ANY_EXTEND &&
7007 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7008 Flags.setReturned();
7011 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7012 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7014 for (unsigned j = 0; j != NumParts; ++j) {
7015 // if it isn't first piece, alignment must be 1
7016 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7017 i < CLI.NumFixedArgs,
7018 i, j*Parts[j].getValueType().getStoreSize());
7019 if (NumParts > 1 && j == 0)
7020 MyFlags.Flags.setSplit();
7022 MyFlags.Flags.setOrigAlign(1);
7024 CLI.Outs.push_back(MyFlags);
7025 CLI.OutVals.push_back(Parts[j]);
7028 if (NeedsRegBlock && Value == NumValues - 1)
7029 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7033 SmallVector<SDValue, 4> InVals;
7034 CLI.Chain = LowerCall(CLI, InVals);
7036 // Verify that the target's LowerCall behaved as expected.
7037 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7038 "LowerCall didn't return a valid chain!");
7039 assert((!CLI.IsTailCall || InVals.empty()) &&
7040 "LowerCall emitted a return value for a tail call!");
7041 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7042 "LowerCall didn't emit the correct number of values!");
7044 // For a tail call, the return value is merely live-out and there aren't
7045 // any nodes in the DAG representing it. Return a special value to
7046 // indicate that a tail call has been emitted and no more Instructions
7047 // should be processed in the current block.
7048 if (CLI.IsTailCall) {
7049 CLI.DAG.setRoot(CLI.Chain);
7050 return std::make_pair(SDValue(), SDValue());
7053 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7054 assert(InVals[i].getNode() &&
7055 "LowerCall emitted a null value!");
7056 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7057 "LowerCall emitted a value with the wrong type!");
7060 SmallVector<SDValue, 4> ReturnValues;
7061 if (!CanLowerReturn) {
7062 // The instruction result is the result of loading from the
7063 // hidden sret parameter.
7064 SmallVector<EVT, 1> PVTs;
7065 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7067 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7068 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7069 EVT PtrVT = PVTs[0];
7071 unsigned NumValues = RetTys.size();
7072 ReturnValues.resize(NumValues);
7073 SmallVector<SDValue, 4> Chains(NumValues);
7075 for (unsigned i = 0; i < NumValues; ++i) {
7076 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7077 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7079 SDValue L = CLI.DAG.getLoad(
7080 RetTys[i], CLI.DL, CLI.Chain, Add,
7081 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7082 DemoteStackIdx, Offsets[i]),
7083 false, false, false, 1);
7084 ReturnValues[i] = L;
7085 Chains[i] = L.getValue(1);
7088 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7090 // Collect the legal value parts into potentially illegal values
7091 // that correspond to the original function's return values.
7092 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7094 AssertOp = ISD::AssertSext;
7095 else if (CLI.RetZExt)
7096 AssertOp = ISD::AssertZext;
7097 unsigned CurReg = 0;
7098 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7100 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7101 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7103 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7104 NumRegs, RegisterVT, VT, nullptr,
7109 // For a function returning void, there is no return value. We can't create
7110 // such a node, so we just return a null return value in that case. In
7111 // that case, nothing will actually look at the value.
7112 if (ReturnValues.empty())
7113 return std::make_pair(SDValue(), CLI.Chain);
7116 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7117 CLI.DAG.getVTList(RetTys), ReturnValues);
7118 return std::make_pair(Res, CLI.Chain);
7121 void TargetLowering::LowerOperationWrapper(SDNode *N,
7122 SmallVectorImpl<SDValue> &Results,
7123 SelectionDAG &DAG) const {
7124 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7126 Results.push_back(Res);
7129 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7130 llvm_unreachable("LowerOperation not implemented for this target!");
7134 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7135 SDValue Op = getNonRegisterValue(V);
7136 assert((Op.getOpcode() != ISD::CopyFromReg ||
7137 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7138 "Copy from a reg to the same reg!");
7139 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7141 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7142 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7144 SDValue Chain = DAG.getEntryNode();
7146 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7147 FuncInfo.PreferredExtendType.end())
7149 : FuncInfo.PreferredExtendType[V];
7150 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7151 PendingExports.push_back(Chain);
7154 #include "llvm/CodeGen/SelectionDAGISel.h"
7156 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7157 /// entry block, return true. This includes arguments used by switches, since
7158 /// the switch may expand into multiple basic blocks.
7159 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7160 // With FastISel active, we may be splitting blocks, so force creation
7161 // of virtual registers for all non-dead arguments.
7163 return A->use_empty();
7165 const BasicBlock *Entry = A->getParent()->begin();
7166 for (const User *U : A->users())
7167 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7168 return false; // Use not in entry block.
7173 void SelectionDAGISel::LowerArguments(const Function &F) {
7174 SelectionDAG &DAG = SDB->DAG;
7175 SDLoc dl = SDB->getCurSDLoc();
7176 const DataLayout &DL = DAG.getDataLayout();
7177 SmallVector<ISD::InputArg, 16> Ins;
7179 if (!FuncInfo->CanLowerReturn) {
7180 // Put in an sret pointer parameter before all the other parameters.
7181 SmallVector<EVT, 1> ValueVTs;
7182 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7183 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7185 // NOTE: Assuming that a pointer will never break down to more than one VT
7187 ISD::ArgFlagsTy Flags;
7189 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7190 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7191 ISD::InputArg::NoArgIndex, 0);
7192 Ins.push_back(RetArg);
7195 // Set up the incoming argument description vector.
7197 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7198 I != E; ++I, ++Idx) {
7199 SmallVector<EVT, 4> ValueVTs;
7200 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7201 bool isArgValueUsed = !I->use_empty();
7202 unsigned PartBase = 0;
7203 Type *FinalType = I->getType();
7204 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7205 FinalType = cast<PointerType>(FinalType)->getElementType();
7206 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7207 FinalType, F.getCallingConv(), F.isVarArg());
7208 for (unsigned Value = 0, NumValues = ValueVTs.size();
7209 Value != NumValues; ++Value) {
7210 EVT VT = ValueVTs[Value];
7211 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7212 ISD::ArgFlagsTy Flags;
7213 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7215 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7217 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7219 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7221 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7223 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7225 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7226 Flags.setInAlloca();
7227 // Set the byval flag for CCAssignFn callbacks that don't know about
7228 // inalloca. This way we can know how many bytes we should've allocated
7229 // and how many bytes a callee cleanup function will pop. If we port
7230 // inalloca to more targets, we'll have to add custom inalloca handling
7231 // in the various CC lowering callbacks.
7234 if (Flags.isByVal() || Flags.isInAlloca()) {
7235 PointerType *Ty = cast<PointerType>(I->getType());
7236 Type *ElementTy = Ty->getElementType();
7237 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7238 // For ByVal, alignment should be passed from FE. BE will guess if
7239 // this info is not there but there are cases it cannot get right.
7240 unsigned FrameAlign;
7241 if (F.getParamAlignment(Idx))
7242 FrameAlign = F.getParamAlignment(Idx);
7244 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7245 Flags.setByValAlign(FrameAlign);
7247 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7250 Flags.setInConsecutiveRegs();
7251 Flags.setOrigAlign(OriginalAlignment);
7253 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7254 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7255 for (unsigned i = 0; i != NumRegs; ++i) {
7256 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7257 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7258 if (NumRegs > 1 && i == 0)
7259 MyFlags.Flags.setSplit();
7260 // if it isn't first piece, alignment must be 1
7262 MyFlags.Flags.setOrigAlign(1);
7263 Ins.push_back(MyFlags);
7265 if (NeedsRegBlock && Value == NumValues - 1)
7266 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7267 PartBase += VT.getStoreSize();
7271 // Call the target to set up the argument values.
7272 SmallVector<SDValue, 8> InVals;
7273 SDValue NewRoot = TLI->LowerFormalArguments(
7274 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7276 // Verify that the target's LowerFormalArguments behaved as expected.
7277 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7278 "LowerFormalArguments didn't return a valid chain!");
7279 assert(InVals.size() == Ins.size() &&
7280 "LowerFormalArguments didn't emit the correct number of values!");
7282 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7283 assert(InVals[i].getNode() &&
7284 "LowerFormalArguments emitted a null value!");
7285 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7286 "LowerFormalArguments emitted a value with the wrong type!");
7290 // Update the DAG with the new chain value resulting from argument lowering.
7291 DAG.setRoot(NewRoot);
7293 // Set up the argument values.
7296 if (!FuncInfo->CanLowerReturn) {
7297 // Create a virtual register for the sret pointer, and put in a copy
7298 // from the sret argument into it.
7299 SmallVector<EVT, 1> ValueVTs;
7300 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7301 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7302 MVT VT = ValueVTs[0].getSimpleVT();
7303 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7304 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7305 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7306 RegVT, VT, nullptr, AssertOp);
7308 MachineFunction& MF = SDB->DAG.getMachineFunction();
7309 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7310 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7311 FuncInfo->DemoteRegister = SRetReg;
7313 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7314 DAG.setRoot(NewRoot);
7316 // i indexes lowered arguments. Bump it past the hidden sret argument.
7317 // Idx indexes LLVM arguments. Don't touch it.
7321 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7323 SmallVector<SDValue, 4> ArgValues;
7324 SmallVector<EVT, 4> ValueVTs;
7325 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7326 unsigned NumValues = ValueVTs.size();
7328 // If this argument is unused then remember its value. It is used to generate
7329 // debugging information.
7330 if (I->use_empty() && NumValues) {
7331 SDB->setUnusedArgValue(I, InVals[i]);
7333 // Also remember any frame index for use in FastISel.
7334 if (FrameIndexSDNode *FI =
7335 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7336 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7339 for (unsigned Val = 0; Val != NumValues; ++Val) {
7340 EVT VT = ValueVTs[Val];
7341 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7342 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7344 if (!I->use_empty()) {
7345 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7346 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7347 AssertOp = ISD::AssertSext;
7348 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7349 AssertOp = ISD::AssertZext;
7351 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7352 NumParts, PartVT, VT,
7353 nullptr, AssertOp));
7359 // We don't need to do anything else for unused arguments.
7360 if (ArgValues.empty())
7363 // Note down frame index.
7364 if (FrameIndexSDNode *FI =
7365 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7366 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7368 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7369 SDB->getCurSDLoc());
7371 SDB->setValue(I, Res);
7372 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7373 if (LoadSDNode *LNode =
7374 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7375 if (FrameIndexSDNode *FI =
7376 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7377 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7380 // If this argument is live outside of the entry block, insert a copy from
7381 // wherever we got it to the vreg that other BB's will reference it as.
7382 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7383 // If we can, though, try to skip creating an unnecessary vreg.
7384 // FIXME: This isn't very clean... it would be nice to make this more
7385 // general. It's also subtly incompatible with the hacks FastISel
7387 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7388 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7389 FuncInfo->ValueMap[I] = Reg;
7393 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7394 FuncInfo->InitializeRegForValue(I);
7395 SDB->CopyToExportRegsIfNeeded(I);
7399 assert(i == InVals.size() && "Argument register count mismatch!");
7401 // Finally, if the target has anything special to do, allow it to do so.
7402 EmitFunctionEntryCode();
7405 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7406 /// ensure constants are generated when needed. Remember the virtual registers
7407 /// that need to be added to the Machine PHI nodes as input. We cannot just
7408 /// directly add them, because expansion might result in multiple MBB's for one
7409 /// BB. As such, the start of the BB might correspond to a different MBB than
7413 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7414 const TerminatorInst *TI = LLVMBB->getTerminator();
7416 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7418 // Check PHI nodes in successors that expect a value to be available from this
7420 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7421 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7422 if (!isa<PHINode>(SuccBB->begin())) continue;
7423 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7425 // If this terminator has multiple identical successors (common for
7426 // switches), only handle each succ once.
7427 if (!SuccsHandled.insert(SuccMBB).second)
7430 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7432 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7433 // nodes and Machine PHI nodes, but the incoming operands have not been
7435 for (BasicBlock::const_iterator I = SuccBB->begin();
7436 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7437 // Ignore dead phi's.
7438 if (PN->use_empty()) continue;
7441 if (PN->getType()->isEmptyTy())
7445 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7447 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7448 unsigned &RegOut = ConstantsOut[C];
7450 RegOut = FuncInfo.CreateRegs(C->getType());
7451 CopyValueToVirtualRegister(C, RegOut);
7455 DenseMap<const Value *, unsigned>::iterator I =
7456 FuncInfo.ValueMap.find(PHIOp);
7457 if (I != FuncInfo.ValueMap.end())
7460 assert(isa<AllocaInst>(PHIOp) &&
7461 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7462 "Didn't codegen value into a register!??");
7463 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7464 CopyValueToVirtualRegister(PHIOp, Reg);
7468 // Remember that this register needs to added to the machine PHI node as
7469 // the input for this MBB.
7470 SmallVector<EVT, 4> ValueVTs;
7471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7472 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7473 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7474 EVT VT = ValueVTs[vti];
7475 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7476 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7477 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7478 Reg += NumRegisters;
7483 ConstantsOut.clear();
7486 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7489 SelectionDAGBuilder::StackProtectorDescriptor::
7490 AddSuccessorMBB(const BasicBlock *BB,
7491 MachineBasicBlock *ParentMBB,
7493 MachineBasicBlock *SuccMBB) {
7494 // If SuccBB has not been created yet, create it.
7496 MachineFunction *MF = ParentMBB->getParent();
7497 MachineFunction::iterator BBI = ParentMBB;
7498 SuccMBB = MF->CreateMachineBasicBlock(BB);
7499 MF->insert(++BBI, SuccMBB);
7501 // Add it as a successor of ParentMBB.
7502 ParentMBB->addSuccessor(
7503 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7507 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7508 MachineFunction::iterator I = MBB;
7509 if (++I == FuncInfo.MF->end())
7514 /// During lowering new call nodes can be created (such as memset, etc.).
7515 /// Those will become new roots of the current DAG, but complications arise
7516 /// when they are tail calls. In such cases, the call lowering will update
7517 /// the root, but the builder still needs to know that a tail call has been
7518 /// lowered in order to avoid generating an additional return.
7519 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7520 // If the node is null, we do have a tail call.
7521 if (MaybeTC.getNode() != nullptr)
7522 DAG.setRoot(MaybeTC);
7527 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7528 unsigned *TotalCases, unsigned First,
7530 assert(Last >= First);
7531 assert(TotalCases[Last] >= TotalCases[First]);
7533 APInt LowCase = Clusters[First].Low->getValue();
7534 APInt HighCase = Clusters[Last].High->getValue();
7535 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7537 // FIXME: A range of consecutive cases has 100% density, but only requires one
7538 // comparison to lower. We should discriminate against such consecutive ranges
7541 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7542 uint64_t Range = Diff + 1;
7545 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7547 assert(NumCases < UINT64_MAX / 100);
7548 assert(Range >= NumCases);
7550 return NumCases * 100 >= Range * MinJumpTableDensity;
7553 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7554 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7555 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7558 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7559 unsigned First, unsigned Last,
7560 const SwitchInst *SI,
7561 MachineBasicBlock *DefaultMBB,
7562 CaseCluster &JTCluster) {
7563 assert(First <= Last);
7565 uint32_t Weight = 0;
7566 unsigned NumCmps = 0;
7567 std::vector<MachineBasicBlock*> Table;
7568 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7569 for (unsigned I = First; I <= Last; ++I) {
7570 assert(Clusters[I].Kind == CC_Range);
7571 Weight += Clusters[I].Weight;
7572 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7573 APInt Low = Clusters[I].Low->getValue();
7574 APInt High = Clusters[I].High->getValue();
7575 NumCmps += (Low == High) ? 1 : 2;
7577 // Fill the gap between this and the previous cluster.
7578 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7579 assert(PreviousHigh.slt(Low));
7580 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7581 for (uint64_t J = 0; J < Gap; J++)
7582 Table.push_back(DefaultMBB);
7584 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7585 for (uint64_t J = 0; J < ClusterSize; ++J)
7586 Table.push_back(Clusters[I].MBB);
7587 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7590 unsigned NumDests = JTWeights.size();
7591 if (isSuitableForBitTests(NumDests, NumCmps,
7592 Clusters[First].Low->getValue(),
7593 Clusters[Last].High->getValue())) {
7594 // Clusters[First..Last] should be lowered as bit tests instead.
7598 // Create the MBB that will load from and jump through the table.
7599 // Note: We create it here, but it's not inserted into the function yet.
7600 MachineFunction *CurMF = FuncInfo.MF;
7601 MachineBasicBlock *JumpTableMBB =
7602 CurMF->CreateMachineBasicBlock(SI->getParent());
7604 // Add successors. Note: use table order for determinism.
7605 SmallPtrSet<MachineBasicBlock *, 8> Done;
7606 for (MachineBasicBlock *Succ : Table) {
7607 if (Done.count(Succ))
7609 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7614 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7615 ->createJumpTableIndex(Table);
7617 // Set up the jump table info.
7618 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7619 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7620 Clusters[Last].High->getValue(), SI->getCondition(),
7622 JTCases.emplace_back(std::move(JTH), std::move(JT));
7624 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7625 JTCases.size() - 1, Weight);
7629 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7630 const SwitchInst *SI,
7631 MachineBasicBlock *DefaultMBB) {
7633 // Clusters must be non-empty, sorted, and only contain Range clusters.
7634 assert(!Clusters.empty());
7635 for (CaseCluster &C : Clusters)
7636 assert(C.Kind == CC_Range);
7637 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7638 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7642 if (!areJTsAllowed(TLI))
7645 const int64_t N = Clusters.size();
7646 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7648 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7649 SmallVector<unsigned, 8> TotalCases(N);
7651 for (unsigned i = 0; i < N; ++i) {
7652 APInt Hi = Clusters[i].High->getValue();
7653 APInt Lo = Clusters[i].Low->getValue();
7654 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7656 TotalCases[i] += TotalCases[i - 1];
7659 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7660 // Cheap case: the whole range might be suitable for jump table.
7661 CaseCluster JTCluster;
7662 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7663 Clusters[0] = JTCluster;
7669 // The algorithm below is not suitable for -O0.
7670 if (TM.getOptLevel() == CodeGenOpt::None)
7673 // Split Clusters into minimum number of dense partitions. The algorithm uses
7674 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7675 // for the Case Statement'" (1994), but builds the MinPartitions array in
7676 // reverse order to make it easier to reconstruct the partitions in ascending
7677 // order. In the choice between two optimal partitionings, it picks the one
7678 // which yields more jump tables.
7680 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7681 SmallVector<unsigned, 8> MinPartitions(N);
7682 // LastElement[i] is the last element of the partition starting at i.
7683 SmallVector<unsigned, 8> LastElement(N);
7684 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7685 SmallVector<unsigned, 8> NumTables(N);
7687 // Base case: There is only one way to partition Clusters[N-1].
7688 MinPartitions[N - 1] = 1;
7689 LastElement[N - 1] = N - 1;
7690 assert(MinJumpTableSize > 1);
7691 NumTables[N - 1] = 0;
7693 // Note: loop indexes are signed to avoid underflow.
7694 for (int64_t i = N - 2; i >= 0; i--) {
7695 // Find optimal partitioning of Clusters[i..N-1].
7696 // Baseline: Put Clusters[i] into a partition on its own.
7697 MinPartitions[i] = MinPartitions[i + 1] + 1;
7699 NumTables[i] = NumTables[i + 1];
7701 // Search for a solution that results in fewer partitions.
7702 for (int64_t j = N - 1; j > i; j--) {
7703 // Try building a partition from Clusters[i..j].
7704 if (isDense(Clusters, &TotalCases[0], i, j)) {
7705 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7706 bool IsTable = j - i + 1 >= MinJumpTableSize;
7707 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7709 // If this j leads to fewer partitions, or same number of partitions
7710 // with more lookup tables, it is a better partitioning.
7711 if (NumPartitions < MinPartitions[i] ||
7712 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7713 MinPartitions[i] = NumPartitions;
7715 NumTables[i] = Tables;
7721 // Iterate over the partitions, replacing some with jump tables in-place.
7722 unsigned DstIndex = 0;
7723 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7724 Last = LastElement[First];
7725 assert(Last >= First);
7726 assert(DstIndex <= First);
7727 unsigned NumClusters = Last - First + 1;
7729 CaseCluster JTCluster;
7730 if (NumClusters >= MinJumpTableSize &&
7731 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7732 Clusters[DstIndex++] = JTCluster;
7734 for (unsigned I = First; I <= Last; ++I)
7735 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7738 Clusters.resize(DstIndex);
7741 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7742 // FIXME: Using the pointer type doesn't seem ideal.
7743 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7744 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7748 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7751 const APInt &High) {
7752 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7753 // range of cases both require only one branch to lower. Just looking at the
7754 // number of clusters and destinations should be enough to decide whether to
7757 // To lower a range with bit tests, the range must fit the bitwidth of a
7759 if (!rangeFitsInWord(Low, High))
7762 // Decide whether it's profitable to lower this range with bit tests. Each
7763 // destination requires a bit test and branch, and there is an overall range
7764 // check branch. For a small number of clusters, separate comparisons might be
7765 // cheaper, and for many destinations, splitting the range might be better.
7766 return (NumDests == 1 && NumCmps >= 3) ||
7767 (NumDests == 2 && NumCmps >= 5) ||
7768 (NumDests == 3 && NumCmps >= 6);
7771 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7772 unsigned First, unsigned Last,
7773 const SwitchInst *SI,
7774 CaseCluster &BTCluster) {
7775 assert(First <= Last);
7779 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7780 unsigned NumCmps = 0;
7781 for (int64_t I = First; I <= Last; ++I) {
7782 assert(Clusters[I].Kind == CC_Range);
7783 Dests.set(Clusters[I].MBB->getNumber());
7784 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7786 unsigned NumDests = Dests.count();
7788 APInt Low = Clusters[First].Low->getValue();
7789 APInt High = Clusters[Last].High->getValue();
7790 assert(Low.slt(High));
7792 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7798 const int BitWidth = DAG.getTargetLoweringInfo()
7799 .getPointerTy(DAG.getDataLayout())
7801 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7803 // Check if the clusters cover a contiguous range such that no value in the
7804 // range will jump to the default statement.
7805 bool ContiguousRange = true;
7806 for (int64_t I = First + 1; I <= Last; ++I) {
7807 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7808 ContiguousRange = false;
7813 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7814 // Optimize the case where all the case values fit in a word without having
7815 // to subtract minValue. In this case, we can optimize away the subtraction.
7816 LowBound = APInt::getNullValue(Low.getBitWidth());
7818 ContiguousRange = false;
7821 CmpRange = High - Low;
7825 uint32_t TotalWeight = 0;
7826 for (unsigned i = First; i <= Last; ++i) {
7827 // Find the CaseBits for this destination.
7829 for (j = 0; j < CBV.size(); ++j)
7830 if (CBV[j].BB == Clusters[i].MBB)
7832 if (j == CBV.size())
7833 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7834 CaseBits *CB = &CBV[j];
7836 // Update Mask, Bits and ExtraWeight.
7837 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7838 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7839 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7840 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7841 CB->Bits += Hi - Lo + 1;
7842 CB->ExtraWeight += Clusters[i].Weight;
7843 TotalWeight += Clusters[i].Weight;
7844 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7848 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7849 // Sort by weight first, number of bits second.
7850 if (a.ExtraWeight != b.ExtraWeight)
7851 return a.ExtraWeight > b.ExtraWeight;
7852 return a.Bits > b.Bits;
7855 for (auto &CB : CBV) {
7856 MachineBasicBlock *BitTestBB =
7857 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7858 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7860 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7861 SI->getCondition(), -1U, MVT::Other, false,
7862 ContiguousRange, nullptr, nullptr, std::move(BTI),
7865 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7866 BitTestCases.size() - 1, TotalWeight);
7870 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7871 const SwitchInst *SI) {
7872 // Partition Clusters into as few subsets as possible, where each subset has a
7873 // range that fits in a machine word and has <= 3 unique destinations.
7876 // Clusters must be sorted and contain Range or JumpTable clusters.
7877 assert(!Clusters.empty());
7878 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7879 for (const CaseCluster &C : Clusters)
7880 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7881 for (unsigned i = 1; i < Clusters.size(); ++i)
7882 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7885 // The algorithm below is not suitable for -O0.
7886 if (TM.getOptLevel() == CodeGenOpt::None)
7889 // If target does not have legal shift left, do not emit bit tests at all.
7890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7891 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7892 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7895 int BitWidth = PTy.getSizeInBits();
7896 const int64_t N = Clusters.size();
7898 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7899 SmallVector<unsigned, 8> MinPartitions(N);
7900 // LastElement[i] is the last element of the partition starting at i.
7901 SmallVector<unsigned, 8> LastElement(N);
7903 // FIXME: This might not be the best algorithm for finding bit test clusters.
7905 // Base case: There is only one way to partition Clusters[N-1].
7906 MinPartitions[N - 1] = 1;
7907 LastElement[N - 1] = N - 1;
7909 // Note: loop indexes are signed to avoid underflow.
7910 for (int64_t i = N - 2; i >= 0; --i) {
7911 // Find optimal partitioning of Clusters[i..N-1].
7912 // Baseline: Put Clusters[i] into a partition on its own.
7913 MinPartitions[i] = MinPartitions[i + 1] + 1;
7916 // Search for a solution that results in fewer partitions.
7917 // Note: the search is limited by BitWidth, reducing time complexity.
7918 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7919 // Try building a partition from Clusters[i..j].
7922 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7923 Clusters[j].High->getValue()))
7926 // Check nbr of destinations and cluster types.
7927 // FIXME: This works, but doesn't seem very efficient.
7928 bool RangesOnly = true;
7929 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7930 for (int64_t k = i; k <= j; k++) {
7931 if (Clusters[k].Kind != CC_Range) {
7935 Dests.set(Clusters[k].MBB->getNumber());
7937 if (!RangesOnly || Dests.count() > 3)
7940 // Check if it's a better partition.
7941 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7942 if (NumPartitions < MinPartitions[i]) {
7943 // Found a better partition.
7944 MinPartitions[i] = NumPartitions;
7950 // Iterate over the partitions, replacing with bit-test clusters in-place.
7951 unsigned DstIndex = 0;
7952 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7953 Last = LastElement[First];
7954 assert(First <= Last);
7955 assert(DstIndex <= First);
7957 CaseCluster BitTestCluster;
7958 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7959 Clusters[DstIndex++] = BitTestCluster;
7961 size_t NumClusters = Last - First + 1;
7962 std::memmove(&Clusters[DstIndex], &Clusters[First],
7963 sizeof(Clusters[0]) * NumClusters);
7964 DstIndex += NumClusters;
7967 Clusters.resize(DstIndex);
7970 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7971 MachineBasicBlock *SwitchMBB,
7972 MachineBasicBlock *DefaultMBB) {
7973 MachineFunction *CurMF = FuncInfo.MF;
7974 MachineBasicBlock *NextMBB = nullptr;
7975 MachineFunction::iterator BBI = W.MBB;
7976 if (++BBI != FuncInfo.MF->end())
7979 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7981 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7983 if (Size == 2 && W.MBB == SwitchMBB) {
7984 // If any two of the cases has the same destination, and if one value
7985 // is the same as the other, but has one bit unset that the other has set,
7986 // use bit manipulation to do two compares at once. For example:
7987 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7988 // TODO: This could be extended to merge any 2 cases in switches with 3
7990 // TODO: Handle cases where W.CaseBB != SwitchBB.
7991 CaseCluster &Small = *W.FirstCluster;
7992 CaseCluster &Big = *W.LastCluster;
7994 if (Small.Low == Small.High && Big.Low == Big.High &&
7995 Small.MBB == Big.MBB) {
7996 const APInt &SmallValue = Small.Low->getValue();
7997 const APInt &BigValue = Big.Low->getValue();
7999 // Check that there is only one bit different.
8000 APInt CommonBit = BigValue ^ SmallValue;
8001 if (CommonBit.isPowerOf2()) {
8002 SDValue CondLHS = getValue(Cond);
8003 EVT VT = CondLHS.getValueType();
8004 SDLoc DL = getCurSDLoc();
8006 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8007 DAG.getConstant(CommonBit, DL, VT));
8008 SDValue Cond = DAG.getSetCC(
8009 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8012 // Update successor info.
8013 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8014 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8015 addSuccessorWithWeight(
8016 SwitchMBB, DefaultMBB,
8017 // The default destination is the first successor in IR.
8018 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8021 // Insert the true branch.
8023 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8024 DAG.getBasicBlock(Small.MBB));
8025 // Insert the false branch.
8026 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8027 DAG.getBasicBlock(DefaultMBB));
8029 DAG.setRoot(BrCond);
8035 if (TM.getOptLevel() != CodeGenOpt::None) {
8036 // Order cases by weight so the most likely case will be checked first.
8037 std::sort(W.FirstCluster, W.LastCluster + 1,
8038 [](const CaseCluster &a, const CaseCluster &b) {
8039 return a.Weight > b.Weight;
8042 // Rearrange the case blocks so that the last one falls through if possible
8043 // without without changing the order of weights.
8044 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8046 if (I->Weight > W.LastCluster->Weight)
8048 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8049 std::swap(*I, *W.LastCluster);
8055 // Compute total weight.
8056 uint32_t DefaultWeight = W.DefaultWeight;
8057 uint32_t UnhandledWeights = DefaultWeight;
8058 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8059 UnhandledWeights += I->Weight;
8060 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8063 MachineBasicBlock *CurMBB = W.MBB;
8064 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8065 MachineBasicBlock *Fallthrough;
8066 if (I == W.LastCluster) {
8067 // For the last cluster, fall through to the default destination.
8068 Fallthrough = DefaultMBB;
8070 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8071 CurMF->insert(BBI, Fallthrough);
8072 // Put Cond in a virtual register to make it available from the new blocks.
8073 ExportFromCurrentBlock(Cond);
8075 UnhandledWeights -= I->Weight;
8078 case CC_JumpTable: {
8079 // FIXME: Optimize away range check based on pivot comparisons.
8080 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8081 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8083 // The jump block hasn't been inserted yet; insert it here.
8084 MachineBasicBlock *JumpMBB = JT->MBB;
8085 CurMF->insert(BBI, JumpMBB);
8087 uint32_t JumpWeight = I->Weight;
8088 uint32_t FallthroughWeight = UnhandledWeights;
8090 // If Fallthrough is a target of the jump table, we evenly distribute
8091 // the weight on the edge to Fallthrough to successors of CurMBB.
8092 // Also update the weight on the edge from JumpMBB to Fallthrough.
8093 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8094 SE = JumpMBB->succ_end();
8096 if (*SI == Fallthrough) {
8097 JumpWeight += DefaultWeight / 2;
8098 FallthroughWeight -= DefaultWeight / 2;
8099 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8104 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8105 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8107 // The jump table header will be inserted in our current block, do the
8108 // range check, and fall through to our fallthrough block.
8109 JTH->HeaderBB = CurMBB;
8110 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8112 // If we're in the right place, emit the jump table header right now.
8113 if (CurMBB == SwitchMBB) {
8114 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8115 JTH->Emitted = true;
8120 // FIXME: Optimize away range check based on pivot comparisons.
8121 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8123 // The bit test blocks haven't been inserted yet; insert them here.
8124 for (BitTestCase &BTC : BTB->Cases)
8125 CurMF->insert(BBI, BTC.ThisBB);
8127 // Fill in fields of the BitTestBlock.
8128 BTB->Parent = CurMBB;
8129 BTB->Default = Fallthrough;
8131 BTB->DefaultWeight = UnhandledWeights;
8132 // If the cases in bit test don't form a contiguous range, we evenly
8133 // distribute the weight on the edge to Fallthrough to two successors
8135 if (!BTB->ContiguousRange) {
8136 BTB->Weight += DefaultWeight / 2;
8137 BTB->DefaultWeight -= DefaultWeight / 2;
8140 // If we're in the right place, emit the bit test header right now.
8141 if (CurMBB == SwitchMBB) {
8142 visitBitTestHeader(*BTB, SwitchMBB);
8143 BTB->Emitted = true;
8148 const Value *RHS, *LHS, *MHS;
8150 if (I->Low == I->High) {
8151 // Check Cond == I->Low.
8157 // Check I->Low <= Cond <= I->High.
8164 // The false weight is the sum of all unhandled cases.
8165 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8168 if (CurMBB == SwitchMBB)
8169 visitSwitchCase(CB, SwitchMBB);
8171 SwitchCases.push_back(CB);
8176 CurMBB = Fallthrough;
8180 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8181 CaseClusterIt First,
8182 CaseClusterIt Last) {
8183 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8184 if (X.Weight != CC.Weight)
8185 return X.Weight > CC.Weight;
8187 // Ties are broken by comparing the case value.
8188 return X.Low->getValue().slt(CC.Low->getValue());
8192 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8193 const SwitchWorkListItem &W,
8195 MachineBasicBlock *SwitchMBB) {
8196 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8197 "Clusters not sorted?");
8199 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8201 // Balance the tree based on branch weights to create a near-optimal (in terms
8202 // of search time given key frequency) binary search tree. See e.g. Kurt
8203 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8204 CaseClusterIt LastLeft = W.FirstCluster;
8205 CaseClusterIt FirstRight = W.LastCluster;
8206 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8207 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8209 // Move LastLeft and FirstRight towards each other from opposite directions to
8210 // find a partitioning of the clusters which balances the weight on both
8211 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8212 // taken to ensure 0-weight nodes are distributed evenly.
8214 while (LastLeft + 1 < FirstRight) {
8215 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8216 LeftWeight += (++LastLeft)->Weight;
8218 RightWeight += (--FirstRight)->Weight;
8223 // Our binary search tree differs from a typical BST in that ours can have up
8224 // to three values in each leaf. The pivot selection above doesn't take that
8225 // into account, which means the tree might require more nodes and be less
8226 // efficient. We compensate for this here.
8228 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8229 unsigned NumRight = W.LastCluster - FirstRight + 1;
8231 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8232 // If one side has less than 3 clusters, and the other has more than 3,
8233 // consider taking a cluster from the other side.
8235 if (NumLeft < NumRight) {
8236 // Consider moving the first cluster on the right to the left side.
8237 CaseCluster &CC = *FirstRight;
8238 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8239 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8240 if (LeftSideRank <= RightSideRank) {
8241 // Moving the cluster to the left does not demote it.
8247 assert(NumRight < NumLeft);
8248 // Consider moving the last element on the left to the right side.
8249 CaseCluster &CC = *LastLeft;
8250 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8251 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8252 if (RightSideRank <= LeftSideRank) {
8253 // Moving the cluster to the right does not demot it.
8263 assert(LastLeft + 1 == FirstRight);
8264 assert(LastLeft >= W.FirstCluster);
8265 assert(FirstRight <= W.LastCluster);
8267 // Use the first element on the right as pivot since we will make less-than
8268 // comparisons against it.
8269 CaseClusterIt PivotCluster = FirstRight;
8270 assert(PivotCluster > W.FirstCluster);
8271 assert(PivotCluster <= W.LastCluster);
8273 CaseClusterIt FirstLeft = W.FirstCluster;
8274 CaseClusterIt LastRight = W.LastCluster;
8276 const ConstantInt *Pivot = PivotCluster->Low;
8278 // New blocks will be inserted immediately after the current one.
8279 MachineFunction::iterator BBI = W.MBB;
8282 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8283 // we can branch to its destination directly if it's squeezed exactly in
8284 // between the known lower bound and Pivot - 1.
8285 MachineBasicBlock *LeftMBB;
8286 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8287 FirstLeft->Low == W.GE &&
8288 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8289 LeftMBB = FirstLeft->MBB;
8291 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8292 FuncInfo.MF->insert(BBI, LeftMBB);
8294 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8295 // Put Cond in a virtual register to make it available from the new blocks.
8296 ExportFromCurrentBlock(Cond);
8299 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8300 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8301 // directly if RHS.High equals the current upper bound.
8302 MachineBasicBlock *RightMBB;
8303 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8304 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8305 RightMBB = FirstRight->MBB;
8307 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8308 FuncInfo.MF->insert(BBI, RightMBB);
8310 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8311 // Put Cond in a virtual register to make it available from the new blocks.
8312 ExportFromCurrentBlock(Cond);
8315 // Create the CaseBlock record that will be used to lower the branch.
8316 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8317 LeftWeight, RightWeight);
8319 if (W.MBB == SwitchMBB)
8320 visitSwitchCase(CB, SwitchMBB);
8322 SwitchCases.push_back(CB);
8325 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8326 // Extract cases from the switch.
8327 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8328 CaseClusterVector Clusters;
8329 Clusters.reserve(SI.getNumCases());
8330 for (auto I : SI.cases()) {
8331 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8332 const ConstantInt *CaseVal = I.getCaseValue();
8334 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8335 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8338 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8340 // Cluster adjacent cases with the same destination. We do this at all
8341 // optimization levels because it's cheap to do and will make codegen faster
8342 // if there are many clusters.
8343 sortAndRangeify(Clusters);
8345 if (TM.getOptLevel() != CodeGenOpt::None) {
8346 // Replace an unreachable default with the most popular destination.
8347 // FIXME: Exploit unreachable default more aggressively.
8348 bool UnreachableDefault =
8349 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8350 if (UnreachableDefault && !Clusters.empty()) {
8351 DenseMap<const BasicBlock *, unsigned> Popularity;
8352 unsigned MaxPop = 0;
8353 const BasicBlock *MaxBB = nullptr;
8354 for (auto I : SI.cases()) {
8355 const BasicBlock *BB = I.getCaseSuccessor();
8356 if (++Popularity[BB] > MaxPop) {
8357 MaxPop = Popularity[BB];
8362 assert(MaxPop > 0 && MaxBB);
8363 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8365 // Remove cases that were pointing to the destination that is now the
8367 CaseClusterVector New;
8368 New.reserve(Clusters.size());
8369 for (CaseCluster &CC : Clusters) {
8370 if (CC.MBB != DefaultMBB)
8373 Clusters = std::move(New);
8377 // If there is only the default destination, jump there directly.
8378 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8379 if (Clusters.empty()) {
8380 SwitchMBB->addSuccessor(DefaultMBB);
8381 if (DefaultMBB != NextBlock(SwitchMBB)) {
8382 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8383 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8388 findJumpTables(Clusters, &SI, DefaultMBB);
8389 findBitTestClusters(Clusters, &SI);
8392 dbgs() << "Case clusters: ";
8393 for (const CaseCluster &C : Clusters) {
8394 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8395 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8397 C.Low->getValue().print(dbgs(), true);
8398 if (C.Low != C.High) {
8400 C.High->getValue().print(dbgs(), true);
8407 assert(!Clusters.empty());
8408 SwitchWorkList WorkList;
8409 CaseClusterIt First = Clusters.begin();
8410 CaseClusterIt Last = Clusters.end() - 1;
8411 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8412 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8414 while (!WorkList.empty()) {
8415 SwitchWorkListItem W = WorkList.back();
8416 WorkList.pop_back();
8417 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8419 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8420 // For optimized builds, lower large range as a balanced binary tree.
8421 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8425 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);