1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/CRSBuilder.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static const unsigned MaxParallelChains = 64;
89 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
90 const SDValue *Parts, unsigned NumParts,
91 EVT PartVT, EVT ValueVT);
93 /// getCopyFromParts - Create a value that contains the specified legal parts
94 /// combined into the value they represent. If the parts combine to a type
95 /// larger then ValueVT then AssertOp can be used to specify whether the extra
96 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
97 /// (ISD::AssertSext).
98 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
102 if (ValueVT.isVector())
103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 assert(NumParts > 0 && "No parts to assemble!");
106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
107 SDValue Val = Parts[0];
110 // Assemble the value from multiple parts.
111 if (ValueVT.isInteger()) {
112 unsigned PartBits = PartVT.getSizeInBits();
113 unsigned ValueBits = ValueVT.getSizeInBits();
115 // Assemble the power of 2 part.
116 unsigned RoundParts = NumParts & (NumParts - 1) ?
117 1 << Log2_32(NumParts) : NumParts;
118 unsigned RoundBits = PartBits * RoundParts;
119 EVT RoundVT = RoundBits == ValueBits ?
120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
125 if (RoundParts > 2) {
126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
129 RoundParts / 2, PartVT, HalfVT);
131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
135 if (TLI.isBigEndian())
138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
140 if (RoundParts < NumParts) {
141 // Assemble the trailing non-power-of-2 part.
142 unsigned OddParts = NumParts - RoundParts;
143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
144 Hi = getCopyFromParts(DAG, DL,
145 Parts + RoundParts, OddParts, PartVT, OddVT);
147 // Combine the round and odd parts.
149 if (TLI.isBigEndian())
151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
154 DAG.getConstant(Lo.getValueType().getSizeInBits(),
155 TLI.getPointerTy()));
156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
159 } else if (PartVT.isFloatingPoint()) {
160 // FP split into multiple FP parts (for ppcf128)
161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
166 if (TLI.isBigEndian())
168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
170 // FP split into integer parts (soft fp)
171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
172 !PartVT.isVector() && "Unexpected split");
173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
178 // There is now one part, held in Val. Correct it to match ValueVT.
179 PartVT = Val.getValueType();
181 if (PartVT == ValueVT)
184 if (PartVT.isInteger() && ValueVT.isInteger()) {
185 if (ValueVT.bitsLT(PartVT)) {
186 // For a truncate, see if we have any information to
187 // indicate whether the truncated bits will always be
188 // zero or sign-extension.
189 if (AssertOp != ISD::DELETED_NODE)
190 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
191 DAG.getValueType(ValueVT));
192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
198 // FP_ROUND's are always exact here.
199 if (ValueVT.bitsLT(Val.getValueType()))
200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
201 DAG.getTargetConstant(1, TLI.getPointerTy()));
203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
209 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
357 ValueVT.isInteger() &&
358 "Unknown mismatch!");
359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 if (PartVT == MVT::x86mmx)
362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
364 } else if (PartBits == ValueVT.getSizeInBits()) {
365 // Different types of the same size.
366 assert(NumParts == 1 && PartVT != ValueVT);
367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
369 // If the parts cover less bits than value has, truncate the value.
370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
371 ValueVT.isInteger() &&
372 "Unknown mismatch!");
373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
375 if (PartVT == MVT::x86mmx)
376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 // The value may have changed - recompute ValueVT.
380 ValueVT = Val.getValueType();
381 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
382 "Failed to tile the value with PartVT!");
385 assert(PartVT == ValueVT && "Type conversion failed!");
390 // Expand the value into multiple parts.
391 if (NumParts & (NumParts - 1)) {
392 // The number of parts is not a power of 2. Split off and copy the tail.
393 assert(PartVT.isInteger() && ValueVT.isInteger() &&
394 "Do not know what to expand to!");
395 unsigned RoundParts = 1 << Log2_32(NumParts);
396 unsigned RoundBits = RoundParts * PartBits;
397 unsigned OddParts = NumParts - RoundParts;
398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
399 DAG.getIntPtrConstant(RoundBits));
400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
402 if (TLI.isBigEndian())
403 // The odd parts were reversed by getCopyToParts - unreverse them.
404 std::reverse(Parts + RoundParts, Parts + NumParts);
406 NumParts = RoundParts;
407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
411 // The number of parts is a power of 2. Repeatedly bisect the value using
413 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
414 EVT::getIntegerVT(*DAG.getContext(),
415 ValueVT.getSizeInBits()),
418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
419 for (unsigned i = 0; i < NumParts; i += StepSize) {
420 unsigned ThisBits = StepSize * PartBits / 2;
421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
422 SDValue &Part0 = Parts[i];
423 SDValue &Part1 = Parts[i+StepSize/2];
425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
426 ThisVT, Part0, DAG.getIntPtrConstant(1));
427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
428 ThisVT, Part0, DAG.getIntPtrConstant(0));
430 if (ThisBits == PartBits && ThisVT != PartVT) {
431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
437 if (TLI.isBigEndian())
438 std::reverse(Parts, Parts + OrigNumParts);
442 /// getCopyToPartsVector - Create a series of nodes that contain the specified
443 /// value split into legal parts.
444 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
445 SDValue Val, SDValue *Parts, unsigned NumParts,
447 EVT ValueVT = Val.getValueType();
448 assert(ValueVT.isVector() && "Not a vector");
449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
452 if (PartVT == ValueVT) {
454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
455 // Bitconvert vector->vector case.
456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
457 } else if (PartVT.isVector() &&
458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
460 EVT ElementVT = PartVT.getVectorElementType();
461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
463 SmallVector<SDValue, 16> Ops;
464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
466 ElementVT, Val, DAG.getIntPtrConstant(i)));
468 for (unsigned i = ValueVT.getVectorNumElements(),
469 e = PartVT.getVectorNumElements(); i != e; ++i)
470 Ops.push_back(DAG.getUNDEF(ElementVT));
472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
474 // FIXME: Use CONCAT for 2x -> 4x.
476 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
478 } else if (PartVT.isVector() &&
479 PartVT.getVectorElementType().bitsGE(
480 ValueVT.getVectorElementType()) &&
481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
483 // Promoted vector extract
484 bool Smaller = PartVT.bitsLE(ValueVT);
485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
488 // Vector -> scalar conversion.
489 assert(ValueVT.getVectorNumElements() == 1 &&
490 "Only trivial vector-to-scalar conversions should get here!");
491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 PartVT, Val, DAG.getIntPtrConstant(0));
494 bool Smaller = ValueVT.bitsLE(PartVT);
495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
503 // Handle a multi-element vector.
504 EVT IntermediateVT, RegisterVT;
505 unsigned NumIntermediates;
506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
508 NumIntermediates, RegisterVT);
509 unsigned NumElements = ValueVT.getVectorNumElements();
511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
512 NumParts = NumRegs; // Silence a compiler warning.
513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
515 // Split the vector into intermediate operands.
516 SmallVector<SDValue, 8> Ops(NumIntermediates);
517 for (unsigned i = 0; i != NumIntermediates; ++i) {
518 if (IntermediateVT.isVector())
519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 IntermediateVT, Val, DAG.getIntPtrConstant(i));
527 // Split the intermediate operands into legal parts.
528 if (NumParts == NumIntermediates) {
529 // If the register was not expanded, promote or copy the value,
531 for (unsigned i = 0; i != NumParts; ++i)
532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
533 } else if (NumParts > 0) {
534 // If the intermediate type was expanded, split each the value into
536 assert(NumParts % NumIntermediates == 0 &&
537 "Must expand into a divisible number of parts!");
538 unsigned Factor = NumParts / NumIntermediates;
539 for (unsigned i = 0; i != NumIntermediates; ++i)
540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
548 /// RegsForValue - This struct represents the registers (physical or virtual)
549 /// that a particular set of values is assigned, and the type information
550 /// about the value. The most common situation is to represent one value at a
551 /// time, but struct or array values are handled element-wise as multiple
552 /// values. The splitting of aggregates is performed recursively, so that we
553 /// never have aggregate-typed registers. The values at this point do not
554 /// necessarily have legal types, so each value may require one or more
555 /// registers of some legal type.
557 struct RegsForValue {
558 /// ValueVTs - The value types of the values, which may not be legal, and
559 /// may need be promoted or synthesized from one or more registers.
561 SmallVector<EVT, 4> ValueVTs;
563 /// RegVTs - The value types of the registers. This is the same size as
564 /// ValueVTs and it records, for each value, what the type of the assigned
565 /// register or registers are. (Individual values are never synthesized
566 /// from more than one type of register.)
568 /// With virtual registers, the contents of RegVTs is redundant with TLI's
569 /// getRegisterType member function, however when with physical registers
570 /// it is necessary to have a separate record of the types.
572 SmallVector<EVT, 4> RegVTs;
574 /// Regs - This list holds the registers assigned to the values.
575 /// Each legal or promoted value requires one register, and each
576 /// expanded value requires multiple registers.
578 SmallVector<unsigned, 4> Regs;
582 RegsForValue(const SmallVector<unsigned, 4> ®s,
583 EVT regvt, EVT valuevt)
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// areValueTypesLegal - Return true if types of all the values are legal.
602 bool areValueTypesLegal(const TargetLowering &TLI) {
603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
604 EVT RegisterVT = RegVTs[Value];
605 if (!TLI.isTypeLegal(RegisterVT))
611 /// append - Add the specified values to this one.
612 void append(const RegsForValue &RHS) {
613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
615 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
619 /// this value and returns the result as a ValueVTs value. This uses
620 /// Chain/Flag as the input and updates them for the output Chain/Flag.
621 /// If the Flag pointer is NULL, no flag is used.
622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
624 SDValue &Chain, SDValue *Flag) const;
626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
627 /// specified value into the registers specified by this object. This uses
628 /// Chain/Flag as the input and updates them for the output Chain/Flag.
629 /// If the Flag pointer is NULL, no flag is used.
630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
631 SDValue &Chain, SDValue *Flag) const;
633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
634 /// operand list. This adds the code marker, matching input operand index
635 /// (if applicable), and includes the number of values added into it.
636 void AddInlineAsmOperands(unsigned Kind,
637 bool HasMatching, unsigned MatchingIdx,
639 std::vector<SDValue> &Ops) const;
643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
644 /// this value and returns the result as a ValueVT value. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
648 FunctionLoweringInfo &FuncInfo,
650 SDValue &Chain, SDValue *Flag) const {
651 // A Value with type {} or [0 x %t] needs no registers.
652 if (ValueVTs.empty())
655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
657 // Assemble the legal parts into the final values.
658 SmallVector<SDValue, 4> Values(ValueVTs.size());
659 SmallVector<SDValue, 8> Parts;
660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
661 // Copy the legal parts from the registers.
662 EVT ValueVT = ValueVTs[Value];
663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
664 EVT RegisterVT = RegVTs[Value];
666 Parts.resize(NumRegs);
667 for (unsigned i = 0; i != NumRegs; ++i) {
670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
673 *Flag = P.getValue(2);
676 Chain = P.getValue(1);
679 // If the source register was virtual and if we know something about it,
680 // add an assert node.
681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
682 !RegisterVT.isInteger() || RegisterVT.isVector())
685 const FunctionLoweringInfo::LiveOutInfo *LOI =
686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
690 unsigned RegSize = RegisterVT.getSizeInBits();
691 unsigned NumSignBits = LOI->NumSignBits;
692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
694 // FIXME: We capture more information than the dag can represent. For
695 // now, just use the tightest assertzext/assertsext possible.
697 EVT FromVT(MVT::Other);
698 if (NumSignBits == RegSize)
699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
700 else if (NumZeroBits >= RegSize-1)
701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
702 else if (NumSignBits > RegSize-8)
703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
704 else if (NumZeroBits >= RegSize-8)
705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
706 else if (NumSignBits > RegSize-16)
707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
708 else if (NumZeroBits >= RegSize-16)
709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
710 else if (NumSignBits > RegSize-32)
711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
712 else if (NumZeroBits >= RegSize-32)
713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
717 // Add an assertion node.
718 assert(FromVT != MVT::Other);
719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
720 RegisterVT, P, DAG.getValueType(FromVT));
723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
724 NumRegs, RegisterVT, ValueVT);
729 return DAG.getNode(ISD::MERGE_VALUES, dl,
730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
731 &Values[0], ValueVTs.size());
734 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
735 /// specified value into the registers specified by this object. This uses
736 /// Chain/Flag as the input and updates them for the output Chain/Flag.
737 /// If the Flag pointer is NULL, no flag is used.
738 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
739 SDValue &Chain, SDValue *Flag) const {
740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
742 // Get the list of the values's legal parts.
743 unsigned NumRegs = Regs.size();
744 SmallVector<SDValue, 8> Parts(NumRegs);
745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
746 EVT ValueVT = ValueVTs[Value];
747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
748 EVT RegisterVT = RegVTs[Value];
750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
751 &Parts[Part], NumParts, RegisterVT);
755 // Copy the parts into the registers.
756 SmallVector<SDValue, 8> Chains(NumRegs);
757 for (unsigned i = 0; i != NumRegs; ++i) {
760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
763 *Flag = Part.getValue(1);
766 Chains[i] = Part.getValue(0);
769 if (NumRegs == 1 || Flag)
770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
771 // flagged to it. That is the CopyToReg nodes and the user are considered
772 // a single scheduling unit. If we create a TokenFactor and return it as
773 // chain, then the TokenFactor is both a predecessor (operand) of the
774 // user as well as a successor (the TF operands are flagged to the user).
775 // c1, f1 = CopyToReg
776 // c2, f2 = CopyToReg
777 // c3 = TokenFactor c1, c2
780 Chain = Chains[NumRegs-1];
782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
785 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
786 /// operand list. This adds the code marker and includes the number of
787 /// values added into it.
788 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
789 unsigned MatchingIdx,
791 std::vector<SDValue> &Ops) const {
792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
797 else if (!Regs.empty() &&
798 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
799 // Put the register class of the virtual registers in the flag word. That
800 // way, later passes can recompute register class constraints for inline
801 // assembly as well as normal instructions.
802 // Don't do this for tied operands that can use the regclass information
804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
814 EVT RegisterVT = RegVTs[Value];
815 for (unsigned i = 0; i != NumRegs; ++i) {
816 assert(Reg < Regs.size() && "Mismatch in # registers expected");
817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
822 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
823 const TargetLibraryInfo *li) {
827 TD = DAG.getTarget().getTargetData();
828 LPadToCallSiteMap.clear();
831 /// clear - Clear out the current SelectionDAG and the associated
832 /// state and prepare this SelectionDAGBuilder object to be used
833 /// for a new block. This doesn't clear out information about
834 /// additional blocks that are needed to complete switch lowering
835 /// or PHI node updating; that information is cleared out as it is
837 void SelectionDAGBuilder::clear() {
839 UnusedArgNodeMap.clear();
840 PendingLoads.clear();
841 PendingExports.clear();
842 CurDebugLoc = DebugLoc();
846 /// clearDanglingDebugInfo - Clear the dangling debug information
847 /// map. This function is seperated from the clear so that debug
848 /// information that is dangling in a basic block can be properly
849 /// resolved in a different basic block. This allows the
850 /// SelectionDAG to resolve dangling debug information attached
852 void SelectionDAGBuilder::clearDanglingDebugInfo() {
853 DanglingDebugInfoMap.clear();
856 /// getRoot - Return the current virtual root of the Selection DAG,
857 /// flushing any PendingLoad items. This must be done before emitting
858 /// a store or any other node that may need to be ordered after any
859 /// prior load instructions.
861 SDValue SelectionDAGBuilder::getRoot() {
862 if (PendingLoads.empty())
863 return DAG.getRoot();
865 if (PendingLoads.size() == 1) {
866 SDValue Root = PendingLoads[0];
868 PendingLoads.clear();
872 // Otherwise, we have to make a token factor node.
873 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
874 &PendingLoads[0], PendingLoads.size());
875 PendingLoads.clear();
880 /// getControlRoot - Similar to getRoot, but instead of flushing all the
881 /// PendingLoad items, flush all the PendingExports items. It is necessary
882 /// to do this before emitting a terminator instruction.
884 SDValue SelectionDAGBuilder::getControlRoot() {
885 SDValue Root = DAG.getRoot();
887 if (PendingExports.empty())
890 // Turn all of the CopyToReg chains into one factored node.
891 if (Root.getOpcode() != ISD::EntryToken) {
892 unsigned i = 0, e = PendingExports.size();
893 for (; i != e; ++i) {
894 assert(PendingExports[i].getNode()->getNumOperands() > 1);
895 if (PendingExports[i].getNode()->getOperand(0) == Root)
896 break; // Don't add the root if we already indirectly depend on it.
900 PendingExports.push_back(Root);
903 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
905 PendingExports.size());
906 PendingExports.clear();
911 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
912 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
913 DAG.AssignOrdering(Node, SDNodeOrder);
915 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
916 AssignOrderingToNode(Node->getOperand(I).getNode());
919 void SelectionDAGBuilder::visit(const Instruction &I) {
920 // Set up outgoing PHI node register values before emitting the terminator.
921 if (isa<TerminatorInst>(&I))
922 HandlePHINodesInSuccessorBlocks(I.getParent());
924 CurDebugLoc = I.getDebugLoc();
926 visit(I.getOpcode(), I);
928 if (!isa<TerminatorInst>(&I) && !HasTailCall)
929 CopyToExportRegsIfNeeded(&I);
931 CurDebugLoc = DebugLoc();
934 void SelectionDAGBuilder::visitPHI(const PHINode &) {
935 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
938 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
939 // Note: this doesn't use InstVisitor, because it has to work with
940 // ConstantExpr's in addition to instructions.
942 default: llvm_unreachable("Unknown instruction type encountered!");
943 // Build the switch statement using the Instruction.def file.
944 #define HANDLE_INST(NUM, OPCODE, CLASS) \
945 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
946 #include "llvm/Instruction.def"
949 // Assign the ordering to the freshly created DAG nodes.
950 if (NodeMap.count(&I)) {
952 AssignOrderingToNode(getValue(&I).getNode());
956 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
957 // generate the debug data structures now that we've seen its definition.
958 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
960 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
962 const DbgValueInst *DI = DDI.getDI();
963 DebugLoc dl = DDI.getdl();
964 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
965 MDNode *Variable = DI->getVariable();
966 uint64_t Offset = DI->getOffset();
969 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
970 SDV = DAG.getDbgValue(Variable, Val.getNode(),
971 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
972 DAG.AddDbgValue(SDV, Val.getNode(), false);
975 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
976 DanglingDebugInfoMap[V] = DanglingDebugInfo();
980 /// getValue - Return an SDValue for the given Value.
981 SDValue SelectionDAGBuilder::getValue(const Value *V) {
982 // If we already have an SDValue for this value, use it. It's important
983 // to do this first, so that we don't create a CopyFromReg if we already
984 // have a regular SDValue.
985 SDValue &N = NodeMap[V];
986 if (N.getNode()) return N;
988 // If there's a virtual register allocated and initialized for this
990 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
991 if (It != FuncInfo.ValueMap.end()) {
992 unsigned InReg = It->second;
993 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
994 SDValue Chain = DAG.getEntryNode();
995 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
996 resolveDanglingDebugInfo(V, N);
1000 // Otherwise create a new SDValue and remember it.
1001 SDValue Val = getValueImpl(V);
1003 resolveDanglingDebugInfo(V, Val);
1007 /// getNonRegisterValue - Return an SDValue for the given Value, but
1008 /// don't look in FuncInfo.ValueMap for a virtual register.
1009 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1010 // If we already have an SDValue for this value, use it.
1011 SDValue &N = NodeMap[V];
1012 if (N.getNode()) return N;
1014 // Otherwise create a new SDValue and remember it.
1015 SDValue Val = getValueImpl(V);
1017 resolveDanglingDebugInfo(V, Val);
1021 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1022 /// Create an SDValue for the given value.
1023 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1024 if (const Constant *C = dyn_cast<Constant>(V)) {
1025 EVT VT = TLI.getValueType(V->getType(), true);
1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1028 return DAG.getConstant(*CI, VT);
1030 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1031 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1033 if (isa<ConstantPointerNull>(C))
1034 return DAG.getConstant(0, TLI.getPointerTy());
1036 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1037 return DAG.getConstantFP(*CFP, VT);
1039 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1040 return DAG.getUNDEF(VT);
1042 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1043 visit(CE->getOpcode(), *CE);
1044 SDValue N1 = NodeMap[V];
1045 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1049 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1050 SmallVector<SDValue, 4> Constants;
1051 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1053 SDNode *Val = getValue(*OI).getNode();
1054 // If the operand is an empty aggregate, there are no values.
1056 // Add each leaf value from the operand to the Constants list
1057 // to form a flattened list of all the values.
1058 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1059 Constants.push_back(SDValue(Val, i));
1062 return DAG.getMergeValues(&Constants[0], Constants.size(),
1066 if (const ConstantDataSequential *CDS =
1067 dyn_cast<ConstantDataSequential>(C)) {
1068 SmallVector<SDValue, 4> Ops;
1069 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1070 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1071 // Add each leaf value from the operand to the Constants list
1072 // to form a flattened list of all the values.
1073 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1074 Ops.push_back(SDValue(Val, i));
1077 if (isa<ArrayType>(CDS->getType()))
1078 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1079 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1080 VT, &Ops[0], Ops.size());
1083 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1084 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1085 "Unknown struct or array constant!");
1087 SmallVector<EVT, 4> ValueVTs;
1088 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1089 unsigned NumElts = ValueVTs.size();
1091 return SDValue(); // empty struct
1092 SmallVector<SDValue, 4> Constants(NumElts);
1093 for (unsigned i = 0; i != NumElts; ++i) {
1094 EVT EltVT = ValueVTs[i];
1095 if (isa<UndefValue>(C))
1096 Constants[i] = DAG.getUNDEF(EltVT);
1097 else if (EltVT.isFloatingPoint())
1098 Constants[i] = DAG.getConstantFP(0, EltVT);
1100 Constants[i] = DAG.getConstant(0, EltVT);
1103 return DAG.getMergeValues(&Constants[0], NumElts,
1107 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1108 return DAG.getBlockAddress(BA, VT);
1110 VectorType *VecTy = cast<VectorType>(V->getType());
1111 unsigned NumElements = VecTy->getNumElements();
1113 // Now that we know the number and type of the elements, get that number of
1114 // elements into the Ops array based on what kind of constant it is.
1115 SmallVector<SDValue, 16> Ops;
1116 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1117 for (unsigned i = 0; i != NumElements; ++i)
1118 Ops.push_back(getValue(CV->getOperand(i)));
1120 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1121 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1124 if (EltVT.isFloatingPoint())
1125 Op = DAG.getConstantFP(0, EltVT);
1127 Op = DAG.getConstant(0, EltVT);
1128 Ops.assign(NumElements, Op);
1131 // Create a BUILD_VECTOR node.
1132 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1133 VT, &Ops[0], Ops.size());
1136 // If this is a static alloca, generate it as the frameindex instead of
1138 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1139 DenseMap<const AllocaInst*, int>::iterator SI =
1140 FuncInfo.StaticAllocaMap.find(AI);
1141 if (SI != FuncInfo.StaticAllocaMap.end())
1142 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1145 // If this is an instruction which fast-isel has deferred, select it now.
1146 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1147 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1148 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1149 SDValue Chain = DAG.getEntryNode();
1150 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1153 llvm_unreachable("Can't get register for value!");
1156 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1157 SDValue Chain = getControlRoot();
1158 SmallVector<ISD::OutputArg, 8> Outs;
1159 SmallVector<SDValue, 8> OutVals;
1161 if (!FuncInfo.CanLowerReturn) {
1162 unsigned DemoteReg = FuncInfo.DemoteRegister;
1163 const Function *F = I.getParent()->getParent();
1165 // Emit a store of the return value through the virtual register.
1166 // Leave Outs empty so that LowerReturn won't try to load return
1167 // registers the usual way.
1168 SmallVector<EVT, 1> PtrValueVTs;
1169 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1172 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1173 SDValue RetOp = getValue(I.getOperand(0));
1175 SmallVector<EVT, 4> ValueVTs;
1176 SmallVector<uint64_t, 4> Offsets;
1177 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1178 unsigned NumValues = ValueVTs.size();
1180 SmallVector<SDValue, 4> Chains(NumValues);
1181 for (unsigned i = 0; i != NumValues; ++i) {
1182 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1183 RetPtr.getValueType(), RetPtr,
1184 DAG.getIntPtrConstant(Offsets[i]));
1186 DAG.getStore(Chain, getCurDebugLoc(),
1187 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1188 // FIXME: better loc info would be nice.
1189 Add, MachinePointerInfo(), false, false, 0);
1192 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1193 MVT::Other, &Chains[0], NumValues);
1194 } else if (I.getNumOperands() != 0) {
1195 SmallVector<EVT, 4> ValueVTs;
1196 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1197 unsigned NumValues = ValueVTs.size();
1199 SDValue RetOp = getValue(I.getOperand(0));
1200 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1201 EVT VT = ValueVTs[j];
1203 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1205 const Function *F = I.getParent()->getParent();
1206 if (F->paramHasAttr(0, Attribute::SExt))
1207 ExtendKind = ISD::SIGN_EXTEND;
1208 else if (F->paramHasAttr(0, Attribute::ZExt))
1209 ExtendKind = ISD::ZERO_EXTEND;
1211 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1212 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1214 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1215 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1216 SmallVector<SDValue, 4> Parts(NumParts);
1217 getCopyToParts(DAG, getCurDebugLoc(),
1218 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1219 &Parts[0], NumParts, PartVT, ExtendKind);
1221 // 'inreg' on function refers to return value
1222 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1223 if (F->paramHasAttr(0, Attribute::InReg))
1226 // Propagate extension type if any
1227 if (ExtendKind == ISD::SIGN_EXTEND)
1229 else if (ExtendKind == ISD::ZERO_EXTEND)
1232 for (unsigned i = 0; i < NumParts; ++i) {
1233 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1235 OutVals.push_back(Parts[i]);
1241 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1242 CallingConv::ID CallConv =
1243 DAG.getMachineFunction().getFunction()->getCallingConv();
1244 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1245 Outs, OutVals, getCurDebugLoc(), DAG);
1247 // Verify that the target's LowerReturn behaved as expected.
1248 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1249 "LowerReturn didn't return a valid chain!");
1251 // Update the DAG with the new chain value resulting from return lowering.
1255 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1256 /// created for it, emit nodes to copy the value into the virtual
1258 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1260 if (V->getType()->isEmptyTy())
1263 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1264 if (VMI != FuncInfo.ValueMap.end()) {
1265 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1266 CopyValueToVirtualRegister(V, VMI->second);
1270 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1271 /// the current basic block, add it to ValueMap now so that we'll get a
1273 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1274 // No need to export constants.
1275 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1277 // Already exported?
1278 if (FuncInfo.isExportedInst(V)) return;
1280 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1281 CopyValueToVirtualRegister(V, Reg);
1284 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1285 const BasicBlock *FromBB) {
1286 // The operands of the setcc have to be in this block. We don't know
1287 // how to export them from some other block.
1288 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1289 // Can export from current BB.
1290 if (VI->getParent() == FromBB)
1293 // Is already exported, noop.
1294 return FuncInfo.isExportedInst(V);
1297 // If this is an argument, we can export it if the BB is the entry block or
1298 // if it is already exported.
1299 if (isa<Argument>(V)) {
1300 if (FromBB == &FromBB->getParent()->getEntryBlock())
1303 // Otherwise, can only export this if it is already exported.
1304 return FuncInfo.isExportedInst(V);
1307 // Otherwise, constants can always be exported.
1311 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1312 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1313 const MachineBasicBlock *Dst) const {
1314 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1317 const BasicBlock *SrcBB = Src->getBasicBlock();
1318 const BasicBlock *DstBB = Dst->getBasicBlock();
1319 return BPI->getEdgeWeight(SrcBB, DstBB);
1322 void SelectionDAGBuilder::
1323 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1324 uint32_t Weight /* = 0 */) {
1326 Weight = getEdgeWeight(Src, Dst);
1327 Src->addSuccessor(Dst, Weight);
1331 static bool InBlock(const Value *V, const BasicBlock *BB) {
1332 if (const Instruction *I = dyn_cast<Instruction>(V))
1333 return I->getParent() == BB;
1337 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1338 /// This function emits a branch and is used at the leaves of an OR or an
1339 /// AND operator tree.
1342 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1343 MachineBasicBlock *TBB,
1344 MachineBasicBlock *FBB,
1345 MachineBasicBlock *CurBB,
1346 MachineBasicBlock *SwitchBB) {
1347 const BasicBlock *BB = CurBB->getBasicBlock();
1349 // If the leaf of the tree is a comparison, merge the condition into
1351 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1352 // The operands of the cmp have to be in this block. We don't know
1353 // how to export them from some other block. If this is the first block
1354 // of the sequence, no exporting is needed.
1355 if (CurBB == SwitchBB ||
1356 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1357 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1358 ISD::CondCode Condition;
1359 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1360 Condition = getICmpCondCode(IC->getPredicate());
1361 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1362 Condition = getFCmpCondCode(FC->getPredicate());
1363 if (TM.Options.NoNaNsFPMath)
1364 Condition = getFCmpCodeWithoutNaN(Condition);
1366 Condition = ISD::SETEQ; // silence warning.
1367 llvm_unreachable("Unknown compare instruction");
1370 CaseBlock CB(Condition, BOp->getOperand(0),
1371 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1372 SwitchCases.push_back(CB);
1377 // Create a CaseBlock record representing this branch.
1378 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1379 NULL, TBB, FBB, CurBB);
1380 SwitchCases.push_back(CB);
1383 /// FindMergedConditions - If Cond is an expression like
1384 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1385 MachineBasicBlock *TBB,
1386 MachineBasicBlock *FBB,
1387 MachineBasicBlock *CurBB,
1388 MachineBasicBlock *SwitchBB,
1390 // If this node is not part of the or/and tree, emit it as a branch.
1391 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1392 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1393 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1394 BOp->getParent() != CurBB->getBasicBlock() ||
1395 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1396 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1397 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1401 // Create TmpBB after CurBB.
1402 MachineFunction::iterator BBI = CurBB;
1403 MachineFunction &MF = DAG.getMachineFunction();
1404 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1405 CurBB->getParent()->insert(++BBI, TmpBB);
1407 if (Opc == Instruction::Or) {
1408 // Codegen X | Y as:
1416 // Emit the LHS condition.
1417 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1419 // Emit the RHS condition into TmpBB.
1420 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1422 assert(Opc == Instruction::And && "Unknown merge op!");
1423 // Codegen X & Y as:
1430 // This requires creation of TmpBB after CurBB.
1432 // Emit the LHS condition.
1433 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1435 // Emit the RHS condition into TmpBB.
1436 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1440 /// If the set of cases should be emitted as a series of branches, return true.
1441 /// If we should emit this as a bunch of and/or'd together conditions, return
1444 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1445 if (Cases.size() != 2) return true;
1447 // If this is two comparisons of the same values or'd or and'd together, they
1448 // will get folded into a single comparison, so don't emit two blocks.
1449 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1450 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1451 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1452 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1456 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1457 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1458 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1459 Cases[0].CC == Cases[1].CC &&
1460 isa<Constant>(Cases[0].CmpRHS) &&
1461 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1462 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1464 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1471 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1472 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1474 // Update machine-CFG edges.
1475 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1477 // Figure out which block is immediately after the current one.
1478 MachineBasicBlock *NextBlock = 0;
1479 MachineFunction::iterator BBI = BrMBB;
1480 if (++BBI != FuncInfo.MF->end())
1483 if (I.isUnconditional()) {
1484 // Update machine-CFG edges.
1485 BrMBB->addSuccessor(Succ0MBB);
1487 // If this is not a fall-through branch, emit the branch.
1488 if (Succ0MBB != NextBlock)
1489 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1490 MVT::Other, getControlRoot(),
1491 DAG.getBasicBlock(Succ0MBB)));
1496 // If this condition is one of the special cases we handle, do special stuff
1498 const Value *CondVal = I.getCondition();
1499 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1501 // If this is a series of conditions that are or'd or and'd together, emit
1502 // this as a sequence of branches instead of setcc's with and/or operations.
1503 // As long as jumps are not expensive, this should improve performance.
1504 // For example, instead of something like:
1517 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1518 if (!TLI.isJumpExpensive() &&
1520 (BOp->getOpcode() == Instruction::And ||
1521 BOp->getOpcode() == Instruction::Or)) {
1522 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1524 // If the compares in later blocks need to use values not currently
1525 // exported from this block, export them now. This block should always
1526 // be the first entry.
1527 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1529 // Allow some cases to be rejected.
1530 if (ShouldEmitAsBranches(SwitchCases)) {
1531 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1532 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1533 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1536 // Emit the branch for this block.
1537 visitSwitchCase(SwitchCases[0], BrMBB);
1538 SwitchCases.erase(SwitchCases.begin());
1542 // Okay, we decided not to do this, remove any inserted MBB's and clear
1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1545 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1547 SwitchCases.clear();
1551 // Create a CaseBlock record representing this branch.
1552 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1553 NULL, Succ0MBB, Succ1MBB, BrMBB);
1555 // Use visitSwitchCase to actually insert the fast branch sequence for this
1557 visitSwitchCase(CB, BrMBB);
1560 /// visitSwitchCase - Emits the necessary code to represent a single node in
1561 /// the binary search tree resulting from lowering a switch instruction.
1562 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1563 MachineBasicBlock *SwitchBB) {
1565 SDValue CondLHS = getValue(CB.CmpLHS);
1566 DebugLoc dl = getCurDebugLoc();
1568 // Build the setcc now.
1569 if (CB.CmpMHS == NULL) {
1570 // Fold "(X == true)" to X and "(X == false)" to !X to
1571 // handle common cases produced by branch lowering.
1572 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1573 CB.CC == ISD::SETEQ)
1575 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1576 CB.CC == ISD::SETEQ) {
1577 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1578 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1580 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1582 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1584 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1585 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1587 SDValue CmpOp = getValue(CB.CmpMHS);
1588 EVT VT = CmpOp.getValueType();
1590 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1591 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1594 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1595 VT, CmpOp, DAG.getConstant(Low, VT));
1596 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1597 DAG.getConstant(High-Low, VT), ISD::SETULE);
1601 // Update successor info
1602 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1603 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1605 // Set NextBlock to be the MBB immediately after the current one, if any.
1606 // This is used to avoid emitting unnecessary branches to the next block.
1607 MachineBasicBlock *NextBlock = 0;
1608 MachineFunction::iterator BBI = SwitchBB;
1609 if (++BBI != FuncInfo.MF->end())
1612 // If the lhs block is the next block, invert the condition so that we can
1613 // fall through to the lhs instead of the rhs block.
1614 if (CB.TrueBB == NextBlock) {
1615 std::swap(CB.TrueBB, CB.FalseBB);
1616 SDValue True = DAG.getConstant(1, Cond.getValueType());
1617 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1620 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1621 MVT::Other, getControlRoot(), Cond,
1622 DAG.getBasicBlock(CB.TrueBB));
1624 // Insert the false branch. Do this even if it's a fall through branch,
1625 // this makes it easier to do DAG optimizations which require inverting
1626 // the branch condition.
1627 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1628 DAG.getBasicBlock(CB.FalseBB));
1630 DAG.setRoot(BrCond);
1633 /// visitJumpTable - Emit JumpTable node in the current MBB
1634 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1635 // Emit the code for the jump table
1636 assert(JT.Reg != -1U && "Should lower JT Header first!");
1637 EVT PTy = TLI.getPointerTy();
1638 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1640 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1641 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1642 MVT::Other, Index.getValue(1),
1644 DAG.setRoot(BrJumpTable);
1647 /// visitJumpTableHeader - This function emits necessary code to produce index
1648 /// in the JumpTable from switch case.
1649 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1650 JumpTableHeader &JTH,
1651 MachineBasicBlock *SwitchBB) {
1652 // Subtract the lowest switch case value from the value being switched on and
1653 // conditional branch to default mbb if the result is greater than the
1654 // difference between smallest and largest cases.
1655 SDValue SwitchOp = getValue(JTH.SValue);
1656 EVT VT = SwitchOp.getValueType();
1657 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1658 DAG.getConstant(JTH.First, VT));
1660 // The SDNode we just created, which holds the value being switched on minus
1661 // the smallest case value, needs to be copied to a virtual register so it
1662 // can be used as an index into the jump table in a subsequent basic block.
1663 // This value may be smaller or larger than the target's pointer type, and
1664 // therefore require extension or truncating.
1665 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1667 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1668 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1669 JumpTableReg, SwitchOp);
1670 JT.Reg = JumpTableReg;
1672 // Emit the range check for the jump table, and branch to the default block
1673 // for the switch statement if the value being switched on exceeds the largest
1674 // case in the switch.
1675 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1676 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1677 DAG.getConstant(JTH.Last-JTH.First,VT),
1680 // Set NextBlock to be the MBB immediately after the current one, if any.
1681 // This is used to avoid emitting unnecessary branches to the next block.
1682 MachineBasicBlock *NextBlock = 0;
1683 MachineFunction::iterator BBI = SwitchBB;
1685 if (++BBI != FuncInfo.MF->end())
1688 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1689 MVT::Other, CopyTo, CMP,
1690 DAG.getBasicBlock(JT.Default));
1692 if (JT.MBB != NextBlock)
1693 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1694 DAG.getBasicBlock(JT.MBB));
1696 DAG.setRoot(BrCond);
1699 /// visitBitTestHeader - This function emits necessary code to produce value
1700 /// suitable for "bit tests"
1701 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1702 MachineBasicBlock *SwitchBB) {
1703 // Subtract the minimum value
1704 SDValue SwitchOp = getValue(B.SValue);
1705 EVT VT = SwitchOp.getValueType();
1706 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1707 DAG.getConstant(B.First, VT));
1710 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1711 TLI.getSetCCResultType(Sub.getValueType()),
1712 Sub, DAG.getConstant(B.Range, VT),
1715 // Determine the type of the test operands.
1716 bool UsePtrType = false;
1717 if (!TLI.isTypeLegal(VT))
1720 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1721 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1722 // Switch table case range are encoded into series of masks.
1723 // Just use pointer type, it's guaranteed to fit.
1729 VT = TLI.getPointerTy();
1730 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1734 B.Reg = FuncInfo.CreateReg(VT);
1735 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1738 // Set NextBlock to be the MBB immediately after the current one, if any.
1739 // This is used to avoid emitting unnecessary branches to the next block.
1740 MachineBasicBlock *NextBlock = 0;
1741 MachineFunction::iterator BBI = SwitchBB;
1742 if (++BBI != FuncInfo.MF->end())
1745 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1747 addSuccessorWithWeight(SwitchBB, B.Default);
1748 addSuccessorWithWeight(SwitchBB, MBB);
1750 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1751 MVT::Other, CopyTo, RangeCmp,
1752 DAG.getBasicBlock(B.Default));
1754 if (MBB != NextBlock)
1755 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1756 DAG.getBasicBlock(MBB));
1758 DAG.setRoot(BrRange);
1761 /// visitBitTestCase - this function produces one "bit test"
1762 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1763 MachineBasicBlock* NextMBB,
1766 MachineBasicBlock *SwitchBB) {
1768 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1771 unsigned PopCount = CountPopulation_64(B.Mask);
1772 if (PopCount == 1) {
1773 // Testing for a single bit; just compare the shift count with what it
1774 // would need to be to shift a 1 bit in that position.
1775 Cmp = DAG.getSetCC(getCurDebugLoc(),
1776 TLI.getSetCCResultType(VT),
1778 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1780 } else if (PopCount == BB.Range) {
1781 // There is only one zero bit in the range, test for it directly.
1782 Cmp = DAG.getSetCC(getCurDebugLoc(),
1783 TLI.getSetCCResultType(VT),
1785 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1788 // Make desired shift
1789 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1790 DAG.getConstant(1, VT), ShiftOp);
1792 // Emit bit tests and jumps
1793 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1794 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1795 Cmp = DAG.getSetCC(getCurDebugLoc(),
1796 TLI.getSetCCResultType(VT),
1797 AndOp, DAG.getConstant(0, VT),
1801 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1802 addSuccessorWithWeight(SwitchBB, NextMBB);
1804 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1805 MVT::Other, getControlRoot(),
1806 Cmp, DAG.getBasicBlock(B.TargetBB));
1808 // Set NextBlock to be the MBB immediately after the current one, if any.
1809 // This is used to avoid emitting unnecessary branches to the next block.
1810 MachineBasicBlock *NextBlock = 0;
1811 MachineFunction::iterator BBI = SwitchBB;
1812 if (++BBI != FuncInfo.MF->end())
1815 if (NextMBB != NextBlock)
1816 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1817 DAG.getBasicBlock(NextMBB));
1822 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1823 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1825 // Retrieve successors.
1826 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1827 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1829 const Value *Callee(I.getCalledValue());
1830 if (isa<InlineAsm>(Callee))
1833 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1835 // If the value of the invoke is used outside of its defining block, make it
1836 // available as a virtual register.
1837 CopyToExportRegsIfNeeded(&I);
1839 // Update successor info
1840 addSuccessorWithWeight(InvokeMBB, Return);
1841 addSuccessorWithWeight(InvokeMBB, LandingPad);
1843 // Drop into normal successor.
1844 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1845 MVT::Other, getControlRoot(),
1846 DAG.getBasicBlock(Return)));
1849 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1850 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1853 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1854 assert(FuncInfo.MBB->isLandingPad() &&
1855 "Call to landingpad not in landing pad!");
1857 MachineBasicBlock *MBB = FuncInfo.MBB;
1858 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1859 AddLandingPadInfo(LP, MMI, MBB);
1861 // If there aren't registers to copy the values into (e.g., during SjLj
1862 // exceptions), then don't bother to create these DAG nodes.
1863 if (TLI.getExceptionPointerRegister() == 0 &&
1864 TLI.getExceptionSelectorRegister() == 0)
1867 SmallVector<EVT, 2> ValueVTs;
1868 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1870 // Insert the EXCEPTIONADDR instruction.
1871 assert(FuncInfo.MBB->isLandingPad() &&
1872 "Call to eh.exception not in landing pad!");
1873 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1875 Ops[0] = DAG.getRoot();
1876 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1877 SDValue Chain = Op1.getValue(1);
1879 // Insert the EHSELECTION instruction.
1880 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1883 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1884 Chain = Op2.getValue(1);
1885 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1889 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1890 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1893 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1894 setValue(&LP, RetPair.first);
1895 DAG.setRoot(RetPair.second);
1898 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1899 /// small case ranges).
1900 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1901 CaseRecVector& WorkList,
1903 MachineBasicBlock *Default,
1904 MachineBasicBlock *SwitchBB) {
1905 Case& BackCase = *(CR.Range.second-1);
1907 // Size is the number of Cases represented by this range.
1908 size_t Size = CR.Range.second - CR.Range.first;
1912 // Get the MachineFunction which holds the current MBB. This is used when
1913 // inserting any additional MBBs necessary to represent the switch.
1914 MachineFunction *CurMF = FuncInfo.MF;
1916 // Figure out which block is immediately after the current one.
1917 MachineBasicBlock *NextBlock = 0;
1918 MachineFunction::iterator BBI = CR.CaseBB;
1920 if (++BBI != FuncInfo.MF->end())
1923 // If any two of the cases has the same destination, and if one value
1924 // is the same as the other, but has one bit unset that the other has set,
1925 // use bit manipulation to do two compares at once. For example:
1926 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1927 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1928 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1929 if (Size == 2 && CR.CaseBB == SwitchBB) {
1930 Case &Small = *CR.Range.first;
1931 Case &Big = *(CR.Range.second-1);
1933 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1934 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1935 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1937 // Check that there is only one bit different.
1938 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1939 (SmallValue | BigValue) == BigValue) {
1940 // Isolate the common bit.
1941 APInt CommonBit = BigValue & ~SmallValue;
1942 assert((SmallValue | CommonBit) == BigValue &&
1943 CommonBit.countPopulation() == 1 && "Not a common bit?");
1945 SDValue CondLHS = getValue(SV);
1946 EVT VT = CondLHS.getValueType();
1947 DebugLoc DL = getCurDebugLoc();
1949 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1950 DAG.getConstant(CommonBit, VT));
1951 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1952 Or, DAG.getConstant(BigValue, VT),
1955 // Update successor info.
1956 addSuccessorWithWeight(SwitchBB, Small.BB);
1957 addSuccessorWithWeight(SwitchBB, Default);
1959 // Insert the true branch.
1960 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1961 getControlRoot(), Cond,
1962 DAG.getBasicBlock(Small.BB));
1964 // Insert the false branch.
1965 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1966 DAG.getBasicBlock(Default));
1968 DAG.setRoot(BrCond);
1974 // Rearrange the case blocks so that the last one falls through if possible.
1975 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1976 // The last case block won't fall through into 'NextBlock' if we emit the
1977 // branches in this order. See if rearranging a case value would help.
1978 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1979 if (I->BB == NextBlock) {
1980 std::swap(*I, BackCase);
1986 // Create a CaseBlock record representing a conditional branch to
1987 // the Case's target mbb if the value being switched on SV is equal
1989 MachineBasicBlock *CurBlock = CR.CaseBB;
1990 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1991 MachineBasicBlock *FallThrough;
1993 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1994 CurMF->insert(BBI, FallThrough);
1996 // Put SV in a virtual register to make it available from the new blocks.
1997 ExportFromCurrentBlock(SV);
1999 // If the last case doesn't match, go to the default block.
2000 FallThrough = Default;
2003 const Value *RHS, *LHS, *MHS;
2005 if (I->High == I->Low) {
2006 // This is just small small case range :) containing exactly 1 case
2008 LHS = SV; RHS = I->High; MHS = NULL;
2011 LHS = I->Low; MHS = SV; RHS = I->High;
2014 uint32_t ExtraWeight = I->ExtraWeight;
2015 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2017 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
2019 // If emitting the first comparison, just call visitSwitchCase to emit the
2020 // code into the current block. Otherwise, push the CaseBlock onto the
2021 // vector to be later processed by SDISel, and insert the node's MBB
2022 // before the next MBB.
2023 if (CurBlock == SwitchBB)
2024 visitSwitchCase(CB, SwitchBB);
2026 SwitchCases.push_back(CB);
2028 CurBlock = FallThrough;
2034 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2035 return !TLI.getTargetMachine().Options.DisableJumpTables &&
2036 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2037 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2040 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2041 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2042 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2043 return (LastExt - FirstExt + 1ULL);
2046 /// handleJTSwitchCase - Emit jumptable for current switch case range
2047 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2048 CaseRecVector &WorkList,
2050 MachineBasicBlock *Default,
2051 MachineBasicBlock *SwitchBB) {
2052 Case& FrontCase = *CR.Range.first;
2053 Case& BackCase = *(CR.Range.second-1);
2055 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2056 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2058 APInt TSize(First.getBitWidth(), 0);
2059 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2062 if (!areJTsAllowed(TLI) || TSize.ult(4))
2065 APInt Range = ComputeRange(First, Last);
2066 // The density is TSize / Range. Require at least 40%.
2067 // It should not be possible for IntTSize to saturate for sane code, but make
2068 // sure we handle Range saturation correctly.
2069 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2070 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2071 if (IntTSize * 10 < IntRange * 4)
2074 DEBUG(dbgs() << "Lowering jump table\n"
2075 << "First entry: " << First << ". Last entry: " << Last << '\n'
2076 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2078 // Get the MachineFunction which holds the current MBB. This is used when
2079 // inserting any additional MBBs necessary to represent the switch.
2080 MachineFunction *CurMF = FuncInfo.MF;
2082 // Figure out which block is immediately after the current one.
2083 MachineFunction::iterator BBI = CR.CaseBB;
2086 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2088 // Create a new basic block to hold the code for loading the address
2089 // of the jump table, and jumping to it. Update successor information;
2090 // we will either branch to the default case for the switch, or the jump
2092 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2093 CurMF->insert(BBI, JumpTableBB);
2095 addSuccessorWithWeight(CR.CaseBB, Default);
2096 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2098 // Build a vector of destination BBs, corresponding to each target
2099 // of the jump table. If the value of the jump table slot corresponds to
2100 // a case statement, push the case's BB onto the vector, otherwise, push
2102 std::vector<MachineBasicBlock*> DestBBs;
2104 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2105 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2106 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2108 if (Low.ule(TEI) && TEI.ule(High)) {
2109 DestBBs.push_back(I->BB);
2113 DestBBs.push_back(Default);
2117 // Update successor info. Add one edge to each unique successor.
2118 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2119 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2120 E = DestBBs.end(); I != E; ++I) {
2121 if (!SuccsHandled[(*I)->getNumber()]) {
2122 SuccsHandled[(*I)->getNumber()] = true;
2123 addSuccessorWithWeight(JumpTableBB, *I);
2127 // Create a jump table index for this jump table.
2128 unsigned JTEncoding = TLI.getJumpTableEncoding();
2129 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2130 ->createJumpTableIndex(DestBBs);
2132 // Set the jump table information so that we can codegen it as a second
2133 // MachineBasicBlock
2134 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2135 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2136 if (CR.CaseBB == SwitchBB)
2137 visitJumpTableHeader(JT, JTH, SwitchBB);
2139 JTCases.push_back(JumpTableBlock(JTH, JT));
2143 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2145 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2146 CaseRecVector& WorkList,
2148 MachineBasicBlock *Default,
2149 MachineBasicBlock *SwitchBB) {
2150 // Get the MachineFunction which holds the current MBB. This is used when
2151 // inserting any additional MBBs necessary to represent the switch.
2152 MachineFunction *CurMF = FuncInfo.MF;
2154 // Figure out which block is immediately after the current one.
2155 MachineFunction::iterator BBI = CR.CaseBB;
2158 Case& FrontCase = *CR.Range.first;
2159 Case& BackCase = *(CR.Range.second-1);
2160 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2162 // Size is the number of Cases represented by this range.
2163 unsigned Size = CR.Range.second - CR.Range.first;
2165 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2166 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2168 CaseItr Pivot = CR.Range.first + Size/2;
2170 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2171 // (heuristically) allow us to emit JumpTable's later.
2172 APInt TSize(First.getBitWidth(), 0);
2173 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2177 APInt LSize = FrontCase.size();
2178 APInt RSize = TSize-LSize;
2179 DEBUG(dbgs() << "Selecting best pivot: \n"
2180 << "First: " << First << ", Last: " << Last <<'\n'
2181 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2182 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2184 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2185 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2186 APInt Range = ComputeRange(LEnd, RBegin);
2187 // Old: assert((Range - 2ULL).isNonNegative() && "Invalid case distance");
2188 // Why APInt::sge wasn't used?
2189 assert(Range.uge(APInt(Range.getBitWidth(), 2)) && "Invalid case distance");
2191 // Use volatile double here to avoid excess precision issues on some hosts,
2192 // e.g. that use 80-bit X87 registers.
2193 volatile double LDensity =
2194 (double)LSize.roundToDouble() /
2195 (LEnd - First + 1ULL).roundToDouble();
2196 volatile double RDensity =
2197 (double)RSize.roundToDouble() /
2198 (Last - RBegin + 1ULL).roundToDouble();
2199 double Metric = Range.logBase2()*(LDensity+RDensity);
2200 // Should always split in some non-trivial place
2201 DEBUG(dbgs() <<"=>Step\n"
2202 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2203 << "LDensity: " << LDensity
2204 << ", RDensity: " << RDensity << '\n'
2205 << "Metric: " << Metric << '\n');
2206 if (FMetric < Metric) {
2209 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2215 if (areJTsAllowed(TLI)) {
2216 // If our case is dense we *really* should handle it earlier!
2217 assert((FMetric > 0) && "Should handle dense range earlier!");
2219 Pivot = CR.Range.first + Size/2;
2222 CaseRange LHSR(CR.Range.first, Pivot);
2223 CaseRange RHSR(Pivot, CR.Range.second);
2224 const Constant *C = Pivot->Low;
2225 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2227 // We know that we branch to the LHS if the Value being switched on is
2228 // less than the Pivot value, C. We use this to optimize our binary
2229 // tree a bit, by recognizing that if SV is greater than or equal to the
2230 // LHS's Case Value, and that Case Value is exactly one less than the
2231 // Pivot's Value, then we can branch directly to the LHS's Target,
2232 // rather than creating a leaf node for it.
2233 if ((LHSR.second - LHSR.first) == 1 &&
2234 LHSR.first->High == CR.GE &&
2235 cast<ConstantInt>(C)->getValue() ==
2236 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2237 TrueBB = LHSR.first->BB;
2239 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2240 CurMF->insert(BBI, TrueBB);
2241 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2243 // Put SV in a virtual register to make it available from the new blocks.
2244 ExportFromCurrentBlock(SV);
2247 // Similar to the optimization above, if the Value being switched on is
2248 // known to be less than the Constant CR.LT, and the current Case Value
2249 // is CR.LT - 1, then we can branch directly to the target block for
2250 // the current Case Value, rather than emitting a RHS leaf node for it.
2251 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2252 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2253 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2254 FalseBB = RHSR.first->BB;
2256 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2257 CurMF->insert(BBI, FalseBB);
2258 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2260 // Put SV in a virtual register to make it available from the new blocks.
2261 ExportFromCurrentBlock(SV);
2264 // Create a CaseBlock record representing a conditional branch to
2265 // the LHS node if the value being switched on SV is less than C.
2266 // Otherwise, branch to LHS.
2267 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2269 if (CR.CaseBB == SwitchBB)
2270 visitSwitchCase(CB, SwitchBB);
2272 SwitchCases.push_back(CB);
2277 /// handleBitTestsSwitchCase - if current case range has few destination and
2278 /// range span less, than machine word bitwidth, encode case range into series
2279 /// of masks and emit bit tests with these masks.
2280 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2281 CaseRecVector& WorkList,
2283 MachineBasicBlock* Default,
2284 MachineBasicBlock *SwitchBB){
2285 EVT PTy = TLI.getPointerTy();
2286 unsigned IntPtrBits = PTy.getSizeInBits();
2288 Case& FrontCase = *CR.Range.first;
2289 Case& BackCase = *(CR.Range.second-1);
2291 // Get the MachineFunction which holds the current MBB. This is used when
2292 // inserting any additional MBBs necessary to represent the switch.
2293 MachineFunction *CurMF = FuncInfo.MF;
2295 // If target does not have legal shift left, do not emit bit tests at all.
2296 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2300 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2302 // Single case counts one, case range - two.
2303 numCmps += (I->Low == I->High ? 1 : 2);
2306 // Count unique destinations
2307 SmallSet<MachineBasicBlock*, 4> Dests;
2308 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2309 Dests.insert(I->BB);
2310 if (Dests.size() > 3)
2311 // Don't bother the code below, if there are too much unique destinations
2314 DEBUG(dbgs() << "Total number of unique destinations: "
2315 << Dests.size() << '\n'
2316 << "Total number of comparisons: " << numCmps << '\n');
2318 // Compute span of values.
2319 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2320 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2321 APInt cmpRange = maxValue - minValue;
2323 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2324 << "Low bound: " << minValue << '\n'
2325 << "High bound: " << maxValue << '\n');
2327 if (cmpRange.uge(IntPtrBits) ||
2328 (!(Dests.size() == 1 && numCmps >= 3) &&
2329 !(Dests.size() == 2 && numCmps >= 5) &&
2330 !(Dests.size() >= 3 && numCmps >= 6)))
2333 DEBUG(dbgs() << "Emitting bit tests\n");
2334 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2336 // Optimize the case where all the case values fit in a
2337 // word without having to subtract minValue. In this case,
2338 // we can optimize away the subtraction.
2339 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2340 cmpRange = maxValue;
2342 lowBound = minValue;
2345 CaseBitsVector CasesBits;
2346 unsigned i, count = 0;
2348 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2349 MachineBasicBlock* Dest = I->BB;
2350 for (i = 0; i < count; ++i)
2351 if (Dest == CasesBits[i].BB)
2355 assert((count < 3) && "Too much destinations to test!");
2356 CasesBits.push_back(CaseBits(0, Dest, 0));
2360 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2361 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2363 uint64_t lo = (lowValue - lowBound).getZExtValue();
2364 uint64_t hi = (highValue - lowBound).getZExtValue();
2366 for (uint64_t j = lo; j <= hi; j++) {
2367 CasesBits[i].Mask |= 1ULL << j;
2368 CasesBits[i].Bits++;
2372 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2376 // Figure out which block is immediately after the current one.
2377 MachineFunction::iterator BBI = CR.CaseBB;
2380 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2382 DEBUG(dbgs() << "Cases:\n");
2383 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2384 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2385 << ", Bits: " << CasesBits[i].Bits
2386 << ", BB: " << CasesBits[i].BB << '\n');
2388 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2389 CurMF->insert(BBI, CaseBB);
2390 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2394 // Put SV in a virtual register to make it available from the new blocks.
2395 ExportFromCurrentBlock(SV);
2398 BitTestBlock BTB(lowBound, cmpRange, SV,
2399 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2400 CR.CaseBB, Default, BTC);
2402 if (CR.CaseBB == SwitchBB)
2403 visitBitTestHeader(BTB, SwitchBB);
2405 BitTestCases.push_back(BTB);
2410 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2411 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2412 const SwitchInst& SI) {
2414 /// Use a shorter form of declaration, and also
2415 /// show the we want to use CRSBuilder as Clusterifier.
2416 typedef CRSBuilderBase<MachineBasicBlock, true> Clusterifier;
2418 Clusterifier TheClusterifier;
2420 // Start with "simple" cases
2421 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2423 const BasicBlock *SuccBB = i.getCaseSuccessor();
2424 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2426 TheClusterifier.add(i.getCaseValueEx(), SMBB);
2429 TheClusterifier.optimize();
2431 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2433 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2434 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2435 Clusterifier::Cluster &C = *i;
2438 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock());
2441 W *= C.first.Weight;
2442 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W);
2445 Cases.push_back(Case(C.first.Low, C.first.High, C.second, W));
2447 if (C.first.Low != C.first.High)
2448 // A range counts double, since it requires two compares.
2455 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2456 MachineBasicBlock *Last) {
2458 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2459 if (JTCases[i].first.HeaderBB == First)
2460 JTCases[i].first.HeaderBB = Last;
2462 // Update BitTestCases.
2463 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2464 if (BitTestCases[i].Parent == First)
2465 BitTestCases[i].Parent = Last;
2468 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2469 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2471 // Figure out which block is immediately after the current one.
2472 MachineBasicBlock *NextBlock = 0;
2473 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2475 // If there is only the default destination, branch to it if it is not the
2476 // next basic block. Otherwise, just fall through.
2477 if (!SI.getNumCases()) {
2478 // Update machine-CFG edges.
2480 // If this is not a fall-through branch, emit the branch.
2481 SwitchMBB->addSuccessor(Default);
2482 if (Default != NextBlock)
2483 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2484 MVT::Other, getControlRoot(),
2485 DAG.getBasicBlock(Default)));
2490 // If there are any non-default case statements, create a vector of Cases
2491 // representing each one, and sort the vector so that we can efficiently
2492 // create a binary search tree from them.
2494 size_t numCmps = Clusterify(Cases, SI);
2495 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2496 << ". Total compares: " << numCmps << '\n');
2499 // Get the Value to be switched on and default basic blocks, which will be
2500 // inserted into CaseBlock records, representing basic blocks in the binary
2502 const Value *SV = SI.getCondition();
2504 // Push the initial CaseRec onto the worklist
2505 CaseRecVector WorkList;
2506 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2507 CaseRange(Cases.begin(),Cases.end())));
2509 while (!WorkList.empty()) {
2510 // Grab a record representing a case range to process off the worklist
2511 CaseRec CR = WorkList.back();
2512 WorkList.pop_back();
2514 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2517 // If the range has few cases (two or less) emit a series of specific
2519 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2522 // If the switch has more than 5 blocks, and at least 40% dense, and the
2523 // target supports indirect branches, then emit a jump table rather than
2524 // lowering the switch to a binary tree of conditional branches.
2525 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2528 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2529 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2530 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2534 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2535 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2537 // Update machine-CFG edges with unique successors.
2538 SmallVector<BasicBlock*, 32> succs;
2539 succs.reserve(I.getNumSuccessors());
2540 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2541 succs.push_back(I.getSuccessor(i));
2542 array_pod_sort(succs.begin(), succs.end());
2543 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2544 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2545 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2546 addSuccessorWithWeight(IndirectBrMBB, Succ);
2549 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2550 MVT::Other, getControlRoot(),
2551 getValue(I.getAddress())));
2554 void SelectionDAGBuilder::visitFSub(const User &I) {
2555 // -0.0 - X --> fneg
2556 Type *Ty = I.getType();
2557 if (isa<Constant>(I.getOperand(0)) &&
2558 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2559 SDValue Op2 = getValue(I.getOperand(1));
2560 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2561 Op2.getValueType(), Op2));
2565 visitBinary(I, ISD::FSUB);
2568 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2569 SDValue Op1 = getValue(I.getOperand(0));
2570 SDValue Op2 = getValue(I.getOperand(1));
2571 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2572 Op1.getValueType(), Op1, Op2));
2575 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2576 SDValue Op1 = getValue(I.getOperand(0));
2577 SDValue Op2 = getValue(I.getOperand(1));
2579 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2581 // Coerce the shift amount to the right type if we can.
2582 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2583 unsigned ShiftSize = ShiftTy.getSizeInBits();
2584 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2585 DebugLoc DL = getCurDebugLoc();
2587 // If the operand is smaller than the shift count type, promote it.
2588 if (ShiftSize > Op2Size)
2589 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2591 // If the operand is larger than the shift count type but the shift
2592 // count type has enough bits to represent any shift value, truncate
2593 // it now. This is a common case and it exposes the truncate to
2594 // optimization early.
2595 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2596 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2597 // Otherwise we'll need to temporarily settle for some other convenient
2598 // type. Type legalization will make adjustments once the shiftee is split.
2600 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2603 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2604 Op1.getValueType(), Op1, Op2));
2607 void SelectionDAGBuilder::visitSDiv(const User &I) {
2608 SDValue Op1 = getValue(I.getOperand(0));
2609 SDValue Op2 = getValue(I.getOperand(1));
2611 // Turn exact SDivs into multiplications.
2612 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2614 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2615 !isa<ConstantSDNode>(Op1) &&
2616 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2617 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2619 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2623 void SelectionDAGBuilder::visitICmp(const User &I) {
2624 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2625 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2626 predicate = IC->getPredicate();
2627 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2628 predicate = ICmpInst::Predicate(IC->getPredicate());
2629 SDValue Op1 = getValue(I.getOperand(0));
2630 SDValue Op2 = getValue(I.getOperand(1));
2631 ISD::CondCode Opcode = getICmpCondCode(predicate);
2633 EVT DestVT = TLI.getValueType(I.getType());
2634 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2637 void SelectionDAGBuilder::visitFCmp(const User &I) {
2638 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2639 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2640 predicate = FC->getPredicate();
2641 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2642 predicate = FCmpInst::Predicate(FC->getPredicate());
2643 SDValue Op1 = getValue(I.getOperand(0));
2644 SDValue Op2 = getValue(I.getOperand(1));
2645 ISD::CondCode Condition = getFCmpCondCode(predicate);
2646 if (TM.Options.NoNaNsFPMath)
2647 Condition = getFCmpCodeWithoutNaN(Condition);
2648 EVT DestVT = TLI.getValueType(I.getType());
2649 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2652 void SelectionDAGBuilder::visitSelect(const User &I) {
2653 SmallVector<EVT, 4> ValueVTs;
2654 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2655 unsigned NumValues = ValueVTs.size();
2656 if (NumValues == 0) return;
2658 SmallVector<SDValue, 4> Values(NumValues);
2659 SDValue Cond = getValue(I.getOperand(0));
2660 SDValue TrueVal = getValue(I.getOperand(1));
2661 SDValue FalseVal = getValue(I.getOperand(2));
2662 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2663 ISD::VSELECT : ISD::SELECT;
2665 for (unsigned i = 0; i != NumValues; ++i)
2666 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2667 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2669 SDValue(TrueVal.getNode(),
2670 TrueVal.getResNo() + i),
2671 SDValue(FalseVal.getNode(),
2672 FalseVal.getResNo() + i));
2674 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2675 DAG.getVTList(&ValueVTs[0], NumValues),
2676 &Values[0], NumValues));
2679 void SelectionDAGBuilder::visitTrunc(const User &I) {
2680 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2681 SDValue N = getValue(I.getOperand(0));
2682 EVT DestVT = TLI.getValueType(I.getType());
2683 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2686 void SelectionDAGBuilder::visitZExt(const User &I) {
2687 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2688 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2689 SDValue N = getValue(I.getOperand(0));
2690 EVT DestVT = TLI.getValueType(I.getType());
2691 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2694 void SelectionDAGBuilder::visitSExt(const User &I) {
2695 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2696 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2697 SDValue N = getValue(I.getOperand(0));
2698 EVT DestVT = TLI.getValueType(I.getType());
2699 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2702 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2703 // FPTrunc is never a no-op cast, no need to check
2704 SDValue N = getValue(I.getOperand(0));
2705 EVT DestVT = TLI.getValueType(I.getType());
2706 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2708 DAG.getTargetConstant(0, TLI.getPointerTy())));
2711 void SelectionDAGBuilder::visitFPExt(const User &I){
2712 // FPExt is never a no-op cast, no need to check
2713 SDValue N = getValue(I.getOperand(0));
2714 EVT DestVT = TLI.getValueType(I.getType());
2715 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2718 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2719 // FPToUI is never a no-op cast, no need to check
2720 SDValue N = getValue(I.getOperand(0));
2721 EVT DestVT = TLI.getValueType(I.getType());
2722 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2725 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2726 // FPToSI is never a no-op cast, no need to check
2727 SDValue N = getValue(I.getOperand(0));
2728 EVT DestVT = TLI.getValueType(I.getType());
2729 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2732 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2733 // UIToFP is never a no-op cast, no need to check
2734 SDValue N = getValue(I.getOperand(0));
2735 EVT DestVT = TLI.getValueType(I.getType());
2736 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2739 void SelectionDAGBuilder::visitSIToFP(const User &I){
2740 // SIToFP is never a no-op cast, no need to check
2741 SDValue N = getValue(I.getOperand(0));
2742 EVT DestVT = TLI.getValueType(I.getType());
2743 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2746 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2747 // What to do depends on the size of the integer and the size of the pointer.
2748 // We can either truncate, zero extend, or no-op, accordingly.
2749 SDValue N = getValue(I.getOperand(0));
2750 EVT DestVT = TLI.getValueType(I.getType());
2751 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2754 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2755 // What to do depends on the size of the integer and the size of the pointer.
2756 // We can either truncate, zero extend, or no-op, accordingly.
2757 SDValue N = getValue(I.getOperand(0));
2758 EVT DestVT = TLI.getValueType(I.getType());
2759 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2762 void SelectionDAGBuilder::visitBitCast(const User &I) {
2763 SDValue N = getValue(I.getOperand(0));
2764 EVT DestVT = TLI.getValueType(I.getType());
2766 // BitCast assures us that source and destination are the same size so this is
2767 // either a BITCAST or a no-op.
2768 if (DestVT != N.getValueType())
2769 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2770 DestVT, N)); // convert types.
2772 setValue(&I, N); // noop cast.
2775 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2776 SDValue InVec = getValue(I.getOperand(0));
2777 SDValue InVal = getValue(I.getOperand(1));
2778 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2780 getValue(I.getOperand(2)));
2781 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2782 TLI.getValueType(I.getType()),
2783 InVec, InVal, InIdx));
2786 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2787 SDValue InVec = getValue(I.getOperand(0));
2788 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2790 getValue(I.getOperand(1)));
2791 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2792 TLI.getValueType(I.getType()), InVec, InIdx));
2795 // Utility for visitShuffleVector - Return true if every element in Mask,
2796 // begining from position Pos and ending in Pos+Size, falls within the
2797 // specified sequential range [L, L+Pos). or is undef.
2798 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2799 unsigned Pos, unsigned Size, int Low) {
2800 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2801 if (Mask[i] >= 0 && Mask[i] != Low)
2806 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2807 SDValue Src1 = getValue(I.getOperand(0));
2808 SDValue Src2 = getValue(I.getOperand(1));
2810 SmallVector<int, 8> Mask;
2811 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2812 unsigned MaskNumElts = Mask.size();
2814 EVT VT = TLI.getValueType(I.getType());
2815 EVT SrcVT = Src1.getValueType();
2816 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2818 if (SrcNumElts == MaskNumElts) {
2819 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2824 // Normalize the shuffle vector since mask and vector length don't match.
2825 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2826 // Mask is longer than the source vectors and is a multiple of the source
2827 // vectors. We can use concatenate vector to make the mask and vectors
2829 if (SrcNumElts*2 == MaskNumElts) {
2830 // First check for Src1 in low and Src2 in high
2831 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2832 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2833 // The shuffle is concatenating two vectors together.
2834 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2838 // Then check for Src2 in low and Src1 in high
2839 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2840 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2841 // The shuffle is concatenating two vectors together.
2842 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2848 // Pad both vectors with undefs to make them the same length as the mask.
2849 unsigned NumConcat = MaskNumElts / SrcNumElts;
2850 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2851 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2852 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2854 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2855 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2859 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2860 getCurDebugLoc(), VT,
2861 &MOps1[0], NumConcat);
2862 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2863 getCurDebugLoc(), VT,
2864 &MOps2[0], NumConcat);
2866 // Readjust mask for new input vector length.
2867 SmallVector<int, 8> MappedOps;
2868 for (unsigned i = 0; i != MaskNumElts; ++i) {
2870 if (Idx >= (int)SrcNumElts)
2871 Idx -= SrcNumElts - MaskNumElts;
2872 MappedOps.push_back(Idx);
2875 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2880 if (SrcNumElts > MaskNumElts) {
2881 // Analyze the access pattern of the vector to see if we can extract
2882 // two subvectors and do the shuffle. The analysis is done by calculating
2883 // the range of elements the mask access on both vectors.
2884 int MinRange[2] = { static_cast<int>(SrcNumElts),
2885 static_cast<int>(SrcNumElts)};
2886 int MaxRange[2] = {-1, -1};
2888 for (unsigned i = 0; i != MaskNumElts; ++i) {
2894 if (Idx >= (int)SrcNumElts) {
2898 if (Idx > MaxRange[Input])
2899 MaxRange[Input] = Idx;
2900 if (Idx < MinRange[Input])
2901 MinRange[Input] = Idx;
2904 // Check if the access is smaller than the vector size and can we find
2905 // a reasonable extract index.
2906 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2908 int StartIdx[2]; // StartIdx to extract from
2909 for (unsigned Input = 0; Input < 2; ++Input) {
2910 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2911 RangeUse[Input] = 0; // Unused
2912 StartIdx[Input] = 0;
2916 // Find a good start index that is a multiple of the mask length. Then
2917 // see if the rest of the elements are in range.
2918 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2919 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2920 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2921 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2924 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2925 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2928 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2929 // Extract appropriate subvector and generate a vector shuffle
2930 for (unsigned Input = 0; Input < 2; ++Input) {
2931 SDValue &Src = Input == 0 ? Src1 : Src2;
2932 if (RangeUse[Input] == 0)
2933 Src = DAG.getUNDEF(VT);
2935 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2936 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2939 // Calculate new mask.
2940 SmallVector<int, 8> MappedOps;
2941 for (unsigned i = 0; i != MaskNumElts; ++i) {
2944 if (Idx < (int)SrcNumElts)
2947 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2949 MappedOps.push_back(Idx);
2952 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2958 // We can't use either concat vectors or extract subvectors so fall back to
2959 // replacing the shuffle with extract and build vector.
2960 // to insert and build vector.
2961 EVT EltVT = VT.getVectorElementType();
2962 EVT PtrVT = TLI.getPointerTy();
2963 SmallVector<SDValue,8> Ops;
2964 for (unsigned i = 0; i != MaskNumElts; ++i) {
2969 Res = DAG.getUNDEF(EltVT);
2971 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2972 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2974 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2975 EltVT, Src, DAG.getConstant(Idx, PtrVT));
2981 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2982 VT, &Ops[0], Ops.size()));
2985 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2986 const Value *Op0 = I.getOperand(0);
2987 const Value *Op1 = I.getOperand(1);
2988 Type *AggTy = I.getType();
2989 Type *ValTy = Op1->getType();
2990 bool IntoUndef = isa<UndefValue>(Op0);
2991 bool FromUndef = isa<UndefValue>(Op1);
2993 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2995 SmallVector<EVT, 4> AggValueVTs;
2996 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2997 SmallVector<EVT, 4> ValValueVTs;
2998 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3000 unsigned NumAggValues = AggValueVTs.size();
3001 unsigned NumValValues = ValValueVTs.size();
3002 SmallVector<SDValue, 4> Values(NumAggValues);
3004 SDValue Agg = getValue(Op0);
3006 // Copy the beginning value(s) from the original aggregate.
3007 for (; i != LinearIndex; ++i)
3008 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3009 SDValue(Agg.getNode(), Agg.getResNo() + i);
3010 // Copy values from the inserted value(s).
3012 SDValue Val = getValue(Op1);
3013 for (; i != LinearIndex + NumValValues; ++i)
3014 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3015 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3017 // Copy remaining value(s) from the original aggregate.
3018 for (; i != NumAggValues; ++i)
3019 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3020 SDValue(Agg.getNode(), Agg.getResNo() + i);
3022 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3023 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3024 &Values[0], NumAggValues));
3027 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3028 const Value *Op0 = I.getOperand(0);
3029 Type *AggTy = Op0->getType();
3030 Type *ValTy = I.getType();
3031 bool OutOfUndef = isa<UndefValue>(Op0);
3033 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3035 SmallVector<EVT, 4> ValValueVTs;
3036 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3038 unsigned NumValValues = ValValueVTs.size();
3040 // Ignore a extractvalue that produces an empty object
3041 if (!NumValValues) {
3042 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3046 SmallVector<SDValue, 4> Values(NumValValues);
3048 SDValue Agg = getValue(Op0);
3049 // Copy out the selected value(s).
3050 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3051 Values[i - LinearIndex] =
3053 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3054 SDValue(Agg.getNode(), Agg.getResNo() + i);
3056 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3057 DAG.getVTList(&ValValueVTs[0], NumValValues),
3058 &Values[0], NumValValues));
3061 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3062 SDValue N = getValue(I.getOperand(0));
3063 // Note that the pointer operand may be a vector of pointers. Take the scalar
3064 // element which holds a pointer.
3065 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3067 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3069 const Value *Idx = *OI;
3070 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3071 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3074 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3075 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3076 DAG.getIntPtrConstant(Offset));
3079 Ty = StTy->getElementType(Field);
3081 Ty = cast<SequentialType>(Ty)->getElementType();
3083 // If this is a constant subscript, handle it quickly.
3084 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3085 if (CI->isZero()) continue;
3087 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3089 EVT PTy = TLI.getPointerTy();
3090 unsigned PtrBits = PTy.getSizeInBits();
3092 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3094 DAG.getConstant(Offs, MVT::i64));
3096 OffsVal = DAG.getIntPtrConstant(Offs);
3098 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3103 // N = N + Idx * ElementSize;
3104 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3105 TD->getTypeAllocSize(Ty));
3106 SDValue IdxN = getValue(Idx);
3108 // If the index is smaller or larger than intptr_t, truncate or extend
3110 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3112 // If this is a multiply by a power of two, turn it into a shl
3113 // immediately. This is a very common case.
3114 if (ElementSize != 1) {
3115 if (ElementSize.isPowerOf2()) {
3116 unsigned Amt = ElementSize.logBase2();
3117 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3118 N.getValueType(), IdxN,
3119 DAG.getConstant(Amt, IdxN.getValueType()));
3121 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3122 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3123 N.getValueType(), IdxN, Scale);
3127 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3128 N.getValueType(), N, IdxN);
3135 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3136 // If this is a fixed sized alloca in the entry block of the function,
3137 // allocate it statically on the stack.
3138 if (FuncInfo.StaticAllocaMap.count(&I))
3139 return; // getValue will auto-populate this.
3141 Type *Ty = I.getAllocatedType();
3142 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3144 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3147 SDValue AllocSize = getValue(I.getArraySize());
3149 EVT IntPtr = TLI.getPointerTy();
3150 if (AllocSize.getValueType() != IntPtr)
3151 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3153 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3155 DAG.getConstant(TySize, IntPtr));
3157 // Handle alignment. If the requested alignment is less than or equal to
3158 // the stack alignment, ignore it. If the size is greater than or equal to
3159 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3160 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3161 if (Align <= StackAlign)
3164 // Round the size of the allocation up to the stack alignment size
3165 // by add SA-1 to the size.
3166 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3167 AllocSize.getValueType(), AllocSize,
3168 DAG.getIntPtrConstant(StackAlign-1));
3170 // Mask out the low bits for alignment purposes.
3171 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3172 AllocSize.getValueType(), AllocSize,
3173 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3175 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3176 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3177 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3180 DAG.setRoot(DSA.getValue(1));
3182 // Inform the Frame Information that we have just allocated a variable-sized
3184 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3187 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3189 return visitAtomicLoad(I);
3191 const Value *SV = I.getOperand(0);
3192 SDValue Ptr = getValue(SV);
3194 Type *Ty = I.getType();
3196 bool isVolatile = I.isVolatile();
3197 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3198 bool isInvariant = I.getMetadata("invariant.load") != 0;
3199 unsigned Alignment = I.getAlignment();
3200 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3201 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3203 SmallVector<EVT, 4> ValueVTs;
3204 SmallVector<uint64_t, 4> Offsets;
3205 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3206 unsigned NumValues = ValueVTs.size();
3211 bool ConstantMemory = false;
3212 if (I.isVolatile() || NumValues > MaxParallelChains)
3213 // Serialize volatile loads with other side effects.
3215 else if (AA->pointsToConstantMemory(
3216 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3217 // Do not serialize (non-volatile) loads of constant memory with anything.
3218 Root = DAG.getEntryNode();
3219 ConstantMemory = true;
3221 // Do not serialize non-volatile loads against each other.
3222 Root = DAG.getRoot();
3225 SmallVector<SDValue, 4> Values(NumValues);
3226 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3228 EVT PtrVT = Ptr.getValueType();
3229 unsigned ChainI = 0;
3230 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3231 // Serializing loads here may result in excessive register pressure, and
3232 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3233 // could recover a bit by hoisting nodes upward in the chain by recognizing
3234 // they are side-effect free or do not alias. The optimizer should really
3235 // avoid this case by converting large object/array copies to llvm.memcpy
3236 // (MaxParallelChains should always remain as failsafe).
3237 if (ChainI == MaxParallelChains) {
3238 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3239 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3240 MVT::Other, &Chains[0], ChainI);
3244 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3246 DAG.getConstant(Offsets[i], PtrVT));
3247 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3248 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3249 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3253 Chains[ChainI] = L.getValue(1);
3256 if (!ConstantMemory) {
3257 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3258 MVT::Other, &Chains[0], ChainI);
3262 PendingLoads.push_back(Chain);
3265 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3266 DAG.getVTList(&ValueVTs[0], NumValues),
3267 &Values[0], NumValues));
3270 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3272 return visitAtomicStore(I);
3274 const Value *SrcV = I.getOperand(0);
3275 const Value *PtrV = I.getOperand(1);
3277 SmallVector<EVT, 4> ValueVTs;
3278 SmallVector<uint64_t, 4> Offsets;
3279 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3280 unsigned NumValues = ValueVTs.size();
3284 // Get the lowered operands. Note that we do this after
3285 // checking if NumResults is zero, because with zero results
3286 // the operands won't have values in the map.
3287 SDValue Src = getValue(SrcV);
3288 SDValue Ptr = getValue(PtrV);
3290 SDValue Root = getRoot();
3291 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3293 EVT PtrVT = Ptr.getValueType();
3294 bool isVolatile = I.isVolatile();
3295 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3296 unsigned Alignment = I.getAlignment();
3297 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3299 unsigned ChainI = 0;
3300 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3301 // See visitLoad comments.
3302 if (ChainI == MaxParallelChains) {
3303 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3304 MVT::Other, &Chains[0], ChainI);
3308 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3309 DAG.getConstant(Offsets[i], PtrVT));
3310 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3311 SDValue(Src.getNode(), Src.getResNo() + i),
3312 Add, MachinePointerInfo(PtrV, Offsets[i]),
3313 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3314 Chains[ChainI] = St;
3317 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3318 MVT::Other, &Chains[0], ChainI);
3320 AssignOrderingToNode(StoreNode.getNode());
3321 DAG.setRoot(StoreNode);
3324 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3325 SynchronizationScope Scope,
3326 bool Before, DebugLoc dl,
3328 const TargetLowering &TLI) {
3329 // Fence, if necessary
3331 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3333 else if (Order == Acquire || Order == Monotonic)
3336 if (Order == AcquireRelease)
3338 else if (Order == Release || Order == Monotonic)
3343 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3344 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3345 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3348 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3349 DebugLoc dl = getCurDebugLoc();
3350 AtomicOrdering Order = I.getOrdering();
3351 SynchronizationScope Scope = I.getSynchScope();
3353 SDValue InChain = getRoot();
3355 if (TLI.getInsertFencesForAtomic())
3356 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3360 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3361 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3363 getValue(I.getPointerOperand()),
3364 getValue(I.getCompareOperand()),
3365 getValue(I.getNewValOperand()),
3366 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3367 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3370 SDValue OutChain = L.getValue(1);
3372 if (TLI.getInsertFencesForAtomic())
3373 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3377 DAG.setRoot(OutChain);
3380 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3381 DebugLoc dl = getCurDebugLoc();
3383 switch (I.getOperation()) {
3384 default: llvm_unreachable("Unknown atomicrmw operation");
3385 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3386 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3387 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3388 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3389 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3390 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3391 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3392 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3393 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3394 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3395 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3397 AtomicOrdering Order = I.getOrdering();
3398 SynchronizationScope Scope = I.getSynchScope();
3400 SDValue InChain = getRoot();
3402 if (TLI.getInsertFencesForAtomic())
3403 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3407 DAG.getAtomic(NT, dl,
3408 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3410 getValue(I.getPointerOperand()),
3411 getValue(I.getValOperand()),
3412 I.getPointerOperand(), 0 /* Alignment */,
3413 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3416 SDValue OutChain = L.getValue(1);
3418 if (TLI.getInsertFencesForAtomic())
3419 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3423 DAG.setRoot(OutChain);
3426 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3427 DebugLoc dl = getCurDebugLoc();
3430 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3431 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3432 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3435 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3436 DebugLoc dl = getCurDebugLoc();
3437 AtomicOrdering Order = I.getOrdering();
3438 SynchronizationScope Scope = I.getSynchScope();
3440 SDValue InChain = getRoot();
3442 EVT VT = EVT::getEVT(I.getType());
3444 if (I.getAlignment() * 8 < VT.getSizeInBits())
3445 report_fatal_error("Cannot generate unaligned atomic load");
3448 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3449 getValue(I.getPointerOperand()),
3450 I.getPointerOperand(), I.getAlignment(),
3451 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3454 SDValue OutChain = L.getValue(1);
3456 if (TLI.getInsertFencesForAtomic())
3457 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3461 DAG.setRoot(OutChain);
3464 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3465 DebugLoc dl = getCurDebugLoc();
3467 AtomicOrdering Order = I.getOrdering();
3468 SynchronizationScope Scope = I.getSynchScope();
3470 SDValue InChain = getRoot();
3472 EVT VT = EVT::getEVT(I.getValueOperand()->getType());
3474 if (I.getAlignment() * 8 < VT.getSizeInBits())
3475 report_fatal_error("Cannot generate unaligned atomic store");
3477 if (TLI.getInsertFencesForAtomic())
3478 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3482 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3484 getValue(I.getPointerOperand()),
3485 getValue(I.getValueOperand()),
3486 I.getPointerOperand(), I.getAlignment(),
3487 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3490 if (TLI.getInsertFencesForAtomic())
3491 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3494 DAG.setRoot(OutChain);
3497 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3499 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3500 unsigned Intrinsic) {
3501 bool HasChain = !I.doesNotAccessMemory();
3502 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3504 // Build the operand list.
3505 SmallVector<SDValue, 8> Ops;
3506 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3508 // We don't need to serialize loads against other loads.
3509 Ops.push_back(DAG.getRoot());
3511 Ops.push_back(getRoot());
3515 // Info is set by getTgtMemInstrinsic
3516 TargetLowering::IntrinsicInfo Info;
3517 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3519 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3520 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3521 Info.opc == ISD::INTRINSIC_W_CHAIN)
3522 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3524 // Add all operands of the call to the operand list.
3525 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3526 SDValue Op = getValue(I.getArgOperand(i));
3530 SmallVector<EVT, 4> ValueVTs;
3531 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3534 ValueVTs.push_back(MVT::Other);
3536 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3540 if (IsTgtIntrinsic) {
3541 // This is target intrinsic that touches memory
3542 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3543 VTs, &Ops[0], Ops.size(),
3545 MachinePointerInfo(Info.ptrVal, Info.offset),
3546 Info.align, Info.vol,
3547 Info.readMem, Info.writeMem);
3548 } else if (!HasChain) {
3549 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3550 VTs, &Ops[0], Ops.size());
3551 } else if (!I.getType()->isVoidTy()) {
3552 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3553 VTs, &Ops[0], Ops.size());
3555 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3556 VTs, &Ops[0], Ops.size());
3560 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3562 PendingLoads.push_back(Chain);
3567 if (!I.getType()->isVoidTy()) {
3568 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3569 EVT VT = TLI.getValueType(PTy);
3570 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3573 setValue(&I, Result);
3575 // Assign order to result here. If the intrinsic does not produce a result,
3576 // it won't be mapped to a SDNode and visit() will not assign it an order
3579 AssignOrderingToNode(Result.getNode());
3583 /// GetSignificand - Get the significand and build it into a floating-point
3584 /// number with exponent of 1:
3586 /// Op = (Op & 0x007fffff) | 0x3f800000;
3588 /// where Op is the hexidecimal representation of floating point value.
3590 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3591 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3592 DAG.getConstant(0x007fffff, MVT::i32));
3593 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3594 DAG.getConstant(0x3f800000, MVT::i32));
3595 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3598 /// GetExponent - Get the exponent:
3600 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3602 /// where Op is the hexidecimal representation of floating point value.
3604 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3606 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3607 DAG.getConstant(0x7f800000, MVT::i32));
3608 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3609 DAG.getConstant(23, TLI.getPointerTy()));
3610 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3611 DAG.getConstant(127, MVT::i32));
3612 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3615 /// getF32Constant - Get 32-bit floating point constant.
3617 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3618 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3621 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3622 /// limited-precision mode.
3624 SelectionDAGBuilder::visitExp(const CallInst &I) {
3626 DebugLoc dl = getCurDebugLoc();
3628 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3629 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3630 SDValue Op = getValue(I.getArgOperand(0));
3632 // Put the exponent in the right bit position for later addition to the
3635 // #define LOG2OFe 1.4426950f
3636 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3637 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3638 getF32Constant(DAG, 0x3fb8aa3b));
3639 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3641 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3642 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3643 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3645 // IntegerPartOfX <<= 23;
3646 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3647 DAG.getConstant(23, TLI.getPointerTy()));
3649 if (LimitFloatPrecision <= 6) {
3650 // For floating-point precision of 6:
3652 // TwoToFractionalPartOfX =
3654 // (0.735607626f + 0.252464424f * x) * x;
3656 // error 0.0144103317, which is 6 bits
3657 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3658 getF32Constant(DAG, 0x3e814304));
3659 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3660 getF32Constant(DAG, 0x3f3c50c8));
3661 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3662 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3663 getF32Constant(DAG, 0x3f7f5e7e));
3664 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3666 // Add the exponent into the result in integer domain.
3667 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3668 TwoToFracPartOfX, IntegerPartOfX);
3670 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3671 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3672 // For floating-point precision of 12:
3674 // TwoToFractionalPartOfX =
3677 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3679 // 0.000107046256 error, which is 13 to 14 bits
3680 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3681 getF32Constant(DAG, 0x3da235e3));
3682 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3683 getF32Constant(DAG, 0x3e65b8f3));
3684 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3685 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3686 getF32Constant(DAG, 0x3f324b07));
3687 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3688 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3689 getF32Constant(DAG, 0x3f7ff8fd));
3690 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3692 // Add the exponent into the result in integer domain.
3693 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3694 TwoToFracPartOfX, IntegerPartOfX);
3696 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3697 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3698 // For floating-point precision of 18:
3700 // TwoToFractionalPartOfX =
3704 // (0.554906021e-1f +
3705 // (0.961591928e-2f +
3706 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3708 // error 2.47208000*10^(-7), which is better than 18 bits
3709 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3710 getF32Constant(DAG, 0x3924b03e));
3711 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3712 getF32Constant(DAG, 0x3ab24b87));
3713 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3714 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3715 getF32Constant(DAG, 0x3c1d8c17));
3716 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3717 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3718 getF32Constant(DAG, 0x3d634a1d));
3719 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3720 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3721 getF32Constant(DAG, 0x3e75fe14));
3722 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3723 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3724 getF32Constant(DAG, 0x3f317234));
3725 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3726 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3727 getF32Constant(DAG, 0x3f800000));
3728 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3731 // Add the exponent into the result in integer domain.
3732 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3733 TwoToFracPartOfX, IntegerPartOfX);
3735 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3738 // No special expansion.
3739 result = DAG.getNode(ISD::FEXP, dl,
3740 getValue(I.getArgOperand(0)).getValueType(),
3741 getValue(I.getArgOperand(0)));
3744 setValue(&I, result);
3747 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3748 /// limited-precision mode.
3750 SelectionDAGBuilder::visitLog(const CallInst &I) {
3752 DebugLoc dl = getCurDebugLoc();
3754 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3755 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3756 SDValue Op = getValue(I.getArgOperand(0));
3757 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3759 // Scale the exponent by log(2) [0.69314718f].
3760 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3761 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3762 getF32Constant(DAG, 0x3f317218));
3764 // Get the significand and build it into a floating-point number with
3766 SDValue X = GetSignificand(DAG, Op1, dl);
3768 if (LimitFloatPrecision <= 6) {
3769 // For floating-point precision of 6:
3773 // (1.4034025f - 0.23903021f * x) * x;
3775 // error 0.0034276066, which is better than 8 bits
3776 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3777 getF32Constant(DAG, 0xbe74c456));
3778 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3779 getF32Constant(DAG, 0x3fb3a2b1));
3780 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3781 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3782 getF32Constant(DAG, 0x3f949a29));
3784 result = DAG.getNode(ISD::FADD, dl,
3785 MVT::f32, LogOfExponent, LogOfMantissa);
3786 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3787 // For floating-point precision of 12:
3793 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3795 // error 0.000061011436, which is 14 bits
3796 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3797 getF32Constant(DAG, 0xbd67b6d6));
3798 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3799 getF32Constant(DAG, 0x3ee4f4b8));
3800 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3801 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3802 getF32Constant(DAG, 0x3fbc278b));
3803 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3804 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3805 getF32Constant(DAG, 0x40348e95));
3806 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3807 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3808 getF32Constant(DAG, 0x3fdef31a));
3810 result = DAG.getNode(ISD::FADD, dl,
3811 MVT::f32, LogOfExponent, LogOfMantissa);
3812 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3813 // For floating-point precision of 18:
3821 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3823 // error 0.0000023660568, which is better than 18 bits
3824 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3825 getF32Constant(DAG, 0xbc91e5ac));
3826 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3827 getF32Constant(DAG, 0x3e4350aa));
3828 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3829 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3830 getF32Constant(DAG, 0x3f60d3e3));
3831 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3832 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3833 getF32Constant(DAG, 0x4011cdf0));
3834 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3835 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3836 getF32Constant(DAG, 0x406cfd1c));
3837 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3838 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3839 getF32Constant(DAG, 0x408797cb));
3840 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3841 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3842 getF32Constant(DAG, 0x4006dcab));
3844 result = DAG.getNode(ISD::FADD, dl,
3845 MVT::f32, LogOfExponent, LogOfMantissa);
3848 // No special expansion.
3849 result = DAG.getNode(ISD::FLOG, dl,
3850 getValue(I.getArgOperand(0)).getValueType(),
3851 getValue(I.getArgOperand(0)));
3854 setValue(&I, result);
3857 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3858 /// limited-precision mode.
3860 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3862 DebugLoc dl = getCurDebugLoc();
3864 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3865 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3866 SDValue Op = getValue(I.getArgOperand(0));
3867 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3869 // Get the exponent.
3870 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3872 // Get the significand and build it into a floating-point number with
3874 SDValue X = GetSignificand(DAG, Op1, dl);
3876 // Different possible minimax approximations of significand in
3877 // floating-point for various degrees of accuracy over [1,2].
3878 if (LimitFloatPrecision <= 6) {
3879 // For floating-point precision of 6:
3881 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3883 // error 0.0049451742, which is more than 7 bits
3884 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3885 getF32Constant(DAG, 0xbeb08fe0));
3886 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3887 getF32Constant(DAG, 0x40019463));
3888 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3889 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3890 getF32Constant(DAG, 0x3fd6633d));
3892 result = DAG.getNode(ISD::FADD, dl,
3893 MVT::f32, LogOfExponent, Log2ofMantissa);
3894 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3895 // For floating-point precision of 12:
3901 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3903 // error 0.0000876136000, which is better than 13 bits
3904 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3905 getF32Constant(DAG, 0xbda7262e));
3906 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3907 getF32Constant(DAG, 0x3f25280b));
3908 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3909 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3910 getF32Constant(DAG, 0x4007b923));
3911 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3912 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3913 getF32Constant(DAG, 0x40823e2f));
3914 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3915 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3916 getF32Constant(DAG, 0x4020d29c));
3918 result = DAG.getNode(ISD::FADD, dl,
3919 MVT::f32, LogOfExponent, Log2ofMantissa);
3920 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3921 // For floating-point precision of 18:
3930 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3932 // error 0.0000018516, which is better than 18 bits
3933 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3934 getF32Constant(DAG, 0xbcd2769e));
3935 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3936 getF32Constant(DAG, 0x3e8ce0b9));
3937 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3938 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3939 getF32Constant(DAG, 0x3fa22ae7));
3940 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3941 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3942 getF32Constant(DAG, 0x40525723));
3943 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3944 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3945 getF32Constant(DAG, 0x40aaf200));
3946 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3947 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3948 getF32Constant(DAG, 0x40c39dad));
3949 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3950 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3951 getF32Constant(DAG, 0x4042902c));
3953 result = DAG.getNode(ISD::FADD, dl,
3954 MVT::f32, LogOfExponent, Log2ofMantissa);
3957 // No special expansion.
3958 result = DAG.getNode(ISD::FLOG2, dl,
3959 getValue(I.getArgOperand(0)).getValueType(),
3960 getValue(I.getArgOperand(0)));
3963 setValue(&I, result);
3966 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3967 /// limited-precision mode.
3969 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3971 DebugLoc dl = getCurDebugLoc();
3973 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3974 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3975 SDValue Op = getValue(I.getArgOperand(0));
3976 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3978 // Scale the exponent by log10(2) [0.30102999f].
3979 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3980 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3981 getF32Constant(DAG, 0x3e9a209a));
3983 // Get the significand and build it into a floating-point number with
3985 SDValue X = GetSignificand(DAG, Op1, dl);
3987 if (LimitFloatPrecision <= 6) {
3988 // For floating-point precision of 6:
3990 // Log10ofMantissa =
3992 // (0.60948995f - 0.10380950f * x) * x;
3994 // error 0.0014886165, which is 6 bits
3995 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3996 getF32Constant(DAG, 0xbdd49a13));
3997 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3998 getF32Constant(DAG, 0x3f1c0789));
3999 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4000 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4001 getF32Constant(DAG, 0x3f011300));
4003 result = DAG.getNode(ISD::FADD, dl,
4004 MVT::f32, LogOfExponent, Log10ofMantissa);
4005 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4006 // For floating-point precision of 12:
4008 // Log10ofMantissa =
4011 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4013 // error 0.00019228036, which is better than 12 bits
4014 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4015 getF32Constant(DAG, 0x3d431f31));
4016 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4017 getF32Constant(DAG, 0x3ea21fb2));
4018 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4019 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4020 getF32Constant(DAG, 0x3f6ae232));
4021 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4022 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4023 getF32Constant(DAG, 0x3f25f7c3));
4025 result = DAG.getNode(ISD::FADD, dl,
4026 MVT::f32, LogOfExponent, Log10ofMantissa);
4027 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4028 // For floating-point precision of 18:
4030 // Log10ofMantissa =
4035 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4037 // error 0.0000037995730, which is better than 18 bits
4038 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4039 getF32Constant(DAG, 0x3c5d51ce));
4040 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4041 getF32Constant(DAG, 0x3e00685a));
4042 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4043 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4044 getF32Constant(DAG, 0x3efb6798));
4045 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4046 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4047 getF32Constant(DAG, 0x3f88d192));
4048 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4049 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4050 getF32Constant(DAG, 0x3fc4316c));
4051 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4052 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4053 getF32Constant(DAG, 0x3f57ce70));
4055 result = DAG.getNode(ISD::FADD, dl,
4056 MVT::f32, LogOfExponent, Log10ofMantissa);
4059 // No special expansion.
4060 result = DAG.getNode(ISD::FLOG10, dl,
4061 getValue(I.getArgOperand(0)).getValueType(),
4062 getValue(I.getArgOperand(0)));
4065 setValue(&I, result);
4068 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4069 /// limited-precision mode.
4071 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4073 DebugLoc dl = getCurDebugLoc();
4075 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4076 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4077 SDValue Op = getValue(I.getArgOperand(0));
4079 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4081 // FractionalPartOfX = x - (float)IntegerPartOfX;
4082 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4083 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4085 // IntegerPartOfX <<= 23;
4086 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4087 DAG.getConstant(23, TLI.getPointerTy()));
4089 if (LimitFloatPrecision <= 6) {
4090 // For floating-point precision of 6:
4092 // TwoToFractionalPartOfX =
4094 // (0.735607626f + 0.252464424f * x) * x;
4096 // error 0.0144103317, which is 6 bits
4097 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4098 getF32Constant(DAG, 0x3e814304));
4099 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4100 getF32Constant(DAG, 0x3f3c50c8));
4101 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4102 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4103 getF32Constant(DAG, 0x3f7f5e7e));
4104 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4105 SDValue TwoToFractionalPartOfX =
4106 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4108 result = DAG.getNode(ISD::BITCAST, dl,
4109 MVT::f32, TwoToFractionalPartOfX);
4110 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4111 // For floating-point precision of 12:
4113 // TwoToFractionalPartOfX =
4116 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4118 // error 0.000107046256, which is 13 to 14 bits
4119 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4120 getF32Constant(DAG, 0x3da235e3));
4121 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4122 getF32Constant(DAG, 0x3e65b8f3));
4123 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4124 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4125 getF32Constant(DAG, 0x3f324b07));
4126 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4127 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4128 getF32Constant(DAG, 0x3f7ff8fd));
4129 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4130 SDValue TwoToFractionalPartOfX =
4131 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4133 result = DAG.getNode(ISD::BITCAST, dl,
4134 MVT::f32, TwoToFractionalPartOfX);
4135 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4136 // For floating-point precision of 18:
4138 // TwoToFractionalPartOfX =
4142 // (0.554906021e-1f +
4143 // (0.961591928e-2f +
4144 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4145 // error 2.47208000*10^(-7), which is better than 18 bits
4146 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4147 getF32Constant(DAG, 0x3924b03e));
4148 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4149 getF32Constant(DAG, 0x3ab24b87));
4150 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4151 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4152 getF32Constant(DAG, 0x3c1d8c17));
4153 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4154 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4155 getF32Constant(DAG, 0x3d634a1d));
4156 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4157 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4158 getF32Constant(DAG, 0x3e75fe14));
4159 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4160 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4161 getF32Constant(DAG, 0x3f317234));
4162 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4163 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4164 getF32Constant(DAG, 0x3f800000));
4165 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4166 SDValue TwoToFractionalPartOfX =
4167 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4169 result = DAG.getNode(ISD::BITCAST, dl,
4170 MVT::f32, TwoToFractionalPartOfX);
4173 // No special expansion.
4174 result = DAG.getNode(ISD::FEXP2, dl,
4175 getValue(I.getArgOperand(0)).getValueType(),
4176 getValue(I.getArgOperand(0)));
4179 setValue(&I, result);
4182 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4183 /// limited-precision mode with x == 10.0f.
4185 SelectionDAGBuilder::visitPow(const CallInst &I) {
4187 const Value *Val = I.getArgOperand(0);
4188 DebugLoc dl = getCurDebugLoc();
4189 bool IsExp10 = false;
4191 if (getValue(Val).getValueType() == MVT::f32 &&
4192 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4193 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4194 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4195 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4197 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4202 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4203 SDValue Op = getValue(I.getArgOperand(1));
4205 // Put the exponent in the right bit position for later addition to the
4208 // #define LOG2OF10 3.3219281f
4209 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4210 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4211 getF32Constant(DAG, 0x40549a78));
4212 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4214 // FractionalPartOfX = x - (float)IntegerPartOfX;
4215 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4216 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4218 // IntegerPartOfX <<= 23;
4219 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4220 DAG.getConstant(23, TLI.getPointerTy()));
4222 if (LimitFloatPrecision <= 6) {
4223 // For floating-point precision of 6:
4225 // twoToFractionalPartOfX =
4227 // (0.735607626f + 0.252464424f * x) * x;
4229 // error 0.0144103317, which is 6 bits
4230 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4231 getF32Constant(DAG, 0x3e814304));
4232 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4233 getF32Constant(DAG, 0x3f3c50c8));
4234 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4235 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4236 getF32Constant(DAG, 0x3f7f5e7e));
4237 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4238 SDValue TwoToFractionalPartOfX =
4239 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4241 result = DAG.getNode(ISD::BITCAST, dl,
4242 MVT::f32, TwoToFractionalPartOfX);
4243 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4244 // For floating-point precision of 12:
4246 // TwoToFractionalPartOfX =
4249 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4251 // error 0.000107046256, which is 13 to 14 bits
4252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4253 getF32Constant(DAG, 0x3da235e3));
4254 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4255 getF32Constant(DAG, 0x3e65b8f3));
4256 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4257 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4258 getF32Constant(DAG, 0x3f324b07));
4259 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4260 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4261 getF32Constant(DAG, 0x3f7ff8fd));
4262 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4263 SDValue TwoToFractionalPartOfX =
4264 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4266 result = DAG.getNode(ISD::BITCAST, dl,
4267 MVT::f32, TwoToFractionalPartOfX);
4268 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4269 // For floating-point precision of 18:
4271 // TwoToFractionalPartOfX =
4275 // (0.554906021e-1f +
4276 // (0.961591928e-2f +
4277 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4278 // error 2.47208000*10^(-7), which is better than 18 bits
4279 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4280 getF32Constant(DAG, 0x3924b03e));
4281 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4282 getF32Constant(DAG, 0x3ab24b87));
4283 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4284 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4285 getF32Constant(DAG, 0x3c1d8c17));
4286 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4287 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4288 getF32Constant(DAG, 0x3d634a1d));
4289 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4290 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4291 getF32Constant(DAG, 0x3e75fe14));
4292 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4293 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4294 getF32Constant(DAG, 0x3f317234));
4295 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4296 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4297 getF32Constant(DAG, 0x3f800000));
4298 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4299 SDValue TwoToFractionalPartOfX =
4300 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4302 result = DAG.getNode(ISD::BITCAST, dl,
4303 MVT::f32, TwoToFractionalPartOfX);
4306 // No special expansion.
4307 result = DAG.getNode(ISD::FPOW, dl,
4308 getValue(I.getArgOperand(0)).getValueType(),
4309 getValue(I.getArgOperand(0)),
4310 getValue(I.getArgOperand(1)));
4313 setValue(&I, result);
4317 /// ExpandPowI - Expand a llvm.powi intrinsic.
4318 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4319 SelectionDAG &DAG) {
4320 // If RHS is a constant, we can expand this out to a multiplication tree,
4321 // otherwise we end up lowering to a call to __powidf2 (for example). When
4322 // optimizing for size, we only want to do this if the expansion would produce
4323 // a small number of multiplies, otherwise we do the full expansion.
4324 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4325 // Get the exponent as a positive value.
4326 unsigned Val = RHSC->getSExtValue();
4327 if ((int)Val < 0) Val = -Val;
4329 // powi(x, 0) -> 1.0
4331 return DAG.getConstantFP(1.0, LHS.getValueType());
4333 const Function *F = DAG.getMachineFunction().getFunction();
4334 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4335 // If optimizing for size, don't insert too many multiplies. This
4336 // inserts up to 5 multiplies.
4337 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4338 // We use the simple binary decomposition method to generate the multiply
4339 // sequence. There are more optimal ways to do this (for example,
4340 // powi(x,15) generates one more multiply than it should), but this has
4341 // the benefit of being both really simple and much better than a libcall.
4342 SDValue Res; // Logically starts equal to 1.0
4343 SDValue CurSquare = LHS;
4347 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4349 Res = CurSquare; // 1.0*CurSquare.
4352 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4353 CurSquare, CurSquare);
4357 // If the original was negative, invert the result, producing 1/(x*x*x).
4358 if (RHSC->getSExtValue() < 0)
4359 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4360 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4365 // Otherwise, expand to a libcall.
4366 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4369 // getTruncatedArgReg - Find underlying register used for an truncated
4371 static unsigned getTruncatedArgReg(const SDValue &N) {
4372 if (N.getOpcode() != ISD::TRUNCATE)
4375 const SDValue &Ext = N.getOperand(0);
4376 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4377 const SDValue &CFR = Ext.getOperand(0);
4378 if (CFR.getOpcode() == ISD::CopyFromReg)
4379 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4380 if (CFR.getOpcode() == ISD::TRUNCATE)
4381 return getTruncatedArgReg(CFR);
4386 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4387 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4388 /// At the end of instruction selection, they will be inserted to the entry BB.
4390 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4393 const Argument *Arg = dyn_cast<Argument>(V);
4397 MachineFunction &MF = DAG.getMachineFunction();
4398 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4399 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4401 // Ignore inlined function arguments here.
4402 DIVariable DV(Variable);
4403 if (DV.isInlinedFnArgument(MF.getFunction()))
4407 // Some arguments' frame index is recorded during argument lowering.
4408 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4410 Reg = TRI->getFrameRegister(MF);
4412 if (!Reg && N.getNode()) {
4413 if (N.getOpcode() == ISD::CopyFromReg)
4414 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4416 Reg = getTruncatedArgReg(N);
4417 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4418 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4419 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4426 // Check if ValueMap has reg number.
4427 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4428 if (VMI != FuncInfo.ValueMap.end())
4432 if (!Reg && N.getNode()) {
4433 // Check if frame index is available.
4434 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4435 if (FrameIndexSDNode *FINode =
4436 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4437 Reg = TRI->getFrameRegister(MF);
4438 Offset = FINode->getIndex();
4445 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4446 TII->get(TargetOpcode::DBG_VALUE))
4447 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4448 FuncInfo.ArgDbgValues.push_back(&*MIB);
4452 // VisualStudio defines setjmp as _setjmp
4453 #if defined(_MSC_VER) && defined(setjmp) && \
4454 !defined(setjmp_undefined_for_msvc)
4455 # pragma push_macro("setjmp")
4457 # define setjmp_undefined_for_msvc
4460 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4461 /// we want to emit this as a call to a named external function, return the name
4462 /// otherwise lower it and return null.
4464 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4465 DebugLoc dl = getCurDebugLoc();
4468 switch (Intrinsic) {
4470 // By default, turn this into a target intrinsic node.
4471 visitTargetIntrinsic(I, Intrinsic);
4473 case Intrinsic::vastart: visitVAStart(I); return 0;
4474 case Intrinsic::vaend: visitVAEnd(I); return 0;
4475 case Intrinsic::vacopy: visitVACopy(I); return 0;
4476 case Intrinsic::returnaddress:
4477 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4478 getValue(I.getArgOperand(0))));
4480 case Intrinsic::frameaddress:
4481 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4482 getValue(I.getArgOperand(0))));
4484 case Intrinsic::setjmp:
4485 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4486 case Intrinsic::longjmp:
4487 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4488 case Intrinsic::memcpy: {
4489 // Assert for address < 256 since we support only user defined address
4491 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4493 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4495 "Unknown address space");
4496 SDValue Op1 = getValue(I.getArgOperand(0));
4497 SDValue Op2 = getValue(I.getArgOperand(1));
4498 SDValue Op3 = getValue(I.getArgOperand(2));
4499 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4500 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4501 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4502 MachinePointerInfo(I.getArgOperand(0)),
4503 MachinePointerInfo(I.getArgOperand(1))));
4506 case Intrinsic::memset: {
4507 // Assert for address < 256 since we support only user defined address
4509 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4511 "Unknown address space");
4512 SDValue Op1 = getValue(I.getArgOperand(0));
4513 SDValue Op2 = getValue(I.getArgOperand(1));
4514 SDValue Op3 = getValue(I.getArgOperand(2));
4515 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4516 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4517 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4518 MachinePointerInfo(I.getArgOperand(0))));
4521 case Intrinsic::memmove: {
4522 // Assert for address < 256 since we support only user defined address
4524 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4526 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4528 "Unknown address space");
4529 SDValue Op1 = getValue(I.getArgOperand(0));
4530 SDValue Op2 = getValue(I.getArgOperand(1));
4531 SDValue Op3 = getValue(I.getArgOperand(2));
4532 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4533 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4534 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4535 MachinePointerInfo(I.getArgOperand(0)),
4536 MachinePointerInfo(I.getArgOperand(1))));
4539 case Intrinsic::dbg_declare: {
4540 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4541 MDNode *Variable = DI.getVariable();
4542 const Value *Address = DI.getAddress();
4543 if (!Address || !DIVariable(Variable).Verify()) {
4544 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4548 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4549 // but do not always have a corresponding SDNode built. The SDNodeOrder
4550 // absolute, but not relative, values are different depending on whether
4551 // debug info exists.
4554 // Check if address has undef value.
4555 if (isa<UndefValue>(Address) ||
4556 (Address->use_empty() && !isa<Argument>(Address))) {
4557 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4561 SDValue &N = NodeMap[Address];
4562 if (!N.getNode() && isa<Argument>(Address))
4563 // Check unused arguments map.
4564 N = UnusedArgNodeMap[Address];
4567 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4568 Address = BCI->getOperand(0);
4569 // Parameters are handled specially.
4571 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4572 isa<Argument>(Address));
4574 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4576 if (isParameter && !AI) {
4577 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4579 // Byval parameter. We have a frame index at this point.
4580 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4581 0, dl, SDNodeOrder);
4583 // Address is an argument, so try to emit its dbg value using
4584 // virtual register info from the FuncInfo.ValueMap.
4585 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4589 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4590 0, dl, SDNodeOrder);
4592 // Can't do anything with other non-AI cases yet.
4593 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4594 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4595 DEBUG(Address->dump());
4598 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4600 // If Address is an argument then try to emit its dbg value using
4601 // virtual register info from the FuncInfo.ValueMap.
4602 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4603 // If variable is pinned by a alloca in dominating bb then
4604 // use StaticAllocaMap.
4605 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4606 if (AI->getParent() != DI.getParent()) {
4607 DenseMap<const AllocaInst*, int>::iterator SI =
4608 FuncInfo.StaticAllocaMap.find(AI);
4609 if (SI != FuncInfo.StaticAllocaMap.end()) {
4610 SDV = DAG.getDbgValue(Variable, SI->second,
4611 0, dl, SDNodeOrder);
4612 DAG.AddDbgValue(SDV, 0, false);
4617 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4622 case Intrinsic::dbg_value: {
4623 const DbgValueInst &DI = cast<DbgValueInst>(I);
4624 if (!DIVariable(DI.getVariable()).Verify())
4627 MDNode *Variable = DI.getVariable();
4628 uint64_t Offset = DI.getOffset();
4629 const Value *V = DI.getValue();
4633 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4634 // but do not always have a corresponding SDNode built. The SDNodeOrder
4635 // absolute, but not relative, values are different depending on whether
4636 // debug info exists.
4639 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4640 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4641 DAG.AddDbgValue(SDV, 0, false);
4643 // Do not use getValue() in here; we don't want to generate code at
4644 // this point if it hasn't been done yet.
4645 SDValue N = NodeMap[V];
4646 if (!N.getNode() && isa<Argument>(V))
4647 // Check unused arguments map.
4648 N = UnusedArgNodeMap[V];
4650 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4651 SDV = DAG.getDbgValue(Variable, N.getNode(),
4652 N.getResNo(), Offset, dl, SDNodeOrder);
4653 DAG.AddDbgValue(SDV, N.getNode(), false);
4655 } else if (!V->use_empty() ) {
4656 // Do not call getValue(V) yet, as we don't want to generate code.
4657 // Remember it for later.
4658 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4659 DanglingDebugInfoMap[V] = DDI;
4661 // We may expand this to cover more cases. One case where we have no
4662 // data available is an unreferenced parameter.
4663 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4667 // Build a debug info table entry.
4668 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4669 V = BCI->getOperand(0);
4670 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4671 // Don't handle byval struct arguments or VLAs, for example.
4673 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4674 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4677 DenseMap<const AllocaInst*, int>::iterator SI =
4678 FuncInfo.StaticAllocaMap.find(AI);
4679 if (SI == FuncInfo.StaticAllocaMap.end())
4681 int FI = SI->second;
4683 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4684 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4685 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4689 case Intrinsic::eh_typeid_for: {
4690 // Find the type id for the given typeinfo.
4691 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4692 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4693 Res = DAG.getConstant(TypeID, MVT::i32);
4698 case Intrinsic::eh_return_i32:
4699 case Intrinsic::eh_return_i64:
4700 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4701 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4704 getValue(I.getArgOperand(0)),
4705 getValue(I.getArgOperand(1))));
4707 case Intrinsic::eh_unwind_init:
4708 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4710 case Intrinsic::eh_dwarf_cfa: {
4711 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4712 TLI.getPointerTy());
4713 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4715 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4716 TLI.getPointerTy()),
4718 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4720 DAG.getConstant(0, TLI.getPointerTy()));
4721 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4725 case Intrinsic::eh_sjlj_callsite: {
4726 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4727 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4728 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4729 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4731 MMI.setCurrentCallSite(CI->getZExtValue());
4734 case Intrinsic::eh_sjlj_functioncontext: {
4735 // Get and store the index of the function context.
4736 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4738 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4739 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4740 MFI->setFunctionContextIndex(FI);
4743 case Intrinsic::eh_sjlj_setjmp: {
4746 Ops[1] = getValue(I.getArgOperand(0));
4747 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4748 DAG.getVTList(MVT::i32, MVT::Other),
4750 setValue(&I, Op.getValue(0));
4751 DAG.setRoot(Op.getValue(1));
4754 case Intrinsic::eh_sjlj_longjmp: {
4755 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4756 getRoot(), getValue(I.getArgOperand(0))));
4760 case Intrinsic::x86_mmx_pslli_w:
4761 case Intrinsic::x86_mmx_pslli_d:
4762 case Intrinsic::x86_mmx_pslli_q:
4763 case Intrinsic::x86_mmx_psrli_w:
4764 case Intrinsic::x86_mmx_psrli_d:
4765 case Intrinsic::x86_mmx_psrli_q:
4766 case Intrinsic::x86_mmx_psrai_w:
4767 case Intrinsic::x86_mmx_psrai_d: {
4768 SDValue ShAmt = getValue(I.getArgOperand(1));
4769 if (isa<ConstantSDNode>(ShAmt)) {
4770 visitTargetIntrinsic(I, Intrinsic);
4773 unsigned NewIntrinsic = 0;
4774 EVT ShAmtVT = MVT::v2i32;
4775 switch (Intrinsic) {
4776 case Intrinsic::x86_mmx_pslli_w:
4777 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4779 case Intrinsic::x86_mmx_pslli_d:
4780 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4782 case Intrinsic::x86_mmx_pslli_q:
4783 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4785 case Intrinsic::x86_mmx_psrli_w:
4786 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4788 case Intrinsic::x86_mmx_psrli_d:
4789 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4791 case Intrinsic::x86_mmx_psrli_q:
4792 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4794 case Intrinsic::x86_mmx_psrai_w:
4795 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4797 case Intrinsic::x86_mmx_psrai_d:
4798 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4800 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4803 // The vector shift intrinsics with scalars uses 32b shift amounts but
4804 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4806 // We must do this early because v2i32 is not a legal type.
4807 DebugLoc dl = getCurDebugLoc();
4810 ShOps[1] = DAG.getConstant(0, MVT::i32);
4811 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4812 EVT DestVT = TLI.getValueType(I.getType());
4813 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4814 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4815 DAG.getConstant(NewIntrinsic, MVT::i32),
4816 getValue(I.getArgOperand(0)), ShAmt);
4820 case Intrinsic::x86_avx_vinsertf128_pd_256:
4821 case Intrinsic::x86_avx_vinsertf128_ps_256:
4822 case Intrinsic::x86_avx_vinsertf128_si_256:
4823 case Intrinsic::x86_avx2_vinserti128: {
4824 DebugLoc dl = getCurDebugLoc();
4825 EVT DestVT = TLI.getValueType(I.getType());
4826 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4827 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4828 ElVT.getVectorNumElements();
4829 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4830 getValue(I.getArgOperand(0)),
4831 getValue(I.getArgOperand(1)),
4832 DAG.getConstant(Idx, MVT::i32));
4836 case Intrinsic::convertff:
4837 case Intrinsic::convertfsi:
4838 case Intrinsic::convertfui:
4839 case Intrinsic::convertsif:
4840 case Intrinsic::convertuif:
4841 case Intrinsic::convertss:
4842 case Intrinsic::convertsu:
4843 case Intrinsic::convertus:
4844 case Intrinsic::convertuu: {
4845 ISD::CvtCode Code = ISD::CVT_INVALID;
4846 switch (Intrinsic) {
4847 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4848 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4849 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4850 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4851 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4852 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4853 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4854 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4855 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4856 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4858 EVT DestVT = TLI.getValueType(I.getType());
4859 const Value *Op1 = I.getArgOperand(0);
4860 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4861 DAG.getValueType(DestVT),
4862 DAG.getValueType(getValue(Op1).getValueType()),
4863 getValue(I.getArgOperand(1)),
4864 getValue(I.getArgOperand(2)),
4869 case Intrinsic::sqrt:
4870 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4871 getValue(I.getArgOperand(0)).getValueType(),
4872 getValue(I.getArgOperand(0))));
4874 case Intrinsic::powi:
4875 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4876 getValue(I.getArgOperand(1)), DAG));
4878 case Intrinsic::sin:
4879 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4880 getValue(I.getArgOperand(0)).getValueType(),
4881 getValue(I.getArgOperand(0))));
4883 case Intrinsic::cos:
4884 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4885 getValue(I.getArgOperand(0)).getValueType(),
4886 getValue(I.getArgOperand(0))));
4888 case Intrinsic::log:
4891 case Intrinsic::log2:
4894 case Intrinsic::log10:
4897 case Intrinsic::exp:
4900 case Intrinsic::exp2:
4903 case Intrinsic::pow:
4906 case Intrinsic::fma:
4907 setValue(&I, DAG.getNode(ISD::FMA, dl,
4908 getValue(I.getArgOperand(0)).getValueType(),
4909 getValue(I.getArgOperand(0)),
4910 getValue(I.getArgOperand(1)),
4911 getValue(I.getArgOperand(2))));
4913 case Intrinsic::convert_to_fp16:
4914 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4915 MVT::i16, getValue(I.getArgOperand(0))));
4917 case Intrinsic::convert_from_fp16:
4918 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4919 MVT::f32, getValue(I.getArgOperand(0))));
4921 case Intrinsic::pcmarker: {
4922 SDValue Tmp = getValue(I.getArgOperand(0));
4923 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4926 case Intrinsic::readcyclecounter: {
4927 SDValue Op = getRoot();
4928 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4929 DAG.getVTList(MVT::i64, MVT::Other),
4932 DAG.setRoot(Res.getValue(1));
4935 case Intrinsic::bswap:
4936 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4937 getValue(I.getArgOperand(0)).getValueType(),
4938 getValue(I.getArgOperand(0))));
4940 case Intrinsic::cttz: {
4941 SDValue Arg = getValue(I.getArgOperand(0));
4942 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4943 EVT Ty = Arg.getValueType();
4944 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4948 case Intrinsic::ctlz: {
4949 SDValue Arg = getValue(I.getArgOperand(0));
4950 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4951 EVT Ty = Arg.getValueType();
4952 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4956 case Intrinsic::ctpop: {
4957 SDValue Arg = getValue(I.getArgOperand(0));
4958 EVT Ty = Arg.getValueType();
4959 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4962 case Intrinsic::stacksave: {
4963 SDValue Op = getRoot();
4964 Res = DAG.getNode(ISD::STACKSAVE, dl,
4965 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4967 DAG.setRoot(Res.getValue(1));
4970 case Intrinsic::stackrestore: {
4971 Res = getValue(I.getArgOperand(0));
4972 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4975 case Intrinsic::stackprotector: {
4976 // Emit code into the DAG to store the stack guard onto the stack.
4977 MachineFunction &MF = DAG.getMachineFunction();
4978 MachineFrameInfo *MFI = MF.getFrameInfo();
4979 EVT PtrTy = TLI.getPointerTy();
4981 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4982 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4984 int FI = FuncInfo.StaticAllocaMap[Slot];
4985 MFI->setStackProtectorIndex(FI);
4987 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4989 // Store the stack protector onto the stack.
4990 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4991 MachinePointerInfo::getFixedStack(FI),
4997 case Intrinsic::objectsize: {
4998 // If we don't know by now, we're never going to know.
4999 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5001 assert(CI && "Non-constant type in __builtin_object_size?");
5003 SDValue Arg = getValue(I.getCalledValue());
5004 EVT Ty = Arg.getValueType();
5007 Res = DAG.getConstant(-1ULL, Ty);
5009 Res = DAG.getConstant(0, Ty);
5014 case Intrinsic::var_annotation:
5015 // Discard annotate attributes
5018 case Intrinsic::init_trampoline: {
5019 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5023 Ops[1] = getValue(I.getArgOperand(0));
5024 Ops[2] = getValue(I.getArgOperand(1));
5025 Ops[3] = getValue(I.getArgOperand(2));
5026 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5027 Ops[5] = DAG.getSrcValue(F);
5029 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5034 case Intrinsic::adjust_trampoline: {
5035 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5037 getValue(I.getArgOperand(0))));
5040 case Intrinsic::gcroot:
5042 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5043 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5045 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5046 GFI->addStackRoot(FI->getIndex(), TypeMap);
5049 case Intrinsic::gcread:
5050 case Intrinsic::gcwrite:
5051 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5052 case Intrinsic::flt_rounds:
5053 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5056 case Intrinsic::expect: {
5057 // Just replace __builtin_expect(exp, c) with EXP.
5058 setValue(&I, getValue(I.getArgOperand(0)));
5062 case Intrinsic::trap: {
5063 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5064 if (TrapFuncName.empty()) {
5065 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5068 TargetLowering::ArgListTy Args;
5069 std::pair<SDValue, SDValue> Result =
5070 TLI.LowerCallTo(getRoot(), I.getType(),
5071 false, false, false, false, 0, CallingConv::C,
5072 /*isTailCall=*/false,
5073 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5074 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5075 Args, DAG, getCurDebugLoc());
5076 DAG.setRoot(Result.second);
5079 case Intrinsic::debugtrap: {
5080 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot()));
5083 case Intrinsic::uadd_with_overflow:
5084 case Intrinsic::sadd_with_overflow:
5085 case Intrinsic::usub_with_overflow:
5086 case Intrinsic::ssub_with_overflow:
5087 case Intrinsic::umul_with_overflow:
5088 case Intrinsic::smul_with_overflow: {
5090 switch (Intrinsic) {
5091 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5092 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5093 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5094 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5095 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5096 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5097 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5099 SDValue Op1 = getValue(I.getArgOperand(0));
5100 SDValue Op2 = getValue(I.getArgOperand(1));
5102 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5103 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
5106 case Intrinsic::prefetch: {
5108 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5110 Ops[1] = getValue(I.getArgOperand(0));
5111 Ops[2] = getValue(I.getArgOperand(1));
5112 Ops[3] = getValue(I.getArgOperand(2));
5113 Ops[4] = getValue(I.getArgOperand(3));
5114 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5115 DAG.getVTList(MVT::Other),
5117 EVT::getIntegerVT(*Context, 8),
5118 MachinePointerInfo(I.getArgOperand(0)),
5120 false, /* volatile */
5122 rw==1)); /* write */
5126 case Intrinsic::invariant_start:
5127 case Intrinsic::lifetime_start:
5128 // Discard region information.
5129 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5131 case Intrinsic::invariant_end:
5132 case Intrinsic::lifetime_end:
5133 // Discard region information.
5138 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5140 MachineBasicBlock *LandingPad) {
5141 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5142 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5143 Type *RetTy = FTy->getReturnType();
5144 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5145 MCSymbol *BeginLabel = 0;
5147 TargetLowering::ArgListTy Args;
5148 TargetLowering::ArgListEntry Entry;
5149 Args.reserve(CS.arg_size());
5151 // Check whether the function can return without sret-demotion.
5152 SmallVector<ISD::OutputArg, 4> Outs;
5153 SmallVector<uint64_t, 4> Offsets;
5154 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5155 Outs, TLI, &Offsets);
5157 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5158 DAG.getMachineFunction(),
5159 FTy->isVarArg(), Outs,
5162 SDValue DemoteStackSlot;
5163 int DemoteStackIdx = -100;
5165 if (!CanLowerReturn) {
5166 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5167 FTy->getReturnType());
5168 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5169 FTy->getReturnType());
5170 MachineFunction &MF = DAG.getMachineFunction();
5171 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5172 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5174 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5175 Entry.Node = DemoteStackSlot;
5176 Entry.Ty = StackSlotPtrType;
5177 Entry.isSExt = false;
5178 Entry.isZExt = false;
5179 Entry.isInReg = false;
5180 Entry.isSRet = true;
5181 Entry.isNest = false;
5182 Entry.isByVal = false;
5183 Entry.Alignment = Align;
5184 Args.push_back(Entry);
5185 RetTy = Type::getVoidTy(FTy->getContext());
5188 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5190 const Value *V = *i;
5193 if (V->getType()->isEmptyTy())
5196 SDValue ArgNode = getValue(V);
5197 Entry.Node = ArgNode; Entry.Ty = V->getType();
5199 unsigned attrInd = i - CS.arg_begin() + 1;
5200 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5201 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5202 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5203 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5204 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5205 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5206 Entry.Alignment = CS.getParamAlignment(attrInd);
5207 Args.push_back(Entry);
5211 // Insert a label before the invoke call to mark the try range. This can be
5212 // used to detect deletion of the invoke via the MachineModuleInfo.
5213 BeginLabel = MMI.getContext().CreateTempSymbol();
5215 // For SjLj, keep track of which landing pads go with which invokes
5216 // so as to maintain the ordering of pads in the LSDA.
5217 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5218 if (CallSiteIndex) {
5219 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5220 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5222 // Now that the call site is handled, stop tracking it.
5223 MMI.setCurrentCallSite(0);
5226 // Both PendingLoads and PendingExports must be flushed here;
5227 // this call might not return.
5229 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5232 // Check if target-independent constraints permit a tail call here.
5233 // Target-dependent constraints are checked within TLI.LowerCallTo.
5235 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5238 // If there's a possibility that fast-isel has already selected some amount
5239 // of the current basic block, don't emit a tail call.
5240 if (isTailCall && TM.Options.EnableFastISel)
5243 std::pair<SDValue,SDValue> Result =
5244 TLI.LowerCallTo(getRoot(), RetTy,
5245 CS.paramHasAttr(0, Attribute::SExt),
5246 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5247 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5248 CS.getCallingConv(),
5251 !CS.getInstruction()->use_empty(),
5252 Callee, Args, DAG, getCurDebugLoc());
5253 assert((isTailCall || Result.second.getNode()) &&
5254 "Non-null chain expected with non-tail call!");
5255 assert((Result.second.getNode() || !Result.first.getNode()) &&
5256 "Null value expected with tail call!");
5257 if (Result.first.getNode()) {
5258 setValue(CS.getInstruction(), Result.first);
5259 } else if (!CanLowerReturn && Result.second.getNode()) {
5260 // The instruction result is the result of loading from the
5261 // hidden sret parameter.
5262 SmallVector<EVT, 1> PVTs;
5263 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5265 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5266 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5267 EVT PtrVT = PVTs[0];
5268 unsigned NumValues = Outs.size();
5269 SmallVector<SDValue, 4> Values(NumValues);
5270 SmallVector<SDValue, 4> Chains(NumValues);
5272 for (unsigned i = 0; i < NumValues; ++i) {
5273 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5275 DAG.getConstant(Offsets[i], PtrVT));
5276 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5278 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5279 false, false, false, 1);
5281 Chains[i] = L.getValue(1);
5284 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5285 MVT::Other, &Chains[0], NumValues);
5286 PendingLoads.push_back(Chain);
5288 // Collect the legal value parts into potentially illegal values
5289 // that correspond to the original function's return values.
5290 SmallVector<EVT, 4> RetTys;
5291 RetTy = FTy->getReturnType();
5292 ComputeValueVTs(TLI, RetTy, RetTys);
5293 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5294 SmallVector<SDValue, 4> ReturnValues;
5295 unsigned CurReg = 0;
5296 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5298 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5299 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5301 SDValue ReturnValue =
5302 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5303 RegisterVT, VT, AssertOp);
5304 ReturnValues.push_back(ReturnValue);
5308 setValue(CS.getInstruction(),
5309 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5310 DAG.getVTList(&RetTys[0], RetTys.size()),
5311 &ReturnValues[0], ReturnValues.size()));
5314 // Assign order to nodes here. If the call does not produce a result, it won't
5315 // be mapped to a SDNode and visit() will not assign it an order number.
5316 if (!Result.second.getNode()) {
5317 // As a special case, a null chain means that a tail call has been emitted and
5318 // the DAG root is already updated.
5321 AssignOrderingToNode(DAG.getRoot().getNode());
5323 DAG.setRoot(Result.second);
5325 AssignOrderingToNode(Result.second.getNode());
5329 // Insert a label at the end of the invoke call to mark the try range. This
5330 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5331 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5332 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5334 // Inform MachineModuleInfo of range.
5335 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5339 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5340 /// value is equal or not-equal to zero.
5341 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5342 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5344 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5345 if (IC->isEquality())
5346 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5347 if (C->isNullValue())
5349 // Unknown instruction.
5355 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5357 SelectionDAGBuilder &Builder) {
5359 // Check to see if this load can be trivially constant folded, e.g. if the
5360 // input is from a string literal.
5361 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5362 // Cast pointer to the type we really want to load.
5363 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5364 PointerType::getUnqual(LoadTy));
5366 if (const Constant *LoadCst =
5367 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5369 return Builder.getValue(LoadCst);
5372 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5373 // still constant memory, the input chain can be the entry node.
5375 bool ConstantMemory = false;
5377 // Do not serialize (non-volatile) loads of constant memory with anything.
5378 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5379 Root = Builder.DAG.getEntryNode();
5380 ConstantMemory = true;
5382 // Do not serialize non-volatile loads against each other.
5383 Root = Builder.DAG.getRoot();
5386 SDValue Ptr = Builder.getValue(PtrVal);
5387 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5388 Ptr, MachinePointerInfo(PtrVal),
5390 false /*nontemporal*/,
5391 false /*isinvariant*/, 1 /* align=1 */);
5393 if (!ConstantMemory)
5394 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5399 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5400 /// If so, return true and lower it, otherwise return false and it will be
5401 /// lowered like a normal call.
5402 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5403 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5404 if (I.getNumArgOperands() != 3)
5407 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5408 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5409 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5410 !I.getType()->isIntegerTy())
5413 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5415 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5416 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5417 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5418 bool ActuallyDoIt = true;
5421 switch (Size->getZExtValue()) {
5423 LoadVT = MVT::Other;
5425 ActuallyDoIt = false;
5429 LoadTy = Type::getInt16Ty(Size->getContext());
5433 LoadTy = Type::getInt32Ty(Size->getContext());
5437 LoadTy = Type::getInt64Ty(Size->getContext());
5441 LoadVT = MVT::v4i32;
5442 LoadTy = Type::getInt32Ty(Size->getContext());
5443 LoadTy = VectorType::get(LoadTy, 4);
5448 // This turns into unaligned loads. We only do this if the target natively
5449 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5450 // we'll only produce a small number of byte loads.
5452 // Require that we can find a legal MVT, and only do this if the target
5453 // supports unaligned loads of that type. Expanding into byte loads would
5455 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5456 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5457 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5458 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5459 ActuallyDoIt = false;
5463 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5464 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5466 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5468 EVT CallVT = TLI.getValueType(I.getType(), true);
5469 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5479 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5480 // Handle inline assembly differently.
5481 if (isa<InlineAsm>(I.getCalledValue())) {
5486 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5487 ComputeUsesVAFloatArgument(I, &MMI);
5489 const char *RenameFn = 0;
5490 if (Function *F = I.getCalledFunction()) {
5491 if (F->isDeclaration()) {
5492 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5493 if (unsigned IID = II->getIntrinsicID(F)) {
5494 RenameFn = visitIntrinsicCall(I, IID);
5499 if (unsigned IID = F->getIntrinsicID()) {
5500 RenameFn = visitIntrinsicCall(I, IID);
5506 // Check for well-known libc/libm calls. If the function is internal, it
5507 // can't be a library call.
5508 if (!F->hasLocalLinkage() && F->hasName()) {
5509 StringRef Name = F->getName();
5510 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") ||
5511 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") ||
5512 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) {
5513 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5514 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5515 I.getType() == I.getArgOperand(0)->getType() &&
5516 I.getType() == I.getArgOperand(1)->getType()) {
5517 SDValue LHS = getValue(I.getArgOperand(0));
5518 SDValue RHS = getValue(I.getArgOperand(1));
5519 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5520 LHS.getValueType(), LHS, RHS));
5523 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") ||
5524 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") ||
5525 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) {
5526 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5527 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5528 I.getType() == I.getArgOperand(0)->getType()) {
5529 SDValue Tmp = getValue(I.getArgOperand(0));
5530 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5531 Tmp.getValueType(), Tmp));
5534 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") ||
5535 (LibInfo->has(LibFunc::sinf) && Name == "sinf") ||
5536 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) {
5537 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5538 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5539 I.getType() == I.getArgOperand(0)->getType() &&
5540 I.onlyReadsMemory()) {
5541 SDValue Tmp = getValue(I.getArgOperand(0));
5542 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5543 Tmp.getValueType(), Tmp));
5546 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") ||
5547 (LibInfo->has(LibFunc::cosf) && Name == "cosf") ||
5548 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) {
5549 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5550 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5551 I.getType() == I.getArgOperand(0)->getType() &&
5552 I.onlyReadsMemory()) {
5553 SDValue Tmp = getValue(I.getArgOperand(0));
5554 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5555 Tmp.getValueType(), Tmp));
5558 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") ||
5559 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") ||
5560 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) {
5561 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5562 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5563 I.getType() == I.getArgOperand(0)->getType() &&
5564 I.onlyReadsMemory()) {
5565 SDValue Tmp = getValue(I.getArgOperand(0));
5566 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5567 Tmp.getValueType(), Tmp));
5570 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") ||
5571 (LibInfo->has(LibFunc::floorf) && Name == "floorf") ||
5572 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) {
5573 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5574 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5575 I.getType() == I.getArgOperand(0)->getType()) {
5576 SDValue Tmp = getValue(I.getArgOperand(0));
5577 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(),
5578 Tmp.getValueType(), Tmp));
5581 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") ||
5582 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") ||
5583 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) {
5584 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5585 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5586 I.getType() == I.getArgOperand(0)->getType()) {
5587 SDValue Tmp = getValue(I.getArgOperand(0));
5588 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(),
5589 Tmp.getValueType(), Tmp));
5592 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") ||
5593 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") ||
5594 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) {
5595 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5596 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5597 I.getType() == I.getArgOperand(0)->getType()) {
5598 SDValue Tmp = getValue(I.getArgOperand(0));
5599 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(),
5600 Tmp.getValueType(), Tmp));
5603 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") ||
5604 (LibInfo->has(LibFunc::rintf) && Name == "rintf") ||
5605 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) {
5606 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5607 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5608 I.getType() == I.getArgOperand(0)->getType()) {
5609 SDValue Tmp = getValue(I.getArgOperand(0));
5610 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(),
5611 Tmp.getValueType(), Tmp));
5614 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") ||
5615 (LibInfo->has(LibFunc::truncf) && Name == "truncf") ||
5616 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) {
5617 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5618 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5619 I.getType() == I.getArgOperand(0)->getType()) {
5620 SDValue Tmp = getValue(I.getArgOperand(0));
5621 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(),
5622 Tmp.getValueType(), Tmp));
5625 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") ||
5626 (LibInfo->has(LibFunc::log2f) && Name == "log2f") ||
5627 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) {
5628 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5629 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5630 I.getType() == I.getArgOperand(0)->getType() &&
5631 I.onlyReadsMemory()) {
5632 SDValue Tmp = getValue(I.getArgOperand(0));
5633 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(),
5634 Tmp.getValueType(), Tmp));
5637 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") ||
5638 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") ||
5639 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) {
5640 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5641 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5642 I.getType() == I.getArgOperand(0)->getType() &&
5643 I.onlyReadsMemory()) {
5644 SDValue Tmp = getValue(I.getArgOperand(0));
5645 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(),
5646 Tmp.getValueType(), Tmp));
5649 } else if (Name == "memcmp") {
5650 if (visitMemCmpCall(I))
5658 Callee = getValue(I.getCalledValue());
5660 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5662 // Check if we can potentially perform a tail call. More detailed checking is
5663 // be done within LowerCallTo, after more information about the call is known.
5664 LowerCallTo(&I, Callee, I.isTailCall());
5669 /// AsmOperandInfo - This contains information for each constraint that we are
5671 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5673 /// CallOperand - If this is the result output operand or a clobber
5674 /// this is null, otherwise it is the incoming operand to the CallInst.
5675 /// This gets modified as the asm is processed.
5676 SDValue CallOperand;
5678 /// AssignedRegs - If this is a register or register class operand, this
5679 /// contains the set of register corresponding to the operand.
5680 RegsForValue AssignedRegs;
5682 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5683 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5686 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5687 /// corresponds to. If there is no Value* for this operand, it returns
5689 EVT getCallOperandValEVT(LLVMContext &Context,
5690 const TargetLowering &TLI,
5691 const TargetData *TD) const {
5692 if (CallOperandVal == 0) return MVT::Other;
5694 if (isa<BasicBlock>(CallOperandVal))
5695 return TLI.getPointerTy();
5697 llvm::Type *OpTy = CallOperandVal->getType();
5699 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5700 // If this is an indirect operand, the operand is a pointer to the
5703 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5705 report_fatal_error("Indirect operand for inline asm not a pointer!");
5706 OpTy = PtrTy->getElementType();
5709 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5710 if (StructType *STy = dyn_cast<StructType>(OpTy))
5711 if (STy->getNumElements() == 1)
5712 OpTy = STy->getElementType(0);
5714 // If OpTy is not a single value, it may be a struct/union that we
5715 // can tile with integers.
5716 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5717 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5726 OpTy = IntegerType::get(Context, BitSize);
5731 return TLI.getValueType(OpTy, true);
5735 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5737 } // end anonymous namespace
5739 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5740 /// specified operand. We prefer to assign virtual registers, to allow the
5741 /// register allocator to handle the assignment process. However, if the asm
5742 /// uses features that we can't model on machineinstrs, we have SDISel do the
5743 /// allocation. This produces generally horrible, but correct, code.
5745 /// OpInfo describes the operand.
5747 static void GetRegistersForValue(SelectionDAG &DAG,
5748 const TargetLowering &TLI,
5750 SDISelAsmOperandInfo &OpInfo) {
5751 LLVMContext &Context = *DAG.getContext();
5753 MachineFunction &MF = DAG.getMachineFunction();
5754 SmallVector<unsigned, 4> Regs;
5756 // If this is a constraint for a single physreg, or a constraint for a
5757 // register class, find it.
5758 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5759 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5760 OpInfo.ConstraintVT);
5762 unsigned NumRegs = 1;
5763 if (OpInfo.ConstraintVT != MVT::Other) {
5764 // If this is a FP input in an integer register (or visa versa) insert a bit
5765 // cast of the input value. More generally, handle any case where the input
5766 // value disagrees with the register class we plan to stick this in.
5767 if (OpInfo.Type == InlineAsm::isInput &&
5768 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5769 // Try to convert to the first EVT that the reg class contains. If the
5770 // types are identical size, use a bitcast to convert (e.g. two differing
5772 EVT RegVT = *PhysReg.second->vt_begin();
5773 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5774 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5775 RegVT, OpInfo.CallOperand);
5776 OpInfo.ConstraintVT = RegVT;
5777 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5778 // If the input is a FP value and we want it in FP registers, do a
5779 // bitcast to the corresponding integer type. This turns an f64 value
5780 // into i64, which can be passed with two i32 values on a 32-bit
5782 RegVT = EVT::getIntegerVT(Context,
5783 OpInfo.ConstraintVT.getSizeInBits());
5784 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5785 RegVT, OpInfo.CallOperand);
5786 OpInfo.ConstraintVT = RegVT;
5790 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5794 EVT ValueVT = OpInfo.ConstraintVT;
5796 // If this is a constraint for a specific physical register, like {r17},
5798 if (unsigned AssignedReg = PhysReg.first) {
5799 const TargetRegisterClass *RC = PhysReg.second;
5800 if (OpInfo.ConstraintVT == MVT::Other)
5801 ValueVT = *RC->vt_begin();
5803 // Get the actual register value type. This is important, because the user
5804 // may have asked for (e.g.) the AX register in i32 type. We need to
5805 // remember that AX is actually i16 to get the right extension.
5806 RegVT = *RC->vt_begin();
5808 // This is a explicit reference to a physical register.
5809 Regs.push_back(AssignedReg);
5811 // If this is an expanded reference, add the rest of the regs to Regs.
5813 TargetRegisterClass::iterator I = RC->begin();
5814 for (; *I != AssignedReg; ++I)
5815 assert(I != RC->end() && "Didn't find reg!");
5817 // Already added the first reg.
5819 for (; NumRegs; --NumRegs, ++I) {
5820 assert(I != RC->end() && "Ran out of registers to allocate!");
5825 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5829 // Otherwise, if this was a reference to an LLVM register class, create vregs
5830 // for this reference.
5831 if (const TargetRegisterClass *RC = PhysReg.second) {
5832 RegVT = *RC->vt_begin();
5833 if (OpInfo.ConstraintVT == MVT::Other)
5836 // Create the appropriate number of virtual registers.
5837 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5838 for (; NumRegs; --NumRegs)
5839 Regs.push_back(RegInfo.createVirtualRegister(RC));
5841 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5845 // Otherwise, we couldn't allocate enough registers for this.
5848 /// visitInlineAsm - Handle a call to an InlineAsm object.
5850 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5851 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5853 /// ConstraintOperands - Information about all of the constraints.
5854 SDISelAsmOperandInfoVector ConstraintOperands;
5856 TargetLowering::AsmOperandInfoVector
5857 TargetConstraints = TLI.ParseConstraints(CS);
5859 bool hasMemory = false;
5861 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5862 unsigned ResNo = 0; // ResNo - The result number of the next output.
5863 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5864 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5865 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5867 EVT OpVT = MVT::Other;
5869 // Compute the value type for each operand.
5870 switch (OpInfo.Type) {
5871 case InlineAsm::isOutput:
5872 // Indirect outputs just consume an argument.
5873 if (OpInfo.isIndirect) {
5874 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5878 // The return value of the call is this value. As such, there is no
5879 // corresponding argument.
5880 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5881 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5882 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5884 assert(ResNo == 0 && "Asm only has one result!");
5885 OpVT = TLI.getValueType(CS.getType());
5889 case InlineAsm::isInput:
5890 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5892 case InlineAsm::isClobber:
5897 // If this is an input or an indirect output, process the call argument.
5898 // BasicBlocks are labels, currently appearing only in asm's.
5899 if (OpInfo.CallOperandVal) {
5900 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5901 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5903 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5906 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5909 OpInfo.ConstraintVT = OpVT;
5911 // Indirect operand accesses access memory.
5912 if (OpInfo.isIndirect)
5915 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5916 TargetLowering::ConstraintType
5917 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5918 if (CType == TargetLowering::C_Memory) {
5926 SDValue Chain, Flag;
5928 // We won't need to flush pending loads if this asm doesn't touch
5929 // memory and is nonvolatile.
5930 if (hasMemory || IA->hasSideEffects())
5933 Chain = DAG.getRoot();
5935 // Second pass over the constraints: compute which constraint option to use
5936 // and assign registers to constraints that want a specific physreg.
5937 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5938 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5940 // If this is an output operand with a matching input operand, look up the
5941 // matching input. If their types mismatch, e.g. one is an integer, the
5942 // other is floating point, or their sizes are different, flag it as an
5944 if (OpInfo.hasMatchingInput()) {
5945 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5947 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5948 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5949 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5950 OpInfo.ConstraintVT);
5951 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5952 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5953 Input.ConstraintVT);
5954 if ((OpInfo.ConstraintVT.isInteger() !=
5955 Input.ConstraintVT.isInteger()) ||
5956 (MatchRC.second != InputRC.second)) {
5957 report_fatal_error("Unsupported asm: input constraint"
5958 " with a matching output constraint of"
5959 " incompatible type!");
5961 Input.ConstraintVT = OpInfo.ConstraintVT;
5965 // Compute the constraint code and ConstraintType to use.
5966 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5968 // If this is a memory input, and if the operand is not indirect, do what we
5969 // need to to provide an address for the memory input.
5970 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5971 !OpInfo.isIndirect) {
5972 assert((OpInfo.isMultipleAlternative ||
5973 (OpInfo.Type == InlineAsm::isInput)) &&
5974 "Can only indirectify direct input operands!");
5976 // Memory operands really want the address of the value. If we don't have
5977 // an indirect input, put it in the constpool if we can, otherwise spill
5978 // it to a stack slot.
5979 // TODO: This isn't quite right. We need to handle these according to
5980 // the addressing mode that the constraint wants. Also, this may take
5981 // an additional register for the computation and we don't want that
5984 // If the operand is a float, integer, or vector constant, spill to a
5985 // constant pool entry to get its address.
5986 const Value *OpVal = OpInfo.CallOperandVal;
5987 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5988 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5989 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5990 TLI.getPointerTy());
5992 // Otherwise, create a stack slot and emit a store to it before the
5994 Type *Ty = OpVal->getType();
5995 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5996 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5997 MachineFunction &MF = DAG.getMachineFunction();
5998 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5999 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6000 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6001 OpInfo.CallOperand, StackSlot,
6002 MachinePointerInfo::getFixedStack(SSFI),
6004 OpInfo.CallOperand = StackSlot;
6007 // There is no longer a Value* corresponding to this operand.
6008 OpInfo.CallOperandVal = 0;
6010 // It is now an indirect operand.
6011 OpInfo.isIndirect = true;
6014 // If this constraint is for a specific register, allocate it before
6016 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6017 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6020 // Second pass - Loop over all of the operands, assigning virtual or physregs
6021 // to register class operands.
6022 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6023 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6025 // C_Register operands have already been allocated, Other/Memory don't need
6027 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6028 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6031 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6032 std::vector<SDValue> AsmNodeOperands;
6033 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6034 AsmNodeOperands.push_back(
6035 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6036 TLI.getPointerTy()));
6038 // If we have a !srcloc metadata node associated with it, we want to attach
6039 // this to the ultimately generated inline asm machineinstr. To do this, we
6040 // pass in the third operand as this (potentially null) inline asm MDNode.
6041 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6042 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6044 // Remember the HasSideEffect and AlignStack bits as operand 3.
6045 unsigned ExtraInfo = 0;
6046 if (IA->hasSideEffects())
6047 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6048 if (IA->isAlignStack())
6049 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6050 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6051 TLI.getPointerTy()));
6053 // Loop over all of the inputs, copying the operand values into the
6054 // appropriate registers and processing the output regs.
6055 RegsForValue RetValRegs;
6057 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6058 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6060 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6061 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6063 switch (OpInfo.Type) {
6064 case InlineAsm::isOutput: {
6065 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6066 OpInfo.ConstraintType != TargetLowering::C_Register) {
6067 // Memory output, or 'other' output (e.g. 'X' constraint).
6068 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6070 // Add information to the INLINEASM node to know about this output.
6071 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6072 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6073 TLI.getPointerTy()));
6074 AsmNodeOperands.push_back(OpInfo.CallOperand);
6078 // Otherwise, this is a register or register class output.
6080 // Copy the output from the appropriate register. Find a register that
6082 if (OpInfo.AssignedRegs.Regs.empty()) {
6083 LLVMContext &Ctx = *DAG.getContext();
6084 Ctx.emitError(CS.getInstruction(),
6085 "couldn't allocate output register for constraint '" +
6086 Twine(OpInfo.ConstraintCode) + "'");
6090 // If this is an indirect operand, store through the pointer after the
6092 if (OpInfo.isIndirect) {
6093 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6094 OpInfo.CallOperandVal));
6096 // This is the result value of the call.
6097 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6098 // Concatenate this output onto the outputs list.
6099 RetValRegs.append(OpInfo.AssignedRegs);
6102 // Add information to the INLINEASM node to know that this register is
6104 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6105 InlineAsm::Kind_RegDefEarlyClobber :
6106 InlineAsm::Kind_RegDef,
6113 case InlineAsm::isInput: {
6114 SDValue InOperandVal = OpInfo.CallOperand;
6116 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6117 // If this is required to match an output register we have already set,
6118 // just use its register.
6119 unsigned OperandNo = OpInfo.getMatchedOperand();
6121 // Scan until we find the definition we already emitted of this operand.
6122 // When we find it, create a RegsForValue operand.
6123 unsigned CurOp = InlineAsm::Op_FirstOperand;
6124 for (; OperandNo; --OperandNo) {
6125 // Advance to the next operand.
6127 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6128 assert((InlineAsm::isRegDefKind(OpFlag) ||
6129 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6130 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6131 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6135 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6136 if (InlineAsm::isRegDefKind(OpFlag) ||
6137 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6138 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6139 if (OpInfo.isIndirect) {
6140 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6141 LLVMContext &Ctx = *DAG.getContext();
6142 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6143 " don't know how to handle tied "
6144 "indirect register inputs");
6147 RegsForValue MatchedRegs;
6148 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6149 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6150 MatchedRegs.RegVTs.push_back(RegVT);
6151 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6152 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6154 MatchedRegs.Regs.push_back
6155 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6157 // Use the produced MatchedRegs object to
6158 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6160 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6161 true, OpInfo.getMatchedOperand(),
6162 DAG, AsmNodeOperands);
6166 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6167 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6168 "Unexpected number of operands");
6169 // Add information to the INLINEASM node to know about this input.
6170 // See InlineAsm.h isUseOperandTiedToDef.
6171 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6172 OpInfo.getMatchedOperand());
6173 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6174 TLI.getPointerTy()));
6175 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6179 // Treat indirect 'X' constraint as memory.
6180 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6182 OpInfo.ConstraintType = TargetLowering::C_Memory;
6184 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6185 std::vector<SDValue> Ops;
6186 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6189 LLVMContext &Ctx = *DAG.getContext();
6190 Ctx.emitError(CS.getInstruction(),
6191 "invalid operand for inline asm constraint '" +
6192 Twine(OpInfo.ConstraintCode) + "'");
6196 // Add information to the INLINEASM node to know about this input.
6197 unsigned ResOpType =
6198 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6199 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6200 TLI.getPointerTy()));
6201 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6205 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6206 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6207 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6208 "Memory operands expect pointer values");
6210 // Add information to the INLINEASM node to know about this input.
6211 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6212 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6213 TLI.getPointerTy()));
6214 AsmNodeOperands.push_back(InOperandVal);
6218 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6219 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6220 "Unknown constraint type!");
6221 assert(!OpInfo.isIndirect &&
6222 "Don't know how to handle indirect register inputs yet!");
6224 // Copy the input into the appropriate registers.
6225 if (OpInfo.AssignedRegs.Regs.empty()) {
6226 LLVMContext &Ctx = *DAG.getContext();
6227 Ctx.emitError(CS.getInstruction(),
6228 "couldn't allocate input reg for constraint '" +
6229 Twine(OpInfo.ConstraintCode) + "'");
6233 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6236 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6237 DAG, AsmNodeOperands);
6240 case InlineAsm::isClobber: {
6241 // Add the clobbered value to the operand list, so that the register
6242 // allocator is aware that the physreg got clobbered.
6243 if (!OpInfo.AssignedRegs.Regs.empty())
6244 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6252 // Finish up input operands. Set the input chain and add the flag last.
6253 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6254 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6256 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6257 DAG.getVTList(MVT::Other, MVT::Glue),
6258 &AsmNodeOperands[0], AsmNodeOperands.size());
6259 Flag = Chain.getValue(1);
6261 // If this asm returns a register value, copy the result from that register
6262 // and set it as the value of the call.
6263 if (!RetValRegs.Regs.empty()) {
6264 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6267 // FIXME: Why don't we do this for inline asms with MRVs?
6268 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6269 EVT ResultType = TLI.getValueType(CS.getType());
6271 // If any of the results of the inline asm is a vector, it may have the
6272 // wrong width/num elts. This can happen for register classes that can
6273 // contain multiple different value types. The preg or vreg allocated may
6274 // not have the same VT as was expected. Convert it to the right type
6275 // with bit_convert.
6276 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6277 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6280 } else if (ResultType != Val.getValueType() &&
6281 ResultType.isInteger() && Val.getValueType().isInteger()) {
6282 // If a result value was tied to an input value, the computed result may
6283 // have a wider width than the expected result. Extract the relevant
6285 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6288 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6291 setValue(CS.getInstruction(), Val);
6292 // Don't need to use this as a chain in this case.
6293 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6297 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6299 // Process indirect outputs, first output all of the flagged copies out of
6301 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6302 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6303 const Value *Ptr = IndirectStoresToEmit[i].second;
6304 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6306 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6309 // Emit the non-flagged stores from the physregs.
6310 SmallVector<SDValue, 8> OutChains;
6311 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6312 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6313 StoresToEmit[i].first,
6314 getValue(StoresToEmit[i].second),
6315 MachinePointerInfo(StoresToEmit[i].second),
6317 OutChains.push_back(Val);
6320 if (!OutChains.empty())
6321 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6322 &OutChains[0], OutChains.size());
6327 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6328 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6329 MVT::Other, getRoot(),
6330 getValue(I.getArgOperand(0)),
6331 DAG.getSrcValue(I.getArgOperand(0))));
6334 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6335 const TargetData &TD = *TLI.getTargetData();
6336 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6337 getRoot(), getValue(I.getOperand(0)),
6338 DAG.getSrcValue(I.getOperand(0)),
6339 TD.getABITypeAlignment(I.getType()));
6341 DAG.setRoot(V.getValue(1));
6344 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6345 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6346 MVT::Other, getRoot(),
6347 getValue(I.getArgOperand(0)),
6348 DAG.getSrcValue(I.getArgOperand(0))));
6351 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6352 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6353 MVT::Other, getRoot(),
6354 getValue(I.getArgOperand(0)),
6355 getValue(I.getArgOperand(1)),
6356 DAG.getSrcValue(I.getArgOperand(0)),
6357 DAG.getSrcValue(I.getArgOperand(1))));
6360 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6361 /// implementation, which just calls LowerCall.
6362 /// FIXME: When all targets are
6363 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6364 std::pair<SDValue, SDValue>
6365 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6366 bool RetSExt, bool RetZExt, bool isVarArg,
6367 bool isInreg, unsigned NumFixedArgs,
6368 CallingConv::ID CallConv, bool isTailCall,
6369 bool doesNotRet, bool isReturnValueUsed,
6371 ArgListTy &Args, SelectionDAG &DAG,
6372 DebugLoc dl) const {
6373 // Handle all of the outgoing arguments.
6374 SmallVector<ISD::OutputArg, 32> Outs;
6375 SmallVector<SDValue, 32> OutVals;
6376 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6377 SmallVector<EVT, 4> ValueVTs;
6378 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6379 for (unsigned Value = 0, NumValues = ValueVTs.size();
6380 Value != NumValues; ++Value) {
6381 EVT VT = ValueVTs[Value];
6382 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6383 SDValue Op = SDValue(Args[i].Node.getNode(),
6384 Args[i].Node.getResNo() + Value);
6385 ISD::ArgFlagsTy Flags;
6386 unsigned OriginalAlignment =
6387 getTargetData()->getABITypeAlignment(ArgTy);
6393 if (Args[i].isInReg)
6397 if (Args[i].isByVal) {
6399 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6400 Type *ElementTy = Ty->getElementType();
6401 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6402 // For ByVal, alignment should come from FE. BE will guess if this
6403 // info is not there but there are cases it cannot get right.
6404 unsigned FrameAlign;
6405 if (Args[i].Alignment)
6406 FrameAlign = Args[i].Alignment;
6408 FrameAlign = getByValTypeAlignment(ElementTy);
6409 Flags.setByValAlign(FrameAlign);
6413 Flags.setOrigAlign(OriginalAlignment);
6415 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6416 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6417 SmallVector<SDValue, 4> Parts(NumParts);
6418 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6421 ExtendKind = ISD::SIGN_EXTEND;
6422 else if (Args[i].isZExt)
6423 ExtendKind = ISD::ZERO_EXTEND;
6425 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6426 PartVT, ExtendKind);
6428 for (unsigned j = 0; j != NumParts; ++j) {
6429 // if it isn't first piece, alignment must be 1
6430 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6432 if (NumParts > 1 && j == 0)
6433 MyFlags.Flags.setSplit();
6435 MyFlags.Flags.setOrigAlign(1);
6437 Outs.push_back(MyFlags);
6438 OutVals.push_back(Parts[j]);
6443 // Handle the incoming return values from the call.
6444 SmallVector<ISD::InputArg, 32> Ins;
6445 SmallVector<EVT, 4> RetTys;
6446 ComputeValueVTs(*this, RetTy, RetTys);
6447 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6449 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6450 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6451 for (unsigned i = 0; i != NumRegs; ++i) {
6452 ISD::InputArg MyFlags;
6453 MyFlags.VT = RegisterVT.getSimpleVT();
6454 MyFlags.Used = isReturnValueUsed;
6456 MyFlags.Flags.setSExt();
6458 MyFlags.Flags.setZExt();
6460 MyFlags.Flags.setInReg();
6461 Ins.push_back(MyFlags);
6465 SmallVector<SDValue, 4> InVals;
6466 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall,
6467 Outs, OutVals, Ins, dl, DAG, InVals);
6469 // Verify that the target's LowerCall behaved as expected.
6470 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6471 "LowerCall didn't return a valid chain!");
6472 assert((!isTailCall || InVals.empty()) &&
6473 "LowerCall emitted a return value for a tail call!");
6474 assert((isTailCall || InVals.size() == Ins.size()) &&
6475 "LowerCall didn't emit the correct number of values!");
6477 // For a tail call, the return value is merely live-out and there aren't
6478 // any nodes in the DAG representing it. Return a special value to
6479 // indicate that a tail call has been emitted and no more Instructions
6480 // should be processed in the current block.
6483 return std::make_pair(SDValue(), SDValue());
6486 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6487 assert(InVals[i].getNode() &&
6488 "LowerCall emitted a null value!");
6489 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6490 "LowerCall emitted a value with the wrong type!");
6493 // Collect the legal value parts into potentially illegal values
6494 // that correspond to the original function's return values.
6495 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6497 AssertOp = ISD::AssertSext;
6499 AssertOp = ISD::AssertZext;
6500 SmallVector<SDValue, 4> ReturnValues;
6501 unsigned CurReg = 0;
6502 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6504 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6505 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6507 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6508 NumRegs, RegisterVT, VT,
6513 // For a function returning void, there is no return value. We can't create
6514 // such a node, so we just return a null return value in that case. In
6515 // that case, nothing will actually look at the value.
6516 if (ReturnValues.empty())
6517 return std::make_pair(SDValue(), Chain);
6519 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6520 DAG.getVTList(&RetTys[0], RetTys.size()),
6521 &ReturnValues[0], ReturnValues.size());
6522 return std::make_pair(Res, Chain);
6525 void TargetLowering::LowerOperationWrapper(SDNode *N,
6526 SmallVectorImpl<SDValue> &Results,
6527 SelectionDAG &DAG) const {
6528 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6530 Results.push_back(Res);
6533 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6534 llvm_unreachable("LowerOperation not implemented for this target!");
6538 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6539 SDValue Op = getNonRegisterValue(V);
6540 assert((Op.getOpcode() != ISD::CopyFromReg ||
6541 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6542 "Copy from a reg to the same reg!");
6543 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6545 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6546 SDValue Chain = DAG.getEntryNode();
6547 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6548 PendingExports.push_back(Chain);
6551 #include "llvm/CodeGen/SelectionDAGISel.h"
6553 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6554 /// entry block, return true. This includes arguments used by switches, since
6555 /// the switch may expand into multiple basic blocks.
6556 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6557 // With FastISel active, we may be splitting blocks, so force creation
6558 // of virtual registers for all non-dead arguments.
6560 return A->use_empty();
6562 const BasicBlock *Entry = A->getParent()->begin();
6563 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6565 const User *U = *UI;
6566 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6567 return false; // Use not in entry block.
6572 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6573 // If this is the entry block, emit arguments.
6574 const Function &F = *LLVMBB->getParent();
6575 SelectionDAG &DAG = SDB->DAG;
6576 DebugLoc dl = SDB->getCurDebugLoc();
6577 const TargetData *TD = TLI.getTargetData();
6578 SmallVector<ISD::InputArg, 16> Ins;
6580 // Check whether the function can return without sret-demotion.
6581 SmallVector<ISD::OutputArg, 4> Outs;
6582 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6585 if (!FuncInfo->CanLowerReturn) {
6586 // Put in an sret pointer parameter before all the other parameters.
6587 SmallVector<EVT, 1> ValueVTs;
6588 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6590 // NOTE: Assuming that a pointer will never break down to more than one VT
6592 ISD::ArgFlagsTy Flags;
6594 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6595 ISD::InputArg RetArg(Flags, RegisterVT, true);
6596 Ins.push_back(RetArg);
6599 // Set up the incoming argument description vector.
6601 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6602 I != E; ++I, ++Idx) {
6603 SmallVector<EVT, 4> ValueVTs;
6604 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6605 bool isArgValueUsed = !I->use_empty();
6606 for (unsigned Value = 0, NumValues = ValueVTs.size();
6607 Value != NumValues; ++Value) {
6608 EVT VT = ValueVTs[Value];
6609 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6610 ISD::ArgFlagsTy Flags;
6611 unsigned OriginalAlignment =
6612 TD->getABITypeAlignment(ArgTy);
6614 if (F.paramHasAttr(Idx, Attribute::ZExt))
6616 if (F.paramHasAttr(Idx, Attribute::SExt))
6618 if (F.paramHasAttr(Idx, Attribute::InReg))
6620 if (F.paramHasAttr(Idx, Attribute::StructRet))
6622 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6624 PointerType *Ty = cast<PointerType>(I->getType());
6625 Type *ElementTy = Ty->getElementType();
6626 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6627 // For ByVal, alignment should be passed from FE. BE will guess if
6628 // this info is not there but there are cases it cannot get right.
6629 unsigned FrameAlign;
6630 if (F.getParamAlignment(Idx))
6631 FrameAlign = F.getParamAlignment(Idx);
6633 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6634 Flags.setByValAlign(FrameAlign);
6636 if (F.paramHasAttr(Idx, Attribute::Nest))
6638 Flags.setOrigAlign(OriginalAlignment);
6640 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6641 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6642 for (unsigned i = 0; i != NumRegs; ++i) {
6643 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6644 if (NumRegs > 1 && i == 0)
6645 MyFlags.Flags.setSplit();
6646 // if it isn't first piece, alignment must be 1
6648 MyFlags.Flags.setOrigAlign(1);
6649 Ins.push_back(MyFlags);
6654 // Call the target to set up the argument values.
6655 SmallVector<SDValue, 8> InVals;
6656 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6660 // Verify that the target's LowerFormalArguments behaved as expected.
6661 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6662 "LowerFormalArguments didn't return a valid chain!");
6663 assert(InVals.size() == Ins.size() &&
6664 "LowerFormalArguments didn't emit the correct number of values!");
6666 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6667 assert(InVals[i].getNode() &&
6668 "LowerFormalArguments emitted a null value!");
6669 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6670 "LowerFormalArguments emitted a value with the wrong type!");
6674 // Update the DAG with the new chain value resulting from argument lowering.
6675 DAG.setRoot(NewRoot);
6677 // Set up the argument values.
6680 if (!FuncInfo->CanLowerReturn) {
6681 // Create a virtual register for the sret pointer, and put in a copy
6682 // from the sret argument into it.
6683 SmallVector<EVT, 1> ValueVTs;
6684 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6685 EVT VT = ValueVTs[0];
6686 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6687 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6688 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6689 RegVT, VT, AssertOp);
6691 MachineFunction& MF = SDB->DAG.getMachineFunction();
6692 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6693 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6694 FuncInfo->DemoteRegister = SRetReg;
6695 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6697 DAG.setRoot(NewRoot);
6699 // i indexes lowered arguments. Bump it past the hidden sret argument.
6700 // Idx indexes LLVM arguments. Don't touch it.
6704 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6706 SmallVector<SDValue, 4> ArgValues;
6707 SmallVector<EVT, 4> ValueVTs;
6708 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6709 unsigned NumValues = ValueVTs.size();
6711 // If this argument is unused then remember its value. It is used to generate
6712 // debugging information.
6713 if (I->use_empty() && NumValues)
6714 SDB->setUnusedArgValue(I, InVals[i]);
6716 for (unsigned Val = 0; Val != NumValues; ++Val) {
6717 EVT VT = ValueVTs[Val];
6718 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6719 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6721 if (!I->use_empty()) {
6722 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6723 if (F.paramHasAttr(Idx, Attribute::SExt))
6724 AssertOp = ISD::AssertSext;
6725 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6726 AssertOp = ISD::AssertZext;
6728 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6729 NumParts, PartVT, VT,
6736 // We don't need to do anything else for unused arguments.
6737 if (ArgValues.empty())
6740 // Note down frame index.
6741 if (FrameIndexSDNode *FI =
6742 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6743 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6745 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6746 SDB->getCurDebugLoc());
6748 SDB->setValue(I, Res);
6749 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6750 if (LoadSDNode *LNode =
6751 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6752 if (FrameIndexSDNode *FI =
6753 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6754 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6757 // If this argument is live outside of the entry block, insert a copy from
6758 // wherever we got it to the vreg that other BB's will reference it as.
6759 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6760 // If we can, though, try to skip creating an unnecessary vreg.
6761 // FIXME: This isn't very clean... it would be nice to make this more
6762 // general. It's also subtly incompatible with the hacks FastISel
6764 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6765 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6766 FuncInfo->ValueMap[I] = Reg;
6770 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6771 FuncInfo->InitializeRegForValue(I);
6772 SDB->CopyToExportRegsIfNeeded(I);
6776 assert(i == InVals.size() && "Argument register count mismatch!");
6778 // Finally, if the target has anything special to do, allow it to do so.
6779 // FIXME: this should insert code into the DAG!
6780 EmitFunctionEntryCode();
6783 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6784 /// ensure constants are generated when needed. Remember the virtual registers
6785 /// that need to be added to the Machine PHI nodes as input. We cannot just
6786 /// directly add them, because expansion might result in multiple MBB's for one
6787 /// BB. As such, the start of the BB might correspond to a different MBB than
6791 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6792 const TerminatorInst *TI = LLVMBB->getTerminator();
6794 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6796 // Check successor nodes' PHI nodes that expect a constant to be available
6798 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6799 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6800 if (!isa<PHINode>(SuccBB->begin())) continue;
6801 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6803 // If this terminator has multiple identical successors (common for
6804 // switches), only handle each succ once.
6805 if (!SuccsHandled.insert(SuccMBB)) continue;
6807 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6809 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6810 // nodes and Machine PHI nodes, but the incoming operands have not been
6812 for (BasicBlock::const_iterator I = SuccBB->begin();
6813 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6814 // Ignore dead phi's.
6815 if (PN->use_empty()) continue;
6818 if (PN->getType()->isEmptyTy())
6822 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6824 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6825 unsigned &RegOut = ConstantsOut[C];
6827 RegOut = FuncInfo.CreateRegs(C->getType());
6828 CopyValueToVirtualRegister(C, RegOut);
6832 DenseMap<const Value *, unsigned>::iterator I =
6833 FuncInfo.ValueMap.find(PHIOp);
6834 if (I != FuncInfo.ValueMap.end())
6837 assert(isa<AllocaInst>(PHIOp) &&
6838 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6839 "Didn't codegen value into a register!??");
6840 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6841 CopyValueToVirtualRegister(PHIOp, Reg);
6845 // Remember that this register needs to added to the machine PHI node as
6846 // the input for this MBB.
6847 SmallVector<EVT, 4> ValueVTs;
6848 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6849 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6850 EVT VT = ValueVTs[vti];
6851 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6852 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6853 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6854 Reg += NumRegisters;
6858 ConstantsOut.clear();