1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isInteger()) {
202 if (ValueVT.bitsLT(PartEVT)) {
203 // For a truncate, see if we have any information to
204 // indicate whether the truncated bits will always be
205 // zero or sign-extension.
206 if (AssertOp != ISD::DELETED_NODE)
207 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
208 DAG.getValueType(ValueVT));
209 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
211 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
214 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
215 // FP_ROUND's are always exact here.
216 if (ValueVT.bitsLT(Val.getValueType()))
218 ISD::FP_ROUND, DL, ValueVT, Val,
219 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
221 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
224 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
225 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
227 llvm_unreachable("Unknown mismatch!");
230 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
231 const Twine &ErrMsg) {
232 const Instruction *I = dyn_cast_or_null<Instruction>(V);
234 return Ctx.emitError(ErrMsg);
236 const char *AsmError = ", possible invalid constraint for vector type";
237 if (const CallInst *CI = dyn_cast<CallInst>(I))
238 if (isa<InlineAsm>(CI->getCalledValue()))
239 return Ctx.emitError(I, ErrMsg + AsmError);
241 return Ctx.emitError(I, ErrMsg);
244 /// getCopyFromPartsVector - Create a value that contains the specified legal
245 /// parts combined into the value they represent. If the parts combine to a
246 /// type larger then ValueVT then AssertOp can be used to specify whether the
247 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
248 /// ValueVT (ISD::AssertSext).
249 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
250 const SDValue *Parts, unsigned NumParts,
251 MVT PartVT, EVT ValueVT, const Value *V) {
252 assert(ValueVT.isVector() && "Not a vector value");
253 assert(NumParts > 0 && "No parts to assemble!");
254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
255 SDValue Val = Parts[0];
257 // Handle a multi-element vector.
261 unsigned NumIntermediates;
263 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
264 NumIntermediates, RegisterVT);
265 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
266 NumParts = NumRegs; // Silence a compiler warning.
267 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
268 assert(RegisterVT.getSizeInBits() ==
269 Parts[0].getSimpleValueType().getSizeInBits() &&
270 "Part type sizes don't match!");
272 // Assemble the parts into intermediate operands.
273 SmallVector<SDValue, 8> Ops(NumIntermediates);
274 if (NumIntermediates == NumParts) {
275 // If the register was not expanded, truncate or copy the value,
277 for (unsigned i = 0; i != NumParts; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
279 PartVT, IntermediateVT, V);
280 } else if (NumParts > 0) {
281 // If the intermediate type was expanded, build the intermediate
282 // operands from the parts.
283 assert(NumParts % NumIntermediates == 0 &&
284 "Must expand into a divisible number of parts!");
285 unsigned Factor = NumParts / NumIntermediates;
286 for (unsigned i = 0; i != NumIntermediates; ++i)
287 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
288 PartVT, IntermediateVT, V);
291 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
292 // intermediate operands.
293 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
298 // There is now one part, held in Val. Correct it to match ValueVT.
299 EVT PartEVT = Val.getValueType();
301 if (PartEVT == ValueVT)
304 if (PartEVT.isVector()) {
305 // If the element type of the source/dest vectors are the same, but the
306 // parts vector has more elements than the value vector, then we have a
307 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
309 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
310 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
311 "Cannot narrow, it would be a lossy transformation");
313 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
314 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
317 // Vector/Vector bitcast.
318 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
319 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
321 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
322 "Cannot handle this kind of promotion");
323 // Promoted vector extract
324 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
328 // Trivial bitcast if the types are the same size and the destination
329 // vector type is legal.
330 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
331 TLI.isTypeLegal(ValueVT))
332 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
334 // Handle cases such as i8 -> <1 x i1>
335 if (ValueVT.getVectorNumElements() != 1) {
336 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
337 "non-trivial scalar-to-vector conversion");
338 return DAG.getUNDEF(ValueVT);
341 if (ValueVT.getVectorNumElements() == 1 &&
342 ValueVT.getVectorElementType() != PartEVT)
343 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
345 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
348 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
349 SDValue Val, SDValue *Parts, unsigned NumParts,
350 MVT PartVT, const Value *V);
352 /// getCopyToParts - Create a series of nodes that contain the specified value
353 /// split into legal parts. If the parts contain more bits than Val, then, for
354 /// integers, ExtendKind can be used to specify how to generate the extra bits.
355 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
356 SDValue Val, SDValue *Parts, unsigned NumParts,
357 MVT PartVT, const Value *V,
358 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
359 EVT ValueVT = Val.getValueType();
361 // Handle the vector case separately.
362 if (ValueVT.isVector())
363 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
365 unsigned PartBits = PartVT.getSizeInBits();
366 unsigned OrigNumParts = NumParts;
367 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
368 "Copying to an illegal type!");
373 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
374 EVT PartEVT = PartVT;
375 if (PartEVT == ValueVT) {
376 assert(NumParts == 1 && "No-op copy with multiple parts!");
381 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
382 // If the parts cover more bits than the value has, promote the value.
383 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
384 assert(NumParts == 1 && "Do not know what to promote to!");
385 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
387 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
388 ValueVT.isInteger() &&
389 "Unknown mismatch!");
390 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
391 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
392 if (PartVT == MVT::x86mmx)
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
395 } else if (PartBits == ValueVT.getSizeInBits()) {
396 // Different types of the same size.
397 assert(NumParts == 1 && PartEVT != ValueVT);
398 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
399 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
400 // If the parts cover less bits than value has, truncate the value.
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
410 // The value may have changed - recompute ValueVT.
411 ValueVT = Val.getValueType();
412 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
413 "Failed to tile the value with PartVT!");
416 if (PartEVT != ValueVT)
417 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
418 "scalar-to-vector conversion failed");
424 // Expand the value into multiple parts.
425 if (NumParts & (NumParts - 1)) {
426 // The number of parts is not a power of 2. Split off and copy the tail.
427 assert(PartVT.isInteger() && ValueVT.isInteger() &&
428 "Do not know what to expand to!");
429 unsigned RoundParts = 1 << Log2_32(NumParts);
430 unsigned RoundBits = RoundParts * PartBits;
431 unsigned OddParts = NumParts - RoundParts;
432 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
433 DAG.getIntPtrConstant(RoundBits, DL));
434 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
436 if (DAG.getDataLayout().isBigEndian())
437 // The odd parts were reversed by getCopyToParts - unreverse them.
438 std::reverse(Parts + RoundParts, Parts + NumParts);
440 NumParts = RoundParts;
441 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
442 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
445 // The number of parts is a power of 2. Repeatedly bisect the value using
447 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
448 EVT::getIntegerVT(*DAG.getContext(),
449 ValueVT.getSizeInBits()),
452 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
453 for (unsigned i = 0; i < NumParts; i += StepSize) {
454 unsigned ThisBits = StepSize * PartBits / 2;
455 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
456 SDValue &Part0 = Parts[i];
457 SDValue &Part1 = Parts[i+StepSize/2];
459 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
460 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
461 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
462 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
464 if (ThisBits == PartBits && ThisVT != PartVT) {
465 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
466 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
471 if (DAG.getDataLayout().isBigEndian())
472 std::reverse(Parts, Parts + OrigNumParts);
476 /// getCopyToPartsVector - Create a series of nodes that contain the specified
477 /// value split into legal parts.
478 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
479 SDValue Val, SDValue *Parts, unsigned NumParts,
480 MVT PartVT, const Value *V) {
481 EVT ValueVT = Val.getValueType();
482 assert(ValueVT.isVector() && "Not a vector");
483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
486 EVT PartEVT = PartVT;
487 if (PartEVT == ValueVT) {
489 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
490 // Bitconvert vector->vector case.
491 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
492 } else if (PartVT.isVector() &&
493 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
494 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
495 EVT ElementVT = PartVT.getVectorElementType();
496 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
498 SmallVector<SDValue, 16> Ops;
499 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
500 Ops.push_back(DAG.getNode(
501 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
502 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
504 for (unsigned i = ValueVT.getVectorNumElements(),
505 e = PartVT.getVectorNumElements(); i != e; ++i)
506 Ops.push_back(DAG.getUNDEF(ElementVT));
508 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
510 // FIXME: Use CONCAT for 2x -> 4x.
512 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
513 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
514 } else if (PartVT.isVector() &&
515 PartEVT.getVectorElementType().bitsGE(
516 ValueVT.getVectorElementType()) &&
517 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
519 // Promoted vector extract
520 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
522 // Vector -> scalar conversion.
523 assert(ValueVT.getVectorNumElements() == 1 &&
524 "Only trivial vector-to-scalar conversions should get here!");
526 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
527 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
529 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Handle a multi-element vector.
539 unsigned NumIntermediates;
540 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
542 NumIntermediates, RegisterVT);
543 unsigned NumElements = ValueVT.getVectorNumElements();
545 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
546 NumParts = NumRegs; // Silence a compiler warning.
547 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
549 // Split the vector into intermediate operands.
550 SmallVector<SDValue, 8> Ops(NumIntermediates);
551 for (unsigned i = 0; i != NumIntermediates; ++i) {
552 if (IntermediateVT.isVector())
554 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
555 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
556 TLI.getVectorIdxTy(DAG.getDataLayout())));
558 Ops[i] = DAG.getNode(
559 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
560 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
563 // Split the intermediate operands into legal parts.
564 if (NumParts == NumIntermediates) {
565 // If the register was not expanded, promote or copy the value,
567 for (unsigned i = 0; i != NumParts; ++i)
568 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
569 } else if (NumParts > 0) {
570 // If the intermediate type was expanded, split each the value into
572 assert(NumIntermediates != 0 && "division by zero");
573 assert(NumParts % NumIntermediates == 0 &&
574 "Must expand into a divisible number of parts!");
575 unsigned Factor = NumParts / NumIntermediates;
576 for (unsigned i = 0; i != NumIntermediates; ++i)
577 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
581 RegsForValue::RegsForValue() {}
583 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
585 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
587 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
588 const DataLayout &DL, unsigned Reg, Type *Ty) {
589 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
591 for (EVT ValueVT : ValueVTs) {
592 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
593 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
602 /// this value and returns the result as a ValueVT value. This uses
603 /// Chain/Flag as the input and updates them for the output Chain/Flag.
604 /// If the Flag pointer is NULL, no flag is used.
605 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
606 FunctionLoweringInfo &FuncInfo,
608 SDValue &Chain, SDValue *Flag,
609 const Value *V) const {
610 // A Value with type {} or [0 x %t] needs no registers.
611 if (ValueVTs.empty())
614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
616 // Assemble the legal parts into the final values.
617 SmallVector<SDValue, 4> Values(ValueVTs.size());
618 SmallVector<SDValue, 8> Parts;
619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 // Copy the legal parts from the registers.
621 EVT ValueVT = ValueVTs[Value];
622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
623 MVT RegisterVT = RegVTs[Value];
625 Parts.resize(NumRegs);
626 for (unsigned i = 0; i != NumRegs; ++i) {
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
632 *Flag = P.getValue(2);
635 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
641 !RegisterVT.isInteger() || RegisterVT.isVector())
644 const FunctionLoweringInfo::LiveOutInfo *LOI =
645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
649 unsigned RegSize = RegisterVT.getSizeInBits();
650 unsigned NumSignBits = LOI->NumSignBits;
651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
653 if (NumZeroBits == RegSize) {
654 // The current value is a zero.
655 // Explicitly express that as it would be easier for
656 // optimizations to kick in.
657 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
661 // FIXME: We capture more information than the dag can represent. For
662 // now, just use the tightest assertzext/assertsext possible.
664 EVT FromVT(MVT::Other);
665 if (NumSignBits == RegSize)
666 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
667 else if (NumZeroBits >= RegSize-1)
668 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
669 else if (NumSignBits > RegSize-8)
670 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
671 else if (NumZeroBits >= RegSize-8)
672 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
673 else if (NumSignBits > RegSize-16)
674 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
675 else if (NumZeroBits >= RegSize-16)
676 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
677 else if (NumSignBits > RegSize-32)
678 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
679 else if (NumZeroBits >= RegSize-32)
680 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
684 // Add an assertion node.
685 assert(FromVT != MVT::Other);
686 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
687 RegisterVT, P, DAG.getValueType(FromVT));
690 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
691 NumRegs, RegisterVT, ValueVT, V);
696 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
699 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
700 /// specified value into the registers specified by this object. This uses
701 /// Chain/Flag as the input and updates them for the output Chain/Flag.
702 /// If the Flag pointer is NULL, no flag is used.
703 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
704 SDValue &Chain, SDValue *Flag, const Value *V,
705 ISD::NodeType PreferredExtendType) const {
706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
707 ISD::NodeType ExtendKind = PreferredExtendType;
709 // Get the list of the values's legal parts.
710 unsigned NumRegs = Regs.size();
711 SmallVector<SDValue, 8> Parts(NumRegs);
712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
713 EVT ValueVT = ValueVTs[Value];
714 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
715 MVT RegisterVT = RegVTs[Value];
717 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
718 ExtendKind = ISD::ZERO_EXTEND;
720 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
721 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
725 // Copy the parts into the registers.
726 SmallVector<SDValue, 8> Chains(NumRegs);
727 for (unsigned i = 0; i != NumRegs; ++i) {
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
732 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
733 *Flag = Part.getValue(1);
736 Chains[i] = Part.getValue(0);
739 if (NumRegs == 1 || Flag)
740 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
741 // flagged to it. That is the CopyToReg nodes and the user are considered
742 // a single scheduling unit. If we create a TokenFactor and return it as
743 // chain, then the TokenFactor is both a predecessor (operand) of the
744 // user as well as a successor (the TF operands are flagged to the user).
745 // c1, f1 = CopyToReg
746 // c2, f2 = CopyToReg
747 // c3 = TokenFactor c1, c2
750 Chain = Chains[NumRegs-1];
752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
755 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
756 /// operand list. This adds the code marker and includes the number of
757 /// values added into it.
758 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
759 unsigned MatchingIdx, SDLoc dl,
761 std::vector<SDValue> &Ops) const {
762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
764 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
766 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
767 else if (!Regs.empty() &&
768 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
769 // Put the register class of the virtual registers in the flag word. That
770 // way, later passes can recompute register class constraints for inline
771 // assembly as well as normal instructions.
772 // Don't do this for tied operands that can use the regclass information
774 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
775 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
776 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
779 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
782 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
783 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
784 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
785 MVT RegisterVT = RegVTs[Value];
786 for (unsigned i = 0; i != NumRegs; ++i) {
787 assert(Reg < Regs.size() && "Mismatch in # registers expected");
788 unsigned TheReg = Regs[Reg++];
789 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
791 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
792 // If we clobbered the stack pointer, MFI should know about it.
793 assert(DAG.getMachineFunction().getFrameInfo()->
794 hasOpaqueSPAdjustment());
800 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
801 const TargetLibraryInfo *li) {
805 DL = &DAG.getDataLayout();
806 Context = DAG.getContext();
807 LPadToCallSiteMap.clear();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
823 SDNodeOrder = LowestSDNodeOrder;
824 StatepointLowering.clear();
827 /// clearDanglingDebugInfo - Clear the dangling debug information
828 /// map. This function is separated from the clear so that debug
829 /// information that is dangling in a basic block can be properly
830 /// resolved in a different basic block. This allows the
831 /// SelectionDAG to resolve dangling debug information attached
833 void SelectionDAGBuilder::clearDanglingDebugInfo() {
834 DanglingDebugInfoMap.clear();
837 /// getRoot - Return the current virtual root of the Selection DAG,
838 /// flushing any PendingLoad items. This must be done before emitting
839 /// a store or any other node that may need to be ordered after any
840 /// prior load instructions.
842 SDValue SelectionDAGBuilder::getRoot() {
843 if (PendingLoads.empty())
844 return DAG.getRoot();
846 if (PendingLoads.size() == 1) {
847 SDValue Root = PendingLoads[0];
849 PendingLoads.clear();
853 // Otherwise, we have to make a token factor node.
854 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
856 PendingLoads.clear();
861 /// getControlRoot - Similar to getRoot, but instead of flushing all the
862 /// PendingLoad items, flush all the PendingExports items. It is necessary
863 /// to do this before emitting a terminator instruction.
865 SDValue SelectionDAGBuilder::getControlRoot() {
866 SDValue Root = DAG.getRoot();
868 if (PendingExports.empty())
871 // Turn all of the CopyToReg chains into one factored node.
872 if (Root.getOpcode() != ISD::EntryToken) {
873 unsigned i = 0, e = PendingExports.size();
874 for (; i != e; ++i) {
875 assert(PendingExports[i].getNode()->getNumOperands() > 1);
876 if (PendingExports[i].getNode()->getOperand(0) == Root)
877 break; // Don't add the root if we already indirectly depend on it.
881 PendingExports.push_back(Root);
884 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
886 PendingExports.clear();
891 void SelectionDAGBuilder::visit(const Instruction &I) {
892 // Set up outgoing PHI node register values before emitting the terminator.
893 if (isa<TerminatorInst>(&I))
894 HandlePHINodesInSuccessorBlocks(I.getParent());
900 visit(I.getOpcode(), I);
902 if (!isa<TerminatorInst>(&I) && !HasTailCall)
903 CopyToExportRegsIfNeeded(&I);
908 void SelectionDAGBuilder::visitPHI(const PHINode &) {
909 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
912 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
913 // Note: this doesn't use InstVisitor, because it has to work with
914 // ConstantExpr's in addition to instructions.
916 default: llvm_unreachable("Unknown instruction type encountered!");
917 // Build the switch statement using the Instruction.def file.
918 #define HANDLE_INST(NUM, OPCODE, CLASS) \
919 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
920 #include "llvm/IR/Instruction.def"
924 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
925 // generate the debug data structures now that we've seen its definition.
926 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
928 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
930 const DbgValueInst *DI = DDI.getDI();
931 DebugLoc dl = DDI.getdl();
932 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
933 DILocalVariable *Variable = DI->getVariable();
934 DIExpression *Expr = DI->getExpression();
935 assert(Variable->isValidLocationForIntrinsic(dl) &&
936 "Expected inlined-at fields to agree");
937 uint64_t Offset = DI->getOffset();
938 // A dbg.value for an alloca is always indirect.
939 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
942 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
944 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
945 IsIndirect, Offset, dl, DbgSDNodeOrder);
946 DAG.AddDbgValue(SDV, Val.getNode(), false);
949 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
950 DanglingDebugInfoMap[V] = DanglingDebugInfo();
954 /// getCopyFromRegs - If there was virtual register allocated for the value V
955 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
956 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
957 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
960 if (It != FuncInfo.ValueMap.end()) {
961 unsigned InReg = It->second;
962 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
963 DAG.getDataLayout(), InReg, Ty);
964 SDValue Chain = DAG.getEntryNode();
965 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
966 resolveDanglingDebugInfo(V, Result);
972 /// getValue - Return an SDValue for the given Value.
973 SDValue SelectionDAGBuilder::getValue(const Value *V) {
974 // If we already have an SDValue for this value, use it. It's important
975 // to do this first, so that we don't create a CopyFromReg if we already
976 // have a regular SDValue.
977 SDValue &N = NodeMap[V];
978 if (N.getNode()) return N;
980 // If there's a virtual register allocated and initialized for this
982 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
983 if (copyFromReg.getNode()) {
987 // Otherwise create a new SDValue and remember it.
988 SDValue Val = getValueImpl(V);
990 resolveDanglingDebugInfo(V, Val);
994 // Return true if SDValue exists for the given Value
995 bool SelectionDAGBuilder::findValue(const Value *V) const {
996 return (NodeMap.find(V) != NodeMap.end()) ||
997 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1000 /// getNonRegisterValue - Return an SDValue for the given Value, but
1001 /// don't look in FuncInfo.ValueMap for a virtual register.
1002 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1003 // If we already have an SDValue for this value, use it.
1004 SDValue &N = NodeMap[V];
1006 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1007 // Remove the debug location from the node as the node is about to be used
1008 // in a location which may differ from the original debug location. This
1009 // is relevant to Constant and ConstantFP nodes because they can appear
1010 // as constant expressions inside PHI nodes.
1011 N->setDebugLoc(DebugLoc());
1016 // Otherwise create a new SDValue and remember it.
1017 SDValue Val = getValueImpl(V);
1019 resolveDanglingDebugInfo(V, Val);
1023 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1024 /// Create an SDValue for the given value.
1025 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1028 if (const Constant *C = dyn_cast<Constant>(V)) {
1029 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1031 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1032 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1034 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1035 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1037 if (isa<ConstantPointerNull>(C)) {
1038 unsigned AS = V->getType()->getPointerAddressSpace();
1039 return DAG.getConstant(0, getCurSDLoc(),
1040 TLI.getPointerTy(DAG.getDataLayout(), AS));
1043 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1044 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1046 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1047 return DAG.getUNDEF(VT);
1049 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1050 visit(CE->getOpcode(), *CE);
1051 SDValue N1 = NodeMap[V];
1052 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1056 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1057 SmallVector<SDValue, 4> Constants;
1058 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1060 SDNode *Val = getValue(*OI).getNode();
1061 // If the operand is an empty aggregate, there are no values.
1063 // Add each leaf value from the operand to the Constants list
1064 // to form a flattened list of all the values.
1065 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1066 Constants.push_back(SDValue(Val, i));
1069 return DAG.getMergeValues(Constants, getCurSDLoc());
1072 if (const ConstantDataSequential *CDS =
1073 dyn_cast<ConstantDataSequential>(C)) {
1074 SmallVector<SDValue, 4> Ops;
1075 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1076 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1077 // Add each leaf value from the operand to the Constants list
1078 // to form a flattened list of all the values.
1079 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1080 Ops.push_back(SDValue(Val, i));
1083 if (isa<ArrayType>(CDS->getType()))
1084 return DAG.getMergeValues(Ops, getCurSDLoc());
1085 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1089 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1090 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1091 "Unknown struct or array constant!");
1093 SmallVector<EVT, 4> ValueVTs;
1094 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1095 unsigned NumElts = ValueVTs.size();
1097 return SDValue(); // empty struct
1098 SmallVector<SDValue, 4> Constants(NumElts);
1099 for (unsigned i = 0; i != NumElts; ++i) {
1100 EVT EltVT = ValueVTs[i];
1101 if (isa<UndefValue>(C))
1102 Constants[i] = DAG.getUNDEF(EltVT);
1103 else if (EltVT.isFloatingPoint())
1104 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1106 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1109 return DAG.getMergeValues(Constants, getCurSDLoc());
1112 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1113 return DAG.getBlockAddress(BA, VT);
1115 VectorType *VecTy = cast<VectorType>(V->getType());
1116 unsigned NumElements = VecTy->getNumElements();
1118 // Now that we know the number and type of the elements, get that number of
1119 // elements into the Ops array based on what kind of constant it is.
1120 SmallVector<SDValue, 16> Ops;
1121 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1122 for (unsigned i = 0; i != NumElements; ++i)
1123 Ops.push_back(getValue(CV->getOperand(i)));
1125 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1127 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1130 if (EltVT.isFloatingPoint())
1131 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1133 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1134 Ops.assign(NumElements, Op);
1137 // Create a BUILD_VECTOR node.
1138 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1141 // If this is a static alloca, generate it as the frameindex instead of
1143 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1144 DenseMap<const AllocaInst*, int>::iterator SI =
1145 FuncInfo.StaticAllocaMap.find(AI);
1146 if (SI != FuncInfo.StaticAllocaMap.end())
1147 return DAG.getFrameIndex(SI->second,
1148 TLI.getPointerTy(DAG.getDataLayout()));
1151 // If this is an instruction which fast-isel has deferred, select it now.
1152 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1153 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1154 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1156 SDValue Chain = DAG.getEntryNode();
1157 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1160 llvm_unreachable("Can't get register for value!");
1163 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1164 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1165 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1166 bool IsSEH = isAsynchronousEHPersonality(Pers);
1167 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1168 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1169 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1170 if (IsMSVCCXX || IsCoreCLR)
1171 CatchPadMBB->setIsEHFuncletEntry();
1173 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1175 // Update machine-CFG edge.
1176 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1178 // CatchPads in SEH are not funclets, they are merely markers which indicate
1179 // where to insert register restoration code.
1181 DAG.setRoot(DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1182 getControlRoot(), DAG.getBasicBlock(NormalDestMBB),
1183 DAG.getBasicBlock(&FuncInfo.MF->front())));
1187 // If this is not a fall-through branch or optimizations are switched off,
1189 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1190 TM.getOptLevel() == CodeGenOpt::None)
1191 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1193 DAG.getBasicBlock(NormalDestMBB)));
1196 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1197 // Update machine-CFG edge.
1198 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1199 FuncInfo.MBB->addSuccessor(TargetMBB);
1201 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1202 bool IsSEH = isAsynchronousEHPersonality(Pers);
1204 // If this is not a fall-through branch or optimizations are switched off,
1206 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1207 TM.getOptLevel() == CodeGenOpt::None)
1208 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1209 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1213 // Figure out the funclet membership for the catchret's successor.
1214 // This will be used by the FuncletLayout pass to determine how to order the
1216 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1217 WinEHFuncInfo &EHInfo =
1218 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1219 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1220 assert(SuccessorColor && "No parent funclet for catchret!");
1221 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1222 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1224 // Create the terminator node.
1225 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1226 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1227 DAG.getBasicBlock(SuccessorColorMBB));
1231 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1232 llvm_unreachable("should never codegen catchendpads");
1235 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1236 // Don't emit any special code for the cleanuppad instruction. It just marks
1237 // the start of a funclet.
1238 FuncInfo.MBB->setIsEHFuncletEntry();
1239 FuncInfo.MBB->setIsCleanupFuncletEntry();
1242 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1243 /// many places it could ultimately go. In the IR, we have a single unwind
1244 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1245 /// This function skips over imaginary basic blocks that hold catchpad,
1246 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1247 /// basic block destinations. As those destinations may not be successors of
1248 /// EHPadBB, here we also calculate the edge weight to those destinations. The
1249 /// passed-in Weight is the edge weight to EHPadBB.
1250 static void findUnwindDestinations(
1251 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, uint32_t Weight,
1252 SmallVectorImpl<std::pair<MachineBasicBlock *, uint32_t>> &UnwindDests) {
1253 EHPersonality Personality =
1254 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1255 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1256 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1259 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1260 BasicBlock *NewEHPadBB = nullptr;
1261 if (isa<LandingPadInst>(Pad)) {
1262 // Stop on landingpads. They are not funclets.
1263 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1265 } else if (isa<CleanupPadInst>(Pad)) {
1266 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1268 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1269 UnwindDests.back().first->setIsEHFuncletEntry();
1271 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1272 // Add the catchpad handler to the possible destinations.
1273 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1274 // In MSVC C++, catchblocks are funclets and need prologues.
1275 if (IsMSVCCXX || IsCoreCLR)
1276 UnwindDests.back().first->setIsEHFuncletEntry();
1277 NewEHPadBB = CPI->getUnwindDest();
1278 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad))
1279 NewEHPadBB = CEPI->getUnwindDest();
1280 else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad))
1281 NewEHPadBB = CEPI->getUnwindDest();
1285 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1286 if (BPI && NewEHPadBB) {
1287 // When BPI is available, the calculated weight cannot be zero as zero
1288 // will be turned to a default weight in MachineBlockFrequencyInfo.
1289 Weight = std::max<uint32_t>(
1290 BPI->getEdgeProbability(EHPadBB, NewEHPadBB).scale(Weight), 1);
1292 EHPadBB = NewEHPadBB;
1296 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1297 // Update successor info.
1298 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
1299 auto UnwindDest = I.getUnwindDest();
1300 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1301 uint32_t UnwindDestWeight =
1302 BPI ? BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(), UnwindDest) : 0;
1303 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestWeight, UnwindDests);
1304 for (auto &UnwindDest : UnwindDests) {
1305 UnwindDest.first->setIsEHPad();
1306 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1309 // Create the terminator node.
1311 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1315 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1316 report_fatal_error("visitCleanupEndPad not yet implemented!");
1319 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1320 report_fatal_error("visitTerminatePad not yet implemented!");
1323 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1324 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1325 auto &DL = DAG.getDataLayout();
1326 SDValue Chain = getControlRoot();
1327 SmallVector<ISD::OutputArg, 8> Outs;
1328 SmallVector<SDValue, 8> OutVals;
1330 if (!FuncInfo.CanLowerReturn) {
1331 unsigned DemoteReg = FuncInfo.DemoteRegister;
1332 const Function *F = I.getParent()->getParent();
1334 // Emit a store of the return value through the virtual register.
1335 // Leave Outs empty so that LowerReturn won't try to load return
1336 // registers the usual way.
1337 SmallVector<EVT, 1> PtrValueVTs;
1338 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1341 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1342 SDValue RetOp = getValue(I.getOperand(0));
1344 SmallVector<EVT, 4> ValueVTs;
1345 SmallVector<uint64_t, 4> Offsets;
1346 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1347 unsigned NumValues = ValueVTs.size();
1349 SmallVector<SDValue, 4> Chains(NumValues);
1350 for (unsigned i = 0; i != NumValues; ++i) {
1351 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1352 RetPtr.getValueType(), RetPtr,
1353 DAG.getIntPtrConstant(Offsets[i],
1356 DAG.getStore(Chain, getCurSDLoc(),
1357 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1358 // FIXME: better loc info would be nice.
1359 Add, MachinePointerInfo(), false, false, 0);
1362 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1363 MVT::Other, Chains);
1364 } else if (I.getNumOperands() != 0) {
1365 SmallVector<EVT, 4> ValueVTs;
1366 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1367 unsigned NumValues = ValueVTs.size();
1369 SDValue RetOp = getValue(I.getOperand(0));
1371 const Function *F = I.getParent()->getParent();
1373 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1374 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1376 ExtendKind = ISD::SIGN_EXTEND;
1377 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1379 ExtendKind = ISD::ZERO_EXTEND;
1381 LLVMContext &Context = F->getContext();
1382 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1385 for (unsigned j = 0; j != NumValues; ++j) {
1386 EVT VT = ValueVTs[j];
1388 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1389 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1391 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1392 MVT PartVT = TLI.getRegisterType(Context, VT);
1393 SmallVector<SDValue, 4> Parts(NumParts);
1394 getCopyToParts(DAG, getCurSDLoc(),
1395 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1396 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1398 // 'inreg' on function refers to return value
1399 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1403 // Propagate extension type if any
1404 if (ExtendKind == ISD::SIGN_EXTEND)
1406 else if (ExtendKind == ISD::ZERO_EXTEND)
1409 for (unsigned i = 0; i < NumParts; ++i) {
1410 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1411 VT, /*isfixed=*/true, 0, 0));
1412 OutVals.push_back(Parts[i]);
1418 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1419 CallingConv::ID CallConv =
1420 DAG.getMachineFunction().getFunction()->getCallingConv();
1421 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1422 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1424 // Verify that the target's LowerReturn behaved as expected.
1425 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1426 "LowerReturn didn't return a valid chain!");
1428 // Update the DAG with the new chain value resulting from return lowering.
1432 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1433 /// created for it, emit nodes to copy the value into the virtual
1435 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1437 if (V->getType()->isEmptyTy())
1440 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1441 if (VMI != FuncInfo.ValueMap.end()) {
1442 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1443 CopyValueToVirtualRegister(V, VMI->second);
1447 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1448 /// the current basic block, add it to ValueMap now so that we'll get a
1450 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1451 // No need to export constants.
1452 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1454 // Already exported?
1455 if (FuncInfo.isExportedInst(V)) return;
1457 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1458 CopyValueToVirtualRegister(V, Reg);
1461 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1462 const BasicBlock *FromBB) {
1463 // The operands of the setcc have to be in this block. We don't know
1464 // how to export them from some other block.
1465 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1466 // Can export from current BB.
1467 if (VI->getParent() == FromBB)
1470 // Is already exported, noop.
1471 return FuncInfo.isExportedInst(V);
1474 // If this is an argument, we can export it if the BB is the entry block or
1475 // if it is already exported.
1476 if (isa<Argument>(V)) {
1477 if (FromBB == &FromBB->getParent()->getEntryBlock())
1480 // Otherwise, can only export this if it is already exported.
1481 return FuncInfo.isExportedInst(V);
1484 // Otherwise, constants can always be exported.
1488 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1489 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1490 const MachineBasicBlock *Dst) const {
1491 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1494 const BasicBlock *SrcBB = Src->getBasicBlock();
1495 const BasicBlock *DstBB = Dst->getBasicBlock();
1496 return BPI->getEdgeWeight(SrcBB, DstBB);
1499 void SelectionDAGBuilder::
1500 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1501 uint32_t Weight /* = 0 */) {
1503 Src->addSuccessorWithoutWeight(Dst);
1506 Weight = getEdgeWeight(Src, Dst);
1507 Src->addSuccessor(Dst, Weight);
1512 static bool InBlock(const Value *V, const BasicBlock *BB) {
1513 if (const Instruction *I = dyn_cast<Instruction>(V))
1514 return I->getParent() == BB;
1518 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1519 /// This function emits a branch and is used at the leaves of an OR or an
1520 /// AND operator tree.
1523 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1524 MachineBasicBlock *TBB,
1525 MachineBasicBlock *FBB,
1526 MachineBasicBlock *CurBB,
1527 MachineBasicBlock *SwitchBB,
1530 const BasicBlock *BB = CurBB->getBasicBlock();
1532 // If the leaf of the tree is a comparison, merge the condition into
1534 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1535 // The operands of the cmp have to be in this block. We don't know
1536 // how to export them from some other block. If this is the first block
1537 // of the sequence, no exporting is needed.
1538 if (CurBB == SwitchBB ||
1539 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1540 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1541 ISD::CondCode Condition;
1542 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1543 Condition = getICmpCondCode(IC->getPredicate());
1545 const FCmpInst *FC = cast<FCmpInst>(Cond);
1546 Condition = getFCmpCondCode(FC->getPredicate());
1547 if (TM.Options.NoNaNsFPMath)
1548 Condition = getFCmpCodeWithoutNaN(Condition);
1551 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1552 TBB, FBB, CurBB, TWeight, FWeight);
1553 SwitchCases.push_back(CB);
1558 // Create a CaseBlock record representing this branch.
1559 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1560 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1561 SwitchCases.push_back(CB);
1564 /// Scale down both weights to fit into uint32_t.
1565 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1566 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1567 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1568 NewTrue = NewTrue / Scale;
1569 NewFalse = NewFalse / Scale;
1572 /// FindMergedConditions - If Cond is an expression like
1573 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1574 MachineBasicBlock *TBB,
1575 MachineBasicBlock *FBB,
1576 MachineBasicBlock *CurBB,
1577 MachineBasicBlock *SwitchBB,
1578 Instruction::BinaryOps Opc,
1581 // If this node is not part of the or/and tree, emit it as a branch.
1582 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1583 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1584 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1585 BOp->getParent() != CurBB->getBasicBlock() ||
1586 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1587 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1588 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1593 // Create TmpBB after CurBB.
1594 MachineFunction::iterator BBI(CurBB);
1595 MachineFunction &MF = DAG.getMachineFunction();
1596 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1597 CurBB->getParent()->insert(++BBI, TmpBB);
1599 if (Opc == Instruction::Or) {
1600 // Codegen X | Y as:
1609 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1610 // The requirement is that
1611 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1612 // = TrueProb for original BB.
1613 // Assuming the original weights are A and B, one choice is to set BB1's
1614 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1616 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1617 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1618 // TmpBB, but the math is more complicated.
1620 uint64_t NewTrueWeight = TWeight;
1621 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1622 ScaleWeights(NewTrueWeight, NewFalseWeight);
1623 // Emit the LHS condition.
1624 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1625 NewTrueWeight, NewFalseWeight);
1627 NewTrueWeight = TWeight;
1628 NewFalseWeight = 2 * (uint64_t)FWeight;
1629 ScaleWeights(NewTrueWeight, NewFalseWeight);
1630 // Emit the RHS condition into TmpBB.
1631 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1632 NewTrueWeight, NewFalseWeight);
1634 assert(Opc == Instruction::And && "Unknown merge op!");
1635 // Codegen X & Y as:
1643 // This requires creation of TmpBB after CurBB.
1645 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1646 // The requirement is that
1647 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1648 // = FalseProb for original BB.
1649 // Assuming the original weights are A and B, one choice is to set BB1's
1650 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1652 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1654 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1655 uint64_t NewFalseWeight = FWeight;
1656 ScaleWeights(NewTrueWeight, NewFalseWeight);
1657 // Emit the LHS condition.
1658 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1659 NewTrueWeight, NewFalseWeight);
1661 NewTrueWeight = 2 * (uint64_t)TWeight;
1662 NewFalseWeight = FWeight;
1663 ScaleWeights(NewTrueWeight, NewFalseWeight);
1664 // Emit the RHS condition into TmpBB.
1665 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1666 NewTrueWeight, NewFalseWeight);
1670 /// If the set of cases should be emitted as a series of branches, return true.
1671 /// If we should emit this as a bunch of and/or'd together conditions, return
1674 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1675 if (Cases.size() != 2) return true;
1677 // If this is two comparisons of the same values or'd or and'd together, they
1678 // will get folded into a single comparison, so don't emit two blocks.
1679 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1680 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1681 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1682 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1686 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1687 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1688 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1689 Cases[0].CC == Cases[1].CC &&
1690 isa<Constant>(Cases[0].CmpRHS) &&
1691 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1692 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1694 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1701 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1702 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1704 // Update machine-CFG edges.
1705 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1707 if (I.isUnconditional()) {
1708 // Update machine-CFG edges.
1709 BrMBB->addSuccessor(Succ0MBB);
1711 // If this is not a fall-through branch or optimizations are switched off,
1713 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1714 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1715 MVT::Other, getControlRoot(),
1716 DAG.getBasicBlock(Succ0MBB)));
1721 // If this condition is one of the special cases we handle, do special stuff
1723 const Value *CondVal = I.getCondition();
1724 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1726 // If this is a series of conditions that are or'd or and'd together, emit
1727 // this as a sequence of branches instead of setcc's with and/or operations.
1728 // As long as jumps are not expensive, this should improve performance.
1729 // For example, instead of something like:
1742 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1743 Instruction::BinaryOps Opcode = BOp->getOpcode();
1744 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1745 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1746 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1747 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1748 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1749 getEdgeWeight(BrMBB, Succ1MBB));
1750 // If the compares in later blocks need to use values not currently
1751 // exported from this block, export them now. This block should always
1752 // be the first entry.
1753 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1755 // Allow some cases to be rejected.
1756 if (ShouldEmitAsBranches(SwitchCases)) {
1757 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1758 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1759 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1762 // Emit the branch for this block.
1763 visitSwitchCase(SwitchCases[0], BrMBB);
1764 SwitchCases.erase(SwitchCases.begin());
1768 // Okay, we decided not to do this, remove any inserted MBB's and clear
1770 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1771 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1773 SwitchCases.clear();
1777 // Create a CaseBlock record representing this branch.
1778 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1779 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1781 // Use visitSwitchCase to actually insert the fast branch sequence for this
1783 visitSwitchCase(CB, BrMBB);
1786 /// visitSwitchCase - Emits the necessary code to represent a single node in
1787 /// the binary search tree resulting from lowering a switch instruction.
1788 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1789 MachineBasicBlock *SwitchBB) {
1791 SDValue CondLHS = getValue(CB.CmpLHS);
1792 SDLoc dl = getCurSDLoc();
1794 // Build the setcc now.
1796 // Fold "(X == true)" to X and "(X == false)" to !X to
1797 // handle common cases produced by branch lowering.
1798 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1799 CB.CC == ISD::SETEQ)
1801 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1802 CB.CC == ISD::SETEQ) {
1803 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1804 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1806 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1808 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1810 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1811 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1813 SDValue CmpOp = getValue(CB.CmpMHS);
1814 EVT VT = CmpOp.getValueType();
1816 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1817 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1820 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1821 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1822 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1823 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1827 // Update successor info
1828 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1829 // TrueBB and FalseBB are always different unless the incoming IR is
1830 // degenerate. This only happens when running llc on weird IR.
1831 if (CB.TrueBB != CB.FalseBB)
1832 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1834 // If the lhs block is the next block, invert the condition so that we can
1835 // fall through to the lhs instead of the rhs block.
1836 if (CB.TrueBB == NextBlock(SwitchBB)) {
1837 std::swap(CB.TrueBB, CB.FalseBB);
1838 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1839 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1842 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1843 MVT::Other, getControlRoot(), Cond,
1844 DAG.getBasicBlock(CB.TrueBB));
1846 // Insert the false branch. Do this even if it's a fall through branch,
1847 // this makes it easier to do DAG optimizations which require inverting
1848 // the branch condition.
1849 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1850 DAG.getBasicBlock(CB.FalseBB));
1852 DAG.setRoot(BrCond);
1855 /// visitJumpTable - Emit JumpTable node in the current MBB
1856 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1857 // Emit the code for the jump table
1858 assert(JT.Reg != -1U && "Should lower JT Header first!");
1859 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1860 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1862 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1863 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1864 MVT::Other, Index.getValue(1),
1866 DAG.setRoot(BrJumpTable);
1869 /// visitJumpTableHeader - This function emits necessary code to produce index
1870 /// in the JumpTable from switch case.
1871 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1872 JumpTableHeader &JTH,
1873 MachineBasicBlock *SwitchBB) {
1874 SDLoc dl = getCurSDLoc();
1876 // Subtract the lowest switch case value from the value being switched on and
1877 // conditional branch to default mbb if the result is greater than the
1878 // difference between smallest and largest cases.
1879 SDValue SwitchOp = getValue(JTH.SValue);
1880 EVT VT = SwitchOp.getValueType();
1881 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1882 DAG.getConstant(JTH.First, dl, VT));
1884 // The SDNode we just created, which holds the value being switched on minus
1885 // the smallest case value, needs to be copied to a virtual register so it
1886 // can be used as an index into the jump table in a subsequent basic block.
1887 // This value may be smaller or larger than the target's pointer type, and
1888 // therefore require extension or truncating.
1889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1890 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1892 unsigned JumpTableReg =
1893 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1894 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1895 JumpTableReg, SwitchOp);
1896 JT.Reg = JumpTableReg;
1898 // Emit the range check for the jump table, and branch to the default block
1899 // for the switch statement if the value being switched on exceeds the largest
1900 // case in the switch.
1901 SDValue CMP = DAG.getSetCC(
1902 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1903 Sub.getValueType()),
1904 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1906 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1907 MVT::Other, CopyTo, CMP,
1908 DAG.getBasicBlock(JT.Default));
1910 // Avoid emitting unnecessary branches to the next block.
1911 if (JT.MBB != NextBlock(SwitchBB))
1912 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1913 DAG.getBasicBlock(JT.MBB));
1915 DAG.setRoot(BrCond);
1918 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1919 /// tail spliced into a stack protector check success bb.
1921 /// For a high level explanation of how this fits into the stack protector
1922 /// generation see the comment on the declaration of class
1923 /// StackProtectorDescriptor.
1924 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1925 MachineBasicBlock *ParentBB) {
1927 // First create the loads to the guard/stack slot for the comparison.
1928 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1929 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1931 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1932 int FI = MFI->getStackProtectorIndex();
1934 const Value *IRGuard = SPD.getGuard();
1935 SDValue GuardPtr = getValue(IRGuard);
1936 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1938 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1941 SDLoc dl = getCurSDLoc();
1943 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1944 // guard value from the virtual register holding the value. Otherwise, emit a
1945 // volatile load to retrieve the stack guard value.
1946 unsigned GuardReg = SPD.getGuardReg();
1948 if (GuardReg && TLI.useLoadStackGuardNode())
1949 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1952 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1953 GuardPtr, MachinePointerInfo(IRGuard, 0),
1954 true, false, false, Align);
1956 SDValue StackSlot = DAG.getLoad(
1957 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1958 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1959 false, false, Align);
1961 // Perform the comparison via a subtract/getsetcc.
1962 EVT VT = Guard.getValueType();
1963 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1965 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1967 Sub.getValueType()),
1968 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1970 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1971 // branch to failure MBB.
1972 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1973 MVT::Other, StackSlot.getOperand(0),
1974 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1975 // Otherwise branch to success MBB.
1976 SDValue Br = DAG.getNode(ISD::BR, dl,
1978 DAG.getBasicBlock(SPD.getSuccessMBB()));
1983 /// Codegen the failure basic block for a stack protector check.
1985 /// A failure stack protector machine basic block consists simply of a call to
1986 /// __stack_chk_fail().
1988 /// For a high level explanation of how this fits into the stack protector
1989 /// generation see the comment on the declaration of class
1990 /// StackProtectorDescriptor.
1992 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1995 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1996 None, false, getCurSDLoc(), false, false).second;
2000 /// visitBitTestHeader - This function emits necessary code to produce value
2001 /// suitable for "bit tests"
2002 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2003 MachineBasicBlock *SwitchBB) {
2004 SDLoc dl = getCurSDLoc();
2006 // Subtract the minimum value
2007 SDValue SwitchOp = getValue(B.SValue);
2008 EVT VT = SwitchOp.getValueType();
2009 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2010 DAG.getConstant(B.First, dl, VT));
2013 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2014 SDValue RangeCmp = DAG.getSetCC(
2015 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2016 Sub.getValueType()),
2017 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2019 // Determine the type of the test operands.
2020 bool UsePtrType = false;
2021 if (!TLI.isTypeLegal(VT))
2024 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2025 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2026 // Switch table case range are encoded into series of masks.
2027 // Just use pointer type, it's guaranteed to fit.
2033 VT = TLI.getPointerTy(DAG.getDataLayout());
2034 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2037 B.RegVT = VT.getSimpleVT();
2038 B.Reg = FuncInfo.CreateReg(B.RegVT);
2039 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2041 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2043 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2044 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2046 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2047 MVT::Other, CopyTo, RangeCmp,
2048 DAG.getBasicBlock(B.Default));
2050 // Avoid emitting unnecessary branches to the next block.
2051 if (MBB != NextBlock(SwitchBB))
2052 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2053 DAG.getBasicBlock(MBB));
2055 DAG.setRoot(BrRange);
2058 /// visitBitTestCase - this function produces one "bit test"
2059 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2060 MachineBasicBlock* NextMBB,
2061 uint32_t BranchWeightToNext,
2064 MachineBasicBlock *SwitchBB) {
2065 SDLoc dl = getCurSDLoc();
2067 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2069 unsigned PopCount = countPopulation(B.Mask);
2070 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2071 if (PopCount == 1) {
2072 // Testing for a single bit; just compare the shift count with what it
2073 // would need to be to shift a 1 bit in that position.
2075 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2076 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2078 } else if (PopCount == BB.Range) {
2079 // There is only one zero bit in the range, test for it directly.
2081 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2082 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2085 // Make desired shift
2086 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2087 DAG.getConstant(1, dl, VT), ShiftOp);
2089 // Emit bit tests and jumps
2090 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2091 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2093 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2094 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2097 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2098 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2099 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2100 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2102 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2103 MVT::Other, getControlRoot(),
2104 Cmp, DAG.getBasicBlock(B.TargetBB));
2106 // Avoid emitting unnecessary branches to the next block.
2107 if (NextMBB != NextBlock(SwitchBB))
2108 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2109 DAG.getBasicBlock(NextMBB));
2114 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2115 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2117 // Retrieve successors. Look through artificial IR level blocks like catchpads
2118 // and catchendpads for successors.
2119 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2120 const BasicBlock *EHPadBB = I.getSuccessor(1);
2122 const Value *Callee(I.getCalledValue());
2123 const Function *Fn = dyn_cast<Function>(Callee);
2124 if (isa<InlineAsm>(Callee))
2126 else if (Fn && Fn->isIntrinsic()) {
2127 switch (Fn->getIntrinsicID()) {
2129 llvm_unreachable("Cannot invoke this intrinsic");
2130 case Intrinsic::donothing:
2131 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2133 case Intrinsic::experimental_patchpoint_void:
2134 case Intrinsic::experimental_patchpoint_i64:
2135 visitPatchpoint(&I, EHPadBB);
2137 case Intrinsic::experimental_gc_statepoint:
2138 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2142 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2144 // If the value of the invoke is used outside of its defining block, make it
2145 // available as a virtual register.
2146 // We already took care of the exported value for the statepoint instruction
2147 // during call to the LowerStatepoint.
2148 if (!isStatepoint(I)) {
2149 CopyToExportRegsIfNeeded(&I);
2152 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
2153 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2154 uint32_t EHPadBBWeight =
2155 BPI ? BPI->getEdgeWeight(InvokeMBB->getBasicBlock(), EHPadBB) : 0;
2156 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBWeight, UnwindDests);
2158 // Update successor info.
2159 addSuccessorWithWeight(InvokeMBB, Return);
2160 for (auto &UnwindDest : UnwindDests) {
2161 UnwindDest.first->setIsEHPad();
2162 addSuccessorWithWeight(InvokeMBB, UnwindDest.first, UnwindDest.second);
2165 // Drop into normal successor.
2166 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2167 MVT::Other, getControlRoot(),
2168 DAG.getBasicBlock(Return)));
2171 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2172 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2175 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2176 assert(FuncInfo.MBB->isEHPad() &&
2177 "Call to landingpad not in landing pad!");
2179 MachineBasicBlock *MBB = FuncInfo.MBB;
2180 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2181 AddLandingPadInfo(LP, MMI, MBB);
2183 // If there aren't registers to copy the values into (e.g., during SjLj
2184 // exceptions), then don't bother to create these DAG nodes.
2185 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2186 if (TLI.getExceptionPointerRegister() == 0 &&
2187 TLI.getExceptionSelectorRegister() == 0)
2190 SmallVector<EVT, 2> ValueVTs;
2191 SDLoc dl = getCurSDLoc();
2192 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2193 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2195 // Get the two live-in registers as SDValues. The physregs have already been
2196 // copied into virtual registers.
2198 if (FuncInfo.ExceptionPointerVirtReg) {
2199 Ops[0] = DAG.getZExtOrTrunc(
2200 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2201 FuncInfo.ExceptionPointerVirtReg,
2202 TLI.getPointerTy(DAG.getDataLayout())),
2205 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2207 Ops[1] = DAG.getZExtOrTrunc(
2208 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2209 FuncInfo.ExceptionSelectorVirtReg,
2210 TLI.getPointerTy(DAG.getDataLayout())),
2214 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2215 DAG.getVTList(ValueVTs), Ops);
2219 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2221 for (const CaseCluster &CC : Clusters)
2222 assert(CC.Low == CC.High && "Input clusters must be single-case");
2225 std::sort(Clusters.begin(), Clusters.end(),
2226 [](const CaseCluster &a, const CaseCluster &b) {
2227 return a.Low->getValue().slt(b.Low->getValue());
2230 // Merge adjacent clusters with the same destination.
2231 const unsigned N = Clusters.size();
2232 unsigned DstIndex = 0;
2233 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2234 CaseCluster &CC = Clusters[SrcIndex];
2235 const ConstantInt *CaseVal = CC.Low;
2236 MachineBasicBlock *Succ = CC.MBB;
2238 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2239 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2240 // If this case has the same successor and is a neighbour, merge it into
2241 // the previous cluster.
2242 Clusters[DstIndex - 1].High = CaseVal;
2243 Clusters[DstIndex - 1].Weight += CC.Weight;
2244 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2246 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2247 sizeof(Clusters[SrcIndex]));
2250 Clusters.resize(DstIndex);
2253 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2254 MachineBasicBlock *Last) {
2256 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2257 if (JTCases[i].first.HeaderBB == First)
2258 JTCases[i].first.HeaderBB = Last;
2260 // Update BitTestCases.
2261 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2262 if (BitTestCases[i].Parent == First)
2263 BitTestCases[i].Parent = Last;
2266 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2267 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2269 // Update machine-CFG edges with unique successors.
2270 SmallSet<BasicBlock*, 32> Done;
2271 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2272 BasicBlock *BB = I.getSuccessor(i);
2273 bool Inserted = Done.insert(BB).second;
2277 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2278 addSuccessorWithWeight(IndirectBrMBB, Succ);
2281 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2282 MVT::Other, getControlRoot(),
2283 getValue(I.getAddress())));
2286 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2287 if (DAG.getTarget().Options.TrapUnreachable)
2289 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2292 void SelectionDAGBuilder::visitFSub(const User &I) {
2293 // -0.0 - X --> fneg
2294 Type *Ty = I.getType();
2295 if (isa<Constant>(I.getOperand(0)) &&
2296 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2297 SDValue Op2 = getValue(I.getOperand(1));
2298 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2299 Op2.getValueType(), Op2));
2303 visitBinary(I, ISD::FSUB);
2306 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2307 SDValue Op1 = getValue(I.getOperand(0));
2308 SDValue Op2 = getValue(I.getOperand(1));
2315 if (const OverflowingBinaryOperator *OFBinOp =
2316 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2317 nuw = OFBinOp->hasNoUnsignedWrap();
2318 nsw = OFBinOp->hasNoSignedWrap();
2320 if (const PossiblyExactOperator *ExactOp =
2321 dyn_cast<const PossiblyExactOperator>(&I))
2322 exact = ExactOp->isExact();
2323 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2324 FMF = FPOp->getFastMathFlags();
2327 Flags.setExact(exact);
2328 Flags.setNoSignedWrap(nsw);
2329 Flags.setNoUnsignedWrap(nuw);
2330 if (EnableFMFInDAG) {
2331 Flags.setAllowReciprocal(FMF.allowReciprocal());
2332 Flags.setNoInfs(FMF.noInfs());
2333 Flags.setNoNaNs(FMF.noNaNs());
2334 Flags.setNoSignedZeros(FMF.noSignedZeros());
2335 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2337 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2339 setValue(&I, BinNodeValue);
2342 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2343 SDValue Op1 = getValue(I.getOperand(0));
2344 SDValue Op2 = getValue(I.getOperand(1));
2346 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2347 Op2.getValueType(), DAG.getDataLayout());
2349 // Coerce the shift amount to the right type if we can.
2350 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2351 unsigned ShiftSize = ShiftTy.getSizeInBits();
2352 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2353 SDLoc DL = getCurSDLoc();
2355 // If the operand is smaller than the shift count type, promote it.
2356 if (ShiftSize > Op2Size)
2357 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2359 // If the operand is larger than the shift count type but the shift
2360 // count type has enough bits to represent any shift value, truncate
2361 // it now. This is a common case and it exposes the truncate to
2362 // optimization early.
2363 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2364 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2365 // Otherwise we'll need to temporarily settle for some other convenient
2366 // type. Type legalization will make adjustments once the shiftee is split.
2368 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2375 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2377 if (const OverflowingBinaryOperator *OFBinOp =
2378 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2379 nuw = OFBinOp->hasNoUnsignedWrap();
2380 nsw = OFBinOp->hasNoSignedWrap();
2382 if (const PossiblyExactOperator *ExactOp =
2383 dyn_cast<const PossiblyExactOperator>(&I))
2384 exact = ExactOp->isExact();
2387 Flags.setExact(exact);
2388 Flags.setNoSignedWrap(nsw);
2389 Flags.setNoUnsignedWrap(nuw);
2390 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2395 void SelectionDAGBuilder::visitSDiv(const User &I) {
2396 SDValue Op1 = getValue(I.getOperand(0));
2397 SDValue Op2 = getValue(I.getOperand(1));
2400 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2401 cast<PossiblyExactOperator>(&I)->isExact());
2402 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2406 void SelectionDAGBuilder::visitICmp(const User &I) {
2407 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2408 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2409 predicate = IC->getPredicate();
2410 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2411 predicate = ICmpInst::Predicate(IC->getPredicate());
2412 SDValue Op1 = getValue(I.getOperand(0));
2413 SDValue Op2 = getValue(I.getOperand(1));
2414 ISD::CondCode Opcode = getICmpCondCode(predicate);
2416 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2418 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2421 void SelectionDAGBuilder::visitFCmp(const User &I) {
2422 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2423 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2424 predicate = FC->getPredicate();
2425 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2426 predicate = FCmpInst::Predicate(FC->getPredicate());
2427 SDValue Op1 = getValue(I.getOperand(0));
2428 SDValue Op2 = getValue(I.getOperand(1));
2429 ISD::CondCode Condition = getFCmpCondCode(predicate);
2431 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2432 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2433 // further optimization, but currently FMF is only applicable to binary nodes.
2434 if (TM.Options.NoNaNsFPMath)
2435 Condition = getFCmpCodeWithoutNaN(Condition);
2436 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2438 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2441 void SelectionDAGBuilder::visitSelect(const User &I) {
2442 SmallVector<EVT, 4> ValueVTs;
2443 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2445 unsigned NumValues = ValueVTs.size();
2446 if (NumValues == 0) return;
2448 SmallVector<SDValue, 4> Values(NumValues);
2449 SDValue Cond = getValue(I.getOperand(0));
2450 SDValue LHSVal = getValue(I.getOperand(1));
2451 SDValue RHSVal = getValue(I.getOperand(2));
2452 auto BaseOps = {Cond};
2453 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2454 ISD::VSELECT : ISD::SELECT;
2456 // Min/max matching is only viable if all output VTs are the same.
2457 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2458 EVT VT = ValueVTs[0];
2459 LLVMContext &Ctx = *DAG.getContext();
2460 auto &TLI = DAG.getTargetLoweringInfo();
2461 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2462 VT = TLI.getTypeToTransformTo(Ctx, VT);
2465 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2466 ISD::NodeType Opc = ISD::DELETED_NODE;
2467 switch (SPR.Flavor) {
2468 case SPF_UMAX: Opc = ISD::UMAX; break;
2469 case SPF_UMIN: Opc = ISD::UMIN; break;
2470 case SPF_SMAX: Opc = ISD::SMAX; break;
2471 case SPF_SMIN: Opc = ISD::SMIN; break;
2473 switch (SPR.NaNBehavior) {
2474 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2475 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2476 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2477 case SPNB_RETURNS_ANY:
2478 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2484 switch (SPR.NaNBehavior) {
2485 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2486 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2487 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2488 case SPNB_RETURNS_ANY:
2489 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2497 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2498 // If the underlying comparison instruction is used by any other instruction,
2499 // the consumed instructions won't be destroyed, so it is not profitable
2500 // to convert to a min/max.
2501 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2503 LHSVal = getValue(LHS);
2504 RHSVal = getValue(RHS);
2509 for (unsigned i = 0; i != NumValues; ++i) {
2510 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2511 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2512 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2513 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2514 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2518 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2519 DAG.getVTList(ValueVTs), Values));
2522 void SelectionDAGBuilder::visitTrunc(const User &I) {
2523 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2524 SDValue N = getValue(I.getOperand(0));
2525 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2527 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2530 void SelectionDAGBuilder::visitZExt(const User &I) {
2531 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2532 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2533 SDValue N = getValue(I.getOperand(0));
2534 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2536 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2539 void SelectionDAGBuilder::visitSExt(const User &I) {
2540 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2541 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2542 SDValue N = getValue(I.getOperand(0));
2543 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2545 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2548 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2549 // FPTrunc is never a no-op cast, no need to check
2550 SDValue N = getValue(I.getOperand(0));
2551 SDLoc dl = getCurSDLoc();
2552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2553 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2554 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2555 DAG.getTargetConstant(
2556 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2559 void SelectionDAGBuilder::visitFPExt(const User &I) {
2560 // FPExt is never a no-op cast, no need to check
2561 SDValue N = getValue(I.getOperand(0));
2562 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2564 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2567 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2568 // FPToUI is never a no-op cast, no need to check
2569 SDValue N = getValue(I.getOperand(0));
2570 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2572 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2575 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2576 // FPToSI is never a no-op cast, no need to check
2577 SDValue N = getValue(I.getOperand(0));
2578 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2580 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2583 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2584 // UIToFP is never a no-op cast, no need to check
2585 SDValue N = getValue(I.getOperand(0));
2586 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2588 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2591 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2592 // SIToFP is never a no-op cast, no need to check
2593 SDValue N = getValue(I.getOperand(0));
2594 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2596 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2599 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2600 // What to do depends on the size of the integer and the size of the pointer.
2601 // We can either truncate, zero extend, or no-op, accordingly.
2602 SDValue N = getValue(I.getOperand(0));
2603 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2605 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2608 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2609 // What to do depends on the size of the integer and the size of the pointer.
2610 // We can either truncate, zero extend, or no-op, accordingly.
2611 SDValue N = getValue(I.getOperand(0));
2612 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2614 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2617 void SelectionDAGBuilder::visitBitCast(const User &I) {
2618 SDValue N = getValue(I.getOperand(0));
2619 SDLoc dl = getCurSDLoc();
2620 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2623 // BitCast assures us that source and destination are the same size so this is
2624 // either a BITCAST or a no-op.
2625 if (DestVT != N.getValueType())
2626 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2627 DestVT, N)); // convert types.
2628 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2629 // might fold any kind of constant expression to an integer constant and that
2630 // is not what we are looking for. Only regcognize a bitcast of a genuine
2631 // constant integer as an opaque constant.
2632 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2633 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2636 setValue(&I, N); // noop cast.
2639 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2641 const Value *SV = I.getOperand(0);
2642 SDValue N = getValue(SV);
2643 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2645 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2646 unsigned DestAS = I.getType()->getPointerAddressSpace();
2648 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2649 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2654 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2656 SDValue InVec = getValue(I.getOperand(0));
2657 SDValue InVal = getValue(I.getOperand(1));
2658 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2659 TLI.getVectorIdxTy(DAG.getDataLayout()));
2660 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2661 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2662 InVec, InVal, InIdx));
2665 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2667 SDValue InVec = getValue(I.getOperand(0));
2668 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2669 TLI.getVectorIdxTy(DAG.getDataLayout()));
2670 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2671 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2675 // Utility for visitShuffleVector - Return true if every element in Mask,
2676 // beginning from position Pos and ending in Pos+Size, falls within the
2677 // specified sequential range [L, L+Pos). or is undef.
2678 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2679 unsigned Pos, unsigned Size, int Low) {
2680 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2681 if (Mask[i] >= 0 && Mask[i] != Low)
2686 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2687 SDValue Src1 = getValue(I.getOperand(0));
2688 SDValue Src2 = getValue(I.getOperand(1));
2690 SmallVector<int, 8> Mask;
2691 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2692 unsigned MaskNumElts = Mask.size();
2694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2695 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2696 EVT SrcVT = Src1.getValueType();
2697 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2699 if (SrcNumElts == MaskNumElts) {
2700 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2705 // Normalize the shuffle vector since mask and vector length don't match.
2706 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2707 // Mask is longer than the source vectors and is a multiple of the source
2708 // vectors. We can use concatenate vector to make the mask and vectors
2710 if (SrcNumElts*2 == MaskNumElts) {
2711 // First check for Src1 in low and Src2 in high
2712 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2713 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2714 // The shuffle is concatenating two vectors together.
2715 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2719 // Then check for Src2 in low and Src1 in high
2720 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2721 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2722 // The shuffle is concatenating two vectors together.
2723 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2729 // Pad both vectors with undefs to make them the same length as the mask.
2730 unsigned NumConcat = MaskNumElts / SrcNumElts;
2731 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2732 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2733 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2735 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2736 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2740 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2741 getCurSDLoc(), VT, MOps1);
2742 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2743 getCurSDLoc(), VT, MOps2);
2745 // Readjust mask for new input vector length.
2746 SmallVector<int, 8> MappedOps;
2747 for (unsigned i = 0; i != MaskNumElts; ++i) {
2749 if (Idx >= (int)SrcNumElts)
2750 Idx -= SrcNumElts - MaskNumElts;
2751 MappedOps.push_back(Idx);
2754 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2759 if (SrcNumElts > MaskNumElts) {
2760 // Analyze the access pattern of the vector to see if we can extract
2761 // two subvectors and do the shuffle. The analysis is done by calculating
2762 // the range of elements the mask access on both vectors.
2763 int MinRange[2] = { static_cast<int>(SrcNumElts),
2764 static_cast<int>(SrcNumElts)};
2765 int MaxRange[2] = {-1, -1};
2767 for (unsigned i = 0; i != MaskNumElts; ++i) {
2773 if (Idx >= (int)SrcNumElts) {
2777 if (Idx > MaxRange[Input])
2778 MaxRange[Input] = Idx;
2779 if (Idx < MinRange[Input])
2780 MinRange[Input] = Idx;
2783 // Check if the access is smaller than the vector size and can we find
2784 // a reasonable extract index.
2785 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2787 int StartIdx[2]; // StartIdx to extract from
2788 for (unsigned Input = 0; Input < 2; ++Input) {
2789 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2790 RangeUse[Input] = 0; // Unused
2791 StartIdx[Input] = 0;
2795 // Find a good start index that is a multiple of the mask length. Then
2796 // see if the rest of the elements are in range.
2797 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2798 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2799 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2800 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2803 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2804 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2807 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2808 // Extract appropriate subvector and generate a vector shuffle
2809 for (unsigned Input = 0; Input < 2; ++Input) {
2810 SDValue &Src = Input == 0 ? Src1 : Src2;
2811 if (RangeUse[Input] == 0)
2812 Src = DAG.getUNDEF(VT);
2814 SDLoc dl = getCurSDLoc();
2816 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2817 DAG.getConstant(StartIdx[Input], dl,
2818 TLI.getVectorIdxTy(DAG.getDataLayout())));
2822 // Calculate new mask.
2823 SmallVector<int, 8> MappedOps;
2824 for (unsigned i = 0; i != MaskNumElts; ++i) {
2827 if (Idx < (int)SrcNumElts)
2830 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2832 MappedOps.push_back(Idx);
2835 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2841 // We can't use either concat vectors or extract subvectors so fall back to
2842 // replacing the shuffle with extract and build vector.
2843 // to insert and build vector.
2844 EVT EltVT = VT.getVectorElementType();
2845 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2846 SDLoc dl = getCurSDLoc();
2847 SmallVector<SDValue,8> Ops;
2848 for (unsigned i = 0; i != MaskNumElts; ++i) {
2853 Res = DAG.getUNDEF(EltVT);
2855 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2856 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2858 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2859 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2865 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2868 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2869 const Value *Op0 = I.getOperand(0);
2870 const Value *Op1 = I.getOperand(1);
2871 Type *AggTy = I.getType();
2872 Type *ValTy = Op1->getType();
2873 bool IntoUndef = isa<UndefValue>(Op0);
2874 bool FromUndef = isa<UndefValue>(Op1);
2876 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2879 SmallVector<EVT, 4> AggValueVTs;
2880 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2881 SmallVector<EVT, 4> ValValueVTs;
2882 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2884 unsigned NumAggValues = AggValueVTs.size();
2885 unsigned NumValValues = ValValueVTs.size();
2886 SmallVector<SDValue, 4> Values(NumAggValues);
2888 // Ignore an insertvalue that produces an empty object
2889 if (!NumAggValues) {
2890 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2894 SDValue Agg = getValue(Op0);
2896 // Copy the beginning value(s) from the original aggregate.
2897 for (; i != LinearIndex; ++i)
2898 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2899 SDValue(Agg.getNode(), Agg.getResNo() + i);
2900 // Copy values from the inserted value(s).
2902 SDValue Val = getValue(Op1);
2903 for (; i != LinearIndex + NumValValues; ++i)
2904 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2905 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2907 // Copy remaining value(s) from the original aggregate.
2908 for (; i != NumAggValues; ++i)
2909 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2910 SDValue(Agg.getNode(), Agg.getResNo() + i);
2912 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2913 DAG.getVTList(AggValueVTs), Values));
2916 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2917 const Value *Op0 = I.getOperand(0);
2918 Type *AggTy = Op0->getType();
2919 Type *ValTy = I.getType();
2920 bool OutOfUndef = isa<UndefValue>(Op0);
2922 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2925 SmallVector<EVT, 4> ValValueVTs;
2926 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2928 unsigned NumValValues = ValValueVTs.size();
2930 // Ignore a extractvalue that produces an empty object
2931 if (!NumValValues) {
2932 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2936 SmallVector<SDValue, 4> Values(NumValValues);
2938 SDValue Agg = getValue(Op0);
2939 // Copy out the selected value(s).
2940 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2941 Values[i - LinearIndex] =
2943 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2944 SDValue(Agg.getNode(), Agg.getResNo() + i);
2946 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2947 DAG.getVTList(ValValueVTs), Values));
2950 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2951 Value *Op0 = I.getOperand(0);
2952 // Note that the pointer operand may be a vector of pointers. Take the scalar
2953 // element which holds a pointer.
2954 Type *Ty = Op0->getType()->getScalarType();
2955 unsigned AS = Ty->getPointerAddressSpace();
2956 SDValue N = getValue(Op0);
2957 SDLoc dl = getCurSDLoc();
2959 // Normalize Vector GEP - all scalar operands should be converted to the
2961 unsigned VectorWidth = I.getType()->isVectorTy() ?
2962 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2964 if (VectorWidth && !N.getValueType().isVector()) {
2965 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2966 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2967 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2969 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2971 const Value *Idx = *OI;
2972 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2973 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2976 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2977 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2978 DAG.getConstant(Offset, dl, N.getValueType()));
2981 Ty = StTy->getElementType(Field);
2983 Ty = cast<SequentialType>(Ty)->getElementType();
2985 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2986 unsigned PtrSize = PtrTy.getSizeInBits();
2987 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2989 // If this is a scalar constant or a splat vector of constants,
2990 // handle it quickly.
2991 const auto *CI = dyn_cast<ConstantInt>(Idx);
2992 if (!CI && isa<ConstantDataVector>(Idx) &&
2993 cast<ConstantDataVector>(Idx)->getSplatValue())
2994 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2999 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3000 SDValue OffsVal = VectorWidth ?
3001 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3002 DAG.getConstant(Offs, dl, PtrTy);
3003 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
3007 // N = N + Idx * ElementSize;
3008 SDValue IdxN = getValue(Idx);
3010 if (!IdxN.getValueType().isVector() && VectorWidth) {
3011 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3012 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3013 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3015 // If the index is smaller or larger than intptr_t, truncate or extend
3017 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3019 // If this is a multiply by a power of two, turn it into a shl
3020 // immediately. This is a very common case.
3021 if (ElementSize != 1) {
3022 if (ElementSize.isPowerOf2()) {
3023 unsigned Amt = ElementSize.logBase2();
3024 IdxN = DAG.getNode(ISD::SHL, dl,
3025 N.getValueType(), IdxN,
3026 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3028 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3029 IdxN = DAG.getNode(ISD::MUL, dl,
3030 N.getValueType(), IdxN, Scale);
3034 N = DAG.getNode(ISD::ADD, dl,
3035 N.getValueType(), N, IdxN);
3042 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3043 // If this is a fixed sized alloca in the entry block of the function,
3044 // allocate it statically on the stack.
3045 if (FuncInfo.StaticAllocaMap.count(&I))
3046 return; // getValue will auto-populate this.
3048 SDLoc dl = getCurSDLoc();
3049 Type *Ty = I.getAllocatedType();
3050 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3051 auto &DL = DAG.getDataLayout();
3052 uint64_t TySize = DL.getTypeAllocSize(Ty);
3054 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3056 SDValue AllocSize = getValue(I.getArraySize());
3058 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3059 if (AllocSize.getValueType() != IntPtr)
3060 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3062 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3064 DAG.getConstant(TySize, dl, IntPtr));
3066 // Handle alignment. If the requested alignment is less than or equal to
3067 // the stack alignment, ignore it. If the size is greater than or equal to
3068 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3069 unsigned StackAlign =
3070 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3071 if (Align <= StackAlign)
3074 // Round the size of the allocation up to the stack alignment size
3075 // by add SA-1 to the size.
3076 AllocSize = DAG.getNode(ISD::ADD, dl,
3077 AllocSize.getValueType(), AllocSize,
3078 DAG.getIntPtrConstant(StackAlign - 1, dl));
3080 // Mask out the low bits for alignment purposes.
3081 AllocSize = DAG.getNode(ISD::AND, dl,
3082 AllocSize.getValueType(), AllocSize,
3083 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3086 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3087 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3088 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3090 DAG.setRoot(DSA.getValue(1));
3092 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3095 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3097 return visitAtomicLoad(I);
3099 const Value *SV = I.getOperand(0);
3100 SDValue Ptr = getValue(SV);
3102 Type *Ty = I.getType();
3104 bool isVolatile = I.isVolatile();
3105 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3107 // The IR notion of invariant_load only guarantees that all *non-faulting*
3108 // invariant loads result in the same value. The MI notion of invariant load
3109 // guarantees that the load can be legally moved to any location within its
3110 // containing function. The MI notion of invariant_load is stronger than the
3111 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3112 // with a guarantee that the location being loaded from is dereferenceable
3113 // throughout the function's lifetime.
3115 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3116 isDereferenceablePointer(SV, DAG.getDataLayout());
3117 unsigned Alignment = I.getAlignment();
3120 I.getAAMetadata(AAInfo);
3121 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3123 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3124 SmallVector<EVT, 4> ValueVTs;
3125 SmallVector<uint64_t, 4> Offsets;
3126 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3127 unsigned NumValues = ValueVTs.size();
3132 bool ConstantMemory = false;
3133 if (isVolatile || NumValues > MaxParallelChains)
3134 // Serialize volatile loads with other side effects.
3136 else if (AA->pointsToConstantMemory(MemoryLocation(
3137 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3138 // Do not serialize (non-volatile) loads of constant memory with anything.
3139 Root = DAG.getEntryNode();
3140 ConstantMemory = true;
3142 // Do not serialize non-volatile loads against each other.
3143 Root = DAG.getRoot();
3146 SDLoc dl = getCurSDLoc();
3149 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3151 SmallVector<SDValue, 4> Values(NumValues);
3152 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3153 EVT PtrVT = Ptr.getValueType();
3154 unsigned ChainI = 0;
3155 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3156 // Serializing loads here may result in excessive register pressure, and
3157 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3158 // could recover a bit by hoisting nodes upward in the chain by recognizing
3159 // they are side-effect free or do not alias. The optimizer should really
3160 // avoid this case by converting large object/array copies to llvm.memcpy
3161 // (MaxParallelChains should always remain as failsafe).
3162 if (ChainI == MaxParallelChains) {
3163 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3164 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3165 makeArrayRef(Chains.data(), ChainI));
3169 SDValue A = DAG.getNode(ISD::ADD, dl,
3171 DAG.getConstant(Offsets[i], dl, PtrVT));
3172 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3173 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3174 isNonTemporal, isInvariant, Alignment, AAInfo,
3178 Chains[ChainI] = L.getValue(1);
3181 if (!ConstantMemory) {
3182 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3183 makeArrayRef(Chains.data(), ChainI));
3187 PendingLoads.push_back(Chain);
3190 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3191 DAG.getVTList(ValueVTs), Values));
3194 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3196 return visitAtomicStore(I);
3198 const Value *SrcV = I.getOperand(0);
3199 const Value *PtrV = I.getOperand(1);
3201 SmallVector<EVT, 4> ValueVTs;
3202 SmallVector<uint64_t, 4> Offsets;
3203 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3204 SrcV->getType(), ValueVTs, &Offsets);
3205 unsigned NumValues = ValueVTs.size();
3209 // Get the lowered operands. Note that we do this after
3210 // checking if NumResults is zero, because with zero results
3211 // the operands won't have values in the map.
3212 SDValue Src = getValue(SrcV);
3213 SDValue Ptr = getValue(PtrV);
3215 SDValue Root = getRoot();
3216 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3217 EVT PtrVT = Ptr.getValueType();
3218 bool isVolatile = I.isVolatile();
3219 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3220 unsigned Alignment = I.getAlignment();
3221 SDLoc dl = getCurSDLoc();
3224 I.getAAMetadata(AAInfo);
3226 unsigned ChainI = 0;
3227 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3228 // See visitLoad comments.
3229 if (ChainI == MaxParallelChains) {
3230 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3231 makeArrayRef(Chains.data(), ChainI));
3235 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3236 DAG.getConstant(Offsets[i], dl, PtrVT));
3237 SDValue St = DAG.getStore(Root, dl,
3238 SDValue(Src.getNode(), Src.getResNo() + i),
3239 Add, MachinePointerInfo(PtrV, Offsets[i]),
3240 isVolatile, isNonTemporal, Alignment, AAInfo);
3241 Chains[ChainI] = St;
3244 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3245 makeArrayRef(Chains.data(), ChainI));
3246 DAG.setRoot(StoreNode);
3249 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3250 SDLoc sdl = getCurSDLoc();
3252 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3253 Value *PtrOperand = I.getArgOperand(1);
3254 SDValue Ptr = getValue(PtrOperand);
3255 SDValue Src0 = getValue(I.getArgOperand(0));
3256 SDValue Mask = getValue(I.getArgOperand(3));
3257 EVT VT = Src0.getValueType();
3258 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3260 Alignment = DAG.getEVTAlignment(VT);
3263 I.getAAMetadata(AAInfo);
3265 MachineMemOperand *MMO =
3266 DAG.getMachineFunction().
3267 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3268 MachineMemOperand::MOStore, VT.getStoreSize(),
3270 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3272 DAG.setRoot(StoreNode);
3273 setValue(&I, StoreNode);
3276 // Get a uniform base for the Gather/Scatter intrinsic.
3277 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3278 // We try to represent it as a base pointer + vector of indices.
3279 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3280 // The first operand of the GEP may be a single pointer or a vector of pointers
3282 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3284 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3285 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3287 // When the first GEP operand is a single pointer - it is the uniform base we
3288 // are looking for. If first operand of the GEP is a splat vector - we
3289 // extract the spalt value and use it as a uniform base.
3290 // In all other cases the function returns 'false'.
3292 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3293 SelectionDAGBuilder* SDB) {
3295 SelectionDAG& DAG = SDB->DAG;
3296 LLVMContext &Context = *DAG.getContext();
3298 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3299 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3300 if (!GEP || GEP->getNumOperands() > 2)
3303 Value *GEPPtr = GEP->getPointerOperand();
3304 if (!GEPPtr->getType()->isVectorTy())
3306 else if (!(Ptr = getSplatValue(GEPPtr)))
3309 Value *IndexVal = GEP->getOperand(1);
3311 // The operands of the GEP may be defined in another basic block.
3312 // In this case we'll not find nodes for the operands.
3313 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3316 Base = SDB->getValue(Ptr);
3317 Index = SDB->getValue(IndexVal);
3319 // Suppress sign extension.
3320 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3321 if (SDB->findValue(Sext->getOperand(0))) {
3322 IndexVal = Sext->getOperand(0);
3323 Index = SDB->getValue(IndexVal);
3326 if (!Index.getValueType().isVector()) {
3327 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3328 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3329 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3330 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3335 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3336 SDLoc sdl = getCurSDLoc();
3338 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3339 Value *Ptr = I.getArgOperand(1);
3340 SDValue Src0 = getValue(I.getArgOperand(0));
3341 SDValue Mask = getValue(I.getArgOperand(3));
3342 EVT VT = Src0.getValueType();
3343 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3345 Alignment = DAG.getEVTAlignment(VT);
3346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3349 I.getAAMetadata(AAInfo);
3353 Value *BasePtr = Ptr;
3354 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3356 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3357 MachineMemOperand *MMO = DAG.getMachineFunction().
3358 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3359 MachineMemOperand::MOStore, VT.getStoreSize(),
3362 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3363 Index = getValue(Ptr);
3365 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3366 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3368 DAG.setRoot(Scatter);
3369 setValue(&I, Scatter);
3372 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3373 SDLoc sdl = getCurSDLoc();
3375 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3376 Value *PtrOperand = I.getArgOperand(0);
3377 SDValue Ptr = getValue(PtrOperand);
3378 SDValue Src0 = getValue(I.getArgOperand(3));
3379 SDValue Mask = getValue(I.getArgOperand(2));
3381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3382 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3383 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3385 Alignment = DAG.getEVTAlignment(VT);
3388 I.getAAMetadata(AAInfo);
3389 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3391 SDValue InChain = DAG.getRoot();
3392 if (AA->pointsToConstantMemory(MemoryLocation(
3393 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3395 // Do not serialize (non-volatile) loads of constant memory with anything.
3396 InChain = DAG.getEntryNode();
3399 MachineMemOperand *MMO =
3400 DAG.getMachineFunction().
3401 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3402 MachineMemOperand::MOLoad, VT.getStoreSize(),
3403 Alignment, AAInfo, Ranges);
3405 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3407 SDValue OutChain = Load.getValue(1);
3408 DAG.setRoot(OutChain);
3412 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3413 SDLoc sdl = getCurSDLoc();
3415 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3416 Value *Ptr = I.getArgOperand(0);
3417 SDValue Src0 = getValue(I.getArgOperand(3));
3418 SDValue Mask = getValue(I.getArgOperand(2));
3420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3421 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3422 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3424 Alignment = DAG.getEVTAlignment(VT);
3427 I.getAAMetadata(AAInfo);
3428 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3430 SDValue Root = DAG.getRoot();
3433 Value *BasePtr = Ptr;
3434 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3435 bool ConstantMemory = false;
3437 AA->pointsToConstantMemory(MemoryLocation(
3438 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3440 // Do not serialize (non-volatile) loads of constant memory with anything.
3441 Root = DAG.getEntryNode();
3442 ConstantMemory = true;
3445 MachineMemOperand *MMO =
3446 DAG.getMachineFunction().
3447 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3448 MachineMemOperand::MOLoad, VT.getStoreSize(),
3449 Alignment, AAInfo, Ranges);
3452 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3453 Index = getValue(Ptr);
3455 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3456 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3459 SDValue OutChain = Gather.getValue(1);
3460 if (!ConstantMemory)
3461 PendingLoads.push_back(OutChain);
3462 setValue(&I, Gather);
3465 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3466 SDLoc dl = getCurSDLoc();
3467 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3468 AtomicOrdering FailureOrder = I.getFailureOrdering();
3469 SynchronizationScope Scope = I.getSynchScope();
3471 SDValue InChain = getRoot();
3473 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3474 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3475 SDValue L = DAG.getAtomicCmpSwap(
3476 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3477 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3478 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3479 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3481 SDValue OutChain = L.getValue(2);
3484 DAG.setRoot(OutChain);
3487 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3488 SDLoc dl = getCurSDLoc();
3490 switch (I.getOperation()) {
3491 default: llvm_unreachable("Unknown atomicrmw operation");
3492 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3493 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3494 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3495 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3496 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3497 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3498 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3499 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3500 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3501 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3502 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3504 AtomicOrdering Order = I.getOrdering();
3505 SynchronizationScope Scope = I.getSynchScope();
3507 SDValue InChain = getRoot();
3510 DAG.getAtomic(NT, dl,
3511 getValue(I.getValOperand()).getSimpleValueType(),
3513 getValue(I.getPointerOperand()),
3514 getValue(I.getValOperand()),
3515 I.getPointerOperand(),
3516 /* Alignment=*/ 0, Order, Scope);
3518 SDValue OutChain = L.getValue(1);
3521 DAG.setRoot(OutChain);
3524 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3525 SDLoc dl = getCurSDLoc();
3526 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3529 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3530 TLI.getPointerTy(DAG.getDataLayout()));
3531 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3532 TLI.getPointerTy(DAG.getDataLayout()));
3533 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3536 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3537 SDLoc dl = getCurSDLoc();
3538 AtomicOrdering Order = I.getOrdering();
3539 SynchronizationScope Scope = I.getSynchScope();
3541 SDValue InChain = getRoot();
3543 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3544 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3546 if (I.getAlignment() < VT.getSizeInBits() / 8)
3547 report_fatal_error("Cannot generate unaligned atomic load");
3549 MachineMemOperand *MMO =
3550 DAG.getMachineFunction().
3551 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3552 MachineMemOperand::MOVolatile |
3553 MachineMemOperand::MOLoad,
3555 I.getAlignment() ? I.getAlignment() :
3556 DAG.getEVTAlignment(VT));
3558 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3560 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3561 getValue(I.getPointerOperand()), MMO,
3564 SDValue OutChain = L.getValue(1);
3567 DAG.setRoot(OutChain);
3570 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3571 SDLoc dl = getCurSDLoc();
3573 AtomicOrdering Order = I.getOrdering();
3574 SynchronizationScope Scope = I.getSynchScope();
3576 SDValue InChain = getRoot();
3578 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3580 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3582 if (I.getAlignment() < VT.getSizeInBits() / 8)
3583 report_fatal_error("Cannot generate unaligned atomic store");
3586 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3588 getValue(I.getPointerOperand()),
3589 getValue(I.getValueOperand()),
3590 I.getPointerOperand(), I.getAlignment(),
3593 DAG.setRoot(OutChain);
3596 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3598 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3599 unsigned Intrinsic) {
3600 bool HasChain = !I.doesNotAccessMemory();
3601 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3603 // Build the operand list.
3604 SmallVector<SDValue, 8> Ops;
3605 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3607 // We don't need to serialize loads against other loads.
3608 Ops.push_back(DAG.getRoot());
3610 Ops.push_back(getRoot());
3614 // Info is set by getTgtMemInstrinsic
3615 TargetLowering::IntrinsicInfo Info;
3616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3617 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3619 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3620 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3621 Info.opc == ISD::INTRINSIC_W_CHAIN)
3622 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3623 TLI.getPointerTy(DAG.getDataLayout())));
3625 // Add all operands of the call to the operand list.
3626 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3627 SDValue Op = getValue(I.getArgOperand(i));
3631 SmallVector<EVT, 4> ValueVTs;
3632 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3635 ValueVTs.push_back(MVT::Other);
3637 SDVTList VTs = DAG.getVTList(ValueVTs);
3641 if (IsTgtIntrinsic) {
3642 // This is target intrinsic that touches memory
3643 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3644 VTs, Ops, Info.memVT,
3645 MachinePointerInfo(Info.ptrVal, Info.offset),
3646 Info.align, Info.vol,
3647 Info.readMem, Info.writeMem, Info.size);
3648 } else if (!HasChain) {
3649 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3650 } else if (!I.getType()->isVoidTy()) {
3651 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3653 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3657 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3659 PendingLoads.push_back(Chain);
3664 if (!I.getType()->isVoidTy()) {
3665 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3666 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3667 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3670 setValue(&I, Result);
3674 /// GetSignificand - Get the significand and build it into a floating-point
3675 /// number with exponent of 1:
3677 /// Op = (Op & 0x007fffff) | 0x3f800000;
3679 /// where Op is the hexadecimal representation of floating point value.
3681 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3682 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3683 DAG.getConstant(0x007fffff, dl, MVT::i32));
3684 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3685 DAG.getConstant(0x3f800000, dl, MVT::i32));
3686 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3689 /// GetExponent - Get the exponent:
3691 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3693 /// where Op is the hexadecimal representation of floating point value.
3695 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3697 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3698 DAG.getConstant(0x7f800000, dl, MVT::i32));
3699 SDValue t1 = DAG.getNode(
3700 ISD::SRL, dl, MVT::i32, t0,
3701 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3702 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3703 DAG.getConstant(127, dl, MVT::i32));
3704 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3707 /// getF32Constant - Get 32-bit floating point constant.
3709 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3710 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3714 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3715 SelectionDAG &DAG) {
3716 // TODO: What fast-math-flags should be set on the floating-point nodes?
3718 // IntegerPartOfX = ((int32_t)(t0);
3719 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3721 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3722 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3723 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3725 // IntegerPartOfX <<= 23;
3726 IntegerPartOfX = DAG.getNode(
3727 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3728 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3729 DAG.getDataLayout())));
3731 SDValue TwoToFractionalPartOfX;
3732 if (LimitFloatPrecision <= 6) {
3733 // For floating-point precision of 6:
3735 // TwoToFractionalPartOfX =
3737 // (0.735607626f + 0.252464424f * x) * x;
3739 // error 0.0144103317, which is 6 bits
3740 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3741 getF32Constant(DAG, 0x3e814304, dl));
3742 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3743 getF32Constant(DAG, 0x3f3c50c8, dl));
3744 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3745 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3746 getF32Constant(DAG, 0x3f7f5e7e, dl));
3747 } else if (LimitFloatPrecision <= 12) {
3748 // For floating-point precision of 12:
3750 // TwoToFractionalPartOfX =
3753 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3755 // error 0.000107046256, which is 13 to 14 bits
3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3757 getF32Constant(DAG, 0x3da235e3, dl));
3758 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3e65b8f3, dl));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x3f324b07, dl));
3763 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3764 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3765 getF32Constant(DAG, 0x3f7ff8fd, dl));
3766 } else { // LimitFloatPrecision <= 18
3767 // For floating-point precision of 18:
3769 // TwoToFractionalPartOfX =
3773 // (0.554906021e-1f +
3774 // (0.961591928e-2f +
3775 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3776 // error 2.47208000*10^(-7), which is better than 18 bits
3777 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3778 getF32Constant(DAG, 0x3924b03e, dl));
3779 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3780 getF32Constant(DAG, 0x3ab24b87, dl));
3781 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3782 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3783 getF32Constant(DAG, 0x3c1d8c17, dl));
3784 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3785 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3786 getF32Constant(DAG, 0x3d634a1d, dl));
3787 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3788 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3789 getF32Constant(DAG, 0x3e75fe14, dl));
3790 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3791 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3792 getF32Constant(DAG, 0x3f317234, dl));
3793 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3794 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3795 getF32Constant(DAG, 0x3f800000, dl));
3798 // Add the exponent into the result in integer domain.
3799 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3800 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3801 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3804 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3805 /// limited-precision mode.
3806 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3807 const TargetLowering &TLI) {
3808 if (Op.getValueType() == MVT::f32 &&
3809 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3811 // Put the exponent in the right bit position for later addition to the
3814 // #define LOG2OFe 1.4426950f
3815 // t0 = Op * LOG2OFe
3817 // TODO: What fast-math-flags should be set here?
3818 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3819 getF32Constant(DAG, 0x3fb8aa3b, dl));
3820 return getLimitedPrecisionExp2(t0, dl, DAG);
3823 // No special expansion.
3824 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3827 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3828 /// limited-precision mode.
3829 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3830 const TargetLowering &TLI) {
3832 // TODO: What fast-math-flags should be set on the floating-point nodes?
3834 if (Op.getValueType() == MVT::f32 &&
3835 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3836 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3838 // Scale the exponent by log(2) [0.69314718f].
3839 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3840 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3841 getF32Constant(DAG, 0x3f317218, dl));
3843 // Get the significand and build it into a floating-point number with
3845 SDValue X = GetSignificand(DAG, Op1, dl);
3847 SDValue LogOfMantissa;
3848 if (LimitFloatPrecision <= 6) {
3849 // For floating-point precision of 6:
3853 // (1.4034025f - 0.23903021f * x) * x;
3855 // error 0.0034276066, which is better than 8 bits
3856 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3857 getF32Constant(DAG, 0xbe74c456, dl));
3858 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3859 getF32Constant(DAG, 0x3fb3a2b1, dl));
3860 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3861 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3862 getF32Constant(DAG, 0x3f949a29, dl));
3863 } else if (LimitFloatPrecision <= 12) {
3864 // For floating-point precision of 12:
3870 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3872 // error 0.000061011436, which is 14 bits
3873 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3874 getF32Constant(DAG, 0xbd67b6d6, dl));
3875 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3876 getF32Constant(DAG, 0x3ee4f4b8, dl));
3877 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3878 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3879 getF32Constant(DAG, 0x3fbc278b, dl));
3880 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3881 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3882 getF32Constant(DAG, 0x40348e95, dl));
3883 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3884 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3885 getF32Constant(DAG, 0x3fdef31a, dl));
3886 } else { // LimitFloatPrecision <= 18
3887 // For floating-point precision of 18:
3895 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3897 // error 0.0000023660568, which is better than 18 bits
3898 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3899 getF32Constant(DAG, 0xbc91e5ac, dl));
3900 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3901 getF32Constant(DAG, 0x3e4350aa, dl));
3902 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3903 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3904 getF32Constant(DAG, 0x3f60d3e3, dl));
3905 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3906 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3907 getF32Constant(DAG, 0x4011cdf0, dl));
3908 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3909 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3910 getF32Constant(DAG, 0x406cfd1c, dl));
3911 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3912 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3913 getF32Constant(DAG, 0x408797cb, dl));
3914 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3915 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3916 getF32Constant(DAG, 0x4006dcab, dl));
3919 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3922 // No special expansion.
3923 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3926 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3927 /// limited-precision mode.
3928 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3929 const TargetLowering &TLI) {
3931 // TODO: What fast-math-flags should be set on the floating-point nodes?
3933 if (Op.getValueType() == MVT::f32 &&
3934 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3935 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3937 // Get the exponent.
3938 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3940 // Get the significand and build it into a floating-point number with
3942 SDValue X = GetSignificand(DAG, Op1, dl);
3944 // Different possible minimax approximations of significand in
3945 // floating-point for various degrees of accuracy over [1,2].
3946 SDValue Log2ofMantissa;
3947 if (LimitFloatPrecision <= 6) {
3948 // For floating-point precision of 6:
3950 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3952 // error 0.0049451742, which is more than 7 bits
3953 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3954 getF32Constant(DAG, 0xbeb08fe0, dl));
3955 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3956 getF32Constant(DAG, 0x40019463, dl));
3957 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3958 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3959 getF32Constant(DAG, 0x3fd6633d, dl));
3960 } else if (LimitFloatPrecision <= 12) {
3961 // For floating-point precision of 12:
3967 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3969 // error 0.0000876136000, which is better than 13 bits
3970 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3971 getF32Constant(DAG, 0xbda7262e, dl));
3972 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3973 getF32Constant(DAG, 0x3f25280b, dl));
3974 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3975 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3976 getF32Constant(DAG, 0x4007b923, dl));
3977 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3978 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3979 getF32Constant(DAG, 0x40823e2f, dl));
3980 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3981 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3982 getF32Constant(DAG, 0x4020d29c, dl));
3983 } else { // LimitFloatPrecision <= 18
3984 // For floating-point precision of 18:
3993 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3995 // error 0.0000018516, which is better than 18 bits
3996 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3997 getF32Constant(DAG, 0xbcd2769e, dl));
3998 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3999 getF32Constant(DAG, 0x3e8ce0b9, dl));
4000 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4001 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4002 getF32Constant(DAG, 0x3fa22ae7, dl));
4003 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4004 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4005 getF32Constant(DAG, 0x40525723, dl));
4006 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4007 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4008 getF32Constant(DAG, 0x40aaf200, dl));
4009 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4010 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4011 getF32Constant(DAG, 0x40c39dad, dl));
4012 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4013 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4014 getF32Constant(DAG, 0x4042902c, dl));
4017 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4020 // No special expansion.
4021 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4024 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4025 /// limited-precision mode.
4026 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4027 const TargetLowering &TLI) {
4029 // TODO: What fast-math-flags should be set on the floating-point nodes?
4031 if (Op.getValueType() == MVT::f32 &&
4032 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4033 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4035 // Scale the exponent by log10(2) [0.30102999f].
4036 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4037 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4038 getF32Constant(DAG, 0x3e9a209a, dl));
4040 // Get the significand and build it into a floating-point number with
4042 SDValue X = GetSignificand(DAG, Op1, dl);
4044 SDValue Log10ofMantissa;
4045 if (LimitFloatPrecision <= 6) {
4046 // For floating-point precision of 6:
4048 // Log10ofMantissa =
4050 // (0.60948995f - 0.10380950f * x) * x;
4052 // error 0.0014886165, which is 6 bits
4053 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4054 getF32Constant(DAG, 0xbdd49a13, dl));
4055 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4056 getF32Constant(DAG, 0x3f1c0789, dl));
4057 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4058 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4059 getF32Constant(DAG, 0x3f011300, dl));
4060 } else if (LimitFloatPrecision <= 12) {
4061 // For floating-point precision of 12:
4063 // Log10ofMantissa =
4066 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4068 // error 0.00019228036, which is better than 12 bits
4069 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4070 getF32Constant(DAG, 0x3d431f31, dl));
4071 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4072 getF32Constant(DAG, 0x3ea21fb2, dl));
4073 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4074 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4075 getF32Constant(DAG, 0x3f6ae232, dl));
4076 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4077 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4078 getF32Constant(DAG, 0x3f25f7c3, dl));
4079 } else { // LimitFloatPrecision <= 18
4080 // For floating-point precision of 18:
4082 // Log10ofMantissa =
4087 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4089 // error 0.0000037995730, which is better than 18 bits
4090 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4091 getF32Constant(DAG, 0x3c5d51ce, dl));
4092 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4093 getF32Constant(DAG, 0x3e00685a, dl));
4094 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4095 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4096 getF32Constant(DAG, 0x3efb6798, dl));
4097 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4098 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4099 getF32Constant(DAG, 0x3f88d192, dl));
4100 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4101 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4102 getF32Constant(DAG, 0x3fc4316c, dl));
4103 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4104 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4105 getF32Constant(DAG, 0x3f57ce70, dl));
4108 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4111 // No special expansion.
4112 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4115 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4116 /// limited-precision mode.
4117 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4118 const TargetLowering &TLI) {
4119 if (Op.getValueType() == MVT::f32 &&
4120 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4121 return getLimitedPrecisionExp2(Op, dl, DAG);
4123 // No special expansion.
4124 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4127 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4128 /// limited-precision mode with x == 10.0f.
4129 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4130 SelectionDAG &DAG, const TargetLowering &TLI) {
4131 bool IsExp10 = false;
4132 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4133 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4134 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4136 IsExp10 = LHSC->isExactlyValue(Ten);
4140 // TODO: What fast-math-flags should be set on the FMUL node?
4142 // Put the exponent in the right bit position for later addition to the
4145 // #define LOG2OF10 3.3219281f
4146 // t0 = Op * LOG2OF10;
4147 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4148 getF32Constant(DAG, 0x40549a78, dl));
4149 return getLimitedPrecisionExp2(t0, dl, DAG);
4152 // No special expansion.
4153 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4157 /// ExpandPowI - Expand a llvm.powi intrinsic.
4158 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4159 SelectionDAG &DAG) {
4160 // If RHS is a constant, we can expand this out to a multiplication tree,
4161 // otherwise we end up lowering to a call to __powidf2 (for example). When
4162 // optimizing for size, we only want to do this if the expansion would produce
4163 // a small number of multiplies, otherwise we do the full expansion.
4164 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4165 // Get the exponent as a positive value.
4166 unsigned Val = RHSC->getSExtValue();
4167 if ((int)Val < 0) Val = -Val;
4169 // powi(x, 0) -> 1.0
4171 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4173 const Function *F = DAG.getMachineFunction().getFunction();
4174 if (!F->optForSize() ||
4175 // If optimizing for size, don't insert too many multiplies.
4176 // This inserts up to 5 multiplies.
4177 countPopulation(Val) + Log2_32(Val) < 7) {
4178 // We use the simple binary decomposition method to generate the multiply
4179 // sequence. There are more optimal ways to do this (for example,
4180 // powi(x,15) generates one more multiply than it should), but this has
4181 // the benefit of being both really simple and much better than a libcall.
4182 SDValue Res; // Logically starts equal to 1.0
4183 SDValue CurSquare = LHS;
4184 // TODO: Intrinsics should have fast-math-flags that propagate to these
4189 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4191 Res = CurSquare; // 1.0*CurSquare.
4194 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4195 CurSquare, CurSquare);
4199 // If the original was negative, invert the result, producing 1/(x*x*x).
4200 if (RHSC->getSExtValue() < 0)
4201 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4202 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4207 // Otherwise, expand to a libcall.
4208 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4211 // getUnderlyingArgReg - Find underlying register used for a truncated or
4212 // bitcasted argument.
4213 static unsigned getUnderlyingArgReg(const SDValue &N) {
4214 switch (N.getOpcode()) {
4215 case ISD::CopyFromReg:
4216 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4218 case ISD::AssertZext:
4219 case ISD::AssertSext:
4221 return getUnderlyingArgReg(N.getOperand(0));
4227 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4228 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4229 /// At the end of instruction selection, they will be inserted to the entry BB.
4230 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4231 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4232 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4233 const Argument *Arg = dyn_cast<Argument>(V);
4237 MachineFunction &MF = DAG.getMachineFunction();
4238 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4240 // Ignore inlined function arguments here.
4242 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4243 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4246 Optional<MachineOperand> Op;
4247 // Some arguments' frame index is recorded during argument lowering.
4248 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4249 Op = MachineOperand::CreateFI(FI);
4251 if (!Op && N.getNode()) {
4252 unsigned Reg = getUnderlyingArgReg(N);
4253 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4254 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4255 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4260 Op = MachineOperand::CreateReg(Reg, false);
4264 // Check if ValueMap has reg number.
4265 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4266 if (VMI != FuncInfo.ValueMap.end())
4267 Op = MachineOperand::CreateReg(VMI->second, false);
4270 if (!Op && N.getNode())
4271 // Check if frame index is available.
4272 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4273 if (FrameIndexSDNode *FINode =
4274 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4275 Op = MachineOperand::CreateFI(FINode->getIndex());
4280 assert(Variable->isValidLocationForIntrinsic(DL) &&
4281 "Expected inlined-at fields to agree");
4283 FuncInfo.ArgDbgValues.push_back(
4284 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4285 Op->getReg(), Offset, Variable, Expr));
4287 FuncInfo.ArgDbgValues.push_back(
4288 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4291 .addMetadata(Variable)
4292 .addMetadata(Expr));
4297 // VisualStudio defines setjmp as _setjmp
4298 #if defined(_MSC_VER) && defined(setjmp) && \
4299 !defined(setjmp_undefined_for_msvc)
4300 # pragma push_macro("setjmp")
4302 # define setjmp_undefined_for_msvc
4305 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4306 /// we want to emit this as a call to a named external function, return the name
4307 /// otherwise lower it and return null.
4309 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4311 SDLoc sdl = getCurSDLoc();
4312 DebugLoc dl = getCurDebugLoc();
4315 switch (Intrinsic) {
4317 // By default, turn this into a target intrinsic node.
4318 visitTargetIntrinsic(I, Intrinsic);
4320 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4321 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4322 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4323 case Intrinsic::returnaddress:
4324 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4325 TLI.getPointerTy(DAG.getDataLayout()),
4326 getValue(I.getArgOperand(0))));
4328 case Intrinsic::frameaddress:
4329 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4330 TLI.getPointerTy(DAG.getDataLayout()),
4331 getValue(I.getArgOperand(0))));
4333 case Intrinsic::read_register: {
4334 Value *Reg = I.getArgOperand(0);
4335 SDValue Chain = getRoot();
4337 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4338 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4339 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4340 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4342 DAG.setRoot(Res.getValue(1));
4345 case Intrinsic::write_register: {
4346 Value *Reg = I.getArgOperand(0);
4347 Value *RegValue = I.getArgOperand(1);
4348 SDValue Chain = getRoot();
4350 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4351 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4352 RegName, getValue(RegValue)));
4355 case Intrinsic::setjmp:
4356 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4357 case Intrinsic::longjmp:
4358 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4359 case Intrinsic::memcpy: {
4360 // FIXME: this definition of "user defined address space" is x86-specific
4361 // Assert for address < 256 since we support only user defined address
4363 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4365 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4367 "Unknown address space");
4368 SDValue Op1 = getValue(I.getArgOperand(0));
4369 SDValue Op2 = getValue(I.getArgOperand(1));
4370 SDValue Op3 = getValue(I.getArgOperand(2));
4371 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4373 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4374 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4375 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4376 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4378 MachinePointerInfo(I.getArgOperand(0)),
4379 MachinePointerInfo(I.getArgOperand(1)));
4380 updateDAGForMaybeTailCall(MC);
4383 case Intrinsic::memset: {
4384 // FIXME: this definition of "user defined address space" is x86-specific
4385 // Assert for address < 256 since we support only user defined address
4387 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4389 "Unknown address space");
4390 SDValue Op1 = getValue(I.getArgOperand(0));
4391 SDValue Op2 = getValue(I.getArgOperand(1));
4392 SDValue Op3 = getValue(I.getArgOperand(2));
4393 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4395 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4396 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4397 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4398 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4399 isTC, MachinePointerInfo(I.getArgOperand(0)));
4400 updateDAGForMaybeTailCall(MS);
4403 case Intrinsic::memmove: {
4404 // FIXME: this definition of "user defined address space" is x86-specific
4405 // Assert for address < 256 since we support only user defined address
4407 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4409 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4411 "Unknown address space");
4412 SDValue Op1 = getValue(I.getArgOperand(0));
4413 SDValue Op2 = getValue(I.getArgOperand(1));
4414 SDValue Op3 = getValue(I.getArgOperand(2));
4415 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4417 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4418 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4419 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4420 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4421 isTC, MachinePointerInfo(I.getArgOperand(0)),
4422 MachinePointerInfo(I.getArgOperand(1)));
4423 updateDAGForMaybeTailCall(MM);
4426 case Intrinsic::dbg_declare: {
4427 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4428 DILocalVariable *Variable = DI.getVariable();
4429 DIExpression *Expression = DI.getExpression();
4430 const Value *Address = DI.getAddress();
4431 assert(Variable && "Missing variable");
4433 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4437 // Check if address has undef value.
4438 if (isa<UndefValue>(Address) ||
4439 (Address->use_empty() && !isa<Argument>(Address))) {
4440 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4444 SDValue &N = NodeMap[Address];
4445 if (!N.getNode() && isa<Argument>(Address))
4446 // Check unused arguments map.
4447 N = UnusedArgNodeMap[Address];
4450 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4451 Address = BCI->getOperand(0);
4452 // Parameters are handled specially.
4453 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4455 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4457 if (isParameter && !AI) {
4458 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4460 // Byval parameter. We have a frame index at this point.
4461 SDV = DAG.getFrameIndexDbgValue(
4462 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4464 // Address is an argument, so try to emit its dbg value using
4465 // virtual register info from the FuncInfo.ValueMap.
4466 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4471 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4472 true, 0, dl, SDNodeOrder);
4474 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4476 // If Address is an argument then try to emit its dbg value using
4477 // virtual register info from the FuncInfo.ValueMap.
4478 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4480 // If variable is pinned by a alloca in dominating bb then
4481 // use StaticAllocaMap.
4482 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4483 if (AI->getParent() != DI.getParent()) {
4484 DenseMap<const AllocaInst*, int>::iterator SI =
4485 FuncInfo.StaticAllocaMap.find(AI);
4486 if (SI != FuncInfo.StaticAllocaMap.end()) {
4487 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4488 0, dl, SDNodeOrder);
4489 DAG.AddDbgValue(SDV, nullptr, false);
4494 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4499 case Intrinsic::dbg_value: {
4500 const DbgValueInst &DI = cast<DbgValueInst>(I);
4501 assert(DI.getVariable() && "Missing variable");
4503 DILocalVariable *Variable = DI.getVariable();
4504 DIExpression *Expression = DI.getExpression();
4505 uint64_t Offset = DI.getOffset();
4506 const Value *V = DI.getValue();
4511 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4512 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4514 DAG.AddDbgValue(SDV, nullptr, false);
4516 // Do not use getValue() in here; we don't want to generate code at
4517 // this point if it hasn't been done yet.
4518 SDValue N = NodeMap[V];
4519 if (!N.getNode() && isa<Argument>(V))
4520 // Check unused arguments map.
4521 N = UnusedArgNodeMap[V];
4523 // A dbg.value for an alloca is always indirect.
4524 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4525 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4527 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4528 IsIndirect, Offset, dl, SDNodeOrder);
4529 DAG.AddDbgValue(SDV, N.getNode(), false);
4531 } else if (!V->use_empty() ) {
4532 // Do not call getValue(V) yet, as we don't want to generate code.
4533 // Remember it for later.
4534 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4535 DanglingDebugInfoMap[V] = DDI;
4537 // We may expand this to cover more cases. One case where we have no
4538 // data available is an unreferenced parameter.
4539 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4543 // Build a debug info table entry.
4544 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4545 V = BCI->getOperand(0);
4546 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4547 // Don't handle byval struct arguments or VLAs, for example.
4549 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4550 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4553 DenseMap<const AllocaInst*, int>::iterator SI =
4554 FuncInfo.StaticAllocaMap.find(AI);
4555 if (SI == FuncInfo.StaticAllocaMap.end())
4556 return nullptr; // VLAs.
4560 case Intrinsic::eh_typeid_for: {
4561 // Find the type id for the given typeinfo.
4562 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4563 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4564 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4569 case Intrinsic::eh_return_i32:
4570 case Intrinsic::eh_return_i64:
4571 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4572 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4575 getValue(I.getArgOperand(0)),
4576 getValue(I.getArgOperand(1))));
4578 case Intrinsic::eh_unwind_init:
4579 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4581 case Intrinsic::eh_dwarf_cfa: {
4582 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4583 TLI.getPointerTy(DAG.getDataLayout()));
4584 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4585 CfaArg.getValueType(),
4586 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4587 CfaArg.getValueType()),
4589 SDValue FA = DAG.getNode(
4590 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4591 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4592 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4596 case Intrinsic::eh_sjlj_callsite: {
4597 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4598 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4599 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4600 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4602 MMI.setCurrentCallSite(CI->getZExtValue());
4605 case Intrinsic::eh_sjlj_functioncontext: {
4606 // Get and store the index of the function context.
4607 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4609 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4610 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4611 MFI->setFunctionContextIndex(FI);
4614 case Intrinsic::eh_sjlj_setjmp: {
4617 Ops[1] = getValue(I.getArgOperand(0));
4618 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4619 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4620 setValue(&I, Op.getValue(0));
4621 DAG.setRoot(Op.getValue(1));
4624 case Intrinsic::eh_sjlj_longjmp: {
4625 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4626 getRoot(), getValue(I.getArgOperand(0))));
4629 case Intrinsic::eh_sjlj_setup_dispatch: {
4630 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4635 case Intrinsic::masked_gather:
4636 visitMaskedGather(I);
4638 case Intrinsic::masked_load:
4641 case Intrinsic::masked_scatter:
4642 visitMaskedScatter(I);
4644 case Intrinsic::masked_store:
4645 visitMaskedStore(I);
4647 case Intrinsic::x86_mmx_pslli_w:
4648 case Intrinsic::x86_mmx_pslli_d:
4649 case Intrinsic::x86_mmx_pslli_q:
4650 case Intrinsic::x86_mmx_psrli_w:
4651 case Intrinsic::x86_mmx_psrli_d:
4652 case Intrinsic::x86_mmx_psrli_q:
4653 case Intrinsic::x86_mmx_psrai_w:
4654 case Intrinsic::x86_mmx_psrai_d: {
4655 SDValue ShAmt = getValue(I.getArgOperand(1));
4656 if (isa<ConstantSDNode>(ShAmt)) {
4657 visitTargetIntrinsic(I, Intrinsic);
4660 unsigned NewIntrinsic = 0;
4661 EVT ShAmtVT = MVT::v2i32;
4662 switch (Intrinsic) {
4663 case Intrinsic::x86_mmx_pslli_w:
4664 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4666 case Intrinsic::x86_mmx_pslli_d:
4667 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4669 case Intrinsic::x86_mmx_pslli_q:
4670 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4672 case Intrinsic::x86_mmx_psrli_w:
4673 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4675 case Intrinsic::x86_mmx_psrli_d:
4676 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4678 case Intrinsic::x86_mmx_psrli_q:
4679 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4681 case Intrinsic::x86_mmx_psrai_w:
4682 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4684 case Intrinsic::x86_mmx_psrai_d:
4685 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4687 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4690 // The vector shift intrinsics with scalars uses 32b shift amounts but
4691 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4693 // We must do this early because v2i32 is not a legal type.
4696 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4697 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4698 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4699 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4700 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4701 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4702 getValue(I.getArgOperand(0)), ShAmt);
4706 case Intrinsic::convertff:
4707 case Intrinsic::convertfsi:
4708 case Intrinsic::convertfui:
4709 case Intrinsic::convertsif:
4710 case Intrinsic::convertuif:
4711 case Intrinsic::convertss:
4712 case Intrinsic::convertsu:
4713 case Intrinsic::convertus:
4714 case Intrinsic::convertuu: {
4715 ISD::CvtCode Code = ISD::CVT_INVALID;
4716 switch (Intrinsic) {
4717 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4718 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4719 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4720 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4721 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4722 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4723 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4724 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4725 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4726 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4728 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4729 const Value *Op1 = I.getArgOperand(0);
4730 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4731 DAG.getValueType(DestVT),
4732 DAG.getValueType(getValue(Op1).getValueType()),
4733 getValue(I.getArgOperand(1)),
4734 getValue(I.getArgOperand(2)),
4739 case Intrinsic::powi:
4740 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4741 getValue(I.getArgOperand(1)), DAG));
4743 case Intrinsic::log:
4744 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4746 case Intrinsic::log2:
4747 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4749 case Intrinsic::log10:
4750 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4752 case Intrinsic::exp:
4753 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4755 case Intrinsic::exp2:
4756 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4758 case Intrinsic::pow:
4759 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4760 getValue(I.getArgOperand(1)), DAG, TLI));
4762 case Intrinsic::sqrt:
4763 case Intrinsic::fabs:
4764 case Intrinsic::sin:
4765 case Intrinsic::cos:
4766 case Intrinsic::floor:
4767 case Intrinsic::ceil:
4768 case Intrinsic::trunc:
4769 case Intrinsic::rint:
4770 case Intrinsic::nearbyint:
4771 case Intrinsic::round: {
4773 switch (Intrinsic) {
4774 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4775 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4776 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4777 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4778 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4779 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4780 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4781 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4782 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4783 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4784 case Intrinsic::round: Opcode = ISD::FROUND; break;
4787 setValue(&I, DAG.getNode(Opcode, sdl,
4788 getValue(I.getArgOperand(0)).getValueType(),
4789 getValue(I.getArgOperand(0))));
4792 case Intrinsic::minnum:
4793 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4794 getValue(I.getArgOperand(0)).getValueType(),
4795 getValue(I.getArgOperand(0)),
4796 getValue(I.getArgOperand(1))));
4798 case Intrinsic::maxnum:
4799 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4800 getValue(I.getArgOperand(0)).getValueType(),
4801 getValue(I.getArgOperand(0)),
4802 getValue(I.getArgOperand(1))));
4804 case Intrinsic::copysign:
4805 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4806 getValue(I.getArgOperand(0)).getValueType(),
4807 getValue(I.getArgOperand(0)),
4808 getValue(I.getArgOperand(1))));
4810 case Intrinsic::fma:
4811 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4812 getValue(I.getArgOperand(0)).getValueType(),
4813 getValue(I.getArgOperand(0)),
4814 getValue(I.getArgOperand(1)),
4815 getValue(I.getArgOperand(2))));
4817 case Intrinsic::fmuladd: {
4818 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4819 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4820 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4821 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4822 getValue(I.getArgOperand(0)).getValueType(),
4823 getValue(I.getArgOperand(0)),
4824 getValue(I.getArgOperand(1)),
4825 getValue(I.getArgOperand(2))));
4827 // TODO: Intrinsic calls should have fast-math-flags.
4828 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4829 getValue(I.getArgOperand(0)).getValueType(),
4830 getValue(I.getArgOperand(0)),
4831 getValue(I.getArgOperand(1)));
4832 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4833 getValue(I.getArgOperand(0)).getValueType(),
4835 getValue(I.getArgOperand(2)));
4840 case Intrinsic::convert_to_fp16:
4841 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4842 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4843 getValue(I.getArgOperand(0)),
4844 DAG.getTargetConstant(0, sdl,
4847 case Intrinsic::convert_from_fp16:
4848 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4849 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4850 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4851 getValue(I.getArgOperand(0)))));
4853 case Intrinsic::pcmarker: {
4854 SDValue Tmp = getValue(I.getArgOperand(0));
4855 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4858 case Intrinsic::readcyclecounter: {
4859 SDValue Op = getRoot();
4860 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4861 DAG.getVTList(MVT::i64, MVT::Other), Op);
4863 DAG.setRoot(Res.getValue(1));
4866 case Intrinsic::bswap:
4867 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4868 getValue(I.getArgOperand(0)).getValueType(),
4869 getValue(I.getArgOperand(0))));
4871 case Intrinsic::uabsdiff:
4872 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4873 getValue(I.getArgOperand(0)).getValueType(),
4874 getValue(I.getArgOperand(0)),
4875 getValue(I.getArgOperand(1))));
4877 case Intrinsic::sabsdiff:
4878 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4879 getValue(I.getArgOperand(0)).getValueType(),
4880 getValue(I.getArgOperand(0)),
4881 getValue(I.getArgOperand(1))));
4883 case Intrinsic::cttz: {
4884 SDValue Arg = getValue(I.getArgOperand(0));
4885 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4886 EVT Ty = Arg.getValueType();
4887 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4891 case Intrinsic::ctlz: {
4892 SDValue Arg = getValue(I.getArgOperand(0));
4893 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4894 EVT Ty = Arg.getValueType();
4895 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4899 case Intrinsic::ctpop: {
4900 SDValue Arg = getValue(I.getArgOperand(0));
4901 EVT Ty = Arg.getValueType();
4902 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4905 case Intrinsic::stacksave: {
4906 SDValue Op = getRoot();
4908 ISD::STACKSAVE, sdl,
4909 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4911 DAG.setRoot(Res.getValue(1));
4914 case Intrinsic::stackrestore: {
4915 Res = getValue(I.getArgOperand(0));
4916 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4919 case Intrinsic::stackprotector: {
4920 // Emit code into the DAG to store the stack guard onto the stack.
4921 MachineFunction &MF = DAG.getMachineFunction();
4922 MachineFrameInfo *MFI = MF.getFrameInfo();
4923 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4924 SDValue Src, Chain = getRoot();
4925 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4926 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4928 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4929 // global variable __stack_chk_guard.
4931 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4932 if (BC->getOpcode() == Instruction::BitCast)
4933 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4935 if (GV && TLI.useLoadStackGuardNode()) {
4936 // Emit a LOAD_STACK_GUARD node.
4937 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4939 MachinePointerInfo MPInfo(GV);
4940 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4941 unsigned Flags = MachineMemOperand::MOLoad |
4942 MachineMemOperand::MOInvariant;
4943 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4944 PtrTy.getSizeInBits() / 8,
4945 DAG.getEVTAlignment(PtrTy));
4946 Node->setMemRefs(MemRefs, MemRefs + 1);
4948 // Copy the guard value to a virtual register so that it can be
4949 // retrieved in the epilogue.
4950 Src = SDValue(Node, 0);
4951 const TargetRegisterClass *RC =
4952 TLI.getRegClassFor(Src.getSimpleValueType());
4953 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4955 SPDescriptor.setGuardReg(Reg);
4956 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4958 Src = getValue(I.getArgOperand(0)); // The guard's value.
4961 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4963 int FI = FuncInfo.StaticAllocaMap[Slot];
4964 MFI->setStackProtectorIndex(FI);
4966 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4968 // Store the stack protector onto the stack.
4969 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4970 DAG.getMachineFunction(), FI),
4976 case Intrinsic::objectsize: {
4977 // If we don't know by now, we're never going to know.
4978 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4980 assert(CI && "Non-constant type in __builtin_object_size?");
4982 SDValue Arg = getValue(I.getCalledValue());
4983 EVT Ty = Arg.getValueType();
4986 Res = DAG.getConstant(-1ULL, sdl, Ty);
4988 Res = DAG.getConstant(0, sdl, Ty);
4993 case Intrinsic::annotation:
4994 case Intrinsic::ptr_annotation:
4995 // Drop the intrinsic, but forward the value
4996 setValue(&I, getValue(I.getOperand(0)));
4998 case Intrinsic::assume:
4999 case Intrinsic::var_annotation:
5000 // Discard annotate attributes and assumptions
5003 case Intrinsic::init_trampoline: {
5004 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5008 Ops[1] = getValue(I.getArgOperand(0));
5009 Ops[2] = getValue(I.getArgOperand(1));
5010 Ops[3] = getValue(I.getArgOperand(2));
5011 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5012 Ops[5] = DAG.getSrcValue(F);
5014 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5019 case Intrinsic::adjust_trampoline: {
5020 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5021 TLI.getPointerTy(DAG.getDataLayout()),
5022 getValue(I.getArgOperand(0))));
5025 case Intrinsic::gcroot:
5027 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5028 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5030 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5031 GFI->addStackRoot(FI->getIndex(), TypeMap);
5034 case Intrinsic::gcread:
5035 case Intrinsic::gcwrite:
5036 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5037 case Intrinsic::flt_rounds:
5038 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5041 case Intrinsic::expect: {
5042 // Just replace __builtin_expect(exp, c) with EXP.
5043 setValue(&I, getValue(I.getArgOperand(0)));
5047 case Intrinsic::debugtrap:
5048 case Intrinsic::trap: {
5049 StringRef TrapFuncName =
5051 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5052 .getValueAsString();
5053 if (TrapFuncName.empty()) {
5054 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5055 ISD::TRAP : ISD::DEBUGTRAP;
5056 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5059 TargetLowering::ArgListTy Args;
5061 TargetLowering::CallLoweringInfo CLI(DAG);
5062 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5063 CallingConv::C, I.getType(),
5064 DAG.getExternalSymbol(TrapFuncName.data(),
5065 TLI.getPointerTy(DAG.getDataLayout())),
5066 std::move(Args), 0);
5068 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5069 DAG.setRoot(Result.second);
5073 case Intrinsic::uadd_with_overflow:
5074 case Intrinsic::sadd_with_overflow:
5075 case Intrinsic::usub_with_overflow:
5076 case Intrinsic::ssub_with_overflow:
5077 case Intrinsic::umul_with_overflow:
5078 case Intrinsic::smul_with_overflow: {
5080 switch (Intrinsic) {
5081 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5082 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5083 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5084 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5085 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5086 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5087 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5089 SDValue Op1 = getValue(I.getArgOperand(0));
5090 SDValue Op2 = getValue(I.getArgOperand(1));
5092 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5093 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5096 case Intrinsic::prefetch: {
5098 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5100 Ops[1] = getValue(I.getArgOperand(0));
5101 Ops[2] = getValue(I.getArgOperand(1));
5102 Ops[3] = getValue(I.getArgOperand(2));
5103 Ops[4] = getValue(I.getArgOperand(3));
5104 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5105 DAG.getVTList(MVT::Other), Ops,
5106 EVT::getIntegerVT(*Context, 8),
5107 MachinePointerInfo(I.getArgOperand(0)),
5109 false, /* volatile */
5111 rw==1)); /* write */
5114 case Intrinsic::lifetime_start:
5115 case Intrinsic::lifetime_end: {
5116 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5117 // Stack coloring is not enabled in O0, discard region information.
5118 if (TM.getOptLevel() == CodeGenOpt::None)
5121 SmallVector<Value *, 4> Allocas;
5122 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5124 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5125 E = Allocas.end(); Object != E; ++Object) {
5126 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5128 // Could not find an Alloca.
5129 if (!LifetimeObject)
5132 // First check that the Alloca is static, otherwise it won't have a
5133 // valid frame index.
5134 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5135 if (SI == FuncInfo.StaticAllocaMap.end())
5138 int FI = SI->second;
5143 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5144 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5146 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5151 case Intrinsic::invariant_start:
5152 // Discard region information.
5153 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5155 case Intrinsic::invariant_end:
5156 // Discard region information.
5158 case Intrinsic::stackprotectorcheck: {
5159 // Do not actually emit anything for this basic block. Instead we initialize
5160 // the stack protector descriptor and export the guard variable so we can
5161 // access it in FinishBasicBlock.
5162 const BasicBlock *BB = I.getParent();
5163 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5164 ExportFromCurrentBlock(SPDescriptor.getGuard());
5166 // Flush our exports since we are going to process a terminator.
5167 (void)getControlRoot();
5170 case Intrinsic::clear_cache:
5171 return TLI.getClearCacheBuiltinName();
5172 case Intrinsic::donothing:
5175 case Intrinsic::experimental_stackmap: {
5179 case Intrinsic::experimental_patchpoint_void:
5180 case Intrinsic::experimental_patchpoint_i64: {
5181 visitPatchpoint(&I);
5184 case Intrinsic::experimental_gc_statepoint: {
5188 case Intrinsic::experimental_gc_result_int:
5189 case Intrinsic::experimental_gc_result_float:
5190 case Intrinsic::experimental_gc_result_ptr:
5191 case Intrinsic::experimental_gc_result: {
5195 case Intrinsic::experimental_gc_relocate: {
5199 case Intrinsic::instrprof_increment:
5200 llvm_unreachable("instrprof failed to lower an increment");
5202 case Intrinsic::localescape: {
5203 MachineFunction &MF = DAG.getMachineFunction();
5204 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5206 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5207 // is the same on all targets.
5208 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5209 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5210 if (isa<ConstantPointerNull>(Arg))
5211 continue; // Skip null pointers. They represent a hole in index space.
5212 AllocaInst *Slot = cast<AllocaInst>(Arg);
5213 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5214 "can only escape static allocas");
5215 int FI = FuncInfo.StaticAllocaMap[Slot];
5216 MCSymbol *FrameAllocSym =
5217 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5218 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5220 TII->get(TargetOpcode::LOCAL_ESCAPE))
5221 .addSym(FrameAllocSym)
5228 case Intrinsic::localrecover: {
5229 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5230 MachineFunction &MF = DAG.getMachineFunction();
5231 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5233 // Get the symbol that defines the frame offset.
5234 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5235 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5236 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5237 MCSymbol *FrameAllocSym =
5238 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5239 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5241 // Create a MCSymbol for the label to avoid any target lowering
5242 // that would make this PC relative.
5243 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5245 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5247 // Add the offset to the FP.
5248 Value *FP = I.getArgOperand(1);
5249 SDValue FPVal = getValue(FP);
5250 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5256 case Intrinsic::eh_exceptionpointer:
5257 case Intrinsic::eh_exceptioncode: {
5258 // Get the exception pointer vreg, copy from it, and resize it to fit.
5259 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5260 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5261 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5262 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5264 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5265 if (Intrinsic == Intrinsic::eh_exceptioncode)
5266 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5273 std::pair<SDValue, SDValue>
5274 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5275 const BasicBlock *EHPadBB) {
5276 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5277 MCSymbol *BeginLabel = nullptr;
5280 // Insert a label before the invoke call to mark the try range. This can be
5281 // used to detect deletion of the invoke via the MachineModuleInfo.
5282 BeginLabel = MMI.getContext().createTempSymbol();
5284 // For SjLj, keep track of which landing pads go with which invokes
5285 // so as to maintain the ordering of pads in the LSDA.
5286 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5287 if (CallSiteIndex) {
5288 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5289 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5291 // Now that the call site is handled, stop tracking it.
5292 MMI.setCurrentCallSite(0);
5295 // Both PendingLoads and PendingExports must be flushed here;
5296 // this call might not return.
5298 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5300 CLI.setChain(getRoot());
5302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5303 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5305 assert((CLI.IsTailCall || Result.second.getNode()) &&
5306 "Non-null chain expected with non-tail call!");
5307 assert((Result.second.getNode() || !Result.first.getNode()) &&
5308 "Null value expected with tail call!");
5310 if (!Result.second.getNode()) {
5311 // As a special case, a null chain means that a tail call has been emitted
5312 // and the DAG root is already updated.
5315 // Since there's no actual continuation from this block, nothing can be
5316 // relying on us setting vregs for them.
5317 PendingExports.clear();
5319 DAG.setRoot(Result.second);
5323 // Insert a label at the end of the invoke call to mark the try range. This
5324 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5325 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5326 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5328 // Inform MachineModuleInfo of range.
5329 if (MMI.hasEHFunclets()) {
5330 WinEHFuncInfo &EHInfo =
5331 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5332 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5334 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5341 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5343 const BasicBlock *EHPadBB) {
5344 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5345 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5346 Type *RetTy = FTy->getReturnType();
5348 TargetLowering::ArgListTy Args;
5349 TargetLowering::ArgListEntry Entry;
5350 Args.reserve(CS.arg_size());
5352 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5354 const Value *V = *i;
5357 if (V->getType()->isEmptyTy())
5360 SDValue ArgNode = getValue(V);
5361 Entry.Node = ArgNode; Entry.Ty = V->getType();
5363 // Skip the first return-type Attribute to get to params.
5364 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5365 Args.push_back(Entry);
5367 // If we have an explicit sret argument that is an Instruction, (i.e., it
5368 // might point to function-local memory), we can't meaningfully tail-call.
5369 if (Entry.isSRet && isa<Instruction>(V))
5373 // Check if target-independent constraints permit a tail call here.
5374 // Target-dependent constraints are checked within TLI->LowerCallTo.
5375 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5378 TargetLowering::CallLoweringInfo CLI(DAG);
5379 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5380 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5381 .setTailCall(isTailCall);
5382 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5384 if (Result.first.getNode())
5385 setValue(CS.getInstruction(), Result.first);
5388 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5389 /// value is equal or not-equal to zero.
5390 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5391 for (const User *U : V->users()) {
5392 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5393 if (IC->isEquality())
5394 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5395 if (C->isNullValue())
5397 // Unknown instruction.
5403 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5405 SelectionDAGBuilder &Builder) {
5407 // Check to see if this load can be trivially constant folded, e.g. if the
5408 // input is from a string literal.
5409 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5410 // Cast pointer to the type we really want to load.
5411 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5412 PointerType::getUnqual(LoadTy));
5414 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5415 const_cast<Constant *>(LoadInput), *Builder.DL))
5416 return Builder.getValue(LoadCst);
5419 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5420 // still constant memory, the input chain can be the entry node.
5422 bool ConstantMemory = false;
5424 // Do not serialize (non-volatile) loads of constant memory with anything.
5425 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5426 Root = Builder.DAG.getEntryNode();
5427 ConstantMemory = true;
5429 // Do not serialize non-volatile loads against each other.
5430 Root = Builder.DAG.getRoot();
5433 SDValue Ptr = Builder.getValue(PtrVal);
5434 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5435 Ptr, MachinePointerInfo(PtrVal),
5437 false /*nontemporal*/,
5438 false /*isinvariant*/, 1 /* align=1 */);
5440 if (!ConstantMemory)
5441 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5445 /// processIntegerCallValue - Record the value for an instruction that
5446 /// produces an integer result, converting the type where necessary.
5447 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5450 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5453 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5455 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5456 setValue(&I, Value);
5459 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5460 /// If so, return true and lower it, otherwise return false and it will be
5461 /// lowered like a normal call.
5462 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5463 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5464 if (I.getNumArgOperands() != 3)
5467 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5468 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5469 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5470 !I.getType()->isIntegerTy())
5473 const Value *Size = I.getArgOperand(2);
5474 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5475 if (CSize && CSize->getZExtValue() == 0) {
5476 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5478 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5482 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5483 std::pair<SDValue, SDValue> Res =
5484 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5485 getValue(LHS), getValue(RHS), getValue(Size),
5486 MachinePointerInfo(LHS),
5487 MachinePointerInfo(RHS));
5488 if (Res.first.getNode()) {
5489 processIntegerCallValue(I, Res.first, true);
5490 PendingLoads.push_back(Res.second);
5494 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5495 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5496 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5497 bool ActuallyDoIt = true;
5500 switch (CSize->getZExtValue()) {
5502 LoadVT = MVT::Other;
5504 ActuallyDoIt = false;
5508 LoadTy = Type::getInt16Ty(CSize->getContext());
5512 LoadTy = Type::getInt32Ty(CSize->getContext());
5516 LoadTy = Type::getInt64Ty(CSize->getContext());
5520 LoadVT = MVT::v4i32;
5521 LoadTy = Type::getInt32Ty(CSize->getContext());
5522 LoadTy = VectorType::get(LoadTy, 4);
5527 // This turns into unaligned loads. We only do this if the target natively
5528 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5529 // we'll only produce a small number of byte loads.
5531 // Require that we can find a legal MVT, and only do this if the target
5532 // supports unaligned loads of that type. Expanding into byte loads would
5534 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5535 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5536 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5537 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5538 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5539 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5540 // TODO: Check alignment of src and dest ptrs.
5541 if (!TLI.isTypeLegal(LoadVT) ||
5542 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5543 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5544 ActuallyDoIt = false;
5548 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5549 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5551 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5553 processIntegerCallValue(I, Res, false);
5562 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5563 /// form. If so, return true and lower it, otherwise return false and it
5564 /// will be lowered like a normal call.
5565 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5566 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5567 if (I.getNumArgOperands() != 3)
5570 const Value *Src = I.getArgOperand(0);
5571 const Value *Char = I.getArgOperand(1);
5572 const Value *Length = I.getArgOperand(2);
5573 if (!Src->getType()->isPointerTy() ||
5574 !Char->getType()->isIntegerTy() ||
5575 !Length->getType()->isIntegerTy() ||
5576 !I.getType()->isPointerTy())
5579 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5580 std::pair<SDValue, SDValue> Res =
5581 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5582 getValue(Src), getValue(Char), getValue(Length),
5583 MachinePointerInfo(Src));
5584 if (Res.first.getNode()) {
5585 setValue(&I, Res.first);
5586 PendingLoads.push_back(Res.second);
5593 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5594 /// optimized form. If so, return true and lower it, otherwise return false
5595 /// and it will be lowered like a normal call.
5596 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5597 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5598 if (I.getNumArgOperands() != 2)
5601 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5602 if (!Arg0->getType()->isPointerTy() ||
5603 !Arg1->getType()->isPointerTy() ||
5604 !I.getType()->isPointerTy())
5607 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5608 std::pair<SDValue, SDValue> Res =
5609 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5610 getValue(Arg0), getValue(Arg1),
5611 MachinePointerInfo(Arg0),
5612 MachinePointerInfo(Arg1), isStpcpy);
5613 if (Res.first.getNode()) {
5614 setValue(&I, Res.first);
5615 DAG.setRoot(Res.second);
5622 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5623 /// If so, return true and lower it, otherwise return false and it will be
5624 /// lowered like a normal call.
5625 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5626 // Verify that the prototype makes sense. int strcmp(void*,void*)
5627 if (I.getNumArgOperands() != 2)
5630 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5631 if (!Arg0->getType()->isPointerTy() ||
5632 !Arg1->getType()->isPointerTy() ||
5633 !I.getType()->isIntegerTy())
5636 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5637 std::pair<SDValue, SDValue> Res =
5638 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5639 getValue(Arg0), getValue(Arg1),
5640 MachinePointerInfo(Arg0),
5641 MachinePointerInfo(Arg1));
5642 if (Res.first.getNode()) {
5643 processIntegerCallValue(I, Res.first, true);
5644 PendingLoads.push_back(Res.second);
5651 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5652 /// form. If so, return true and lower it, otherwise return false and it
5653 /// will be lowered like a normal call.
5654 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5655 // Verify that the prototype makes sense. size_t strlen(char *)
5656 if (I.getNumArgOperands() != 1)
5659 const Value *Arg0 = I.getArgOperand(0);
5660 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5663 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5664 std::pair<SDValue, SDValue> Res =
5665 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5666 getValue(Arg0), MachinePointerInfo(Arg0));
5667 if (Res.first.getNode()) {
5668 processIntegerCallValue(I, Res.first, false);
5669 PendingLoads.push_back(Res.second);
5676 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5677 /// form. If so, return true and lower it, otherwise return false and it
5678 /// will be lowered like a normal call.
5679 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5680 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5681 if (I.getNumArgOperands() != 2)
5684 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5685 if (!Arg0->getType()->isPointerTy() ||
5686 !Arg1->getType()->isIntegerTy() ||
5687 !I.getType()->isIntegerTy())
5690 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5691 std::pair<SDValue, SDValue> Res =
5692 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5693 getValue(Arg0), getValue(Arg1),
5694 MachinePointerInfo(Arg0));
5695 if (Res.first.getNode()) {
5696 processIntegerCallValue(I, Res.first, false);
5697 PendingLoads.push_back(Res.second);
5704 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5705 /// operation (as expected), translate it to an SDNode with the specified opcode
5706 /// and return true.
5707 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5709 // Sanity check that it really is a unary floating-point call.
5710 if (I.getNumArgOperands() != 1 ||
5711 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5712 I.getType() != I.getArgOperand(0)->getType() ||
5713 !I.onlyReadsMemory())
5716 SDValue Tmp = getValue(I.getArgOperand(0));
5717 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5721 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5722 /// operation (as expected), translate it to an SDNode with the specified opcode
5723 /// and return true.
5724 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5726 // Sanity check that it really is a binary floating-point call.
5727 if (I.getNumArgOperands() != 2 ||
5728 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5729 I.getType() != I.getArgOperand(0)->getType() ||
5730 I.getType() != I.getArgOperand(1)->getType() ||
5731 !I.onlyReadsMemory())
5734 SDValue Tmp0 = getValue(I.getArgOperand(0));
5735 SDValue Tmp1 = getValue(I.getArgOperand(1));
5736 EVT VT = Tmp0.getValueType();
5737 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5741 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5742 // Handle inline assembly differently.
5743 if (isa<InlineAsm>(I.getCalledValue())) {
5748 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5749 ComputeUsesVAFloatArgument(I, &MMI);
5751 const char *RenameFn = nullptr;
5752 if (Function *F = I.getCalledFunction()) {
5753 if (F->isDeclaration()) {
5754 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5755 if (unsigned IID = II->getIntrinsicID(F)) {
5756 RenameFn = visitIntrinsicCall(I, IID);
5761 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5762 RenameFn = visitIntrinsicCall(I, IID);
5768 // Check for well-known libc/libm calls. If the function is internal, it
5769 // can't be a library call.
5771 if (!F->hasLocalLinkage() && F->hasName() &&
5772 LibInfo->getLibFunc(F->getName(), Func) &&
5773 LibInfo->hasOptimizedCodeGen(Func)) {
5776 case LibFunc::copysign:
5777 case LibFunc::copysignf:
5778 case LibFunc::copysignl:
5779 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5780 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5781 I.getType() == I.getArgOperand(0)->getType() &&
5782 I.getType() == I.getArgOperand(1)->getType() &&
5783 I.onlyReadsMemory()) {
5784 SDValue LHS = getValue(I.getArgOperand(0));
5785 SDValue RHS = getValue(I.getArgOperand(1));
5786 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5787 LHS.getValueType(), LHS, RHS));
5792 case LibFunc::fabsf:
5793 case LibFunc::fabsl:
5794 if (visitUnaryFloatCall(I, ISD::FABS))
5798 case LibFunc::fminf:
5799 case LibFunc::fminl:
5800 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5804 case LibFunc::fmaxf:
5805 case LibFunc::fmaxl:
5806 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5812 if (visitUnaryFloatCall(I, ISD::FSIN))
5818 if (visitUnaryFloatCall(I, ISD::FCOS))
5822 case LibFunc::sqrtf:
5823 case LibFunc::sqrtl:
5824 case LibFunc::sqrt_finite:
5825 case LibFunc::sqrtf_finite:
5826 case LibFunc::sqrtl_finite:
5827 if (visitUnaryFloatCall(I, ISD::FSQRT))
5830 case LibFunc::floor:
5831 case LibFunc::floorf:
5832 case LibFunc::floorl:
5833 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5836 case LibFunc::nearbyint:
5837 case LibFunc::nearbyintf:
5838 case LibFunc::nearbyintl:
5839 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5843 case LibFunc::ceilf:
5844 case LibFunc::ceill:
5845 if (visitUnaryFloatCall(I, ISD::FCEIL))
5849 case LibFunc::rintf:
5850 case LibFunc::rintl:
5851 if (visitUnaryFloatCall(I, ISD::FRINT))
5854 case LibFunc::round:
5855 case LibFunc::roundf:
5856 case LibFunc::roundl:
5857 if (visitUnaryFloatCall(I, ISD::FROUND))
5860 case LibFunc::trunc:
5861 case LibFunc::truncf:
5862 case LibFunc::truncl:
5863 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5867 case LibFunc::log2f:
5868 case LibFunc::log2l:
5869 if (visitUnaryFloatCall(I, ISD::FLOG2))
5873 case LibFunc::exp2f:
5874 case LibFunc::exp2l:
5875 if (visitUnaryFloatCall(I, ISD::FEXP2))
5878 case LibFunc::memcmp:
5879 if (visitMemCmpCall(I))
5882 case LibFunc::memchr:
5883 if (visitMemChrCall(I))
5886 case LibFunc::strcpy:
5887 if (visitStrCpyCall(I, false))
5890 case LibFunc::stpcpy:
5891 if (visitStrCpyCall(I, true))
5894 case LibFunc::strcmp:
5895 if (visitStrCmpCall(I))
5898 case LibFunc::strlen:
5899 if (visitStrLenCall(I))
5902 case LibFunc::strnlen:
5903 if (visitStrNLenCall(I))
5912 Callee = getValue(I.getCalledValue());
5914 Callee = DAG.getExternalSymbol(
5916 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5918 // Check if we can potentially perform a tail call. More detailed checking is
5919 // be done within LowerCallTo, after more information about the call is known.
5920 LowerCallTo(&I, Callee, I.isTailCall());
5925 /// AsmOperandInfo - This contains information for each constraint that we are
5927 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5929 /// CallOperand - If this is the result output operand or a clobber
5930 /// this is null, otherwise it is the incoming operand to the CallInst.
5931 /// This gets modified as the asm is processed.
5932 SDValue CallOperand;
5934 /// AssignedRegs - If this is a register or register class operand, this
5935 /// contains the set of register corresponding to the operand.
5936 RegsForValue AssignedRegs;
5938 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5939 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5942 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5943 /// corresponds to. If there is no Value* for this operand, it returns
5945 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5946 const DataLayout &DL) const {
5947 if (!CallOperandVal) return MVT::Other;
5949 if (isa<BasicBlock>(CallOperandVal))
5950 return TLI.getPointerTy(DL);
5952 llvm::Type *OpTy = CallOperandVal->getType();
5954 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5955 // If this is an indirect operand, the operand is a pointer to the
5958 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5960 report_fatal_error("Indirect operand for inline asm not a pointer!");
5961 OpTy = PtrTy->getElementType();
5964 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5965 if (StructType *STy = dyn_cast<StructType>(OpTy))
5966 if (STy->getNumElements() == 1)
5967 OpTy = STy->getElementType(0);
5969 // If OpTy is not a single value, it may be a struct/union that we
5970 // can tile with integers.
5971 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5972 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5981 OpTy = IntegerType::get(Context, BitSize);
5986 return TLI.getValueType(DL, OpTy, true);
5990 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5992 } // end anonymous namespace
5994 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5995 /// specified operand. We prefer to assign virtual registers, to allow the
5996 /// register allocator to handle the assignment process. However, if the asm
5997 /// uses features that we can't model on machineinstrs, we have SDISel do the
5998 /// allocation. This produces generally horrible, but correct, code.
6000 /// OpInfo describes the operand.
6002 static void GetRegistersForValue(SelectionDAG &DAG,
6003 const TargetLowering &TLI,
6005 SDISelAsmOperandInfo &OpInfo) {
6006 LLVMContext &Context = *DAG.getContext();
6008 MachineFunction &MF = DAG.getMachineFunction();
6009 SmallVector<unsigned, 4> Regs;
6011 // If this is a constraint for a single physreg, or a constraint for a
6012 // register class, find it.
6013 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6014 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6015 OpInfo.ConstraintCode,
6016 OpInfo.ConstraintVT);
6018 unsigned NumRegs = 1;
6019 if (OpInfo.ConstraintVT != MVT::Other) {
6020 // If this is a FP input in an integer register (or visa versa) insert a bit
6021 // cast of the input value. More generally, handle any case where the input
6022 // value disagrees with the register class we plan to stick this in.
6023 if (OpInfo.Type == InlineAsm::isInput &&
6024 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6025 // Try to convert to the first EVT that the reg class contains. If the
6026 // types are identical size, use a bitcast to convert (e.g. two differing
6028 MVT RegVT = *PhysReg.second->vt_begin();
6029 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6030 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6031 RegVT, OpInfo.CallOperand);
6032 OpInfo.ConstraintVT = RegVT;
6033 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6034 // If the input is a FP value and we want it in FP registers, do a
6035 // bitcast to the corresponding integer type. This turns an f64 value
6036 // into i64, which can be passed with two i32 values on a 32-bit
6038 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6039 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6040 RegVT, OpInfo.CallOperand);
6041 OpInfo.ConstraintVT = RegVT;
6045 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6049 EVT ValueVT = OpInfo.ConstraintVT;
6051 // If this is a constraint for a specific physical register, like {r17},
6053 if (unsigned AssignedReg = PhysReg.first) {
6054 const TargetRegisterClass *RC = PhysReg.second;
6055 if (OpInfo.ConstraintVT == MVT::Other)
6056 ValueVT = *RC->vt_begin();
6058 // Get the actual register value type. This is important, because the user
6059 // may have asked for (e.g.) the AX register in i32 type. We need to
6060 // remember that AX is actually i16 to get the right extension.
6061 RegVT = *RC->vt_begin();
6063 // This is a explicit reference to a physical register.
6064 Regs.push_back(AssignedReg);
6066 // If this is an expanded reference, add the rest of the regs to Regs.
6068 TargetRegisterClass::iterator I = RC->begin();
6069 for (; *I != AssignedReg; ++I)
6070 assert(I != RC->end() && "Didn't find reg!");
6072 // Already added the first reg.
6074 for (; NumRegs; --NumRegs, ++I) {
6075 assert(I != RC->end() && "Ran out of registers to allocate!");
6080 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6084 // Otherwise, if this was a reference to an LLVM register class, create vregs
6085 // for this reference.
6086 if (const TargetRegisterClass *RC = PhysReg.second) {
6087 RegVT = *RC->vt_begin();
6088 if (OpInfo.ConstraintVT == MVT::Other)
6091 // Create the appropriate number of virtual registers.
6092 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6093 for (; NumRegs; --NumRegs)
6094 Regs.push_back(RegInfo.createVirtualRegister(RC));
6096 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6100 // Otherwise, we couldn't allocate enough registers for this.
6103 /// visitInlineAsm - Handle a call to an InlineAsm object.
6105 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6106 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6108 /// ConstraintOperands - Information about all of the constraints.
6109 SDISelAsmOperandInfoVector ConstraintOperands;
6111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6112 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6113 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6115 bool hasMemory = false;
6117 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6118 unsigned ResNo = 0; // ResNo - The result number of the next output.
6119 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6120 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6121 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6123 MVT OpVT = MVT::Other;
6125 // Compute the value type for each operand.
6126 switch (OpInfo.Type) {
6127 case InlineAsm::isOutput:
6128 // Indirect outputs just consume an argument.
6129 if (OpInfo.isIndirect) {
6130 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6134 // The return value of the call is this value. As such, there is no
6135 // corresponding argument.
6136 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6137 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6138 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6139 STy->getElementType(ResNo));
6141 assert(ResNo == 0 && "Asm only has one result!");
6142 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6146 case InlineAsm::isInput:
6147 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6149 case InlineAsm::isClobber:
6154 // If this is an input or an indirect output, process the call argument.
6155 // BasicBlocks are labels, currently appearing only in asm's.
6156 if (OpInfo.CallOperandVal) {
6157 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6158 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6160 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6163 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6164 DAG.getDataLayout()).getSimpleVT();
6167 OpInfo.ConstraintVT = OpVT;
6169 // Indirect operand accesses access memory.
6170 if (OpInfo.isIndirect)
6173 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6174 TargetLowering::ConstraintType
6175 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6176 if (CType == TargetLowering::C_Memory) {
6184 SDValue Chain, Flag;
6186 // We won't need to flush pending loads if this asm doesn't touch
6187 // memory and is nonvolatile.
6188 if (hasMemory || IA->hasSideEffects())
6191 Chain = DAG.getRoot();
6193 // Second pass over the constraints: compute which constraint option to use
6194 // and assign registers to constraints that want a specific physreg.
6195 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6196 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6198 // If this is an output operand with a matching input operand, look up the
6199 // matching input. If their types mismatch, e.g. one is an integer, the
6200 // other is floating point, or their sizes are different, flag it as an
6202 if (OpInfo.hasMatchingInput()) {
6203 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6205 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6206 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6207 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6208 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6209 OpInfo.ConstraintVT);
6210 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6211 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6212 Input.ConstraintVT);
6213 if ((OpInfo.ConstraintVT.isInteger() !=
6214 Input.ConstraintVT.isInteger()) ||
6215 (MatchRC.second != InputRC.second)) {
6216 report_fatal_error("Unsupported asm: input constraint"
6217 " with a matching output constraint of"
6218 " incompatible type!");
6220 Input.ConstraintVT = OpInfo.ConstraintVT;
6224 // Compute the constraint code and ConstraintType to use.
6225 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6227 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6228 OpInfo.Type == InlineAsm::isClobber)
6231 // If this is a memory input, and if the operand is not indirect, do what we
6232 // need to to provide an address for the memory input.
6233 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6234 !OpInfo.isIndirect) {
6235 assert((OpInfo.isMultipleAlternative ||
6236 (OpInfo.Type == InlineAsm::isInput)) &&
6237 "Can only indirectify direct input operands!");
6239 // Memory operands really want the address of the value. If we don't have
6240 // an indirect input, put it in the constpool if we can, otherwise spill
6241 // it to a stack slot.
6242 // TODO: This isn't quite right. We need to handle these according to
6243 // the addressing mode that the constraint wants. Also, this may take
6244 // an additional register for the computation and we don't want that
6247 // If the operand is a float, integer, or vector constant, spill to a
6248 // constant pool entry to get its address.
6249 const Value *OpVal = OpInfo.CallOperandVal;
6250 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6251 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6252 OpInfo.CallOperand = DAG.getConstantPool(
6253 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6255 // Otherwise, create a stack slot and emit a store to it before the
6257 Type *Ty = OpVal->getType();
6258 auto &DL = DAG.getDataLayout();
6259 uint64_t TySize = DL.getTypeAllocSize(Ty);
6260 unsigned Align = DL.getPrefTypeAlignment(Ty);
6261 MachineFunction &MF = DAG.getMachineFunction();
6262 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6264 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6265 Chain = DAG.getStore(
6266 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6267 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6269 OpInfo.CallOperand = StackSlot;
6272 // There is no longer a Value* corresponding to this operand.
6273 OpInfo.CallOperandVal = nullptr;
6275 // It is now an indirect operand.
6276 OpInfo.isIndirect = true;
6279 // If this constraint is for a specific register, allocate it before
6281 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6282 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6285 // Second pass - Loop over all of the operands, assigning virtual or physregs
6286 // to register class operands.
6287 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6288 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6290 // C_Register operands have already been allocated, Other/Memory don't need
6292 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6293 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6296 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6297 std::vector<SDValue> AsmNodeOperands;
6298 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6299 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6300 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6302 // If we have a !srcloc metadata node associated with it, we want to attach
6303 // this to the ultimately generated inline asm machineinstr. To do this, we
6304 // pass in the third operand as this (potentially null) inline asm MDNode.
6305 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6306 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6308 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6309 // bits as operand 3.
6310 unsigned ExtraInfo = 0;
6311 if (IA->hasSideEffects())
6312 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6313 if (IA->isAlignStack())
6314 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6315 // Set the asm dialect.
6316 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6318 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6319 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6320 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6322 // Compute the constraint code and ConstraintType to use.
6323 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6325 // Ideally, we would only check against memory constraints. However, the
6326 // meaning of an other constraint can be target-specific and we can't easily
6327 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6328 // for other constriants as well.
6329 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6330 OpInfo.ConstraintType == TargetLowering::C_Other) {
6331 if (OpInfo.Type == InlineAsm::isInput)
6332 ExtraInfo |= InlineAsm::Extra_MayLoad;
6333 else if (OpInfo.Type == InlineAsm::isOutput)
6334 ExtraInfo |= InlineAsm::Extra_MayStore;
6335 else if (OpInfo.Type == InlineAsm::isClobber)
6336 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6340 AsmNodeOperands.push_back(DAG.getTargetConstant(
6341 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6343 // Loop over all of the inputs, copying the operand values into the
6344 // appropriate registers and processing the output regs.
6345 RegsForValue RetValRegs;
6347 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6348 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6350 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6351 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6353 switch (OpInfo.Type) {
6354 case InlineAsm::isOutput: {
6355 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6356 OpInfo.ConstraintType != TargetLowering::C_Register) {
6357 // Memory output, or 'other' output (e.g. 'X' constraint).
6358 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6360 unsigned ConstraintID =
6361 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6362 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6363 "Failed to convert memory constraint code to constraint id.");
6365 // Add information to the INLINEASM node to know about this output.
6366 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6367 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6368 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6370 AsmNodeOperands.push_back(OpInfo.CallOperand);
6374 // Otherwise, this is a register or register class output.
6376 // Copy the output from the appropriate register. Find a register that
6378 if (OpInfo.AssignedRegs.Regs.empty()) {
6379 LLVMContext &Ctx = *DAG.getContext();
6380 Ctx.emitError(CS.getInstruction(),
6381 "couldn't allocate output register for constraint '" +
6382 Twine(OpInfo.ConstraintCode) + "'");
6386 // If this is an indirect operand, store through the pointer after the
6388 if (OpInfo.isIndirect) {
6389 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6390 OpInfo.CallOperandVal));
6392 // This is the result value of the call.
6393 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6394 // Concatenate this output onto the outputs list.
6395 RetValRegs.append(OpInfo.AssignedRegs);
6398 // Add information to the INLINEASM node to know that this register is
6401 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6402 ? InlineAsm::Kind_RegDefEarlyClobber
6403 : InlineAsm::Kind_RegDef,
6404 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6407 case InlineAsm::isInput: {
6408 SDValue InOperandVal = OpInfo.CallOperand;
6410 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6411 // If this is required to match an output register we have already set,
6412 // just use its register.
6413 unsigned OperandNo = OpInfo.getMatchedOperand();
6415 // Scan until we find the definition we already emitted of this operand.
6416 // When we find it, create a RegsForValue operand.
6417 unsigned CurOp = InlineAsm::Op_FirstOperand;
6418 for (; OperandNo; --OperandNo) {
6419 // Advance to the next operand.
6421 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6422 assert((InlineAsm::isRegDefKind(OpFlag) ||
6423 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6424 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6425 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6429 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6430 if (InlineAsm::isRegDefKind(OpFlag) ||
6431 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6432 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6433 if (OpInfo.isIndirect) {
6434 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6435 LLVMContext &Ctx = *DAG.getContext();
6436 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6437 " don't know how to handle tied "
6438 "indirect register inputs");
6442 RegsForValue MatchedRegs;
6443 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6444 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6445 MatchedRegs.RegVTs.push_back(RegVT);
6446 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6447 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6449 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6450 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6452 LLVMContext &Ctx = *DAG.getContext();
6453 Ctx.emitError(CS.getInstruction(),
6454 "inline asm error: This value"
6455 " type register class is not natively supported!");
6459 SDLoc dl = getCurSDLoc();
6460 // Use the produced MatchedRegs object to
6461 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6462 Chain, &Flag, CS.getInstruction());
6463 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6464 true, OpInfo.getMatchedOperand(), dl,
6465 DAG, AsmNodeOperands);
6469 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6470 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6471 "Unexpected number of operands");
6472 // Add information to the INLINEASM node to know about this input.
6473 // See InlineAsm.h isUseOperandTiedToDef.
6474 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6475 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6476 OpInfo.getMatchedOperand());
6477 AsmNodeOperands.push_back(DAG.getTargetConstant(
6478 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6479 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6483 // Treat indirect 'X' constraint as memory.
6484 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6486 OpInfo.ConstraintType = TargetLowering::C_Memory;
6488 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6489 std::vector<SDValue> Ops;
6490 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6493 LLVMContext &Ctx = *DAG.getContext();
6494 Ctx.emitError(CS.getInstruction(),
6495 "invalid operand for inline asm constraint '" +
6496 Twine(OpInfo.ConstraintCode) + "'");
6500 // Add information to the INLINEASM node to know about this input.
6501 unsigned ResOpType =
6502 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6503 AsmNodeOperands.push_back(DAG.getTargetConstant(
6504 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6505 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6509 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6510 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6511 assert(InOperandVal.getValueType() ==
6512 TLI.getPointerTy(DAG.getDataLayout()) &&
6513 "Memory operands expect pointer values");
6515 unsigned ConstraintID =
6516 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6517 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6518 "Failed to convert memory constraint code to constraint id.");
6520 // Add information to the INLINEASM node to know about this input.
6521 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6522 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6523 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6526 AsmNodeOperands.push_back(InOperandVal);
6530 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6531 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6532 "Unknown constraint type!");
6534 // TODO: Support this.
6535 if (OpInfo.isIndirect) {
6536 LLVMContext &Ctx = *DAG.getContext();
6537 Ctx.emitError(CS.getInstruction(),
6538 "Don't know how to handle indirect register inputs yet "
6539 "for constraint '" +
6540 Twine(OpInfo.ConstraintCode) + "'");
6544 // Copy the input into the appropriate registers.
6545 if (OpInfo.AssignedRegs.Regs.empty()) {
6546 LLVMContext &Ctx = *DAG.getContext();
6547 Ctx.emitError(CS.getInstruction(),
6548 "couldn't allocate input reg for constraint '" +
6549 Twine(OpInfo.ConstraintCode) + "'");
6553 SDLoc dl = getCurSDLoc();
6555 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6556 Chain, &Flag, CS.getInstruction());
6558 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6559 dl, DAG, AsmNodeOperands);
6562 case InlineAsm::isClobber: {
6563 // Add the clobbered value to the operand list, so that the register
6564 // allocator is aware that the physreg got clobbered.
6565 if (!OpInfo.AssignedRegs.Regs.empty())
6566 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6567 false, 0, getCurSDLoc(), DAG,
6574 // Finish up input operands. Set the input chain and add the flag last.
6575 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6576 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6578 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6579 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6580 Flag = Chain.getValue(1);
6582 // If this asm returns a register value, copy the result from that register
6583 // and set it as the value of the call.
6584 if (!RetValRegs.Regs.empty()) {
6585 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6586 Chain, &Flag, CS.getInstruction());
6588 // FIXME: Why don't we do this for inline asms with MRVs?
6589 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6590 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6592 // If any of the results of the inline asm is a vector, it may have the
6593 // wrong width/num elts. This can happen for register classes that can
6594 // contain multiple different value types. The preg or vreg allocated may
6595 // not have the same VT as was expected. Convert it to the right type
6596 // with bit_convert.
6597 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6598 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6601 } else if (ResultType != Val.getValueType() &&
6602 ResultType.isInteger() && Val.getValueType().isInteger()) {
6603 // If a result value was tied to an input value, the computed result may
6604 // have a wider width than the expected result. Extract the relevant
6606 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6609 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6612 setValue(CS.getInstruction(), Val);
6613 // Don't need to use this as a chain in this case.
6614 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6618 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6620 // Process indirect outputs, first output all of the flagged copies out of
6622 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6623 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6624 const Value *Ptr = IndirectStoresToEmit[i].second;
6625 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6627 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6630 // Emit the non-flagged stores from the physregs.
6631 SmallVector<SDValue, 8> OutChains;
6632 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6633 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6634 StoresToEmit[i].first,
6635 getValue(StoresToEmit[i].second),
6636 MachinePointerInfo(StoresToEmit[i].second),
6638 OutChains.push_back(Val);
6641 if (!OutChains.empty())
6642 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6647 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6648 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6649 MVT::Other, getRoot(),
6650 getValue(I.getArgOperand(0)),
6651 DAG.getSrcValue(I.getArgOperand(0))));
6654 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6656 const DataLayout &DL = DAG.getDataLayout();
6657 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6658 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6659 DAG.getSrcValue(I.getOperand(0)),
6660 DL.getABITypeAlignment(I.getType()));
6662 DAG.setRoot(V.getValue(1));
6665 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6666 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6667 MVT::Other, getRoot(),
6668 getValue(I.getArgOperand(0)),
6669 DAG.getSrcValue(I.getArgOperand(0))));
6672 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6673 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6674 MVT::Other, getRoot(),
6675 getValue(I.getArgOperand(0)),
6676 getValue(I.getArgOperand(1)),
6677 DAG.getSrcValue(I.getArgOperand(0)),
6678 DAG.getSrcValue(I.getArgOperand(1))));
6681 /// \brief Lower an argument list according to the target calling convention.
6683 /// \return A tuple of <return-value, token-chain>
6685 /// This is a helper for lowering intrinsics that follow a target calling
6686 /// convention or require stack pointer adjustment. Only a subset of the
6687 /// intrinsic's operands need to participate in the calling convention.
6688 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6689 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6690 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6691 TargetLowering::ArgListTy Args;
6692 Args.reserve(NumArgs);
6694 // Populate the argument list.
6695 // Attributes for args start at offset 1, after the return attribute.
6696 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6697 ArgI != ArgE; ++ArgI) {
6698 const Value *V = CS->getOperand(ArgI);
6700 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6702 TargetLowering::ArgListEntry Entry;
6703 Entry.Node = getValue(V);
6704 Entry.Ty = V->getType();
6705 Entry.setAttributes(&CS, AttrI);
6706 Args.push_back(Entry);
6709 TargetLowering::CallLoweringInfo CLI(DAG);
6710 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6711 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6712 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6714 return lowerInvokable(CLI, EHPadBB);
6717 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6718 /// or patchpoint target node's operand list.
6720 /// Constants are converted to TargetConstants purely as an optimization to
6721 /// avoid constant materialization and register allocation.
6723 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6724 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6725 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6726 /// address materialization and register allocation, but may also be required
6727 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6728 /// alloca in the entry block, then the runtime may assume that the alloca's
6729 /// StackMap location can be read immediately after compilation and that the
6730 /// location is valid at any point during execution (this is similar to the
6731 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6732 /// only available in a register, then the runtime would need to trap when
6733 /// execution reaches the StackMap in order to read the alloca's location.
6734 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6735 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6736 SelectionDAGBuilder &Builder) {
6737 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6738 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6739 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6741 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6743 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6744 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6745 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6746 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6747 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6749 Ops.push_back(OpVal);
6753 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6754 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6755 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6756 // [live variables...])
6758 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6760 SDValue Chain, InFlag, Callee, NullPtr;
6761 SmallVector<SDValue, 32> Ops;
6763 SDLoc DL = getCurSDLoc();
6764 Callee = getValue(CI.getCalledValue());
6765 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6767 // The stackmap intrinsic only records the live variables (the arguemnts
6768 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6769 // intrinsic, this won't be lowered to a function call. This means we don't
6770 // have to worry about calling conventions and target specific lowering code.
6771 // Instead we perform the call lowering right here.
6773 // chain, flag = CALLSEQ_START(chain, 0)
6774 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6775 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6777 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6778 InFlag = Chain.getValue(1);
6780 // Add the <id> and <numBytes> constants.
6781 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6782 Ops.push_back(DAG.getTargetConstant(
6783 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6784 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6785 Ops.push_back(DAG.getTargetConstant(
6786 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6789 // Push live variables for the stack map.
6790 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6792 // We are not pushing any register mask info here on the operands list,
6793 // because the stackmap doesn't clobber anything.
6795 // Push the chain and the glue flag.
6796 Ops.push_back(Chain);
6797 Ops.push_back(InFlag);
6799 // Create the STACKMAP node.
6800 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6801 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6802 Chain = SDValue(SM, 0);
6803 InFlag = Chain.getValue(1);
6805 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6807 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6809 // Set the root to the target-lowered call chain.
6812 // Inform the Frame Information that we have a stackmap in this function.
6813 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6816 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6817 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6818 const BasicBlock *EHPadBB) {
6819 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6824 // [live variables...])
6826 CallingConv::ID CC = CS.getCallingConv();
6827 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6828 bool HasDef = !CS->getType()->isVoidTy();
6829 SDLoc dl = getCurSDLoc();
6830 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6832 // Handle immediate and symbolic callees.
6833 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6834 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6836 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6837 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6838 SDLoc(SymbolicCallee),
6839 SymbolicCallee->getValueType(0));
6841 // Get the real number of arguments participating in the call <numArgs>
6842 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6843 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6845 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6846 // Intrinsics include all meta-operands up to but not including CC.
6847 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6848 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6849 "Not enough arguments provided to the patchpoint intrinsic");
6851 // For AnyRegCC the arguments are lowered later on manually.
6852 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6854 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6855 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6856 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6858 SDNode *CallEnd = Result.second.getNode();
6859 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6860 CallEnd = CallEnd->getOperand(0).getNode();
6862 /// Get a call instruction from the call sequence chain.
6863 /// Tail calls are not allowed.
6864 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6865 "Expected a callseq node.");
6866 SDNode *Call = CallEnd->getOperand(0).getNode();
6867 bool HasGlue = Call->getGluedNode();
6869 // Replace the target specific call node with the patchable intrinsic.
6870 SmallVector<SDValue, 8> Ops;
6872 // Add the <id> and <numBytes> constants.
6873 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6874 Ops.push_back(DAG.getTargetConstant(
6875 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6876 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6877 Ops.push_back(DAG.getTargetConstant(
6878 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6882 Ops.push_back(Callee);
6884 // Adjust <numArgs> to account for any arguments that have been passed on the
6886 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6887 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6888 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6889 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6891 // Add the calling convention
6892 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6894 // Add the arguments we omitted previously. The register allocator should
6895 // place these in any free register.
6897 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6898 Ops.push_back(getValue(CS.getArgument(i)));
6900 // Push the arguments from the call instruction up to the register mask.
6901 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6902 Ops.append(Call->op_begin() + 2, e);
6904 // Push live variables for the stack map.
6905 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6907 // Push the register mask info.
6909 Ops.push_back(*(Call->op_end()-2));
6911 Ops.push_back(*(Call->op_end()-1));
6913 // Push the chain (this is originally the first operand of the call, but
6914 // becomes now the last or second to last operand).
6915 Ops.push_back(*(Call->op_begin()));
6917 // Push the glue flag (last operand).
6919 Ops.push_back(*(Call->op_end()-1));
6922 if (IsAnyRegCC && HasDef) {
6923 // Create the return types based on the intrinsic definition
6924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6925 SmallVector<EVT, 3> ValueVTs;
6926 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6927 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6929 // There is always a chain and a glue type at the end
6930 ValueVTs.push_back(MVT::Other);
6931 ValueVTs.push_back(MVT::Glue);
6932 NodeTys = DAG.getVTList(ValueVTs);
6934 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6936 // Replace the target specific call node with a PATCHPOINT node.
6937 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6940 // Update the NodeMap.
6943 setValue(CS.getInstruction(), SDValue(MN, 0));
6945 setValue(CS.getInstruction(), Result.first);
6948 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6949 // call sequence. Furthermore the location of the chain and glue can change
6950 // when the AnyReg calling convention is used and the intrinsic returns a
6952 if (IsAnyRegCC && HasDef) {
6953 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6954 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6955 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6957 DAG.ReplaceAllUsesWith(Call, MN);
6958 DAG.DeleteNode(Call);
6960 // Inform the Frame Information that we have a patchpoint in this function.
6961 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6964 /// Returns an AttributeSet representing the attributes applied to the return
6965 /// value of the given call.
6966 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6967 SmallVector<Attribute::AttrKind, 2> Attrs;
6969 Attrs.push_back(Attribute::SExt);
6971 Attrs.push_back(Attribute::ZExt);
6973 Attrs.push_back(Attribute::InReg);
6975 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6979 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6980 /// implementation, which just calls LowerCall.
6981 /// FIXME: When all targets are
6982 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6983 std::pair<SDValue, SDValue>
6984 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6985 // Handle the incoming return values from the call.
6987 Type *OrigRetTy = CLI.RetTy;
6988 SmallVector<EVT, 4> RetTys;
6989 SmallVector<uint64_t, 4> Offsets;
6990 auto &DL = CLI.DAG.getDataLayout();
6991 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6993 SmallVector<ISD::OutputArg, 4> Outs;
6994 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6996 bool CanLowerReturn =
6997 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6998 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7000 SDValue DemoteStackSlot;
7001 int DemoteStackIdx = -100;
7002 if (!CanLowerReturn) {
7003 // FIXME: equivalent assert?
7004 // assert(!CS.hasInAllocaArgument() &&
7005 // "sret demotion is incompatible with inalloca");
7006 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7007 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7008 MachineFunction &MF = CLI.DAG.getMachineFunction();
7009 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7010 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7012 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7014 Entry.Node = DemoteStackSlot;
7015 Entry.Ty = StackSlotPtrType;
7016 Entry.isSExt = false;
7017 Entry.isZExt = false;
7018 Entry.isInReg = false;
7019 Entry.isSRet = true;
7020 Entry.isNest = false;
7021 Entry.isByVal = false;
7022 Entry.isReturned = false;
7023 Entry.Alignment = Align;
7024 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7025 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7027 // sret demotion isn't compatible with tail-calls, since the sret argument
7028 // points into the callers stack frame.
7029 CLI.IsTailCall = false;
7031 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7033 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7034 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7035 for (unsigned i = 0; i != NumRegs; ++i) {
7036 ISD::InputArg MyFlags;
7037 MyFlags.VT = RegisterVT;
7039 MyFlags.Used = CLI.IsReturnValueUsed;
7041 MyFlags.Flags.setSExt();
7043 MyFlags.Flags.setZExt();
7045 MyFlags.Flags.setInReg();
7046 CLI.Ins.push_back(MyFlags);
7051 // Handle all of the outgoing arguments.
7053 CLI.OutVals.clear();
7054 ArgListTy &Args = CLI.getArgs();
7055 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7056 SmallVector<EVT, 4> ValueVTs;
7057 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7058 Type *FinalType = Args[i].Ty;
7059 if (Args[i].isByVal)
7060 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7061 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7062 FinalType, CLI.CallConv, CLI.IsVarArg);
7063 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7065 EVT VT = ValueVTs[Value];
7066 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7067 SDValue Op = SDValue(Args[i].Node.getNode(),
7068 Args[i].Node.getResNo() + Value);
7069 ISD::ArgFlagsTy Flags;
7070 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7076 if (Args[i].isInReg)
7080 if (Args[i].isByVal)
7082 if (Args[i].isInAlloca) {
7083 Flags.setInAlloca();
7084 // Set the byval flag for CCAssignFn callbacks that don't know about
7085 // inalloca. This way we can know how many bytes we should've allocated
7086 // and how many bytes a callee cleanup function will pop. If we port
7087 // inalloca to more targets, we'll have to add custom inalloca handling
7088 // in the various CC lowering callbacks.
7091 if (Args[i].isByVal || Args[i].isInAlloca) {
7092 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7093 Type *ElementTy = Ty->getElementType();
7094 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7095 // For ByVal, alignment should come from FE. BE will guess if this
7096 // info is not there but there are cases it cannot get right.
7097 unsigned FrameAlign;
7098 if (Args[i].Alignment)
7099 FrameAlign = Args[i].Alignment;
7101 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7102 Flags.setByValAlign(FrameAlign);
7107 Flags.setInConsecutiveRegs();
7108 Flags.setOrigAlign(OriginalAlignment);
7110 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7111 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7112 SmallVector<SDValue, 4> Parts(NumParts);
7113 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7116 ExtendKind = ISD::SIGN_EXTEND;
7117 else if (Args[i].isZExt)
7118 ExtendKind = ISD::ZERO_EXTEND;
7120 // Conservatively only handle 'returned' on non-vectors for now
7121 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7122 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7123 "unexpected use of 'returned'");
7124 // Before passing 'returned' to the target lowering code, ensure that
7125 // either the register MVT and the actual EVT are the same size or that
7126 // the return value and argument are extended in the same way; in these
7127 // cases it's safe to pass the argument register value unchanged as the
7128 // return register value (although it's at the target's option whether
7130 // TODO: allow code generation to take advantage of partially preserved
7131 // registers rather than clobbering the entire register when the
7132 // parameter extension method is not compatible with the return
7134 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7135 (ExtendKind != ISD::ANY_EXTEND &&
7136 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7137 Flags.setReturned();
7140 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7141 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7143 for (unsigned j = 0; j != NumParts; ++j) {
7144 // if it isn't first piece, alignment must be 1
7145 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7146 i < CLI.NumFixedArgs,
7147 i, j*Parts[j].getValueType().getStoreSize());
7148 if (NumParts > 1 && j == 0)
7149 MyFlags.Flags.setSplit();
7151 MyFlags.Flags.setOrigAlign(1);
7153 CLI.Outs.push_back(MyFlags);
7154 CLI.OutVals.push_back(Parts[j]);
7157 if (NeedsRegBlock && Value == NumValues - 1)
7158 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7162 SmallVector<SDValue, 4> InVals;
7163 CLI.Chain = LowerCall(CLI, InVals);
7165 // Verify that the target's LowerCall behaved as expected.
7166 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7167 "LowerCall didn't return a valid chain!");
7168 assert((!CLI.IsTailCall || InVals.empty()) &&
7169 "LowerCall emitted a return value for a tail call!");
7170 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7171 "LowerCall didn't emit the correct number of values!");
7173 // For a tail call, the return value is merely live-out and there aren't
7174 // any nodes in the DAG representing it. Return a special value to
7175 // indicate that a tail call has been emitted and no more Instructions
7176 // should be processed in the current block.
7177 if (CLI.IsTailCall) {
7178 CLI.DAG.setRoot(CLI.Chain);
7179 return std::make_pair(SDValue(), SDValue());
7182 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7183 assert(InVals[i].getNode() &&
7184 "LowerCall emitted a null value!");
7185 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7186 "LowerCall emitted a value with the wrong type!");
7189 SmallVector<SDValue, 4> ReturnValues;
7190 if (!CanLowerReturn) {
7191 // The instruction result is the result of loading from the
7192 // hidden sret parameter.
7193 SmallVector<EVT, 1> PVTs;
7194 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7196 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7197 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7198 EVT PtrVT = PVTs[0];
7200 unsigned NumValues = RetTys.size();
7201 ReturnValues.resize(NumValues);
7202 SmallVector<SDValue, 4> Chains(NumValues);
7204 for (unsigned i = 0; i < NumValues; ++i) {
7205 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7206 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7208 SDValue L = CLI.DAG.getLoad(
7209 RetTys[i], CLI.DL, CLI.Chain, Add,
7210 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7211 DemoteStackIdx, Offsets[i]),
7212 false, false, false, 1);
7213 ReturnValues[i] = L;
7214 Chains[i] = L.getValue(1);
7217 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7219 // Collect the legal value parts into potentially illegal values
7220 // that correspond to the original function's return values.
7221 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7223 AssertOp = ISD::AssertSext;
7224 else if (CLI.RetZExt)
7225 AssertOp = ISD::AssertZext;
7226 unsigned CurReg = 0;
7227 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7229 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7230 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7232 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7233 NumRegs, RegisterVT, VT, nullptr,
7238 // For a function returning void, there is no return value. We can't create
7239 // such a node, so we just return a null return value in that case. In
7240 // that case, nothing will actually look at the value.
7241 if (ReturnValues.empty())
7242 return std::make_pair(SDValue(), CLI.Chain);
7245 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7246 CLI.DAG.getVTList(RetTys), ReturnValues);
7247 return std::make_pair(Res, CLI.Chain);
7250 void TargetLowering::LowerOperationWrapper(SDNode *N,
7251 SmallVectorImpl<SDValue> &Results,
7252 SelectionDAG &DAG) const {
7253 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7255 Results.push_back(Res);
7258 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7259 llvm_unreachable("LowerOperation not implemented for this target!");
7263 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7264 SDValue Op = getNonRegisterValue(V);
7265 assert((Op.getOpcode() != ISD::CopyFromReg ||
7266 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7267 "Copy from a reg to the same reg!");
7268 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7270 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7271 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7273 SDValue Chain = DAG.getEntryNode();
7275 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7276 FuncInfo.PreferredExtendType.end())
7278 : FuncInfo.PreferredExtendType[V];
7279 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7280 PendingExports.push_back(Chain);
7283 #include "llvm/CodeGen/SelectionDAGISel.h"
7285 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7286 /// entry block, return true. This includes arguments used by switches, since
7287 /// the switch may expand into multiple basic blocks.
7288 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7289 // With FastISel active, we may be splitting blocks, so force creation
7290 // of virtual registers for all non-dead arguments.
7292 return A->use_empty();
7294 const BasicBlock &Entry = A->getParent()->front();
7295 for (const User *U : A->users())
7296 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7297 return false; // Use not in entry block.
7302 void SelectionDAGISel::LowerArguments(const Function &F) {
7303 SelectionDAG &DAG = SDB->DAG;
7304 SDLoc dl = SDB->getCurSDLoc();
7305 const DataLayout &DL = DAG.getDataLayout();
7306 SmallVector<ISD::InputArg, 16> Ins;
7308 if (!FuncInfo->CanLowerReturn) {
7309 // Put in an sret pointer parameter before all the other parameters.
7310 SmallVector<EVT, 1> ValueVTs;
7311 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7312 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7314 // NOTE: Assuming that a pointer will never break down to more than one VT
7316 ISD::ArgFlagsTy Flags;
7318 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7319 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7320 ISD::InputArg::NoArgIndex, 0);
7321 Ins.push_back(RetArg);
7324 // Set up the incoming argument description vector.
7326 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7327 I != E; ++I, ++Idx) {
7328 SmallVector<EVT, 4> ValueVTs;
7329 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7330 bool isArgValueUsed = !I->use_empty();
7331 unsigned PartBase = 0;
7332 Type *FinalType = I->getType();
7333 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7334 FinalType = cast<PointerType>(FinalType)->getElementType();
7335 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7336 FinalType, F.getCallingConv(), F.isVarArg());
7337 for (unsigned Value = 0, NumValues = ValueVTs.size();
7338 Value != NumValues; ++Value) {
7339 EVT VT = ValueVTs[Value];
7340 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7341 ISD::ArgFlagsTy Flags;
7342 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7344 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7346 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7348 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7350 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7352 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7354 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7355 Flags.setInAlloca();
7356 // Set the byval flag for CCAssignFn callbacks that don't know about
7357 // inalloca. This way we can know how many bytes we should've allocated
7358 // and how many bytes a callee cleanup function will pop. If we port
7359 // inalloca to more targets, we'll have to add custom inalloca handling
7360 // in the various CC lowering callbacks.
7363 if (Flags.isByVal() || Flags.isInAlloca()) {
7364 PointerType *Ty = cast<PointerType>(I->getType());
7365 Type *ElementTy = Ty->getElementType();
7366 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7367 // For ByVal, alignment should be passed from FE. BE will guess if
7368 // this info is not there but there are cases it cannot get right.
7369 unsigned FrameAlign;
7370 if (F.getParamAlignment(Idx))
7371 FrameAlign = F.getParamAlignment(Idx);
7373 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7374 Flags.setByValAlign(FrameAlign);
7376 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7379 Flags.setInConsecutiveRegs();
7380 Flags.setOrigAlign(OriginalAlignment);
7382 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7383 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7384 for (unsigned i = 0; i != NumRegs; ++i) {
7385 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7386 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7387 if (NumRegs > 1 && i == 0)
7388 MyFlags.Flags.setSplit();
7389 // if it isn't first piece, alignment must be 1
7391 MyFlags.Flags.setOrigAlign(1);
7392 Ins.push_back(MyFlags);
7394 if (NeedsRegBlock && Value == NumValues - 1)
7395 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7396 PartBase += VT.getStoreSize();
7400 // Call the target to set up the argument values.
7401 SmallVector<SDValue, 8> InVals;
7402 SDValue NewRoot = TLI->LowerFormalArguments(
7403 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7405 // Verify that the target's LowerFormalArguments behaved as expected.
7406 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7407 "LowerFormalArguments didn't return a valid chain!");
7408 assert(InVals.size() == Ins.size() &&
7409 "LowerFormalArguments didn't emit the correct number of values!");
7411 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7412 assert(InVals[i].getNode() &&
7413 "LowerFormalArguments emitted a null value!");
7414 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7415 "LowerFormalArguments emitted a value with the wrong type!");
7419 // Update the DAG with the new chain value resulting from argument lowering.
7420 DAG.setRoot(NewRoot);
7422 // Set up the argument values.
7425 if (!FuncInfo->CanLowerReturn) {
7426 // Create a virtual register for the sret pointer, and put in a copy
7427 // from the sret argument into it.
7428 SmallVector<EVT, 1> ValueVTs;
7429 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7430 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7431 MVT VT = ValueVTs[0].getSimpleVT();
7432 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7433 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7434 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7435 RegVT, VT, nullptr, AssertOp);
7437 MachineFunction& MF = SDB->DAG.getMachineFunction();
7438 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7439 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7440 FuncInfo->DemoteRegister = SRetReg;
7442 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7443 DAG.setRoot(NewRoot);
7445 // i indexes lowered arguments. Bump it past the hidden sret argument.
7446 // Idx indexes LLVM arguments. Don't touch it.
7450 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7452 SmallVector<SDValue, 4> ArgValues;
7453 SmallVector<EVT, 4> ValueVTs;
7454 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7455 unsigned NumValues = ValueVTs.size();
7457 // If this argument is unused then remember its value. It is used to generate
7458 // debugging information.
7459 if (I->use_empty() && NumValues) {
7460 SDB->setUnusedArgValue(&*I, InVals[i]);
7462 // Also remember any frame index for use in FastISel.
7463 if (FrameIndexSDNode *FI =
7464 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7465 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7468 for (unsigned Val = 0; Val != NumValues; ++Val) {
7469 EVT VT = ValueVTs[Val];
7470 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7471 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7473 if (!I->use_empty()) {
7474 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7475 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7476 AssertOp = ISD::AssertSext;
7477 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7478 AssertOp = ISD::AssertZext;
7480 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7481 NumParts, PartVT, VT,
7482 nullptr, AssertOp));
7488 // We don't need to do anything else for unused arguments.
7489 if (ArgValues.empty())
7492 // Note down frame index.
7493 if (FrameIndexSDNode *FI =
7494 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7495 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7497 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7498 SDB->getCurSDLoc());
7500 SDB->setValue(&*I, Res);
7501 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7502 if (LoadSDNode *LNode =
7503 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7504 if (FrameIndexSDNode *FI =
7505 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7506 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7509 // If this argument is live outside of the entry block, insert a copy from
7510 // wherever we got it to the vreg that other BB's will reference it as.
7511 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7512 // If we can, though, try to skip creating an unnecessary vreg.
7513 // FIXME: This isn't very clean... it would be nice to make this more
7514 // general. It's also subtly incompatible with the hacks FastISel
7516 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7517 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7518 FuncInfo->ValueMap[&*I] = Reg;
7522 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7523 FuncInfo->InitializeRegForValue(&*I);
7524 SDB->CopyToExportRegsIfNeeded(&*I);
7528 assert(i == InVals.size() && "Argument register count mismatch!");
7530 // Finally, if the target has anything special to do, allow it to do so.
7531 EmitFunctionEntryCode();
7534 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7535 /// ensure constants are generated when needed. Remember the virtual registers
7536 /// that need to be added to the Machine PHI nodes as input. We cannot just
7537 /// directly add them, because expansion might result in multiple MBB's for one
7538 /// BB. As such, the start of the BB might correspond to a different MBB than
7542 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7543 const TerminatorInst *TI = LLVMBB->getTerminator();
7545 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7547 // Check PHI nodes in successors that expect a value to be available from this
7549 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7550 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7551 if (!isa<PHINode>(SuccBB->begin())) continue;
7552 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7554 // If this terminator has multiple identical successors (common for
7555 // switches), only handle each succ once.
7556 if (!SuccsHandled.insert(SuccMBB).second)
7559 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7561 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7562 // nodes and Machine PHI nodes, but the incoming operands have not been
7564 for (BasicBlock::const_iterator I = SuccBB->begin();
7565 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7566 // Ignore dead phi's.
7567 if (PN->use_empty()) continue;
7570 if (PN->getType()->isEmptyTy())
7574 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7576 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7577 unsigned &RegOut = ConstantsOut[C];
7579 RegOut = FuncInfo.CreateRegs(C->getType());
7580 CopyValueToVirtualRegister(C, RegOut);
7584 DenseMap<const Value *, unsigned>::iterator I =
7585 FuncInfo.ValueMap.find(PHIOp);
7586 if (I != FuncInfo.ValueMap.end())
7589 assert(isa<AllocaInst>(PHIOp) &&
7590 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7591 "Didn't codegen value into a register!??");
7592 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7593 CopyValueToVirtualRegister(PHIOp, Reg);
7597 // Remember that this register needs to added to the machine PHI node as
7598 // the input for this MBB.
7599 SmallVector<EVT, 4> ValueVTs;
7600 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7601 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7602 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7603 EVT VT = ValueVTs[vti];
7604 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7605 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7606 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7607 Reg += NumRegisters;
7612 ConstantsOut.clear();
7615 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7618 SelectionDAGBuilder::StackProtectorDescriptor::
7619 AddSuccessorMBB(const BasicBlock *BB,
7620 MachineBasicBlock *ParentMBB,
7622 MachineBasicBlock *SuccMBB) {
7623 // If SuccBB has not been created yet, create it.
7625 MachineFunction *MF = ParentMBB->getParent();
7626 MachineFunction::iterator BBI(ParentMBB);
7627 SuccMBB = MF->CreateMachineBasicBlock(BB);
7628 MF->insert(++BBI, SuccMBB);
7630 // Add it as a successor of ParentMBB.
7631 ParentMBB->addSuccessor(
7632 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7636 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7637 MachineFunction::iterator I(MBB);
7638 if (++I == FuncInfo.MF->end())
7643 /// During lowering new call nodes can be created (such as memset, etc.).
7644 /// Those will become new roots of the current DAG, but complications arise
7645 /// when they are tail calls. In such cases, the call lowering will update
7646 /// the root, but the builder still needs to know that a tail call has been
7647 /// lowered in order to avoid generating an additional return.
7648 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7649 // If the node is null, we do have a tail call.
7650 if (MaybeTC.getNode() != nullptr)
7651 DAG.setRoot(MaybeTC);
7656 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7657 unsigned *TotalCases, unsigned First,
7659 assert(Last >= First);
7660 assert(TotalCases[Last] >= TotalCases[First]);
7662 APInt LowCase = Clusters[First].Low->getValue();
7663 APInt HighCase = Clusters[Last].High->getValue();
7664 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7666 // FIXME: A range of consecutive cases has 100% density, but only requires one
7667 // comparison to lower. We should discriminate against such consecutive ranges
7670 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7671 uint64_t Range = Diff + 1;
7674 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7676 assert(NumCases < UINT64_MAX / 100);
7677 assert(Range >= NumCases);
7679 return NumCases * 100 >= Range * MinJumpTableDensity;
7682 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7683 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7684 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7687 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7688 unsigned First, unsigned Last,
7689 const SwitchInst *SI,
7690 MachineBasicBlock *DefaultMBB,
7691 CaseCluster &JTCluster) {
7692 assert(First <= Last);
7694 uint32_t Weight = 0;
7695 unsigned NumCmps = 0;
7696 std::vector<MachineBasicBlock*> Table;
7697 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7698 for (unsigned I = First; I <= Last; ++I) {
7699 assert(Clusters[I].Kind == CC_Range);
7700 Weight += Clusters[I].Weight;
7701 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7702 APInt Low = Clusters[I].Low->getValue();
7703 APInt High = Clusters[I].High->getValue();
7704 NumCmps += (Low == High) ? 1 : 2;
7706 // Fill the gap between this and the previous cluster.
7707 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7708 assert(PreviousHigh.slt(Low));
7709 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7710 for (uint64_t J = 0; J < Gap; J++)
7711 Table.push_back(DefaultMBB);
7713 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7714 for (uint64_t J = 0; J < ClusterSize; ++J)
7715 Table.push_back(Clusters[I].MBB);
7716 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7719 unsigned NumDests = JTWeights.size();
7720 if (isSuitableForBitTests(NumDests, NumCmps,
7721 Clusters[First].Low->getValue(),
7722 Clusters[Last].High->getValue())) {
7723 // Clusters[First..Last] should be lowered as bit tests instead.
7727 // Create the MBB that will load from and jump through the table.
7728 // Note: We create it here, but it's not inserted into the function yet.
7729 MachineFunction *CurMF = FuncInfo.MF;
7730 MachineBasicBlock *JumpTableMBB =
7731 CurMF->CreateMachineBasicBlock(SI->getParent());
7733 // Add successors. Note: use table order for determinism.
7734 SmallPtrSet<MachineBasicBlock *, 8> Done;
7735 for (MachineBasicBlock *Succ : Table) {
7736 if (Done.count(Succ))
7738 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7743 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7744 ->createJumpTableIndex(Table);
7746 // Set up the jump table info.
7747 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7748 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7749 Clusters[Last].High->getValue(), SI->getCondition(),
7751 JTCases.emplace_back(std::move(JTH), std::move(JT));
7753 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7754 JTCases.size() - 1, Weight);
7758 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7759 const SwitchInst *SI,
7760 MachineBasicBlock *DefaultMBB) {
7762 // Clusters must be non-empty, sorted, and only contain Range clusters.
7763 assert(!Clusters.empty());
7764 for (CaseCluster &C : Clusters)
7765 assert(C.Kind == CC_Range);
7766 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7767 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7771 if (!areJTsAllowed(TLI))
7774 const int64_t N = Clusters.size();
7775 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7777 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7778 SmallVector<unsigned, 8> TotalCases(N);
7780 for (unsigned i = 0; i < N; ++i) {
7781 APInt Hi = Clusters[i].High->getValue();
7782 APInt Lo = Clusters[i].Low->getValue();
7783 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7785 TotalCases[i] += TotalCases[i - 1];
7788 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7789 // Cheap case: the whole range might be suitable for jump table.
7790 CaseCluster JTCluster;
7791 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7792 Clusters[0] = JTCluster;
7798 // The algorithm below is not suitable for -O0.
7799 if (TM.getOptLevel() == CodeGenOpt::None)
7802 // Split Clusters into minimum number of dense partitions. The algorithm uses
7803 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7804 // for the Case Statement'" (1994), but builds the MinPartitions array in
7805 // reverse order to make it easier to reconstruct the partitions in ascending
7806 // order. In the choice between two optimal partitionings, it picks the one
7807 // which yields more jump tables.
7809 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7810 SmallVector<unsigned, 8> MinPartitions(N);
7811 // LastElement[i] is the last element of the partition starting at i.
7812 SmallVector<unsigned, 8> LastElement(N);
7813 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7814 SmallVector<unsigned, 8> NumTables(N);
7816 // Base case: There is only one way to partition Clusters[N-1].
7817 MinPartitions[N - 1] = 1;
7818 LastElement[N - 1] = N - 1;
7819 assert(MinJumpTableSize > 1);
7820 NumTables[N - 1] = 0;
7822 // Note: loop indexes are signed to avoid underflow.
7823 for (int64_t i = N - 2; i >= 0; i--) {
7824 // Find optimal partitioning of Clusters[i..N-1].
7825 // Baseline: Put Clusters[i] into a partition on its own.
7826 MinPartitions[i] = MinPartitions[i + 1] + 1;
7828 NumTables[i] = NumTables[i + 1];
7830 // Search for a solution that results in fewer partitions.
7831 for (int64_t j = N - 1; j > i; j--) {
7832 // Try building a partition from Clusters[i..j].
7833 if (isDense(Clusters, &TotalCases[0], i, j)) {
7834 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7835 bool IsTable = j - i + 1 >= MinJumpTableSize;
7836 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7838 // If this j leads to fewer partitions, or same number of partitions
7839 // with more lookup tables, it is a better partitioning.
7840 if (NumPartitions < MinPartitions[i] ||
7841 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7842 MinPartitions[i] = NumPartitions;
7844 NumTables[i] = Tables;
7850 // Iterate over the partitions, replacing some with jump tables in-place.
7851 unsigned DstIndex = 0;
7852 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7853 Last = LastElement[First];
7854 assert(Last >= First);
7855 assert(DstIndex <= First);
7856 unsigned NumClusters = Last - First + 1;
7858 CaseCluster JTCluster;
7859 if (NumClusters >= MinJumpTableSize &&
7860 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7861 Clusters[DstIndex++] = JTCluster;
7863 for (unsigned I = First; I <= Last; ++I)
7864 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7867 Clusters.resize(DstIndex);
7870 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7871 // FIXME: Using the pointer type doesn't seem ideal.
7872 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7873 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7877 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7880 const APInt &High) {
7881 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7882 // range of cases both require only one branch to lower. Just looking at the
7883 // number of clusters and destinations should be enough to decide whether to
7886 // To lower a range with bit tests, the range must fit the bitwidth of a
7888 if (!rangeFitsInWord(Low, High))
7891 // Decide whether it's profitable to lower this range with bit tests. Each
7892 // destination requires a bit test and branch, and there is an overall range
7893 // check branch. For a small number of clusters, separate comparisons might be
7894 // cheaper, and for many destinations, splitting the range might be better.
7895 return (NumDests == 1 && NumCmps >= 3) ||
7896 (NumDests == 2 && NumCmps >= 5) ||
7897 (NumDests == 3 && NumCmps >= 6);
7900 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7901 unsigned First, unsigned Last,
7902 const SwitchInst *SI,
7903 CaseCluster &BTCluster) {
7904 assert(First <= Last);
7908 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7909 unsigned NumCmps = 0;
7910 for (int64_t I = First; I <= Last; ++I) {
7911 assert(Clusters[I].Kind == CC_Range);
7912 Dests.set(Clusters[I].MBB->getNumber());
7913 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7915 unsigned NumDests = Dests.count();
7917 APInt Low = Clusters[First].Low->getValue();
7918 APInt High = Clusters[Last].High->getValue();
7919 assert(Low.slt(High));
7921 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7927 const int BitWidth = DAG.getTargetLoweringInfo()
7928 .getPointerTy(DAG.getDataLayout())
7930 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7932 // Check if the clusters cover a contiguous range such that no value in the
7933 // range will jump to the default statement.
7934 bool ContiguousRange = true;
7935 for (int64_t I = First + 1; I <= Last; ++I) {
7936 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7937 ContiguousRange = false;
7942 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7943 // Optimize the case where all the case values fit in a word without having
7944 // to subtract minValue. In this case, we can optimize away the subtraction.
7945 LowBound = APInt::getNullValue(Low.getBitWidth());
7947 ContiguousRange = false;
7950 CmpRange = High - Low;
7954 uint32_t TotalWeight = 0;
7955 for (unsigned i = First; i <= Last; ++i) {
7956 // Find the CaseBits for this destination.
7958 for (j = 0; j < CBV.size(); ++j)
7959 if (CBV[j].BB == Clusters[i].MBB)
7961 if (j == CBV.size())
7962 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7963 CaseBits *CB = &CBV[j];
7965 // Update Mask, Bits and ExtraWeight.
7966 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7967 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7968 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7969 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7970 CB->Bits += Hi - Lo + 1;
7971 CB->ExtraWeight += Clusters[i].Weight;
7972 TotalWeight += Clusters[i].Weight;
7973 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7977 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7978 // Sort by weight first, number of bits second.
7979 if (a.ExtraWeight != b.ExtraWeight)
7980 return a.ExtraWeight > b.ExtraWeight;
7981 return a.Bits > b.Bits;
7984 for (auto &CB : CBV) {
7985 MachineBasicBlock *BitTestBB =
7986 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7987 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7989 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7990 SI->getCondition(), -1U, MVT::Other, false,
7991 ContiguousRange, nullptr, nullptr, std::move(BTI),
7994 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7995 BitTestCases.size() - 1, TotalWeight);
7999 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8000 const SwitchInst *SI) {
8001 // Partition Clusters into as few subsets as possible, where each subset has a
8002 // range that fits in a machine word and has <= 3 unique destinations.
8005 // Clusters must be sorted and contain Range or JumpTable clusters.
8006 assert(!Clusters.empty());
8007 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8008 for (const CaseCluster &C : Clusters)
8009 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8010 for (unsigned i = 1; i < Clusters.size(); ++i)
8011 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8014 // The algorithm below is not suitable for -O0.
8015 if (TM.getOptLevel() == CodeGenOpt::None)
8018 // If target does not have legal shift left, do not emit bit tests at all.
8019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8020 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8021 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8024 int BitWidth = PTy.getSizeInBits();
8025 const int64_t N = Clusters.size();
8027 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8028 SmallVector<unsigned, 8> MinPartitions(N);
8029 // LastElement[i] is the last element of the partition starting at i.
8030 SmallVector<unsigned, 8> LastElement(N);
8032 // FIXME: This might not be the best algorithm for finding bit test clusters.
8034 // Base case: There is only one way to partition Clusters[N-1].
8035 MinPartitions[N - 1] = 1;
8036 LastElement[N - 1] = N - 1;
8038 // Note: loop indexes are signed to avoid underflow.
8039 for (int64_t i = N - 2; i >= 0; --i) {
8040 // Find optimal partitioning of Clusters[i..N-1].
8041 // Baseline: Put Clusters[i] into a partition on its own.
8042 MinPartitions[i] = MinPartitions[i + 1] + 1;
8045 // Search for a solution that results in fewer partitions.
8046 // Note: the search is limited by BitWidth, reducing time complexity.
8047 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8048 // Try building a partition from Clusters[i..j].
8051 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8052 Clusters[j].High->getValue()))
8055 // Check nbr of destinations and cluster types.
8056 // FIXME: This works, but doesn't seem very efficient.
8057 bool RangesOnly = true;
8058 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8059 for (int64_t k = i; k <= j; k++) {
8060 if (Clusters[k].Kind != CC_Range) {
8064 Dests.set(Clusters[k].MBB->getNumber());
8066 if (!RangesOnly || Dests.count() > 3)
8069 // Check if it's a better partition.
8070 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8071 if (NumPartitions < MinPartitions[i]) {
8072 // Found a better partition.
8073 MinPartitions[i] = NumPartitions;
8079 // Iterate over the partitions, replacing with bit-test clusters in-place.
8080 unsigned DstIndex = 0;
8081 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8082 Last = LastElement[First];
8083 assert(First <= Last);
8084 assert(DstIndex <= First);
8086 CaseCluster BitTestCluster;
8087 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8088 Clusters[DstIndex++] = BitTestCluster;
8090 size_t NumClusters = Last - First + 1;
8091 std::memmove(&Clusters[DstIndex], &Clusters[First],
8092 sizeof(Clusters[0]) * NumClusters);
8093 DstIndex += NumClusters;
8096 Clusters.resize(DstIndex);
8099 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8100 MachineBasicBlock *SwitchMBB,
8101 MachineBasicBlock *DefaultMBB) {
8102 MachineFunction *CurMF = FuncInfo.MF;
8103 MachineBasicBlock *NextMBB = nullptr;
8104 MachineFunction::iterator BBI(W.MBB);
8105 if (++BBI != FuncInfo.MF->end())
8108 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8110 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8112 if (Size == 2 && W.MBB == SwitchMBB) {
8113 // If any two of the cases has the same destination, and if one value
8114 // is the same as the other, but has one bit unset that the other has set,
8115 // use bit manipulation to do two compares at once. For example:
8116 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8117 // TODO: This could be extended to merge any 2 cases in switches with 3
8119 // TODO: Handle cases where W.CaseBB != SwitchBB.
8120 CaseCluster &Small = *W.FirstCluster;
8121 CaseCluster &Big = *W.LastCluster;
8123 if (Small.Low == Small.High && Big.Low == Big.High &&
8124 Small.MBB == Big.MBB) {
8125 const APInt &SmallValue = Small.Low->getValue();
8126 const APInt &BigValue = Big.Low->getValue();
8128 // Check that there is only one bit different.
8129 APInt CommonBit = BigValue ^ SmallValue;
8130 if (CommonBit.isPowerOf2()) {
8131 SDValue CondLHS = getValue(Cond);
8132 EVT VT = CondLHS.getValueType();
8133 SDLoc DL = getCurSDLoc();
8135 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8136 DAG.getConstant(CommonBit, DL, VT));
8137 SDValue Cond = DAG.getSetCC(
8138 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8141 // Update successor info.
8142 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8143 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8144 addSuccessorWithWeight(
8145 SwitchMBB, DefaultMBB,
8146 // The default destination is the first successor in IR.
8147 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8150 // Insert the true branch.
8152 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8153 DAG.getBasicBlock(Small.MBB));
8154 // Insert the false branch.
8155 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8156 DAG.getBasicBlock(DefaultMBB));
8158 DAG.setRoot(BrCond);
8164 if (TM.getOptLevel() != CodeGenOpt::None) {
8165 // Order cases by weight so the most likely case will be checked first.
8166 std::sort(W.FirstCluster, W.LastCluster + 1,
8167 [](const CaseCluster &a, const CaseCluster &b) {
8168 return a.Weight > b.Weight;
8171 // Rearrange the case blocks so that the last one falls through if possible
8172 // without without changing the order of weights.
8173 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8175 if (I->Weight > W.LastCluster->Weight)
8177 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8178 std::swap(*I, *W.LastCluster);
8184 // Compute total weight.
8185 uint32_t DefaultWeight = W.DefaultWeight;
8186 uint32_t UnhandledWeights = DefaultWeight;
8187 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8188 UnhandledWeights += I->Weight;
8189 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8192 MachineBasicBlock *CurMBB = W.MBB;
8193 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8194 MachineBasicBlock *Fallthrough;
8195 if (I == W.LastCluster) {
8196 // For the last cluster, fall through to the default destination.
8197 Fallthrough = DefaultMBB;
8199 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8200 CurMF->insert(BBI, Fallthrough);
8201 // Put Cond in a virtual register to make it available from the new blocks.
8202 ExportFromCurrentBlock(Cond);
8204 UnhandledWeights -= I->Weight;
8207 case CC_JumpTable: {
8208 // FIXME: Optimize away range check based on pivot comparisons.
8209 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8210 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8212 // The jump block hasn't been inserted yet; insert it here.
8213 MachineBasicBlock *JumpMBB = JT->MBB;
8214 CurMF->insert(BBI, JumpMBB);
8216 uint32_t JumpWeight = I->Weight;
8217 uint32_t FallthroughWeight = UnhandledWeights;
8219 // If the default statement is a target of the jump table, we evenly
8220 // distribute the default weight to successors of CurMBB. Also update
8221 // the weight on the edge from JumpMBB to Fallthrough.
8222 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8223 SE = JumpMBB->succ_end();
8225 if (*SI == DefaultMBB) {
8226 JumpWeight += DefaultWeight / 2;
8227 FallthroughWeight -= DefaultWeight / 2;
8228 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8233 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8234 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8236 // The jump table header will be inserted in our current block, do the
8237 // range check, and fall through to our fallthrough block.
8238 JTH->HeaderBB = CurMBB;
8239 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8241 // If we're in the right place, emit the jump table header right now.
8242 if (CurMBB == SwitchMBB) {
8243 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8244 JTH->Emitted = true;
8249 // FIXME: Optimize away range check based on pivot comparisons.
8250 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8252 // The bit test blocks haven't been inserted yet; insert them here.
8253 for (BitTestCase &BTC : BTB->Cases)
8254 CurMF->insert(BBI, BTC.ThisBB);
8256 // Fill in fields of the BitTestBlock.
8257 BTB->Parent = CurMBB;
8258 BTB->Default = Fallthrough;
8260 BTB->DefaultWeight = UnhandledWeights;
8261 // If the cases in bit test don't form a contiguous range, we evenly
8262 // distribute the weight on the edge to Fallthrough to two successors
8264 if (!BTB->ContiguousRange) {
8265 BTB->Weight += DefaultWeight / 2;
8266 BTB->DefaultWeight -= DefaultWeight / 2;
8269 // If we're in the right place, emit the bit test header right now.
8270 if (CurMBB == SwitchMBB) {
8271 visitBitTestHeader(*BTB, SwitchMBB);
8272 BTB->Emitted = true;
8277 const Value *RHS, *LHS, *MHS;
8279 if (I->Low == I->High) {
8280 // Check Cond == I->Low.
8286 // Check I->Low <= Cond <= I->High.
8293 // The false weight is the sum of all unhandled cases.
8294 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8297 if (CurMBB == SwitchMBB)
8298 visitSwitchCase(CB, SwitchMBB);
8300 SwitchCases.push_back(CB);
8305 CurMBB = Fallthrough;
8309 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8310 CaseClusterIt First,
8311 CaseClusterIt Last) {
8312 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8313 if (X.Weight != CC.Weight)
8314 return X.Weight > CC.Weight;
8316 // Ties are broken by comparing the case value.
8317 return X.Low->getValue().slt(CC.Low->getValue());
8321 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8322 const SwitchWorkListItem &W,
8324 MachineBasicBlock *SwitchMBB) {
8325 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8326 "Clusters not sorted?");
8328 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8330 // Balance the tree based on branch weights to create a near-optimal (in terms
8331 // of search time given key frequency) binary search tree. See e.g. Kurt
8332 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8333 CaseClusterIt LastLeft = W.FirstCluster;
8334 CaseClusterIt FirstRight = W.LastCluster;
8335 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8336 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8338 // Move LastLeft and FirstRight towards each other from opposite directions to
8339 // find a partitioning of the clusters which balances the weight on both
8340 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8341 // taken to ensure 0-weight nodes are distributed evenly.
8343 while (LastLeft + 1 < FirstRight) {
8344 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8345 LeftWeight += (++LastLeft)->Weight;
8347 RightWeight += (--FirstRight)->Weight;
8352 // Our binary search tree differs from a typical BST in that ours can have up
8353 // to three values in each leaf. The pivot selection above doesn't take that
8354 // into account, which means the tree might require more nodes and be less
8355 // efficient. We compensate for this here.
8357 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8358 unsigned NumRight = W.LastCluster - FirstRight + 1;
8360 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8361 // If one side has less than 3 clusters, and the other has more than 3,
8362 // consider taking a cluster from the other side.
8364 if (NumLeft < NumRight) {
8365 // Consider moving the first cluster on the right to the left side.
8366 CaseCluster &CC = *FirstRight;
8367 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8368 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8369 if (LeftSideRank <= RightSideRank) {
8370 // Moving the cluster to the left does not demote it.
8376 assert(NumRight < NumLeft);
8377 // Consider moving the last element on the left to the right side.
8378 CaseCluster &CC = *LastLeft;
8379 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8380 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8381 if (RightSideRank <= LeftSideRank) {
8382 // Moving the cluster to the right does not demot it.
8392 assert(LastLeft + 1 == FirstRight);
8393 assert(LastLeft >= W.FirstCluster);
8394 assert(FirstRight <= W.LastCluster);
8396 // Use the first element on the right as pivot since we will make less-than
8397 // comparisons against it.
8398 CaseClusterIt PivotCluster = FirstRight;
8399 assert(PivotCluster > W.FirstCluster);
8400 assert(PivotCluster <= W.LastCluster);
8402 CaseClusterIt FirstLeft = W.FirstCluster;
8403 CaseClusterIt LastRight = W.LastCluster;
8405 const ConstantInt *Pivot = PivotCluster->Low;
8407 // New blocks will be inserted immediately after the current one.
8408 MachineFunction::iterator BBI(W.MBB);
8411 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8412 // we can branch to its destination directly if it's squeezed exactly in
8413 // between the known lower bound and Pivot - 1.
8414 MachineBasicBlock *LeftMBB;
8415 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8416 FirstLeft->Low == W.GE &&
8417 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8418 LeftMBB = FirstLeft->MBB;
8420 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8421 FuncInfo.MF->insert(BBI, LeftMBB);
8423 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8424 // Put Cond in a virtual register to make it available from the new blocks.
8425 ExportFromCurrentBlock(Cond);
8428 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8429 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8430 // directly if RHS.High equals the current upper bound.
8431 MachineBasicBlock *RightMBB;
8432 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8433 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8434 RightMBB = FirstRight->MBB;
8436 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8437 FuncInfo.MF->insert(BBI, RightMBB);
8439 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8440 // Put Cond in a virtual register to make it available from the new blocks.
8441 ExportFromCurrentBlock(Cond);
8444 // Create the CaseBlock record that will be used to lower the branch.
8445 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8446 LeftWeight, RightWeight);
8448 if (W.MBB == SwitchMBB)
8449 visitSwitchCase(CB, SwitchMBB);
8451 SwitchCases.push_back(CB);
8454 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8455 // Extract cases from the switch.
8456 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8457 CaseClusterVector Clusters;
8458 Clusters.reserve(SI.getNumCases());
8459 for (auto I : SI.cases()) {
8460 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8461 const ConstantInt *CaseVal = I.getCaseValue();
8463 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8464 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8467 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8469 // Cluster adjacent cases with the same destination. We do this at all
8470 // optimization levels because it's cheap to do and will make codegen faster
8471 // if there are many clusters.
8472 sortAndRangeify(Clusters);
8474 if (TM.getOptLevel() != CodeGenOpt::None) {
8475 // Replace an unreachable default with the most popular destination.
8476 // FIXME: Exploit unreachable default more aggressively.
8477 bool UnreachableDefault =
8478 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8479 if (UnreachableDefault && !Clusters.empty()) {
8480 DenseMap<const BasicBlock *, unsigned> Popularity;
8481 unsigned MaxPop = 0;
8482 const BasicBlock *MaxBB = nullptr;
8483 for (auto I : SI.cases()) {
8484 const BasicBlock *BB = I.getCaseSuccessor();
8485 if (++Popularity[BB] > MaxPop) {
8486 MaxPop = Popularity[BB];
8491 assert(MaxPop > 0 && MaxBB);
8492 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8494 // Remove cases that were pointing to the destination that is now the
8496 CaseClusterVector New;
8497 New.reserve(Clusters.size());
8498 for (CaseCluster &CC : Clusters) {
8499 if (CC.MBB != DefaultMBB)
8502 Clusters = std::move(New);
8506 // If there is only the default destination, jump there directly.
8507 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8508 if (Clusters.empty()) {
8509 SwitchMBB->addSuccessor(DefaultMBB);
8510 if (DefaultMBB != NextBlock(SwitchMBB)) {
8511 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8512 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8517 findJumpTables(Clusters, &SI, DefaultMBB);
8518 findBitTestClusters(Clusters, &SI);
8521 dbgs() << "Case clusters: ";
8522 for (const CaseCluster &C : Clusters) {
8523 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8524 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8526 C.Low->getValue().print(dbgs(), true);
8527 if (C.Low != C.High) {
8529 C.High->getValue().print(dbgs(), true);
8536 assert(!Clusters.empty());
8537 SwitchWorkList WorkList;
8538 CaseClusterIt First = Clusters.begin();
8539 CaseClusterIt Last = Clusters.end() - 1;
8540 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8541 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8543 while (!WorkList.empty()) {
8544 SwitchWorkListItem W = WorkList.back();
8545 WorkList.pop_back();
8546 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8548 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8549 // For optimized builds, lower large range as a balanced binary tree.
8550 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8554 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);