1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
202 ValueVT.bitsLT(PartEVT)) {
203 // For an FP value in an integer part, we need to truncate to the right
205 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
206 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
209 if (PartEVT.isInteger() && ValueVT.isInteger()) {
210 if (ValueVT.bitsLT(PartEVT)) {
211 // For a truncate, see if we have any information to
212 // indicate whether the truncated bits will always be
213 // zero or sign-extension.
214 if (AssertOp != ISD::DELETED_NODE)
215 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
216 DAG.getValueType(ValueVT));
217 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
219 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
223 // FP_ROUND's are always exact here.
224 if (ValueVT.bitsLT(Val.getValueType()))
226 ISD::FP_ROUND, DL, ValueVT, Val,
227 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
232 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
233 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
235 llvm_unreachable("Unknown mismatch!");
238 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
239 const Twine &ErrMsg) {
240 const Instruction *I = dyn_cast_or_null<Instruction>(V);
242 return Ctx.emitError(ErrMsg);
244 const char *AsmError = ", possible invalid constraint for vector type";
245 if (const CallInst *CI = dyn_cast<CallInst>(I))
246 if (isa<InlineAsm>(CI->getCalledValue()))
247 return Ctx.emitError(I, ErrMsg + AsmError);
249 return Ctx.emitError(I, ErrMsg);
252 /// getCopyFromPartsVector - Create a value that contains the specified legal
253 /// parts combined into the value they represent. If the parts combine to a
254 /// type larger then ValueVT then AssertOp can be used to specify whether the
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
256 /// ValueVT (ISD::AssertSext).
257 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
258 const SDValue *Parts, unsigned NumParts,
259 MVT PartVT, EVT ValueVT, const Value *V) {
260 assert(ValueVT.isVector() && "Not a vector value");
261 assert(NumParts > 0 && "No parts to assemble!");
262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
263 SDValue Val = Parts[0];
265 // Handle a multi-element vector.
269 unsigned NumIntermediates;
271 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
272 NumIntermediates, RegisterVT);
273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
274 NumParts = NumRegs; // Silence a compiler warning.
275 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
276 assert(RegisterVT.getSizeInBits() ==
277 Parts[0].getSimpleValueType().getSizeInBits() &&
278 "Part type sizes don't match!");
280 // Assemble the parts into intermediate operands.
281 SmallVector<SDValue, 8> Ops(NumIntermediates);
282 if (NumIntermediates == NumParts) {
283 // If the register was not expanded, truncate or copy the value,
285 for (unsigned i = 0; i != NumParts; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
287 PartVT, IntermediateVT, V);
288 } else if (NumParts > 0) {
289 // If the intermediate type was expanded, build the intermediate
290 // operands from the parts.
291 assert(NumParts % NumIntermediates == 0 &&
292 "Must expand into a divisible number of parts!");
293 unsigned Factor = NumParts / NumIntermediates;
294 for (unsigned i = 0; i != NumIntermediates; ++i)
295 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
296 PartVT, IntermediateVT, V);
299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
300 // intermediate operands.
301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
306 // There is now one part, held in Val. Correct it to match ValueVT.
307 EVT PartEVT = Val.getValueType();
309 if (PartEVT == ValueVT)
312 if (PartEVT.isVector()) {
313 // If the element type of the source/dest vectors are the same, but the
314 // parts vector has more elements than the value vector, then we have a
315 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
317 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
318 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
319 "Cannot narrow, it would be a lossy transformation");
321 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
322 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
325 // Vector/Vector bitcast.
326 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
327 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
329 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
330 "Cannot handle this kind of promotion");
331 // Promoted vector extract
332 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
336 // Trivial bitcast if the types are the same size and the destination
337 // vector type is legal.
338 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
339 TLI.isTypeLegal(ValueVT))
340 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
342 // Handle cases such as i8 -> <1 x i1>
343 if (ValueVT.getVectorNumElements() != 1) {
344 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
345 "non-trivial scalar-to-vector conversion");
346 return DAG.getUNDEF(ValueVT);
349 if (ValueVT.getVectorNumElements() == 1 &&
350 ValueVT.getVectorElementType() != PartEVT)
351 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
353 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
356 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
357 SDValue Val, SDValue *Parts, unsigned NumParts,
358 MVT PartVT, const Value *V);
360 /// getCopyToParts - Create a series of nodes that contain the specified value
361 /// split into legal parts. If the parts contain more bits than Val, then, for
362 /// integers, ExtendKind can be used to specify how to generate the extra bits.
363 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
364 SDValue Val, SDValue *Parts, unsigned NumParts,
365 MVT PartVT, const Value *V,
366 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
367 EVT ValueVT = Val.getValueType();
369 // Handle the vector case separately.
370 if (ValueVT.isVector())
371 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
373 unsigned PartBits = PartVT.getSizeInBits();
374 unsigned OrigNumParts = NumParts;
375 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
376 "Copying to an illegal type!");
381 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
382 EVT PartEVT = PartVT;
383 if (PartEVT == ValueVT) {
384 assert(NumParts == 1 && "No-op copy with multiple parts!");
389 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
390 // If the parts cover more bits than the value has, promote the value.
391 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
392 assert(NumParts == 1 && "Do not know what to promote to!");
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
395 if (ValueVT.isFloatingPoint()) {
396 // FP values need to be bitcast, then extended if they are being put
397 // into a larger container.
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
399 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 } else if (PartBits == ValueVT.getSizeInBits()) {
410 // Different types of the same size.
411 assert(NumParts == 1 && PartEVT != ValueVT);
412 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
413 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
414 // If the parts cover less bits than value has, truncate the value.
415 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
416 ValueVT.isInteger() &&
417 "Unknown mismatch!");
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
419 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
420 if (PartVT == MVT::x86mmx)
421 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 if (PartEVT != ValueVT)
431 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
432 "scalar-to-vector conversion failed");
438 // Expand the value into multiple parts.
439 if (NumParts & (NumParts - 1)) {
440 // The number of parts is not a power of 2. Split off and copy the tail.
441 assert(PartVT.isInteger() && ValueVT.isInteger() &&
442 "Do not know what to expand to!");
443 unsigned RoundParts = 1 << Log2_32(NumParts);
444 unsigned RoundBits = RoundParts * PartBits;
445 unsigned OddParts = NumParts - RoundParts;
446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
447 DAG.getIntPtrConstant(RoundBits, DL));
448 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
450 if (DAG.getDataLayout().isBigEndian())
451 // The odd parts were reversed by getCopyToParts - unreverse them.
452 std::reverse(Parts + RoundParts, Parts + NumParts);
454 NumParts = RoundParts;
455 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
456 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
459 // The number of parts is a power of 2. Repeatedly bisect the value using
461 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
462 EVT::getIntegerVT(*DAG.getContext(),
463 ValueVT.getSizeInBits()),
466 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
467 for (unsigned i = 0; i < NumParts; i += StepSize) {
468 unsigned ThisBits = StepSize * PartBits / 2;
469 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
470 SDValue &Part0 = Parts[i];
471 SDValue &Part1 = Parts[i+StepSize/2];
473 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
474 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
475 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
476 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
478 if (ThisBits == PartBits && ThisVT != PartVT) {
479 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
480 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
485 if (DAG.getDataLayout().isBigEndian())
486 std::reverse(Parts, Parts + OrigNumParts);
490 /// getCopyToPartsVector - Create a series of nodes that contain the specified
491 /// value split into legal parts.
492 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
493 SDValue Val, SDValue *Parts, unsigned NumParts,
494 MVT PartVT, const Value *V) {
495 EVT ValueVT = Val.getValueType();
496 assert(ValueVT.isVector() && "Not a vector");
497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
500 EVT PartEVT = PartVT;
501 if (PartEVT == ValueVT) {
503 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
504 // Bitconvert vector->vector case.
505 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
508 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
509 EVT ElementVT = PartVT.getVectorElementType();
510 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
512 SmallVector<SDValue, 16> Ops;
513 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
514 Ops.push_back(DAG.getNode(
515 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
516 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
518 for (unsigned i = ValueVT.getVectorNumElements(),
519 e = PartVT.getVectorNumElements(); i != e; ++i)
520 Ops.push_back(DAG.getUNDEF(ElementVT));
522 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
524 // FIXME: Use CONCAT for 2x -> 4x.
526 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType().bitsGE(
530 ValueVT.getVectorElementType()) &&
531 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
533 // Promoted vector extract
534 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Vector -> scalar conversion.
537 assert(ValueVT.getVectorNumElements() == 1 &&
538 "Only trivial vector-to-scalar conversions should get here!");
540 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
541 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
543 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
550 // Handle a multi-element vector.
553 unsigned NumIntermediates;
554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
556 NumIntermediates, RegisterVT);
557 unsigned NumElements = ValueVT.getVectorNumElements();
559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
560 NumParts = NumRegs; // Silence a compiler warning.
561 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
563 // Split the vector into intermediate operands.
564 SmallVector<SDValue, 8> Ops(NumIntermediates);
565 for (unsigned i = 0; i != NumIntermediates; ++i) {
566 if (IntermediateVT.isVector())
568 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
569 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
570 TLI.getVectorIdxTy(DAG.getDataLayout())));
572 Ops[i] = DAG.getNode(
573 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
574 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
577 // Split the intermediate operands into legal parts.
578 if (NumParts == NumIntermediates) {
579 // If the register was not expanded, promote or copy the value,
581 for (unsigned i = 0; i != NumParts; ++i)
582 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
583 } else if (NumParts > 0) {
584 // If the intermediate type was expanded, split each the value into
586 assert(NumIntermediates != 0 && "division by zero");
587 assert(NumParts % NumIntermediates == 0 &&
588 "Must expand into a divisible number of parts!");
589 unsigned Factor = NumParts / NumIntermediates;
590 for (unsigned i = 0; i != NumIntermediates; ++i)
591 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
595 RegsForValue::RegsForValue() {}
597 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
601 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
602 const DataLayout &DL, unsigned Reg, Type *Ty) {
603 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
605 for (EVT ValueVT : ValueVTs) {
606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
607 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
608 for (unsigned i = 0; i != NumRegs; ++i)
609 Regs.push_back(Reg + i);
610 RegVTs.push_back(RegisterVT);
615 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
616 /// this value and returns the result as a ValueVT value. This uses
617 /// Chain/Flag as the input and updates them for the output Chain/Flag.
618 /// If the Flag pointer is NULL, no flag is used.
619 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
620 FunctionLoweringInfo &FuncInfo,
622 SDValue &Chain, SDValue *Flag,
623 const Value *V) const {
624 // A Value with type {} or [0 x %t] needs no registers.
625 if (ValueVTs.empty())
628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
630 // Assemble the legal parts into the final values.
631 SmallVector<SDValue, 4> Values(ValueVTs.size());
632 SmallVector<SDValue, 8> Parts;
633 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
634 // Copy the legal parts from the registers.
635 EVT ValueVT = ValueVTs[Value];
636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
637 MVT RegisterVT = RegVTs[Value];
639 Parts.resize(NumRegs);
640 for (unsigned i = 0; i != NumRegs; ++i) {
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
646 *Flag = P.getValue(2);
649 Chain = P.getValue(1);
652 // If the source register was virtual and if we know something about it,
653 // add an assert node.
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
655 !RegisterVT.isInteger() || RegisterVT.isVector())
658 const FunctionLoweringInfo::LiveOutInfo *LOI =
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
663 unsigned RegSize = RegisterVT.getSizeInBits();
664 unsigned NumSignBits = LOI->NumSignBits;
665 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
667 if (NumZeroBits == RegSize) {
668 // The current value is a zero.
669 // Explicitly express that as it would be easier for
670 // optimizations to kick in.
671 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
675 // FIXME: We capture more information than the dag can represent. For
676 // now, just use the tightest assertzext/assertsext possible.
678 EVT FromVT(MVT::Other);
679 if (NumSignBits == RegSize)
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
681 else if (NumZeroBits >= RegSize-1)
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
683 else if (NumSignBits > RegSize-8)
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
685 else if (NumZeroBits >= RegSize-8)
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
687 else if (NumSignBits > RegSize-16)
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
689 else if (NumZeroBits >= RegSize-16)
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
691 else if (NumSignBits > RegSize-32)
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
693 else if (NumZeroBits >= RegSize-32)
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
698 // Add an assertion node.
699 assert(FromVT != MVT::Other);
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
701 RegisterVT, P, DAG.getValueType(FromVT));
704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
705 NumRegs, RegisterVT, ValueVT, V);
710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
713 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
714 /// specified value into the registers specified by this object. This uses
715 /// Chain/Flag as the input and updates them for the output Chain/Flag.
716 /// If the Flag pointer is NULL, no flag is used.
717 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
718 SDValue &Chain, SDValue *Flag, const Value *V,
719 ISD::NodeType PreferredExtendType) const {
720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
721 ISD::NodeType ExtendKind = PreferredExtendType;
723 // Get the list of the values's legal parts.
724 unsigned NumRegs = Regs.size();
725 SmallVector<SDValue, 8> Parts(NumRegs);
726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
727 EVT ValueVT = ValueVTs[Value];
728 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
729 MVT RegisterVT = RegVTs[Value];
731 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
732 ExtendKind = ISD::ZERO_EXTEND;
734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
735 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
739 // Copy the parts into the registers.
740 SmallVector<SDValue, 8> Chains(NumRegs);
741 for (unsigned i = 0; i != NumRegs; ++i) {
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
747 *Flag = Part.getValue(1);
750 Chains[i] = Part.getValue(0);
753 if (NumRegs == 1 || Flag)
754 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
755 // flagged to it. That is the CopyToReg nodes and the user are considered
756 // a single scheduling unit. If we create a TokenFactor and return it as
757 // chain, then the TokenFactor is both a predecessor (operand) of the
758 // user as well as a successor (the TF operands are flagged to the user).
759 // c1, f1 = CopyToReg
760 // c2, f2 = CopyToReg
761 // c3 = TokenFactor c1, c2
764 Chain = Chains[NumRegs-1];
766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
769 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
770 /// operand list. This adds the code marker and includes the number of
771 /// values added into it.
772 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
773 unsigned MatchingIdx, SDLoc dl,
775 std::vector<SDValue> &Ops) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
780 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
783 // Put the register class of the virtual registers in the flag word. That
784 // way, later passes can recompute register class constraints for inline
785 // assembly as well as normal instructions.
786 // Don't do this for tied operands that can use the regclass information
788 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
790 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
793 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
796 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
797 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
798 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
799 MVT RegisterVT = RegVTs[Value];
800 for (unsigned i = 0; i != NumRegs; ++i) {
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
803 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
805 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
806 // If we clobbered the stack pointer, MFI should know about it.
807 assert(DAG.getMachineFunction().getFrameInfo()->
808 hasOpaqueSPAdjustment());
814 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
815 const TargetLibraryInfo *li) {
819 DL = &DAG.getDataLayout();
820 Context = DAG.getContext();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
837 SDNodeOrder = LowestSDNodeOrder;
838 StatepointLowering.clear();
841 /// clearDanglingDebugInfo - Clear the dangling debug information
842 /// map. This function is separated from the clear so that debug
843 /// information that is dangling in a basic block can be properly
844 /// resolved in a different basic block. This allows the
845 /// SelectionDAG to resolve dangling debug information attached
847 void SelectionDAGBuilder::clearDanglingDebugInfo() {
848 DanglingDebugInfoMap.clear();
851 /// getRoot - Return the current virtual root of the Selection DAG,
852 /// flushing any PendingLoad items. This must be done before emitting
853 /// a store or any other node that may need to be ordered after any
854 /// prior load instructions.
856 SDValue SelectionDAGBuilder::getRoot() {
857 if (PendingLoads.empty())
858 return DAG.getRoot();
860 if (PendingLoads.size() == 1) {
861 SDValue Root = PendingLoads[0];
863 PendingLoads.clear();
867 // Otherwise, we have to make a token factor node.
868 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads.clear();
875 /// getControlRoot - Similar to getRoot, but instead of flushing all the
876 /// PendingLoad items, flush all the PendingExports items. It is necessary
877 /// to do this before emitting a terminator instruction.
879 SDValue SelectionDAGBuilder::getControlRoot() {
880 SDValue Root = DAG.getRoot();
882 if (PendingExports.empty())
885 // Turn all of the CopyToReg chains into one factored node.
886 if (Root.getOpcode() != ISD::EntryToken) {
887 unsigned i = 0, e = PendingExports.size();
888 for (; i != e; ++i) {
889 assert(PendingExports[i].getNode()->getNumOperands() > 1);
890 if (PendingExports[i].getNode()->getOperand(0) == Root)
891 break; // Don't add the root if we already indirectly depend on it.
895 PendingExports.push_back(Root);
898 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
900 PendingExports.clear();
905 void SelectionDAGBuilder::visit(const Instruction &I) {
906 // Set up outgoing PHI node register values before emitting the terminator.
907 if (isa<TerminatorInst>(&I))
908 HandlePHINodesInSuccessorBlocks(I.getParent());
914 visit(I.getOpcode(), I);
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
923 void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
927 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
931 default: llvm_unreachable("Unknown instruction type encountered!");
932 // Build the switch statement using the Instruction.def file.
933 #define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935 #include "llvm/IR/Instruction.def"
939 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940 // generate the debug data structures now that we've seen its definition.
941 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&
951 "Expected inlined-at fields to agree");
952 uint64_t Offset = DI->getOffset();
953 // A dbg.value for an alloca is always indirect.
954 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
957 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
959 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
960 IsIndirect, Offset, dl, DbgSDNodeOrder);
961 DAG.AddDbgValue(SDV, Val.getNode(), false);
964 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
965 DanglingDebugInfoMap[V] = DanglingDebugInfo();
969 /// getCopyFromRegs - If there was virtual register allocated for the value V
970 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
971 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
972 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
975 if (It != FuncInfo.ValueMap.end()) {
976 unsigned InReg = It->second;
977 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
978 DAG.getDataLayout(), InReg, Ty);
979 SDValue Chain = DAG.getEntryNode();
980 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
981 resolveDanglingDebugInfo(V, Result);
987 /// getValue - Return an SDValue for the given Value.
988 SDValue SelectionDAGBuilder::getValue(const Value *V) {
989 // If we already have an SDValue for this value, use it. It's important
990 // to do this first, so that we don't create a CopyFromReg if we already
991 // have a regular SDValue.
992 SDValue &N = NodeMap[V];
993 if (N.getNode()) return N;
995 // If there's a virtual register allocated and initialized for this
997 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
998 if (copyFromReg.getNode()) {
1002 // Otherwise create a new SDValue and remember it.
1003 SDValue Val = getValueImpl(V);
1005 resolveDanglingDebugInfo(V, Val);
1009 // Return true if SDValue exists for the given Value
1010 bool SelectionDAGBuilder::findValue(const Value *V) const {
1011 return (NodeMap.find(V) != NodeMap.end()) ||
1012 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1015 /// getNonRegisterValue - Return an SDValue for the given Value, but
1016 /// don't look in FuncInfo.ValueMap for a virtual register.
1017 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1018 // If we already have an SDValue for this value, use it.
1019 SDValue &N = NodeMap[V];
1021 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1022 // Remove the debug location from the node as the node is about to be used
1023 // in a location which may differ from the original debug location. This
1024 // is relevant to Constant and ConstantFP nodes because they can appear
1025 // as constant expressions inside PHI nodes.
1026 N->setDebugLoc(DebugLoc());
1031 // Otherwise create a new SDValue and remember it.
1032 SDValue Val = getValueImpl(V);
1034 resolveDanglingDebugInfo(V, Val);
1038 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1039 /// Create an SDValue for the given value.
1040 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1043 if (const Constant *C = dyn_cast<Constant>(V)) {
1044 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1046 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1047 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1049 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1050 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1052 if (isa<ConstantPointerNull>(C)) {
1053 unsigned AS = V->getType()->getPointerAddressSpace();
1054 return DAG.getConstant(0, getCurSDLoc(),
1055 TLI.getPointerTy(DAG.getDataLayout(), AS));
1058 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1059 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1061 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1062 return DAG.getUNDEF(VT);
1064 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1065 visit(CE->getOpcode(), *CE);
1066 SDValue N1 = NodeMap[V];
1067 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1071 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1072 SmallVector<SDValue, 4> Constants;
1073 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1075 SDNode *Val = getValue(*OI).getNode();
1076 // If the operand is an empty aggregate, there are no values.
1078 // Add each leaf value from the operand to the Constants list
1079 // to form a flattened list of all the values.
1080 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1081 Constants.push_back(SDValue(Val, i));
1084 return DAG.getMergeValues(Constants, getCurSDLoc());
1087 if (const ConstantDataSequential *CDS =
1088 dyn_cast<ConstantDataSequential>(C)) {
1089 SmallVector<SDValue, 4> Ops;
1090 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1091 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1092 // Add each leaf value from the operand to the Constants list
1093 // to form a flattened list of all the values.
1094 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1095 Ops.push_back(SDValue(Val, i));
1098 if (isa<ArrayType>(CDS->getType()))
1099 return DAG.getMergeValues(Ops, getCurSDLoc());
1100 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1104 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1105 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1106 "Unknown struct or array constant!");
1108 SmallVector<EVT, 4> ValueVTs;
1109 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1110 unsigned NumElts = ValueVTs.size();
1112 return SDValue(); // empty struct
1113 SmallVector<SDValue, 4> Constants(NumElts);
1114 for (unsigned i = 0; i != NumElts; ++i) {
1115 EVT EltVT = ValueVTs[i];
1116 if (isa<UndefValue>(C))
1117 Constants[i] = DAG.getUNDEF(EltVT);
1118 else if (EltVT.isFloatingPoint())
1119 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1121 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1124 return DAG.getMergeValues(Constants, getCurSDLoc());
1127 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1128 return DAG.getBlockAddress(BA, VT);
1130 VectorType *VecTy = cast<VectorType>(V->getType());
1131 unsigned NumElements = VecTy->getNumElements();
1133 // Now that we know the number and type of the elements, get that number of
1134 // elements into the Ops array based on what kind of constant it is.
1135 SmallVector<SDValue, 16> Ops;
1136 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1137 for (unsigned i = 0; i != NumElements; ++i)
1138 Ops.push_back(getValue(CV->getOperand(i)));
1140 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1142 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1145 if (EltVT.isFloatingPoint())
1146 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1148 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1149 Ops.assign(NumElements, Op);
1152 // Create a BUILD_VECTOR node.
1153 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1156 // If this is a static alloca, generate it as the frameindex instead of
1158 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1159 DenseMap<const AllocaInst*, int>::iterator SI =
1160 FuncInfo.StaticAllocaMap.find(AI);
1161 if (SI != FuncInfo.StaticAllocaMap.end())
1162 return DAG.getFrameIndex(SI->second,
1163 TLI.getPointerTy(DAG.getDataLayout()));
1166 // If this is an instruction which fast-isel has deferred, select it now.
1167 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1168 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1169 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1171 SDValue Chain = DAG.getEntryNode();
1172 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1175 llvm_unreachable("Can't get register for value!");
1178 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1179 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1180 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1181 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1182 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1183 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1184 if (IsMSVCCXX || IsCoreCLR)
1185 CatchPadMBB->setIsEHFuncletEntry();
1187 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1189 // Update machine-CFG edge.
1190 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1193 DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot());
1195 // If this is not a fall-through branch or optimizations are switched off,
1197 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1198 TM.getOptLevel() == CodeGenOpt::None)
1199 Chain = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
1200 DAG.getBasicBlock(NormalDestMBB));
1204 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1205 // Update machine-CFG edge.
1206 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1207 FuncInfo.MBB->addSuccessor(TargetMBB);
1209 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1210 bool IsSEH = isAsynchronousEHPersonality(Pers);
1212 // If this is not a fall-through branch or optimizations are switched off,
1214 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1215 TM.getOptLevel() == CodeGenOpt::None)
1216 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1217 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1221 // Figure out the funclet membership for the catchret's successor.
1222 // This will be used by the FuncletLayout pass to determine how to order the
1224 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
1225 const BasicBlock *SuccessorColor = EHInfo->CatchRetSuccessorColorMap[&I];
1226 assert(SuccessorColor && "No parent funclet for catchret!");
1227 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1228 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1230 // Create the terminator node.
1231 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1232 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1233 DAG.getBasicBlock(SuccessorColorMBB));
1237 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1238 llvm_unreachable("should never codegen catchendpads");
1241 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1242 // Don't emit any special code for the cleanuppad instruction. It just marks
1243 // the start of a funclet.
1244 FuncInfo.MBB->setIsEHFuncletEntry();
1245 FuncInfo.MBB->setIsCleanupFuncletEntry();
1248 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1249 /// many places it could ultimately go. In the IR, we have a single unwind
1250 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1251 /// This function skips over imaginary basic blocks that hold catchpad,
1252 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1253 /// basic block destinations. As those destinations may not be successors of
1254 /// EHPadBB, here we also calculate the edge probability to those destinations.
1255 /// The passed-in Prob is the edge probability to EHPadBB.
1256 static void findUnwindDestinations(
1257 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB,
1258 BranchProbability Prob,
1259 SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
1261 EHPersonality Personality =
1262 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1263 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1264 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1267 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1268 BasicBlock *NewEHPadBB = nullptr;
1269 if (isa<LandingPadInst>(Pad)) {
1270 // Stop on landingpads. They are not funclets.
1271 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1273 } else if (isa<CleanupPadInst>(Pad)) {
1274 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1276 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1277 UnwindDests.back().first->setIsEHFuncletEntry();
1279 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1280 // Add the catchpad handler to the possible destinations.
1281 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Prob);
1282 // In MSVC C++, catchblocks are funclets and need prologues.
1283 if (IsMSVCCXX || IsCoreCLR)
1284 UnwindDests.back().first->setIsEHFuncletEntry();
1285 NewEHPadBB = CPI->getUnwindDest();
1286 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad))
1287 NewEHPadBB = CEPI->getUnwindDest();
1288 else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad))
1289 NewEHPadBB = CEPI->getUnwindDest();
1293 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1294 if (BPI && NewEHPadBB)
1295 Prob *= BPI->getEdgeProbability(EHPadBB, NewEHPadBB);
1296 EHPadBB = NewEHPadBB;
1300 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1301 // Update successor info.
1302 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
1303 auto UnwindDest = I.getUnwindDest();
1304 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1305 BranchProbability UnwindDestProb =
1307 ? BPI->getEdgeProbability(FuncInfo.MBB->getBasicBlock(), UnwindDest)
1308 : BranchProbability::getZero();
1309 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestProb, UnwindDests);
1310 for (auto &UnwindDest : UnwindDests) {
1311 UnwindDest.first->setIsEHPad();
1312 addSuccessorWithProb(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1314 FuncInfo.MBB->normalizeSuccProbs();
1316 // Create the terminator node.
1318 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1322 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1323 report_fatal_error("visitCleanupEndPad not yet implemented!");
1326 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1327 report_fatal_error("visitTerminatePad not yet implemented!");
1330 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1332 auto &DL = DAG.getDataLayout();
1333 SDValue Chain = getControlRoot();
1334 SmallVector<ISD::OutputArg, 8> Outs;
1335 SmallVector<SDValue, 8> OutVals;
1337 if (!FuncInfo.CanLowerReturn) {
1338 unsigned DemoteReg = FuncInfo.DemoteRegister;
1339 const Function *F = I.getParent()->getParent();
1341 // Emit a store of the return value through the virtual register.
1342 // Leave Outs empty so that LowerReturn won't try to load return
1343 // registers the usual way.
1344 SmallVector<EVT, 1> PtrValueVTs;
1345 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1348 SDValue RetPtr = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
1349 DemoteReg, PtrValueVTs[0]);
1350 SDValue RetOp = getValue(I.getOperand(0));
1352 SmallVector<EVT, 4> ValueVTs;
1353 SmallVector<uint64_t, 4> Offsets;
1354 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1355 unsigned NumValues = ValueVTs.size();
1357 SmallVector<SDValue, 4> Chains(NumValues);
1358 for (unsigned i = 0; i != NumValues; ++i) {
1359 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1360 RetPtr.getValueType(), RetPtr,
1361 DAG.getIntPtrConstant(Offsets[i],
1364 DAG.getStore(Chain, getCurSDLoc(),
1365 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1366 // FIXME: better loc info would be nice.
1367 Add, MachinePointerInfo(), false, false, 0);
1370 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1371 MVT::Other, Chains);
1372 } else if (I.getNumOperands() != 0) {
1373 SmallVector<EVT, 4> ValueVTs;
1374 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1375 unsigned NumValues = ValueVTs.size();
1377 SDValue RetOp = getValue(I.getOperand(0));
1379 const Function *F = I.getParent()->getParent();
1381 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1382 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1384 ExtendKind = ISD::SIGN_EXTEND;
1385 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1387 ExtendKind = ISD::ZERO_EXTEND;
1389 LLVMContext &Context = F->getContext();
1390 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1393 for (unsigned j = 0; j != NumValues; ++j) {
1394 EVT VT = ValueVTs[j];
1396 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1397 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1399 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1400 MVT PartVT = TLI.getRegisterType(Context, VT);
1401 SmallVector<SDValue, 4> Parts(NumParts);
1402 getCopyToParts(DAG, getCurSDLoc(),
1403 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1404 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1406 // 'inreg' on function refers to return value
1407 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1411 // Propagate extension type if any
1412 if (ExtendKind == ISD::SIGN_EXTEND)
1414 else if (ExtendKind == ISD::ZERO_EXTEND)
1417 for (unsigned i = 0; i < NumParts; ++i) {
1418 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1419 VT, /*isfixed=*/true, 0, 0));
1420 OutVals.push_back(Parts[i]);
1426 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1427 CallingConv::ID CallConv =
1428 DAG.getMachineFunction().getFunction()->getCallingConv();
1429 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1430 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1432 // Verify that the target's LowerReturn behaved as expected.
1433 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1434 "LowerReturn didn't return a valid chain!");
1436 // Update the DAG with the new chain value resulting from return lowering.
1440 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1441 /// created for it, emit nodes to copy the value into the virtual
1443 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1445 if (V->getType()->isEmptyTy())
1448 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1449 if (VMI != FuncInfo.ValueMap.end()) {
1450 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1451 CopyValueToVirtualRegister(V, VMI->second);
1455 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1456 /// the current basic block, add it to ValueMap now so that we'll get a
1458 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1459 // No need to export constants.
1460 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1462 // Already exported?
1463 if (FuncInfo.isExportedInst(V)) return;
1465 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1466 CopyValueToVirtualRegister(V, Reg);
1469 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1470 const BasicBlock *FromBB) {
1471 // The operands of the setcc have to be in this block. We don't know
1472 // how to export them from some other block.
1473 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1474 // Can export from current BB.
1475 if (VI->getParent() == FromBB)
1478 // Is already exported, noop.
1479 return FuncInfo.isExportedInst(V);
1482 // If this is an argument, we can export it if the BB is the entry block or
1483 // if it is already exported.
1484 if (isa<Argument>(V)) {
1485 if (FromBB == &FromBB->getParent()->getEntryBlock())
1488 // Otherwise, can only export this if it is already exported.
1489 return FuncInfo.isExportedInst(V);
1492 // Otherwise, constants can always be exported.
1496 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1498 SelectionDAGBuilder::getEdgeProbability(const MachineBasicBlock *Src,
1499 const MachineBasicBlock *Dst) const {
1500 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1501 const BasicBlock *SrcBB = Src->getBasicBlock();
1502 const BasicBlock *DstBB = Dst->getBasicBlock();
1504 // If BPI is not available, set the default probability as 1 / N, where N is
1505 // the number of successors.
1506 auto SuccSize = std::max<uint32_t>(
1507 std::distance(succ_begin(SrcBB), succ_end(SrcBB)), 1);
1508 return BranchProbability(1, SuccSize);
1510 return BPI->getEdgeProbability(SrcBB, DstBB);
1513 void SelectionDAGBuilder::addSuccessorWithProb(MachineBasicBlock *Src,
1514 MachineBasicBlock *Dst,
1515 BranchProbability Prob) {
1517 Src->addSuccessorWithoutProb(Dst);
1519 if (Prob.isUnknown())
1520 Prob = getEdgeProbability(Src, Dst);
1521 Src->addSuccessor(Dst, Prob);
1525 static bool InBlock(const Value *V, const BasicBlock *BB) {
1526 if (const Instruction *I = dyn_cast<Instruction>(V))
1527 return I->getParent() == BB;
1531 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1532 /// This function emits a branch and is used at the leaves of an OR or an
1533 /// AND operator tree.
1536 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1537 MachineBasicBlock *TBB,
1538 MachineBasicBlock *FBB,
1539 MachineBasicBlock *CurBB,
1540 MachineBasicBlock *SwitchBB,
1541 BranchProbability TProb,
1542 BranchProbability FProb) {
1543 const BasicBlock *BB = CurBB->getBasicBlock();
1545 // If the leaf of the tree is a comparison, merge the condition into
1547 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1548 // The operands of the cmp have to be in this block. We don't know
1549 // how to export them from some other block. If this is the first block
1550 // of the sequence, no exporting is needed.
1551 if (CurBB == SwitchBB ||
1552 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1553 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1554 ISD::CondCode Condition;
1555 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1556 Condition = getICmpCondCode(IC->getPredicate());
1558 const FCmpInst *FC = cast<FCmpInst>(Cond);
1559 Condition = getFCmpCondCode(FC->getPredicate());
1560 if (TM.Options.NoNaNsFPMath)
1561 Condition = getFCmpCodeWithoutNaN(Condition);
1564 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1565 TBB, FBB, CurBB, TProb, FProb);
1566 SwitchCases.push_back(CB);
1571 // Create a CaseBlock record representing this branch.
1572 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1573 nullptr, TBB, FBB, CurBB, TProb, FProb);
1574 SwitchCases.push_back(CB);
1577 /// FindMergedConditions - If Cond is an expression like
1578 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1579 MachineBasicBlock *TBB,
1580 MachineBasicBlock *FBB,
1581 MachineBasicBlock *CurBB,
1582 MachineBasicBlock *SwitchBB,
1583 Instruction::BinaryOps Opc,
1584 BranchProbability TProb,
1585 BranchProbability FProb) {
1586 // If this node is not part of the or/and tree, emit it as a branch.
1587 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1588 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1589 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1590 BOp->getParent() != CurBB->getBasicBlock() ||
1591 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1592 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1593 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1598 // Create TmpBB after CurBB.
1599 MachineFunction::iterator BBI(CurBB);
1600 MachineFunction &MF = DAG.getMachineFunction();
1601 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1602 CurBB->getParent()->insert(++BBI, TmpBB);
1604 if (Opc == Instruction::Or) {
1605 // Codegen X | Y as:
1614 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1615 // The requirement is that
1616 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1617 // = TrueProb for original BB.
1618 // Assuming the original probabilities are A and B, one choice is to set
1619 // BB1's probabilities to A/2 and A/2+B, and set TmpBB's probabilities to
1620 // A/(1+B) and 2B/(1+B). This choice assumes that
1621 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1622 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1623 // TmpBB, but the math is more complicated.
1625 auto NewTrueProb = TProb / 2;
1626 auto NewFalseProb = TProb / 2 + FProb;
1627 // Emit the LHS condition.
1628 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1629 NewTrueProb, NewFalseProb);
1631 // Normalize A/2 and B to get A/(1+B) and 2B/(1+B).
1632 SmallVector<BranchProbability, 2> Probs{TProb / 2, FProb};
1633 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1634 // Emit the RHS condition into TmpBB.
1635 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1636 Probs[0], Probs[1]);
1638 assert(Opc == Instruction::And && "Unknown merge op!");
1639 // Codegen X & Y as:
1647 // This requires creation of TmpBB after CurBB.
1649 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1650 // The requirement is that
1651 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1652 // = FalseProb for original BB.
1653 // Assuming the original probabilities are A and B, one choice is to set
1654 // BB1's probabilities to A+B/2 and B/2, and set TmpBB's probabilities to
1655 // 2A/(1+A) and B/(1+A). This choice assumes that FalseProb for BB1 ==
1656 // TrueProb for BB1 * FalseProb for TmpBB.
1658 auto NewTrueProb = TProb + FProb / 2;
1659 auto NewFalseProb = FProb / 2;
1660 // Emit the LHS condition.
1661 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1662 NewTrueProb, NewFalseProb);
1664 // Normalize A and B/2 to get 2A/(1+A) and B/(1+A).
1665 SmallVector<BranchProbability, 2> Probs{TProb, FProb / 2};
1666 BranchProbability::normalizeProbabilities(Probs.begin(), Probs.end());
1667 // Emit the RHS condition into TmpBB.
1668 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1669 Probs[0], Probs[1]);
1673 /// If the set of cases should be emitted as a series of branches, return true.
1674 /// If we should emit this as a bunch of and/or'd together conditions, return
1677 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1678 if (Cases.size() != 2) return true;
1680 // If this is two comparisons of the same values or'd or and'd together, they
1681 // will get folded into a single comparison, so don't emit two blocks.
1682 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1683 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1684 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1685 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1689 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1690 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1691 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1692 Cases[0].CC == Cases[1].CC &&
1693 isa<Constant>(Cases[0].CmpRHS) &&
1694 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1695 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1697 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1704 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1705 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1707 // Update machine-CFG edges.
1708 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1710 if (I.isUnconditional()) {
1711 // Update machine-CFG edges.
1712 BrMBB->addSuccessor(Succ0MBB);
1714 // If this is not a fall-through branch or optimizations are switched off,
1716 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1717 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1718 MVT::Other, getControlRoot(),
1719 DAG.getBasicBlock(Succ0MBB)));
1724 // If this condition is one of the special cases we handle, do special stuff
1726 const Value *CondVal = I.getCondition();
1727 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1729 // If this is a series of conditions that are or'd or and'd together, emit
1730 // this as a sequence of branches instead of setcc's with and/or operations.
1731 // As long as jumps are not expensive, this should improve performance.
1732 // For example, instead of something like:
1745 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1746 Instruction::BinaryOps Opcode = BOp->getOpcode();
1747 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1748 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1749 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1750 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1752 getEdgeProbability(BrMBB, Succ0MBB),
1753 getEdgeProbability(BrMBB, Succ1MBB));
1754 // If the compares in later blocks need to use values not currently
1755 // exported from this block, export them now. This block should always
1756 // be the first entry.
1757 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1759 // Allow some cases to be rejected.
1760 if (ShouldEmitAsBranches(SwitchCases)) {
1761 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1762 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1763 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1766 // Emit the branch for this block.
1767 visitSwitchCase(SwitchCases[0], BrMBB);
1768 SwitchCases.erase(SwitchCases.begin());
1772 // Okay, we decided not to do this, remove any inserted MBB's and clear
1774 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1775 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1777 SwitchCases.clear();
1781 // Create a CaseBlock record representing this branch.
1782 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1783 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1785 // Use visitSwitchCase to actually insert the fast branch sequence for this
1787 visitSwitchCase(CB, BrMBB);
1790 /// visitSwitchCase - Emits the necessary code to represent a single node in
1791 /// the binary search tree resulting from lowering a switch instruction.
1792 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1793 MachineBasicBlock *SwitchBB) {
1795 SDValue CondLHS = getValue(CB.CmpLHS);
1796 SDLoc dl = getCurSDLoc();
1798 // Build the setcc now.
1800 // Fold "(X == true)" to X and "(X == false)" to !X to
1801 // handle common cases produced by branch lowering.
1802 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1803 CB.CC == ISD::SETEQ)
1805 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1806 CB.CC == ISD::SETEQ) {
1807 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1808 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1810 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1812 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1814 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1815 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1817 SDValue CmpOp = getValue(CB.CmpMHS);
1818 EVT VT = CmpOp.getValueType();
1820 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1821 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1824 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1825 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1826 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1827 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1831 // Update successor info
1832 addSuccessorWithProb(SwitchBB, CB.TrueBB, CB.TrueProb);
1833 // TrueBB and FalseBB are always different unless the incoming IR is
1834 // degenerate. This only happens when running llc on weird IR.
1835 if (CB.TrueBB != CB.FalseBB)
1836 addSuccessorWithProb(SwitchBB, CB.FalseBB, CB.FalseProb);
1837 SwitchBB->normalizeSuccProbs();
1839 // If the lhs block is the next block, invert the condition so that we can
1840 // fall through to the lhs instead of the rhs block.
1841 if (CB.TrueBB == NextBlock(SwitchBB)) {
1842 std::swap(CB.TrueBB, CB.FalseBB);
1843 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1844 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1847 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1848 MVT::Other, getControlRoot(), Cond,
1849 DAG.getBasicBlock(CB.TrueBB));
1851 // Insert the false branch. Do this even if it's a fall through branch,
1852 // this makes it easier to do DAG optimizations which require inverting
1853 // the branch condition.
1854 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1855 DAG.getBasicBlock(CB.FalseBB));
1857 DAG.setRoot(BrCond);
1860 /// visitJumpTable - Emit JumpTable node in the current MBB
1861 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1862 // Emit the code for the jump table
1863 assert(JT.Reg != -1U && "Should lower JT Header first!");
1864 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1865 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1867 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1868 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1869 MVT::Other, Index.getValue(1),
1871 DAG.setRoot(BrJumpTable);
1874 /// visitJumpTableHeader - This function emits necessary code to produce index
1875 /// in the JumpTable from switch case.
1876 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1877 JumpTableHeader &JTH,
1878 MachineBasicBlock *SwitchBB) {
1879 SDLoc dl = getCurSDLoc();
1881 // Subtract the lowest switch case value from the value being switched on and
1882 // conditional branch to default mbb if the result is greater than the
1883 // difference between smallest and largest cases.
1884 SDValue SwitchOp = getValue(JTH.SValue);
1885 EVT VT = SwitchOp.getValueType();
1886 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1887 DAG.getConstant(JTH.First, dl, VT));
1889 // The SDNode we just created, which holds the value being switched on minus
1890 // the smallest case value, needs to be copied to a virtual register so it
1891 // can be used as an index into the jump table in a subsequent basic block.
1892 // This value may be smaller or larger than the target's pointer type, and
1893 // therefore require extension or truncating.
1894 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1895 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1897 unsigned JumpTableReg =
1898 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1899 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1900 JumpTableReg, SwitchOp);
1901 JT.Reg = JumpTableReg;
1903 // Emit the range check for the jump table, and branch to the default block
1904 // for the switch statement if the value being switched on exceeds the largest
1905 // case in the switch.
1906 SDValue CMP = DAG.getSetCC(
1907 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1908 Sub.getValueType()),
1909 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1911 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1912 MVT::Other, CopyTo, CMP,
1913 DAG.getBasicBlock(JT.Default));
1915 // Avoid emitting unnecessary branches to the next block.
1916 if (JT.MBB != NextBlock(SwitchBB))
1917 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1918 DAG.getBasicBlock(JT.MBB));
1920 DAG.setRoot(BrCond);
1923 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1924 /// tail spliced into a stack protector check success bb.
1926 /// For a high level explanation of how this fits into the stack protector
1927 /// generation see the comment on the declaration of class
1928 /// StackProtectorDescriptor.
1929 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1930 MachineBasicBlock *ParentBB) {
1932 // First create the loads to the guard/stack slot for the comparison.
1933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1934 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1936 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1937 int FI = MFI->getStackProtectorIndex();
1939 const Value *IRGuard = SPD.getGuard();
1940 SDValue GuardPtr = getValue(IRGuard);
1941 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1943 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1946 SDLoc dl = getCurSDLoc();
1948 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1949 // guard value from the virtual register holding the value. Otherwise, emit a
1950 // volatile load to retrieve the stack guard value.
1951 unsigned GuardReg = SPD.getGuardReg();
1953 if (GuardReg && TLI.useLoadStackGuardNode())
1954 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1957 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1958 GuardPtr, MachinePointerInfo(IRGuard, 0),
1959 true, false, false, Align);
1961 SDValue StackSlot = DAG.getLoad(
1962 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1963 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1964 false, false, Align);
1966 // Perform the comparison via a subtract/getsetcc.
1967 EVT VT = Guard.getValueType();
1968 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1970 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1972 Sub.getValueType()),
1973 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1975 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1976 // branch to failure MBB.
1977 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1978 MVT::Other, StackSlot.getOperand(0),
1979 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1980 // Otherwise branch to success MBB.
1981 SDValue Br = DAG.getNode(ISD::BR, dl,
1983 DAG.getBasicBlock(SPD.getSuccessMBB()));
1988 /// Codegen the failure basic block for a stack protector check.
1990 /// A failure stack protector machine basic block consists simply of a call to
1991 /// __stack_chk_fail().
1993 /// For a high level explanation of how this fits into the stack protector
1994 /// generation see the comment on the declaration of class
1995 /// StackProtectorDescriptor.
1997 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2000 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2001 None, false, getCurSDLoc(), false, false).second;
2005 /// visitBitTestHeader - This function emits necessary code to produce value
2006 /// suitable for "bit tests"
2007 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2008 MachineBasicBlock *SwitchBB) {
2009 SDLoc dl = getCurSDLoc();
2011 // Subtract the minimum value
2012 SDValue SwitchOp = getValue(B.SValue);
2013 EVT VT = SwitchOp.getValueType();
2014 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2015 DAG.getConstant(B.First, dl, VT));
2018 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2019 SDValue RangeCmp = DAG.getSetCC(
2020 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2021 Sub.getValueType()),
2022 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2024 // Determine the type of the test operands.
2025 bool UsePtrType = false;
2026 if (!TLI.isTypeLegal(VT))
2029 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2030 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2031 // Switch table case range are encoded into series of masks.
2032 // Just use pointer type, it's guaranteed to fit.
2038 VT = TLI.getPointerTy(DAG.getDataLayout());
2039 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2042 B.RegVT = VT.getSimpleVT();
2043 B.Reg = FuncInfo.CreateReg(B.RegVT);
2044 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2046 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2048 addSuccessorWithProb(SwitchBB, B.Default, B.DefaultProb);
2049 addSuccessorWithProb(SwitchBB, MBB, B.Prob);
2050 SwitchBB->normalizeSuccProbs();
2052 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2053 MVT::Other, CopyTo, RangeCmp,
2054 DAG.getBasicBlock(B.Default));
2056 // Avoid emitting unnecessary branches to the next block.
2057 if (MBB != NextBlock(SwitchBB))
2058 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2059 DAG.getBasicBlock(MBB));
2061 DAG.setRoot(BrRange);
2064 /// visitBitTestCase - this function produces one "bit test"
2065 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2066 MachineBasicBlock* NextMBB,
2067 BranchProbability BranchProbToNext,
2070 MachineBasicBlock *SwitchBB) {
2071 SDLoc dl = getCurSDLoc();
2073 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2075 unsigned PopCount = countPopulation(B.Mask);
2076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2077 if (PopCount == 1) {
2078 // Testing for a single bit; just compare the shift count with what it
2079 // would need to be to shift a 1 bit in that position.
2081 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2082 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2084 } else if (PopCount == BB.Range) {
2085 // There is only one zero bit in the range, test for it directly.
2087 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2088 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2091 // Make desired shift
2092 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2093 DAG.getConstant(1, dl, VT), ShiftOp);
2095 // Emit bit tests and jumps
2096 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2097 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2099 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2100 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2103 // The branch probability from SwitchBB to B.TargetBB is B.ExtraProb.
2104 addSuccessorWithProb(SwitchBB, B.TargetBB, B.ExtraProb);
2105 // The branch probability from SwitchBB to NextMBB is BranchProbToNext.
2106 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
2107 // It is not guaranteed that the sum of B.ExtraProb and BranchProbToNext is
2108 // one as they are relative probabilities (and thus work more like weights),
2109 // and hence we need to normalize them to let the sum of them become one.
2110 SwitchBB->normalizeSuccProbs();
2112 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2113 MVT::Other, getControlRoot(),
2114 Cmp, DAG.getBasicBlock(B.TargetBB));
2116 // Avoid emitting unnecessary branches to the next block.
2117 if (NextMBB != NextBlock(SwitchBB))
2118 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2119 DAG.getBasicBlock(NextMBB));
2124 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2125 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2127 // Retrieve successors. Look through artificial IR level blocks like catchpads
2128 // and catchendpads for successors.
2129 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2130 const BasicBlock *EHPadBB = I.getSuccessor(1);
2132 const Value *Callee(I.getCalledValue());
2133 const Function *Fn = dyn_cast<Function>(Callee);
2134 if (isa<InlineAsm>(Callee))
2136 else if (Fn && Fn->isIntrinsic()) {
2137 switch (Fn->getIntrinsicID()) {
2139 llvm_unreachable("Cannot invoke this intrinsic");
2140 case Intrinsic::donothing:
2141 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2143 case Intrinsic::experimental_patchpoint_void:
2144 case Intrinsic::experimental_patchpoint_i64:
2145 visitPatchpoint(&I, EHPadBB);
2147 case Intrinsic::experimental_gc_statepoint:
2148 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2152 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2154 // If the value of the invoke is used outside of its defining block, make it
2155 // available as a virtual register.
2156 // We already took care of the exported value for the statepoint instruction
2157 // during call to the LowerStatepoint.
2158 if (!isStatepoint(I)) {
2159 CopyToExportRegsIfNeeded(&I);
2162 SmallVector<std::pair<MachineBasicBlock *, BranchProbability>, 1> UnwindDests;
2163 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2164 BranchProbability EHPadBBProb =
2165 BPI ? BPI->getEdgeProbability(InvokeMBB->getBasicBlock(), EHPadBB)
2166 : BranchProbability::getZero();
2167 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBProb, UnwindDests);
2169 // Update successor info.
2170 addSuccessorWithProb(InvokeMBB, Return);
2171 for (auto &UnwindDest : UnwindDests) {
2172 UnwindDest.first->setIsEHPad();
2173 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
2175 InvokeMBB->normalizeSuccProbs();
2177 // Drop into normal successor.
2178 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2179 MVT::Other, getControlRoot(),
2180 DAG.getBasicBlock(Return)));
2183 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2184 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2187 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2188 assert(FuncInfo.MBB->isEHPad() &&
2189 "Call to landingpad not in landing pad!");
2191 MachineBasicBlock *MBB = FuncInfo.MBB;
2192 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2193 AddLandingPadInfo(LP, MMI, MBB);
2195 // If there aren't registers to copy the values into (e.g., during SjLj
2196 // exceptions), then don't bother to create these DAG nodes.
2197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2198 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2199 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2200 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2203 SmallVector<EVT, 2> ValueVTs;
2204 SDLoc dl = getCurSDLoc();
2205 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2206 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2208 // Get the two live-in registers as SDValues. The physregs have already been
2209 // copied into virtual registers.
2211 if (FuncInfo.ExceptionPointerVirtReg) {
2212 Ops[0] = DAG.getZExtOrTrunc(
2213 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2214 FuncInfo.ExceptionPointerVirtReg,
2215 TLI.getPointerTy(DAG.getDataLayout())),
2218 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2220 Ops[1] = DAG.getZExtOrTrunc(
2221 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2222 FuncInfo.ExceptionSelectorVirtReg,
2223 TLI.getPointerTy(DAG.getDataLayout())),
2227 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2228 DAG.getVTList(ValueVTs), Ops);
2232 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2234 for (const CaseCluster &CC : Clusters)
2235 assert(CC.Low == CC.High && "Input clusters must be single-case");
2238 std::sort(Clusters.begin(), Clusters.end(),
2239 [](const CaseCluster &a, const CaseCluster &b) {
2240 return a.Low->getValue().slt(b.Low->getValue());
2243 // Merge adjacent clusters with the same destination.
2244 const unsigned N = Clusters.size();
2245 unsigned DstIndex = 0;
2246 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2247 CaseCluster &CC = Clusters[SrcIndex];
2248 const ConstantInt *CaseVal = CC.Low;
2249 MachineBasicBlock *Succ = CC.MBB;
2251 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2252 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2253 // If this case has the same successor and is a neighbour, merge it into
2254 // the previous cluster.
2255 Clusters[DstIndex - 1].High = CaseVal;
2256 Clusters[DstIndex - 1].Prob += CC.Prob;
2258 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2259 sizeof(Clusters[SrcIndex]));
2262 Clusters.resize(DstIndex);
2265 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2266 MachineBasicBlock *Last) {
2268 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2269 if (JTCases[i].first.HeaderBB == First)
2270 JTCases[i].first.HeaderBB = Last;
2272 // Update BitTestCases.
2273 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2274 if (BitTestCases[i].Parent == First)
2275 BitTestCases[i].Parent = Last;
2278 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2279 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2281 // Update machine-CFG edges with unique successors.
2282 SmallSet<BasicBlock*, 32> Done;
2283 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2284 BasicBlock *BB = I.getSuccessor(i);
2285 bool Inserted = Done.insert(BB).second;
2289 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2290 addSuccessorWithProb(IndirectBrMBB, Succ);
2293 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2294 MVT::Other, getControlRoot(),
2295 getValue(I.getAddress())));
2298 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2299 if (DAG.getTarget().Options.TrapUnreachable)
2301 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2304 void SelectionDAGBuilder::visitFSub(const User &I) {
2305 // -0.0 - X --> fneg
2306 Type *Ty = I.getType();
2307 if (isa<Constant>(I.getOperand(0)) &&
2308 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2309 SDValue Op2 = getValue(I.getOperand(1));
2310 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2311 Op2.getValueType(), Op2));
2315 visitBinary(I, ISD::FSUB);
2318 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2319 SDValue Op1 = getValue(I.getOperand(0));
2320 SDValue Op2 = getValue(I.getOperand(1));
2327 if (const OverflowingBinaryOperator *OFBinOp =
2328 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2329 nuw = OFBinOp->hasNoUnsignedWrap();
2330 nsw = OFBinOp->hasNoSignedWrap();
2332 if (const PossiblyExactOperator *ExactOp =
2333 dyn_cast<const PossiblyExactOperator>(&I))
2334 exact = ExactOp->isExact();
2335 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2336 FMF = FPOp->getFastMathFlags();
2339 Flags.setExact(exact);
2340 Flags.setNoSignedWrap(nsw);
2341 Flags.setNoUnsignedWrap(nuw);
2342 if (EnableFMFInDAG) {
2343 Flags.setAllowReciprocal(FMF.allowReciprocal());
2344 Flags.setNoInfs(FMF.noInfs());
2345 Flags.setNoNaNs(FMF.noNaNs());
2346 Flags.setNoSignedZeros(FMF.noSignedZeros());
2347 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2349 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2351 setValue(&I, BinNodeValue);
2354 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2355 SDValue Op1 = getValue(I.getOperand(0));
2356 SDValue Op2 = getValue(I.getOperand(1));
2358 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2359 Op2.getValueType(), DAG.getDataLayout());
2361 // Coerce the shift amount to the right type if we can.
2362 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2363 unsigned ShiftSize = ShiftTy.getSizeInBits();
2364 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2365 SDLoc DL = getCurSDLoc();
2367 // If the operand is smaller than the shift count type, promote it.
2368 if (ShiftSize > Op2Size)
2369 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2371 // If the operand is larger than the shift count type but the shift
2372 // count type has enough bits to represent any shift value, truncate
2373 // it now. This is a common case and it exposes the truncate to
2374 // optimization early.
2375 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2376 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2377 // Otherwise we'll need to temporarily settle for some other convenient
2378 // type. Type legalization will make adjustments once the shiftee is split.
2380 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2387 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2389 if (const OverflowingBinaryOperator *OFBinOp =
2390 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2391 nuw = OFBinOp->hasNoUnsignedWrap();
2392 nsw = OFBinOp->hasNoSignedWrap();
2394 if (const PossiblyExactOperator *ExactOp =
2395 dyn_cast<const PossiblyExactOperator>(&I))
2396 exact = ExactOp->isExact();
2399 Flags.setExact(exact);
2400 Flags.setNoSignedWrap(nsw);
2401 Flags.setNoUnsignedWrap(nuw);
2402 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2407 void SelectionDAGBuilder::visitSDiv(const User &I) {
2408 SDValue Op1 = getValue(I.getOperand(0));
2409 SDValue Op2 = getValue(I.getOperand(1));
2412 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2413 cast<PossiblyExactOperator>(&I)->isExact());
2414 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2418 void SelectionDAGBuilder::visitICmp(const User &I) {
2419 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2420 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2421 predicate = IC->getPredicate();
2422 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2423 predicate = ICmpInst::Predicate(IC->getPredicate());
2424 SDValue Op1 = getValue(I.getOperand(0));
2425 SDValue Op2 = getValue(I.getOperand(1));
2426 ISD::CondCode Opcode = getICmpCondCode(predicate);
2428 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2430 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2433 void SelectionDAGBuilder::visitFCmp(const User &I) {
2434 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2435 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2436 predicate = FC->getPredicate();
2437 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2438 predicate = FCmpInst::Predicate(FC->getPredicate());
2439 SDValue Op1 = getValue(I.getOperand(0));
2440 SDValue Op2 = getValue(I.getOperand(1));
2441 ISD::CondCode Condition = getFCmpCondCode(predicate);
2443 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2444 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2445 // further optimization, but currently FMF is only applicable to binary nodes.
2446 if (TM.Options.NoNaNsFPMath)
2447 Condition = getFCmpCodeWithoutNaN(Condition);
2448 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2450 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2453 void SelectionDAGBuilder::visitSelect(const User &I) {
2454 SmallVector<EVT, 4> ValueVTs;
2455 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2457 unsigned NumValues = ValueVTs.size();
2458 if (NumValues == 0) return;
2460 SmallVector<SDValue, 4> Values(NumValues);
2461 SDValue Cond = getValue(I.getOperand(0));
2462 SDValue LHSVal = getValue(I.getOperand(1));
2463 SDValue RHSVal = getValue(I.getOperand(2));
2464 auto BaseOps = {Cond};
2465 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2466 ISD::VSELECT : ISD::SELECT;
2468 // Min/max matching is only viable if all output VTs are the same.
2469 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2470 EVT VT = ValueVTs[0];
2471 LLVMContext &Ctx = *DAG.getContext();
2472 auto &TLI = DAG.getTargetLoweringInfo();
2473 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2474 VT = TLI.getTypeToTransformTo(Ctx, VT);
2477 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2478 ISD::NodeType Opc = ISD::DELETED_NODE;
2479 switch (SPR.Flavor) {
2480 case SPF_UMAX: Opc = ISD::UMAX; break;
2481 case SPF_UMIN: Opc = ISD::UMIN; break;
2482 case SPF_SMAX: Opc = ISD::SMAX; break;
2483 case SPF_SMIN: Opc = ISD::SMIN; break;
2485 switch (SPR.NaNBehavior) {
2486 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2487 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2488 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2489 case SPNB_RETURNS_ANY:
2490 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2496 switch (SPR.NaNBehavior) {
2497 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2498 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2499 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2500 case SPNB_RETURNS_ANY:
2501 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2509 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2510 // If the underlying comparison instruction is used by any other instruction,
2511 // the consumed instructions won't be destroyed, so it is not profitable
2512 // to convert to a min/max.
2513 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2515 LHSVal = getValue(LHS);
2516 RHSVal = getValue(RHS);
2521 for (unsigned i = 0; i != NumValues; ++i) {
2522 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2523 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2524 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2525 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2526 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2530 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2531 DAG.getVTList(ValueVTs), Values));
2534 void SelectionDAGBuilder::visitTrunc(const User &I) {
2535 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2536 SDValue N = getValue(I.getOperand(0));
2537 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2539 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2542 void SelectionDAGBuilder::visitZExt(const User &I) {
2543 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2544 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2545 SDValue N = getValue(I.getOperand(0));
2546 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2548 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2551 void SelectionDAGBuilder::visitSExt(const User &I) {
2552 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2553 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2554 SDValue N = getValue(I.getOperand(0));
2555 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2557 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2560 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2561 // FPTrunc is never a no-op cast, no need to check
2562 SDValue N = getValue(I.getOperand(0));
2563 SDLoc dl = getCurSDLoc();
2564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2565 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2566 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2567 DAG.getTargetConstant(
2568 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2571 void SelectionDAGBuilder::visitFPExt(const User &I) {
2572 // FPExt is never a no-op cast, no need to check
2573 SDValue N = getValue(I.getOperand(0));
2574 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2576 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2579 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2580 // FPToUI is never a no-op cast, no need to check
2581 SDValue N = getValue(I.getOperand(0));
2582 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2584 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2587 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2588 // FPToSI is never a no-op cast, no need to check
2589 SDValue N = getValue(I.getOperand(0));
2590 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2592 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2595 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2596 // UIToFP is never a no-op cast, no need to check
2597 SDValue N = getValue(I.getOperand(0));
2598 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2600 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2603 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2604 // SIToFP is never a no-op cast, no need to check
2605 SDValue N = getValue(I.getOperand(0));
2606 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2608 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2611 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2612 // What to do depends on the size of the integer and the size of the pointer.
2613 // We can either truncate, zero extend, or no-op, accordingly.
2614 SDValue N = getValue(I.getOperand(0));
2615 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2617 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2620 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2621 // What to do depends on the size of the integer and the size of the pointer.
2622 // We can either truncate, zero extend, or no-op, accordingly.
2623 SDValue N = getValue(I.getOperand(0));
2624 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2626 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2629 void SelectionDAGBuilder::visitBitCast(const User &I) {
2630 SDValue N = getValue(I.getOperand(0));
2631 SDLoc dl = getCurSDLoc();
2632 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2635 // BitCast assures us that source and destination are the same size so this is
2636 // either a BITCAST or a no-op.
2637 if (DestVT != N.getValueType())
2638 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2639 DestVT, N)); // convert types.
2640 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2641 // might fold any kind of constant expression to an integer constant and that
2642 // is not what we are looking for. Only regcognize a bitcast of a genuine
2643 // constant integer as an opaque constant.
2644 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2645 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2648 setValue(&I, N); // noop cast.
2651 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2652 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2653 const Value *SV = I.getOperand(0);
2654 SDValue N = getValue(SV);
2655 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2657 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2658 unsigned DestAS = I.getType()->getPointerAddressSpace();
2660 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2661 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2666 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2668 SDValue InVec = getValue(I.getOperand(0));
2669 SDValue InVal = getValue(I.getOperand(1));
2670 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2671 TLI.getVectorIdxTy(DAG.getDataLayout()));
2672 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2673 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2674 InVec, InVal, InIdx));
2677 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2678 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2679 SDValue InVec = getValue(I.getOperand(0));
2680 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2681 TLI.getVectorIdxTy(DAG.getDataLayout()));
2682 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2683 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2687 // Utility for visitShuffleVector - Return true if every element in Mask,
2688 // beginning from position Pos and ending in Pos+Size, falls within the
2689 // specified sequential range [L, L+Pos). or is undef.
2690 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2691 unsigned Pos, unsigned Size, int Low) {
2692 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2693 if (Mask[i] >= 0 && Mask[i] != Low)
2698 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2699 SDValue Src1 = getValue(I.getOperand(0));
2700 SDValue Src2 = getValue(I.getOperand(1));
2702 SmallVector<int, 8> Mask;
2703 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2704 unsigned MaskNumElts = Mask.size();
2706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2707 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2708 EVT SrcVT = Src1.getValueType();
2709 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2711 if (SrcNumElts == MaskNumElts) {
2712 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2717 // Normalize the shuffle vector since mask and vector length don't match.
2718 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2719 // Mask is longer than the source vectors and is a multiple of the source
2720 // vectors. We can use concatenate vector to make the mask and vectors
2722 if (SrcNumElts*2 == MaskNumElts) {
2723 // First check for Src1 in low and Src2 in high
2724 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2725 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2726 // The shuffle is concatenating two vectors together.
2727 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2731 // Then check for Src2 in low and Src1 in high
2732 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2733 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2734 // The shuffle is concatenating two vectors together.
2735 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2741 // Pad both vectors with undefs to make them the same length as the mask.
2742 unsigned NumConcat = MaskNumElts / SrcNumElts;
2743 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2744 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2745 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2747 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2748 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2752 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2753 getCurSDLoc(), VT, MOps1);
2754 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2755 getCurSDLoc(), VT, MOps2);
2757 // Readjust mask for new input vector length.
2758 SmallVector<int, 8> MappedOps;
2759 for (unsigned i = 0; i != MaskNumElts; ++i) {
2761 if (Idx >= (int)SrcNumElts)
2762 Idx -= SrcNumElts - MaskNumElts;
2763 MappedOps.push_back(Idx);
2766 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2771 if (SrcNumElts > MaskNumElts) {
2772 // Analyze the access pattern of the vector to see if we can extract
2773 // two subvectors and do the shuffle. The analysis is done by calculating
2774 // the range of elements the mask access on both vectors.
2775 int MinRange[2] = { static_cast<int>(SrcNumElts),
2776 static_cast<int>(SrcNumElts)};
2777 int MaxRange[2] = {-1, -1};
2779 for (unsigned i = 0; i != MaskNumElts; ++i) {
2785 if (Idx >= (int)SrcNumElts) {
2789 if (Idx > MaxRange[Input])
2790 MaxRange[Input] = Idx;
2791 if (Idx < MinRange[Input])
2792 MinRange[Input] = Idx;
2795 // Check if the access is smaller than the vector size and can we find
2796 // a reasonable extract index.
2797 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2799 int StartIdx[2]; // StartIdx to extract from
2800 for (unsigned Input = 0; Input < 2; ++Input) {
2801 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2802 RangeUse[Input] = 0; // Unused
2803 StartIdx[Input] = 0;
2807 // Find a good start index that is a multiple of the mask length. Then
2808 // see if the rest of the elements are in range.
2809 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2810 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2811 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2812 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2815 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2816 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2819 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2820 // Extract appropriate subvector and generate a vector shuffle
2821 for (unsigned Input = 0; Input < 2; ++Input) {
2822 SDValue &Src = Input == 0 ? Src1 : Src2;
2823 if (RangeUse[Input] == 0)
2824 Src = DAG.getUNDEF(VT);
2826 SDLoc dl = getCurSDLoc();
2828 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2829 DAG.getConstant(StartIdx[Input], dl,
2830 TLI.getVectorIdxTy(DAG.getDataLayout())));
2834 // Calculate new mask.
2835 SmallVector<int, 8> MappedOps;
2836 for (unsigned i = 0; i != MaskNumElts; ++i) {
2839 if (Idx < (int)SrcNumElts)
2842 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2844 MappedOps.push_back(Idx);
2847 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2853 // We can't use either concat vectors or extract subvectors so fall back to
2854 // replacing the shuffle with extract and build vector.
2855 // to insert and build vector.
2856 EVT EltVT = VT.getVectorElementType();
2857 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2858 SDLoc dl = getCurSDLoc();
2859 SmallVector<SDValue,8> Ops;
2860 for (unsigned i = 0; i != MaskNumElts; ++i) {
2865 Res = DAG.getUNDEF(EltVT);
2867 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2868 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2870 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2871 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2877 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2880 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2881 const Value *Op0 = I.getOperand(0);
2882 const Value *Op1 = I.getOperand(1);
2883 Type *AggTy = I.getType();
2884 Type *ValTy = Op1->getType();
2885 bool IntoUndef = isa<UndefValue>(Op0);
2886 bool FromUndef = isa<UndefValue>(Op1);
2888 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2891 SmallVector<EVT, 4> AggValueVTs;
2892 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2893 SmallVector<EVT, 4> ValValueVTs;
2894 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2896 unsigned NumAggValues = AggValueVTs.size();
2897 unsigned NumValValues = ValValueVTs.size();
2898 SmallVector<SDValue, 4> Values(NumAggValues);
2900 // Ignore an insertvalue that produces an empty object
2901 if (!NumAggValues) {
2902 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2906 SDValue Agg = getValue(Op0);
2908 // Copy the beginning value(s) from the original aggregate.
2909 for (; i != LinearIndex; ++i)
2910 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2911 SDValue(Agg.getNode(), Agg.getResNo() + i);
2912 // Copy values from the inserted value(s).
2914 SDValue Val = getValue(Op1);
2915 for (; i != LinearIndex + NumValValues; ++i)
2916 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2917 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2919 // Copy remaining value(s) from the original aggregate.
2920 for (; i != NumAggValues; ++i)
2921 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2922 SDValue(Agg.getNode(), Agg.getResNo() + i);
2924 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2925 DAG.getVTList(AggValueVTs), Values));
2928 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2929 const Value *Op0 = I.getOperand(0);
2930 Type *AggTy = Op0->getType();
2931 Type *ValTy = I.getType();
2932 bool OutOfUndef = isa<UndefValue>(Op0);
2934 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2937 SmallVector<EVT, 4> ValValueVTs;
2938 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2940 unsigned NumValValues = ValValueVTs.size();
2942 // Ignore a extractvalue that produces an empty object
2943 if (!NumValValues) {
2944 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2948 SmallVector<SDValue, 4> Values(NumValValues);
2950 SDValue Agg = getValue(Op0);
2951 // Copy out the selected value(s).
2952 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2953 Values[i - LinearIndex] =
2955 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2956 SDValue(Agg.getNode(), Agg.getResNo() + i);
2958 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2959 DAG.getVTList(ValValueVTs), Values));
2962 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2963 Value *Op0 = I.getOperand(0);
2964 // Note that the pointer operand may be a vector of pointers. Take the scalar
2965 // element which holds a pointer.
2966 Type *Ty = Op0->getType()->getScalarType();
2967 unsigned AS = Ty->getPointerAddressSpace();
2968 SDValue N = getValue(Op0);
2969 SDLoc dl = getCurSDLoc();
2971 // Normalize Vector GEP - all scalar operands should be converted to the
2973 unsigned VectorWidth = I.getType()->isVectorTy() ?
2974 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2976 if (VectorWidth && !N.getValueType().isVector()) {
2977 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2978 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2979 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2981 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2983 const Value *Idx = *OI;
2984 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2985 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2988 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2989 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2990 DAG.getConstant(Offset, dl, N.getValueType()));
2993 Ty = StTy->getElementType(Field);
2995 Ty = cast<SequentialType>(Ty)->getElementType();
2997 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2998 unsigned PtrSize = PtrTy.getSizeInBits();
2999 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3001 // If this is a scalar constant or a splat vector of constants,
3002 // handle it quickly.
3003 const auto *CI = dyn_cast<ConstantInt>(Idx);
3004 if (!CI && isa<ConstantDataVector>(Idx) &&
3005 cast<ConstantDataVector>(Idx)->getSplatValue())
3006 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3011 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3012 SDValue OffsVal = VectorWidth ?
3013 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3014 DAG.getConstant(Offs, dl, PtrTy);
3015 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
3019 // N = N + Idx * ElementSize;
3020 SDValue IdxN = getValue(Idx);
3022 if (!IdxN.getValueType().isVector() && VectorWidth) {
3023 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3024 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3025 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3027 // If the index is smaller or larger than intptr_t, truncate or extend
3029 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3031 // If this is a multiply by a power of two, turn it into a shl
3032 // immediately. This is a very common case.
3033 if (ElementSize != 1) {
3034 if (ElementSize.isPowerOf2()) {
3035 unsigned Amt = ElementSize.logBase2();
3036 IdxN = DAG.getNode(ISD::SHL, dl,
3037 N.getValueType(), IdxN,
3038 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3040 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3041 IdxN = DAG.getNode(ISD::MUL, dl,
3042 N.getValueType(), IdxN, Scale);
3046 N = DAG.getNode(ISD::ADD, dl,
3047 N.getValueType(), N, IdxN);
3054 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3055 // If this is a fixed sized alloca in the entry block of the function,
3056 // allocate it statically on the stack.
3057 if (FuncInfo.StaticAllocaMap.count(&I))
3058 return; // getValue will auto-populate this.
3060 SDLoc dl = getCurSDLoc();
3061 Type *Ty = I.getAllocatedType();
3062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3063 auto &DL = DAG.getDataLayout();
3064 uint64_t TySize = DL.getTypeAllocSize(Ty);
3066 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3068 SDValue AllocSize = getValue(I.getArraySize());
3070 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3071 if (AllocSize.getValueType() != IntPtr)
3072 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3074 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3076 DAG.getConstant(TySize, dl, IntPtr));
3078 // Handle alignment. If the requested alignment is less than or equal to
3079 // the stack alignment, ignore it. If the size is greater than or equal to
3080 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3081 unsigned StackAlign =
3082 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3083 if (Align <= StackAlign)
3086 // Round the size of the allocation up to the stack alignment size
3087 // by add SA-1 to the size.
3088 AllocSize = DAG.getNode(ISD::ADD, dl,
3089 AllocSize.getValueType(), AllocSize,
3090 DAG.getIntPtrConstant(StackAlign - 1, dl));
3092 // Mask out the low bits for alignment purposes.
3093 AllocSize = DAG.getNode(ISD::AND, dl,
3094 AllocSize.getValueType(), AllocSize,
3095 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3098 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3099 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3100 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3102 DAG.setRoot(DSA.getValue(1));
3104 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3107 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3109 return visitAtomicLoad(I);
3111 const Value *SV = I.getOperand(0);
3112 SDValue Ptr = getValue(SV);
3114 Type *Ty = I.getType();
3116 bool isVolatile = I.isVolatile();
3117 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3119 // The IR notion of invariant_load only guarantees that all *non-faulting*
3120 // invariant loads result in the same value. The MI notion of invariant load
3121 // guarantees that the load can be legally moved to any location within its
3122 // containing function. The MI notion of invariant_load is stronger than the
3123 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3124 // with a guarantee that the location being loaded from is dereferenceable
3125 // throughout the function's lifetime.
3127 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3128 isDereferenceablePointer(SV, DAG.getDataLayout());
3129 unsigned Alignment = I.getAlignment();
3132 I.getAAMetadata(AAInfo);
3133 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3136 SmallVector<EVT, 4> ValueVTs;
3137 SmallVector<uint64_t, 4> Offsets;
3138 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3139 unsigned NumValues = ValueVTs.size();
3144 bool ConstantMemory = false;
3145 if (isVolatile || NumValues > MaxParallelChains)
3146 // Serialize volatile loads with other side effects.
3148 else if (AA->pointsToConstantMemory(MemoryLocation(
3149 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3150 // Do not serialize (non-volatile) loads of constant memory with anything.
3151 Root = DAG.getEntryNode();
3152 ConstantMemory = true;
3154 // Do not serialize non-volatile loads against each other.
3155 Root = DAG.getRoot();
3158 SDLoc dl = getCurSDLoc();
3161 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3163 SmallVector<SDValue, 4> Values(NumValues);
3164 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3165 EVT PtrVT = Ptr.getValueType();
3166 unsigned ChainI = 0;
3167 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3168 // Serializing loads here may result in excessive register pressure, and
3169 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3170 // could recover a bit by hoisting nodes upward in the chain by recognizing
3171 // they are side-effect free or do not alias. The optimizer should really
3172 // avoid this case by converting large object/array copies to llvm.memcpy
3173 // (MaxParallelChains should always remain as failsafe).
3174 if (ChainI == MaxParallelChains) {
3175 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3176 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3177 makeArrayRef(Chains.data(), ChainI));
3181 SDValue A = DAG.getNode(ISD::ADD, dl,
3183 DAG.getConstant(Offsets[i], dl, PtrVT));
3184 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3185 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3186 isNonTemporal, isInvariant, Alignment, AAInfo,
3190 Chains[ChainI] = L.getValue(1);
3193 if (!ConstantMemory) {
3194 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3195 makeArrayRef(Chains.data(), ChainI));
3199 PendingLoads.push_back(Chain);
3202 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3203 DAG.getVTList(ValueVTs), Values));
3206 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3208 return visitAtomicStore(I);
3210 const Value *SrcV = I.getOperand(0);
3211 const Value *PtrV = I.getOperand(1);
3213 SmallVector<EVT, 4> ValueVTs;
3214 SmallVector<uint64_t, 4> Offsets;
3215 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3216 SrcV->getType(), ValueVTs, &Offsets);
3217 unsigned NumValues = ValueVTs.size();
3221 // Get the lowered operands. Note that we do this after
3222 // checking if NumResults is zero, because with zero results
3223 // the operands won't have values in the map.
3224 SDValue Src = getValue(SrcV);
3225 SDValue Ptr = getValue(PtrV);
3227 SDValue Root = getRoot();
3228 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3229 EVT PtrVT = Ptr.getValueType();
3230 bool isVolatile = I.isVolatile();
3231 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3232 unsigned Alignment = I.getAlignment();
3233 SDLoc dl = getCurSDLoc();
3236 I.getAAMetadata(AAInfo);
3238 unsigned ChainI = 0;
3239 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3240 // See visitLoad comments.
3241 if (ChainI == MaxParallelChains) {
3242 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3243 makeArrayRef(Chains.data(), ChainI));
3247 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3248 DAG.getConstant(Offsets[i], dl, PtrVT));
3249 SDValue St = DAG.getStore(Root, dl,
3250 SDValue(Src.getNode(), Src.getResNo() + i),
3251 Add, MachinePointerInfo(PtrV, Offsets[i]),
3252 isVolatile, isNonTemporal, Alignment, AAInfo);
3253 Chains[ChainI] = St;
3256 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3257 makeArrayRef(Chains.data(), ChainI));
3258 DAG.setRoot(StoreNode);
3261 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3262 SDLoc sdl = getCurSDLoc();
3264 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3265 Value *PtrOperand = I.getArgOperand(1);
3266 SDValue Ptr = getValue(PtrOperand);
3267 SDValue Src0 = getValue(I.getArgOperand(0));
3268 SDValue Mask = getValue(I.getArgOperand(3));
3269 EVT VT = Src0.getValueType();
3270 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3272 Alignment = DAG.getEVTAlignment(VT);
3275 I.getAAMetadata(AAInfo);
3277 MachineMemOperand *MMO =
3278 DAG.getMachineFunction().
3279 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3280 MachineMemOperand::MOStore, VT.getStoreSize(),
3282 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3284 DAG.setRoot(StoreNode);
3285 setValue(&I, StoreNode);
3288 // Get a uniform base for the Gather/Scatter intrinsic.
3289 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3290 // We try to represent it as a base pointer + vector of indices.
3291 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3292 // The first operand of the GEP may be a single pointer or a vector of pointers
3294 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3296 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3297 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3299 // When the first GEP operand is a single pointer - it is the uniform base we
3300 // are looking for. If first operand of the GEP is a splat vector - we
3301 // extract the spalt value and use it as a uniform base.
3302 // In all other cases the function returns 'false'.
3304 static bool getUniformBase(const Value *& Ptr, SDValue& Base, SDValue& Index,
3305 SelectionDAGBuilder* SDB) {
3307 SelectionDAG& DAG = SDB->DAG;
3308 LLVMContext &Context = *DAG.getContext();
3310 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3311 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3312 if (!GEP || GEP->getNumOperands() > 2)
3315 const Value *GEPPtr = GEP->getPointerOperand();
3316 if (!GEPPtr->getType()->isVectorTy())
3318 else if (!(Ptr = getSplatValue(GEPPtr)))
3321 Value *IndexVal = GEP->getOperand(1);
3323 // The operands of the GEP may be defined in another basic block.
3324 // In this case we'll not find nodes for the operands.
3325 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3328 Base = SDB->getValue(Ptr);
3329 Index = SDB->getValue(IndexVal);
3331 // Suppress sign extension.
3332 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3333 if (SDB->findValue(Sext->getOperand(0))) {
3334 IndexVal = Sext->getOperand(0);
3335 Index = SDB->getValue(IndexVal);
3338 if (!Index.getValueType().isVector()) {
3339 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3340 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3341 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3342 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3347 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3348 SDLoc sdl = getCurSDLoc();
3350 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3351 const Value *Ptr = I.getArgOperand(1);
3352 SDValue Src0 = getValue(I.getArgOperand(0));
3353 SDValue Mask = getValue(I.getArgOperand(3));
3354 EVT VT = Src0.getValueType();
3355 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3357 Alignment = DAG.getEVTAlignment(VT);
3358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3361 I.getAAMetadata(AAInfo);
3365 const Value *BasePtr = Ptr;
3366 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3368 const Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3369 MachineMemOperand *MMO = DAG.getMachineFunction().
3370 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3371 MachineMemOperand::MOStore, VT.getStoreSize(),
3374 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3375 Index = getValue(Ptr);
3377 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3378 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3380 DAG.setRoot(Scatter);
3381 setValue(&I, Scatter);
3384 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3385 SDLoc sdl = getCurSDLoc();
3387 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3388 Value *PtrOperand = I.getArgOperand(0);
3389 SDValue Ptr = getValue(PtrOperand);
3390 SDValue Src0 = getValue(I.getArgOperand(3));
3391 SDValue Mask = getValue(I.getArgOperand(2));
3393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3394 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3395 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3397 Alignment = DAG.getEVTAlignment(VT);
3400 I.getAAMetadata(AAInfo);
3401 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3403 SDValue InChain = DAG.getRoot();
3404 if (AA->pointsToConstantMemory(MemoryLocation(
3405 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3407 // Do not serialize (non-volatile) loads of constant memory with anything.
3408 InChain = DAG.getEntryNode();
3411 MachineMemOperand *MMO =
3412 DAG.getMachineFunction().
3413 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3414 MachineMemOperand::MOLoad, VT.getStoreSize(),
3415 Alignment, AAInfo, Ranges);
3417 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3419 SDValue OutChain = Load.getValue(1);
3420 DAG.setRoot(OutChain);
3424 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3425 SDLoc sdl = getCurSDLoc();
3427 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3428 const Value *Ptr = I.getArgOperand(0);
3429 SDValue Src0 = getValue(I.getArgOperand(3));
3430 SDValue Mask = getValue(I.getArgOperand(2));
3432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3433 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3434 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3436 Alignment = DAG.getEVTAlignment(VT);
3439 I.getAAMetadata(AAInfo);
3440 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3442 SDValue Root = DAG.getRoot();
3445 const Value *BasePtr = Ptr;
3446 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3447 bool ConstantMemory = false;
3449 AA->pointsToConstantMemory(MemoryLocation(
3450 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3452 // Do not serialize (non-volatile) loads of constant memory with anything.
3453 Root = DAG.getEntryNode();
3454 ConstantMemory = true;
3457 MachineMemOperand *MMO =
3458 DAG.getMachineFunction().
3459 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3460 MachineMemOperand::MOLoad, VT.getStoreSize(),
3461 Alignment, AAInfo, Ranges);
3464 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3465 Index = getValue(Ptr);
3467 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3468 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3471 SDValue OutChain = Gather.getValue(1);
3472 if (!ConstantMemory)
3473 PendingLoads.push_back(OutChain);
3474 setValue(&I, Gather);
3477 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3478 SDLoc dl = getCurSDLoc();
3479 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3480 AtomicOrdering FailureOrder = I.getFailureOrdering();
3481 SynchronizationScope Scope = I.getSynchScope();
3483 SDValue InChain = getRoot();
3485 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3486 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3487 SDValue L = DAG.getAtomicCmpSwap(
3488 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3489 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3490 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3491 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3493 SDValue OutChain = L.getValue(2);
3496 DAG.setRoot(OutChain);
3499 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3500 SDLoc dl = getCurSDLoc();
3502 switch (I.getOperation()) {
3503 default: llvm_unreachable("Unknown atomicrmw operation");
3504 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3505 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3506 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3507 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3508 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3509 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3510 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3511 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3512 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3513 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3514 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3516 AtomicOrdering Order = I.getOrdering();
3517 SynchronizationScope Scope = I.getSynchScope();
3519 SDValue InChain = getRoot();
3522 DAG.getAtomic(NT, dl,
3523 getValue(I.getValOperand()).getSimpleValueType(),
3525 getValue(I.getPointerOperand()),
3526 getValue(I.getValOperand()),
3527 I.getPointerOperand(),
3528 /* Alignment=*/ 0, Order, Scope);
3530 SDValue OutChain = L.getValue(1);
3533 DAG.setRoot(OutChain);
3536 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3537 SDLoc dl = getCurSDLoc();
3538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3541 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3542 TLI.getPointerTy(DAG.getDataLayout()));
3543 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3544 TLI.getPointerTy(DAG.getDataLayout()));
3545 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3548 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3549 SDLoc dl = getCurSDLoc();
3550 AtomicOrdering Order = I.getOrdering();
3551 SynchronizationScope Scope = I.getSynchScope();
3553 SDValue InChain = getRoot();
3555 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3556 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3558 if (I.getAlignment() < VT.getSizeInBits() / 8)
3559 report_fatal_error("Cannot generate unaligned atomic load");
3561 MachineMemOperand *MMO =
3562 DAG.getMachineFunction().
3563 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3564 MachineMemOperand::MOVolatile |
3565 MachineMemOperand::MOLoad,
3567 I.getAlignment() ? I.getAlignment() :
3568 DAG.getEVTAlignment(VT));
3570 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3572 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3573 getValue(I.getPointerOperand()), MMO,
3576 SDValue OutChain = L.getValue(1);
3579 DAG.setRoot(OutChain);
3582 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3583 SDLoc dl = getCurSDLoc();
3585 AtomicOrdering Order = I.getOrdering();
3586 SynchronizationScope Scope = I.getSynchScope();
3588 SDValue InChain = getRoot();
3590 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3592 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3594 if (I.getAlignment() < VT.getSizeInBits() / 8)
3595 report_fatal_error("Cannot generate unaligned atomic store");
3598 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3600 getValue(I.getPointerOperand()),
3601 getValue(I.getValueOperand()),
3602 I.getPointerOperand(), I.getAlignment(),
3605 DAG.setRoot(OutChain);
3608 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3610 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3611 unsigned Intrinsic) {
3612 bool HasChain = !I.doesNotAccessMemory();
3613 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3615 // Build the operand list.
3616 SmallVector<SDValue, 8> Ops;
3617 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3619 // We don't need to serialize loads against other loads.
3620 Ops.push_back(DAG.getRoot());
3622 Ops.push_back(getRoot());
3626 // Info is set by getTgtMemInstrinsic
3627 TargetLowering::IntrinsicInfo Info;
3628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3629 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3631 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3632 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3633 Info.opc == ISD::INTRINSIC_W_CHAIN)
3634 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3635 TLI.getPointerTy(DAG.getDataLayout())));
3637 // Add all operands of the call to the operand list.
3638 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3639 SDValue Op = getValue(I.getArgOperand(i));
3643 SmallVector<EVT, 4> ValueVTs;
3644 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3647 ValueVTs.push_back(MVT::Other);
3649 SDVTList VTs = DAG.getVTList(ValueVTs);
3653 if (IsTgtIntrinsic) {
3654 // This is target intrinsic that touches memory
3655 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3656 VTs, Ops, Info.memVT,
3657 MachinePointerInfo(Info.ptrVal, Info.offset),
3658 Info.align, Info.vol,
3659 Info.readMem, Info.writeMem, Info.size);
3660 } else if (!HasChain) {
3661 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3662 } else if (!I.getType()->isVoidTy()) {
3663 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3665 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3669 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3671 PendingLoads.push_back(Chain);
3676 if (!I.getType()->isVoidTy()) {
3677 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3678 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3679 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3682 setValue(&I, Result);
3686 /// GetSignificand - Get the significand and build it into a floating-point
3687 /// number with exponent of 1:
3689 /// Op = (Op & 0x007fffff) | 0x3f800000;
3691 /// where Op is the hexadecimal representation of floating point value.
3693 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3694 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3695 DAG.getConstant(0x007fffff, dl, MVT::i32));
3696 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3697 DAG.getConstant(0x3f800000, dl, MVT::i32));
3698 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3701 /// GetExponent - Get the exponent:
3703 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3705 /// where Op is the hexadecimal representation of floating point value.
3707 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3709 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3710 DAG.getConstant(0x7f800000, dl, MVT::i32));
3711 SDValue t1 = DAG.getNode(
3712 ISD::SRL, dl, MVT::i32, t0,
3713 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3714 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3715 DAG.getConstant(127, dl, MVT::i32));
3716 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3719 /// getF32Constant - Get 32-bit floating point constant.
3721 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3722 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3726 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3727 SelectionDAG &DAG) {
3728 // TODO: What fast-math-flags should be set on the floating-point nodes?
3730 // IntegerPartOfX = ((int32_t)(t0);
3731 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3733 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3734 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3735 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3737 // IntegerPartOfX <<= 23;
3738 IntegerPartOfX = DAG.getNode(
3739 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3740 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3741 DAG.getDataLayout())));
3743 SDValue TwoToFractionalPartOfX;
3744 if (LimitFloatPrecision <= 6) {
3745 // For floating-point precision of 6:
3747 // TwoToFractionalPartOfX =
3749 // (0.735607626f + 0.252464424f * x) * x;
3751 // error 0.0144103317, which is 6 bits
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0x3e814304, dl));
3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3f3c50c8, dl));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x3f7f5e7e, dl));
3759 } else if (LimitFloatPrecision <= 12) {
3760 // For floating-point precision of 12:
3762 // TwoToFractionalPartOfX =
3765 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3767 // error 0.000107046256, which is 13 to 14 bits
3768 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3769 getF32Constant(DAG, 0x3da235e3, dl));
3770 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3771 getF32Constant(DAG, 0x3e65b8f3, dl));
3772 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3773 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3774 getF32Constant(DAG, 0x3f324b07, dl));
3775 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3776 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3777 getF32Constant(DAG, 0x3f7ff8fd, dl));
3778 } else { // LimitFloatPrecision <= 18
3779 // For floating-point precision of 18:
3781 // TwoToFractionalPartOfX =
3785 // (0.554906021e-1f +
3786 // (0.961591928e-2f +
3787 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3788 // error 2.47208000*10^(-7), which is better than 18 bits
3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3790 getF32Constant(DAG, 0x3924b03e, dl));
3791 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3792 getF32Constant(DAG, 0x3ab24b87, dl));
3793 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3794 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3795 getF32Constant(DAG, 0x3c1d8c17, dl));
3796 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3797 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3798 getF32Constant(DAG, 0x3d634a1d, dl));
3799 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3800 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3801 getF32Constant(DAG, 0x3e75fe14, dl));
3802 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3803 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3804 getF32Constant(DAG, 0x3f317234, dl));
3805 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3806 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3807 getF32Constant(DAG, 0x3f800000, dl));
3810 // Add the exponent into the result in integer domain.
3811 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3812 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3813 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3816 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3817 /// limited-precision mode.
3818 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3819 const TargetLowering &TLI) {
3820 if (Op.getValueType() == MVT::f32 &&
3821 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3823 // Put the exponent in the right bit position for later addition to the
3826 // #define LOG2OFe 1.4426950f
3827 // t0 = Op * LOG2OFe
3829 // TODO: What fast-math-flags should be set here?
3830 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3831 getF32Constant(DAG, 0x3fb8aa3b, dl));
3832 return getLimitedPrecisionExp2(t0, dl, DAG);
3835 // No special expansion.
3836 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3839 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3840 /// limited-precision mode.
3841 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3842 const TargetLowering &TLI) {
3844 // TODO: What fast-math-flags should be set on the floating-point nodes?
3846 if (Op.getValueType() == MVT::f32 &&
3847 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3848 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3850 // Scale the exponent by log(2) [0.69314718f].
3851 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3852 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3853 getF32Constant(DAG, 0x3f317218, dl));
3855 // Get the significand and build it into a floating-point number with
3857 SDValue X = GetSignificand(DAG, Op1, dl);
3859 SDValue LogOfMantissa;
3860 if (LimitFloatPrecision <= 6) {
3861 // For floating-point precision of 6:
3865 // (1.4034025f - 0.23903021f * x) * x;
3867 // error 0.0034276066, which is better than 8 bits
3868 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3869 getF32Constant(DAG, 0xbe74c456, dl));
3870 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3871 getF32Constant(DAG, 0x3fb3a2b1, dl));
3872 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3873 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3874 getF32Constant(DAG, 0x3f949a29, dl));
3875 } else if (LimitFloatPrecision <= 12) {
3876 // For floating-point precision of 12:
3882 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3884 // error 0.000061011436, which is 14 bits
3885 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3886 getF32Constant(DAG, 0xbd67b6d6, dl));
3887 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3888 getF32Constant(DAG, 0x3ee4f4b8, dl));
3889 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3890 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3891 getF32Constant(DAG, 0x3fbc278b, dl));
3892 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3893 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3894 getF32Constant(DAG, 0x40348e95, dl));
3895 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3896 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3897 getF32Constant(DAG, 0x3fdef31a, dl));
3898 } else { // LimitFloatPrecision <= 18
3899 // For floating-point precision of 18:
3907 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3909 // error 0.0000023660568, which is better than 18 bits
3910 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3911 getF32Constant(DAG, 0xbc91e5ac, dl));
3912 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3913 getF32Constant(DAG, 0x3e4350aa, dl));
3914 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3915 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3916 getF32Constant(DAG, 0x3f60d3e3, dl));
3917 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3918 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3919 getF32Constant(DAG, 0x4011cdf0, dl));
3920 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3921 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3922 getF32Constant(DAG, 0x406cfd1c, dl));
3923 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3924 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3925 getF32Constant(DAG, 0x408797cb, dl));
3926 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3927 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3928 getF32Constant(DAG, 0x4006dcab, dl));
3931 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3934 // No special expansion.
3935 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3938 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3939 /// limited-precision mode.
3940 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3941 const TargetLowering &TLI) {
3943 // TODO: What fast-math-flags should be set on the floating-point nodes?
3945 if (Op.getValueType() == MVT::f32 &&
3946 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3947 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3949 // Get the exponent.
3950 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3952 // Get the significand and build it into a floating-point number with
3954 SDValue X = GetSignificand(DAG, Op1, dl);
3956 // Different possible minimax approximations of significand in
3957 // floating-point for various degrees of accuracy over [1,2].
3958 SDValue Log2ofMantissa;
3959 if (LimitFloatPrecision <= 6) {
3960 // For floating-point precision of 6:
3962 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3964 // error 0.0049451742, which is more than 7 bits
3965 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3966 getF32Constant(DAG, 0xbeb08fe0, dl));
3967 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3968 getF32Constant(DAG, 0x40019463, dl));
3969 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3970 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3971 getF32Constant(DAG, 0x3fd6633d, dl));
3972 } else if (LimitFloatPrecision <= 12) {
3973 // For floating-point precision of 12:
3979 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3981 // error 0.0000876136000, which is better than 13 bits
3982 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3983 getF32Constant(DAG, 0xbda7262e, dl));
3984 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3985 getF32Constant(DAG, 0x3f25280b, dl));
3986 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3987 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3988 getF32Constant(DAG, 0x4007b923, dl));
3989 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3990 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3991 getF32Constant(DAG, 0x40823e2f, dl));
3992 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3993 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3994 getF32Constant(DAG, 0x4020d29c, dl));
3995 } else { // LimitFloatPrecision <= 18
3996 // For floating-point precision of 18:
4005 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4007 // error 0.0000018516, which is better than 18 bits
4008 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4009 getF32Constant(DAG, 0xbcd2769e, dl));
4010 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4011 getF32Constant(DAG, 0x3e8ce0b9, dl));
4012 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4013 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4014 getF32Constant(DAG, 0x3fa22ae7, dl));
4015 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4016 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4017 getF32Constant(DAG, 0x40525723, dl));
4018 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4019 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4020 getF32Constant(DAG, 0x40aaf200, dl));
4021 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4022 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4023 getF32Constant(DAG, 0x40c39dad, dl));
4024 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4025 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4026 getF32Constant(DAG, 0x4042902c, dl));
4029 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4032 // No special expansion.
4033 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4036 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4037 /// limited-precision mode.
4038 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4039 const TargetLowering &TLI) {
4041 // TODO: What fast-math-flags should be set on the floating-point nodes?
4043 if (Op.getValueType() == MVT::f32 &&
4044 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4045 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4047 // Scale the exponent by log10(2) [0.30102999f].
4048 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4049 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4050 getF32Constant(DAG, 0x3e9a209a, dl));
4052 // Get the significand and build it into a floating-point number with
4054 SDValue X = GetSignificand(DAG, Op1, dl);
4056 SDValue Log10ofMantissa;
4057 if (LimitFloatPrecision <= 6) {
4058 // For floating-point precision of 6:
4060 // Log10ofMantissa =
4062 // (0.60948995f - 0.10380950f * x) * x;
4064 // error 0.0014886165, which is 6 bits
4065 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4066 getF32Constant(DAG, 0xbdd49a13, dl));
4067 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4068 getF32Constant(DAG, 0x3f1c0789, dl));
4069 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4070 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4071 getF32Constant(DAG, 0x3f011300, dl));
4072 } else if (LimitFloatPrecision <= 12) {
4073 // For floating-point precision of 12:
4075 // Log10ofMantissa =
4078 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4080 // error 0.00019228036, which is better than 12 bits
4081 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4082 getF32Constant(DAG, 0x3d431f31, dl));
4083 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4084 getF32Constant(DAG, 0x3ea21fb2, dl));
4085 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4086 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4087 getF32Constant(DAG, 0x3f6ae232, dl));
4088 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4089 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4090 getF32Constant(DAG, 0x3f25f7c3, dl));
4091 } else { // LimitFloatPrecision <= 18
4092 // For floating-point precision of 18:
4094 // Log10ofMantissa =
4099 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4101 // error 0.0000037995730, which is better than 18 bits
4102 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4103 getF32Constant(DAG, 0x3c5d51ce, dl));
4104 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4105 getF32Constant(DAG, 0x3e00685a, dl));
4106 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4107 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4108 getF32Constant(DAG, 0x3efb6798, dl));
4109 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4110 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4111 getF32Constant(DAG, 0x3f88d192, dl));
4112 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4113 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4114 getF32Constant(DAG, 0x3fc4316c, dl));
4115 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4116 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4117 getF32Constant(DAG, 0x3f57ce70, dl));
4120 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4123 // No special expansion.
4124 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4127 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4128 /// limited-precision mode.
4129 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4130 const TargetLowering &TLI) {
4131 if (Op.getValueType() == MVT::f32 &&
4132 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4133 return getLimitedPrecisionExp2(Op, dl, DAG);
4135 // No special expansion.
4136 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4139 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4140 /// limited-precision mode with x == 10.0f.
4141 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4142 SelectionDAG &DAG, const TargetLowering &TLI) {
4143 bool IsExp10 = false;
4144 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4145 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4146 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4148 IsExp10 = LHSC->isExactlyValue(Ten);
4152 // TODO: What fast-math-flags should be set on the FMUL node?
4154 // Put the exponent in the right bit position for later addition to the
4157 // #define LOG2OF10 3.3219281f
4158 // t0 = Op * LOG2OF10;
4159 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4160 getF32Constant(DAG, 0x40549a78, dl));
4161 return getLimitedPrecisionExp2(t0, dl, DAG);
4164 // No special expansion.
4165 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4169 /// ExpandPowI - Expand a llvm.powi intrinsic.
4170 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4171 SelectionDAG &DAG) {
4172 // If RHS is a constant, we can expand this out to a multiplication tree,
4173 // otherwise we end up lowering to a call to __powidf2 (for example). When
4174 // optimizing for size, we only want to do this if the expansion would produce
4175 // a small number of multiplies, otherwise we do the full expansion.
4176 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4177 // Get the exponent as a positive value.
4178 unsigned Val = RHSC->getSExtValue();
4179 if ((int)Val < 0) Val = -Val;
4181 // powi(x, 0) -> 1.0
4183 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4185 const Function *F = DAG.getMachineFunction().getFunction();
4186 if (!F->optForSize() ||
4187 // If optimizing for size, don't insert too many multiplies.
4188 // This inserts up to 5 multiplies.
4189 countPopulation(Val) + Log2_32(Val) < 7) {
4190 // We use the simple binary decomposition method to generate the multiply
4191 // sequence. There are more optimal ways to do this (for example,
4192 // powi(x,15) generates one more multiply than it should), but this has
4193 // the benefit of being both really simple and much better than a libcall.
4194 SDValue Res; // Logically starts equal to 1.0
4195 SDValue CurSquare = LHS;
4196 // TODO: Intrinsics should have fast-math-flags that propagate to these
4201 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4203 Res = CurSquare; // 1.0*CurSquare.
4206 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4207 CurSquare, CurSquare);
4211 // If the original was negative, invert the result, producing 1/(x*x*x).
4212 if (RHSC->getSExtValue() < 0)
4213 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4214 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4219 // Otherwise, expand to a libcall.
4220 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4223 // getUnderlyingArgReg - Find underlying register used for a truncated or
4224 // bitcasted argument.
4225 static unsigned getUnderlyingArgReg(const SDValue &N) {
4226 switch (N.getOpcode()) {
4227 case ISD::CopyFromReg:
4228 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4230 case ISD::AssertZext:
4231 case ISD::AssertSext:
4233 return getUnderlyingArgReg(N.getOperand(0));
4239 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4240 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4241 /// At the end of instruction selection, they will be inserted to the entry BB.
4242 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4243 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4244 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4245 const Argument *Arg = dyn_cast<Argument>(V);
4249 MachineFunction &MF = DAG.getMachineFunction();
4250 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4252 // Ignore inlined function arguments here.
4254 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4255 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4258 Optional<MachineOperand> Op;
4259 // Some arguments' frame index is recorded during argument lowering.
4260 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4261 Op = MachineOperand::CreateFI(FI);
4263 if (!Op && N.getNode()) {
4264 unsigned Reg = getUnderlyingArgReg(N);
4265 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4266 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4267 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4272 Op = MachineOperand::CreateReg(Reg, false);
4276 // Check if ValueMap has reg number.
4277 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4278 if (VMI != FuncInfo.ValueMap.end())
4279 Op = MachineOperand::CreateReg(VMI->second, false);
4282 if (!Op && N.getNode())
4283 // Check if frame index is available.
4284 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4285 if (FrameIndexSDNode *FINode =
4286 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4287 Op = MachineOperand::CreateFI(FINode->getIndex());
4292 assert(Variable->isValidLocationForIntrinsic(DL) &&
4293 "Expected inlined-at fields to agree");
4295 FuncInfo.ArgDbgValues.push_back(
4296 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4297 Op->getReg(), Offset, Variable, Expr));
4299 FuncInfo.ArgDbgValues.push_back(
4300 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4303 .addMetadata(Variable)
4304 .addMetadata(Expr));
4309 // VisualStudio defines setjmp as _setjmp
4310 #if defined(_MSC_VER) && defined(setjmp) && \
4311 !defined(setjmp_undefined_for_msvc)
4312 # pragma push_macro("setjmp")
4314 # define setjmp_undefined_for_msvc
4317 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4318 /// we want to emit this as a call to a named external function, return the name
4319 /// otherwise lower it and return null.
4321 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4322 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4323 SDLoc sdl = getCurSDLoc();
4324 DebugLoc dl = getCurDebugLoc();
4327 switch (Intrinsic) {
4329 // By default, turn this into a target intrinsic node.
4330 visitTargetIntrinsic(I, Intrinsic);
4332 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4333 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4334 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4335 case Intrinsic::returnaddress:
4336 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4337 TLI.getPointerTy(DAG.getDataLayout()),
4338 getValue(I.getArgOperand(0))));
4340 case Intrinsic::frameaddress:
4341 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4342 TLI.getPointerTy(DAG.getDataLayout()),
4343 getValue(I.getArgOperand(0))));
4345 case Intrinsic::read_register: {
4346 Value *Reg = I.getArgOperand(0);
4347 SDValue Chain = getRoot();
4349 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4350 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4351 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4352 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4354 DAG.setRoot(Res.getValue(1));
4357 case Intrinsic::write_register: {
4358 Value *Reg = I.getArgOperand(0);
4359 Value *RegValue = I.getArgOperand(1);
4360 SDValue Chain = getRoot();
4362 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4363 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4364 RegName, getValue(RegValue)));
4367 case Intrinsic::setjmp:
4368 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4369 case Intrinsic::longjmp:
4370 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4371 case Intrinsic::memcpy: {
4372 // FIXME: this definition of "user defined address space" is x86-specific
4373 // Assert for address < 256 since we support only user defined address
4375 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4377 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4379 "Unknown address space");
4380 SDValue Op1 = getValue(I.getArgOperand(0));
4381 SDValue Op2 = getValue(I.getArgOperand(1));
4382 SDValue Op3 = getValue(I.getArgOperand(2));
4383 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4385 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4386 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4387 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4388 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4390 MachinePointerInfo(I.getArgOperand(0)),
4391 MachinePointerInfo(I.getArgOperand(1)));
4392 updateDAGForMaybeTailCall(MC);
4395 case Intrinsic::memset: {
4396 // FIXME: this definition of "user defined address space" is x86-specific
4397 // Assert for address < 256 since we support only user defined address
4399 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4401 "Unknown address space");
4402 SDValue Op1 = getValue(I.getArgOperand(0));
4403 SDValue Op2 = getValue(I.getArgOperand(1));
4404 SDValue Op3 = getValue(I.getArgOperand(2));
4405 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4407 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4408 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4409 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4410 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4411 isTC, MachinePointerInfo(I.getArgOperand(0)));
4412 updateDAGForMaybeTailCall(MS);
4415 case Intrinsic::memmove: {
4416 // FIXME: this definition of "user defined address space" is x86-specific
4417 // Assert for address < 256 since we support only user defined address
4419 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4421 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4423 "Unknown address space");
4424 SDValue Op1 = getValue(I.getArgOperand(0));
4425 SDValue Op2 = getValue(I.getArgOperand(1));
4426 SDValue Op3 = getValue(I.getArgOperand(2));
4427 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4429 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4430 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4431 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4432 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4433 isTC, MachinePointerInfo(I.getArgOperand(0)),
4434 MachinePointerInfo(I.getArgOperand(1)));
4435 updateDAGForMaybeTailCall(MM);
4438 case Intrinsic::dbg_declare: {
4439 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4440 DILocalVariable *Variable = DI.getVariable();
4441 DIExpression *Expression = DI.getExpression();
4442 const Value *Address = DI.getAddress();
4443 assert(Variable && "Missing variable");
4445 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4449 // Check if address has undef value.
4450 if (isa<UndefValue>(Address) ||
4451 (Address->use_empty() && !isa<Argument>(Address))) {
4452 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4456 SDValue &N = NodeMap[Address];
4457 if (!N.getNode() && isa<Argument>(Address))
4458 // Check unused arguments map.
4459 N = UnusedArgNodeMap[Address];
4462 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4463 Address = BCI->getOperand(0);
4464 // Parameters are handled specially.
4465 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4466 auto FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4467 if (isParameter && FINode) {
4468 // Byval parameter. We have a frame index at this point.
4469 SDV = DAG.getFrameIndexDbgValue(Variable, Expression,
4470 FINode->getIndex(), 0, dl, SDNodeOrder);
4471 } else if (isa<Argument>(Address)) {
4472 // Address is an argument, so try to emit its dbg value using
4473 // virtual register info from the FuncInfo.ValueMap.
4474 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4478 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4479 true, 0, dl, SDNodeOrder);
4481 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4483 // If Address is an argument then try to emit its dbg value using
4484 // virtual register info from the FuncInfo.ValueMap.
4485 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4487 // If variable is pinned by a alloca in dominating bb then
4488 // use StaticAllocaMap.
4489 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4490 if (AI->getParent() != DI.getParent()) {
4491 DenseMap<const AllocaInst*, int>::iterator SI =
4492 FuncInfo.StaticAllocaMap.find(AI);
4493 if (SI != FuncInfo.StaticAllocaMap.end()) {
4494 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4495 0, dl, SDNodeOrder);
4496 DAG.AddDbgValue(SDV, nullptr, false);
4501 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4506 case Intrinsic::dbg_value: {
4507 const DbgValueInst &DI = cast<DbgValueInst>(I);
4508 assert(DI.getVariable() && "Missing variable");
4510 DILocalVariable *Variable = DI.getVariable();
4511 DIExpression *Expression = DI.getExpression();
4512 uint64_t Offset = DI.getOffset();
4513 const Value *V = DI.getValue();
4518 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4519 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4521 DAG.AddDbgValue(SDV, nullptr, false);
4523 // Do not use getValue() in here; we don't want to generate code at
4524 // this point if it hasn't been done yet.
4525 SDValue N = NodeMap[V];
4526 if (!N.getNode() && isa<Argument>(V))
4527 // Check unused arguments map.
4528 N = UnusedArgNodeMap[V];
4530 // A dbg.value for an alloca is always indirect.
4531 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4532 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4534 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4535 IsIndirect, Offset, dl, SDNodeOrder);
4536 DAG.AddDbgValue(SDV, N.getNode(), false);
4538 } else if (!V->use_empty() ) {
4539 // Do not call getValue(V) yet, as we don't want to generate code.
4540 // Remember it for later.
4541 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4542 DanglingDebugInfoMap[V] = DDI;
4544 // We may expand this to cover more cases. One case where we have no
4545 // data available is an unreferenced parameter.
4546 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4550 // Build a debug info table entry.
4551 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4552 V = BCI->getOperand(0);
4553 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4554 // Don't handle byval struct arguments or VLAs, for example.
4556 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4557 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4560 DenseMap<const AllocaInst*, int>::iterator SI =
4561 FuncInfo.StaticAllocaMap.find(AI);
4562 if (SI == FuncInfo.StaticAllocaMap.end())
4563 return nullptr; // VLAs.
4567 case Intrinsic::eh_typeid_for: {
4568 // Find the type id for the given typeinfo.
4569 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4570 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4571 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4576 case Intrinsic::eh_return_i32:
4577 case Intrinsic::eh_return_i64:
4578 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4579 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4582 getValue(I.getArgOperand(0)),
4583 getValue(I.getArgOperand(1))));
4585 case Intrinsic::eh_unwind_init:
4586 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4588 case Intrinsic::eh_dwarf_cfa: {
4589 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4590 TLI.getPointerTy(DAG.getDataLayout()));
4591 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4592 CfaArg.getValueType(),
4593 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4594 CfaArg.getValueType()),
4596 SDValue FA = DAG.getNode(
4597 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4598 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4599 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4603 case Intrinsic::eh_sjlj_callsite: {
4604 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4605 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4606 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4607 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4609 MMI.setCurrentCallSite(CI->getZExtValue());
4612 case Intrinsic::eh_sjlj_functioncontext: {
4613 // Get and store the index of the function context.
4614 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4616 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4617 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4618 MFI->setFunctionContextIndex(FI);
4621 case Intrinsic::eh_sjlj_setjmp: {
4624 Ops[1] = getValue(I.getArgOperand(0));
4625 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4626 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4627 setValue(&I, Op.getValue(0));
4628 DAG.setRoot(Op.getValue(1));
4631 case Intrinsic::eh_sjlj_longjmp: {
4632 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4633 getRoot(), getValue(I.getArgOperand(0))));
4636 case Intrinsic::eh_sjlj_setup_dispatch: {
4637 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4642 case Intrinsic::masked_gather:
4643 visitMaskedGather(I);
4645 case Intrinsic::masked_load:
4648 case Intrinsic::masked_scatter:
4649 visitMaskedScatter(I);
4651 case Intrinsic::masked_store:
4652 visitMaskedStore(I);
4654 case Intrinsic::x86_mmx_pslli_w:
4655 case Intrinsic::x86_mmx_pslli_d:
4656 case Intrinsic::x86_mmx_pslli_q:
4657 case Intrinsic::x86_mmx_psrli_w:
4658 case Intrinsic::x86_mmx_psrli_d:
4659 case Intrinsic::x86_mmx_psrli_q:
4660 case Intrinsic::x86_mmx_psrai_w:
4661 case Intrinsic::x86_mmx_psrai_d: {
4662 SDValue ShAmt = getValue(I.getArgOperand(1));
4663 if (isa<ConstantSDNode>(ShAmt)) {
4664 visitTargetIntrinsic(I, Intrinsic);
4667 unsigned NewIntrinsic = 0;
4668 EVT ShAmtVT = MVT::v2i32;
4669 switch (Intrinsic) {
4670 case Intrinsic::x86_mmx_pslli_w:
4671 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4673 case Intrinsic::x86_mmx_pslli_d:
4674 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4676 case Intrinsic::x86_mmx_pslli_q:
4677 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4679 case Intrinsic::x86_mmx_psrli_w:
4680 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4682 case Intrinsic::x86_mmx_psrli_d:
4683 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4685 case Intrinsic::x86_mmx_psrli_q:
4686 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4688 case Intrinsic::x86_mmx_psrai_w:
4689 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4691 case Intrinsic::x86_mmx_psrai_d:
4692 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4694 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4697 // The vector shift intrinsics with scalars uses 32b shift amounts but
4698 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4700 // We must do this early because v2i32 is not a legal type.
4703 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4704 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4705 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4706 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4707 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4708 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4709 getValue(I.getArgOperand(0)), ShAmt);
4713 case Intrinsic::convertff:
4714 case Intrinsic::convertfsi:
4715 case Intrinsic::convertfui:
4716 case Intrinsic::convertsif:
4717 case Intrinsic::convertuif:
4718 case Intrinsic::convertss:
4719 case Intrinsic::convertsu:
4720 case Intrinsic::convertus:
4721 case Intrinsic::convertuu: {
4722 ISD::CvtCode Code = ISD::CVT_INVALID;
4723 switch (Intrinsic) {
4724 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4725 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4726 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4727 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4728 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4729 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4730 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4731 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4732 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4733 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4735 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4736 const Value *Op1 = I.getArgOperand(0);
4737 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4738 DAG.getValueType(DestVT),
4739 DAG.getValueType(getValue(Op1).getValueType()),
4740 getValue(I.getArgOperand(1)),
4741 getValue(I.getArgOperand(2)),
4746 case Intrinsic::powi:
4747 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4748 getValue(I.getArgOperand(1)), DAG));
4750 case Intrinsic::log:
4751 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4753 case Intrinsic::log2:
4754 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4756 case Intrinsic::log10:
4757 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4759 case Intrinsic::exp:
4760 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4762 case Intrinsic::exp2:
4763 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4765 case Intrinsic::pow:
4766 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4767 getValue(I.getArgOperand(1)), DAG, TLI));
4769 case Intrinsic::sqrt:
4770 case Intrinsic::fabs:
4771 case Intrinsic::sin:
4772 case Intrinsic::cos:
4773 case Intrinsic::floor:
4774 case Intrinsic::ceil:
4775 case Intrinsic::trunc:
4776 case Intrinsic::rint:
4777 case Intrinsic::nearbyint:
4778 case Intrinsic::round: {
4780 switch (Intrinsic) {
4781 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4782 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4783 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4784 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4785 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4786 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4787 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4788 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4789 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4790 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4791 case Intrinsic::round: Opcode = ISD::FROUND; break;
4794 setValue(&I, DAG.getNode(Opcode, sdl,
4795 getValue(I.getArgOperand(0)).getValueType(),
4796 getValue(I.getArgOperand(0))));
4799 case Intrinsic::minnum:
4800 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4801 getValue(I.getArgOperand(0)).getValueType(),
4802 getValue(I.getArgOperand(0)),
4803 getValue(I.getArgOperand(1))));
4805 case Intrinsic::maxnum:
4806 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4807 getValue(I.getArgOperand(0)).getValueType(),
4808 getValue(I.getArgOperand(0)),
4809 getValue(I.getArgOperand(1))));
4811 case Intrinsic::copysign:
4812 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4813 getValue(I.getArgOperand(0)).getValueType(),
4814 getValue(I.getArgOperand(0)),
4815 getValue(I.getArgOperand(1))));
4817 case Intrinsic::fma:
4818 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4819 getValue(I.getArgOperand(0)).getValueType(),
4820 getValue(I.getArgOperand(0)),
4821 getValue(I.getArgOperand(1)),
4822 getValue(I.getArgOperand(2))));
4824 case Intrinsic::fmuladd: {
4825 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4826 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4827 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4828 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4829 getValue(I.getArgOperand(0)).getValueType(),
4830 getValue(I.getArgOperand(0)),
4831 getValue(I.getArgOperand(1)),
4832 getValue(I.getArgOperand(2))));
4834 // TODO: Intrinsic calls should have fast-math-flags.
4835 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4836 getValue(I.getArgOperand(0)).getValueType(),
4837 getValue(I.getArgOperand(0)),
4838 getValue(I.getArgOperand(1)));
4839 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4840 getValue(I.getArgOperand(0)).getValueType(),
4842 getValue(I.getArgOperand(2)));
4847 case Intrinsic::convert_to_fp16:
4848 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4849 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4850 getValue(I.getArgOperand(0)),
4851 DAG.getTargetConstant(0, sdl,
4854 case Intrinsic::convert_from_fp16:
4855 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4856 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4857 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4858 getValue(I.getArgOperand(0)))));
4860 case Intrinsic::pcmarker: {
4861 SDValue Tmp = getValue(I.getArgOperand(0));
4862 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4865 case Intrinsic::readcyclecounter: {
4866 SDValue Op = getRoot();
4867 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4868 DAG.getVTList(MVT::i64, MVT::Other), Op);
4870 DAG.setRoot(Res.getValue(1));
4873 case Intrinsic::bitreverse:
4874 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
4875 getValue(I.getArgOperand(0)).getValueType(),
4876 getValue(I.getArgOperand(0))));
4878 case Intrinsic::bswap:
4879 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4880 getValue(I.getArgOperand(0)).getValueType(),
4881 getValue(I.getArgOperand(0))));
4883 case Intrinsic::uabsdiff:
4884 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4885 getValue(I.getArgOperand(0)).getValueType(),
4886 getValue(I.getArgOperand(0)),
4887 getValue(I.getArgOperand(1))));
4889 case Intrinsic::sabsdiff:
4890 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4891 getValue(I.getArgOperand(0)).getValueType(),
4892 getValue(I.getArgOperand(0)),
4893 getValue(I.getArgOperand(1))));
4895 case Intrinsic::cttz: {
4896 SDValue Arg = getValue(I.getArgOperand(0));
4897 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4898 EVT Ty = Arg.getValueType();
4899 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4903 case Intrinsic::ctlz: {
4904 SDValue Arg = getValue(I.getArgOperand(0));
4905 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4906 EVT Ty = Arg.getValueType();
4907 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4911 case Intrinsic::ctpop: {
4912 SDValue Arg = getValue(I.getArgOperand(0));
4913 EVT Ty = Arg.getValueType();
4914 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4917 case Intrinsic::stacksave: {
4918 SDValue Op = getRoot();
4920 ISD::STACKSAVE, sdl,
4921 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4923 DAG.setRoot(Res.getValue(1));
4926 case Intrinsic::stackrestore: {
4927 Res = getValue(I.getArgOperand(0));
4928 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4931 case Intrinsic::get_dynamic_area_offset: {
4932 SDValue Op = getRoot();
4933 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4934 EVT ResTy = TLI.getValueType(DAG.getDataLayout(), I.getType());
4935 // Result type for @llvm.get.dynamic.area.offset should match PtrTy for
4938 report_fatal_error("Wrong result type for @llvm.get.dynamic.area.offset"
4940 Res = DAG.getNode(ISD::GET_DYNAMIC_AREA_OFFSET, sdl, DAG.getVTList(ResTy),
4946 case Intrinsic::stackprotector: {
4947 // Emit code into the DAG to store the stack guard onto the stack.
4948 MachineFunction &MF = DAG.getMachineFunction();
4949 MachineFrameInfo *MFI = MF.getFrameInfo();
4950 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4951 SDValue Src, Chain = getRoot();
4952 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4953 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4955 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4956 // global variable __stack_chk_guard.
4958 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4959 if (BC->getOpcode() == Instruction::BitCast)
4960 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4962 if (GV && TLI.useLoadStackGuardNode()) {
4963 // Emit a LOAD_STACK_GUARD node.
4964 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4966 MachinePointerInfo MPInfo(GV);
4967 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4968 unsigned Flags = MachineMemOperand::MOLoad |
4969 MachineMemOperand::MOInvariant;
4970 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4971 PtrTy.getSizeInBits() / 8,
4972 DAG.getEVTAlignment(PtrTy));
4973 Node->setMemRefs(MemRefs, MemRefs + 1);
4975 // Copy the guard value to a virtual register so that it can be
4976 // retrieved in the epilogue.
4977 Src = SDValue(Node, 0);
4978 const TargetRegisterClass *RC =
4979 TLI.getRegClassFor(Src.getSimpleValueType());
4980 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4982 SPDescriptor.setGuardReg(Reg);
4983 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4985 Src = getValue(I.getArgOperand(0)); // The guard's value.
4988 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4990 int FI = FuncInfo.StaticAllocaMap[Slot];
4991 MFI->setStackProtectorIndex(FI);
4993 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4995 // Store the stack protector onto the stack.
4996 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4997 DAG.getMachineFunction(), FI),
5003 case Intrinsic::objectsize: {
5004 // If we don't know by now, we're never going to know.
5005 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5007 assert(CI && "Non-constant type in __builtin_object_size?");
5009 SDValue Arg = getValue(I.getCalledValue());
5010 EVT Ty = Arg.getValueType();
5013 Res = DAG.getConstant(-1ULL, sdl, Ty);
5015 Res = DAG.getConstant(0, sdl, Ty);
5020 case Intrinsic::annotation:
5021 case Intrinsic::ptr_annotation:
5022 // Drop the intrinsic, but forward the value
5023 setValue(&I, getValue(I.getOperand(0)));
5025 case Intrinsic::assume:
5026 case Intrinsic::var_annotation:
5027 // Discard annotate attributes and assumptions
5030 case Intrinsic::init_trampoline: {
5031 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5035 Ops[1] = getValue(I.getArgOperand(0));
5036 Ops[2] = getValue(I.getArgOperand(1));
5037 Ops[3] = getValue(I.getArgOperand(2));
5038 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5039 Ops[5] = DAG.getSrcValue(F);
5041 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5046 case Intrinsic::adjust_trampoline: {
5047 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5048 TLI.getPointerTy(DAG.getDataLayout()),
5049 getValue(I.getArgOperand(0))));
5052 case Intrinsic::gcroot:
5054 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5055 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5057 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5058 GFI->addStackRoot(FI->getIndex(), TypeMap);
5061 case Intrinsic::gcread:
5062 case Intrinsic::gcwrite:
5063 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5064 case Intrinsic::flt_rounds:
5065 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5068 case Intrinsic::expect: {
5069 // Just replace __builtin_expect(exp, c) with EXP.
5070 setValue(&I, getValue(I.getArgOperand(0)));
5074 case Intrinsic::debugtrap:
5075 case Intrinsic::trap: {
5076 StringRef TrapFuncName =
5078 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5079 .getValueAsString();
5080 if (TrapFuncName.empty()) {
5081 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5082 ISD::TRAP : ISD::DEBUGTRAP;
5083 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5086 TargetLowering::ArgListTy Args;
5088 TargetLowering::CallLoweringInfo CLI(DAG);
5089 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5090 CallingConv::C, I.getType(),
5091 DAG.getExternalSymbol(TrapFuncName.data(),
5092 TLI.getPointerTy(DAG.getDataLayout())),
5093 std::move(Args), 0);
5095 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5096 DAG.setRoot(Result.second);
5100 case Intrinsic::uadd_with_overflow:
5101 case Intrinsic::sadd_with_overflow:
5102 case Intrinsic::usub_with_overflow:
5103 case Intrinsic::ssub_with_overflow:
5104 case Intrinsic::umul_with_overflow:
5105 case Intrinsic::smul_with_overflow: {
5107 switch (Intrinsic) {
5108 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5109 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5110 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5111 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5112 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5113 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5114 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5116 SDValue Op1 = getValue(I.getArgOperand(0));
5117 SDValue Op2 = getValue(I.getArgOperand(1));
5119 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5120 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5123 case Intrinsic::prefetch: {
5125 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5127 Ops[1] = getValue(I.getArgOperand(0));
5128 Ops[2] = getValue(I.getArgOperand(1));
5129 Ops[3] = getValue(I.getArgOperand(2));
5130 Ops[4] = getValue(I.getArgOperand(3));
5131 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5132 DAG.getVTList(MVT::Other), Ops,
5133 EVT::getIntegerVT(*Context, 8),
5134 MachinePointerInfo(I.getArgOperand(0)),
5136 false, /* volatile */
5138 rw==1)); /* write */
5141 case Intrinsic::lifetime_start:
5142 case Intrinsic::lifetime_end: {
5143 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5144 // Stack coloring is not enabled in O0, discard region information.
5145 if (TM.getOptLevel() == CodeGenOpt::None)
5148 SmallVector<Value *, 4> Allocas;
5149 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5151 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5152 E = Allocas.end(); Object != E; ++Object) {
5153 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5155 // Could not find an Alloca.
5156 if (!LifetimeObject)
5159 // First check that the Alloca is static, otherwise it won't have a
5160 // valid frame index.
5161 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5162 if (SI == FuncInfo.StaticAllocaMap.end())
5165 int FI = SI->second;
5170 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5171 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5173 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5178 case Intrinsic::invariant_start:
5179 // Discard region information.
5180 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5182 case Intrinsic::invariant_end:
5183 // Discard region information.
5185 case Intrinsic::stackprotectorcheck: {
5186 // Do not actually emit anything for this basic block. Instead we initialize
5187 // the stack protector descriptor and export the guard variable so we can
5188 // access it in FinishBasicBlock.
5189 const BasicBlock *BB = I.getParent();
5190 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5191 ExportFromCurrentBlock(SPDescriptor.getGuard());
5193 // Flush our exports since we are going to process a terminator.
5194 (void)getControlRoot();
5197 case Intrinsic::clear_cache:
5198 return TLI.getClearCacheBuiltinName();
5199 case Intrinsic::donothing:
5202 case Intrinsic::experimental_stackmap: {
5206 case Intrinsic::experimental_patchpoint_void:
5207 case Intrinsic::experimental_patchpoint_i64: {
5208 visitPatchpoint(&I);
5211 case Intrinsic::experimental_gc_statepoint: {
5215 case Intrinsic::experimental_gc_result_int:
5216 case Intrinsic::experimental_gc_result_float:
5217 case Intrinsic::experimental_gc_result_ptr:
5218 case Intrinsic::experimental_gc_result: {
5222 case Intrinsic::experimental_gc_relocate: {
5226 case Intrinsic::instrprof_increment:
5227 llvm_unreachable("instrprof failed to lower an increment");
5228 case Intrinsic::instrprof_value_profile:
5229 llvm_unreachable("instrprof failed to lower a value profiling call");
5230 case Intrinsic::localescape: {
5231 MachineFunction &MF = DAG.getMachineFunction();
5232 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5234 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5235 // is the same on all targets.
5236 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5237 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5238 if (isa<ConstantPointerNull>(Arg))
5239 continue; // Skip null pointers. They represent a hole in index space.
5240 AllocaInst *Slot = cast<AllocaInst>(Arg);
5241 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5242 "can only escape static allocas");
5243 int FI = FuncInfo.StaticAllocaMap[Slot];
5244 MCSymbol *FrameAllocSym =
5245 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5246 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5247 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5248 TII->get(TargetOpcode::LOCAL_ESCAPE))
5249 .addSym(FrameAllocSym)
5256 case Intrinsic::localrecover: {
5257 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5258 MachineFunction &MF = DAG.getMachineFunction();
5259 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5261 // Get the symbol that defines the frame offset.
5262 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5263 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5264 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5265 MCSymbol *FrameAllocSym =
5266 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5267 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5269 // Create a MCSymbol for the label to avoid any target lowering
5270 // that would make this PC relative.
5271 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5273 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5275 // Add the offset to the FP.
5276 Value *FP = I.getArgOperand(1);
5277 SDValue FPVal = getValue(FP);
5278 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5284 case Intrinsic::eh_exceptionpointer:
5285 case Intrinsic::eh_exceptioncode: {
5286 // Get the exception pointer vreg, copy from it, and resize it to fit.
5287 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5288 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5289 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5290 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5292 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5293 if (Intrinsic == Intrinsic::eh_exceptioncode)
5294 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5301 std::pair<SDValue, SDValue>
5302 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5303 const BasicBlock *EHPadBB) {
5304 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5305 MCSymbol *BeginLabel = nullptr;
5308 // Insert a label before the invoke call to mark the try range. This can be
5309 // used to detect deletion of the invoke via the MachineModuleInfo.
5310 BeginLabel = MMI.getContext().createTempSymbol();
5312 // For SjLj, keep track of which landing pads go with which invokes
5313 // so as to maintain the ordering of pads in the LSDA.
5314 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5315 if (CallSiteIndex) {
5316 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5317 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5319 // Now that the call site is handled, stop tracking it.
5320 MMI.setCurrentCallSite(0);
5323 // Both PendingLoads and PendingExports must be flushed here;
5324 // this call might not return.
5326 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5328 CLI.setChain(getRoot());
5330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5331 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5333 assert((CLI.IsTailCall || Result.second.getNode()) &&
5334 "Non-null chain expected with non-tail call!");
5335 assert((Result.second.getNode() || !Result.first.getNode()) &&
5336 "Null value expected with tail call!");
5338 if (!Result.second.getNode()) {
5339 // As a special case, a null chain means that a tail call has been emitted
5340 // and the DAG root is already updated.
5343 // Since there's no actual continuation from this block, nothing can be
5344 // relying on us setting vregs for them.
5345 PendingExports.clear();
5347 DAG.setRoot(Result.second);
5351 // Insert a label at the end of the invoke call to mark the try range. This
5352 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5353 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5354 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5356 // Inform MachineModuleInfo of range.
5357 if (MMI.hasEHFunclets()) {
5358 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
5359 EHInfo->addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5361 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5368 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5370 const BasicBlock *EHPadBB) {
5371 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5372 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5373 Type *RetTy = FTy->getReturnType();
5375 TargetLowering::ArgListTy Args;
5376 TargetLowering::ArgListEntry Entry;
5377 Args.reserve(CS.arg_size());
5379 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5381 const Value *V = *i;
5384 if (V->getType()->isEmptyTy())
5387 SDValue ArgNode = getValue(V);
5388 Entry.Node = ArgNode; Entry.Ty = V->getType();
5390 // Skip the first return-type Attribute to get to params.
5391 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5392 Args.push_back(Entry);
5394 // If we have an explicit sret argument that is an Instruction, (i.e., it
5395 // might point to function-local memory), we can't meaningfully tail-call.
5396 if (Entry.isSRet && isa<Instruction>(V))
5400 // Check if target-independent constraints permit a tail call here.
5401 // Target-dependent constraints are checked within TLI->LowerCallTo.
5402 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5405 TargetLowering::CallLoweringInfo CLI(DAG);
5406 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5407 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5408 .setTailCall(isTailCall);
5409 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5411 if (Result.first.getNode())
5412 setValue(CS.getInstruction(), Result.first);
5415 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5416 /// value is equal or not-equal to zero.
5417 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5418 for (const User *U : V->users()) {
5419 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5420 if (IC->isEquality())
5421 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5422 if (C->isNullValue())
5424 // Unknown instruction.
5430 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5432 SelectionDAGBuilder &Builder) {
5434 // Check to see if this load can be trivially constant folded, e.g. if the
5435 // input is from a string literal.
5436 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5437 // Cast pointer to the type we really want to load.
5438 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5439 PointerType::getUnqual(LoadTy));
5441 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5442 const_cast<Constant *>(LoadInput), *Builder.DL))
5443 return Builder.getValue(LoadCst);
5446 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5447 // still constant memory, the input chain can be the entry node.
5449 bool ConstantMemory = false;
5451 // Do not serialize (non-volatile) loads of constant memory with anything.
5452 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5453 Root = Builder.DAG.getEntryNode();
5454 ConstantMemory = true;
5456 // Do not serialize non-volatile loads against each other.
5457 Root = Builder.DAG.getRoot();
5460 SDValue Ptr = Builder.getValue(PtrVal);
5461 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5462 Ptr, MachinePointerInfo(PtrVal),
5464 false /*nontemporal*/,
5465 false /*isinvariant*/, 1 /* align=1 */);
5467 if (!ConstantMemory)
5468 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5472 /// processIntegerCallValue - Record the value for an instruction that
5473 /// produces an integer result, converting the type where necessary.
5474 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5477 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5480 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5482 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5483 setValue(&I, Value);
5486 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5487 /// If so, return true and lower it, otherwise return false and it will be
5488 /// lowered like a normal call.
5489 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5490 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5491 if (I.getNumArgOperands() != 3)
5494 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5495 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5496 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5497 !I.getType()->isIntegerTy())
5500 const Value *Size = I.getArgOperand(2);
5501 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5502 if (CSize && CSize->getZExtValue() == 0) {
5503 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5505 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5509 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5510 std::pair<SDValue, SDValue> Res =
5511 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5512 getValue(LHS), getValue(RHS), getValue(Size),
5513 MachinePointerInfo(LHS),
5514 MachinePointerInfo(RHS));
5515 if (Res.first.getNode()) {
5516 processIntegerCallValue(I, Res.first, true);
5517 PendingLoads.push_back(Res.second);
5521 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5522 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5523 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5524 bool ActuallyDoIt = true;
5527 switch (CSize->getZExtValue()) {
5529 LoadVT = MVT::Other;
5531 ActuallyDoIt = false;
5535 LoadTy = Type::getInt16Ty(CSize->getContext());
5539 LoadTy = Type::getInt32Ty(CSize->getContext());
5543 LoadTy = Type::getInt64Ty(CSize->getContext());
5547 LoadVT = MVT::v4i32;
5548 LoadTy = Type::getInt32Ty(CSize->getContext());
5549 LoadTy = VectorType::get(LoadTy, 4);
5554 // This turns into unaligned loads. We only do this if the target natively
5555 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5556 // we'll only produce a small number of byte loads.
5558 // Require that we can find a legal MVT, and only do this if the target
5559 // supports unaligned loads of that type. Expanding into byte loads would
5561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5562 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5563 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5564 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5565 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5566 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5567 // TODO: Check alignment of src and dest ptrs.
5568 if (!TLI.isTypeLegal(LoadVT) ||
5569 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5570 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5571 ActuallyDoIt = false;
5575 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5576 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5578 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5580 processIntegerCallValue(I, Res, false);
5589 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5590 /// form. If so, return true and lower it, otherwise return false and it
5591 /// will be lowered like a normal call.
5592 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5593 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5594 if (I.getNumArgOperands() != 3)
5597 const Value *Src = I.getArgOperand(0);
5598 const Value *Char = I.getArgOperand(1);
5599 const Value *Length = I.getArgOperand(2);
5600 if (!Src->getType()->isPointerTy() ||
5601 !Char->getType()->isIntegerTy() ||
5602 !Length->getType()->isIntegerTy() ||
5603 !I.getType()->isPointerTy())
5606 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5607 std::pair<SDValue, SDValue> Res =
5608 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5609 getValue(Src), getValue(Char), getValue(Length),
5610 MachinePointerInfo(Src));
5611 if (Res.first.getNode()) {
5612 setValue(&I, Res.first);
5613 PendingLoads.push_back(Res.second);
5620 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5621 /// optimized form. If so, return true and lower it, otherwise return false
5622 /// and it will be lowered like a normal call.
5623 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5624 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5625 if (I.getNumArgOperands() != 2)
5628 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5629 if (!Arg0->getType()->isPointerTy() ||
5630 !Arg1->getType()->isPointerTy() ||
5631 !I.getType()->isPointerTy())
5634 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5635 std::pair<SDValue, SDValue> Res =
5636 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5637 getValue(Arg0), getValue(Arg1),
5638 MachinePointerInfo(Arg0),
5639 MachinePointerInfo(Arg1), isStpcpy);
5640 if (Res.first.getNode()) {
5641 setValue(&I, Res.first);
5642 DAG.setRoot(Res.second);
5649 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5650 /// If so, return true and lower it, otherwise return false and it will be
5651 /// lowered like a normal call.
5652 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5653 // Verify that the prototype makes sense. int strcmp(void*,void*)
5654 if (I.getNumArgOperands() != 2)
5657 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5658 if (!Arg0->getType()->isPointerTy() ||
5659 !Arg1->getType()->isPointerTy() ||
5660 !I.getType()->isIntegerTy())
5663 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5664 std::pair<SDValue, SDValue> Res =
5665 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5666 getValue(Arg0), getValue(Arg1),
5667 MachinePointerInfo(Arg0),
5668 MachinePointerInfo(Arg1));
5669 if (Res.first.getNode()) {
5670 processIntegerCallValue(I, Res.first, true);
5671 PendingLoads.push_back(Res.second);
5678 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5679 /// form. If so, return true and lower it, otherwise return false and it
5680 /// will be lowered like a normal call.
5681 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5682 // Verify that the prototype makes sense. size_t strlen(char *)
5683 if (I.getNumArgOperands() != 1)
5686 const Value *Arg0 = I.getArgOperand(0);
5687 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5690 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5691 std::pair<SDValue, SDValue> Res =
5692 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5693 getValue(Arg0), MachinePointerInfo(Arg0));
5694 if (Res.first.getNode()) {
5695 processIntegerCallValue(I, Res.first, false);
5696 PendingLoads.push_back(Res.second);
5703 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5704 /// form. If so, return true and lower it, otherwise return false and it
5705 /// will be lowered like a normal call.
5706 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5707 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5708 if (I.getNumArgOperands() != 2)
5711 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5712 if (!Arg0->getType()->isPointerTy() ||
5713 !Arg1->getType()->isIntegerTy() ||
5714 !I.getType()->isIntegerTy())
5717 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5718 std::pair<SDValue, SDValue> Res =
5719 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5720 getValue(Arg0), getValue(Arg1),
5721 MachinePointerInfo(Arg0));
5722 if (Res.first.getNode()) {
5723 processIntegerCallValue(I, Res.first, false);
5724 PendingLoads.push_back(Res.second);
5731 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5732 /// operation (as expected), translate it to an SDNode with the specified opcode
5733 /// and return true.
5734 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5736 // Sanity check that it really is a unary floating-point call.
5737 if (I.getNumArgOperands() != 1 ||
5738 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5739 I.getType() != I.getArgOperand(0)->getType() ||
5740 !I.onlyReadsMemory())
5743 SDValue Tmp = getValue(I.getArgOperand(0));
5744 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5748 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5749 /// operation (as expected), translate it to an SDNode with the specified opcode
5750 /// and return true.
5751 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5753 // Sanity check that it really is a binary floating-point call.
5754 if (I.getNumArgOperands() != 2 ||
5755 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5756 I.getType() != I.getArgOperand(0)->getType() ||
5757 I.getType() != I.getArgOperand(1)->getType() ||
5758 !I.onlyReadsMemory())
5761 SDValue Tmp0 = getValue(I.getArgOperand(0));
5762 SDValue Tmp1 = getValue(I.getArgOperand(1));
5763 EVT VT = Tmp0.getValueType();
5764 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5768 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5769 // Handle inline assembly differently.
5770 if (isa<InlineAsm>(I.getCalledValue())) {
5775 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5776 ComputeUsesVAFloatArgument(I, &MMI);
5778 const char *RenameFn = nullptr;
5779 if (Function *F = I.getCalledFunction()) {
5780 if (F->isDeclaration()) {
5781 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5782 if (unsigned IID = II->getIntrinsicID(F)) {
5783 RenameFn = visitIntrinsicCall(I, IID);
5788 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5789 RenameFn = visitIntrinsicCall(I, IID);
5795 // Check for well-known libc/libm calls. If the function is internal, it
5796 // can't be a library call.
5798 if (!F->hasLocalLinkage() && F->hasName() &&
5799 LibInfo->getLibFunc(F->getName(), Func) &&
5800 LibInfo->hasOptimizedCodeGen(Func)) {
5803 case LibFunc::copysign:
5804 case LibFunc::copysignf:
5805 case LibFunc::copysignl:
5806 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5807 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5808 I.getType() == I.getArgOperand(0)->getType() &&
5809 I.getType() == I.getArgOperand(1)->getType() &&
5810 I.onlyReadsMemory()) {
5811 SDValue LHS = getValue(I.getArgOperand(0));
5812 SDValue RHS = getValue(I.getArgOperand(1));
5813 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5814 LHS.getValueType(), LHS, RHS));
5819 case LibFunc::fabsf:
5820 case LibFunc::fabsl:
5821 if (visitUnaryFloatCall(I, ISD::FABS))
5825 case LibFunc::fminf:
5826 case LibFunc::fminl:
5827 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5831 case LibFunc::fmaxf:
5832 case LibFunc::fmaxl:
5833 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5839 if (visitUnaryFloatCall(I, ISD::FSIN))
5845 if (visitUnaryFloatCall(I, ISD::FCOS))
5849 case LibFunc::sqrtf:
5850 case LibFunc::sqrtl:
5851 case LibFunc::sqrt_finite:
5852 case LibFunc::sqrtf_finite:
5853 case LibFunc::sqrtl_finite:
5854 if (visitUnaryFloatCall(I, ISD::FSQRT))
5857 case LibFunc::floor:
5858 case LibFunc::floorf:
5859 case LibFunc::floorl:
5860 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5863 case LibFunc::nearbyint:
5864 case LibFunc::nearbyintf:
5865 case LibFunc::nearbyintl:
5866 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5870 case LibFunc::ceilf:
5871 case LibFunc::ceill:
5872 if (visitUnaryFloatCall(I, ISD::FCEIL))
5876 case LibFunc::rintf:
5877 case LibFunc::rintl:
5878 if (visitUnaryFloatCall(I, ISD::FRINT))
5881 case LibFunc::round:
5882 case LibFunc::roundf:
5883 case LibFunc::roundl:
5884 if (visitUnaryFloatCall(I, ISD::FROUND))
5887 case LibFunc::trunc:
5888 case LibFunc::truncf:
5889 case LibFunc::truncl:
5890 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5894 case LibFunc::log2f:
5895 case LibFunc::log2l:
5896 if (visitUnaryFloatCall(I, ISD::FLOG2))
5900 case LibFunc::exp2f:
5901 case LibFunc::exp2l:
5902 if (visitUnaryFloatCall(I, ISD::FEXP2))
5905 case LibFunc::memcmp:
5906 if (visitMemCmpCall(I))
5909 case LibFunc::memchr:
5910 if (visitMemChrCall(I))
5913 case LibFunc::strcpy:
5914 if (visitStrCpyCall(I, false))
5917 case LibFunc::stpcpy:
5918 if (visitStrCpyCall(I, true))
5921 case LibFunc::strcmp:
5922 if (visitStrCmpCall(I))
5925 case LibFunc::strlen:
5926 if (visitStrLenCall(I))
5929 case LibFunc::strnlen:
5930 if (visitStrNLenCall(I))
5939 Callee = getValue(I.getCalledValue());
5941 Callee = DAG.getExternalSymbol(
5943 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5945 // Check if we can potentially perform a tail call. More detailed checking is
5946 // be done within LowerCallTo, after more information about the call is known.
5947 LowerCallTo(&I, Callee, I.isTailCall());
5952 /// AsmOperandInfo - This contains information for each constraint that we are
5954 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5956 /// CallOperand - If this is the result output operand or a clobber
5957 /// this is null, otherwise it is the incoming operand to the CallInst.
5958 /// This gets modified as the asm is processed.
5959 SDValue CallOperand;
5961 /// AssignedRegs - If this is a register or register class operand, this
5962 /// contains the set of register corresponding to the operand.
5963 RegsForValue AssignedRegs;
5965 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5966 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5969 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5970 /// corresponds to. If there is no Value* for this operand, it returns
5972 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5973 const DataLayout &DL) const {
5974 if (!CallOperandVal) return MVT::Other;
5976 if (isa<BasicBlock>(CallOperandVal))
5977 return TLI.getPointerTy(DL);
5979 llvm::Type *OpTy = CallOperandVal->getType();
5981 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5982 // If this is an indirect operand, the operand is a pointer to the
5985 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5987 report_fatal_error("Indirect operand for inline asm not a pointer!");
5988 OpTy = PtrTy->getElementType();
5991 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5992 if (StructType *STy = dyn_cast<StructType>(OpTy))
5993 if (STy->getNumElements() == 1)
5994 OpTy = STy->getElementType(0);
5996 // If OpTy is not a single value, it may be a struct/union that we
5997 // can tile with integers.
5998 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5999 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
6008 OpTy = IntegerType::get(Context, BitSize);
6013 return TLI.getValueType(DL, OpTy, true);
6017 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6019 } // end anonymous namespace
6021 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6022 /// specified operand. We prefer to assign virtual registers, to allow the
6023 /// register allocator to handle the assignment process. However, if the asm
6024 /// uses features that we can't model on machineinstrs, we have SDISel do the
6025 /// allocation. This produces generally horrible, but correct, code.
6027 /// OpInfo describes the operand.
6029 static void GetRegistersForValue(SelectionDAG &DAG,
6030 const TargetLowering &TLI,
6032 SDISelAsmOperandInfo &OpInfo) {
6033 LLVMContext &Context = *DAG.getContext();
6035 MachineFunction &MF = DAG.getMachineFunction();
6036 SmallVector<unsigned, 4> Regs;
6038 // If this is a constraint for a single physreg, or a constraint for a
6039 // register class, find it.
6040 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6041 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6042 OpInfo.ConstraintCode,
6043 OpInfo.ConstraintVT);
6045 unsigned NumRegs = 1;
6046 if (OpInfo.ConstraintVT != MVT::Other) {
6047 // If this is a FP input in an integer register (or visa versa) insert a bit
6048 // cast of the input value. More generally, handle any case where the input
6049 // value disagrees with the register class we plan to stick this in.
6050 if (OpInfo.Type == InlineAsm::isInput &&
6051 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6052 // Try to convert to the first EVT that the reg class contains. If the
6053 // types are identical size, use a bitcast to convert (e.g. two differing
6055 MVT RegVT = *PhysReg.second->vt_begin();
6056 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6057 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6058 RegVT, OpInfo.CallOperand);
6059 OpInfo.ConstraintVT = RegVT;
6060 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6061 // If the input is a FP value and we want it in FP registers, do a
6062 // bitcast to the corresponding integer type. This turns an f64 value
6063 // into i64, which can be passed with two i32 values on a 32-bit
6065 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6066 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6067 RegVT, OpInfo.CallOperand);
6068 OpInfo.ConstraintVT = RegVT;
6072 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6076 EVT ValueVT = OpInfo.ConstraintVT;
6078 // If this is a constraint for a specific physical register, like {r17},
6080 if (unsigned AssignedReg = PhysReg.first) {
6081 const TargetRegisterClass *RC = PhysReg.second;
6082 if (OpInfo.ConstraintVT == MVT::Other)
6083 ValueVT = *RC->vt_begin();
6085 // Get the actual register value type. This is important, because the user
6086 // may have asked for (e.g.) the AX register in i32 type. We need to
6087 // remember that AX is actually i16 to get the right extension.
6088 RegVT = *RC->vt_begin();
6090 // This is a explicit reference to a physical register.
6091 Regs.push_back(AssignedReg);
6093 // If this is an expanded reference, add the rest of the regs to Regs.
6095 TargetRegisterClass::iterator I = RC->begin();
6096 for (; *I != AssignedReg; ++I)
6097 assert(I != RC->end() && "Didn't find reg!");
6099 // Already added the first reg.
6101 for (; NumRegs; --NumRegs, ++I) {
6102 assert(I != RC->end() && "Ran out of registers to allocate!");
6107 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6111 // Otherwise, if this was a reference to an LLVM register class, create vregs
6112 // for this reference.
6113 if (const TargetRegisterClass *RC = PhysReg.second) {
6114 RegVT = *RC->vt_begin();
6115 if (OpInfo.ConstraintVT == MVT::Other)
6118 // Create the appropriate number of virtual registers.
6119 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6120 for (; NumRegs; --NumRegs)
6121 Regs.push_back(RegInfo.createVirtualRegister(RC));
6123 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6127 // Otherwise, we couldn't allocate enough registers for this.
6130 /// visitInlineAsm - Handle a call to an InlineAsm object.
6132 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6133 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6135 /// ConstraintOperands - Information about all of the constraints.
6136 SDISelAsmOperandInfoVector ConstraintOperands;
6138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6139 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6140 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6142 bool hasMemory = false;
6144 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6145 unsigned ResNo = 0; // ResNo - The result number of the next output.
6146 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6147 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6148 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6150 MVT OpVT = MVT::Other;
6152 // Compute the value type for each operand.
6153 switch (OpInfo.Type) {
6154 case InlineAsm::isOutput:
6155 // Indirect outputs just consume an argument.
6156 if (OpInfo.isIndirect) {
6157 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6161 // The return value of the call is this value. As such, there is no
6162 // corresponding argument.
6163 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6164 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6165 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6166 STy->getElementType(ResNo));
6168 assert(ResNo == 0 && "Asm only has one result!");
6169 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6173 case InlineAsm::isInput:
6174 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6176 case InlineAsm::isClobber:
6181 // If this is an input or an indirect output, process the call argument.
6182 // BasicBlocks are labels, currently appearing only in asm's.
6183 if (OpInfo.CallOperandVal) {
6184 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6185 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6187 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6190 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6191 DAG.getDataLayout()).getSimpleVT();
6194 OpInfo.ConstraintVT = OpVT;
6196 // Indirect operand accesses access memory.
6197 if (OpInfo.isIndirect)
6200 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6201 TargetLowering::ConstraintType
6202 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6203 if (CType == TargetLowering::C_Memory) {
6211 SDValue Chain, Flag;
6213 // We won't need to flush pending loads if this asm doesn't touch
6214 // memory and is nonvolatile.
6215 if (hasMemory || IA->hasSideEffects())
6218 Chain = DAG.getRoot();
6220 // Second pass over the constraints: compute which constraint option to use
6221 // and assign registers to constraints that want a specific physreg.
6222 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6223 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6225 // If this is an output operand with a matching input operand, look up the
6226 // matching input. If their types mismatch, e.g. one is an integer, the
6227 // other is floating point, or their sizes are different, flag it as an
6229 if (OpInfo.hasMatchingInput()) {
6230 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6232 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6233 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6234 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6235 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6236 OpInfo.ConstraintVT);
6237 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6238 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6239 Input.ConstraintVT);
6240 if ((OpInfo.ConstraintVT.isInteger() !=
6241 Input.ConstraintVT.isInteger()) ||
6242 (MatchRC.second != InputRC.second)) {
6243 report_fatal_error("Unsupported asm: input constraint"
6244 " with a matching output constraint of"
6245 " incompatible type!");
6247 Input.ConstraintVT = OpInfo.ConstraintVT;
6251 // Compute the constraint code and ConstraintType to use.
6252 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6254 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6255 OpInfo.Type == InlineAsm::isClobber)
6258 // If this is a memory input, and if the operand is not indirect, do what we
6259 // need to to provide an address for the memory input.
6260 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6261 !OpInfo.isIndirect) {
6262 assert((OpInfo.isMultipleAlternative ||
6263 (OpInfo.Type == InlineAsm::isInput)) &&
6264 "Can only indirectify direct input operands!");
6266 // Memory operands really want the address of the value. If we don't have
6267 // an indirect input, put it in the constpool if we can, otherwise spill
6268 // it to a stack slot.
6269 // TODO: This isn't quite right. We need to handle these according to
6270 // the addressing mode that the constraint wants. Also, this may take
6271 // an additional register for the computation and we don't want that
6274 // If the operand is a float, integer, or vector constant, spill to a
6275 // constant pool entry to get its address.
6276 const Value *OpVal = OpInfo.CallOperandVal;
6277 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6278 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6279 OpInfo.CallOperand = DAG.getConstantPool(
6280 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6282 // Otherwise, create a stack slot and emit a store to it before the
6284 Type *Ty = OpVal->getType();
6285 auto &DL = DAG.getDataLayout();
6286 uint64_t TySize = DL.getTypeAllocSize(Ty);
6287 unsigned Align = DL.getPrefTypeAlignment(Ty);
6288 MachineFunction &MF = DAG.getMachineFunction();
6289 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6291 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6292 Chain = DAG.getStore(
6293 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6294 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6296 OpInfo.CallOperand = StackSlot;
6299 // There is no longer a Value* corresponding to this operand.
6300 OpInfo.CallOperandVal = nullptr;
6302 // It is now an indirect operand.
6303 OpInfo.isIndirect = true;
6306 // If this constraint is for a specific register, allocate it before
6308 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6309 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6312 // Second pass - Loop over all of the operands, assigning virtual or physregs
6313 // to register class operands.
6314 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6315 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6317 // C_Register operands have already been allocated, Other/Memory don't need
6319 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6320 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6323 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6324 std::vector<SDValue> AsmNodeOperands;
6325 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6326 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6327 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6329 // If we have a !srcloc metadata node associated with it, we want to attach
6330 // this to the ultimately generated inline asm machineinstr. To do this, we
6331 // pass in the third operand as this (potentially null) inline asm MDNode.
6332 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6333 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6335 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6336 // bits as operand 3.
6337 unsigned ExtraInfo = 0;
6338 if (IA->hasSideEffects())
6339 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6340 if (IA->isAlignStack())
6341 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6342 // Set the asm dialect.
6343 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6345 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6346 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6347 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6349 // Compute the constraint code and ConstraintType to use.
6350 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6352 // Ideally, we would only check against memory constraints. However, the
6353 // meaning of an other constraint can be target-specific and we can't easily
6354 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6355 // for other constriants as well.
6356 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6357 OpInfo.ConstraintType == TargetLowering::C_Other) {
6358 if (OpInfo.Type == InlineAsm::isInput)
6359 ExtraInfo |= InlineAsm::Extra_MayLoad;
6360 else if (OpInfo.Type == InlineAsm::isOutput)
6361 ExtraInfo |= InlineAsm::Extra_MayStore;
6362 else if (OpInfo.Type == InlineAsm::isClobber)
6363 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6367 AsmNodeOperands.push_back(DAG.getTargetConstant(
6368 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6370 // Loop over all of the inputs, copying the operand values into the
6371 // appropriate registers and processing the output regs.
6372 RegsForValue RetValRegs;
6374 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6375 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6377 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6378 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6380 switch (OpInfo.Type) {
6381 case InlineAsm::isOutput: {
6382 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6383 OpInfo.ConstraintType != TargetLowering::C_Register) {
6384 // Memory output, or 'other' output (e.g. 'X' constraint).
6385 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6387 unsigned ConstraintID =
6388 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6389 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6390 "Failed to convert memory constraint code to constraint id.");
6392 // Add information to the INLINEASM node to know about this output.
6393 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6394 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6395 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6397 AsmNodeOperands.push_back(OpInfo.CallOperand);
6401 // Otherwise, this is a register or register class output.
6403 // Copy the output from the appropriate register. Find a register that
6405 if (OpInfo.AssignedRegs.Regs.empty()) {
6406 LLVMContext &Ctx = *DAG.getContext();
6407 Ctx.emitError(CS.getInstruction(),
6408 "couldn't allocate output register for constraint '" +
6409 Twine(OpInfo.ConstraintCode) + "'");
6413 // If this is an indirect operand, store through the pointer after the
6415 if (OpInfo.isIndirect) {
6416 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6417 OpInfo.CallOperandVal));
6419 // This is the result value of the call.
6420 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6421 // Concatenate this output onto the outputs list.
6422 RetValRegs.append(OpInfo.AssignedRegs);
6425 // Add information to the INLINEASM node to know that this register is
6428 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6429 ? InlineAsm::Kind_RegDefEarlyClobber
6430 : InlineAsm::Kind_RegDef,
6431 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6434 case InlineAsm::isInput: {
6435 SDValue InOperandVal = OpInfo.CallOperand;
6437 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6438 // If this is required to match an output register we have already set,
6439 // just use its register.
6440 unsigned OperandNo = OpInfo.getMatchedOperand();
6442 // Scan until we find the definition we already emitted of this operand.
6443 // When we find it, create a RegsForValue operand.
6444 unsigned CurOp = InlineAsm::Op_FirstOperand;
6445 for (; OperandNo; --OperandNo) {
6446 // Advance to the next operand.
6448 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6449 assert((InlineAsm::isRegDefKind(OpFlag) ||
6450 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6451 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6452 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6456 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6457 if (InlineAsm::isRegDefKind(OpFlag) ||
6458 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6459 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6460 if (OpInfo.isIndirect) {
6461 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6462 LLVMContext &Ctx = *DAG.getContext();
6463 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6464 " don't know how to handle tied "
6465 "indirect register inputs");
6469 RegsForValue MatchedRegs;
6470 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6471 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6472 MatchedRegs.RegVTs.push_back(RegVT);
6473 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6474 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6476 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6477 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6479 LLVMContext &Ctx = *DAG.getContext();
6480 Ctx.emitError(CS.getInstruction(),
6481 "inline asm error: This value"
6482 " type register class is not natively supported!");
6486 SDLoc dl = getCurSDLoc();
6487 // Use the produced MatchedRegs object to
6488 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6489 Chain, &Flag, CS.getInstruction());
6490 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6491 true, OpInfo.getMatchedOperand(), dl,
6492 DAG, AsmNodeOperands);
6496 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6497 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6498 "Unexpected number of operands");
6499 // Add information to the INLINEASM node to know about this input.
6500 // See InlineAsm.h isUseOperandTiedToDef.
6501 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6502 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6503 OpInfo.getMatchedOperand());
6504 AsmNodeOperands.push_back(DAG.getTargetConstant(
6505 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6506 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6510 // Treat indirect 'X' constraint as memory.
6511 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6513 OpInfo.ConstraintType = TargetLowering::C_Memory;
6515 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6516 std::vector<SDValue> Ops;
6517 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6520 LLVMContext &Ctx = *DAG.getContext();
6521 Ctx.emitError(CS.getInstruction(),
6522 "invalid operand for inline asm constraint '" +
6523 Twine(OpInfo.ConstraintCode) + "'");
6527 // Add information to the INLINEASM node to know about this input.
6528 unsigned ResOpType =
6529 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6530 AsmNodeOperands.push_back(DAG.getTargetConstant(
6531 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6532 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6536 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6537 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6538 assert(InOperandVal.getValueType() ==
6539 TLI.getPointerTy(DAG.getDataLayout()) &&
6540 "Memory operands expect pointer values");
6542 unsigned ConstraintID =
6543 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6544 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6545 "Failed to convert memory constraint code to constraint id.");
6547 // Add information to the INLINEASM node to know about this input.
6548 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6549 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6550 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6553 AsmNodeOperands.push_back(InOperandVal);
6557 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6558 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6559 "Unknown constraint type!");
6561 // TODO: Support this.
6562 if (OpInfo.isIndirect) {
6563 LLVMContext &Ctx = *DAG.getContext();
6564 Ctx.emitError(CS.getInstruction(),
6565 "Don't know how to handle indirect register inputs yet "
6566 "for constraint '" +
6567 Twine(OpInfo.ConstraintCode) + "'");
6571 // Copy the input into the appropriate registers.
6572 if (OpInfo.AssignedRegs.Regs.empty()) {
6573 LLVMContext &Ctx = *DAG.getContext();
6574 Ctx.emitError(CS.getInstruction(),
6575 "couldn't allocate input reg for constraint '" +
6576 Twine(OpInfo.ConstraintCode) + "'");
6580 SDLoc dl = getCurSDLoc();
6582 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6583 Chain, &Flag, CS.getInstruction());
6585 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6586 dl, DAG, AsmNodeOperands);
6589 case InlineAsm::isClobber: {
6590 // Add the clobbered value to the operand list, so that the register
6591 // allocator is aware that the physreg got clobbered.
6592 if (!OpInfo.AssignedRegs.Regs.empty())
6593 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6594 false, 0, getCurSDLoc(), DAG,
6601 // Finish up input operands. Set the input chain and add the flag last.
6602 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6603 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6605 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6606 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6607 Flag = Chain.getValue(1);
6609 // If this asm returns a register value, copy the result from that register
6610 // and set it as the value of the call.
6611 if (!RetValRegs.Regs.empty()) {
6612 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6613 Chain, &Flag, CS.getInstruction());
6615 // FIXME: Why don't we do this for inline asms with MRVs?
6616 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6617 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6619 // If any of the results of the inline asm is a vector, it may have the
6620 // wrong width/num elts. This can happen for register classes that can
6621 // contain multiple different value types. The preg or vreg allocated may
6622 // not have the same VT as was expected. Convert it to the right type
6623 // with bit_convert.
6624 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6625 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6628 } else if (ResultType != Val.getValueType() &&
6629 ResultType.isInteger() && Val.getValueType().isInteger()) {
6630 // If a result value was tied to an input value, the computed result may
6631 // have a wider width than the expected result. Extract the relevant
6633 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6636 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6639 setValue(CS.getInstruction(), Val);
6640 // Don't need to use this as a chain in this case.
6641 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6645 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6647 // Process indirect outputs, first output all of the flagged copies out of
6649 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6650 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6651 const Value *Ptr = IndirectStoresToEmit[i].second;
6652 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6654 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6657 // Emit the non-flagged stores from the physregs.
6658 SmallVector<SDValue, 8> OutChains;
6659 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6660 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6661 StoresToEmit[i].first,
6662 getValue(StoresToEmit[i].second),
6663 MachinePointerInfo(StoresToEmit[i].second),
6665 OutChains.push_back(Val);
6668 if (!OutChains.empty())
6669 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6674 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6675 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6676 MVT::Other, getRoot(),
6677 getValue(I.getArgOperand(0)),
6678 DAG.getSrcValue(I.getArgOperand(0))));
6681 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6683 const DataLayout &DL = DAG.getDataLayout();
6684 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6685 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6686 DAG.getSrcValue(I.getOperand(0)),
6687 DL.getABITypeAlignment(I.getType()));
6689 DAG.setRoot(V.getValue(1));
6692 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6693 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6694 MVT::Other, getRoot(),
6695 getValue(I.getArgOperand(0)),
6696 DAG.getSrcValue(I.getArgOperand(0))));
6699 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6700 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6701 MVT::Other, getRoot(),
6702 getValue(I.getArgOperand(0)),
6703 getValue(I.getArgOperand(1)),
6704 DAG.getSrcValue(I.getArgOperand(0)),
6705 DAG.getSrcValue(I.getArgOperand(1))));
6708 /// \brief Lower an argument list according to the target calling convention.
6710 /// \return A tuple of <return-value, token-chain>
6712 /// This is a helper for lowering intrinsics that follow a target calling
6713 /// convention or require stack pointer adjustment. Only a subset of the
6714 /// intrinsic's operands need to participate in the calling convention.
6715 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6716 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6717 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6718 TargetLowering::ArgListTy Args;
6719 Args.reserve(NumArgs);
6721 // Populate the argument list.
6722 // Attributes for args start at offset 1, after the return attribute.
6723 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6724 ArgI != ArgE; ++ArgI) {
6725 const Value *V = CS->getOperand(ArgI);
6727 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6729 TargetLowering::ArgListEntry Entry;
6730 Entry.Node = getValue(V);
6731 Entry.Ty = V->getType();
6732 Entry.setAttributes(&CS, AttrI);
6733 Args.push_back(Entry);
6736 TargetLowering::CallLoweringInfo CLI(DAG);
6737 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6738 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6739 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6741 return lowerInvokable(CLI, EHPadBB);
6744 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6745 /// or patchpoint target node's operand list.
6747 /// Constants are converted to TargetConstants purely as an optimization to
6748 /// avoid constant materialization and register allocation.
6750 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6751 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6752 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6753 /// address materialization and register allocation, but may also be required
6754 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6755 /// alloca in the entry block, then the runtime may assume that the alloca's
6756 /// StackMap location can be read immediately after compilation and that the
6757 /// location is valid at any point during execution (this is similar to the
6758 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6759 /// only available in a register, then the runtime would need to trap when
6760 /// execution reaches the StackMap in order to read the alloca's location.
6761 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6762 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6763 SelectionDAGBuilder &Builder) {
6764 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6765 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6768 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6770 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6771 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6772 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6773 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6774 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6776 Ops.push_back(OpVal);
6780 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6781 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6782 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6783 // [live variables...])
6785 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6787 SDValue Chain, InFlag, Callee, NullPtr;
6788 SmallVector<SDValue, 32> Ops;
6790 SDLoc DL = getCurSDLoc();
6791 Callee = getValue(CI.getCalledValue());
6792 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6794 // The stackmap intrinsic only records the live variables (the arguemnts
6795 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6796 // intrinsic, this won't be lowered to a function call. This means we don't
6797 // have to worry about calling conventions and target specific lowering code.
6798 // Instead we perform the call lowering right here.
6800 // chain, flag = CALLSEQ_START(chain, 0)
6801 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6802 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6804 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6805 InFlag = Chain.getValue(1);
6807 // Add the <id> and <numBytes> constants.
6808 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6809 Ops.push_back(DAG.getTargetConstant(
6810 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6811 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6812 Ops.push_back(DAG.getTargetConstant(
6813 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6816 // Push live variables for the stack map.
6817 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6819 // We are not pushing any register mask info here on the operands list,
6820 // because the stackmap doesn't clobber anything.
6822 // Push the chain and the glue flag.
6823 Ops.push_back(Chain);
6824 Ops.push_back(InFlag);
6826 // Create the STACKMAP node.
6827 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6828 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6829 Chain = SDValue(SM, 0);
6830 InFlag = Chain.getValue(1);
6832 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6834 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6836 // Set the root to the target-lowered call chain.
6839 // Inform the Frame Information that we have a stackmap in this function.
6840 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6843 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6844 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6845 const BasicBlock *EHPadBB) {
6846 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6851 // [live variables...])
6853 CallingConv::ID CC = CS.getCallingConv();
6854 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6855 bool HasDef = !CS->getType()->isVoidTy();
6856 SDLoc dl = getCurSDLoc();
6857 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6859 // Handle immediate and symbolic callees.
6860 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6861 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6863 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6864 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6865 SDLoc(SymbolicCallee),
6866 SymbolicCallee->getValueType(0));
6868 // Get the real number of arguments participating in the call <numArgs>
6869 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6870 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6872 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6873 // Intrinsics include all meta-operands up to but not including CC.
6874 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6875 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6876 "Not enough arguments provided to the patchpoint intrinsic");
6878 // For AnyRegCC the arguments are lowered later on manually.
6879 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6881 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6882 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6883 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6885 SDNode *CallEnd = Result.second.getNode();
6886 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6887 CallEnd = CallEnd->getOperand(0).getNode();
6889 /// Get a call instruction from the call sequence chain.
6890 /// Tail calls are not allowed.
6891 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6892 "Expected a callseq node.");
6893 SDNode *Call = CallEnd->getOperand(0).getNode();
6894 bool HasGlue = Call->getGluedNode();
6896 // Replace the target specific call node with the patchable intrinsic.
6897 SmallVector<SDValue, 8> Ops;
6899 // Add the <id> and <numBytes> constants.
6900 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6901 Ops.push_back(DAG.getTargetConstant(
6902 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6903 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6904 Ops.push_back(DAG.getTargetConstant(
6905 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6909 Ops.push_back(Callee);
6911 // Adjust <numArgs> to account for any arguments that have been passed on the
6913 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6914 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6915 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6916 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6918 // Add the calling convention
6919 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6921 // Add the arguments we omitted previously. The register allocator should
6922 // place these in any free register.
6924 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6925 Ops.push_back(getValue(CS.getArgument(i)));
6927 // Push the arguments from the call instruction up to the register mask.
6928 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6929 Ops.append(Call->op_begin() + 2, e);
6931 // Push live variables for the stack map.
6932 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6934 // Push the register mask info.
6936 Ops.push_back(*(Call->op_end()-2));
6938 Ops.push_back(*(Call->op_end()-1));
6940 // Push the chain (this is originally the first operand of the call, but
6941 // becomes now the last or second to last operand).
6942 Ops.push_back(*(Call->op_begin()));
6944 // Push the glue flag (last operand).
6946 Ops.push_back(*(Call->op_end()-1));
6949 if (IsAnyRegCC && HasDef) {
6950 // Create the return types based on the intrinsic definition
6951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6952 SmallVector<EVT, 3> ValueVTs;
6953 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6954 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6956 // There is always a chain and a glue type at the end
6957 ValueVTs.push_back(MVT::Other);
6958 ValueVTs.push_back(MVT::Glue);
6959 NodeTys = DAG.getVTList(ValueVTs);
6961 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6963 // Replace the target specific call node with a PATCHPOINT node.
6964 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6967 // Update the NodeMap.
6970 setValue(CS.getInstruction(), SDValue(MN, 0));
6972 setValue(CS.getInstruction(), Result.first);
6975 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6976 // call sequence. Furthermore the location of the chain and glue can change
6977 // when the AnyReg calling convention is used and the intrinsic returns a
6979 if (IsAnyRegCC && HasDef) {
6980 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6981 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6982 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6984 DAG.ReplaceAllUsesWith(Call, MN);
6985 DAG.DeleteNode(Call);
6987 // Inform the Frame Information that we have a patchpoint in this function.
6988 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6991 /// Returns an AttributeSet representing the attributes applied to the return
6992 /// value of the given call.
6993 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6994 SmallVector<Attribute::AttrKind, 2> Attrs;
6996 Attrs.push_back(Attribute::SExt);
6998 Attrs.push_back(Attribute::ZExt);
7000 Attrs.push_back(Attribute::InReg);
7002 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7006 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7007 /// implementation, which just calls LowerCall.
7008 /// FIXME: When all targets are
7009 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7010 std::pair<SDValue, SDValue>
7011 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7012 // Handle the incoming return values from the call.
7014 Type *OrigRetTy = CLI.RetTy;
7015 SmallVector<EVT, 4> RetTys;
7016 SmallVector<uint64_t, 4> Offsets;
7017 auto &DL = CLI.DAG.getDataLayout();
7018 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7020 SmallVector<ISD::OutputArg, 4> Outs;
7021 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7023 bool CanLowerReturn =
7024 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7025 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7027 SDValue DemoteStackSlot;
7028 int DemoteStackIdx = -100;
7029 if (!CanLowerReturn) {
7030 // FIXME: equivalent assert?
7031 // assert(!CS.hasInAllocaArgument() &&
7032 // "sret demotion is incompatible with inalloca");
7033 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7034 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7035 MachineFunction &MF = CLI.DAG.getMachineFunction();
7036 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7037 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7039 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7041 Entry.Node = DemoteStackSlot;
7042 Entry.Ty = StackSlotPtrType;
7043 Entry.isSExt = false;
7044 Entry.isZExt = false;
7045 Entry.isInReg = false;
7046 Entry.isSRet = true;
7047 Entry.isNest = false;
7048 Entry.isByVal = false;
7049 Entry.isReturned = false;
7050 Entry.Alignment = Align;
7051 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7052 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7054 // sret demotion isn't compatible with tail-calls, since the sret argument
7055 // points into the callers stack frame.
7056 CLI.IsTailCall = false;
7058 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7060 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7061 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7062 for (unsigned i = 0; i != NumRegs; ++i) {
7063 ISD::InputArg MyFlags;
7064 MyFlags.VT = RegisterVT;
7066 MyFlags.Used = CLI.IsReturnValueUsed;
7068 MyFlags.Flags.setSExt();
7070 MyFlags.Flags.setZExt();
7072 MyFlags.Flags.setInReg();
7073 CLI.Ins.push_back(MyFlags);
7078 // Handle all of the outgoing arguments.
7080 CLI.OutVals.clear();
7081 ArgListTy &Args = CLI.getArgs();
7082 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7083 SmallVector<EVT, 4> ValueVTs;
7084 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7085 Type *FinalType = Args[i].Ty;
7086 if (Args[i].isByVal)
7087 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7088 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7089 FinalType, CLI.CallConv, CLI.IsVarArg);
7090 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7092 EVT VT = ValueVTs[Value];
7093 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7094 SDValue Op = SDValue(Args[i].Node.getNode(),
7095 Args[i].Node.getResNo() + Value);
7096 ISD::ArgFlagsTy Flags;
7097 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7103 if (Args[i].isInReg)
7107 if (Args[i].isByVal)
7109 if (Args[i].isInAlloca) {
7110 Flags.setInAlloca();
7111 // Set the byval flag for CCAssignFn callbacks that don't know about
7112 // inalloca. This way we can know how many bytes we should've allocated
7113 // and how many bytes a callee cleanup function will pop. If we port
7114 // inalloca to more targets, we'll have to add custom inalloca handling
7115 // in the various CC lowering callbacks.
7118 if (Args[i].isByVal || Args[i].isInAlloca) {
7119 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7120 Type *ElementTy = Ty->getElementType();
7121 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7122 // For ByVal, alignment should come from FE. BE will guess if this
7123 // info is not there but there are cases it cannot get right.
7124 unsigned FrameAlign;
7125 if (Args[i].Alignment)
7126 FrameAlign = Args[i].Alignment;
7128 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7129 Flags.setByValAlign(FrameAlign);
7134 Flags.setInConsecutiveRegs();
7135 Flags.setOrigAlign(OriginalAlignment);
7137 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7138 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7139 SmallVector<SDValue, 4> Parts(NumParts);
7140 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7143 ExtendKind = ISD::SIGN_EXTEND;
7144 else if (Args[i].isZExt)
7145 ExtendKind = ISD::ZERO_EXTEND;
7147 // Conservatively only handle 'returned' on non-vectors for now
7148 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7149 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7150 "unexpected use of 'returned'");
7151 // Before passing 'returned' to the target lowering code, ensure that
7152 // either the register MVT and the actual EVT are the same size or that
7153 // the return value and argument are extended in the same way; in these
7154 // cases it's safe to pass the argument register value unchanged as the
7155 // return register value (although it's at the target's option whether
7157 // TODO: allow code generation to take advantage of partially preserved
7158 // registers rather than clobbering the entire register when the
7159 // parameter extension method is not compatible with the return
7161 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7162 (ExtendKind != ISD::ANY_EXTEND &&
7163 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7164 Flags.setReturned();
7167 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7168 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7170 for (unsigned j = 0; j != NumParts; ++j) {
7171 // if it isn't first piece, alignment must be 1
7172 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7173 i < CLI.NumFixedArgs,
7174 i, j*Parts[j].getValueType().getStoreSize());
7175 if (NumParts > 1 && j == 0)
7176 MyFlags.Flags.setSplit();
7178 MyFlags.Flags.setOrigAlign(1);
7180 CLI.Outs.push_back(MyFlags);
7181 CLI.OutVals.push_back(Parts[j]);
7184 if (NeedsRegBlock && Value == NumValues - 1)
7185 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7189 SmallVector<SDValue, 4> InVals;
7190 CLI.Chain = LowerCall(CLI, InVals);
7192 // Verify that the target's LowerCall behaved as expected.
7193 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7194 "LowerCall didn't return a valid chain!");
7195 assert((!CLI.IsTailCall || InVals.empty()) &&
7196 "LowerCall emitted a return value for a tail call!");
7197 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7198 "LowerCall didn't emit the correct number of values!");
7200 // For a tail call, the return value is merely live-out and there aren't
7201 // any nodes in the DAG representing it. Return a special value to
7202 // indicate that a tail call has been emitted and no more Instructions
7203 // should be processed in the current block.
7204 if (CLI.IsTailCall) {
7205 CLI.DAG.setRoot(CLI.Chain);
7206 return std::make_pair(SDValue(), SDValue());
7209 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7210 assert(InVals[i].getNode() &&
7211 "LowerCall emitted a null value!");
7212 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7213 "LowerCall emitted a value with the wrong type!");
7216 SmallVector<SDValue, 4> ReturnValues;
7217 if (!CanLowerReturn) {
7218 // The instruction result is the result of loading from the
7219 // hidden sret parameter.
7220 SmallVector<EVT, 1> PVTs;
7221 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7223 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7224 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7225 EVT PtrVT = PVTs[0];
7227 unsigned NumValues = RetTys.size();
7228 ReturnValues.resize(NumValues);
7229 SmallVector<SDValue, 4> Chains(NumValues);
7231 for (unsigned i = 0; i < NumValues; ++i) {
7232 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7233 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7235 SDValue L = CLI.DAG.getLoad(
7236 RetTys[i], CLI.DL, CLI.Chain, Add,
7237 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7238 DemoteStackIdx, Offsets[i]),
7239 false, false, false, 1);
7240 ReturnValues[i] = L;
7241 Chains[i] = L.getValue(1);
7244 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7246 // Collect the legal value parts into potentially illegal values
7247 // that correspond to the original function's return values.
7248 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7250 AssertOp = ISD::AssertSext;
7251 else if (CLI.RetZExt)
7252 AssertOp = ISD::AssertZext;
7253 unsigned CurReg = 0;
7254 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7256 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7257 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7259 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7260 NumRegs, RegisterVT, VT, nullptr,
7265 // For a function returning void, there is no return value. We can't create
7266 // such a node, so we just return a null return value in that case. In
7267 // that case, nothing will actually look at the value.
7268 if (ReturnValues.empty())
7269 return std::make_pair(SDValue(), CLI.Chain);
7272 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7273 CLI.DAG.getVTList(RetTys), ReturnValues);
7274 return std::make_pair(Res, CLI.Chain);
7277 void TargetLowering::LowerOperationWrapper(SDNode *N,
7278 SmallVectorImpl<SDValue> &Results,
7279 SelectionDAG &DAG) const {
7280 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7282 Results.push_back(Res);
7285 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7286 llvm_unreachable("LowerOperation not implemented for this target!");
7290 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7291 SDValue Op = getNonRegisterValue(V);
7292 assert((Op.getOpcode() != ISD::CopyFromReg ||
7293 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7294 "Copy from a reg to the same reg!");
7295 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7298 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7300 SDValue Chain = DAG.getEntryNode();
7302 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7303 FuncInfo.PreferredExtendType.end())
7305 : FuncInfo.PreferredExtendType[V];
7306 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7307 PendingExports.push_back(Chain);
7310 #include "llvm/CodeGen/SelectionDAGISel.h"
7312 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7313 /// entry block, return true. This includes arguments used by switches, since
7314 /// the switch may expand into multiple basic blocks.
7315 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7316 // With FastISel active, we may be splitting blocks, so force creation
7317 // of virtual registers for all non-dead arguments.
7319 return A->use_empty();
7321 const BasicBlock &Entry = A->getParent()->front();
7322 for (const User *U : A->users())
7323 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7324 return false; // Use not in entry block.
7329 void SelectionDAGISel::LowerArguments(const Function &F) {
7330 SelectionDAG &DAG = SDB->DAG;
7331 SDLoc dl = SDB->getCurSDLoc();
7332 const DataLayout &DL = DAG.getDataLayout();
7333 SmallVector<ISD::InputArg, 16> Ins;
7335 if (!FuncInfo->CanLowerReturn) {
7336 // Put in an sret pointer parameter before all the other parameters.
7337 SmallVector<EVT, 1> ValueVTs;
7338 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7339 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7341 // NOTE: Assuming that a pointer will never break down to more than one VT
7343 ISD::ArgFlagsTy Flags;
7345 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7346 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7347 ISD::InputArg::NoArgIndex, 0);
7348 Ins.push_back(RetArg);
7351 // Set up the incoming argument description vector.
7353 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7354 I != E; ++I, ++Idx) {
7355 SmallVector<EVT, 4> ValueVTs;
7356 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7357 bool isArgValueUsed = !I->use_empty();
7358 unsigned PartBase = 0;
7359 Type *FinalType = I->getType();
7360 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7361 FinalType = cast<PointerType>(FinalType)->getElementType();
7362 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7363 FinalType, F.getCallingConv(), F.isVarArg());
7364 for (unsigned Value = 0, NumValues = ValueVTs.size();
7365 Value != NumValues; ++Value) {
7366 EVT VT = ValueVTs[Value];
7367 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7368 ISD::ArgFlagsTy Flags;
7369 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7371 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7373 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7375 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7377 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7379 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7381 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7382 Flags.setInAlloca();
7383 // Set the byval flag for CCAssignFn callbacks that don't know about
7384 // inalloca. This way we can know how many bytes we should've allocated
7385 // and how many bytes a callee cleanup function will pop. If we port
7386 // inalloca to more targets, we'll have to add custom inalloca handling
7387 // in the various CC lowering callbacks.
7390 if (Flags.isByVal() || Flags.isInAlloca()) {
7391 PointerType *Ty = cast<PointerType>(I->getType());
7392 Type *ElementTy = Ty->getElementType();
7393 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7394 // For ByVal, alignment should be passed from FE. BE will guess if
7395 // this info is not there but there are cases it cannot get right.
7396 unsigned FrameAlign;
7397 if (F.getParamAlignment(Idx))
7398 FrameAlign = F.getParamAlignment(Idx);
7400 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7401 Flags.setByValAlign(FrameAlign);
7403 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7406 Flags.setInConsecutiveRegs();
7407 Flags.setOrigAlign(OriginalAlignment);
7409 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7410 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7411 for (unsigned i = 0; i != NumRegs; ++i) {
7412 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7413 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7414 if (NumRegs > 1 && i == 0)
7415 MyFlags.Flags.setSplit();
7416 // if it isn't first piece, alignment must be 1
7418 MyFlags.Flags.setOrigAlign(1);
7419 Ins.push_back(MyFlags);
7421 if (NeedsRegBlock && Value == NumValues - 1)
7422 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7423 PartBase += VT.getStoreSize();
7427 // Call the target to set up the argument values.
7428 SmallVector<SDValue, 8> InVals;
7429 SDValue NewRoot = TLI->LowerFormalArguments(
7430 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7432 // Verify that the target's LowerFormalArguments behaved as expected.
7433 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7434 "LowerFormalArguments didn't return a valid chain!");
7435 assert(InVals.size() == Ins.size() &&
7436 "LowerFormalArguments didn't emit the correct number of values!");
7438 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7439 assert(InVals[i].getNode() &&
7440 "LowerFormalArguments emitted a null value!");
7441 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7442 "LowerFormalArguments emitted a value with the wrong type!");
7446 // Update the DAG with the new chain value resulting from argument lowering.
7447 DAG.setRoot(NewRoot);
7449 // Set up the argument values.
7452 if (!FuncInfo->CanLowerReturn) {
7453 // Create a virtual register for the sret pointer, and put in a copy
7454 // from the sret argument into it.
7455 SmallVector<EVT, 1> ValueVTs;
7456 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7457 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7458 MVT VT = ValueVTs[0].getSimpleVT();
7459 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7460 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7461 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7462 RegVT, VT, nullptr, AssertOp);
7464 MachineFunction& MF = SDB->DAG.getMachineFunction();
7465 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7466 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7467 FuncInfo->DemoteRegister = SRetReg;
7469 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7470 DAG.setRoot(NewRoot);
7472 // i indexes lowered arguments. Bump it past the hidden sret argument.
7473 // Idx indexes LLVM arguments. Don't touch it.
7477 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7479 SmallVector<SDValue, 4> ArgValues;
7480 SmallVector<EVT, 4> ValueVTs;
7481 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7482 unsigned NumValues = ValueVTs.size();
7484 // If this argument is unused then remember its value. It is used to generate
7485 // debugging information.
7486 if (I->use_empty() && NumValues) {
7487 SDB->setUnusedArgValue(&*I, InVals[i]);
7489 // Also remember any frame index for use in FastISel.
7490 if (FrameIndexSDNode *FI =
7491 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7492 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7495 for (unsigned Val = 0; Val != NumValues; ++Val) {
7496 EVT VT = ValueVTs[Val];
7497 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7498 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7500 if (!I->use_empty()) {
7501 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7502 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7503 AssertOp = ISD::AssertSext;
7504 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7505 AssertOp = ISD::AssertZext;
7507 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7508 NumParts, PartVT, VT,
7509 nullptr, AssertOp));
7515 // We don't need to do anything else for unused arguments.
7516 if (ArgValues.empty())
7519 // Note down frame index.
7520 if (FrameIndexSDNode *FI =
7521 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7522 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7524 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7525 SDB->getCurSDLoc());
7527 SDB->setValue(&*I, Res);
7528 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7529 if (LoadSDNode *LNode =
7530 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7531 if (FrameIndexSDNode *FI =
7532 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7533 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7536 // If this argument is live outside of the entry block, insert a copy from
7537 // wherever we got it to the vreg that other BB's will reference it as.
7538 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7539 // If we can, though, try to skip creating an unnecessary vreg.
7540 // FIXME: This isn't very clean... it would be nice to make this more
7541 // general. It's also subtly incompatible with the hacks FastISel
7543 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7544 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7545 FuncInfo->ValueMap[&*I] = Reg;
7549 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7550 FuncInfo->InitializeRegForValue(&*I);
7551 SDB->CopyToExportRegsIfNeeded(&*I);
7555 assert(i == InVals.size() && "Argument register count mismatch!");
7557 // Finally, if the target has anything special to do, allow it to do so.
7558 EmitFunctionEntryCode();
7561 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7562 /// ensure constants are generated when needed. Remember the virtual registers
7563 /// that need to be added to the Machine PHI nodes as input. We cannot just
7564 /// directly add them, because expansion might result in multiple MBB's for one
7565 /// BB. As such, the start of the BB might correspond to a different MBB than
7569 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7570 const TerminatorInst *TI = LLVMBB->getTerminator();
7572 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7574 // Check PHI nodes in successors that expect a value to be available from this
7576 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7577 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7578 if (!isa<PHINode>(SuccBB->begin())) continue;
7579 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7581 // If this terminator has multiple identical successors (common for
7582 // switches), only handle each succ once.
7583 if (!SuccsHandled.insert(SuccMBB).second)
7586 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7588 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7589 // nodes and Machine PHI nodes, but the incoming operands have not been
7591 for (BasicBlock::const_iterator I = SuccBB->begin();
7592 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7593 // Ignore dead phi's.
7594 if (PN->use_empty()) continue;
7597 if (PN->getType()->isEmptyTy())
7601 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7603 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7604 unsigned &RegOut = ConstantsOut[C];
7606 RegOut = FuncInfo.CreateRegs(C->getType());
7607 CopyValueToVirtualRegister(C, RegOut);
7611 DenseMap<const Value *, unsigned>::iterator I =
7612 FuncInfo.ValueMap.find(PHIOp);
7613 if (I != FuncInfo.ValueMap.end())
7616 assert(isa<AllocaInst>(PHIOp) &&
7617 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7618 "Didn't codegen value into a register!??");
7619 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7620 CopyValueToVirtualRegister(PHIOp, Reg);
7624 // Remember that this register needs to added to the machine PHI node as
7625 // the input for this MBB.
7626 SmallVector<EVT, 4> ValueVTs;
7627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7628 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7629 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7630 EVT VT = ValueVTs[vti];
7631 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7632 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7633 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7634 Reg += NumRegisters;
7639 ConstantsOut.clear();
7642 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7645 SelectionDAGBuilder::StackProtectorDescriptor::
7646 AddSuccessorMBB(const BasicBlock *BB,
7647 MachineBasicBlock *ParentMBB,
7649 MachineBasicBlock *SuccMBB) {
7650 // If SuccBB has not been created yet, create it.
7652 MachineFunction *MF = ParentMBB->getParent();
7653 MachineFunction::iterator BBI(ParentMBB);
7654 SuccMBB = MF->CreateMachineBasicBlock(BB);
7655 MF->insert(++BBI, SuccMBB);
7657 // Add it as a successor of ParentMBB.
7658 ParentMBB->addSuccessor(
7659 SuccMBB, BranchProbabilityInfo::getBranchProbStackProtector(IsLikely));
7663 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7664 MachineFunction::iterator I(MBB);
7665 if (++I == FuncInfo.MF->end())
7670 /// During lowering new call nodes can be created (such as memset, etc.).
7671 /// Those will become new roots of the current DAG, but complications arise
7672 /// when they are tail calls. In such cases, the call lowering will update
7673 /// the root, but the builder still needs to know that a tail call has been
7674 /// lowered in order to avoid generating an additional return.
7675 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7676 // If the node is null, we do have a tail call.
7677 if (MaybeTC.getNode() != nullptr)
7678 DAG.setRoot(MaybeTC);
7683 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7684 unsigned *TotalCases, unsigned First,
7686 assert(Last >= First);
7687 assert(TotalCases[Last] >= TotalCases[First]);
7689 APInt LowCase = Clusters[First].Low->getValue();
7690 APInt HighCase = Clusters[Last].High->getValue();
7691 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7693 // FIXME: A range of consecutive cases has 100% density, but only requires one
7694 // comparison to lower. We should discriminate against such consecutive ranges
7697 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7698 uint64_t Range = Diff + 1;
7701 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7703 assert(NumCases < UINT64_MAX / 100);
7704 assert(Range >= NumCases);
7706 return NumCases * 100 >= Range * MinJumpTableDensity;
7709 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7710 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7711 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7714 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7715 unsigned First, unsigned Last,
7716 const SwitchInst *SI,
7717 MachineBasicBlock *DefaultMBB,
7718 CaseCluster &JTCluster) {
7719 assert(First <= Last);
7721 auto Prob = BranchProbability::getZero();
7722 unsigned NumCmps = 0;
7723 std::vector<MachineBasicBlock*> Table;
7724 DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
7726 // Initialize probabilities in JTProbs.
7727 for (unsigned I = First; I <= Last; ++I)
7728 JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
7730 for (unsigned I = First; I <= Last; ++I) {
7731 assert(Clusters[I].Kind == CC_Range);
7732 Prob += Clusters[I].Prob;
7733 APInt Low = Clusters[I].Low->getValue();
7734 APInt High = Clusters[I].High->getValue();
7735 NumCmps += (Low == High) ? 1 : 2;
7737 // Fill the gap between this and the previous cluster.
7738 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7739 assert(PreviousHigh.slt(Low));
7740 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7741 for (uint64_t J = 0; J < Gap; J++)
7742 Table.push_back(DefaultMBB);
7744 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7745 for (uint64_t J = 0; J < ClusterSize; ++J)
7746 Table.push_back(Clusters[I].MBB);
7747 JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
7750 unsigned NumDests = JTProbs.size();
7751 if (isSuitableForBitTests(NumDests, NumCmps,
7752 Clusters[First].Low->getValue(),
7753 Clusters[Last].High->getValue())) {
7754 // Clusters[First..Last] should be lowered as bit tests instead.
7758 // Create the MBB that will load from and jump through the table.
7759 // Note: We create it here, but it's not inserted into the function yet.
7760 MachineFunction *CurMF = FuncInfo.MF;
7761 MachineBasicBlock *JumpTableMBB =
7762 CurMF->CreateMachineBasicBlock(SI->getParent());
7764 // Add successors. Note: use table order for determinism.
7765 SmallPtrSet<MachineBasicBlock *, 8> Done;
7766 for (MachineBasicBlock *Succ : Table) {
7767 if (Done.count(Succ))
7769 addSuccessorWithProb(JumpTableMBB, Succ, JTProbs[Succ]);
7772 JumpTableMBB->normalizeSuccProbs();
7774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7775 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7776 ->createJumpTableIndex(Table);
7778 // Set up the jump table info.
7779 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7780 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7781 Clusters[Last].High->getValue(), SI->getCondition(),
7783 JTCases.emplace_back(std::move(JTH), std::move(JT));
7785 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7786 JTCases.size() - 1, Prob);
7790 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7791 const SwitchInst *SI,
7792 MachineBasicBlock *DefaultMBB) {
7794 // Clusters must be non-empty, sorted, and only contain Range clusters.
7795 assert(!Clusters.empty());
7796 for (CaseCluster &C : Clusters)
7797 assert(C.Kind == CC_Range);
7798 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7799 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7802 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7803 if (!areJTsAllowed(TLI))
7806 const int64_t N = Clusters.size();
7807 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7809 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7810 SmallVector<unsigned, 8> TotalCases(N);
7812 for (unsigned i = 0; i < N; ++i) {
7813 APInt Hi = Clusters[i].High->getValue();
7814 APInt Lo = Clusters[i].Low->getValue();
7815 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7817 TotalCases[i] += TotalCases[i - 1];
7820 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7821 // Cheap case: the whole range might be suitable for jump table.
7822 CaseCluster JTCluster;
7823 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7824 Clusters[0] = JTCluster;
7830 // The algorithm below is not suitable for -O0.
7831 if (TM.getOptLevel() == CodeGenOpt::None)
7834 // Split Clusters into minimum number of dense partitions. The algorithm uses
7835 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7836 // for the Case Statement'" (1994), but builds the MinPartitions array in
7837 // reverse order to make it easier to reconstruct the partitions in ascending
7838 // order. In the choice between two optimal partitionings, it picks the one
7839 // which yields more jump tables.
7841 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7842 SmallVector<unsigned, 8> MinPartitions(N);
7843 // LastElement[i] is the last element of the partition starting at i.
7844 SmallVector<unsigned, 8> LastElement(N);
7845 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7846 SmallVector<unsigned, 8> NumTables(N);
7848 // Base case: There is only one way to partition Clusters[N-1].
7849 MinPartitions[N - 1] = 1;
7850 LastElement[N - 1] = N - 1;
7851 assert(MinJumpTableSize > 1);
7852 NumTables[N - 1] = 0;
7854 // Note: loop indexes are signed to avoid underflow.
7855 for (int64_t i = N - 2; i >= 0; i--) {
7856 // Find optimal partitioning of Clusters[i..N-1].
7857 // Baseline: Put Clusters[i] into a partition on its own.
7858 MinPartitions[i] = MinPartitions[i + 1] + 1;
7860 NumTables[i] = NumTables[i + 1];
7862 // Search for a solution that results in fewer partitions.
7863 for (int64_t j = N - 1; j > i; j--) {
7864 // Try building a partition from Clusters[i..j].
7865 if (isDense(Clusters, &TotalCases[0], i, j)) {
7866 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7867 bool IsTable = j - i + 1 >= MinJumpTableSize;
7868 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7870 // If this j leads to fewer partitions, or same number of partitions
7871 // with more lookup tables, it is a better partitioning.
7872 if (NumPartitions < MinPartitions[i] ||
7873 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7874 MinPartitions[i] = NumPartitions;
7876 NumTables[i] = Tables;
7882 // Iterate over the partitions, replacing some with jump tables in-place.
7883 unsigned DstIndex = 0;
7884 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7885 Last = LastElement[First];
7886 assert(Last >= First);
7887 assert(DstIndex <= First);
7888 unsigned NumClusters = Last - First + 1;
7890 CaseCluster JTCluster;
7891 if (NumClusters >= MinJumpTableSize &&
7892 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7893 Clusters[DstIndex++] = JTCluster;
7895 for (unsigned I = First; I <= Last; ++I)
7896 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7899 Clusters.resize(DstIndex);
7902 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7903 // FIXME: Using the pointer type doesn't seem ideal.
7904 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7905 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7909 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7912 const APInt &High) {
7913 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7914 // range of cases both require only one branch to lower. Just looking at the
7915 // number of clusters and destinations should be enough to decide whether to
7918 // To lower a range with bit tests, the range must fit the bitwidth of a
7920 if (!rangeFitsInWord(Low, High))
7923 // Decide whether it's profitable to lower this range with bit tests. Each
7924 // destination requires a bit test and branch, and there is an overall range
7925 // check branch. For a small number of clusters, separate comparisons might be
7926 // cheaper, and for many destinations, splitting the range might be better.
7927 return (NumDests == 1 && NumCmps >= 3) ||
7928 (NumDests == 2 && NumCmps >= 5) ||
7929 (NumDests == 3 && NumCmps >= 6);
7932 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7933 unsigned First, unsigned Last,
7934 const SwitchInst *SI,
7935 CaseCluster &BTCluster) {
7936 assert(First <= Last);
7940 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7941 unsigned NumCmps = 0;
7942 for (int64_t I = First; I <= Last; ++I) {
7943 assert(Clusters[I].Kind == CC_Range);
7944 Dests.set(Clusters[I].MBB->getNumber());
7945 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7947 unsigned NumDests = Dests.count();
7949 APInt Low = Clusters[First].Low->getValue();
7950 APInt High = Clusters[Last].High->getValue();
7951 assert(Low.slt(High));
7953 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7959 const int BitWidth = DAG.getTargetLoweringInfo()
7960 .getPointerTy(DAG.getDataLayout())
7962 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7964 // Check if the clusters cover a contiguous range such that no value in the
7965 // range will jump to the default statement.
7966 bool ContiguousRange = true;
7967 for (int64_t I = First + 1; I <= Last; ++I) {
7968 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7969 ContiguousRange = false;
7974 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7975 // Optimize the case where all the case values fit in a word without having
7976 // to subtract minValue. In this case, we can optimize away the subtraction.
7977 LowBound = APInt::getNullValue(Low.getBitWidth());
7979 ContiguousRange = false;
7982 CmpRange = High - Low;
7986 auto TotalProb = BranchProbability::getZero();
7987 for (unsigned i = First; i <= Last; ++i) {
7988 // Find the CaseBits for this destination.
7990 for (j = 0; j < CBV.size(); ++j)
7991 if (CBV[j].BB == Clusters[i].MBB)
7993 if (j == CBV.size())
7995 CaseBits(0, Clusters[i].MBB, 0, BranchProbability::getZero()));
7996 CaseBits *CB = &CBV[j];
7998 // Update Mask, Bits and ExtraProb.
7999 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
8000 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
8001 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
8002 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
8003 CB->Bits += Hi - Lo + 1;
8004 CB->ExtraProb += Clusters[i].Prob;
8005 TotalProb += Clusters[i].Prob;
8009 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
8010 // Sort by probability first, number of bits second.
8011 if (a.ExtraProb != b.ExtraProb)
8012 return a.ExtraProb > b.ExtraProb;
8013 return a.Bits > b.Bits;
8016 for (auto &CB : CBV) {
8017 MachineBasicBlock *BitTestBB =
8018 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
8019 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb));
8021 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8022 SI->getCondition(), -1U, MVT::Other, false,
8023 ContiguousRange, nullptr, nullptr, std::move(BTI),
8026 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8027 BitTestCases.size() - 1, TotalProb);
8031 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8032 const SwitchInst *SI) {
8033 // Partition Clusters into as few subsets as possible, where each subset has a
8034 // range that fits in a machine word and has <= 3 unique destinations.
8037 // Clusters must be sorted and contain Range or JumpTable clusters.
8038 assert(!Clusters.empty());
8039 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8040 for (const CaseCluster &C : Clusters)
8041 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8042 for (unsigned i = 1; i < Clusters.size(); ++i)
8043 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8046 // The algorithm below is not suitable for -O0.
8047 if (TM.getOptLevel() == CodeGenOpt::None)
8050 // If target does not have legal shift left, do not emit bit tests at all.
8051 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8052 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8053 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8056 int BitWidth = PTy.getSizeInBits();
8057 const int64_t N = Clusters.size();
8059 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8060 SmallVector<unsigned, 8> MinPartitions(N);
8061 // LastElement[i] is the last element of the partition starting at i.
8062 SmallVector<unsigned, 8> LastElement(N);
8064 // FIXME: This might not be the best algorithm for finding bit test clusters.
8066 // Base case: There is only one way to partition Clusters[N-1].
8067 MinPartitions[N - 1] = 1;
8068 LastElement[N - 1] = N - 1;
8070 // Note: loop indexes are signed to avoid underflow.
8071 for (int64_t i = N - 2; i >= 0; --i) {
8072 // Find optimal partitioning of Clusters[i..N-1].
8073 // Baseline: Put Clusters[i] into a partition on its own.
8074 MinPartitions[i] = MinPartitions[i + 1] + 1;
8077 // Search for a solution that results in fewer partitions.
8078 // Note: the search is limited by BitWidth, reducing time complexity.
8079 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8080 // Try building a partition from Clusters[i..j].
8083 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8084 Clusters[j].High->getValue()))
8087 // Check nbr of destinations and cluster types.
8088 // FIXME: This works, but doesn't seem very efficient.
8089 bool RangesOnly = true;
8090 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8091 for (int64_t k = i; k <= j; k++) {
8092 if (Clusters[k].Kind != CC_Range) {
8096 Dests.set(Clusters[k].MBB->getNumber());
8098 if (!RangesOnly || Dests.count() > 3)
8101 // Check if it's a better partition.
8102 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8103 if (NumPartitions < MinPartitions[i]) {
8104 // Found a better partition.
8105 MinPartitions[i] = NumPartitions;
8111 // Iterate over the partitions, replacing with bit-test clusters in-place.
8112 unsigned DstIndex = 0;
8113 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8114 Last = LastElement[First];
8115 assert(First <= Last);
8116 assert(DstIndex <= First);
8118 CaseCluster BitTestCluster;
8119 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8120 Clusters[DstIndex++] = BitTestCluster;
8122 size_t NumClusters = Last - First + 1;
8123 std::memmove(&Clusters[DstIndex], &Clusters[First],
8124 sizeof(Clusters[0]) * NumClusters);
8125 DstIndex += NumClusters;
8128 Clusters.resize(DstIndex);
8131 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8132 MachineBasicBlock *SwitchMBB,
8133 MachineBasicBlock *DefaultMBB) {
8134 MachineFunction *CurMF = FuncInfo.MF;
8135 MachineBasicBlock *NextMBB = nullptr;
8136 MachineFunction::iterator BBI(W.MBB);
8137 if (++BBI != FuncInfo.MF->end())
8140 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8142 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8144 if (Size == 2 && W.MBB == SwitchMBB) {
8145 // If any two of the cases has the same destination, and if one value
8146 // is the same as the other, but has one bit unset that the other has set,
8147 // use bit manipulation to do two compares at once. For example:
8148 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8149 // TODO: This could be extended to merge any 2 cases in switches with 3
8151 // TODO: Handle cases where W.CaseBB != SwitchBB.
8152 CaseCluster &Small = *W.FirstCluster;
8153 CaseCluster &Big = *W.LastCluster;
8155 if (Small.Low == Small.High && Big.Low == Big.High &&
8156 Small.MBB == Big.MBB) {
8157 const APInt &SmallValue = Small.Low->getValue();
8158 const APInt &BigValue = Big.Low->getValue();
8160 // Check that there is only one bit different.
8161 APInt CommonBit = BigValue ^ SmallValue;
8162 if (CommonBit.isPowerOf2()) {
8163 SDValue CondLHS = getValue(Cond);
8164 EVT VT = CondLHS.getValueType();
8165 SDLoc DL = getCurSDLoc();
8167 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8168 DAG.getConstant(CommonBit, DL, VT));
8169 SDValue Cond = DAG.getSetCC(
8170 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8173 // Update successor info.
8174 // Both Small and Big will jump to Small.BB, so we sum up the
8176 addSuccessorWithProb(SwitchMBB, Small.MBB, Small.Prob + Big.Prob);
8178 addSuccessorWithProb(
8179 SwitchMBB, DefaultMBB,
8180 // The default destination is the first successor in IR.
8181 BPI->getEdgeProbability(SwitchMBB->getBasicBlock(), (unsigned)0));
8183 addSuccessorWithProb(SwitchMBB, DefaultMBB);
8185 // Insert the true branch.
8187 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8188 DAG.getBasicBlock(Small.MBB));
8189 // Insert the false branch.
8190 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8191 DAG.getBasicBlock(DefaultMBB));
8193 DAG.setRoot(BrCond);
8199 if (TM.getOptLevel() != CodeGenOpt::None) {
8200 // Order cases by probability so the most likely case will be checked first.
8201 std::sort(W.FirstCluster, W.LastCluster + 1,
8202 [](const CaseCluster &a, const CaseCluster &b) {
8203 return a.Prob > b.Prob;
8206 // Rearrange the case blocks so that the last one falls through if possible
8207 // without without changing the order of probabilities.
8208 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8210 if (I->Prob > W.LastCluster->Prob)
8212 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8213 std::swap(*I, *W.LastCluster);
8219 // Compute total probability.
8220 BranchProbability DefaultProb = W.DefaultProb;
8221 BranchProbability UnhandledProbs = DefaultProb;
8222 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
8223 UnhandledProbs += I->Prob;
8225 MachineBasicBlock *CurMBB = W.MBB;
8226 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8227 MachineBasicBlock *Fallthrough;
8228 if (I == W.LastCluster) {
8229 // For the last cluster, fall through to the default destination.
8230 Fallthrough = DefaultMBB;
8232 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8233 CurMF->insert(BBI, Fallthrough);
8234 // Put Cond in a virtual register to make it available from the new blocks.
8235 ExportFromCurrentBlock(Cond);
8237 UnhandledProbs -= I->Prob;
8240 case CC_JumpTable: {
8241 // FIXME: Optimize away range check based on pivot comparisons.
8242 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8243 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8245 // The jump block hasn't been inserted yet; insert it here.
8246 MachineBasicBlock *JumpMBB = JT->MBB;
8247 CurMF->insert(BBI, JumpMBB);
8249 auto JumpProb = I->Prob;
8250 auto FallthroughProb = UnhandledProbs;
8252 // If the default statement is a target of the jump table, we evenly
8253 // distribute the default probability to successors of CurMBB. Also
8254 // update the probability on the edge from JumpMBB to Fallthrough.
8255 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8256 SE = JumpMBB->succ_end();
8258 if (*SI == DefaultMBB) {
8259 JumpProb += DefaultProb / 2;
8260 FallthroughProb -= DefaultProb / 2;
8261 JumpMBB->setSuccProbability(SI, DefaultProb / 2);
8266 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
8267 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
8269 // The jump table header will be inserted in our current block, do the
8270 // range check, and fall through to our fallthrough block.
8271 JTH->HeaderBB = CurMBB;
8272 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8274 // If we're in the right place, emit the jump table header right now.
8275 if (CurMBB == SwitchMBB) {
8276 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8277 JTH->Emitted = true;
8282 // FIXME: Optimize away range check based on pivot comparisons.
8283 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8285 // The bit test blocks haven't been inserted yet; insert them here.
8286 for (BitTestCase &BTC : BTB->Cases)
8287 CurMF->insert(BBI, BTC.ThisBB);
8289 // Fill in fields of the BitTestBlock.
8290 BTB->Parent = CurMBB;
8291 BTB->Default = Fallthrough;
8293 BTB->DefaultProb = UnhandledProbs;
8294 // If the cases in bit test don't form a contiguous range, we evenly
8295 // distribute the probability on the edge to Fallthrough to two
8296 // successors of CurMBB.
8297 if (!BTB->ContiguousRange) {
8298 BTB->Prob += DefaultProb / 2;
8299 BTB->DefaultProb -= DefaultProb / 2;
8302 // If we're in the right place, emit the bit test header right now.
8303 if (CurMBB == SwitchMBB) {
8304 visitBitTestHeader(*BTB, SwitchMBB);
8305 BTB->Emitted = true;
8310 const Value *RHS, *LHS, *MHS;
8312 if (I->Low == I->High) {
8313 // Check Cond == I->Low.
8319 // Check I->Low <= Cond <= I->High.
8326 // The false probability is the sum of all unhandled cases.
8327 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Prob,
8330 if (CurMBB == SwitchMBB)
8331 visitSwitchCase(CB, SwitchMBB);
8333 SwitchCases.push_back(CB);
8338 CurMBB = Fallthrough;
8342 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8343 CaseClusterIt First,
8344 CaseClusterIt Last) {
8345 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8346 if (X.Prob != CC.Prob)
8347 return X.Prob > CC.Prob;
8349 // Ties are broken by comparing the case value.
8350 return X.Low->getValue().slt(CC.Low->getValue());
8354 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8355 const SwitchWorkListItem &W,
8357 MachineBasicBlock *SwitchMBB) {
8358 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8359 "Clusters not sorted?");
8361 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8363 // Balance the tree based on branch probabilities to create a near-optimal (in
8364 // terms of search time given key frequency) binary search tree. See e.g. Kurt
8365 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8366 CaseClusterIt LastLeft = W.FirstCluster;
8367 CaseClusterIt FirstRight = W.LastCluster;
8368 auto LeftProb = LastLeft->Prob + W.DefaultProb / 2;
8369 auto RightProb = FirstRight->Prob + W.DefaultProb / 2;
8371 // Move LastLeft and FirstRight towards each other from opposite directions to
8372 // find a partitioning of the clusters which balances the probability on both
8373 // sides. If LeftProb and RightProb are equal, alternate which side is
8374 // taken to ensure 0-probability nodes are distributed evenly.
8376 while (LastLeft + 1 < FirstRight) {
8377 if (LeftProb < RightProb || (LeftProb == RightProb && (I & 1)))
8378 LeftProb += (++LastLeft)->Prob;
8380 RightProb += (--FirstRight)->Prob;
8385 // Our binary search tree differs from a typical BST in that ours can have up
8386 // to three values in each leaf. The pivot selection above doesn't take that
8387 // into account, which means the tree might require more nodes and be less
8388 // efficient. We compensate for this here.
8390 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8391 unsigned NumRight = W.LastCluster - FirstRight + 1;
8393 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8394 // If one side has less than 3 clusters, and the other has more than 3,
8395 // consider taking a cluster from the other side.
8397 if (NumLeft < NumRight) {
8398 // Consider moving the first cluster on the right to the left side.
8399 CaseCluster &CC = *FirstRight;
8400 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8401 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8402 if (LeftSideRank <= RightSideRank) {
8403 // Moving the cluster to the left does not demote it.
8409 assert(NumRight < NumLeft);
8410 // Consider moving the last element on the left to the right side.
8411 CaseCluster &CC = *LastLeft;
8412 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8413 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8414 if (RightSideRank <= LeftSideRank) {
8415 // Moving the cluster to the right does not demot it.
8425 assert(LastLeft + 1 == FirstRight);
8426 assert(LastLeft >= W.FirstCluster);
8427 assert(FirstRight <= W.LastCluster);
8429 // Use the first element on the right as pivot since we will make less-than
8430 // comparisons against it.
8431 CaseClusterIt PivotCluster = FirstRight;
8432 assert(PivotCluster > W.FirstCluster);
8433 assert(PivotCluster <= W.LastCluster);
8435 CaseClusterIt FirstLeft = W.FirstCluster;
8436 CaseClusterIt LastRight = W.LastCluster;
8438 const ConstantInt *Pivot = PivotCluster->Low;
8440 // New blocks will be inserted immediately after the current one.
8441 MachineFunction::iterator BBI(W.MBB);
8444 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8445 // we can branch to its destination directly if it's squeezed exactly in
8446 // between the known lower bound and Pivot - 1.
8447 MachineBasicBlock *LeftMBB;
8448 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8449 FirstLeft->Low == W.GE &&
8450 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8451 LeftMBB = FirstLeft->MBB;
8453 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8454 FuncInfo.MF->insert(BBI, LeftMBB);
8456 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultProb / 2});
8457 // Put Cond in a virtual register to make it available from the new blocks.
8458 ExportFromCurrentBlock(Cond);
8461 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8462 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8463 // directly if RHS.High equals the current upper bound.
8464 MachineBasicBlock *RightMBB;
8465 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8466 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8467 RightMBB = FirstRight->MBB;
8469 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8470 FuncInfo.MF->insert(BBI, RightMBB);
8472 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultProb / 2});
8473 // Put Cond in a virtual register to make it available from the new blocks.
8474 ExportFromCurrentBlock(Cond);
8477 // Create the CaseBlock record that will be used to lower the branch.
8478 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8479 LeftProb, RightProb);
8481 if (W.MBB == SwitchMBB)
8482 visitSwitchCase(CB, SwitchMBB);
8484 SwitchCases.push_back(CB);
8487 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8488 // Extract cases from the switch.
8489 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8490 CaseClusterVector Clusters;
8491 Clusters.reserve(SI.getNumCases());
8492 for (auto I : SI.cases()) {
8493 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8494 const ConstantInt *CaseVal = I.getCaseValue();
8495 BranchProbability Prob =
8496 BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
8497 : BranchProbability(1, SI.getNumCases() + 1);
8498 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
8501 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8503 // Cluster adjacent cases with the same destination. We do this at all
8504 // optimization levels because it's cheap to do and will make codegen faster
8505 // if there are many clusters.
8506 sortAndRangeify(Clusters);
8508 if (TM.getOptLevel() != CodeGenOpt::None) {
8509 // Replace an unreachable default with the most popular destination.
8510 // FIXME: Exploit unreachable default more aggressively.
8511 bool UnreachableDefault =
8512 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8513 if (UnreachableDefault && !Clusters.empty()) {
8514 DenseMap<const BasicBlock *, unsigned> Popularity;
8515 unsigned MaxPop = 0;
8516 const BasicBlock *MaxBB = nullptr;
8517 for (auto I : SI.cases()) {
8518 const BasicBlock *BB = I.getCaseSuccessor();
8519 if (++Popularity[BB] > MaxPop) {
8520 MaxPop = Popularity[BB];
8525 assert(MaxPop > 0 && MaxBB);
8526 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8528 // Remove cases that were pointing to the destination that is now the
8530 CaseClusterVector New;
8531 New.reserve(Clusters.size());
8532 for (CaseCluster &CC : Clusters) {
8533 if (CC.MBB != DefaultMBB)
8536 Clusters = std::move(New);
8540 // If there is only the default destination, jump there directly.
8541 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8542 if (Clusters.empty()) {
8543 SwitchMBB->addSuccessor(DefaultMBB);
8544 if (DefaultMBB != NextBlock(SwitchMBB)) {
8545 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8546 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8551 findJumpTables(Clusters, &SI, DefaultMBB);
8552 findBitTestClusters(Clusters, &SI);
8555 dbgs() << "Case clusters: ";
8556 for (const CaseCluster &C : Clusters) {
8557 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8558 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8560 C.Low->getValue().print(dbgs(), true);
8561 if (C.Low != C.High) {
8563 C.High->getValue().print(dbgs(), true);
8570 assert(!Clusters.empty());
8571 SwitchWorkList WorkList;
8572 CaseClusterIt First = Clusters.begin();
8573 CaseClusterIt Last = Clusters.end() - 1;
8574 auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);
8575 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
8577 while (!WorkList.empty()) {
8578 SwitchWorkListItem W = WorkList.back();
8579 WorkList.pop_back();
8580 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8582 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8583 // For optimized builds, lower large range as a balanced binary tree.
8584 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8588 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);