1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 // Update machine-CFG edges.
1164 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1165 MachineBasicBlock *CatchingMBB = FuncInfo.MBBMap[I.getNormalDest()];
1166 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1167 PadMBB->addSuccessor(CatchingMBB);
1168 PadMBB->addSuccessor(UnwindMBB);
1170 CatchingMBB->setIsEHFuncletEntry();
1171 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1172 MMI.setHasEHFunclets(true);
1175 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1176 // Update machine-CFG edge.
1177 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1178 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1179 PadMBB->addSuccessor(TargetMBB);
1181 // Create the terminator node.
1182 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1183 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1187 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1188 // If this unwinds to caller, we don't need a DAG node hanging around.
1189 if (!I.hasUnwindDest())
1192 // Update machine-CFG edge.
1193 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1194 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1195 PadMBB->addSuccessor(UnwindMBB);
1198 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1199 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1200 MMI.setHasEHFunclets(true);
1201 report_fatal_error("visitCleanupPad not yet implemented!");
1204 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1205 report_fatal_error("visitCleanupRet not yet implemented!");
1208 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1209 report_fatal_error("visitTerminatePad not yet implemented!");
1212 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1214 auto &DL = DAG.getDataLayout();
1215 SDValue Chain = getControlRoot();
1216 SmallVector<ISD::OutputArg, 8> Outs;
1217 SmallVector<SDValue, 8> OutVals;
1219 if (!FuncInfo.CanLowerReturn) {
1220 unsigned DemoteReg = FuncInfo.DemoteRegister;
1221 const Function *F = I.getParent()->getParent();
1223 // Emit a store of the return value through the virtual register.
1224 // Leave Outs empty so that LowerReturn won't try to load return
1225 // registers the usual way.
1226 SmallVector<EVT, 1> PtrValueVTs;
1227 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1230 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1231 SDValue RetOp = getValue(I.getOperand(0));
1233 SmallVector<EVT, 4> ValueVTs;
1234 SmallVector<uint64_t, 4> Offsets;
1235 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1236 unsigned NumValues = ValueVTs.size();
1238 SmallVector<SDValue, 4> Chains(NumValues);
1239 for (unsigned i = 0; i != NumValues; ++i) {
1240 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1241 RetPtr.getValueType(), RetPtr,
1242 DAG.getIntPtrConstant(Offsets[i],
1245 DAG.getStore(Chain, getCurSDLoc(),
1246 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1247 // FIXME: better loc info would be nice.
1248 Add, MachinePointerInfo(), false, false, 0);
1251 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1252 MVT::Other, Chains);
1253 } else if (I.getNumOperands() != 0) {
1254 SmallVector<EVT, 4> ValueVTs;
1255 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1256 unsigned NumValues = ValueVTs.size();
1258 SDValue RetOp = getValue(I.getOperand(0));
1260 const Function *F = I.getParent()->getParent();
1262 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1263 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1265 ExtendKind = ISD::SIGN_EXTEND;
1266 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1268 ExtendKind = ISD::ZERO_EXTEND;
1270 LLVMContext &Context = F->getContext();
1271 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1274 for (unsigned j = 0; j != NumValues; ++j) {
1275 EVT VT = ValueVTs[j];
1277 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1278 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1280 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1281 MVT PartVT = TLI.getRegisterType(Context, VT);
1282 SmallVector<SDValue, 4> Parts(NumParts);
1283 getCopyToParts(DAG, getCurSDLoc(),
1284 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1285 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1287 // 'inreg' on function refers to return value
1288 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1292 // Propagate extension type if any
1293 if (ExtendKind == ISD::SIGN_EXTEND)
1295 else if (ExtendKind == ISD::ZERO_EXTEND)
1298 for (unsigned i = 0; i < NumParts; ++i) {
1299 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1300 VT, /*isfixed=*/true, 0, 0));
1301 OutVals.push_back(Parts[i]);
1307 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1308 CallingConv::ID CallConv =
1309 DAG.getMachineFunction().getFunction()->getCallingConv();
1310 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1311 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1313 // Verify that the target's LowerReturn behaved as expected.
1314 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1315 "LowerReturn didn't return a valid chain!");
1317 // Update the DAG with the new chain value resulting from return lowering.
1321 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1322 /// created for it, emit nodes to copy the value into the virtual
1324 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1326 if (V->getType()->isEmptyTy())
1329 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1330 if (VMI != FuncInfo.ValueMap.end()) {
1331 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1332 CopyValueToVirtualRegister(V, VMI->second);
1336 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1337 /// the current basic block, add it to ValueMap now so that we'll get a
1339 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1340 // No need to export constants.
1341 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1343 // Already exported?
1344 if (FuncInfo.isExportedInst(V)) return;
1346 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1347 CopyValueToVirtualRegister(V, Reg);
1350 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1351 const BasicBlock *FromBB) {
1352 // The operands of the setcc have to be in this block. We don't know
1353 // how to export them from some other block.
1354 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1355 // Can export from current BB.
1356 if (VI->getParent() == FromBB)
1359 // Is already exported, noop.
1360 return FuncInfo.isExportedInst(V);
1363 // If this is an argument, we can export it if the BB is the entry block or
1364 // if it is already exported.
1365 if (isa<Argument>(V)) {
1366 if (FromBB == &FromBB->getParent()->getEntryBlock())
1369 // Otherwise, can only export this if it is already exported.
1370 return FuncInfo.isExportedInst(V);
1373 // Otherwise, constants can always be exported.
1377 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1378 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1379 const MachineBasicBlock *Dst) const {
1380 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1383 const BasicBlock *SrcBB = Src->getBasicBlock();
1384 const BasicBlock *DstBB = Dst->getBasicBlock();
1385 return BPI->getEdgeWeight(SrcBB, DstBB);
1388 void SelectionDAGBuilder::
1389 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1390 uint32_t Weight /* = 0 */) {
1392 Weight = getEdgeWeight(Src, Dst);
1393 Src->addSuccessor(Dst, Weight);
1397 static bool InBlock(const Value *V, const BasicBlock *BB) {
1398 if (const Instruction *I = dyn_cast<Instruction>(V))
1399 return I->getParent() == BB;
1403 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1404 /// This function emits a branch and is used at the leaves of an OR or an
1405 /// AND operator tree.
1408 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1409 MachineBasicBlock *TBB,
1410 MachineBasicBlock *FBB,
1411 MachineBasicBlock *CurBB,
1412 MachineBasicBlock *SwitchBB,
1415 const BasicBlock *BB = CurBB->getBasicBlock();
1417 // If the leaf of the tree is a comparison, merge the condition into
1419 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1420 // The operands of the cmp have to be in this block. We don't know
1421 // how to export them from some other block. If this is the first block
1422 // of the sequence, no exporting is needed.
1423 if (CurBB == SwitchBB ||
1424 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1425 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1426 ISD::CondCode Condition;
1427 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1428 Condition = getICmpCondCode(IC->getPredicate());
1430 const FCmpInst *FC = cast<FCmpInst>(Cond);
1431 Condition = getFCmpCondCode(FC->getPredicate());
1432 if (TM.Options.NoNaNsFPMath)
1433 Condition = getFCmpCodeWithoutNaN(Condition);
1436 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1437 TBB, FBB, CurBB, TWeight, FWeight);
1438 SwitchCases.push_back(CB);
1443 // Create a CaseBlock record representing this branch.
1444 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1445 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1446 SwitchCases.push_back(CB);
1449 /// Scale down both weights to fit into uint32_t.
1450 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1451 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1452 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1453 NewTrue = NewTrue / Scale;
1454 NewFalse = NewFalse / Scale;
1457 /// FindMergedConditions - If Cond is an expression like
1458 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1459 MachineBasicBlock *TBB,
1460 MachineBasicBlock *FBB,
1461 MachineBasicBlock *CurBB,
1462 MachineBasicBlock *SwitchBB,
1463 Instruction::BinaryOps Opc,
1466 // If this node is not part of the or/and tree, emit it as a branch.
1467 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1468 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1469 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1470 BOp->getParent() != CurBB->getBasicBlock() ||
1471 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1472 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1473 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1478 // Create TmpBB after CurBB.
1479 MachineFunction::iterator BBI = CurBB;
1480 MachineFunction &MF = DAG.getMachineFunction();
1481 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1482 CurBB->getParent()->insert(++BBI, TmpBB);
1484 if (Opc == Instruction::Or) {
1485 // Codegen X | Y as:
1494 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1495 // The requirement is that
1496 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1497 // = TrueProb for original BB.
1498 // Assuming the original weights are A and B, one choice is to set BB1's
1499 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1501 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1502 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1503 // TmpBB, but the math is more complicated.
1505 uint64_t NewTrueWeight = TWeight;
1506 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1507 ScaleWeights(NewTrueWeight, NewFalseWeight);
1508 // Emit the LHS condition.
1509 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1510 NewTrueWeight, NewFalseWeight);
1512 NewTrueWeight = TWeight;
1513 NewFalseWeight = 2 * (uint64_t)FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the RHS condition into TmpBB.
1516 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 assert(Opc == Instruction::And && "Unknown merge op!");
1520 // Codegen X & Y as:
1528 // This requires creation of TmpBB after CurBB.
1530 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1531 // The requirement is that
1532 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1533 // = FalseProb for original BB.
1534 // Assuming the original weights are A and B, one choice is to set BB1's
1535 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1537 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1539 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1540 uint64_t NewFalseWeight = FWeight;
1541 ScaleWeights(NewTrueWeight, NewFalseWeight);
1542 // Emit the LHS condition.
1543 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1544 NewTrueWeight, NewFalseWeight);
1546 NewTrueWeight = 2 * (uint64_t)TWeight;
1547 NewFalseWeight = FWeight;
1548 ScaleWeights(NewTrueWeight, NewFalseWeight);
1549 // Emit the RHS condition into TmpBB.
1550 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1551 NewTrueWeight, NewFalseWeight);
1555 /// If the set of cases should be emitted as a series of branches, return true.
1556 /// If we should emit this as a bunch of and/or'd together conditions, return
1559 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1560 if (Cases.size() != 2) return true;
1562 // If this is two comparisons of the same values or'd or and'd together, they
1563 // will get folded into a single comparison, so don't emit two blocks.
1564 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1565 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1566 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1567 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1571 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1572 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1573 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1574 Cases[0].CC == Cases[1].CC &&
1575 isa<Constant>(Cases[0].CmpRHS) &&
1576 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1577 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1579 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1586 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1587 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1589 // Update machine-CFG edges.
1590 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1592 if (I.isUnconditional()) {
1593 // Update machine-CFG edges.
1594 BrMBB->addSuccessor(Succ0MBB);
1596 // If this is not a fall-through branch or optimizations are switched off,
1598 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1599 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1600 MVT::Other, getControlRoot(),
1601 DAG.getBasicBlock(Succ0MBB)));
1606 // If this condition is one of the special cases we handle, do special stuff
1608 const Value *CondVal = I.getCondition();
1609 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1611 // If this is a series of conditions that are or'd or and'd together, emit
1612 // this as a sequence of branches instead of setcc's with and/or operations.
1613 // As long as jumps are not expensive, this should improve performance.
1614 // For example, instead of something like:
1627 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1628 Instruction::BinaryOps Opcode = BOp->getOpcode();
1629 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1630 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1631 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1632 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1633 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1634 getEdgeWeight(BrMBB, Succ1MBB));
1635 // If the compares in later blocks need to use values not currently
1636 // exported from this block, export them now. This block should always
1637 // be the first entry.
1638 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1640 // Allow some cases to be rejected.
1641 if (ShouldEmitAsBranches(SwitchCases)) {
1642 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1643 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1644 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1647 // Emit the branch for this block.
1648 visitSwitchCase(SwitchCases[0], BrMBB);
1649 SwitchCases.erase(SwitchCases.begin());
1653 // Okay, we decided not to do this, remove any inserted MBB's and clear
1655 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1656 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1658 SwitchCases.clear();
1662 // Create a CaseBlock record representing this branch.
1663 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1664 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1666 // Use visitSwitchCase to actually insert the fast branch sequence for this
1668 visitSwitchCase(CB, BrMBB);
1671 /// visitSwitchCase - Emits the necessary code to represent a single node in
1672 /// the binary search tree resulting from lowering a switch instruction.
1673 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1674 MachineBasicBlock *SwitchBB) {
1676 SDValue CondLHS = getValue(CB.CmpLHS);
1677 SDLoc dl = getCurSDLoc();
1679 // Build the setcc now.
1681 // Fold "(X == true)" to X and "(X == false)" to !X to
1682 // handle common cases produced by branch lowering.
1683 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1684 CB.CC == ISD::SETEQ)
1686 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1687 CB.CC == ISD::SETEQ) {
1688 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1689 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1691 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1693 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1695 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1696 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1698 SDValue CmpOp = getValue(CB.CmpMHS);
1699 EVT VT = CmpOp.getValueType();
1701 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1702 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1705 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1706 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1707 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1708 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1712 // Update successor info
1713 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1714 // TrueBB and FalseBB are always different unless the incoming IR is
1715 // degenerate. This only happens when running llc on weird IR.
1716 if (CB.TrueBB != CB.FalseBB)
1717 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1719 // If the lhs block is the next block, invert the condition so that we can
1720 // fall through to the lhs instead of the rhs block.
1721 if (CB.TrueBB == NextBlock(SwitchBB)) {
1722 std::swap(CB.TrueBB, CB.FalseBB);
1723 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1724 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1727 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1728 MVT::Other, getControlRoot(), Cond,
1729 DAG.getBasicBlock(CB.TrueBB));
1731 // Insert the false branch. Do this even if it's a fall through branch,
1732 // this makes it easier to do DAG optimizations which require inverting
1733 // the branch condition.
1734 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1735 DAG.getBasicBlock(CB.FalseBB));
1737 DAG.setRoot(BrCond);
1740 /// visitJumpTable - Emit JumpTable node in the current MBB
1741 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1742 // Emit the code for the jump table
1743 assert(JT.Reg != -1U && "Should lower JT Header first!");
1744 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1745 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1747 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1748 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1749 MVT::Other, Index.getValue(1),
1751 DAG.setRoot(BrJumpTable);
1754 /// visitJumpTableHeader - This function emits necessary code to produce index
1755 /// in the JumpTable from switch case.
1756 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1757 JumpTableHeader &JTH,
1758 MachineBasicBlock *SwitchBB) {
1759 SDLoc dl = getCurSDLoc();
1761 // Subtract the lowest switch case value from the value being switched on and
1762 // conditional branch to default mbb if the result is greater than the
1763 // difference between smallest and largest cases.
1764 SDValue SwitchOp = getValue(JTH.SValue);
1765 EVT VT = SwitchOp.getValueType();
1766 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1767 DAG.getConstant(JTH.First, dl, VT));
1769 // The SDNode we just created, which holds the value being switched on minus
1770 // the smallest case value, needs to be copied to a virtual register so it
1771 // can be used as an index into the jump table in a subsequent basic block.
1772 // This value may be smaller or larger than the target's pointer type, and
1773 // therefore require extension or truncating.
1774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1775 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1777 unsigned JumpTableReg =
1778 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1779 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1780 JumpTableReg, SwitchOp);
1781 JT.Reg = JumpTableReg;
1783 // Emit the range check for the jump table, and branch to the default block
1784 // for the switch statement if the value being switched on exceeds the largest
1785 // case in the switch.
1786 SDValue CMP = DAG.getSetCC(
1787 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1788 Sub.getValueType()),
1789 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1791 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1792 MVT::Other, CopyTo, CMP,
1793 DAG.getBasicBlock(JT.Default));
1795 // Avoid emitting unnecessary branches to the next block.
1796 if (JT.MBB != NextBlock(SwitchBB))
1797 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1798 DAG.getBasicBlock(JT.MBB));
1800 DAG.setRoot(BrCond);
1803 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1804 /// tail spliced into a stack protector check success bb.
1806 /// For a high level explanation of how this fits into the stack protector
1807 /// generation see the comment on the declaration of class
1808 /// StackProtectorDescriptor.
1809 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1810 MachineBasicBlock *ParentBB) {
1812 // First create the loads to the guard/stack slot for the comparison.
1813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1814 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1816 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1817 int FI = MFI->getStackProtectorIndex();
1819 const Value *IRGuard = SPD.getGuard();
1820 SDValue GuardPtr = getValue(IRGuard);
1821 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1823 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1826 SDLoc dl = getCurSDLoc();
1828 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1829 // guard value from the virtual register holding the value. Otherwise, emit a
1830 // volatile load to retrieve the stack guard value.
1831 unsigned GuardReg = SPD.getGuardReg();
1833 if (GuardReg && TLI.useLoadStackGuardNode())
1834 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1837 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1838 GuardPtr, MachinePointerInfo(IRGuard, 0),
1839 true, false, false, Align);
1841 SDValue StackSlot = DAG.getLoad(
1842 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1843 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1844 false, false, Align);
1846 // Perform the comparison via a subtract/getsetcc.
1847 EVT VT = Guard.getValueType();
1848 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1850 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1852 Sub.getValueType()),
1853 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1855 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1856 // branch to failure MBB.
1857 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1858 MVT::Other, StackSlot.getOperand(0),
1859 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1860 // Otherwise branch to success MBB.
1861 SDValue Br = DAG.getNode(ISD::BR, dl,
1863 DAG.getBasicBlock(SPD.getSuccessMBB()));
1868 /// Codegen the failure basic block for a stack protector check.
1870 /// A failure stack protector machine basic block consists simply of a call to
1871 /// __stack_chk_fail().
1873 /// For a high level explanation of how this fits into the stack protector
1874 /// generation see the comment on the declaration of class
1875 /// StackProtectorDescriptor.
1877 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1880 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1881 nullptr, 0, false, getCurSDLoc(), false, false).second;
1885 /// visitBitTestHeader - This function emits necessary code to produce value
1886 /// suitable for "bit tests"
1887 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1888 MachineBasicBlock *SwitchBB) {
1889 SDLoc dl = getCurSDLoc();
1891 // Subtract the minimum value
1892 SDValue SwitchOp = getValue(B.SValue);
1893 EVT VT = SwitchOp.getValueType();
1894 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1895 DAG.getConstant(B.First, dl, VT));
1898 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1899 SDValue RangeCmp = DAG.getSetCC(
1900 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1901 Sub.getValueType()),
1902 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1904 // Determine the type of the test operands.
1905 bool UsePtrType = false;
1906 if (!TLI.isTypeLegal(VT))
1909 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1910 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1911 // Switch table case range are encoded into series of masks.
1912 // Just use pointer type, it's guaranteed to fit.
1918 VT = TLI.getPointerTy(DAG.getDataLayout());
1919 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1922 B.RegVT = VT.getSimpleVT();
1923 B.Reg = FuncInfo.CreateReg(B.RegVT);
1924 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1926 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1928 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1929 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1931 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1932 MVT::Other, CopyTo, RangeCmp,
1933 DAG.getBasicBlock(B.Default));
1935 // Avoid emitting unnecessary branches to the next block.
1936 if (MBB != NextBlock(SwitchBB))
1937 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1938 DAG.getBasicBlock(MBB));
1940 DAG.setRoot(BrRange);
1943 /// visitBitTestCase - this function produces one "bit test"
1944 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1945 MachineBasicBlock* NextMBB,
1946 uint32_t BranchWeightToNext,
1949 MachineBasicBlock *SwitchBB) {
1950 SDLoc dl = getCurSDLoc();
1952 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1954 unsigned PopCount = countPopulation(B.Mask);
1955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1956 if (PopCount == 1) {
1957 // Testing for a single bit; just compare the shift count with what it
1958 // would need to be to shift a 1 bit in that position.
1960 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1961 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1963 } else if (PopCount == BB.Range) {
1964 // There is only one zero bit in the range, test for it directly.
1966 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1967 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1970 // Make desired shift
1971 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1972 DAG.getConstant(1, dl, VT), ShiftOp);
1974 // Emit bit tests and jumps
1975 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1976 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1978 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1979 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1982 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1983 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1984 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1985 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1987 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1988 MVT::Other, getControlRoot(),
1989 Cmp, DAG.getBasicBlock(B.TargetBB));
1991 // Avoid emitting unnecessary branches to the next block.
1992 if (NextMBB != NextBlock(SwitchBB))
1993 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1994 DAG.getBasicBlock(NextMBB));
1999 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2000 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2002 // Retrieve successors.
2003 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2004 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2006 const Value *Callee(I.getCalledValue());
2007 const Function *Fn = dyn_cast<Function>(Callee);
2008 if (isa<InlineAsm>(Callee))
2010 else if (Fn && Fn->isIntrinsic()) {
2011 switch (Fn->getIntrinsicID()) {
2013 llvm_unreachable("Cannot invoke this intrinsic");
2014 case Intrinsic::donothing:
2015 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2017 case Intrinsic::experimental_patchpoint_void:
2018 case Intrinsic::experimental_patchpoint_i64:
2019 visitPatchpoint(&I, LandingPad);
2021 case Intrinsic::experimental_gc_statepoint:
2022 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2026 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2028 // If the value of the invoke is used outside of its defining block, make it
2029 // available as a virtual register.
2030 // We already took care of the exported value for the statepoint instruction
2031 // during call to the LowerStatepoint.
2032 if (!isStatepoint(I)) {
2033 CopyToExportRegsIfNeeded(&I);
2036 // Update successor info
2037 addSuccessorWithWeight(InvokeMBB, Return);
2038 addSuccessorWithWeight(InvokeMBB, LandingPad);
2040 // Drop into normal successor.
2041 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2042 MVT::Other, getControlRoot(),
2043 DAG.getBasicBlock(Return)));
2046 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2047 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2050 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2051 assert(FuncInfo.MBB->isEHPad() &&
2052 "Call to landingpad not in landing pad!");
2054 MachineBasicBlock *MBB = FuncInfo.MBB;
2055 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2056 AddLandingPadInfo(LP, MMI, MBB);
2058 // If there aren't registers to copy the values into (e.g., during SjLj
2059 // exceptions), then don't bother to create these DAG nodes.
2060 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2061 if (TLI.getExceptionPointerRegister() == 0 &&
2062 TLI.getExceptionSelectorRegister() == 0)
2065 SmallVector<EVT, 2> ValueVTs;
2066 SDLoc dl = getCurSDLoc();
2067 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2068 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2070 // Get the two live-in registers as SDValues. The physregs have already been
2071 // copied into virtual registers.
2073 if (FuncInfo.ExceptionPointerVirtReg) {
2074 Ops[0] = DAG.getZExtOrTrunc(
2075 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2076 FuncInfo.ExceptionPointerVirtReg,
2077 TLI.getPointerTy(DAG.getDataLayout())),
2080 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2082 Ops[1] = DAG.getZExtOrTrunc(
2083 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2084 FuncInfo.ExceptionSelectorVirtReg,
2085 TLI.getPointerTy(DAG.getDataLayout())),
2089 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2090 DAG.getVTList(ValueVTs), Ops);
2094 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2096 for (const CaseCluster &CC : Clusters)
2097 assert(CC.Low == CC.High && "Input clusters must be single-case");
2100 std::sort(Clusters.begin(), Clusters.end(),
2101 [](const CaseCluster &a, const CaseCluster &b) {
2102 return a.Low->getValue().slt(b.Low->getValue());
2105 // Merge adjacent clusters with the same destination.
2106 const unsigned N = Clusters.size();
2107 unsigned DstIndex = 0;
2108 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2109 CaseCluster &CC = Clusters[SrcIndex];
2110 const ConstantInt *CaseVal = CC.Low;
2111 MachineBasicBlock *Succ = CC.MBB;
2113 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2114 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2115 // If this case has the same successor and is a neighbour, merge it into
2116 // the previous cluster.
2117 Clusters[DstIndex - 1].High = CaseVal;
2118 Clusters[DstIndex - 1].Weight += CC.Weight;
2119 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2121 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2122 sizeof(Clusters[SrcIndex]));
2125 Clusters.resize(DstIndex);
2128 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2129 MachineBasicBlock *Last) {
2131 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2132 if (JTCases[i].first.HeaderBB == First)
2133 JTCases[i].first.HeaderBB = Last;
2135 // Update BitTestCases.
2136 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2137 if (BitTestCases[i].Parent == First)
2138 BitTestCases[i].Parent = Last;
2141 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2142 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2144 // Update machine-CFG edges with unique successors.
2145 SmallSet<BasicBlock*, 32> Done;
2146 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2147 BasicBlock *BB = I.getSuccessor(i);
2148 bool Inserted = Done.insert(BB).second;
2152 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2153 addSuccessorWithWeight(IndirectBrMBB, Succ);
2156 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2157 MVT::Other, getControlRoot(),
2158 getValue(I.getAddress())));
2161 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2162 if (DAG.getTarget().Options.TrapUnreachable)
2163 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2166 void SelectionDAGBuilder::visitFSub(const User &I) {
2167 // -0.0 - X --> fneg
2168 Type *Ty = I.getType();
2169 if (isa<Constant>(I.getOperand(0)) &&
2170 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2171 SDValue Op2 = getValue(I.getOperand(1));
2172 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2173 Op2.getValueType(), Op2));
2177 visitBinary(I, ISD::FSUB);
2180 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2181 SDValue Op1 = getValue(I.getOperand(0));
2182 SDValue Op2 = getValue(I.getOperand(1));
2189 if (const OverflowingBinaryOperator *OFBinOp =
2190 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2191 nuw = OFBinOp->hasNoUnsignedWrap();
2192 nsw = OFBinOp->hasNoSignedWrap();
2194 if (const PossiblyExactOperator *ExactOp =
2195 dyn_cast<const PossiblyExactOperator>(&I))
2196 exact = ExactOp->isExact();
2197 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2198 FMF = FPOp->getFastMathFlags();
2201 Flags.setExact(exact);
2202 Flags.setNoSignedWrap(nsw);
2203 Flags.setNoUnsignedWrap(nuw);
2204 if (EnableFMFInDAG) {
2205 Flags.setAllowReciprocal(FMF.allowReciprocal());
2206 Flags.setNoInfs(FMF.noInfs());
2207 Flags.setNoNaNs(FMF.noNaNs());
2208 Flags.setNoSignedZeros(FMF.noSignedZeros());
2209 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2211 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2213 setValue(&I, BinNodeValue);
2216 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2217 SDValue Op1 = getValue(I.getOperand(0));
2218 SDValue Op2 = getValue(I.getOperand(1));
2220 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2221 Op2.getValueType(), DAG.getDataLayout());
2223 // Coerce the shift amount to the right type if we can.
2224 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2225 unsigned ShiftSize = ShiftTy.getSizeInBits();
2226 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2227 SDLoc DL = getCurSDLoc();
2229 // If the operand is smaller than the shift count type, promote it.
2230 if (ShiftSize > Op2Size)
2231 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2233 // If the operand is larger than the shift count type but the shift
2234 // count type has enough bits to represent any shift value, truncate
2235 // it now. This is a common case and it exposes the truncate to
2236 // optimization early.
2237 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2238 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2239 // Otherwise we'll need to temporarily settle for some other convenient
2240 // type. Type legalization will make adjustments once the shiftee is split.
2242 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2249 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2251 if (const OverflowingBinaryOperator *OFBinOp =
2252 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2253 nuw = OFBinOp->hasNoUnsignedWrap();
2254 nsw = OFBinOp->hasNoSignedWrap();
2256 if (const PossiblyExactOperator *ExactOp =
2257 dyn_cast<const PossiblyExactOperator>(&I))
2258 exact = ExactOp->isExact();
2261 Flags.setExact(exact);
2262 Flags.setNoSignedWrap(nsw);
2263 Flags.setNoUnsignedWrap(nuw);
2264 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2269 void SelectionDAGBuilder::visitSDiv(const User &I) {
2270 SDValue Op1 = getValue(I.getOperand(0));
2271 SDValue Op2 = getValue(I.getOperand(1));
2274 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2275 cast<PossiblyExactOperator>(&I)->isExact());
2276 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2280 void SelectionDAGBuilder::visitICmp(const User &I) {
2281 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2282 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2283 predicate = IC->getPredicate();
2284 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2285 predicate = ICmpInst::Predicate(IC->getPredicate());
2286 SDValue Op1 = getValue(I.getOperand(0));
2287 SDValue Op2 = getValue(I.getOperand(1));
2288 ISD::CondCode Opcode = getICmpCondCode(predicate);
2290 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2292 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2295 void SelectionDAGBuilder::visitFCmp(const User &I) {
2296 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2297 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2298 predicate = FC->getPredicate();
2299 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2300 predicate = FCmpInst::Predicate(FC->getPredicate());
2301 SDValue Op1 = getValue(I.getOperand(0));
2302 SDValue Op2 = getValue(I.getOperand(1));
2303 ISD::CondCode Condition = getFCmpCondCode(predicate);
2304 if (TM.Options.NoNaNsFPMath)
2305 Condition = getFCmpCodeWithoutNaN(Condition);
2306 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2308 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2311 void SelectionDAGBuilder::visitSelect(const User &I) {
2312 SmallVector<EVT, 4> ValueVTs;
2313 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2315 unsigned NumValues = ValueVTs.size();
2316 if (NumValues == 0) return;
2318 SmallVector<SDValue, 4> Values(NumValues);
2319 SDValue Cond = getValue(I.getOperand(0));
2320 SDValue LHSVal = getValue(I.getOperand(1));
2321 SDValue RHSVal = getValue(I.getOperand(2));
2322 auto BaseOps = {Cond};
2323 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2324 ISD::VSELECT : ISD::SELECT;
2326 // Min/max matching is only viable if all output VTs are the same.
2327 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2328 EVT VT = ValueVTs[0];
2329 LLVMContext &Ctx = *DAG.getContext();
2330 auto &TLI = DAG.getTargetLoweringInfo();
2331 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2332 VT = TLI.getTypeToTransformTo(Ctx, VT);
2335 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2336 ISD::NodeType Opc = ISD::DELETED_NODE;
2337 switch (SPR.Flavor) {
2338 case SPF_UMAX: Opc = ISD::UMAX; break;
2339 case SPF_UMIN: Opc = ISD::UMIN; break;
2340 case SPF_SMAX: Opc = ISD::SMAX; break;
2341 case SPF_SMIN: Opc = ISD::SMIN; break;
2343 switch (SPR.NaNBehavior) {
2344 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2345 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2346 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2347 case SPNB_RETURNS_ANY:
2348 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2354 switch (SPR.NaNBehavior) {
2355 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2356 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2357 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2358 case SPNB_RETURNS_ANY:
2359 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2367 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2368 // If the underlying comparison instruction is used by any other instruction,
2369 // the consumed instructions won't be destroyed, so it is not profitable
2370 // to convert to a min/max.
2371 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2373 LHSVal = getValue(LHS);
2374 RHSVal = getValue(RHS);
2379 for (unsigned i = 0; i != NumValues; ++i) {
2380 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2381 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2382 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2383 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2384 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2388 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2389 DAG.getVTList(ValueVTs), Values));
2392 void SelectionDAGBuilder::visitTrunc(const User &I) {
2393 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2394 SDValue N = getValue(I.getOperand(0));
2395 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2397 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2400 void SelectionDAGBuilder::visitZExt(const User &I) {
2401 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2402 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2403 SDValue N = getValue(I.getOperand(0));
2404 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2406 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2409 void SelectionDAGBuilder::visitSExt(const User &I) {
2410 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2411 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2412 SDValue N = getValue(I.getOperand(0));
2413 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2415 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2418 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2419 // FPTrunc is never a no-op cast, no need to check
2420 SDValue N = getValue(I.getOperand(0));
2421 SDLoc dl = getCurSDLoc();
2422 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2423 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2424 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2425 DAG.getTargetConstant(
2426 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2429 void SelectionDAGBuilder::visitFPExt(const User &I) {
2430 // FPExt is never a no-op cast, no need to check
2431 SDValue N = getValue(I.getOperand(0));
2432 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2434 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2437 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2438 // FPToUI is never a no-op cast, no need to check
2439 SDValue N = getValue(I.getOperand(0));
2440 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2442 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2445 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2446 // FPToSI is never a no-op cast, no need to check
2447 SDValue N = getValue(I.getOperand(0));
2448 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2450 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2453 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2454 // UIToFP is never a no-op cast, no need to check
2455 SDValue N = getValue(I.getOperand(0));
2456 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2458 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2461 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2462 // SIToFP is never a no-op cast, no need to check
2463 SDValue N = getValue(I.getOperand(0));
2464 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2466 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2469 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2470 // What to do depends on the size of the integer and the size of the pointer.
2471 // We can either truncate, zero extend, or no-op, accordingly.
2472 SDValue N = getValue(I.getOperand(0));
2473 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2475 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2478 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2479 // What to do depends on the size of the integer and the size of the pointer.
2480 // We can either truncate, zero extend, or no-op, accordingly.
2481 SDValue N = getValue(I.getOperand(0));
2482 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2484 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2487 void SelectionDAGBuilder::visitBitCast(const User &I) {
2488 SDValue N = getValue(I.getOperand(0));
2489 SDLoc dl = getCurSDLoc();
2490 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2493 // BitCast assures us that source and destination are the same size so this is
2494 // either a BITCAST or a no-op.
2495 if (DestVT != N.getValueType())
2496 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2497 DestVT, N)); // convert types.
2498 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2499 // might fold any kind of constant expression to an integer constant and that
2500 // is not what we are looking for. Only regcognize a bitcast of a genuine
2501 // constant integer as an opaque constant.
2502 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2503 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2506 setValue(&I, N); // noop cast.
2509 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2510 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2511 const Value *SV = I.getOperand(0);
2512 SDValue N = getValue(SV);
2513 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2515 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2516 unsigned DestAS = I.getType()->getPointerAddressSpace();
2518 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2519 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2524 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2525 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2526 SDValue InVec = getValue(I.getOperand(0));
2527 SDValue InVal = getValue(I.getOperand(1));
2528 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2529 TLI.getVectorIdxTy(DAG.getDataLayout()));
2530 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2531 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2532 InVec, InVal, InIdx));
2535 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2537 SDValue InVec = getValue(I.getOperand(0));
2538 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2539 TLI.getVectorIdxTy(DAG.getDataLayout()));
2540 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2541 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2545 // Utility for visitShuffleVector - Return true if every element in Mask,
2546 // beginning from position Pos and ending in Pos+Size, falls within the
2547 // specified sequential range [L, L+Pos). or is undef.
2548 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2549 unsigned Pos, unsigned Size, int Low) {
2550 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2551 if (Mask[i] >= 0 && Mask[i] != Low)
2556 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2557 SDValue Src1 = getValue(I.getOperand(0));
2558 SDValue Src2 = getValue(I.getOperand(1));
2560 SmallVector<int, 8> Mask;
2561 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2562 unsigned MaskNumElts = Mask.size();
2564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2565 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2566 EVT SrcVT = Src1.getValueType();
2567 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2569 if (SrcNumElts == MaskNumElts) {
2570 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2575 // Normalize the shuffle vector since mask and vector length don't match.
2576 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2577 // Mask is longer than the source vectors and is a multiple of the source
2578 // vectors. We can use concatenate vector to make the mask and vectors
2580 if (SrcNumElts*2 == MaskNumElts) {
2581 // First check for Src1 in low and Src2 in high
2582 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2583 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2584 // The shuffle is concatenating two vectors together.
2585 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2589 // Then check for Src2 in low and Src1 in high
2590 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2591 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2592 // The shuffle is concatenating two vectors together.
2593 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2599 // Pad both vectors with undefs to make them the same length as the mask.
2600 unsigned NumConcat = MaskNumElts / SrcNumElts;
2601 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2602 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2603 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2605 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2606 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2610 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2611 getCurSDLoc(), VT, MOps1);
2612 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2613 getCurSDLoc(), VT, MOps2);
2615 // Readjust mask for new input vector length.
2616 SmallVector<int, 8> MappedOps;
2617 for (unsigned i = 0; i != MaskNumElts; ++i) {
2619 if (Idx >= (int)SrcNumElts)
2620 Idx -= SrcNumElts - MaskNumElts;
2621 MappedOps.push_back(Idx);
2624 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2629 if (SrcNumElts > MaskNumElts) {
2630 // Analyze the access pattern of the vector to see if we can extract
2631 // two subvectors and do the shuffle. The analysis is done by calculating
2632 // the range of elements the mask access on both vectors.
2633 int MinRange[2] = { static_cast<int>(SrcNumElts),
2634 static_cast<int>(SrcNumElts)};
2635 int MaxRange[2] = {-1, -1};
2637 for (unsigned i = 0; i != MaskNumElts; ++i) {
2643 if (Idx >= (int)SrcNumElts) {
2647 if (Idx > MaxRange[Input])
2648 MaxRange[Input] = Idx;
2649 if (Idx < MinRange[Input])
2650 MinRange[Input] = Idx;
2653 // Check if the access is smaller than the vector size and can we find
2654 // a reasonable extract index.
2655 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2657 int StartIdx[2]; // StartIdx to extract from
2658 for (unsigned Input = 0; Input < 2; ++Input) {
2659 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2660 RangeUse[Input] = 0; // Unused
2661 StartIdx[Input] = 0;
2665 // Find a good start index that is a multiple of the mask length. Then
2666 // see if the rest of the elements are in range.
2667 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2668 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2669 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2670 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2673 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2674 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2677 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2678 // Extract appropriate subvector and generate a vector shuffle
2679 for (unsigned Input = 0; Input < 2; ++Input) {
2680 SDValue &Src = Input == 0 ? Src1 : Src2;
2681 if (RangeUse[Input] == 0)
2682 Src = DAG.getUNDEF(VT);
2684 SDLoc dl = getCurSDLoc();
2686 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2687 DAG.getConstant(StartIdx[Input], dl,
2688 TLI.getVectorIdxTy(DAG.getDataLayout())));
2692 // Calculate new mask.
2693 SmallVector<int, 8> MappedOps;
2694 for (unsigned i = 0; i != MaskNumElts; ++i) {
2697 if (Idx < (int)SrcNumElts)
2700 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2702 MappedOps.push_back(Idx);
2705 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2711 // We can't use either concat vectors or extract subvectors so fall back to
2712 // replacing the shuffle with extract and build vector.
2713 // to insert and build vector.
2714 EVT EltVT = VT.getVectorElementType();
2715 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2716 SDLoc dl = getCurSDLoc();
2717 SmallVector<SDValue,8> Ops;
2718 for (unsigned i = 0; i != MaskNumElts; ++i) {
2723 Res = DAG.getUNDEF(EltVT);
2725 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2726 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2728 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2729 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2735 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2738 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2739 const Value *Op0 = I.getOperand(0);
2740 const Value *Op1 = I.getOperand(1);
2741 Type *AggTy = I.getType();
2742 Type *ValTy = Op1->getType();
2743 bool IntoUndef = isa<UndefValue>(Op0);
2744 bool FromUndef = isa<UndefValue>(Op1);
2746 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2749 SmallVector<EVT, 4> AggValueVTs;
2750 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2751 SmallVector<EVT, 4> ValValueVTs;
2752 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2754 unsigned NumAggValues = AggValueVTs.size();
2755 unsigned NumValValues = ValValueVTs.size();
2756 SmallVector<SDValue, 4> Values(NumAggValues);
2758 // Ignore an insertvalue that produces an empty object
2759 if (!NumAggValues) {
2760 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2764 SDValue Agg = getValue(Op0);
2766 // Copy the beginning value(s) from the original aggregate.
2767 for (; i != LinearIndex; ++i)
2768 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2769 SDValue(Agg.getNode(), Agg.getResNo() + i);
2770 // Copy values from the inserted value(s).
2772 SDValue Val = getValue(Op1);
2773 for (; i != LinearIndex + NumValValues; ++i)
2774 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2775 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2777 // Copy remaining value(s) from the original aggregate.
2778 for (; i != NumAggValues; ++i)
2779 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2780 SDValue(Agg.getNode(), Agg.getResNo() + i);
2782 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2783 DAG.getVTList(AggValueVTs), Values));
2786 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2787 const Value *Op0 = I.getOperand(0);
2788 Type *AggTy = Op0->getType();
2789 Type *ValTy = I.getType();
2790 bool OutOfUndef = isa<UndefValue>(Op0);
2792 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2794 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2795 SmallVector<EVT, 4> ValValueVTs;
2796 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2798 unsigned NumValValues = ValValueVTs.size();
2800 // Ignore a extractvalue that produces an empty object
2801 if (!NumValValues) {
2802 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2806 SmallVector<SDValue, 4> Values(NumValValues);
2808 SDValue Agg = getValue(Op0);
2809 // Copy out the selected value(s).
2810 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2811 Values[i - LinearIndex] =
2813 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2814 SDValue(Agg.getNode(), Agg.getResNo() + i);
2816 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2817 DAG.getVTList(ValValueVTs), Values));
2820 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2821 Value *Op0 = I.getOperand(0);
2822 // Note that the pointer operand may be a vector of pointers. Take the scalar
2823 // element which holds a pointer.
2824 Type *Ty = Op0->getType()->getScalarType();
2825 unsigned AS = Ty->getPointerAddressSpace();
2826 SDValue N = getValue(Op0);
2827 SDLoc dl = getCurSDLoc();
2829 // Normalize Vector GEP - all scalar operands should be converted to the
2831 unsigned VectorWidth = I.getType()->isVectorTy() ?
2832 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2834 if (VectorWidth && !N.getValueType().isVector()) {
2835 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2836 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2837 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2839 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2841 const Value *Idx = *OI;
2842 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2843 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2846 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2847 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2848 DAG.getConstant(Offset, dl, N.getValueType()));
2851 Ty = StTy->getElementType(Field);
2853 Ty = cast<SequentialType>(Ty)->getElementType();
2855 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2856 unsigned PtrSize = PtrTy.getSizeInBits();
2857 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2859 // If this is a scalar constant or a splat vector of constants,
2860 // handle it quickly.
2861 const auto *CI = dyn_cast<ConstantInt>(Idx);
2862 if (!CI && isa<ConstantDataVector>(Idx) &&
2863 cast<ConstantDataVector>(Idx)->getSplatValue())
2864 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2869 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2870 SDValue OffsVal = VectorWidth ?
2871 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2872 DAG.getConstant(Offs, dl, PtrTy);
2873 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2877 // N = N + Idx * ElementSize;
2878 SDValue IdxN = getValue(Idx);
2880 if (!IdxN.getValueType().isVector() && VectorWidth) {
2881 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2882 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2883 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2885 // If the index is smaller or larger than intptr_t, truncate or extend
2887 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2889 // If this is a multiply by a power of two, turn it into a shl
2890 // immediately. This is a very common case.
2891 if (ElementSize != 1) {
2892 if (ElementSize.isPowerOf2()) {
2893 unsigned Amt = ElementSize.logBase2();
2894 IdxN = DAG.getNode(ISD::SHL, dl,
2895 N.getValueType(), IdxN,
2896 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2898 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2899 IdxN = DAG.getNode(ISD::MUL, dl,
2900 N.getValueType(), IdxN, Scale);
2904 N = DAG.getNode(ISD::ADD, dl,
2905 N.getValueType(), N, IdxN);
2912 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2913 // If this is a fixed sized alloca in the entry block of the function,
2914 // allocate it statically on the stack.
2915 if (FuncInfo.StaticAllocaMap.count(&I))
2916 return; // getValue will auto-populate this.
2918 SDLoc dl = getCurSDLoc();
2919 Type *Ty = I.getAllocatedType();
2920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2921 auto &DL = DAG.getDataLayout();
2922 uint64_t TySize = DL.getTypeAllocSize(Ty);
2924 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2926 SDValue AllocSize = getValue(I.getArraySize());
2928 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2929 if (AllocSize.getValueType() != IntPtr)
2930 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2932 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2934 DAG.getConstant(TySize, dl, IntPtr));
2936 // Handle alignment. If the requested alignment is less than or equal to
2937 // the stack alignment, ignore it. If the size is greater than or equal to
2938 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2939 unsigned StackAlign =
2940 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2941 if (Align <= StackAlign)
2944 // Round the size of the allocation up to the stack alignment size
2945 // by add SA-1 to the size.
2946 AllocSize = DAG.getNode(ISD::ADD, dl,
2947 AllocSize.getValueType(), AllocSize,
2948 DAG.getIntPtrConstant(StackAlign - 1, dl));
2950 // Mask out the low bits for alignment purposes.
2951 AllocSize = DAG.getNode(ISD::AND, dl,
2952 AllocSize.getValueType(), AllocSize,
2953 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2956 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2957 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2958 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2960 DAG.setRoot(DSA.getValue(1));
2962 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2965 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2967 return visitAtomicLoad(I);
2969 const Value *SV = I.getOperand(0);
2970 SDValue Ptr = getValue(SV);
2972 Type *Ty = I.getType();
2974 bool isVolatile = I.isVolatile();
2975 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2977 // The IR notion of invariant_load only guarantees that all *non-faulting*
2978 // invariant loads result in the same value. The MI notion of invariant load
2979 // guarantees that the load can be legally moved to any location within its
2980 // containing function. The MI notion of invariant_load is stronger than the
2981 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2982 // with a guarantee that the location being loaded from is dereferenceable
2983 // throughout the function's lifetime.
2985 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2986 isDereferenceablePointer(SV, DAG.getDataLayout());
2987 unsigned Alignment = I.getAlignment();
2990 I.getAAMetadata(AAInfo);
2991 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2994 SmallVector<EVT, 4> ValueVTs;
2995 SmallVector<uint64_t, 4> Offsets;
2996 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2997 unsigned NumValues = ValueVTs.size();
3002 bool ConstantMemory = false;
3003 if (isVolatile || NumValues > MaxParallelChains)
3004 // Serialize volatile loads with other side effects.
3006 else if (AA->pointsToConstantMemory(MemoryLocation(
3007 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3008 // Do not serialize (non-volatile) loads of constant memory with anything.
3009 Root = DAG.getEntryNode();
3010 ConstantMemory = true;
3012 // Do not serialize non-volatile loads against each other.
3013 Root = DAG.getRoot();
3016 SDLoc dl = getCurSDLoc();
3019 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3021 SmallVector<SDValue, 4> Values(NumValues);
3022 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3023 EVT PtrVT = Ptr.getValueType();
3024 unsigned ChainI = 0;
3025 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3026 // Serializing loads here may result in excessive register pressure, and
3027 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3028 // could recover a bit by hoisting nodes upward in the chain by recognizing
3029 // they are side-effect free or do not alias. The optimizer should really
3030 // avoid this case by converting large object/array copies to llvm.memcpy
3031 // (MaxParallelChains should always remain as failsafe).
3032 if (ChainI == MaxParallelChains) {
3033 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3034 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3035 makeArrayRef(Chains.data(), ChainI));
3039 SDValue A = DAG.getNode(ISD::ADD, dl,
3041 DAG.getConstant(Offsets[i], dl, PtrVT));
3042 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3043 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3044 isNonTemporal, isInvariant, Alignment, AAInfo,
3048 Chains[ChainI] = L.getValue(1);
3051 if (!ConstantMemory) {
3052 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3053 makeArrayRef(Chains.data(), ChainI));
3057 PendingLoads.push_back(Chain);
3060 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3061 DAG.getVTList(ValueVTs), Values));
3064 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3066 return visitAtomicStore(I);
3068 const Value *SrcV = I.getOperand(0);
3069 const Value *PtrV = I.getOperand(1);
3071 SmallVector<EVT, 4> ValueVTs;
3072 SmallVector<uint64_t, 4> Offsets;
3073 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3074 SrcV->getType(), ValueVTs, &Offsets);
3075 unsigned NumValues = ValueVTs.size();
3079 // Get the lowered operands. Note that we do this after
3080 // checking if NumResults is zero, because with zero results
3081 // the operands won't have values in the map.
3082 SDValue Src = getValue(SrcV);
3083 SDValue Ptr = getValue(PtrV);
3085 SDValue Root = getRoot();
3086 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3087 EVT PtrVT = Ptr.getValueType();
3088 bool isVolatile = I.isVolatile();
3089 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3090 unsigned Alignment = I.getAlignment();
3091 SDLoc dl = getCurSDLoc();
3094 I.getAAMetadata(AAInfo);
3096 unsigned ChainI = 0;
3097 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3098 // See visitLoad comments.
3099 if (ChainI == MaxParallelChains) {
3100 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3101 makeArrayRef(Chains.data(), ChainI));
3105 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3106 DAG.getConstant(Offsets[i], dl, PtrVT));
3107 SDValue St = DAG.getStore(Root, dl,
3108 SDValue(Src.getNode(), Src.getResNo() + i),
3109 Add, MachinePointerInfo(PtrV, Offsets[i]),
3110 isVolatile, isNonTemporal, Alignment, AAInfo);
3111 Chains[ChainI] = St;
3114 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3115 makeArrayRef(Chains.data(), ChainI));
3116 DAG.setRoot(StoreNode);
3119 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3120 SDLoc sdl = getCurSDLoc();
3122 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3123 Value *PtrOperand = I.getArgOperand(1);
3124 SDValue Ptr = getValue(PtrOperand);
3125 SDValue Src0 = getValue(I.getArgOperand(0));
3126 SDValue Mask = getValue(I.getArgOperand(3));
3127 EVT VT = Src0.getValueType();
3128 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3130 Alignment = DAG.getEVTAlignment(VT);
3133 I.getAAMetadata(AAInfo);
3135 MachineMemOperand *MMO =
3136 DAG.getMachineFunction().
3137 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3138 MachineMemOperand::MOStore, VT.getStoreSize(),
3140 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3142 DAG.setRoot(StoreNode);
3143 setValue(&I, StoreNode);
3146 // Get a uniform base for the Gather/Scatter intrinsic.
3147 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3148 // We try to represent it as a base pointer + vector of indices.
3149 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3150 // The first operand of the GEP may be a single pointer or a vector of pointers
3152 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3154 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3155 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3157 // When the first GEP operand is a single pointer - it is the uniform base we
3158 // are looking for. If first operand of the GEP is a splat vector - we
3159 // extract the spalt value and use it as a uniform base.
3160 // In all other cases the function returns 'false'.
3162 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3163 SelectionDAGBuilder* SDB) {
3165 SelectionDAG& DAG = SDB->DAG;
3166 LLVMContext &Context = *DAG.getContext();
3168 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3169 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3170 if (!GEP || GEP->getNumOperands() > 2)
3173 Value *GEPPtr = GEP->getPointerOperand();
3174 if (!GEPPtr->getType()->isVectorTy())
3176 else if (!(Ptr = getSplatValue(GEPPtr)))
3179 Value *IndexVal = GEP->getOperand(1);
3181 // The operands of the GEP may be defined in another basic block.
3182 // In this case we'll not find nodes for the operands.
3183 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3186 Base = SDB->getValue(Ptr);
3187 Index = SDB->getValue(IndexVal);
3189 // Suppress sign extension.
3190 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3191 if (SDB->findValue(Sext->getOperand(0))) {
3192 IndexVal = Sext->getOperand(0);
3193 Index = SDB->getValue(IndexVal);
3196 if (!Index.getValueType().isVector()) {
3197 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3198 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3199 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3200 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3205 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3206 SDLoc sdl = getCurSDLoc();
3208 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3209 Value *Ptr = I.getArgOperand(1);
3210 SDValue Src0 = getValue(I.getArgOperand(0));
3211 SDValue Mask = getValue(I.getArgOperand(3));
3212 EVT VT = Src0.getValueType();
3213 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3215 Alignment = DAG.getEVTAlignment(VT);
3216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3219 I.getAAMetadata(AAInfo);
3223 Value *BasePtr = Ptr;
3224 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3226 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3227 MachineMemOperand *MMO = DAG.getMachineFunction().
3228 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3229 MachineMemOperand::MOStore, VT.getStoreSize(),
3232 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3233 Index = getValue(Ptr);
3235 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3236 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3238 DAG.setRoot(Scatter);
3239 setValue(&I, Scatter);
3242 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3243 SDLoc sdl = getCurSDLoc();
3245 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3246 Value *PtrOperand = I.getArgOperand(0);
3247 SDValue Ptr = getValue(PtrOperand);
3248 SDValue Src0 = getValue(I.getArgOperand(3));
3249 SDValue Mask = getValue(I.getArgOperand(2));
3251 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3252 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3253 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3255 Alignment = DAG.getEVTAlignment(VT);
3258 I.getAAMetadata(AAInfo);
3259 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3261 SDValue InChain = DAG.getRoot();
3262 if (AA->pointsToConstantMemory(MemoryLocation(
3263 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3265 // Do not serialize (non-volatile) loads of constant memory with anything.
3266 InChain = DAG.getEntryNode();
3269 MachineMemOperand *MMO =
3270 DAG.getMachineFunction().
3271 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3272 MachineMemOperand::MOLoad, VT.getStoreSize(),
3273 Alignment, AAInfo, Ranges);
3275 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3277 SDValue OutChain = Load.getValue(1);
3278 DAG.setRoot(OutChain);
3282 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3283 SDLoc sdl = getCurSDLoc();
3285 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3286 Value *Ptr = I.getArgOperand(0);
3287 SDValue Src0 = getValue(I.getArgOperand(3));
3288 SDValue Mask = getValue(I.getArgOperand(2));
3290 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3291 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3292 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3294 Alignment = DAG.getEVTAlignment(VT);
3297 I.getAAMetadata(AAInfo);
3298 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3300 SDValue Root = DAG.getRoot();
3303 Value *BasePtr = Ptr;
3304 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3305 bool ConstantMemory = false;
3307 AA->pointsToConstantMemory(MemoryLocation(
3308 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3310 // Do not serialize (non-volatile) loads of constant memory with anything.
3311 Root = DAG.getEntryNode();
3312 ConstantMemory = true;
3315 MachineMemOperand *MMO =
3316 DAG.getMachineFunction().
3317 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3318 MachineMemOperand::MOLoad, VT.getStoreSize(),
3319 Alignment, AAInfo, Ranges);
3322 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3323 Index = getValue(Ptr);
3325 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3326 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3329 SDValue OutChain = Gather.getValue(1);
3330 if (!ConstantMemory)
3331 PendingLoads.push_back(OutChain);
3332 setValue(&I, Gather);
3335 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3336 SDLoc dl = getCurSDLoc();
3337 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3338 AtomicOrdering FailureOrder = I.getFailureOrdering();
3339 SynchronizationScope Scope = I.getSynchScope();
3341 SDValue InChain = getRoot();
3343 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3344 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3345 SDValue L = DAG.getAtomicCmpSwap(
3346 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3347 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3348 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3349 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3351 SDValue OutChain = L.getValue(2);
3354 DAG.setRoot(OutChain);
3357 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3358 SDLoc dl = getCurSDLoc();
3360 switch (I.getOperation()) {
3361 default: llvm_unreachable("Unknown atomicrmw operation");
3362 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3363 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3364 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3365 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3366 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3367 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3368 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3369 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3370 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3371 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3372 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3374 AtomicOrdering Order = I.getOrdering();
3375 SynchronizationScope Scope = I.getSynchScope();
3377 SDValue InChain = getRoot();
3380 DAG.getAtomic(NT, dl,
3381 getValue(I.getValOperand()).getSimpleValueType(),
3383 getValue(I.getPointerOperand()),
3384 getValue(I.getValOperand()),
3385 I.getPointerOperand(),
3386 /* Alignment=*/ 0, Order, Scope);
3388 SDValue OutChain = L.getValue(1);
3391 DAG.setRoot(OutChain);
3394 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3395 SDLoc dl = getCurSDLoc();
3396 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3399 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3400 TLI.getPointerTy(DAG.getDataLayout()));
3401 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3402 TLI.getPointerTy(DAG.getDataLayout()));
3403 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3406 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3407 SDLoc dl = getCurSDLoc();
3408 AtomicOrdering Order = I.getOrdering();
3409 SynchronizationScope Scope = I.getSynchScope();
3411 SDValue InChain = getRoot();
3413 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3414 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3416 if (I.getAlignment() < VT.getSizeInBits() / 8)
3417 report_fatal_error("Cannot generate unaligned atomic load");
3419 MachineMemOperand *MMO =
3420 DAG.getMachineFunction().
3421 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3422 MachineMemOperand::MOVolatile |
3423 MachineMemOperand::MOLoad,
3425 I.getAlignment() ? I.getAlignment() :
3426 DAG.getEVTAlignment(VT));
3428 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3430 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3431 getValue(I.getPointerOperand()), MMO,
3434 SDValue OutChain = L.getValue(1);
3437 DAG.setRoot(OutChain);
3440 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3441 SDLoc dl = getCurSDLoc();
3443 AtomicOrdering Order = I.getOrdering();
3444 SynchronizationScope Scope = I.getSynchScope();
3446 SDValue InChain = getRoot();
3448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3450 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3452 if (I.getAlignment() < VT.getSizeInBits() / 8)
3453 report_fatal_error("Cannot generate unaligned atomic store");
3456 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3458 getValue(I.getPointerOperand()),
3459 getValue(I.getValueOperand()),
3460 I.getPointerOperand(), I.getAlignment(),
3463 DAG.setRoot(OutChain);
3466 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3468 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3469 unsigned Intrinsic) {
3470 bool HasChain = !I.doesNotAccessMemory();
3471 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3473 // Build the operand list.
3474 SmallVector<SDValue, 8> Ops;
3475 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3477 // We don't need to serialize loads against other loads.
3478 Ops.push_back(DAG.getRoot());
3480 Ops.push_back(getRoot());
3484 // Info is set by getTgtMemInstrinsic
3485 TargetLowering::IntrinsicInfo Info;
3486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3487 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3489 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3490 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3491 Info.opc == ISD::INTRINSIC_W_CHAIN)
3492 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3493 TLI.getPointerTy(DAG.getDataLayout())));
3495 // Add all operands of the call to the operand list.
3496 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3497 SDValue Op = getValue(I.getArgOperand(i));
3501 SmallVector<EVT, 4> ValueVTs;
3502 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3505 ValueVTs.push_back(MVT::Other);
3507 SDVTList VTs = DAG.getVTList(ValueVTs);
3511 if (IsTgtIntrinsic) {
3512 // This is target intrinsic that touches memory
3513 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3514 VTs, Ops, Info.memVT,
3515 MachinePointerInfo(Info.ptrVal, Info.offset),
3516 Info.align, Info.vol,
3517 Info.readMem, Info.writeMem, Info.size);
3518 } else if (!HasChain) {
3519 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3520 } else if (!I.getType()->isVoidTy()) {
3521 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3523 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3527 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3529 PendingLoads.push_back(Chain);
3534 if (!I.getType()->isVoidTy()) {
3535 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3536 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3537 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3540 setValue(&I, Result);
3544 /// GetSignificand - Get the significand and build it into a floating-point
3545 /// number with exponent of 1:
3547 /// Op = (Op & 0x007fffff) | 0x3f800000;
3549 /// where Op is the hexadecimal representation of floating point value.
3551 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3552 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3553 DAG.getConstant(0x007fffff, dl, MVT::i32));
3554 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3555 DAG.getConstant(0x3f800000, dl, MVT::i32));
3556 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3559 /// GetExponent - Get the exponent:
3561 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3563 /// where Op is the hexadecimal representation of floating point value.
3565 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3567 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3568 DAG.getConstant(0x7f800000, dl, MVT::i32));
3569 SDValue t1 = DAG.getNode(
3570 ISD::SRL, dl, MVT::i32, t0,
3571 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3572 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3573 DAG.getConstant(127, dl, MVT::i32));
3574 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3577 /// getF32Constant - Get 32-bit floating point constant.
3579 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3580 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3584 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3585 SelectionDAG &DAG) {
3586 // IntegerPartOfX = ((int32_t)(t0);
3587 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3589 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3590 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3591 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3593 // IntegerPartOfX <<= 23;
3594 IntegerPartOfX = DAG.getNode(
3595 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3596 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3597 DAG.getDataLayout())));
3599 SDValue TwoToFractionalPartOfX;
3600 if (LimitFloatPrecision <= 6) {
3601 // For floating-point precision of 6:
3603 // TwoToFractionalPartOfX =
3605 // (0.735607626f + 0.252464424f * x) * x;
3607 // error 0.0144103317, which is 6 bits
3608 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3609 getF32Constant(DAG, 0x3e814304, dl));
3610 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3611 getF32Constant(DAG, 0x3f3c50c8, dl));
3612 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3613 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3614 getF32Constant(DAG, 0x3f7f5e7e, dl));
3615 } else if (LimitFloatPrecision <= 12) {
3616 // For floating-point precision of 12:
3618 // TwoToFractionalPartOfX =
3621 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3623 // error 0.000107046256, which is 13 to 14 bits
3624 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3625 getF32Constant(DAG, 0x3da235e3, dl));
3626 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3627 getF32Constant(DAG, 0x3e65b8f3, dl));
3628 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3629 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3630 getF32Constant(DAG, 0x3f324b07, dl));
3631 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3632 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3633 getF32Constant(DAG, 0x3f7ff8fd, dl));
3634 } else { // LimitFloatPrecision <= 18
3635 // For floating-point precision of 18:
3637 // TwoToFractionalPartOfX =
3641 // (0.554906021e-1f +
3642 // (0.961591928e-2f +
3643 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3644 // error 2.47208000*10^(-7), which is better than 18 bits
3645 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3646 getF32Constant(DAG, 0x3924b03e, dl));
3647 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3648 getF32Constant(DAG, 0x3ab24b87, dl));
3649 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3650 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3651 getF32Constant(DAG, 0x3c1d8c17, dl));
3652 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3653 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3654 getF32Constant(DAG, 0x3d634a1d, dl));
3655 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3656 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3657 getF32Constant(DAG, 0x3e75fe14, dl));
3658 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3659 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3660 getF32Constant(DAG, 0x3f317234, dl));
3661 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3662 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3663 getF32Constant(DAG, 0x3f800000, dl));
3666 // Add the exponent into the result in integer domain.
3667 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3668 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3669 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3672 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3673 /// limited-precision mode.
3674 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3675 const TargetLowering &TLI) {
3676 if (Op.getValueType() == MVT::f32 &&
3677 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3679 // Put the exponent in the right bit position for later addition to the
3682 // #define LOG2OFe 1.4426950f
3683 // t0 = Op * LOG2OFe
3684 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3685 getF32Constant(DAG, 0x3fb8aa3b, dl));
3686 return getLimitedPrecisionExp2(t0, dl, DAG);
3689 // No special expansion.
3690 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3693 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3694 /// limited-precision mode.
3695 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3696 const TargetLowering &TLI) {
3697 if (Op.getValueType() == MVT::f32 &&
3698 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3699 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3701 // Scale the exponent by log(2) [0.69314718f].
3702 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3703 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3704 getF32Constant(DAG, 0x3f317218, dl));
3706 // Get the significand and build it into a floating-point number with
3708 SDValue X = GetSignificand(DAG, Op1, dl);
3710 SDValue LogOfMantissa;
3711 if (LimitFloatPrecision <= 6) {
3712 // For floating-point precision of 6:
3716 // (1.4034025f - 0.23903021f * x) * x;
3718 // error 0.0034276066, which is better than 8 bits
3719 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3720 getF32Constant(DAG, 0xbe74c456, dl));
3721 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3722 getF32Constant(DAG, 0x3fb3a2b1, dl));
3723 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3724 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3725 getF32Constant(DAG, 0x3f949a29, dl));
3726 } else if (LimitFloatPrecision <= 12) {
3727 // For floating-point precision of 12:
3733 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3735 // error 0.000061011436, which is 14 bits
3736 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3737 getF32Constant(DAG, 0xbd67b6d6, dl));
3738 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3739 getF32Constant(DAG, 0x3ee4f4b8, dl));
3740 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3741 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3742 getF32Constant(DAG, 0x3fbc278b, dl));
3743 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3744 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3745 getF32Constant(DAG, 0x40348e95, dl));
3746 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3747 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3748 getF32Constant(DAG, 0x3fdef31a, dl));
3749 } else { // LimitFloatPrecision <= 18
3750 // For floating-point precision of 18:
3758 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3760 // error 0.0000023660568, which is better than 18 bits
3761 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3762 getF32Constant(DAG, 0xbc91e5ac, dl));
3763 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3764 getF32Constant(DAG, 0x3e4350aa, dl));
3765 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3766 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3767 getF32Constant(DAG, 0x3f60d3e3, dl));
3768 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3769 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3770 getF32Constant(DAG, 0x4011cdf0, dl));
3771 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3772 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3773 getF32Constant(DAG, 0x406cfd1c, dl));
3774 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3775 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3776 getF32Constant(DAG, 0x408797cb, dl));
3777 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3778 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3779 getF32Constant(DAG, 0x4006dcab, dl));
3782 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3785 // No special expansion.
3786 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3789 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3790 /// limited-precision mode.
3791 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3792 const TargetLowering &TLI) {
3793 if (Op.getValueType() == MVT::f32 &&
3794 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3795 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3797 // Get the exponent.
3798 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3800 // Get the significand and build it into a floating-point number with
3802 SDValue X = GetSignificand(DAG, Op1, dl);
3804 // Different possible minimax approximations of significand in
3805 // floating-point for various degrees of accuracy over [1,2].
3806 SDValue Log2ofMantissa;
3807 if (LimitFloatPrecision <= 6) {
3808 // For floating-point precision of 6:
3810 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3812 // error 0.0049451742, which is more than 7 bits
3813 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3814 getF32Constant(DAG, 0xbeb08fe0, dl));
3815 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3816 getF32Constant(DAG, 0x40019463, dl));
3817 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3818 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3819 getF32Constant(DAG, 0x3fd6633d, dl));
3820 } else if (LimitFloatPrecision <= 12) {
3821 // For floating-point precision of 12:
3827 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3829 // error 0.0000876136000, which is better than 13 bits
3830 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3831 getF32Constant(DAG, 0xbda7262e, dl));
3832 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3833 getF32Constant(DAG, 0x3f25280b, dl));
3834 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3835 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3836 getF32Constant(DAG, 0x4007b923, dl));
3837 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3838 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3839 getF32Constant(DAG, 0x40823e2f, dl));
3840 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3841 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3842 getF32Constant(DAG, 0x4020d29c, dl));
3843 } else { // LimitFloatPrecision <= 18
3844 // For floating-point precision of 18:
3853 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3855 // error 0.0000018516, which is better than 18 bits
3856 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3857 getF32Constant(DAG, 0xbcd2769e, dl));
3858 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3859 getF32Constant(DAG, 0x3e8ce0b9, dl));
3860 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3861 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3862 getF32Constant(DAG, 0x3fa22ae7, dl));
3863 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3864 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3865 getF32Constant(DAG, 0x40525723, dl));
3866 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3867 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3868 getF32Constant(DAG, 0x40aaf200, dl));
3869 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3870 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3871 getF32Constant(DAG, 0x40c39dad, dl));
3872 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3873 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3874 getF32Constant(DAG, 0x4042902c, dl));
3877 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3880 // No special expansion.
3881 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3884 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3885 /// limited-precision mode.
3886 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3887 const TargetLowering &TLI) {
3888 if (Op.getValueType() == MVT::f32 &&
3889 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3890 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3892 // Scale the exponent by log10(2) [0.30102999f].
3893 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3894 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3895 getF32Constant(DAG, 0x3e9a209a, dl));
3897 // Get the significand and build it into a floating-point number with
3899 SDValue X = GetSignificand(DAG, Op1, dl);
3901 SDValue Log10ofMantissa;
3902 if (LimitFloatPrecision <= 6) {
3903 // For floating-point precision of 6:
3905 // Log10ofMantissa =
3907 // (0.60948995f - 0.10380950f * x) * x;
3909 // error 0.0014886165, which is 6 bits
3910 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3911 getF32Constant(DAG, 0xbdd49a13, dl));
3912 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3913 getF32Constant(DAG, 0x3f1c0789, dl));
3914 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3915 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3916 getF32Constant(DAG, 0x3f011300, dl));
3917 } else if (LimitFloatPrecision <= 12) {
3918 // For floating-point precision of 12:
3920 // Log10ofMantissa =
3923 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3925 // error 0.00019228036, which is better than 12 bits
3926 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3927 getF32Constant(DAG, 0x3d431f31, dl));
3928 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3929 getF32Constant(DAG, 0x3ea21fb2, dl));
3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3931 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3932 getF32Constant(DAG, 0x3f6ae232, dl));
3933 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3934 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3935 getF32Constant(DAG, 0x3f25f7c3, dl));
3936 } else { // LimitFloatPrecision <= 18
3937 // For floating-point precision of 18:
3939 // Log10ofMantissa =
3944 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3946 // error 0.0000037995730, which is better than 18 bits
3947 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3948 getF32Constant(DAG, 0x3c5d51ce, dl));
3949 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3950 getF32Constant(DAG, 0x3e00685a, dl));
3951 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3952 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3953 getF32Constant(DAG, 0x3efb6798, dl));
3954 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3955 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3956 getF32Constant(DAG, 0x3f88d192, dl));
3957 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3958 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3959 getF32Constant(DAG, 0x3fc4316c, dl));
3960 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3961 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3962 getF32Constant(DAG, 0x3f57ce70, dl));
3965 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3968 // No special expansion.
3969 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3972 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3973 /// limited-precision mode.
3974 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3975 const TargetLowering &TLI) {
3976 if (Op.getValueType() == MVT::f32 &&
3977 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3978 return getLimitedPrecisionExp2(Op, dl, DAG);
3980 // No special expansion.
3981 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3984 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3985 /// limited-precision mode with x == 10.0f.
3986 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3987 SelectionDAG &DAG, const TargetLowering &TLI) {
3988 bool IsExp10 = false;
3989 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3990 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3991 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3993 IsExp10 = LHSC->isExactlyValue(Ten);
3998 // Put the exponent in the right bit position for later addition to the
4001 // #define LOG2OF10 3.3219281f
4002 // t0 = Op * LOG2OF10;
4003 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4004 getF32Constant(DAG, 0x40549a78, dl));
4005 return getLimitedPrecisionExp2(t0, dl, DAG);
4008 // No special expansion.
4009 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4013 /// ExpandPowI - Expand a llvm.powi intrinsic.
4014 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4015 SelectionDAG &DAG) {
4016 // If RHS is a constant, we can expand this out to a multiplication tree,
4017 // otherwise we end up lowering to a call to __powidf2 (for example). When
4018 // optimizing for size, we only want to do this if the expansion would produce
4019 // a small number of multiplies, otherwise we do the full expansion.
4020 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4021 // Get the exponent as a positive value.
4022 unsigned Val = RHSC->getSExtValue();
4023 if ((int)Val < 0) Val = -Val;
4025 // powi(x, 0) -> 1.0
4027 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4029 const Function *F = DAG.getMachineFunction().getFunction();
4030 if (!F->optForSize() ||
4031 // If optimizing for size, don't insert too many multiplies.
4032 // This inserts up to 5 multiplies.
4033 countPopulation(Val) + Log2_32(Val) < 7) {
4034 // We use the simple binary decomposition method to generate the multiply
4035 // sequence. There are more optimal ways to do this (for example,
4036 // powi(x,15) generates one more multiply than it should), but this has
4037 // the benefit of being both really simple and much better than a libcall.
4038 SDValue Res; // Logically starts equal to 1.0
4039 SDValue CurSquare = LHS;
4043 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4045 Res = CurSquare; // 1.0*CurSquare.
4048 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4049 CurSquare, CurSquare);
4053 // If the original was negative, invert the result, producing 1/(x*x*x).
4054 if (RHSC->getSExtValue() < 0)
4055 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4056 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4061 // Otherwise, expand to a libcall.
4062 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4065 // getTruncatedArgReg - Find underlying register used for an truncated
4067 static unsigned getTruncatedArgReg(const SDValue &N) {
4068 if (N.getOpcode() != ISD::TRUNCATE)
4071 const SDValue &Ext = N.getOperand(0);
4072 if (Ext.getOpcode() == ISD::AssertZext ||
4073 Ext.getOpcode() == ISD::AssertSext) {
4074 const SDValue &CFR = Ext.getOperand(0);
4075 if (CFR.getOpcode() == ISD::CopyFromReg)
4076 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4077 if (CFR.getOpcode() == ISD::TRUNCATE)
4078 return getTruncatedArgReg(CFR);
4083 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4084 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4085 /// At the end of instruction selection, they will be inserted to the entry BB.
4086 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4087 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4088 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4089 const Argument *Arg = dyn_cast<Argument>(V);
4093 MachineFunction &MF = DAG.getMachineFunction();
4094 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4096 // Ignore inlined function arguments here.
4098 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4099 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4102 Optional<MachineOperand> Op;
4103 // Some arguments' frame index is recorded during argument lowering.
4104 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4105 Op = MachineOperand::CreateFI(FI);
4107 if (!Op && N.getNode()) {
4109 if (N.getOpcode() == ISD::CopyFromReg)
4110 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4112 Reg = getTruncatedArgReg(N);
4113 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4114 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4115 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4120 Op = MachineOperand::CreateReg(Reg, false);
4124 // Check if ValueMap has reg number.
4125 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4126 if (VMI != FuncInfo.ValueMap.end())
4127 Op = MachineOperand::CreateReg(VMI->second, false);
4130 if (!Op && N.getNode())
4131 // Check if frame index is available.
4132 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4133 if (FrameIndexSDNode *FINode =
4134 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4135 Op = MachineOperand::CreateFI(FINode->getIndex());
4140 assert(Variable->isValidLocationForIntrinsic(DL) &&
4141 "Expected inlined-at fields to agree");
4143 FuncInfo.ArgDbgValues.push_back(
4144 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4145 Op->getReg(), Offset, Variable, Expr));
4147 FuncInfo.ArgDbgValues.push_back(
4148 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4151 .addMetadata(Variable)
4152 .addMetadata(Expr));
4157 // VisualStudio defines setjmp as _setjmp
4158 #if defined(_MSC_VER) && defined(setjmp) && \
4159 !defined(setjmp_undefined_for_msvc)
4160 # pragma push_macro("setjmp")
4162 # define setjmp_undefined_for_msvc
4165 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4166 /// we want to emit this as a call to a named external function, return the name
4167 /// otherwise lower it and return null.
4169 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4171 SDLoc sdl = getCurSDLoc();
4172 DebugLoc dl = getCurDebugLoc();
4175 switch (Intrinsic) {
4177 // By default, turn this into a target intrinsic node.
4178 visitTargetIntrinsic(I, Intrinsic);
4180 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4181 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4182 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4183 case Intrinsic::returnaddress:
4184 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4185 TLI.getPointerTy(DAG.getDataLayout()),
4186 getValue(I.getArgOperand(0))));
4188 case Intrinsic::frameaddress:
4189 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4190 TLI.getPointerTy(DAG.getDataLayout()),
4191 getValue(I.getArgOperand(0))));
4193 case Intrinsic::read_register: {
4194 Value *Reg = I.getArgOperand(0);
4195 SDValue Chain = getRoot();
4197 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4198 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4199 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4200 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4202 DAG.setRoot(Res.getValue(1));
4205 case Intrinsic::write_register: {
4206 Value *Reg = I.getArgOperand(0);
4207 Value *RegValue = I.getArgOperand(1);
4208 SDValue Chain = getRoot();
4210 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4211 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4212 RegName, getValue(RegValue)));
4215 case Intrinsic::setjmp:
4216 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4217 case Intrinsic::longjmp:
4218 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4219 case Intrinsic::memcpy: {
4220 // FIXME: this definition of "user defined address space" is x86-specific
4221 // Assert for address < 256 since we support only user defined address
4223 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4225 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4227 "Unknown address space");
4228 SDValue Op1 = getValue(I.getArgOperand(0));
4229 SDValue Op2 = getValue(I.getArgOperand(1));
4230 SDValue Op3 = getValue(I.getArgOperand(2));
4231 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4233 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4234 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4235 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4236 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4238 MachinePointerInfo(I.getArgOperand(0)),
4239 MachinePointerInfo(I.getArgOperand(1)));
4240 updateDAGForMaybeTailCall(MC);
4243 case Intrinsic::memset: {
4244 // FIXME: this definition of "user defined address space" is x86-specific
4245 // Assert for address < 256 since we support only user defined address
4247 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4249 "Unknown address space");
4250 SDValue Op1 = getValue(I.getArgOperand(0));
4251 SDValue Op2 = getValue(I.getArgOperand(1));
4252 SDValue Op3 = getValue(I.getArgOperand(2));
4253 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4255 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4256 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4257 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4258 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4259 isTC, MachinePointerInfo(I.getArgOperand(0)));
4260 updateDAGForMaybeTailCall(MS);
4263 case Intrinsic::memmove: {
4264 // FIXME: this definition of "user defined address space" is x86-specific
4265 // Assert for address < 256 since we support only user defined address
4267 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4269 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4271 "Unknown address space");
4272 SDValue Op1 = getValue(I.getArgOperand(0));
4273 SDValue Op2 = getValue(I.getArgOperand(1));
4274 SDValue Op3 = getValue(I.getArgOperand(2));
4275 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4277 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4278 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4279 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4280 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4281 isTC, MachinePointerInfo(I.getArgOperand(0)),
4282 MachinePointerInfo(I.getArgOperand(1)));
4283 updateDAGForMaybeTailCall(MM);
4286 case Intrinsic::dbg_declare: {
4287 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4288 DILocalVariable *Variable = DI.getVariable();
4289 DIExpression *Expression = DI.getExpression();
4290 const Value *Address = DI.getAddress();
4291 assert(Variable && "Missing variable");
4293 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4297 // Check if address has undef value.
4298 if (isa<UndefValue>(Address) ||
4299 (Address->use_empty() && !isa<Argument>(Address))) {
4300 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4304 SDValue &N = NodeMap[Address];
4305 if (!N.getNode() && isa<Argument>(Address))
4306 // Check unused arguments map.
4307 N = UnusedArgNodeMap[Address];
4310 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4311 Address = BCI->getOperand(0);
4312 // Parameters are handled specially.
4313 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4315 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4317 if (isParameter && !AI) {
4318 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4320 // Byval parameter. We have a frame index at this point.
4321 SDV = DAG.getFrameIndexDbgValue(
4322 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4324 // Address is an argument, so try to emit its dbg value using
4325 // virtual register info from the FuncInfo.ValueMap.
4326 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4331 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4332 true, 0, dl, SDNodeOrder);
4334 // Can't do anything with other non-AI cases yet.
4335 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4336 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4337 DEBUG(Address->dump());
4340 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4342 // If Address is an argument then try to emit its dbg value using
4343 // virtual register info from the FuncInfo.ValueMap.
4344 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4346 // If variable is pinned by a alloca in dominating bb then
4347 // use StaticAllocaMap.
4348 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4349 if (AI->getParent() != DI.getParent()) {
4350 DenseMap<const AllocaInst*, int>::iterator SI =
4351 FuncInfo.StaticAllocaMap.find(AI);
4352 if (SI != FuncInfo.StaticAllocaMap.end()) {
4353 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4354 0, dl, SDNodeOrder);
4355 DAG.AddDbgValue(SDV, nullptr, false);
4360 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4365 case Intrinsic::dbg_value: {
4366 const DbgValueInst &DI = cast<DbgValueInst>(I);
4367 assert(DI.getVariable() && "Missing variable");
4369 DILocalVariable *Variable = DI.getVariable();
4370 DIExpression *Expression = DI.getExpression();
4371 uint64_t Offset = DI.getOffset();
4372 const Value *V = DI.getValue();
4377 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4378 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4380 DAG.AddDbgValue(SDV, nullptr, false);
4382 // Do not use getValue() in here; we don't want to generate code at
4383 // this point if it hasn't been done yet.
4384 SDValue N = NodeMap[V];
4385 if (!N.getNode() && isa<Argument>(V))
4386 // Check unused arguments map.
4387 N = UnusedArgNodeMap[V];
4389 // A dbg.value for an alloca is always indirect.
4390 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4391 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4393 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4394 IsIndirect, Offset, dl, SDNodeOrder);
4395 DAG.AddDbgValue(SDV, N.getNode(), false);
4397 } else if (!V->use_empty() ) {
4398 // Do not call getValue(V) yet, as we don't want to generate code.
4399 // Remember it for later.
4400 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4401 DanglingDebugInfoMap[V] = DDI;
4403 // We may expand this to cover more cases. One case where we have no
4404 // data available is an unreferenced parameter.
4405 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4409 // Build a debug info table entry.
4410 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4411 V = BCI->getOperand(0);
4412 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4413 // Don't handle byval struct arguments or VLAs, for example.
4415 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4416 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4419 DenseMap<const AllocaInst*, int>::iterator SI =
4420 FuncInfo.StaticAllocaMap.find(AI);
4421 if (SI == FuncInfo.StaticAllocaMap.end())
4422 return nullptr; // VLAs.
4426 case Intrinsic::eh_typeid_for: {
4427 // Find the type id for the given typeinfo.
4428 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4429 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4430 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4435 case Intrinsic::eh_return_i32:
4436 case Intrinsic::eh_return_i64:
4437 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4438 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4441 getValue(I.getArgOperand(0)),
4442 getValue(I.getArgOperand(1))));
4444 case Intrinsic::eh_unwind_init:
4445 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4447 case Intrinsic::eh_dwarf_cfa: {
4448 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4449 TLI.getPointerTy(DAG.getDataLayout()));
4450 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4451 CfaArg.getValueType(),
4452 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4453 CfaArg.getValueType()),
4455 SDValue FA = DAG.getNode(
4456 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4457 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4458 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4462 case Intrinsic::eh_sjlj_callsite: {
4463 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4464 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4465 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4466 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4468 MMI.setCurrentCallSite(CI->getZExtValue());
4471 case Intrinsic::eh_sjlj_functioncontext: {
4472 // Get and store the index of the function context.
4473 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4475 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4476 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4477 MFI->setFunctionContextIndex(FI);
4480 case Intrinsic::eh_sjlj_setjmp: {
4483 Ops[1] = getValue(I.getArgOperand(0));
4484 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4485 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4486 setValue(&I, Op.getValue(0));
4487 DAG.setRoot(Op.getValue(1));
4490 case Intrinsic::eh_sjlj_longjmp: {
4491 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4492 getRoot(), getValue(I.getArgOperand(0))));
4495 case Intrinsic::eh_sjlj_setup_dispatch: {
4496 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4501 case Intrinsic::masked_gather:
4502 visitMaskedGather(I);
4504 case Intrinsic::masked_load:
4507 case Intrinsic::masked_scatter:
4508 visitMaskedScatter(I);
4510 case Intrinsic::masked_store:
4511 visitMaskedStore(I);
4513 case Intrinsic::x86_mmx_pslli_w:
4514 case Intrinsic::x86_mmx_pslli_d:
4515 case Intrinsic::x86_mmx_pslli_q:
4516 case Intrinsic::x86_mmx_psrli_w:
4517 case Intrinsic::x86_mmx_psrli_d:
4518 case Intrinsic::x86_mmx_psrli_q:
4519 case Intrinsic::x86_mmx_psrai_w:
4520 case Intrinsic::x86_mmx_psrai_d: {
4521 SDValue ShAmt = getValue(I.getArgOperand(1));
4522 if (isa<ConstantSDNode>(ShAmt)) {
4523 visitTargetIntrinsic(I, Intrinsic);
4526 unsigned NewIntrinsic = 0;
4527 EVT ShAmtVT = MVT::v2i32;
4528 switch (Intrinsic) {
4529 case Intrinsic::x86_mmx_pslli_w:
4530 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4532 case Intrinsic::x86_mmx_pslli_d:
4533 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4535 case Intrinsic::x86_mmx_pslli_q:
4536 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4538 case Intrinsic::x86_mmx_psrli_w:
4539 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4541 case Intrinsic::x86_mmx_psrli_d:
4542 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4544 case Intrinsic::x86_mmx_psrli_q:
4545 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4547 case Intrinsic::x86_mmx_psrai_w:
4548 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4550 case Intrinsic::x86_mmx_psrai_d:
4551 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4553 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4556 // The vector shift intrinsics with scalars uses 32b shift amounts but
4557 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4559 // We must do this early because v2i32 is not a legal type.
4562 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4563 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4564 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4565 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4566 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4567 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4568 getValue(I.getArgOperand(0)), ShAmt);
4572 case Intrinsic::convertff:
4573 case Intrinsic::convertfsi:
4574 case Intrinsic::convertfui:
4575 case Intrinsic::convertsif:
4576 case Intrinsic::convertuif:
4577 case Intrinsic::convertss:
4578 case Intrinsic::convertsu:
4579 case Intrinsic::convertus:
4580 case Intrinsic::convertuu: {
4581 ISD::CvtCode Code = ISD::CVT_INVALID;
4582 switch (Intrinsic) {
4583 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4584 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4585 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4586 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4587 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4588 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4589 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4590 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4591 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4592 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4594 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4595 const Value *Op1 = I.getArgOperand(0);
4596 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4597 DAG.getValueType(DestVT),
4598 DAG.getValueType(getValue(Op1).getValueType()),
4599 getValue(I.getArgOperand(1)),
4600 getValue(I.getArgOperand(2)),
4605 case Intrinsic::powi:
4606 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4607 getValue(I.getArgOperand(1)), DAG));
4609 case Intrinsic::log:
4610 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4612 case Intrinsic::log2:
4613 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4615 case Intrinsic::log10:
4616 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4618 case Intrinsic::exp:
4619 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4621 case Intrinsic::exp2:
4622 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4624 case Intrinsic::pow:
4625 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4626 getValue(I.getArgOperand(1)), DAG, TLI));
4628 case Intrinsic::sqrt:
4629 case Intrinsic::fabs:
4630 case Intrinsic::sin:
4631 case Intrinsic::cos:
4632 case Intrinsic::floor:
4633 case Intrinsic::ceil:
4634 case Intrinsic::trunc:
4635 case Intrinsic::rint:
4636 case Intrinsic::nearbyint:
4637 case Intrinsic::round: {
4639 switch (Intrinsic) {
4640 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4641 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4642 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4643 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4644 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4645 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4646 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4647 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4648 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4649 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4650 case Intrinsic::round: Opcode = ISD::FROUND; break;
4653 setValue(&I, DAG.getNode(Opcode, sdl,
4654 getValue(I.getArgOperand(0)).getValueType(),
4655 getValue(I.getArgOperand(0))));
4658 case Intrinsic::minnum:
4659 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4660 getValue(I.getArgOperand(0)).getValueType(),
4661 getValue(I.getArgOperand(0)),
4662 getValue(I.getArgOperand(1))));
4664 case Intrinsic::maxnum:
4665 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4666 getValue(I.getArgOperand(0)).getValueType(),
4667 getValue(I.getArgOperand(0)),
4668 getValue(I.getArgOperand(1))));
4670 case Intrinsic::copysign:
4671 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4672 getValue(I.getArgOperand(0)).getValueType(),
4673 getValue(I.getArgOperand(0)),
4674 getValue(I.getArgOperand(1))));
4676 case Intrinsic::fma:
4677 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4678 getValue(I.getArgOperand(0)).getValueType(),
4679 getValue(I.getArgOperand(0)),
4680 getValue(I.getArgOperand(1)),
4681 getValue(I.getArgOperand(2))));
4683 case Intrinsic::fmuladd: {
4684 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4685 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4686 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4687 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4688 getValue(I.getArgOperand(0)).getValueType(),
4689 getValue(I.getArgOperand(0)),
4690 getValue(I.getArgOperand(1)),
4691 getValue(I.getArgOperand(2))));
4693 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4694 getValue(I.getArgOperand(0)).getValueType(),
4695 getValue(I.getArgOperand(0)),
4696 getValue(I.getArgOperand(1)));
4697 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4698 getValue(I.getArgOperand(0)).getValueType(),
4700 getValue(I.getArgOperand(2)));
4705 case Intrinsic::convert_to_fp16:
4706 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4707 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4708 getValue(I.getArgOperand(0)),
4709 DAG.getTargetConstant(0, sdl,
4712 case Intrinsic::convert_from_fp16:
4713 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4714 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4715 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4716 getValue(I.getArgOperand(0)))));
4718 case Intrinsic::pcmarker: {
4719 SDValue Tmp = getValue(I.getArgOperand(0));
4720 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4723 case Intrinsic::readcyclecounter: {
4724 SDValue Op = getRoot();
4725 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4726 DAG.getVTList(MVT::i64, MVT::Other), Op);
4728 DAG.setRoot(Res.getValue(1));
4731 case Intrinsic::bswap:
4732 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4733 getValue(I.getArgOperand(0)).getValueType(),
4734 getValue(I.getArgOperand(0))));
4736 case Intrinsic::uabsdiff:
4737 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4738 getValue(I.getArgOperand(0)).getValueType(),
4739 getValue(I.getArgOperand(0)),
4740 getValue(I.getArgOperand(1))));
4742 case Intrinsic::sabsdiff:
4743 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4744 getValue(I.getArgOperand(0)).getValueType(),
4745 getValue(I.getArgOperand(0)),
4746 getValue(I.getArgOperand(1))));
4748 case Intrinsic::cttz: {
4749 SDValue Arg = getValue(I.getArgOperand(0));
4750 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4751 EVT Ty = Arg.getValueType();
4752 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4756 case Intrinsic::ctlz: {
4757 SDValue Arg = getValue(I.getArgOperand(0));
4758 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4759 EVT Ty = Arg.getValueType();
4760 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4764 case Intrinsic::ctpop: {
4765 SDValue Arg = getValue(I.getArgOperand(0));
4766 EVT Ty = Arg.getValueType();
4767 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4770 case Intrinsic::stacksave: {
4771 SDValue Op = getRoot();
4773 ISD::STACKSAVE, sdl,
4774 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4776 DAG.setRoot(Res.getValue(1));
4779 case Intrinsic::stackrestore: {
4780 Res = getValue(I.getArgOperand(0));
4781 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4784 case Intrinsic::stackprotector: {
4785 // Emit code into the DAG to store the stack guard onto the stack.
4786 MachineFunction &MF = DAG.getMachineFunction();
4787 MachineFrameInfo *MFI = MF.getFrameInfo();
4788 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4789 SDValue Src, Chain = getRoot();
4790 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4791 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4793 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4794 // global variable __stack_chk_guard.
4796 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4797 if (BC->getOpcode() == Instruction::BitCast)
4798 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4800 if (GV && TLI.useLoadStackGuardNode()) {
4801 // Emit a LOAD_STACK_GUARD node.
4802 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4804 MachinePointerInfo MPInfo(GV);
4805 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4806 unsigned Flags = MachineMemOperand::MOLoad |
4807 MachineMemOperand::MOInvariant;
4808 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4809 PtrTy.getSizeInBits() / 8,
4810 DAG.getEVTAlignment(PtrTy));
4811 Node->setMemRefs(MemRefs, MemRefs + 1);
4813 // Copy the guard value to a virtual register so that it can be
4814 // retrieved in the epilogue.
4815 Src = SDValue(Node, 0);
4816 const TargetRegisterClass *RC =
4817 TLI.getRegClassFor(Src.getSimpleValueType());
4818 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4820 SPDescriptor.setGuardReg(Reg);
4821 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4823 Src = getValue(I.getArgOperand(0)); // The guard's value.
4826 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4828 int FI = FuncInfo.StaticAllocaMap[Slot];
4829 MFI->setStackProtectorIndex(FI);
4831 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4833 // Store the stack protector onto the stack.
4834 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4835 DAG.getMachineFunction(), FI),
4841 case Intrinsic::objectsize: {
4842 // If we don't know by now, we're never going to know.
4843 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4845 assert(CI && "Non-constant type in __builtin_object_size?");
4847 SDValue Arg = getValue(I.getCalledValue());
4848 EVT Ty = Arg.getValueType();
4851 Res = DAG.getConstant(-1ULL, sdl, Ty);
4853 Res = DAG.getConstant(0, sdl, Ty);
4858 case Intrinsic::annotation:
4859 case Intrinsic::ptr_annotation:
4860 // Drop the intrinsic, but forward the value
4861 setValue(&I, getValue(I.getOperand(0)));
4863 case Intrinsic::assume:
4864 case Intrinsic::var_annotation:
4865 // Discard annotate attributes and assumptions
4868 case Intrinsic::init_trampoline: {
4869 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4873 Ops[1] = getValue(I.getArgOperand(0));
4874 Ops[2] = getValue(I.getArgOperand(1));
4875 Ops[3] = getValue(I.getArgOperand(2));
4876 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4877 Ops[5] = DAG.getSrcValue(F);
4879 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4884 case Intrinsic::adjust_trampoline: {
4885 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4886 TLI.getPointerTy(DAG.getDataLayout()),
4887 getValue(I.getArgOperand(0))));
4890 case Intrinsic::gcroot:
4892 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4893 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4895 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4896 GFI->addStackRoot(FI->getIndex(), TypeMap);
4899 case Intrinsic::gcread:
4900 case Intrinsic::gcwrite:
4901 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4902 case Intrinsic::flt_rounds:
4903 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4906 case Intrinsic::expect: {
4907 // Just replace __builtin_expect(exp, c) with EXP.
4908 setValue(&I, getValue(I.getArgOperand(0)));
4912 case Intrinsic::debugtrap:
4913 case Intrinsic::trap: {
4914 StringRef TrapFuncName =
4916 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4917 .getValueAsString();
4918 if (TrapFuncName.empty()) {
4919 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4920 ISD::TRAP : ISD::DEBUGTRAP;
4921 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4924 TargetLowering::ArgListTy Args;
4926 TargetLowering::CallLoweringInfo CLI(DAG);
4927 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4928 CallingConv::C, I.getType(),
4929 DAG.getExternalSymbol(TrapFuncName.data(),
4930 TLI.getPointerTy(DAG.getDataLayout())),
4931 std::move(Args), 0);
4933 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4934 DAG.setRoot(Result.second);
4938 case Intrinsic::uadd_with_overflow:
4939 case Intrinsic::sadd_with_overflow:
4940 case Intrinsic::usub_with_overflow:
4941 case Intrinsic::ssub_with_overflow:
4942 case Intrinsic::umul_with_overflow:
4943 case Intrinsic::smul_with_overflow: {
4945 switch (Intrinsic) {
4946 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4947 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4948 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4949 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4950 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4951 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4952 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4954 SDValue Op1 = getValue(I.getArgOperand(0));
4955 SDValue Op2 = getValue(I.getArgOperand(1));
4957 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4958 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4961 case Intrinsic::prefetch: {
4963 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4965 Ops[1] = getValue(I.getArgOperand(0));
4966 Ops[2] = getValue(I.getArgOperand(1));
4967 Ops[3] = getValue(I.getArgOperand(2));
4968 Ops[4] = getValue(I.getArgOperand(3));
4969 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4970 DAG.getVTList(MVT::Other), Ops,
4971 EVT::getIntegerVT(*Context, 8),
4972 MachinePointerInfo(I.getArgOperand(0)),
4974 false, /* volatile */
4976 rw==1)); /* write */
4979 case Intrinsic::lifetime_start:
4980 case Intrinsic::lifetime_end: {
4981 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4982 // Stack coloring is not enabled in O0, discard region information.
4983 if (TM.getOptLevel() == CodeGenOpt::None)
4986 SmallVector<Value *, 4> Allocas;
4987 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4989 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4990 E = Allocas.end(); Object != E; ++Object) {
4991 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4993 // Could not find an Alloca.
4994 if (!LifetimeObject)
4997 // First check that the Alloca is static, otherwise it won't have a
4998 // valid frame index.
4999 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5000 if (SI == FuncInfo.StaticAllocaMap.end())
5003 int FI = SI->second;
5008 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5009 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5011 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5016 case Intrinsic::invariant_start:
5017 // Discard region information.
5018 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5020 case Intrinsic::invariant_end:
5021 // Discard region information.
5023 case Intrinsic::stackprotectorcheck: {
5024 // Do not actually emit anything for this basic block. Instead we initialize
5025 // the stack protector descriptor and export the guard variable so we can
5026 // access it in FinishBasicBlock.
5027 const BasicBlock *BB = I.getParent();
5028 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5029 ExportFromCurrentBlock(SPDescriptor.getGuard());
5031 // Flush our exports since we are going to process a terminator.
5032 (void)getControlRoot();
5035 case Intrinsic::clear_cache:
5036 return TLI.getClearCacheBuiltinName();
5037 case Intrinsic::eh_actions:
5038 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5040 case Intrinsic::donothing:
5043 case Intrinsic::experimental_stackmap: {
5047 case Intrinsic::experimental_patchpoint_void:
5048 case Intrinsic::experimental_patchpoint_i64: {
5049 visitPatchpoint(&I);
5052 case Intrinsic::experimental_gc_statepoint: {
5056 case Intrinsic::experimental_gc_result_int:
5057 case Intrinsic::experimental_gc_result_float:
5058 case Intrinsic::experimental_gc_result_ptr:
5059 case Intrinsic::experimental_gc_result: {
5063 case Intrinsic::experimental_gc_relocate: {
5067 case Intrinsic::instrprof_increment:
5068 llvm_unreachable("instrprof failed to lower an increment");
5070 case Intrinsic::localescape: {
5071 MachineFunction &MF = DAG.getMachineFunction();
5072 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5074 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5075 // is the same on all targets.
5076 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5077 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5078 if (isa<ConstantPointerNull>(Arg))
5079 continue; // Skip null pointers. They represent a hole in index space.
5080 AllocaInst *Slot = cast<AllocaInst>(Arg);
5081 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5082 "can only escape static allocas");
5083 int FI = FuncInfo.StaticAllocaMap[Slot];
5084 MCSymbol *FrameAllocSym =
5085 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5086 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5087 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5088 TII->get(TargetOpcode::LOCAL_ESCAPE))
5089 .addSym(FrameAllocSym)
5096 case Intrinsic::localrecover: {
5097 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5098 MachineFunction &MF = DAG.getMachineFunction();
5099 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5101 // Get the symbol that defines the frame offset.
5102 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5103 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5104 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5105 MCSymbol *FrameAllocSym =
5106 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5107 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5109 // Create a MCSymbol for the label to avoid any target lowering
5110 // that would make this PC relative.
5111 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5113 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5115 // Add the offset to the FP.
5116 Value *FP = I.getArgOperand(1);
5117 SDValue FPVal = getValue(FP);
5118 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5123 case Intrinsic::eh_begincatch:
5124 case Intrinsic::eh_endcatch:
5125 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5126 case Intrinsic::eh_exceptioncode: {
5127 unsigned Reg = TLI.getExceptionPointerRegister();
5128 assert(Reg && "cannot get exception code on this platform");
5129 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5130 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5131 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5132 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5134 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5135 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5142 std::pair<SDValue, SDValue>
5143 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5144 MachineBasicBlock *LandingPad) {
5145 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5146 MCSymbol *BeginLabel = nullptr;
5149 // Insert a label before the invoke call to mark the try range. This can be
5150 // used to detect deletion of the invoke via the MachineModuleInfo.
5151 BeginLabel = MMI.getContext().createTempSymbol();
5153 // For SjLj, keep track of which landing pads go with which invokes
5154 // so as to maintain the ordering of pads in the LSDA.
5155 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5156 if (CallSiteIndex) {
5157 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5158 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5160 // Now that the call site is handled, stop tracking it.
5161 MMI.setCurrentCallSite(0);
5164 // Both PendingLoads and PendingExports must be flushed here;
5165 // this call might not return.
5167 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5169 CLI.setChain(getRoot());
5171 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5172 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5174 assert((CLI.IsTailCall || Result.second.getNode()) &&
5175 "Non-null chain expected with non-tail call!");
5176 assert((Result.second.getNode() || !Result.first.getNode()) &&
5177 "Null value expected with tail call!");
5179 if (!Result.second.getNode()) {
5180 // As a special case, a null chain means that a tail call has been emitted
5181 // and the DAG root is already updated.
5184 // Since there's no actual continuation from this block, nothing can be
5185 // relying on us setting vregs for them.
5186 PendingExports.clear();
5188 DAG.setRoot(Result.second);
5192 // Insert a label at the end of the invoke call to mark the try range. This
5193 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5194 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5195 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5197 // Inform MachineModuleInfo of range.
5198 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5204 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5206 MachineBasicBlock *LandingPad) {
5207 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5208 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5209 Type *RetTy = FTy->getReturnType();
5211 TargetLowering::ArgListTy Args;
5212 TargetLowering::ArgListEntry Entry;
5213 Args.reserve(CS.arg_size());
5215 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5217 const Value *V = *i;
5220 if (V->getType()->isEmptyTy())
5223 SDValue ArgNode = getValue(V);
5224 Entry.Node = ArgNode; Entry.Ty = V->getType();
5226 // Skip the first return-type Attribute to get to params.
5227 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5228 Args.push_back(Entry);
5230 // If we have an explicit sret argument that is an Instruction, (i.e., it
5231 // might point to function-local memory), we can't meaningfully tail-call.
5232 if (Entry.isSRet && isa<Instruction>(V))
5236 // Check if target-independent constraints permit a tail call here.
5237 // Target-dependent constraints are checked within TLI->LowerCallTo.
5238 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5241 TargetLowering::CallLoweringInfo CLI(DAG);
5242 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5243 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5244 .setTailCall(isTailCall);
5245 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5247 if (Result.first.getNode())
5248 setValue(CS.getInstruction(), Result.first);
5251 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5252 /// value is equal or not-equal to zero.
5253 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5254 for (const User *U : V->users()) {
5255 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5256 if (IC->isEquality())
5257 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5258 if (C->isNullValue())
5260 // Unknown instruction.
5266 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5268 SelectionDAGBuilder &Builder) {
5270 // Check to see if this load can be trivially constant folded, e.g. if the
5271 // input is from a string literal.
5272 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5273 // Cast pointer to the type we really want to load.
5274 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5275 PointerType::getUnqual(LoadTy));
5277 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5278 const_cast<Constant *>(LoadInput), *Builder.DL))
5279 return Builder.getValue(LoadCst);
5282 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5283 // still constant memory, the input chain can be the entry node.
5285 bool ConstantMemory = false;
5287 // Do not serialize (non-volatile) loads of constant memory with anything.
5288 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5289 Root = Builder.DAG.getEntryNode();
5290 ConstantMemory = true;
5292 // Do not serialize non-volatile loads against each other.
5293 Root = Builder.DAG.getRoot();
5296 SDValue Ptr = Builder.getValue(PtrVal);
5297 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5298 Ptr, MachinePointerInfo(PtrVal),
5300 false /*nontemporal*/,
5301 false /*isinvariant*/, 1 /* align=1 */);
5303 if (!ConstantMemory)
5304 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5308 /// processIntegerCallValue - Record the value for an instruction that
5309 /// produces an integer result, converting the type where necessary.
5310 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5313 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5316 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5318 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5319 setValue(&I, Value);
5322 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5323 /// If so, return true and lower it, otherwise return false and it will be
5324 /// lowered like a normal call.
5325 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5326 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5327 if (I.getNumArgOperands() != 3)
5330 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5331 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5332 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5333 !I.getType()->isIntegerTy())
5336 const Value *Size = I.getArgOperand(2);
5337 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5338 if (CSize && CSize->getZExtValue() == 0) {
5339 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5341 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5345 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5346 std::pair<SDValue, SDValue> Res =
5347 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5348 getValue(LHS), getValue(RHS), getValue(Size),
5349 MachinePointerInfo(LHS),
5350 MachinePointerInfo(RHS));
5351 if (Res.first.getNode()) {
5352 processIntegerCallValue(I, Res.first, true);
5353 PendingLoads.push_back(Res.second);
5357 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5358 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5359 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5360 bool ActuallyDoIt = true;
5363 switch (CSize->getZExtValue()) {
5365 LoadVT = MVT::Other;
5367 ActuallyDoIt = false;
5371 LoadTy = Type::getInt16Ty(CSize->getContext());
5375 LoadTy = Type::getInt32Ty(CSize->getContext());
5379 LoadTy = Type::getInt64Ty(CSize->getContext());
5383 LoadVT = MVT::v4i32;
5384 LoadTy = Type::getInt32Ty(CSize->getContext());
5385 LoadTy = VectorType::get(LoadTy, 4);
5390 // This turns into unaligned loads. We only do this if the target natively
5391 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5392 // we'll only produce a small number of byte loads.
5394 // Require that we can find a legal MVT, and only do this if the target
5395 // supports unaligned loads of that type. Expanding into byte loads would
5397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5398 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5399 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5400 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5401 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5402 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5403 // TODO: Check alignment of src and dest ptrs.
5404 if (!TLI.isTypeLegal(LoadVT) ||
5405 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5406 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5407 ActuallyDoIt = false;
5411 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5412 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5414 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5416 processIntegerCallValue(I, Res, false);
5425 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5426 /// form. If so, return true and lower it, otherwise return false and it
5427 /// will be lowered like a normal call.
5428 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5429 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5430 if (I.getNumArgOperands() != 3)
5433 const Value *Src = I.getArgOperand(0);
5434 const Value *Char = I.getArgOperand(1);
5435 const Value *Length = I.getArgOperand(2);
5436 if (!Src->getType()->isPointerTy() ||
5437 !Char->getType()->isIntegerTy() ||
5438 !Length->getType()->isIntegerTy() ||
5439 !I.getType()->isPointerTy())
5442 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5443 std::pair<SDValue, SDValue> Res =
5444 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5445 getValue(Src), getValue(Char), getValue(Length),
5446 MachinePointerInfo(Src));
5447 if (Res.first.getNode()) {
5448 setValue(&I, Res.first);
5449 PendingLoads.push_back(Res.second);
5456 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5457 /// optimized form. If so, return true and lower it, otherwise return false
5458 /// and it will be lowered like a normal call.
5459 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5460 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5461 if (I.getNumArgOperands() != 2)
5464 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5465 if (!Arg0->getType()->isPointerTy() ||
5466 !Arg1->getType()->isPointerTy() ||
5467 !I.getType()->isPointerTy())
5470 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5471 std::pair<SDValue, SDValue> Res =
5472 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5473 getValue(Arg0), getValue(Arg1),
5474 MachinePointerInfo(Arg0),
5475 MachinePointerInfo(Arg1), isStpcpy);
5476 if (Res.first.getNode()) {
5477 setValue(&I, Res.first);
5478 DAG.setRoot(Res.second);
5485 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5486 /// If so, return true and lower it, otherwise return false and it will be
5487 /// lowered like a normal call.
5488 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5489 // Verify that the prototype makes sense. int strcmp(void*,void*)
5490 if (I.getNumArgOperands() != 2)
5493 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5494 if (!Arg0->getType()->isPointerTy() ||
5495 !Arg1->getType()->isPointerTy() ||
5496 !I.getType()->isIntegerTy())
5499 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5500 std::pair<SDValue, SDValue> Res =
5501 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5502 getValue(Arg0), getValue(Arg1),
5503 MachinePointerInfo(Arg0),
5504 MachinePointerInfo(Arg1));
5505 if (Res.first.getNode()) {
5506 processIntegerCallValue(I, Res.first, true);
5507 PendingLoads.push_back(Res.second);
5514 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5515 /// form. If so, return true and lower it, otherwise return false and it
5516 /// will be lowered like a normal call.
5517 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5518 // Verify that the prototype makes sense. size_t strlen(char *)
5519 if (I.getNumArgOperands() != 1)
5522 const Value *Arg0 = I.getArgOperand(0);
5523 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5526 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5527 std::pair<SDValue, SDValue> Res =
5528 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5529 getValue(Arg0), MachinePointerInfo(Arg0));
5530 if (Res.first.getNode()) {
5531 processIntegerCallValue(I, Res.first, false);
5532 PendingLoads.push_back(Res.second);
5539 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5540 /// form. If so, return true and lower it, otherwise return false and it
5541 /// will be lowered like a normal call.
5542 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5543 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5544 if (I.getNumArgOperands() != 2)
5547 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5548 if (!Arg0->getType()->isPointerTy() ||
5549 !Arg1->getType()->isIntegerTy() ||
5550 !I.getType()->isIntegerTy())
5553 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5554 std::pair<SDValue, SDValue> Res =
5555 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5556 getValue(Arg0), getValue(Arg1),
5557 MachinePointerInfo(Arg0));
5558 if (Res.first.getNode()) {
5559 processIntegerCallValue(I, Res.first, false);
5560 PendingLoads.push_back(Res.second);
5567 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5568 /// operation (as expected), translate it to an SDNode with the specified opcode
5569 /// and return true.
5570 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5572 // Sanity check that it really is a unary floating-point call.
5573 if (I.getNumArgOperands() != 1 ||
5574 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5575 I.getType() != I.getArgOperand(0)->getType() ||
5576 !I.onlyReadsMemory())
5579 SDValue Tmp = getValue(I.getArgOperand(0));
5580 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5584 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5585 /// operation (as expected), translate it to an SDNode with the specified opcode
5586 /// and return true.
5587 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5589 // Sanity check that it really is a binary floating-point call.
5590 if (I.getNumArgOperands() != 2 ||
5591 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5592 I.getType() != I.getArgOperand(0)->getType() ||
5593 I.getType() != I.getArgOperand(1)->getType() ||
5594 !I.onlyReadsMemory())
5597 SDValue Tmp0 = getValue(I.getArgOperand(0));
5598 SDValue Tmp1 = getValue(I.getArgOperand(1));
5599 EVT VT = Tmp0.getValueType();
5600 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5604 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5605 // Handle inline assembly differently.
5606 if (isa<InlineAsm>(I.getCalledValue())) {
5611 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5612 ComputeUsesVAFloatArgument(I, &MMI);
5614 const char *RenameFn = nullptr;
5615 if (Function *F = I.getCalledFunction()) {
5616 if (F->isDeclaration()) {
5617 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5618 if (unsigned IID = II->getIntrinsicID(F)) {
5619 RenameFn = visitIntrinsicCall(I, IID);
5624 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5625 RenameFn = visitIntrinsicCall(I, IID);
5631 // Check for well-known libc/libm calls. If the function is internal, it
5632 // can't be a library call.
5634 if (!F->hasLocalLinkage() && F->hasName() &&
5635 LibInfo->getLibFunc(F->getName(), Func) &&
5636 LibInfo->hasOptimizedCodeGen(Func)) {
5639 case LibFunc::copysign:
5640 case LibFunc::copysignf:
5641 case LibFunc::copysignl:
5642 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5643 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5644 I.getType() == I.getArgOperand(0)->getType() &&
5645 I.getType() == I.getArgOperand(1)->getType() &&
5646 I.onlyReadsMemory()) {
5647 SDValue LHS = getValue(I.getArgOperand(0));
5648 SDValue RHS = getValue(I.getArgOperand(1));
5649 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5650 LHS.getValueType(), LHS, RHS));
5655 case LibFunc::fabsf:
5656 case LibFunc::fabsl:
5657 if (visitUnaryFloatCall(I, ISD::FABS))
5661 case LibFunc::fminf:
5662 case LibFunc::fminl:
5663 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5667 case LibFunc::fmaxf:
5668 case LibFunc::fmaxl:
5669 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5675 if (visitUnaryFloatCall(I, ISD::FSIN))
5681 if (visitUnaryFloatCall(I, ISD::FCOS))
5685 case LibFunc::sqrtf:
5686 case LibFunc::sqrtl:
5687 case LibFunc::sqrt_finite:
5688 case LibFunc::sqrtf_finite:
5689 case LibFunc::sqrtl_finite:
5690 if (visitUnaryFloatCall(I, ISD::FSQRT))
5693 case LibFunc::floor:
5694 case LibFunc::floorf:
5695 case LibFunc::floorl:
5696 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5699 case LibFunc::nearbyint:
5700 case LibFunc::nearbyintf:
5701 case LibFunc::nearbyintl:
5702 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5706 case LibFunc::ceilf:
5707 case LibFunc::ceill:
5708 if (visitUnaryFloatCall(I, ISD::FCEIL))
5712 case LibFunc::rintf:
5713 case LibFunc::rintl:
5714 if (visitUnaryFloatCall(I, ISD::FRINT))
5717 case LibFunc::round:
5718 case LibFunc::roundf:
5719 case LibFunc::roundl:
5720 if (visitUnaryFloatCall(I, ISD::FROUND))
5723 case LibFunc::trunc:
5724 case LibFunc::truncf:
5725 case LibFunc::truncl:
5726 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5730 case LibFunc::log2f:
5731 case LibFunc::log2l:
5732 if (visitUnaryFloatCall(I, ISD::FLOG2))
5736 case LibFunc::exp2f:
5737 case LibFunc::exp2l:
5738 if (visitUnaryFloatCall(I, ISD::FEXP2))
5741 case LibFunc::memcmp:
5742 if (visitMemCmpCall(I))
5745 case LibFunc::memchr:
5746 if (visitMemChrCall(I))
5749 case LibFunc::strcpy:
5750 if (visitStrCpyCall(I, false))
5753 case LibFunc::stpcpy:
5754 if (visitStrCpyCall(I, true))
5757 case LibFunc::strcmp:
5758 if (visitStrCmpCall(I))
5761 case LibFunc::strlen:
5762 if (visitStrLenCall(I))
5765 case LibFunc::strnlen:
5766 if (visitStrNLenCall(I))
5775 Callee = getValue(I.getCalledValue());
5777 Callee = DAG.getExternalSymbol(
5779 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5781 // Check if we can potentially perform a tail call. More detailed checking is
5782 // be done within LowerCallTo, after more information about the call is known.
5783 LowerCallTo(&I, Callee, I.isTailCall());
5788 /// AsmOperandInfo - This contains information for each constraint that we are
5790 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5792 /// CallOperand - If this is the result output operand or a clobber
5793 /// this is null, otherwise it is the incoming operand to the CallInst.
5794 /// This gets modified as the asm is processed.
5795 SDValue CallOperand;
5797 /// AssignedRegs - If this is a register or register class operand, this
5798 /// contains the set of register corresponding to the operand.
5799 RegsForValue AssignedRegs;
5801 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5802 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5805 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5806 /// corresponds to. If there is no Value* for this operand, it returns
5808 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5809 const DataLayout &DL) const {
5810 if (!CallOperandVal) return MVT::Other;
5812 if (isa<BasicBlock>(CallOperandVal))
5813 return TLI.getPointerTy(DL);
5815 llvm::Type *OpTy = CallOperandVal->getType();
5817 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5818 // If this is an indirect operand, the operand is a pointer to the
5821 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5823 report_fatal_error("Indirect operand for inline asm not a pointer!");
5824 OpTy = PtrTy->getElementType();
5827 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5828 if (StructType *STy = dyn_cast<StructType>(OpTy))
5829 if (STy->getNumElements() == 1)
5830 OpTy = STy->getElementType(0);
5832 // If OpTy is not a single value, it may be a struct/union that we
5833 // can tile with integers.
5834 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5835 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5844 OpTy = IntegerType::get(Context, BitSize);
5849 return TLI.getValueType(DL, OpTy, true);
5853 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5855 } // end anonymous namespace
5857 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5858 /// specified operand. We prefer to assign virtual registers, to allow the
5859 /// register allocator to handle the assignment process. However, if the asm
5860 /// uses features that we can't model on machineinstrs, we have SDISel do the
5861 /// allocation. This produces generally horrible, but correct, code.
5863 /// OpInfo describes the operand.
5865 static void GetRegistersForValue(SelectionDAG &DAG,
5866 const TargetLowering &TLI,
5868 SDISelAsmOperandInfo &OpInfo) {
5869 LLVMContext &Context = *DAG.getContext();
5871 MachineFunction &MF = DAG.getMachineFunction();
5872 SmallVector<unsigned, 4> Regs;
5874 // If this is a constraint for a single physreg, or a constraint for a
5875 // register class, find it.
5876 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5877 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5878 OpInfo.ConstraintCode,
5879 OpInfo.ConstraintVT);
5881 unsigned NumRegs = 1;
5882 if (OpInfo.ConstraintVT != MVT::Other) {
5883 // If this is a FP input in an integer register (or visa versa) insert a bit
5884 // cast of the input value. More generally, handle any case where the input
5885 // value disagrees with the register class we plan to stick this in.
5886 if (OpInfo.Type == InlineAsm::isInput &&
5887 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5888 // Try to convert to the first EVT that the reg class contains. If the
5889 // types are identical size, use a bitcast to convert (e.g. two differing
5891 MVT RegVT = *PhysReg.second->vt_begin();
5892 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5893 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5894 RegVT, OpInfo.CallOperand);
5895 OpInfo.ConstraintVT = RegVT;
5896 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5897 // If the input is a FP value and we want it in FP registers, do a
5898 // bitcast to the corresponding integer type. This turns an f64 value
5899 // into i64, which can be passed with two i32 values on a 32-bit
5901 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5902 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5903 RegVT, OpInfo.CallOperand);
5904 OpInfo.ConstraintVT = RegVT;
5908 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5912 EVT ValueVT = OpInfo.ConstraintVT;
5914 // If this is a constraint for a specific physical register, like {r17},
5916 if (unsigned AssignedReg = PhysReg.first) {
5917 const TargetRegisterClass *RC = PhysReg.second;
5918 if (OpInfo.ConstraintVT == MVT::Other)
5919 ValueVT = *RC->vt_begin();
5921 // Get the actual register value type. This is important, because the user
5922 // may have asked for (e.g.) the AX register in i32 type. We need to
5923 // remember that AX is actually i16 to get the right extension.
5924 RegVT = *RC->vt_begin();
5926 // This is a explicit reference to a physical register.
5927 Regs.push_back(AssignedReg);
5929 // If this is an expanded reference, add the rest of the regs to Regs.
5931 TargetRegisterClass::iterator I = RC->begin();
5932 for (; *I != AssignedReg; ++I)
5933 assert(I != RC->end() && "Didn't find reg!");
5935 // Already added the first reg.
5937 for (; NumRegs; --NumRegs, ++I) {
5938 assert(I != RC->end() && "Ran out of registers to allocate!");
5943 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5947 // Otherwise, if this was a reference to an LLVM register class, create vregs
5948 // for this reference.
5949 if (const TargetRegisterClass *RC = PhysReg.second) {
5950 RegVT = *RC->vt_begin();
5951 if (OpInfo.ConstraintVT == MVT::Other)
5954 // Create the appropriate number of virtual registers.
5955 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5956 for (; NumRegs; --NumRegs)
5957 Regs.push_back(RegInfo.createVirtualRegister(RC));
5959 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5963 // Otherwise, we couldn't allocate enough registers for this.
5966 /// visitInlineAsm - Handle a call to an InlineAsm object.
5968 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5969 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5971 /// ConstraintOperands - Information about all of the constraints.
5972 SDISelAsmOperandInfoVector ConstraintOperands;
5974 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5975 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5976 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5978 bool hasMemory = false;
5980 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5981 unsigned ResNo = 0; // ResNo - The result number of the next output.
5982 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5983 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5984 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5986 MVT OpVT = MVT::Other;
5988 // Compute the value type for each operand.
5989 switch (OpInfo.Type) {
5990 case InlineAsm::isOutput:
5991 // Indirect outputs just consume an argument.
5992 if (OpInfo.isIndirect) {
5993 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5997 // The return value of the call is this value. As such, there is no
5998 // corresponding argument.
5999 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6000 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6001 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6002 STy->getElementType(ResNo));
6004 assert(ResNo == 0 && "Asm only has one result!");
6005 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6009 case InlineAsm::isInput:
6010 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6012 case InlineAsm::isClobber:
6017 // If this is an input or an indirect output, process the call argument.
6018 // BasicBlocks are labels, currently appearing only in asm's.
6019 if (OpInfo.CallOperandVal) {
6020 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6021 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6023 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6026 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6027 DAG.getDataLayout()).getSimpleVT();
6030 OpInfo.ConstraintVT = OpVT;
6032 // Indirect operand accesses access memory.
6033 if (OpInfo.isIndirect)
6036 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6037 TargetLowering::ConstraintType
6038 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6039 if (CType == TargetLowering::C_Memory) {
6047 SDValue Chain, Flag;
6049 // We won't need to flush pending loads if this asm doesn't touch
6050 // memory and is nonvolatile.
6051 if (hasMemory || IA->hasSideEffects())
6054 Chain = DAG.getRoot();
6056 // Second pass over the constraints: compute which constraint option to use
6057 // and assign registers to constraints that want a specific physreg.
6058 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6059 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6061 // If this is an output operand with a matching input operand, look up the
6062 // matching input. If their types mismatch, e.g. one is an integer, the
6063 // other is floating point, or their sizes are different, flag it as an
6065 if (OpInfo.hasMatchingInput()) {
6066 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6068 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6069 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6070 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6071 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6072 OpInfo.ConstraintVT);
6073 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6074 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6075 Input.ConstraintVT);
6076 if ((OpInfo.ConstraintVT.isInteger() !=
6077 Input.ConstraintVT.isInteger()) ||
6078 (MatchRC.second != InputRC.second)) {
6079 report_fatal_error("Unsupported asm: input constraint"
6080 " with a matching output constraint of"
6081 " incompatible type!");
6083 Input.ConstraintVT = OpInfo.ConstraintVT;
6087 // Compute the constraint code and ConstraintType to use.
6088 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6090 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6091 OpInfo.Type == InlineAsm::isClobber)
6094 // If this is a memory input, and if the operand is not indirect, do what we
6095 // need to to provide an address for the memory input.
6096 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6097 !OpInfo.isIndirect) {
6098 assert((OpInfo.isMultipleAlternative ||
6099 (OpInfo.Type == InlineAsm::isInput)) &&
6100 "Can only indirectify direct input operands!");
6102 // Memory operands really want the address of the value. If we don't have
6103 // an indirect input, put it in the constpool if we can, otherwise spill
6104 // it to a stack slot.
6105 // TODO: This isn't quite right. We need to handle these according to
6106 // the addressing mode that the constraint wants. Also, this may take
6107 // an additional register for the computation and we don't want that
6110 // If the operand is a float, integer, or vector constant, spill to a
6111 // constant pool entry to get its address.
6112 const Value *OpVal = OpInfo.CallOperandVal;
6113 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6114 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6115 OpInfo.CallOperand = DAG.getConstantPool(
6116 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6118 // Otherwise, create a stack slot and emit a store to it before the
6120 Type *Ty = OpVal->getType();
6121 auto &DL = DAG.getDataLayout();
6122 uint64_t TySize = DL.getTypeAllocSize(Ty);
6123 unsigned Align = DL.getPrefTypeAlignment(Ty);
6124 MachineFunction &MF = DAG.getMachineFunction();
6125 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6127 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6128 Chain = DAG.getStore(
6129 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6130 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6132 OpInfo.CallOperand = StackSlot;
6135 // There is no longer a Value* corresponding to this operand.
6136 OpInfo.CallOperandVal = nullptr;
6138 // It is now an indirect operand.
6139 OpInfo.isIndirect = true;
6142 // If this constraint is for a specific register, allocate it before
6144 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6145 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6148 // Second pass - Loop over all of the operands, assigning virtual or physregs
6149 // to register class operands.
6150 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6151 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6153 // C_Register operands have already been allocated, Other/Memory don't need
6155 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6156 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6159 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6160 std::vector<SDValue> AsmNodeOperands;
6161 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6162 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6163 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6165 // If we have a !srcloc metadata node associated with it, we want to attach
6166 // this to the ultimately generated inline asm machineinstr. To do this, we
6167 // pass in the third operand as this (potentially null) inline asm MDNode.
6168 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6169 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6171 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6172 // bits as operand 3.
6173 unsigned ExtraInfo = 0;
6174 if (IA->hasSideEffects())
6175 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6176 if (IA->isAlignStack())
6177 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6178 // Set the asm dialect.
6179 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6181 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6182 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6183 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6185 // Compute the constraint code and ConstraintType to use.
6186 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6188 // Ideally, we would only check against memory constraints. However, the
6189 // meaning of an other constraint can be target-specific and we can't easily
6190 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6191 // for other constriants as well.
6192 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6193 OpInfo.ConstraintType == TargetLowering::C_Other) {
6194 if (OpInfo.Type == InlineAsm::isInput)
6195 ExtraInfo |= InlineAsm::Extra_MayLoad;
6196 else if (OpInfo.Type == InlineAsm::isOutput)
6197 ExtraInfo |= InlineAsm::Extra_MayStore;
6198 else if (OpInfo.Type == InlineAsm::isClobber)
6199 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6203 AsmNodeOperands.push_back(DAG.getTargetConstant(
6204 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6206 // Loop over all of the inputs, copying the operand values into the
6207 // appropriate registers and processing the output regs.
6208 RegsForValue RetValRegs;
6210 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6211 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6213 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6214 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6216 switch (OpInfo.Type) {
6217 case InlineAsm::isOutput: {
6218 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6219 OpInfo.ConstraintType != TargetLowering::C_Register) {
6220 // Memory output, or 'other' output (e.g. 'X' constraint).
6221 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6223 unsigned ConstraintID =
6224 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6225 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6226 "Failed to convert memory constraint code to constraint id.");
6228 // Add information to the INLINEASM node to know about this output.
6229 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6230 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6231 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6233 AsmNodeOperands.push_back(OpInfo.CallOperand);
6237 // Otherwise, this is a register or register class output.
6239 // Copy the output from the appropriate register. Find a register that
6241 if (OpInfo.AssignedRegs.Regs.empty()) {
6242 LLVMContext &Ctx = *DAG.getContext();
6243 Ctx.emitError(CS.getInstruction(),
6244 "couldn't allocate output register for constraint '" +
6245 Twine(OpInfo.ConstraintCode) + "'");
6249 // If this is an indirect operand, store through the pointer after the
6251 if (OpInfo.isIndirect) {
6252 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6253 OpInfo.CallOperandVal));
6255 // This is the result value of the call.
6256 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6257 // Concatenate this output onto the outputs list.
6258 RetValRegs.append(OpInfo.AssignedRegs);
6261 // Add information to the INLINEASM node to know that this register is
6264 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6265 ? InlineAsm::Kind_RegDefEarlyClobber
6266 : InlineAsm::Kind_RegDef,
6267 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6270 case InlineAsm::isInput: {
6271 SDValue InOperandVal = OpInfo.CallOperand;
6273 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6274 // If this is required to match an output register we have already set,
6275 // just use its register.
6276 unsigned OperandNo = OpInfo.getMatchedOperand();
6278 // Scan until we find the definition we already emitted of this operand.
6279 // When we find it, create a RegsForValue operand.
6280 unsigned CurOp = InlineAsm::Op_FirstOperand;
6281 for (; OperandNo; --OperandNo) {
6282 // Advance to the next operand.
6284 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6285 assert((InlineAsm::isRegDefKind(OpFlag) ||
6286 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6287 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6288 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6292 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6293 if (InlineAsm::isRegDefKind(OpFlag) ||
6294 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6295 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6296 if (OpInfo.isIndirect) {
6297 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6298 LLVMContext &Ctx = *DAG.getContext();
6299 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6300 " don't know how to handle tied "
6301 "indirect register inputs");
6305 RegsForValue MatchedRegs;
6306 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6307 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6308 MatchedRegs.RegVTs.push_back(RegVT);
6309 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6310 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6312 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6313 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6315 LLVMContext &Ctx = *DAG.getContext();
6316 Ctx.emitError(CS.getInstruction(),
6317 "inline asm error: This value"
6318 " type register class is not natively supported!");
6322 SDLoc dl = getCurSDLoc();
6323 // Use the produced MatchedRegs object to
6324 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6325 Chain, &Flag, CS.getInstruction());
6326 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6327 true, OpInfo.getMatchedOperand(), dl,
6328 DAG, AsmNodeOperands);
6332 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6333 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6334 "Unexpected number of operands");
6335 // Add information to the INLINEASM node to know about this input.
6336 // See InlineAsm.h isUseOperandTiedToDef.
6337 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6338 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6339 OpInfo.getMatchedOperand());
6340 AsmNodeOperands.push_back(DAG.getTargetConstant(
6341 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6342 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6346 // Treat indirect 'X' constraint as memory.
6347 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6349 OpInfo.ConstraintType = TargetLowering::C_Memory;
6351 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6352 std::vector<SDValue> Ops;
6353 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6356 LLVMContext &Ctx = *DAG.getContext();
6357 Ctx.emitError(CS.getInstruction(),
6358 "invalid operand for inline asm constraint '" +
6359 Twine(OpInfo.ConstraintCode) + "'");
6363 // Add information to the INLINEASM node to know about this input.
6364 unsigned ResOpType =
6365 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6366 AsmNodeOperands.push_back(DAG.getTargetConstant(
6367 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6368 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6372 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6373 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6374 assert(InOperandVal.getValueType() ==
6375 TLI.getPointerTy(DAG.getDataLayout()) &&
6376 "Memory operands expect pointer values");
6378 unsigned ConstraintID =
6379 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6380 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6381 "Failed to convert memory constraint code to constraint id.");
6383 // Add information to the INLINEASM node to know about this input.
6384 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6385 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6386 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6389 AsmNodeOperands.push_back(InOperandVal);
6393 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6394 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6395 "Unknown constraint type!");
6397 // TODO: Support this.
6398 if (OpInfo.isIndirect) {
6399 LLVMContext &Ctx = *DAG.getContext();
6400 Ctx.emitError(CS.getInstruction(),
6401 "Don't know how to handle indirect register inputs yet "
6402 "for constraint '" +
6403 Twine(OpInfo.ConstraintCode) + "'");
6407 // Copy the input into the appropriate registers.
6408 if (OpInfo.AssignedRegs.Regs.empty()) {
6409 LLVMContext &Ctx = *DAG.getContext();
6410 Ctx.emitError(CS.getInstruction(),
6411 "couldn't allocate input reg for constraint '" +
6412 Twine(OpInfo.ConstraintCode) + "'");
6416 SDLoc dl = getCurSDLoc();
6418 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6419 Chain, &Flag, CS.getInstruction());
6421 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6422 dl, DAG, AsmNodeOperands);
6425 case InlineAsm::isClobber: {
6426 // Add the clobbered value to the operand list, so that the register
6427 // allocator is aware that the physreg got clobbered.
6428 if (!OpInfo.AssignedRegs.Regs.empty())
6429 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6430 false, 0, getCurSDLoc(), DAG,
6437 // Finish up input operands. Set the input chain and add the flag last.
6438 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6439 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6441 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6442 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6443 Flag = Chain.getValue(1);
6445 // If this asm returns a register value, copy the result from that register
6446 // and set it as the value of the call.
6447 if (!RetValRegs.Regs.empty()) {
6448 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6449 Chain, &Flag, CS.getInstruction());
6451 // FIXME: Why don't we do this for inline asms with MRVs?
6452 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6453 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6455 // If any of the results of the inline asm is a vector, it may have the
6456 // wrong width/num elts. This can happen for register classes that can
6457 // contain multiple different value types. The preg or vreg allocated may
6458 // not have the same VT as was expected. Convert it to the right type
6459 // with bit_convert.
6460 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6461 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6464 } else if (ResultType != Val.getValueType() &&
6465 ResultType.isInteger() && Val.getValueType().isInteger()) {
6466 // If a result value was tied to an input value, the computed result may
6467 // have a wider width than the expected result. Extract the relevant
6469 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6472 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6475 setValue(CS.getInstruction(), Val);
6476 // Don't need to use this as a chain in this case.
6477 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6481 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6483 // Process indirect outputs, first output all of the flagged copies out of
6485 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6486 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6487 const Value *Ptr = IndirectStoresToEmit[i].second;
6488 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6490 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6493 // Emit the non-flagged stores from the physregs.
6494 SmallVector<SDValue, 8> OutChains;
6495 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6496 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6497 StoresToEmit[i].first,
6498 getValue(StoresToEmit[i].second),
6499 MachinePointerInfo(StoresToEmit[i].second),
6501 OutChains.push_back(Val);
6504 if (!OutChains.empty())
6505 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6510 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6511 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6512 MVT::Other, getRoot(),
6513 getValue(I.getArgOperand(0)),
6514 DAG.getSrcValue(I.getArgOperand(0))));
6517 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6519 const DataLayout &DL = DAG.getDataLayout();
6520 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6521 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6522 DAG.getSrcValue(I.getOperand(0)),
6523 DL.getABITypeAlignment(I.getType()));
6525 DAG.setRoot(V.getValue(1));
6528 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6529 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6530 MVT::Other, getRoot(),
6531 getValue(I.getArgOperand(0)),
6532 DAG.getSrcValue(I.getArgOperand(0))));
6535 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6536 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6537 MVT::Other, getRoot(),
6538 getValue(I.getArgOperand(0)),
6539 getValue(I.getArgOperand(1)),
6540 DAG.getSrcValue(I.getArgOperand(0)),
6541 DAG.getSrcValue(I.getArgOperand(1))));
6544 /// \brief Lower an argument list according to the target calling convention.
6546 /// \return A tuple of <return-value, token-chain>
6548 /// This is a helper for lowering intrinsics that follow a target calling
6549 /// convention or require stack pointer adjustment. Only a subset of the
6550 /// intrinsic's operands need to participate in the calling convention.
6551 std::pair<SDValue, SDValue>
6552 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6553 unsigned NumArgs, SDValue Callee,
6555 MachineBasicBlock *LandingPad,
6556 bool IsPatchPoint) {
6557 TargetLowering::ArgListTy Args;
6558 Args.reserve(NumArgs);
6560 // Populate the argument list.
6561 // Attributes for args start at offset 1, after the return attribute.
6562 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6563 ArgI != ArgE; ++ArgI) {
6564 const Value *V = CS->getOperand(ArgI);
6566 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6568 TargetLowering::ArgListEntry Entry;
6569 Entry.Node = getValue(V);
6570 Entry.Ty = V->getType();
6571 Entry.setAttributes(&CS, AttrI);
6572 Args.push_back(Entry);
6575 TargetLowering::CallLoweringInfo CLI(DAG);
6576 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6577 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6578 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6580 return lowerInvokable(CLI, LandingPad);
6583 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6584 /// or patchpoint target node's operand list.
6586 /// Constants are converted to TargetConstants purely as an optimization to
6587 /// avoid constant materialization and register allocation.
6589 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6590 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6591 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6592 /// address materialization and register allocation, but may also be required
6593 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6594 /// alloca in the entry block, then the runtime may assume that the alloca's
6595 /// StackMap location can be read immediately after compilation and that the
6596 /// location is valid at any point during execution (this is similar to the
6597 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6598 /// only available in a register, then the runtime would need to trap when
6599 /// execution reaches the StackMap in order to read the alloca's location.
6600 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6601 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6602 SelectionDAGBuilder &Builder) {
6603 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6604 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6607 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6609 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6610 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6611 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6612 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6613 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6615 Ops.push_back(OpVal);
6619 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6620 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6621 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6622 // [live variables...])
6624 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6626 SDValue Chain, InFlag, Callee, NullPtr;
6627 SmallVector<SDValue, 32> Ops;
6629 SDLoc DL = getCurSDLoc();
6630 Callee = getValue(CI.getCalledValue());
6631 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6633 // The stackmap intrinsic only records the live variables (the arguemnts
6634 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6635 // intrinsic, this won't be lowered to a function call. This means we don't
6636 // have to worry about calling conventions and target specific lowering code.
6637 // Instead we perform the call lowering right here.
6639 // chain, flag = CALLSEQ_START(chain, 0)
6640 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6641 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6643 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6644 InFlag = Chain.getValue(1);
6646 // Add the <id> and <numBytes> constants.
6647 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6648 Ops.push_back(DAG.getTargetConstant(
6649 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6650 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6651 Ops.push_back(DAG.getTargetConstant(
6652 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6655 // Push live variables for the stack map.
6656 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6658 // We are not pushing any register mask info here on the operands list,
6659 // because the stackmap doesn't clobber anything.
6661 // Push the chain and the glue flag.
6662 Ops.push_back(Chain);
6663 Ops.push_back(InFlag);
6665 // Create the STACKMAP node.
6666 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6667 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6668 Chain = SDValue(SM, 0);
6669 InFlag = Chain.getValue(1);
6671 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6673 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6675 // Set the root to the target-lowered call chain.
6678 // Inform the Frame Information that we have a stackmap in this function.
6679 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6682 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6683 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6684 MachineBasicBlock *LandingPad) {
6685 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6690 // [live variables...])
6692 CallingConv::ID CC = CS.getCallingConv();
6693 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6694 bool HasDef = !CS->getType()->isVoidTy();
6695 SDLoc dl = getCurSDLoc();
6696 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6698 // Handle immediate and symbolic callees.
6699 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6700 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6702 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6703 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6704 SDLoc(SymbolicCallee),
6705 SymbolicCallee->getValueType(0));
6707 // Get the real number of arguments participating in the call <numArgs>
6708 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6709 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6711 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6712 // Intrinsics include all meta-operands up to but not including CC.
6713 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6714 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6715 "Not enough arguments provided to the patchpoint intrinsic");
6717 // For AnyRegCC the arguments are lowered later on manually.
6718 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6720 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6721 std::pair<SDValue, SDValue> Result =
6722 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6725 SDNode *CallEnd = Result.second.getNode();
6726 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6727 CallEnd = CallEnd->getOperand(0).getNode();
6729 /// Get a call instruction from the call sequence chain.
6730 /// Tail calls are not allowed.
6731 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6732 "Expected a callseq node.");
6733 SDNode *Call = CallEnd->getOperand(0).getNode();
6734 bool HasGlue = Call->getGluedNode();
6736 // Replace the target specific call node with the patchable intrinsic.
6737 SmallVector<SDValue, 8> Ops;
6739 // Add the <id> and <numBytes> constants.
6740 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6741 Ops.push_back(DAG.getTargetConstant(
6742 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6743 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6744 Ops.push_back(DAG.getTargetConstant(
6745 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6749 Ops.push_back(Callee);
6751 // Adjust <numArgs> to account for any arguments that have been passed on the
6753 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6754 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6755 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6756 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6758 // Add the calling convention
6759 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6761 // Add the arguments we omitted previously. The register allocator should
6762 // place these in any free register.
6764 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6765 Ops.push_back(getValue(CS.getArgument(i)));
6767 // Push the arguments from the call instruction up to the register mask.
6768 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6769 Ops.append(Call->op_begin() + 2, e);
6771 // Push live variables for the stack map.
6772 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6774 // Push the register mask info.
6776 Ops.push_back(*(Call->op_end()-2));
6778 Ops.push_back(*(Call->op_end()-1));
6780 // Push the chain (this is originally the first operand of the call, but
6781 // becomes now the last or second to last operand).
6782 Ops.push_back(*(Call->op_begin()));
6784 // Push the glue flag (last operand).
6786 Ops.push_back(*(Call->op_end()-1));
6789 if (IsAnyRegCC && HasDef) {
6790 // Create the return types based on the intrinsic definition
6791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6792 SmallVector<EVT, 3> ValueVTs;
6793 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6794 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6796 // There is always a chain and a glue type at the end
6797 ValueVTs.push_back(MVT::Other);
6798 ValueVTs.push_back(MVT::Glue);
6799 NodeTys = DAG.getVTList(ValueVTs);
6801 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6803 // Replace the target specific call node with a PATCHPOINT node.
6804 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6807 // Update the NodeMap.
6810 setValue(CS.getInstruction(), SDValue(MN, 0));
6812 setValue(CS.getInstruction(), Result.first);
6815 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6816 // call sequence. Furthermore the location of the chain and glue can change
6817 // when the AnyReg calling convention is used and the intrinsic returns a
6819 if (IsAnyRegCC && HasDef) {
6820 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6821 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6822 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6824 DAG.ReplaceAllUsesWith(Call, MN);
6825 DAG.DeleteNode(Call);
6827 // Inform the Frame Information that we have a patchpoint in this function.
6828 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6831 /// Returns an AttributeSet representing the attributes applied to the return
6832 /// value of the given call.
6833 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6834 SmallVector<Attribute::AttrKind, 2> Attrs;
6836 Attrs.push_back(Attribute::SExt);
6838 Attrs.push_back(Attribute::ZExt);
6840 Attrs.push_back(Attribute::InReg);
6842 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6846 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6847 /// implementation, which just calls LowerCall.
6848 /// FIXME: When all targets are
6849 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6850 std::pair<SDValue, SDValue>
6851 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6852 // Handle the incoming return values from the call.
6854 Type *OrigRetTy = CLI.RetTy;
6855 SmallVector<EVT, 4> RetTys;
6856 SmallVector<uint64_t, 4> Offsets;
6857 auto &DL = CLI.DAG.getDataLayout();
6858 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6860 SmallVector<ISD::OutputArg, 4> Outs;
6861 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6863 bool CanLowerReturn =
6864 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6865 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6867 SDValue DemoteStackSlot;
6868 int DemoteStackIdx = -100;
6869 if (!CanLowerReturn) {
6870 // FIXME: equivalent assert?
6871 // assert(!CS.hasInAllocaArgument() &&
6872 // "sret demotion is incompatible with inalloca");
6873 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6874 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6875 MachineFunction &MF = CLI.DAG.getMachineFunction();
6876 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6877 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6879 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6881 Entry.Node = DemoteStackSlot;
6882 Entry.Ty = StackSlotPtrType;
6883 Entry.isSExt = false;
6884 Entry.isZExt = false;
6885 Entry.isInReg = false;
6886 Entry.isSRet = true;
6887 Entry.isNest = false;
6888 Entry.isByVal = false;
6889 Entry.isReturned = false;
6890 Entry.Alignment = Align;
6891 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6892 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6894 // sret demotion isn't compatible with tail-calls, since the sret argument
6895 // points into the callers stack frame.
6896 CLI.IsTailCall = false;
6898 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6900 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6901 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6902 for (unsigned i = 0; i != NumRegs; ++i) {
6903 ISD::InputArg MyFlags;
6904 MyFlags.VT = RegisterVT;
6906 MyFlags.Used = CLI.IsReturnValueUsed;
6908 MyFlags.Flags.setSExt();
6910 MyFlags.Flags.setZExt();
6912 MyFlags.Flags.setInReg();
6913 CLI.Ins.push_back(MyFlags);
6918 // Handle all of the outgoing arguments.
6920 CLI.OutVals.clear();
6921 ArgListTy &Args = CLI.getArgs();
6922 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6923 SmallVector<EVT, 4> ValueVTs;
6924 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6925 Type *FinalType = Args[i].Ty;
6926 if (Args[i].isByVal)
6927 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6928 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6929 FinalType, CLI.CallConv, CLI.IsVarArg);
6930 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6932 EVT VT = ValueVTs[Value];
6933 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6934 SDValue Op = SDValue(Args[i].Node.getNode(),
6935 Args[i].Node.getResNo() + Value);
6936 ISD::ArgFlagsTy Flags;
6937 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6943 if (Args[i].isInReg)
6947 if (Args[i].isByVal)
6949 if (Args[i].isInAlloca) {
6950 Flags.setInAlloca();
6951 // Set the byval flag for CCAssignFn callbacks that don't know about
6952 // inalloca. This way we can know how many bytes we should've allocated
6953 // and how many bytes a callee cleanup function will pop. If we port
6954 // inalloca to more targets, we'll have to add custom inalloca handling
6955 // in the various CC lowering callbacks.
6958 if (Args[i].isByVal || Args[i].isInAlloca) {
6959 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6960 Type *ElementTy = Ty->getElementType();
6961 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6962 // For ByVal, alignment should come from FE. BE will guess if this
6963 // info is not there but there are cases it cannot get right.
6964 unsigned FrameAlign;
6965 if (Args[i].Alignment)
6966 FrameAlign = Args[i].Alignment;
6968 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6969 Flags.setByValAlign(FrameAlign);
6974 Flags.setInConsecutiveRegs();
6975 Flags.setOrigAlign(OriginalAlignment);
6977 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6978 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6979 SmallVector<SDValue, 4> Parts(NumParts);
6980 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6983 ExtendKind = ISD::SIGN_EXTEND;
6984 else if (Args[i].isZExt)
6985 ExtendKind = ISD::ZERO_EXTEND;
6987 // Conservatively only handle 'returned' on non-vectors for now
6988 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6989 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6990 "unexpected use of 'returned'");
6991 // Before passing 'returned' to the target lowering code, ensure that
6992 // either the register MVT and the actual EVT are the same size or that
6993 // the return value and argument are extended in the same way; in these
6994 // cases it's safe to pass the argument register value unchanged as the
6995 // return register value (although it's at the target's option whether
6997 // TODO: allow code generation to take advantage of partially preserved
6998 // registers rather than clobbering the entire register when the
6999 // parameter extension method is not compatible with the return
7001 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7002 (ExtendKind != ISD::ANY_EXTEND &&
7003 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7004 Flags.setReturned();
7007 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7008 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7010 for (unsigned j = 0; j != NumParts; ++j) {
7011 // if it isn't first piece, alignment must be 1
7012 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7013 i < CLI.NumFixedArgs,
7014 i, j*Parts[j].getValueType().getStoreSize());
7015 if (NumParts > 1 && j == 0)
7016 MyFlags.Flags.setSplit();
7018 MyFlags.Flags.setOrigAlign(1);
7020 CLI.Outs.push_back(MyFlags);
7021 CLI.OutVals.push_back(Parts[j]);
7024 if (NeedsRegBlock && Value == NumValues - 1)
7025 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7029 SmallVector<SDValue, 4> InVals;
7030 CLI.Chain = LowerCall(CLI, InVals);
7032 // Verify that the target's LowerCall behaved as expected.
7033 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7034 "LowerCall didn't return a valid chain!");
7035 assert((!CLI.IsTailCall || InVals.empty()) &&
7036 "LowerCall emitted a return value for a tail call!");
7037 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7038 "LowerCall didn't emit the correct number of values!");
7040 // For a tail call, the return value is merely live-out and there aren't
7041 // any nodes in the DAG representing it. Return a special value to
7042 // indicate that a tail call has been emitted and no more Instructions
7043 // should be processed in the current block.
7044 if (CLI.IsTailCall) {
7045 CLI.DAG.setRoot(CLI.Chain);
7046 return std::make_pair(SDValue(), SDValue());
7049 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7050 assert(InVals[i].getNode() &&
7051 "LowerCall emitted a null value!");
7052 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7053 "LowerCall emitted a value with the wrong type!");
7056 SmallVector<SDValue, 4> ReturnValues;
7057 if (!CanLowerReturn) {
7058 // The instruction result is the result of loading from the
7059 // hidden sret parameter.
7060 SmallVector<EVT, 1> PVTs;
7061 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7063 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7064 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7065 EVT PtrVT = PVTs[0];
7067 unsigned NumValues = RetTys.size();
7068 ReturnValues.resize(NumValues);
7069 SmallVector<SDValue, 4> Chains(NumValues);
7071 for (unsigned i = 0; i < NumValues; ++i) {
7072 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7073 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7075 SDValue L = CLI.DAG.getLoad(
7076 RetTys[i], CLI.DL, CLI.Chain, Add,
7077 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7078 DemoteStackIdx, Offsets[i]),
7079 false, false, false, 1);
7080 ReturnValues[i] = L;
7081 Chains[i] = L.getValue(1);
7084 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7086 // Collect the legal value parts into potentially illegal values
7087 // that correspond to the original function's return values.
7088 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7090 AssertOp = ISD::AssertSext;
7091 else if (CLI.RetZExt)
7092 AssertOp = ISD::AssertZext;
7093 unsigned CurReg = 0;
7094 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7096 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7097 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7099 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7100 NumRegs, RegisterVT, VT, nullptr,
7105 // For a function returning void, there is no return value. We can't create
7106 // such a node, so we just return a null return value in that case. In
7107 // that case, nothing will actually look at the value.
7108 if (ReturnValues.empty())
7109 return std::make_pair(SDValue(), CLI.Chain);
7112 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7113 CLI.DAG.getVTList(RetTys), ReturnValues);
7114 return std::make_pair(Res, CLI.Chain);
7117 void TargetLowering::LowerOperationWrapper(SDNode *N,
7118 SmallVectorImpl<SDValue> &Results,
7119 SelectionDAG &DAG) const {
7120 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7122 Results.push_back(Res);
7125 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7126 llvm_unreachable("LowerOperation not implemented for this target!");
7130 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7131 SDValue Op = getNonRegisterValue(V);
7132 assert((Op.getOpcode() != ISD::CopyFromReg ||
7133 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7134 "Copy from a reg to the same reg!");
7135 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7138 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7140 SDValue Chain = DAG.getEntryNode();
7142 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7143 FuncInfo.PreferredExtendType.end())
7145 : FuncInfo.PreferredExtendType[V];
7146 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7147 PendingExports.push_back(Chain);
7150 #include "llvm/CodeGen/SelectionDAGISel.h"
7152 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7153 /// entry block, return true. This includes arguments used by switches, since
7154 /// the switch may expand into multiple basic blocks.
7155 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7156 // With FastISel active, we may be splitting blocks, so force creation
7157 // of virtual registers for all non-dead arguments.
7159 return A->use_empty();
7161 const BasicBlock *Entry = A->getParent()->begin();
7162 for (const User *U : A->users())
7163 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7164 return false; // Use not in entry block.
7169 void SelectionDAGISel::LowerArguments(const Function &F) {
7170 SelectionDAG &DAG = SDB->DAG;
7171 SDLoc dl = SDB->getCurSDLoc();
7172 const DataLayout &DL = DAG.getDataLayout();
7173 SmallVector<ISD::InputArg, 16> Ins;
7175 if (!FuncInfo->CanLowerReturn) {
7176 // Put in an sret pointer parameter before all the other parameters.
7177 SmallVector<EVT, 1> ValueVTs;
7178 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7179 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7181 // NOTE: Assuming that a pointer will never break down to more than one VT
7183 ISD::ArgFlagsTy Flags;
7185 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7186 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7187 ISD::InputArg::NoArgIndex, 0);
7188 Ins.push_back(RetArg);
7191 // Set up the incoming argument description vector.
7193 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7194 I != E; ++I, ++Idx) {
7195 SmallVector<EVT, 4> ValueVTs;
7196 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7197 bool isArgValueUsed = !I->use_empty();
7198 unsigned PartBase = 0;
7199 Type *FinalType = I->getType();
7200 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7201 FinalType = cast<PointerType>(FinalType)->getElementType();
7202 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7203 FinalType, F.getCallingConv(), F.isVarArg());
7204 for (unsigned Value = 0, NumValues = ValueVTs.size();
7205 Value != NumValues; ++Value) {
7206 EVT VT = ValueVTs[Value];
7207 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7208 ISD::ArgFlagsTy Flags;
7209 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7211 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7213 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7215 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7217 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7219 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7221 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7222 Flags.setInAlloca();
7223 // Set the byval flag for CCAssignFn callbacks that don't know about
7224 // inalloca. This way we can know how many bytes we should've allocated
7225 // and how many bytes a callee cleanup function will pop. If we port
7226 // inalloca to more targets, we'll have to add custom inalloca handling
7227 // in the various CC lowering callbacks.
7230 if (Flags.isByVal() || Flags.isInAlloca()) {
7231 PointerType *Ty = cast<PointerType>(I->getType());
7232 Type *ElementTy = Ty->getElementType();
7233 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7234 // For ByVal, alignment should be passed from FE. BE will guess if
7235 // this info is not there but there are cases it cannot get right.
7236 unsigned FrameAlign;
7237 if (F.getParamAlignment(Idx))
7238 FrameAlign = F.getParamAlignment(Idx);
7240 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7241 Flags.setByValAlign(FrameAlign);
7243 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7246 Flags.setInConsecutiveRegs();
7247 Flags.setOrigAlign(OriginalAlignment);
7249 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7250 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7251 for (unsigned i = 0; i != NumRegs; ++i) {
7252 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7253 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7254 if (NumRegs > 1 && i == 0)
7255 MyFlags.Flags.setSplit();
7256 // if it isn't first piece, alignment must be 1
7258 MyFlags.Flags.setOrigAlign(1);
7259 Ins.push_back(MyFlags);
7261 if (NeedsRegBlock && Value == NumValues - 1)
7262 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7263 PartBase += VT.getStoreSize();
7267 // Call the target to set up the argument values.
7268 SmallVector<SDValue, 8> InVals;
7269 SDValue NewRoot = TLI->LowerFormalArguments(
7270 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7272 // Verify that the target's LowerFormalArguments behaved as expected.
7273 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7274 "LowerFormalArguments didn't return a valid chain!");
7275 assert(InVals.size() == Ins.size() &&
7276 "LowerFormalArguments didn't emit the correct number of values!");
7278 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7279 assert(InVals[i].getNode() &&
7280 "LowerFormalArguments emitted a null value!");
7281 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7282 "LowerFormalArguments emitted a value with the wrong type!");
7286 // Update the DAG with the new chain value resulting from argument lowering.
7287 DAG.setRoot(NewRoot);
7289 // Set up the argument values.
7292 if (!FuncInfo->CanLowerReturn) {
7293 // Create a virtual register for the sret pointer, and put in a copy
7294 // from the sret argument into it.
7295 SmallVector<EVT, 1> ValueVTs;
7296 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7297 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7298 MVT VT = ValueVTs[0].getSimpleVT();
7299 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7300 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7301 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7302 RegVT, VT, nullptr, AssertOp);
7304 MachineFunction& MF = SDB->DAG.getMachineFunction();
7305 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7306 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7307 FuncInfo->DemoteRegister = SRetReg;
7309 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7310 DAG.setRoot(NewRoot);
7312 // i indexes lowered arguments. Bump it past the hidden sret argument.
7313 // Idx indexes LLVM arguments. Don't touch it.
7317 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7319 SmallVector<SDValue, 4> ArgValues;
7320 SmallVector<EVT, 4> ValueVTs;
7321 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7322 unsigned NumValues = ValueVTs.size();
7324 // If this argument is unused then remember its value. It is used to generate
7325 // debugging information.
7326 if (I->use_empty() && NumValues) {
7327 SDB->setUnusedArgValue(I, InVals[i]);
7329 // Also remember any frame index for use in FastISel.
7330 if (FrameIndexSDNode *FI =
7331 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7332 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7335 for (unsigned Val = 0; Val != NumValues; ++Val) {
7336 EVT VT = ValueVTs[Val];
7337 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7338 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7340 if (!I->use_empty()) {
7341 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7342 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7343 AssertOp = ISD::AssertSext;
7344 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7345 AssertOp = ISD::AssertZext;
7347 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7348 NumParts, PartVT, VT,
7349 nullptr, AssertOp));
7355 // We don't need to do anything else for unused arguments.
7356 if (ArgValues.empty())
7359 // Note down frame index.
7360 if (FrameIndexSDNode *FI =
7361 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7362 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7364 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7365 SDB->getCurSDLoc());
7367 SDB->setValue(I, Res);
7368 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7369 if (LoadSDNode *LNode =
7370 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7371 if (FrameIndexSDNode *FI =
7372 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7373 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7376 // If this argument is live outside of the entry block, insert a copy from
7377 // wherever we got it to the vreg that other BB's will reference it as.
7378 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7379 // If we can, though, try to skip creating an unnecessary vreg.
7380 // FIXME: This isn't very clean... it would be nice to make this more
7381 // general. It's also subtly incompatible with the hacks FastISel
7383 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7384 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7385 FuncInfo->ValueMap[I] = Reg;
7389 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7390 FuncInfo->InitializeRegForValue(I);
7391 SDB->CopyToExportRegsIfNeeded(I);
7395 assert(i == InVals.size() && "Argument register count mismatch!");
7397 // Finally, if the target has anything special to do, allow it to do so.
7398 EmitFunctionEntryCode();
7401 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7402 /// ensure constants are generated when needed. Remember the virtual registers
7403 /// that need to be added to the Machine PHI nodes as input. We cannot just
7404 /// directly add them, because expansion might result in multiple MBB's for one
7405 /// BB. As such, the start of the BB might correspond to a different MBB than
7409 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7410 const TerminatorInst *TI = LLVMBB->getTerminator();
7412 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7414 // Check PHI nodes in successors that expect a value to be available from this
7416 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7417 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7418 if (!isa<PHINode>(SuccBB->begin())) continue;
7419 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7421 // If this terminator has multiple identical successors (common for
7422 // switches), only handle each succ once.
7423 if (!SuccsHandled.insert(SuccMBB).second)
7426 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7428 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7429 // nodes and Machine PHI nodes, but the incoming operands have not been
7431 for (BasicBlock::const_iterator I = SuccBB->begin();
7432 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7433 // Ignore dead phi's.
7434 if (PN->use_empty()) continue;
7437 if (PN->getType()->isEmptyTy())
7441 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7443 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7444 unsigned &RegOut = ConstantsOut[C];
7446 RegOut = FuncInfo.CreateRegs(C->getType());
7447 CopyValueToVirtualRegister(C, RegOut);
7451 DenseMap<const Value *, unsigned>::iterator I =
7452 FuncInfo.ValueMap.find(PHIOp);
7453 if (I != FuncInfo.ValueMap.end())
7456 assert(isa<AllocaInst>(PHIOp) &&
7457 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7458 "Didn't codegen value into a register!??");
7459 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7460 CopyValueToVirtualRegister(PHIOp, Reg);
7464 // Remember that this register needs to added to the machine PHI node as
7465 // the input for this MBB.
7466 SmallVector<EVT, 4> ValueVTs;
7467 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7468 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7469 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7470 EVT VT = ValueVTs[vti];
7471 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7472 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7473 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7474 Reg += NumRegisters;
7479 ConstantsOut.clear();
7482 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7485 SelectionDAGBuilder::StackProtectorDescriptor::
7486 AddSuccessorMBB(const BasicBlock *BB,
7487 MachineBasicBlock *ParentMBB,
7489 MachineBasicBlock *SuccMBB) {
7490 // If SuccBB has not been created yet, create it.
7492 MachineFunction *MF = ParentMBB->getParent();
7493 MachineFunction::iterator BBI = ParentMBB;
7494 SuccMBB = MF->CreateMachineBasicBlock(BB);
7495 MF->insert(++BBI, SuccMBB);
7497 // Add it as a successor of ParentMBB.
7498 ParentMBB->addSuccessor(
7499 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7503 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7504 MachineFunction::iterator I = MBB;
7505 if (++I == FuncInfo.MF->end())
7510 /// During lowering new call nodes can be created (such as memset, etc.).
7511 /// Those will become new roots of the current DAG, but complications arise
7512 /// when they are tail calls. In such cases, the call lowering will update
7513 /// the root, but the builder still needs to know that a tail call has been
7514 /// lowered in order to avoid generating an additional return.
7515 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7516 // If the node is null, we do have a tail call.
7517 if (MaybeTC.getNode() != nullptr)
7518 DAG.setRoot(MaybeTC);
7523 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7524 unsigned *TotalCases, unsigned First,
7526 assert(Last >= First);
7527 assert(TotalCases[Last] >= TotalCases[First]);
7529 APInt LowCase = Clusters[First].Low->getValue();
7530 APInt HighCase = Clusters[Last].High->getValue();
7531 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7533 // FIXME: A range of consecutive cases has 100% density, but only requires one
7534 // comparison to lower. We should discriminate against such consecutive ranges
7537 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7538 uint64_t Range = Diff + 1;
7541 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7543 assert(NumCases < UINT64_MAX / 100);
7544 assert(Range >= NumCases);
7546 return NumCases * 100 >= Range * MinJumpTableDensity;
7549 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7550 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7551 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7554 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7555 unsigned First, unsigned Last,
7556 const SwitchInst *SI,
7557 MachineBasicBlock *DefaultMBB,
7558 CaseCluster &JTCluster) {
7559 assert(First <= Last);
7561 uint32_t Weight = 0;
7562 unsigned NumCmps = 0;
7563 std::vector<MachineBasicBlock*> Table;
7564 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7565 for (unsigned I = First; I <= Last; ++I) {
7566 assert(Clusters[I].Kind == CC_Range);
7567 Weight += Clusters[I].Weight;
7568 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7569 APInt Low = Clusters[I].Low->getValue();
7570 APInt High = Clusters[I].High->getValue();
7571 NumCmps += (Low == High) ? 1 : 2;
7573 // Fill the gap between this and the previous cluster.
7574 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7575 assert(PreviousHigh.slt(Low));
7576 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7577 for (uint64_t J = 0; J < Gap; J++)
7578 Table.push_back(DefaultMBB);
7580 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7581 for (uint64_t J = 0; J < ClusterSize; ++J)
7582 Table.push_back(Clusters[I].MBB);
7583 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7586 unsigned NumDests = JTWeights.size();
7587 if (isSuitableForBitTests(NumDests, NumCmps,
7588 Clusters[First].Low->getValue(),
7589 Clusters[Last].High->getValue())) {
7590 // Clusters[First..Last] should be lowered as bit tests instead.
7594 // Create the MBB that will load from and jump through the table.
7595 // Note: We create it here, but it's not inserted into the function yet.
7596 MachineFunction *CurMF = FuncInfo.MF;
7597 MachineBasicBlock *JumpTableMBB =
7598 CurMF->CreateMachineBasicBlock(SI->getParent());
7600 // Add successors. Note: use table order for determinism.
7601 SmallPtrSet<MachineBasicBlock *, 8> Done;
7602 for (MachineBasicBlock *Succ : Table) {
7603 if (Done.count(Succ))
7605 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7609 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7610 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7611 ->createJumpTableIndex(Table);
7613 // Set up the jump table info.
7614 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7615 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7616 Clusters[Last].High->getValue(), SI->getCondition(),
7618 JTCases.emplace_back(std::move(JTH), std::move(JT));
7620 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7621 JTCases.size() - 1, Weight);
7625 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7626 const SwitchInst *SI,
7627 MachineBasicBlock *DefaultMBB) {
7629 // Clusters must be non-empty, sorted, and only contain Range clusters.
7630 assert(!Clusters.empty());
7631 for (CaseCluster &C : Clusters)
7632 assert(C.Kind == CC_Range);
7633 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7634 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7637 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7638 if (!areJTsAllowed(TLI))
7641 const int64_t N = Clusters.size();
7642 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7644 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7645 SmallVector<unsigned, 8> TotalCases(N);
7647 for (unsigned i = 0; i < N; ++i) {
7648 APInt Hi = Clusters[i].High->getValue();
7649 APInt Lo = Clusters[i].Low->getValue();
7650 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7652 TotalCases[i] += TotalCases[i - 1];
7655 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7656 // Cheap case: the whole range might be suitable for jump table.
7657 CaseCluster JTCluster;
7658 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7659 Clusters[0] = JTCluster;
7665 // The algorithm below is not suitable for -O0.
7666 if (TM.getOptLevel() == CodeGenOpt::None)
7669 // Split Clusters into minimum number of dense partitions. The algorithm uses
7670 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7671 // for the Case Statement'" (1994), but builds the MinPartitions array in
7672 // reverse order to make it easier to reconstruct the partitions in ascending
7673 // order. In the choice between two optimal partitionings, it picks the one
7674 // which yields more jump tables.
7676 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7677 SmallVector<unsigned, 8> MinPartitions(N);
7678 // LastElement[i] is the last element of the partition starting at i.
7679 SmallVector<unsigned, 8> LastElement(N);
7680 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7681 SmallVector<unsigned, 8> NumTables(N);
7683 // Base case: There is only one way to partition Clusters[N-1].
7684 MinPartitions[N - 1] = 1;
7685 LastElement[N - 1] = N - 1;
7686 assert(MinJumpTableSize > 1);
7687 NumTables[N - 1] = 0;
7689 // Note: loop indexes are signed to avoid underflow.
7690 for (int64_t i = N - 2; i >= 0; i--) {
7691 // Find optimal partitioning of Clusters[i..N-1].
7692 // Baseline: Put Clusters[i] into a partition on its own.
7693 MinPartitions[i] = MinPartitions[i + 1] + 1;
7695 NumTables[i] = NumTables[i + 1];
7697 // Search for a solution that results in fewer partitions.
7698 for (int64_t j = N - 1; j > i; j--) {
7699 // Try building a partition from Clusters[i..j].
7700 if (isDense(Clusters, &TotalCases[0], i, j)) {
7701 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7702 bool IsTable = j - i + 1 >= MinJumpTableSize;
7703 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7705 // If this j leads to fewer partitions, or same number of partitions
7706 // with more lookup tables, it is a better partitioning.
7707 if (NumPartitions < MinPartitions[i] ||
7708 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7709 MinPartitions[i] = NumPartitions;
7711 NumTables[i] = Tables;
7717 // Iterate over the partitions, replacing some with jump tables in-place.
7718 unsigned DstIndex = 0;
7719 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7720 Last = LastElement[First];
7721 assert(Last >= First);
7722 assert(DstIndex <= First);
7723 unsigned NumClusters = Last - First + 1;
7725 CaseCluster JTCluster;
7726 if (NumClusters >= MinJumpTableSize &&
7727 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7728 Clusters[DstIndex++] = JTCluster;
7730 for (unsigned I = First; I <= Last; ++I)
7731 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7734 Clusters.resize(DstIndex);
7737 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7738 // FIXME: Using the pointer type doesn't seem ideal.
7739 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7740 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7744 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7747 const APInt &High) {
7748 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7749 // range of cases both require only one branch to lower. Just looking at the
7750 // number of clusters and destinations should be enough to decide whether to
7753 // To lower a range with bit tests, the range must fit the bitwidth of a
7755 if (!rangeFitsInWord(Low, High))
7758 // Decide whether it's profitable to lower this range with bit tests. Each
7759 // destination requires a bit test and branch, and there is an overall range
7760 // check branch. For a small number of clusters, separate comparisons might be
7761 // cheaper, and for many destinations, splitting the range might be better.
7762 return (NumDests == 1 && NumCmps >= 3) ||
7763 (NumDests == 2 && NumCmps >= 5) ||
7764 (NumDests == 3 && NumCmps >= 6);
7767 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7768 unsigned First, unsigned Last,
7769 const SwitchInst *SI,
7770 CaseCluster &BTCluster) {
7771 assert(First <= Last);
7775 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7776 unsigned NumCmps = 0;
7777 for (int64_t I = First; I <= Last; ++I) {
7778 assert(Clusters[I].Kind == CC_Range);
7779 Dests.set(Clusters[I].MBB->getNumber());
7780 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7782 unsigned NumDests = Dests.count();
7784 APInt Low = Clusters[First].Low->getValue();
7785 APInt High = Clusters[Last].High->getValue();
7786 assert(Low.slt(High));
7788 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7794 const int BitWidth = DAG.getTargetLoweringInfo()
7795 .getPointerTy(DAG.getDataLayout())
7797 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7799 // Check if the clusters cover a contiguous range such that no value in the
7800 // range will jump to the default statement.
7801 bool ContiguousRange = true;
7802 for (int64_t I = First + 1; I <= Last; ++I) {
7803 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7804 ContiguousRange = false;
7809 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7810 // Optimize the case where all the case values fit in a word without having
7811 // to subtract minValue. In this case, we can optimize away the subtraction.
7812 LowBound = APInt::getNullValue(Low.getBitWidth());
7814 ContiguousRange = false;
7817 CmpRange = High - Low;
7821 uint32_t TotalWeight = 0;
7822 for (unsigned i = First; i <= Last; ++i) {
7823 // Find the CaseBits for this destination.
7825 for (j = 0; j < CBV.size(); ++j)
7826 if (CBV[j].BB == Clusters[i].MBB)
7828 if (j == CBV.size())
7829 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7830 CaseBits *CB = &CBV[j];
7832 // Update Mask, Bits and ExtraWeight.
7833 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7834 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7835 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7836 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7837 CB->Bits += Hi - Lo + 1;
7838 CB->ExtraWeight += Clusters[i].Weight;
7839 TotalWeight += Clusters[i].Weight;
7840 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7844 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7845 // Sort by weight first, number of bits second.
7846 if (a.ExtraWeight != b.ExtraWeight)
7847 return a.ExtraWeight > b.ExtraWeight;
7848 return a.Bits > b.Bits;
7851 for (auto &CB : CBV) {
7852 MachineBasicBlock *BitTestBB =
7853 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7854 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7856 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7857 SI->getCondition(), -1U, MVT::Other, false,
7858 ContiguousRange, nullptr, nullptr, std::move(BTI),
7861 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7862 BitTestCases.size() - 1, TotalWeight);
7866 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7867 const SwitchInst *SI) {
7868 // Partition Clusters into as few subsets as possible, where each subset has a
7869 // range that fits in a machine word and has <= 3 unique destinations.
7872 // Clusters must be sorted and contain Range or JumpTable clusters.
7873 assert(!Clusters.empty());
7874 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7875 for (const CaseCluster &C : Clusters)
7876 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7877 for (unsigned i = 1; i < Clusters.size(); ++i)
7878 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7881 // The algorithm below is not suitable for -O0.
7882 if (TM.getOptLevel() == CodeGenOpt::None)
7885 // If target does not have legal shift left, do not emit bit tests at all.
7886 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7887 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7888 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7891 int BitWidth = PTy.getSizeInBits();
7892 const int64_t N = Clusters.size();
7894 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7895 SmallVector<unsigned, 8> MinPartitions(N);
7896 // LastElement[i] is the last element of the partition starting at i.
7897 SmallVector<unsigned, 8> LastElement(N);
7899 // FIXME: This might not be the best algorithm for finding bit test clusters.
7901 // Base case: There is only one way to partition Clusters[N-1].
7902 MinPartitions[N - 1] = 1;
7903 LastElement[N - 1] = N - 1;
7905 // Note: loop indexes are signed to avoid underflow.
7906 for (int64_t i = N - 2; i >= 0; --i) {
7907 // Find optimal partitioning of Clusters[i..N-1].
7908 // Baseline: Put Clusters[i] into a partition on its own.
7909 MinPartitions[i] = MinPartitions[i + 1] + 1;
7912 // Search for a solution that results in fewer partitions.
7913 // Note: the search is limited by BitWidth, reducing time complexity.
7914 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7915 // Try building a partition from Clusters[i..j].
7918 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7919 Clusters[j].High->getValue()))
7922 // Check nbr of destinations and cluster types.
7923 // FIXME: This works, but doesn't seem very efficient.
7924 bool RangesOnly = true;
7925 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7926 for (int64_t k = i; k <= j; k++) {
7927 if (Clusters[k].Kind != CC_Range) {
7931 Dests.set(Clusters[k].MBB->getNumber());
7933 if (!RangesOnly || Dests.count() > 3)
7936 // Check if it's a better partition.
7937 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7938 if (NumPartitions < MinPartitions[i]) {
7939 // Found a better partition.
7940 MinPartitions[i] = NumPartitions;
7946 // Iterate over the partitions, replacing with bit-test clusters in-place.
7947 unsigned DstIndex = 0;
7948 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7949 Last = LastElement[First];
7950 assert(First <= Last);
7951 assert(DstIndex <= First);
7953 CaseCluster BitTestCluster;
7954 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7955 Clusters[DstIndex++] = BitTestCluster;
7957 size_t NumClusters = Last - First + 1;
7958 std::memmove(&Clusters[DstIndex], &Clusters[First],
7959 sizeof(Clusters[0]) * NumClusters);
7960 DstIndex += NumClusters;
7963 Clusters.resize(DstIndex);
7966 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7967 MachineBasicBlock *SwitchMBB,
7968 MachineBasicBlock *DefaultMBB) {
7969 MachineFunction *CurMF = FuncInfo.MF;
7970 MachineBasicBlock *NextMBB = nullptr;
7971 MachineFunction::iterator BBI = W.MBB;
7972 if (++BBI != FuncInfo.MF->end())
7975 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7977 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7979 if (Size == 2 && W.MBB == SwitchMBB) {
7980 // If any two of the cases has the same destination, and if one value
7981 // is the same as the other, but has one bit unset that the other has set,
7982 // use bit manipulation to do two compares at once. For example:
7983 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7984 // TODO: This could be extended to merge any 2 cases in switches with 3
7986 // TODO: Handle cases where W.CaseBB != SwitchBB.
7987 CaseCluster &Small = *W.FirstCluster;
7988 CaseCluster &Big = *W.LastCluster;
7990 if (Small.Low == Small.High && Big.Low == Big.High &&
7991 Small.MBB == Big.MBB) {
7992 const APInt &SmallValue = Small.Low->getValue();
7993 const APInt &BigValue = Big.Low->getValue();
7995 // Check that there is only one bit different.
7996 APInt CommonBit = BigValue ^ SmallValue;
7997 if (CommonBit.isPowerOf2()) {
7998 SDValue CondLHS = getValue(Cond);
7999 EVT VT = CondLHS.getValueType();
8000 SDLoc DL = getCurSDLoc();
8002 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8003 DAG.getConstant(CommonBit, DL, VT));
8004 SDValue Cond = DAG.getSetCC(
8005 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8008 // Update successor info.
8009 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8010 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8011 addSuccessorWithWeight(
8012 SwitchMBB, DefaultMBB,
8013 // The default destination is the first successor in IR.
8014 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8017 // Insert the true branch.
8019 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8020 DAG.getBasicBlock(Small.MBB));
8021 // Insert the false branch.
8022 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8023 DAG.getBasicBlock(DefaultMBB));
8025 DAG.setRoot(BrCond);
8031 if (TM.getOptLevel() != CodeGenOpt::None) {
8032 // Order cases by weight so the most likely case will be checked first.
8033 std::sort(W.FirstCluster, W.LastCluster + 1,
8034 [](const CaseCluster &a, const CaseCluster &b) {
8035 return a.Weight > b.Weight;
8038 // Rearrange the case blocks so that the last one falls through if possible
8039 // without without changing the order of weights.
8040 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8042 if (I->Weight > W.LastCluster->Weight)
8044 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8045 std::swap(*I, *W.LastCluster);
8051 // Compute total weight.
8052 uint32_t DefaultWeight = W.DefaultWeight;
8053 uint32_t UnhandledWeights = DefaultWeight;
8054 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8055 UnhandledWeights += I->Weight;
8056 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8059 MachineBasicBlock *CurMBB = W.MBB;
8060 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8061 MachineBasicBlock *Fallthrough;
8062 if (I == W.LastCluster) {
8063 // For the last cluster, fall through to the default destination.
8064 Fallthrough = DefaultMBB;
8066 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8067 CurMF->insert(BBI, Fallthrough);
8068 // Put Cond in a virtual register to make it available from the new blocks.
8069 ExportFromCurrentBlock(Cond);
8071 UnhandledWeights -= I->Weight;
8074 case CC_JumpTable: {
8075 // FIXME: Optimize away range check based on pivot comparisons.
8076 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8077 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8079 // The jump block hasn't been inserted yet; insert it here.
8080 MachineBasicBlock *JumpMBB = JT->MBB;
8081 CurMF->insert(BBI, JumpMBB);
8083 uint32_t JumpWeight = I->Weight;
8084 uint32_t FallthroughWeight = UnhandledWeights;
8086 // If Fallthrough is a target of the jump table, we evenly distribute
8087 // the weight on the edge to Fallthrough to successors of CurMBB.
8088 // Also update the weight on the edge from JumpMBB to Fallthrough.
8089 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8090 SE = JumpMBB->succ_end();
8092 if (*SI == Fallthrough) {
8093 JumpWeight += DefaultWeight / 2;
8094 FallthroughWeight -= DefaultWeight / 2;
8095 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8100 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8101 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8103 // The jump table header will be inserted in our current block, do the
8104 // range check, and fall through to our fallthrough block.
8105 JTH->HeaderBB = CurMBB;
8106 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8108 // If we're in the right place, emit the jump table header right now.
8109 if (CurMBB == SwitchMBB) {
8110 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8111 JTH->Emitted = true;
8116 // FIXME: Optimize away range check based on pivot comparisons.
8117 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8119 // The bit test blocks haven't been inserted yet; insert them here.
8120 for (BitTestCase &BTC : BTB->Cases)
8121 CurMF->insert(BBI, BTC.ThisBB);
8123 // Fill in fields of the BitTestBlock.
8124 BTB->Parent = CurMBB;
8125 BTB->Default = Fallthrough;
8127 BTB->DefaultWeight = UnhandledWeights;
8128 // If the cases in bit test don't form a contiguous range, we evenly
8129 // distribute the weight on the edge to Fallthrough to two successors
8131 if (!BTB->ContiguousRange) {
8132 BTB->Weight += DefaultWeight / 2;
8133 BTB->DefaultWeight -= DefaultWeight / 2;
8136 // If we're in the right place, emit the bit test header right now.
8137 if (CurMBB == SwitchMBB) {
8138 visitBitTestHeader(*BTB, SwitchMBB);
8139 BTB->Emitted = true;
8144 const Value *RHS, *LHS, *MHS;
8146 if (I->Low == I->High) {
8147 // Check Cond == I->Low.
8153 // Check I->Low <= Cond <= I->High.
8160 // The false weight is the sum of all unhandled cases.
8161 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8164 if (CurMBB == SwitchMBB)
8165 visitSwitchCase(CB, SwitchMBB);
8167 SwitchCases.push_back(CB);
8172 CurMBB = Fallthrough;
8176 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8177 CaseClusterIt First,
8178 CaseClusterIt Last) {
8179 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8180 if (X.Weight != CC.Weight)
8181 return X.Weight > CC.Weight;
8183 // Ties are broken by comparing the case value.
8184 return X.Low->getValue().slt(CC.Low->getValue());
8188 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8189 const SwitchWorkListItem &W,
8191 MachineBasicBlock *SwitchMBB) {
8192 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8193 "Clusters not sorted?");
8195 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8197 // Balance the tree based on branch weights to create a near-optimal (in terms
8198 // of search time given key frequency) binary search tree. See e.g. Kurt
8199 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8200 CaseClusterIt LastLeft = W.FirstCluster;
8201 CaseClusterIt FirstRight = W.LastCluster;
8202 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8203 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8205 // Move LastLeft and FirstRight towards each other from opposite directions to
8206 // find a partitioning of the clusters which balances the weight on both
8207 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8208 // taken to ensure 0-weight nodes are distributed evenly.
8210 while (LastLeft + 1 < FirstRight) {
8211 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8212 LeftWeight += (++LastLeft)->Weight;
8214 RightWeight += (--FirstRight)->Weight;
8219 // Our binary search tree differs from a typical BST in that ours can have up
8220 // to three values in each leaf. The pivot selection above doesn't take that
8221 // into account, which means the tree might require more nodes and be less
8222 // efficient. We compensate for this here.
8224 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8225 unsigned NumRight = W.LastCluster - FirstRight + 1;
8227 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8228 // If one side has less than 3 clusters, and the other has more than 3,
8229 // consider taking a cluster from the other side.
8231 if (NumLeft < NumRight) {
8232 // Consider moving the first cluster on the right to the left side.
8233 CaseCluster &CC = *FirstRight;
8234 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8235 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8236 if (LeftSideRank <= RightSideRank) {
8237 // Moving the cluster to the left does not demote it.
8243 assert(NumRight < NumLeft);
8244 // Consider moving the last element on the left to the right side.
8245 CaseCluster &CC = *LastLeft;
8246 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8247 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8248 if (RightSideRank <= LeftSideRank) {
8249 // Moving the cluster to the right does not demot it.
8259 assert(LastLeft + 1 == FirstRight);
8260 assert(LastLeft >= W.FirstCluster);
8261 assert(FirstRight <= W.LastCluster);
8263 // Use the first element on the right as pivot since we will make less-than
8264 // comparisons against it.
8265 CaseClusterIt PivotCluster = FirstRight;
8266 assert(PivotCluster > W.FirstCluster);
8267 assert(PivotCluster <= W.LastCluster);
8269 CaseClusterIt FirstLeft = W.FirstCluster;
8270 CaseClusterIt LastRight = W.LastCluster;
8272 const ConstantInt *Pivot = PivotCluster->Low;
8274 // New blocks will be inserted immediately after the current one.
8275 MachineFunction::iterator BBI = W.MBB;
8278 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8279 // we can branch to its destination directly if it's squeezed exactly in
8280 // between the known lower bound and Pivot - 1.
8281 MachineBasicBlock *LeftMBB;
8282 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8283 FirstLeft->Low == W.GE &&
8284 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8285 LeftMBB = FirstLeft->MBB;
8287 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8288 FuncInfo.MF->insert(BBI, LeftMBB);
8290 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8291 // Put Cond in a virtual register to make it available from the new blocks.
8292 ExportFromCurrentBlock(Cond);
8295 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8296 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8297 // directly if RHS.High equals the current upper bound.
8298 MachineBasicBlock *RightMBB;
8299 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8300 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8301 RightMBB = FirstRight->MBB;
8303 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8304 FuncInfo.MF->insert(BBI, RightMBB);
8306 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8307 // Put Cond in a virtual register to make it available from the new blocks.
8308 ExportFromCurrentBlock(Cond);
8311 // Create the CaseBlock record that will be used to lower the branch.
8312 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8313 LeftWeight, RightWeight);
8315 if (W.MBB == SwitchMBB)
8316 visitSwitchCase(CB, SwitchMBB);
8318 SwitchCases.push_back(CB);
8321 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8322 // Extract cases from the switch.
8323 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8324 CaseClusterVector Clusters;
8325 Clusters.reserve(SI.getNumCases());
8326 for (auto I : SI.cases()) {
8327 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8328 const ConstantInt *CaseVal = I.getCaseValue();
8330 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8331 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8334 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8336 // Cluster adjacent cases with the same destination. We do this at all
8337 // optimization levels because it's cheap to do and will make codegen faster
8338 // if there are many clusters.
8339 sortAndRangeify(Clusters);
8341 if (TM.getOptLevel() != CodeGenOpt::None) {
8342 // Replace an unreachable default with the most popular destination.
8343 // FIXME: Exploit unreachable default more aggressively.
8344 bool UnreachableDefault =
8345 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8346 if (UnreachableDefault && !Clusters.empty()) {
8347 DenseMap<const BasicBlock *, unsigned> Popularity;
8348 unsigned MaxPop = 0;
8349 const BasicBlock *MaxBB = nullptr;
8350 for (auto I : SI.cases()) {
8351 const BasicBlock *BB = I.getCaseSuccessor();
8352 if (++Popularity[BB] > MaxPop) {
8353 MaxPop = Popularity[BB];
8358 assert(MaxPop > 0 && MaxBB);
8359 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8361 // Remove cases that were pointing to the destination that is now the
8363 CaseClusterVector New;
8364 New.reserve(Clusters.size());
8365 for (CaseCluster &CC : Clusters) {
8366 if (CC.MBB != DefaultMBB)
8369 Clusters = std::move(New);
8373 // If there is only the default destination, jump there directly.
8374 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8375 if (Clusters.empty()) {
8376 SwitchMBB->addSuccessor(DefaultMBB);
8377 if (DefaultMBB != NextBlock(SwitchMBB)) {
8378 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8379 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8384 findJumpTables(Clusters, &SI, DefaultMBB);
8385 findBitTestClusters(Clusters, &SI);
8388 dbgs() << "Case clusters: ";
8389 for (const CaseCluster &C : Clusters) {
8390 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8391 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8393 C.Low->getValue().print(dbgs(), true);
8394 if (C.Low != C.High) {
8396 C.High->getValue().print(dbgs(), true);
8403 assert(!Clusters.empty());
8404 SwitchWorkList WorkList;
8405 CaseClusterIt First = Clusters.begin();
8406 CaseClusterIt Last = Clusters.end() - 1;
8407 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8408 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8410 while (!WorkList.empty()) {
8411 SwitchWorkListItem W = WorkList.back();
8412 WorkList.pop_back();
8413 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8415 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8416 // For optimized builds, lower large range as a balanced binary tree.
8417 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8421 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);