1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 llvm_unreachable("should never codegen catchpads");
1166 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1167 // Update machine-CFG edge.
1168 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1169 FuncInfo.MBB->addSuccessor(TargetMBB);
1171 // Create the terminator node.
1172 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1173 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1177 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1178 llvm_unreachable("should never codegen catchendpads");
1181 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1182 // Don't emit any special code for the cleanuppad instruction. It just marks
1183 // the start of a funclet.
1184 FuncInfo.MBB->setIsEHFuncletEntry();
1185 FuncInfo.MBB->setIsCleanupFuncletEntry();
1188 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1189 /// many places it could ultimately go. In the IR, we have a single unwind
1190 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1191 /// This function skips over imaginary basic blocks that hold catchpad,
1192 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1193 /// basic block destinations.
1195 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1196 const BasicBlock *EHPadBB,
1197 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1198 bool IsMSVCCXX = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn()) ==
1199 EHPersonality::MSVC_CXX;
1201 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1202 if (isa<LandingPadInst>(Pad)) {
1203 // Stop on landingpads. They are not funclets.
1204 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1206 } else if (isa<CleanupPadInst>(Pad) || isa<LandingPadInst>(Pad)) {
1207 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1209 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1210 UnwindDests.back()->setIsEHFuncletEntry();
1212 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1213 // Add the catchpad handler to the possible destinations.
1214 UnwindDests.push_back(FuncInfo.MBBMap[CPI->getNormalDest()]);
1215 // In MSVC C++, catchblocks are funclets and need prologues.
1217 UnwindDests.back()->setIsEHFuncletEntry();
1218 EHPadBB = CPI->getUnwindDest();
1219 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1220 EHPadBB = CEPI->getUnwindDest();
1221 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1222 EHPadBB = CEPI->getUnwindDest();
1227 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1228 // Update successor info.
1229 // FIXME: The weights for catchpads will be wrong.
1230 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1231 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1232 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1233 UnwindDest->setIsEHPad();
1234 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1237 // Create the terminator node.
1239 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1243 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1244 report_fatal_error("visitCleanupEndPad not yet implemented!");
1247 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1248 report_fatal_error("visitTerminatePad not yet implemented!");
1251 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1253 auto &DL = DAG.getDataLayout();
1254 SDValue Chain = getControlRoot();
1255 SmallVector<ISD::OutputArg, 8> Outs;
1256 SmallVector<SDValue, 8> OutVals;
1258 if (!FuncInfo.CanLowerReturn) {
1259 unsigned DemoteReg = FuncInfo.DemoteRegister;
1260 const Function *F = I.getParent()->getParent();
1262 // Emit a store of the return value through the virtual register.
1263 // Leave Outs empty so that LowerReturn won't try to load return
1264 // registers the usual way.
1265 SmallVector<EVT, 1> PtrValueVTs;
1266 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1269 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1270 SDValue RetOp = getValue(I.getOperand(0));
1272 SmallVector<EVT, 4> ValueVTs;
1273 SmallVector<uint64_t, 4> Offsets;
1274 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1275 unsigned NumValues = ValueVTs.size();
1277 SmallVector<SDValue, 4> Chains(NumValues);
1278 for (unsigned i = 0; i != NumValues; ++i) {
1279 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1280 RetPtr.getValueType(), RetPtr,
1281 DAG.getIntPtrConstant(Offsets[i],
1284 DAG.getStore(Chain, getCurSDLoc(),
1285 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1286 // FIXME: better loc info would be nice.
1287 Add, MachinePointerInfo(), false, false, 0);
1290 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1291 MVT::Other, Chains);
1292 } else if (I.getNumOperands() != 0) {
1293 SmallVector<EVT, 4> ValueVTs;
1294 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1295 unsigned NumValues = ValueVTs.size();
1297 SDValue RetOp = getValue(I.getOperand(0));
1299 const Function *F = I.getParent()->getParent();
1301 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1302 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1304 ExtendKind = ISD::SIGN_EXTEND;
1305 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1307 ExtendKind = ISD::ZERO_EXTEND;
1309 LLVMContext &Context = F->getContext();
1310 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1313 for (unsigned j = 0; j != NumValues; ++j) {
1314 EVT VT = ValueVTs[j];
1316 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1317 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1319 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1320 MVT PartVT = TLI.getRegisterType(Context, VT);
1321 SmallVector<SDValue, 4> Parts(NumParts);
1322 getCopyToParts(DAG, getCurSDLoc(),
1323 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1324 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1326 // 'inreg' on function refers to return value
1327 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1331 // Propagate extension type if any
1332 if (ExtendKind == ISD::SIGN_EXTEND)
1334 else if (ExtendKind == ISD::ZERO_EXTEND)
1337 for (unsigned i = 0; i < NumParts; ++i) {
1338 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1339 VT, /*isfixed=*/true, 0, 0));
1340 OutVals.push_back(Parts[i]);
1346 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1347 CallingConv::ID CallConv =
1348 DAG.getMachineFunction().getFunction()->getCallingConv();
1349 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1350 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1352 // Verify that the target's LowerReturn behaved as expected.
1353 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1354 "LowerReturn didn't return a valid chain!");
1356 // Update the DAG with the new chain value resulting from return lowering.
1360 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1361 /// created for it, emit nodes to copy the value into the virtual
1363 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1365 if (V->getType()->isEmptyTy())
1368 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1369 if (VMI != FuncInfo.ValueMap.end()) {
1370 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1371 CopyValueToVirtualRegister(V, VMI->second);
1375 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1376 /// the current basic block, add it to ValueMap now so that we'll get a
1378 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1379 // No need to export constants.
1380 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1382 // Already exported?
1383 if (FuncInfo.isExportedInst(V)) return;
1385 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1386 CopyValueToVirtualRegister(V, Reg);
1389 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1390 const BasicBlock *FromBB) {
1391 // The operands of the setcc have to be in this block. We don't know
1392 // how to export them from some other block.
1393 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1394 // Can export from current BB.
1395 if (VI->getParent() == FromBB)
1398 // Is already exported, noop.
1399 return FuncInfo.isExportedInst(V);
1402 // If this is an argument, we can export it if the BB is the entry block or
1403 // if it is already exported.
1404 if (isa<Argument>(V)) {
1405 if (FromBB == &FromBB->getParent()->getEntryBlock())
1408 // Otherwise, can only export this if it is already exported.
1409 return FuncInfo.isExportedInst(V);
1412 // Otherwise, constants can always be exported.
1416 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1417 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1418 const MachineBasicBlock *Dst) const {
1419 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1422 const BasicBlock *SrcBB = Src->getBasicBlock();
1423 const BasicBlock *DstBB = Dst->getBasicBlock();
1424 return BPI->getEdgeWeight(SrcBB, DstBB);
1427 void SelectionDAGBuilder::
1428 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1429 uint32_t Weight /* = 0 */) {
1431 Weight = getEdgeWeight(Src, Dst);
1432 Src->addSuccessor(Dst, Weight);
1436 static bool InBlock(const Value *V, const BasicBlock *BB) {
1437 if (const Instruction *I = dyn_cast<Instruction>(V))
1438 return I->getParent() == BB;
1442 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1443 /// This function emits a branch and is used at the leaves of an OR or an
1444 /// AND operator tree.
1447 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1448 MachineBasicBlock *TBB,
1449 MachineBasicBlock *FBB,
1450 MachineBasicBlock *CurBB,
1451 MachineBasicBlock *SwitchBB,
1454 const BasicBlock *BB = CurBB->getBasicBlock();
1456 // If the leaf of the tree is a comparison, merge the condition into
1458 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1459 // The operands of the cmp have to be in this block. We don't know
1460 // how to export them from some other block. If this is the first block
1461 // of the sequence, no exporting is needed.
1462 if (CurBB == SwitchBB ||
1463 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1464 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1465 ISD::CondCode Condition;
1466 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1467 Condition = getICmpCondCode(IC->getPredicate());
1469 const FCmpInst *FC = cast<FCmpInst>(Cond);
1470 Condition = getFCmpCondCode(FC->getPredicate());
1471 if (TM.Options.NoNaNsFPMath)
1472 Condition = getFCmpCodeWithoutNaN(Condition);
1475 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1476 TBB, FBB, CurBB, TWeight, FWeight);
1477 SwitchCases.push_back(CB);
1482 // Create a CaseBlock record representing this branch.
1483 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1484 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1485 SwitchCases.push_back(CB);
1488 /// Scale down both weights to fit into uint32_t.
1489 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1490 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1491 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1492 NewTrue = NewTrue / Scale;
1493 NewFalse = NewFalse / Scale;
1496 /// FindMergedConditions - If Cond is an expression like
1497 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1498 MachineBasicBlock *TBB,
1499 MachineBasicBlock *FBB,
1500 MachineBasicBlock *CurBB,
1501 MachineBasicBlock *SwitchBB,
1502 Instruction::BinaryOps Opc,
1505 // If this node is not part of the or/and tree, emit it as a branch.
1506 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1507 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1508 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1509 BOp->getParent() != CurBB->getBasicBlock() ||
1510 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1511 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1512 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1517 // Create TmpBB after CurBB.
1518 MachineFunction::iterator BBI = CurBB;
1519 MachineFunction &MF = DAG.getMachineFunction();
1520 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1521 CurBB->getParent()->insert(++BBI, TmpBB);
1523 if (Opc == Instruction::Or) {
1524 // Codegen X | Y as:
1533 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1534 // The requirement is that
1535 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1536 // = TrueProb for original BB.
1537 // Assuming the original weights are A and B, one choice is to set BB1's
1538 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1540 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1541 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1542 // TmpBB, but the math is more complicated.
1544 uint64_t NewTrueWeight = TWeight;
1545 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1546 ScaleWeights(NewTrueWeight, NewFalseWeight);
1547 // Emit the LHS condition.
1548 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1549 NewTrueWeight, NewFalseWeight);
1551 NewTrueWeight = TWeight;
1552 NewFalseWeight = 2 * (uint64_t)FWeight;
1553 ScaleWeights(NewTrueWeight, NewFalseWeight);
1554 // Emit the RHS condition into TmpBB.
1555 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1556 NewTrueWeight, NewFalseWeight);
1558 assert(Opc == Instruction::And && "Unknown merge op!");
1559 // Codegen X & Y as:
1567 // This requires creation of TmpBB after CurBB.
1569 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1570 // The requirement is that
1571 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1572 // = FalseProb for original BB.
1573 // Assuming the original weights are A and B, one choice is to set BB1's
1574 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1576 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1578 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1579 uint64_t NewFalseWeight = FWeight;
1580 ScaleWeights(NewTrueWeight, NewFalseWeight);
1581 // Emit the LHS condition.
1582 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1583 NewTrueWeight, NewFalseWeight);
1585 NewTrueWeight = 2 * (uint64_t)TWeight;
1586 NewFalseWeight = FWeight;
1587 ScaleWeights(NewTrueWeight, NewFalseWeight);
1588 // Emit the RHS condition into TmpBB.
1589 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1590 NewTrueWeight, NewFalseWeight);
1594 /// If the set of cases should be emitted as a series of branches, return true.
1595 /// If we should emit this as a bunch of and/or'd together conditions, return
1598 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1599 if (Cases.size() != 2) return true;
1601 // If this is two comparisons of the same values or'd or and'd together, they
1602 // will get folded into a single comparison, so don't emit two blocks.
1603 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1604 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1605 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1606 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1610 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1611 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1612 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1613 Cases[0].CC == Cases[1].CC &&
1614 isa<Constant>(Cases[0].CmpRHS) &&
1615 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1616 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1618 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1625 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1626 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1628 // Update machine-CFG edges.
1629 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1631 if (I.isUnconditional()) {
1632 // Update machine-CFG edges.
1633 BrMBB->addSuccessor(Succ0MBB);
1635 // If this is not a fall-through branch or optimizations are switched off,
1637 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1638 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1639 MVT::Other, getControlRoot(),
1640 DAG.getBasicBlock(Succ0MBB)));
1645 // If this condition is one of the special cases we handle, do special stuff
1647 const Value *CondVal = I.getCondition();
1648 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1650 // If this is a series of conditions that are or'd or and'd together, emit
1651 // this as a sequence of branches instead of setcc's with and/or operations.
1652 // As long as jumps are not expensive, this should improve performance.
1653 // For example, instead of something like:
1666 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1667 Instruction::BinaryOps Opcode = BOp->getOpcode();
1668 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1669 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1670 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1671 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1672 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1673 getEdgeWeight(BrMBB, Succ1MBB));
1674 // If the compares in later blocks need to use values not currently
1675 // exported from this block, export them now. This block should always
1676 // be the first entry.
1677 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1679 // Allow some cases to be rejected.
1680 if (ShouldEmitAsBranches(SwitchCases)) {
1681 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1682 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1683 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1686 // Emit the branch for this block.
1687 visitSwitchCase(SwitchCases[0], BrMBB);
1688 SwitchCases.erase(SwitchCases.begin());
1692 // Okay, we decided not to do this, remove any inserted MBB's and clear
1694 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1695 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1697 SwitchCases.clear();
1701 // Create a CaseBlock record representing this branch.
1702 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1703 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1705 // Use visitSwitchCase to actually insert the fast branch sequence for this
1707 visitSwitchCase(CB, BrMBB);
1710 /// visitSwitchCase - Emits the necessary code to represent a single node in
1711 /// the binary search tree resulting from lowering a switch instruction.
1712 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1713 MachineBasicBlock *SwitchBB) {
1715 SDValue CondLHS = getValue(CB.CmpLHS);
1716 SDLoc dl = getCurSDLoc();
1718 // Build the setcc now.
1720 // Fold "(X == true)" to X and "(X == false)" to !X to
1721 // handle common cases produced by branch lowering.
1722 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1723 CB.CC == ISD::SETEQ)
1725 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1726 CB.CC == ISD::SETEQ) {
1727 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1728 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1730 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1732 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1734 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1735 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1737 SDValue CmpOp = getValue(CB.CmpMHS);
1738 EVT VT = CmpOp.getValueType();
1740 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1741 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1744 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1745 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1746 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1747 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1751 // Update successor info
1752 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1753 // TrueBB and FalseBB are always different unless the incoming IR is
1754 // degenerate. This only happens when running llc on weird IR.
1755 if (CB.TrueBB != CB.FalseBB)
1756 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1758 // If the lhs block is the next block, invert the condition so that we can
1759 // fall through to the lhs instead of the rhs block.
1760 if (CB.TrueBB == NextBlock(SwitchBB)) {
1761 std::swap(CB.TrueBB, CB.FalseBB);
1762 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1763 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1766 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1767 MVT::Other, getControlRoot(), Cond,
1768 DAG.getBasicBlock(CB.TrueBB));
1770 // Insert the false branch. Do this even if it's a fall through branch,
1771 // this makes it easier to do DAG optimizations which require inverting
1772 // the branch condition.
1773 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1774 DAG.getBasicBlock(CB.FalseBB));
1776 DAG.setRoot(BrCond);
1779 /// visitJumpTable - Emit JumpTable node in the current MBB
1780 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1781 // Emit the code for the jump table
1782 assert(JT.Reg != -1U && "Should lower JT Header first!");
1783 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1784 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1786 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1787 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1788 MVT::Other, Index.getValue(1),
1790 DAG.setRoot(BrJumpTable);
1793 /// visitJumpTableHeader - This function emits necessary code to produce index
1794 /// in the JumpTable from switch case.
1795 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1796 JumpTableHeader &JTH,
1797 MachineBasicBlock *SwitchBB) {
1798 SDLoc dl = getCurSDLoc();
1800 // Subtract the lowest switch case value from the value being switched on and
1801 // conditional branch to default mbb if the result is greater than the
1802 // difference between smallest and largest cases.
1803 SDValue SwitchOp = getValue(JTH.SValue);
1804 EVT VT = SwitchOp.getValueType();
1805 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1806 DAG.getConstant(JTH.First, dl, VT));
1808 // The SDNode we just created, which holds the value being switched on minus
1809 // the smallest case value, needs to be copied to a virtual register so it
1810 // can be used as an index into the jump table in a subsequent basic block.
1811 // This value may be smaller or larger than the target's pointer type, and
1812 // therefore require extension or truncating.
1813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1814 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1816 unsigned JumpTableReg =
1817 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1818 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1819 JumpTableReg, SwitchOp);
1820 JT.Reg = JumpTableReg;
1822 // Emit the range check for the jump table, and branch to the default block
1823 // for the switch statement if the value being switched on exceeds the largest
1824 // case in the switch.
1825 SDValue CMP = DAG.getSetCC(
1826 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1827 Sub.getValueType()),
1828 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1830 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1831 MVT::Other, CopyTo, CMP,
1832 DAG.getBasicBlock(JT.Default));
1834 // Avoid emitting unnecessary branches to the next block.
1835 if (JT.MBB != NextBlock(SwitchBB))
1836 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1837 DAG.getBasicBlock(JT.MBB));
1839 DAG.setRoot(BrCond);
1842 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1843 /// tail spliced into a stack protector check success bb.
1845 /// For a high level explanation of how this fits into the stack protector
1846 /// generation see the comment on the declaration of class
1847 /// StackProtectorDescriptor.
1848 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1849 MachineBasicBlock *ParentBB) {
1851 // First create the loads to the guard/stack slot for the comparison.
1852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1853 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1855 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1856 int FI = MFI->getStackProtectorIndex();
1858 const Value *IRGuard = SPD.getGuard();
1859 SDValue GuardPtr = getValue(IRGuard);
1860 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1862 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1865 SDLoc dl = getCurSDLoc();
1867 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1868 // guard value from the virtual register holding the value. Otherwise, emit a
1869 // volatile load to retrieve the stack guard value.
1870 unsigned GuardReg = SPD.getGuardReg();
1872 if (GuardReg && TLI.useLoadStackGuardNode())
1873 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1876 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1877 GuardPtr, MachinePointerInfo(IRGuard, 0),
1878 true, false, false, Align);
1880 SDValue StackSlot = DAG.getLoad(
1881 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1882 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1883 false, false, Align);
1885 // Perform the comparison via a subtract/getsetcc.
1886 EVT VT = Guard.getValueType();
1887 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1889 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1891 Sub.getValueType()),
1892 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1894 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1895 // branch to failure MBB.
1896 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1897 MVT::Other, StackSlot.getOperand(0),
1898 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1899 // Otherwise branch to success MBB.
1900 SDValue Br = DAG.getNode(ISD::BR, dl,
1902 DAG.getBasicBlock(SPD.getSuccessMBB()));
1907 /// Codegen the failure basic block for a stack protector check.
1909 /// A failure stack protector machine basic block consists simply of a call to
1910 /// __stack_chk_fail().
1912 /// For a high level explanation of how this fits into the stack protector
1913 /// generation see the comment on the declaration of class
1914 /// StackProtectorDescriptor.
1916 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1919 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1920 nullptr, 0, false, getCurSDLoc(), false, false).second;
1924 /// visitBitTestHeader - This function emits necessary code to produce value
1925 /// suitable for "bit tests"
1926 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1927 MachineBasicBlock *SwitchBB) {
1928 SDLoc dl = getCurSDLoc();
1930 // Subtract the minimum value
1931 SDValue SwitchOp = getValue(B.SValue);
1932 EVT VT = SwitchOp.getValueType();
1933 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1934 DAG.getConstant(B.First, dl, VT));
1937 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1938 SDValue RangeCmp = DAG.getSetCC(
1939 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1940 Sub.getValueType()),
1941 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1943 // Determine the type of the test operands.
1944 bool UsePtrType = false;
1945 if (!TLI.isTypeLegal(VT))
1948 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1949 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1950 // Switch table case range are encoded into series of masks.
1951 // Just use pointer type, it's guaranteed to fit.
1957 VT = TLI.getPointerTy(DAG.getDataLayout());
1958 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1961 B.RegVT = VT.getSimpleVT();
1962 B.Reg = FuncInfo.CreateReg(B.RegVT);
1963 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1965 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1967 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1968 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1970 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1971 MVT::Other, CopyTo, RangeCmp,
1972 DAG.getBasicBlock(B.Default));
1974 // Avoid emitting unnecessary branches to the next block.
1975 if (MBB != NextBlock(SwitchBB))
1976 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1977 DAG.getBasicBlock(MBB));
1979 DAG.setRoot(BrRange);
1982 /// visitBitTestCase - this function produces one "bit test"
1983 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1984 MachineBasicBlock* NextMBB,
1985 uint32_t BranchWeightToNext,
1988 MachineBasicBlock *SwitchBB) {
1989 SDLoc dl = getCurSDLoc();
1991 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1993 unsigned PopCount = countPopulation(B.Mask);
1994 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1995 if (PopCount == 1) {
1996 // Testing for a single bit; just compare the shift count with what it
1997 // would need to be to shift a 1 bit in that position.
1999 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2000 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2002 } else if (PopCount == BB.Range) {
2003 // There is only one zero bit in the range, test for it directly.
2005 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2006 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2009 // Make desired shift
2010 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2011 DAG.getConstant(1, dl, VT), ShiftOp);
2013 // Emit bit tests and jumps
2014 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2015 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2017 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2018 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2021 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2022 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2023 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2024 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2026 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2027 MVT::Other, getControlRoot(),
2028 Cmp, DAG.getBasicBlock(B.TargetBB));
2030 // Avoid emitting unnecessary branches to the next block.
2031 if (NextMBB != NextBlock(SwitchBB))
2032 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2033 DAG.getBasicBlock(NextMBB));
2038 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2039 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2041 // Retrieve successors. Look through artificial IR level blocks like catchpads
2042 // and catchendpads for successors.
2043 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2044 const BasicBlock *EHPadBB = I.getSuccessor(1);
2046 const Value *Callee(I.getCalledValue());
2047 const Function *Fn = dyn_cast<Function>(Callee);
2048 if (isa<InlineAsm>(Callee))
2050 else if (Fn && Fn->isIntrinsic()) {
2051 switch (Fn->getIntrinsicID()) {
2053 llvm_unreachable("Cannot invoke this intrinsic");
2054 case Intrinsic::donothing:
2055 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2057 case Intrinsic::experimental_patchpoint_void:
2058 case Intrinsic::experimental_patchpoint_i64:
2059 visitPatchpoint(&I, EHPadBB);
2061 case Intrinsic::experimental_gc_statepoint:
2062 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2066 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2068 // If the value of the invoke is used outside of its defining block, make it
2069 // available as a virtual register.
2070 // We already took care of the exported value for the statepoint instruction
2071 // during call to the LowerStatepoint.
2072 if (!isStatepoint(I)) {
2073 CopyToExportRegsIfNeeded(&I);
2076 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2077 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2079 // Update successor info.
2080 // FIXME: The weights for catchpads will be wrong.
2081 addSuccessorWithWeight(InvokeMBB, Return);
2082 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2083 UnwindDest->setIsEHPad();
2084 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2087 // Drop into normal successor.
2088 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2089 MVT::Other, getControlRoot(),
2090 DAG.getBasicBlock(Return)));
2093 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2094 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2097 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2098 assert(FuncInfo.MBB->isEHPad() &&
2099 "Call to landingpad not in landing pad!");
2101 MachineBasicBlock *MBB = FuncInfo.MBB;
2102 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2103 AddLandingPadInfo(LP, MMI, MBB);
2105 // If there aren't registers to copy the values into (e.g., during SjLj
2106 // exceptions), then don't bother to create these DAG nodes.
2107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2108 if (TLI.getExceptionPointerRegister() == 0 &&
2109 TLI.getExceptionSelectorRegister() == 0)
2112 SmallVector<EVT, 2> ValueVTs;
2113 SDLoc dl = getCurSDLoc();
2114 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2115 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2117 // Get the two live-in registers as SDValues. The physregs have already been
2118 // copied into virtual registers.
2120 if (FuncInfo.ExceptionPointerVirtReg) {
2121 Ops[0] = DAG.getZExtOrTrunc(
2122 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2123 FuncInfo.ExceptionPointerVirtReg,
2124 TLI.getPointerTy(DAG.getDataLayout())),
2127 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2129 Ops[1] = DAG.getZExtOrTrunc(
2130 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2131 FuncInfo.ExceptionSelectorVirtReg,
2132 TLI.getPointerTy(DAG.getDataLayout())),
2136 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2137 DAG.getVTList(ValueVTs), Ops);
2141 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2143 for (const CaseCluster &CC : Clusters)
2144 assert(CC.Low == CC.High && "Input clusters must be single-case");
2147 std::sort(Clusters.begin(), Clusters.end(),
2148 [](const CaseCluster &a, const CaseCluster &b) {
2149 return a.Low->getValue().slt(b.Low->getValue());
2152 // Merge adjacent clusters with the same destination.
2153 const unsigned N = Clusters.size();
2154 unsigned DstIndex = 0;
2155 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2156 CaseCluster &CC = Clusters[SrcIndex];
2157 const ConstantInt *CaseVal = CC.Low;
2158 MachineBasicBlock *Succ = CC.MBB;
2160 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2161 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2162 // If this case has the same successor and is a neighbour, merge it into
2163 // the previous cluster.
2164 Clusters[DstIndex - 1].High = CaseVal;
2165 Clusters[DstIndex - 1].Weight += CC.Weight;
2166 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2168 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2169 sizeof(Clusters[SrcIndex]));
2172 Clusters.resize(DstIndex);
2175 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2176 MachineBasicBlock *Last) {
2178 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2179 if (JTCases[i].first.HeaderBB == First)
2180 JTCases[i].first.HeaderBB = Last;
2182 // Update BitTestCases.
2183 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2184 if (BitTestCases[i].Parent == First)
2185 BitTestCases[i].Parent = Last;
2188 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2189 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2191 // Update machine-CFG edges with unique successors.
2192 SmallSet<BasicBlock*, 32> Done;
2193 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2194 BasicBlock *BB = I.getSuccessor(i);
2195 bool Inserted = Done.insert(BB).second;
2199 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2200 addSuccessorWithWeight(IndirectBrMBB, Succ);
2203 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2204 MVT::Other, getControlRoot(),
2205 getValue(I.getAddress())));
2208 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2209 if (DAG.getTarget().Options.TrapUnreachable)
2210 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2213 void SelectionDAGBuilder::visitFSub(const User &I) {
2214 // -0.0 - X --> fneg
2215 Type *Ty = I.getType();
2216 if (isa<Constant>(I.getOperand(0)) &&
2217 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2218 SDValue Op2 = getValue(I.getOperand(1));
2219 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2220 Op2.getValueType(), Op2));
2224 visitBinary(I, ISD::FSUB);
2227 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2228 SDValue Op1 = getValue(I.getOperand(0));
2229 SDValue Op2 = getValue(I.getOperand(1));
2236 if (const OverflowingBinaryOperator *OFBinOp =
2237 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2238 nuw = OFBinOp->hasNoUnsignedWrap();
2239 nsw = OFBinOp->hasNoSignedWrap();
2241 if (const PossiblyExactOperator *ExactOp =
2242 dyn_cast<const PossiblyExactOperator>(&I))
2243 exact = ExactOp->isExact();
2244 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2245 FMF = FPOp->getFastMathFlags();
2248 Flags.setExact(exact);
2249 Flags.setNoSignedWrap(nsw);
2250 Flags.setNoUnsignedWrap(nuw);
2251 if (EnableFMFInDAG) {
2252 Flags.setAllowReciprocal(FMF.allowReciprocal());
2253 Flags.setNoInfs(FMF.noInfs());
2254 Flags.setNoNaNs(FMF.noNaNs());
2255 Flags.setNoSignedZeros(FMF.noSignedZeros());
2256 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2258 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2260 setValue(&I, BinNodeValue);
2263 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2264 SDValue Op1 = getValue(I.getOperand(0));
2265 SDValue Op2 = getValue(I.getOperand(1));
2267 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2268 Op2.getValueType(), DAG.getDataLayout());
2270 // Coerce the shift amount to the right type if we can.
2271 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2272 unsigned ShiftSize = ShiftTy.getSizeInBits();
2273 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2274 SDLoc DL = getCurSDLoc();
2276 // If the operand is smaller than the shift count type, promote it.
2277 if (ShiftSize > Op2Size)
2278 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2280 // If the operand is larger than the shift count type but the shift
2281 // count type has enough bits to represent any shift value, truncate
2282 // it now. This is a common case and it exposes the truncate to
2283 // optimization early.
2284 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2285 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2286 // Otherwise we'll need to temporarily settle for some other convenient
2287 // type. Type legalization will make adjustments once the shiftee is split.
2289 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2296 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2298 if (const OverflowingBinaryOperator *OFBinOp =
2299 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2300 nuw = OFBinOp->hasNoUnsignedWrap();
2301 nsw = OFBinOp->hasNoSignedWrap();
2303 if (const PossiblyExactOperator *ExactOp =
2304 dyn_cast<const PossiblyExactOperator>(&I))
2305 exact = ExactOp->isExact();
2308 Flags.setExact(exact);
2309 Flags.setNoSignedWrap(nsw);
2310 Flags.setNoUnsignedWrap(nuw);
2311 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2316 void SelectionDAGBuilder::visitSDiv(const User &I) {
2317 SDValue Op1 = getValue(I.getOperand(0));
2318 SDValue Op2 = getValue(I.getOperand(1));
2321 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2322 cast<PossiblyExactOperator>(&I)->isExact());
2323 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2327 void SelectionDAGBuilder::visitICmp(const User &I) {
2328 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2329 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2330 predicate = IC->getPredicate();
2331 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2332 predicate = ICmpInst::Predicate(IC->getPredicate());
2333 SDValue Op1 = getValue(I.getOperand(0));
2334 SDValue Op2 = getValue(I.getOperand(1));
2335 ISD::CondCode Opcode = getICmpCondCode(predicate);
2337 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2339 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2342 void SelectionDAGBuilder::visitFCmp(const User &I) {
2343 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2344 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2345 predicate = FC->getPredicate();
2346 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2347 predicate = FCmpInst::Predicate(FC->getPredicate());
2348 SDValue Op1 = getValue(I.getOperand(0));
2349 SDValue Op2 = getValue(I.getOperand(1));
2350 ISD::CondCode Condition = getFCmpCondCode(predicate);
2352 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2353 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2354 // further optimization, but currently FMF is only applicable to binary nodes.
2355 if (TM.Options.NoNaNsFPMath)
2356 Condition = getFCmpCodeWithoutNaN(Condition);
2357 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2359 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2362 void SelectionDAGBuilder::visitSelect(const User &I) {
2363 SmallVector<EVT, 4> ValueVTs;
2364 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2366 unsigned NumValues = ValueVTs.size();
2367 if (NumValues == 0) return;
2369 SmallVector<SDValue, 4> Values(NumValues);
2370 SDValue Cond = getValue(I.getOperand(0));
2371 SDValue LHSVal = getValue(I.getOperand(1));
2372 SDValue RHSVal = getValue(I.getOperand(2));
2373 auto BaseOps = {Cond};
2374 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2375 ISD::VSELECT : ISD::SELECT;
2377 // Min/max matching is only viable if all output VTs are the same.
2378 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2379 EVT VT = ValueVTs[0];
2380 LLVMContext &Ctx = *DAG.getContext();
2381 auto &TLI = DAG.getTargetLoweringInfo();
2382 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2383 VT = TLI.getTypeToTransformTo(Ctx, VT);
2386 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2387 ISD::NodeType Opc = ISD::DELETED_NODE;
2388 switch (SPR.Flavor) {
2389 case SPF_UMAX: Opc = ISD::UMAX; break;
2390 case SPF_UMIN: Opc = ISD::UMIN; break;
2391 case SPF_SMAX: Opc = ISD::SMAX; break;
2392 case SPF_SMIN: Opc = ISD::SMIN; break;
2394 switch (SPR.NaNBehavior) {
2395 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2396 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2397 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2398 case SPNB_RETURNS_ANY:
2399 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2405 switch (SPR.NaNBehavior) {
2406 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2407 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2408 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2409 case SPNB_RETURNS_ANY:
2410 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2418 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2419 // If the underlying comparison instruction is used by any other instruction,
2420 // the consumed instructions won't be destroyed, so it is not profitable
2421 // to convert to a min/max.
2422 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2424 LHSVal = getValue(LHS);
2425 RHSVal = getValue(RHS);
2430 for (unsigned i = 0; i != NumValues; ++i) {
2431 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2432 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2433 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2434 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2435 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2439 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2440 DAG.getVTList(ValueVTs), Values));
2443 void SelectionDAGBuilder::visitTrunc(const User &I) {
2444 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2445 SDValue N = getValue(I.getOperand(0));
2446 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2448 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2451 void SelectionDAGBuilder::visitZExt(const User &I) {
2452 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2453 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2454 SDValue N = getValue(I.getOperand(0));
2455 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2457 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2460 void SelectionDAGBuilder::visitSExt(const User &I) {
2461 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2462 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2463 SDValue N = getValue(I.getOperand(0));
2464 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2466 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2469 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2470 // FPTrunc is never a no-op cast, no need to check
2471 SDValue N = getValue(I.getOperand(0));
2472 SDLoc dl = getCurSDLoc();
2473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2474 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2475 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2476 DAG.getTargetConstant(
2477 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2480 void SelectionDAGBuilder::visitFPExt(const User &I) {
2481 // FPExt is never a no-op cast, no need to check
2482 SDValue N = getValue(I.getOperand(0));
2483 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2485 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2488 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2489 // FPToUI is never a no-op cast, no need to check
2490 SDValue N = getValue(I.getOperand(0));
2491 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2493 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2496 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2497 // FPToSI is never a no-op cast, no need to check
2498 SDValue N = getValue(I.getOperand(0));
2499 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2501 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2504 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2505 // UIToFP is never a no-op cast, no need to check
2506 SDValue N = getValue(I.getOperand(0));
2507 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2509 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2512 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2513 // SIToFP is never a no-op cast, no need to check
2514 SDValue N = getValue(I.getOperand(0));
2515 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2517 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2520 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2521 // What to do depends on the size of the integer and the size of the pointer.
2522 // We can either truncate, zero extend, or no-op, accordingly.
2523 SDValue N = getValue(I.getOperand(0));
2524 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2526 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2529 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2530 // What to do depends on the size of the integer and the size of the pointer.
2531 // We can either truncate, zero extend, or no-op, accordingly.
2532 SDValue N = getValue(I.getOperand(0));
2533 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2535 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2538 void SelectionDAGBuilder::visitBitCast(const User &I) {
2539 SDValue N = getValue(I.getOperand(0));
2540 SDLoc dl = getCurSDLoc();
2541 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2544 // BitCast assures us that source and destination are the same size so this is
2545 // either a BITCAST or a no-op.
2546 if (DestVT != N.getValueType())
2547 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2548 DestVT, N)); // convert types.
2549 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2550 // might fold any kind of constant expression to an integer constant and that
2551 // is not what we are looking for. Only regcognize a bitcast of a genuine
2552 // constant integer as an opaque constant.
2553 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2554 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2557 setValue(&I, N); // noop cast.
2560 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2562 const Value *SV = I.getOperand(0);
2563 SDValue N = getValue(SV);
2564 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2566 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2567 unsigned DestAS = I.getType()->getPointerAddressSpace();
2569 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2570 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2575 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2576 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2577 SDValue InVec = getValue(I.getOperand(0));
2578 SDValue InVal = getValue(I.getOperand(1));
2579 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2580 TLI.getVectorIdxTy(DAG.getDataLayout()));
2581 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2582 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2583 InVec, InVal, InIdx));
2586 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2588 SDValue InVec = getValue(I.getOperand(0));
2589 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2590 TLI.getVectorIdxTy(DAG.getDataLayout()));
2591 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2592 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2596 // Utility for visitShuffleVector - Return true if every element in Mask,
2597 // beginning from position Pos and ending in Pos+Size, falls within the
2598 // specified sequential range [L, L+Pos). or is undef.
2599 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2600 unsigned Pos, unsigned Size, int Low) {
2601 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2602 if (Mask[i] >= 0 && Mask[i] != Low)
2607 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2608 SDValue Src1 = getValue(I.getOperand(0));
2609 SDValue Src2 = getValue(I.getOperand(1));
2611 SmallVector<int, 8> Mask;
2612 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2613 unsigned MaskNumElts = Mask.size();
2615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2616 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2617 EVT SrcVT = Src1.getValueType();
2618 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2620 if (SrcNumElts == MaskNumElts) {
2621 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2626 // Normalize the shuffle vector since mask and vector length don't match.
2627 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2628 // Mask is longer than the source vectors and is a multiple of the source
2629 // vectors. We can use concatenate vector to make the mask and vectors
2631 if (SrcNumElts*2 == MaskNumElts) {
2632 // First check for Src1 in low and Src2 in high
2633 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2634 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2635 // The shuffle is concatenating two vectors together.
2636 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2640 // Then check for Src2 in low and Src1 in high
2641 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2642 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2643 // The shuffle is concatenating two vectors together.
2644 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2650 // Pad both vectors with undefs to make them the same length as the mask.
2651 unsigned NumConcat = MaskNumElts / SrcNumElts;
2652 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2653 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2654 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2656 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2657 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2661 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2662 getCurSDLoc(), VT, MOps1);
2663 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2664 getCurSDLoc(), VT, MOps2);
2666 // Readjust mask for new input vector length.
2667 SmallVector<int, 8> MappedOps;
2668 for (unsigned i = 0; i != MaskNumElts; ++i) {
2670 if (Idx >= (int)SrcNumElts)
2671 Idx -= SrcNumElts - MaskNumElts;
2672 MappedOps.push_back(Idx);
2675 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2680 if (SrcNumElts > MaskNumElts) {
2681 // Analyze the access pattern of the vector to see if we can extract
2682 // two subvectors and do the shuffle. The analysis is done by calculating
2683 // the range of elements the mask access on both vectors.
2684 int MinRange[2] = { static_cast<int>(SrcNumElts),
2685 static_cast<int>(SrcNumElts)};
2686 int MaxRange[2] = {-1, -1};
2688 for (unsigned i = 0; i != MaskNumElts; ++i) {
2694 if (Idx >= (int)SrcNumElts) {
2698 if (Idx > MaxRange[Input])
2699 MaxRange[Input] = Idx;
2700 if (Idx < MinRange[Input])
2701 MinRange[Input] = Idx;
2704 // Check if the access is smaller than the vector size and can we find
2705 // a reasonable extract index.
2706 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2708 int StartIdx[2]; // StartIdx to extract from
2709 for (unsigned Input = 0; Input < 2; ++Input) {
2710 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2711 RangeUse[Input] = 0; // Unused
2712 StartIdx[Input] = 0;
2716 // Find a good start index that is a multiple of the mask length. Then
2717 // see if the rest of the elements are in range.
2718 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2719 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2720 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2721 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2724 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2725 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2728 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2729 // Extract appropriate subvector and generate a vector shuffle
2730 for (unsigned Input = 0; Input < 2; ++Input) {
2731 SDValue &Src = Input == 0 ? Src1 : Src2;
2732 if (RangeUse[Input] == 0)
2733 Src = DAG.getUNDEF(VT);
2735 SDLoc dl = getCurSDLoc();
2737 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2738 DAG.getConstant(StartIdx[Input], dl,
2739 TLI.getVectorIdxTy(DAG.getDataLayout())));
2743 // Calculate new mask.
2744 SmallVector<int, 8> MappedOps;
2745 for (unsigned i = 0; i != MaskNumElts; ++i) {
2748 if (Idx < (int)SrcNumElts)
2751 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2753 MappedOps.push_back(Idx);
2756 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2762 // We can't use either concat vectors or extract subvectors so fall back to
2763 // replacing the shuffle with extract and build vector.
2764 // to insert and build vector.
2765 EVT EltVT = VT.getVectorElementType();
2766 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2767 SDLoc dl = getCurSDLoc();
2768 SmallVector<SDValue,8> Ops;
2769 for (unsigned i = 0; i != MaskNumElts; ++i) {
2774 Res = DAG.getUNDEF(EltVT);
2776 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2777 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2779 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2780 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2786 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2789 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2790 const Value *Op0 = I.getOperand(0);
2791 const Value *Op1 = I.getOperand(1);
2792 Type *AggTy = I.getType();
2793 Type *ValTy = Op1->getType();
2794 bool IntoUndef = isa<UndefValue>(Op0);
2795 bool FromUndef = isa<UndefValue>(Op1);
2797 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2800 SmallVector<EVT, 4> AggValueVTs;
2801 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2802 SmallVector<EVT, 4> ValValueVTs;
2803 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2805 unsigned NumAggValues = AggValueVTs.size();
2806 unsigned NumValValues = ValValueVTs.size();
2807 SmallVector<SDValue, 4> Values(NumAggValues);
2809 // Ignore an insertvalue that produces an empty object
2810 if (!NumAggValues) {
2811 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2815 SDValue Agg = getValue(Op0);
2817 // Copy the beginning value(s) from the original aggregate.
2818 for (; i != LinearIndex; ++i)
2819 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2820 SDValue(Agg.getNode(), Agg.getResNo() + i);
2821 // Copy values from the inserted value(s).
2823 SDValue Val = getValue(Op1);
2824 for (; i != LinearIndex + NumValValues; ++i)
2825 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2826 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2828 // Copy remaining value(s) from the original aggregate.
2829 for (; i != NumAggValues; ++i)
2830 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2831 SDValue(Agg.getNode(), Agg.getResNo() + i);
2833 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2834 DAG.getVTList(AggValueVTs), Values));
2837 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2838 const Value *Op0 = I.getOperand(0);
2839 Type *AggTy = Op0->getType();
2840 Type *ValTy = I.getType();
2841 bool OutOfUndef = isa<UndefValue>(Op0);
2843 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2846 SmallVector<EVT, 4> ValValueVTs;
2847 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2849 unsigned NumValValues = ValValueVTs.size();
2851 // Ignore a extractvalue that produces an empty object
2852 if (!NumValValues) {
2853 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2857 SmallVector<SDValue, 4> Values(NumValValues);
2859 SDValue Agg = getValue(Op0);
2860 // Copy out the selected value(s).
2861 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2862 Values[i - LinearIndex] =
2864 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2865 SDValue(Agg.getNode(), Agg.getResNo() + i);
2867 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2868 DAG.getVTList(ValValueVTs), Values));
2871 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2872 Value *Op0 = I.getOperand(0);
2873 // Note that the pointer operand may be a vector of pointers. Take the scalar
2874 // element which holds a pointer.
2875 Type *Ty = Op0->getType()->getScalarType();
2876 unsigned AS = Ty->getPointerAddressSpace();
2877 SDValue N = getValue(Op0);
2878 SDLoc dl = getCurSDLoc();
2880 // Normalize Vector GEP - all scalar operands should be converted to the
2882 unsigned VectorWidth = I.getType()->isVectorTy() ?
2883 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2885 if (VectorWidth && !N.getValueType().isVector()) {
2886 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2887 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2888 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2890 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2892 const Value *Idx = *OI;
2893 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2894 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2897 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2898 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2899 DAG.getConstant(Offset, dl, N.getValueType()));
2902 Ty = StTy->getElementType(Field);
2904 Ty = cast<SequentialType>(Ty)->getElementType();
2906 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2907 unsigned PtrSize = PtrTy.getSizeInBits();
2908 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2910 // If this is a scalar constant or a splat vector of constants,
2911 // handle it quickly.
2912 const auto *CI = dyn_cast<ConstantInt>(Idx);
2913 if (!CI && isa<ConstantDataVector>(Idx) &&
2914 cast<ConstantDataVector>(Idx)->getSplatValue())
2915 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2920 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2921 SDValue OffsVal = VectorWidth ?
2922 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2923 DAG.getConstant(Offs, dl, PtrTy);
2924 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2928 // N = N + Idx * ElementSize;
2929 SDValue IdxN = getValue(Idx);
2931 if (!IdxN.getValueType().isVector() && VectorWidth) {
2932 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2933 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2934 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2936 // If the index is smaller or larger than intptr_t, truncate or extend
2938 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2940 // If this is a multiply by a power of two, turn it into a shl
2941 // immediately. This is a very common case.
2942 if (ElementSize != 1) {
2943 if (ElementSize.isPowerOf2()) {
2944 unsigned Amt = ElementSize.logBase2();
2945 IdxN = DAG.getNode(ISD::SHL, dl,
2946 N.getValueType(), IdxN,
2947 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2949 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2950 IdxN = DAG.getNode(ISD::MUL, dl,
2951 N.getValueType(), IdxN, Scale);
2955 N = DAG.getNode(ISD::ADD, dl,
2956 N.getValueType(), N, IdxN);
2963 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2964 // If this is a fixed sized alloca in the entry block of the function,
2965 // allocate it statically on the stack.
2966 if (FuncInfo.StaticAllocaMap.count(&I))
2967 return; // getValue will auto-populate this.
2969 SDLoc dl = getCurSDLoc();
2970 Type *Ty = I.getAllocatedType();
2971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2972 auto &DL = DAG.getDataLayout();
2973 uint64_t TySize = DL.getTypeAllocSize(Ty);
2975 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2977 SDValue AllocSize = getValue(I.getArraySize());
2979 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2980 if (AllocSize.getValueType() != IntPtr)
2981 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2983 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2985 DAG.getConstant(TySize, dl, IntPtr));
2987 // Handle alignment. If the requested alignment is less than or equal to
2988 // the stack alignment, ignore it. If the size is greater than or equal to
2989 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2990 unsigned StackAlign =
2991 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2992 if (Align <= StackAlign)
2995 // Round the size of the allocation up to the stack alignment size
2996 // by add SA-1 to the size.
2997 AllocSize = DAG.getNode(ISD::ADD, dl,
2998 AllocSize.getValueType(), AllocSize,
2999 DAG.getIntPtrConstant(StackAlign - 1, dl));
3001 // Mask out the low bits for alignment purposes.
3002 AllocSize = DAG.getNode(ISD::AND, dl,
3003 AllocSize.getValueType(), AllocSize,
3004 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3007 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3008 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3009 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3011 DAG.setRoot(DSA.getValue(1));
3013 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3016 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3018 return visitAtomicLoad(I);
3020 const Value *SV = I.getOperand(0);
3021 SDValue Ptr = getValue(SV);
3023 Type *Ty = I.getType();
3025 bool isVolatile = I.isVolatile();
3026 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3028 // The IR notion of invariant_load only guarantees that all *non-faulting*
3029 // invariant loads result in the same value. The MI notion of invariant load
3030 // guarantees that the load can be legally moved to any location within its
3031 // containing function. The MI notion of invariant_load is stronger than the
3032 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3033 // with a guarantee that the location being loaded from is dereferenceable
3034 // throughout the function's lifetime.
3036 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3037 isDereferenceablePointer(SV, DAG.getDataLayout());
3038 unsigned Alignment = I.getAlignment();
3041 I.getAAMetadata(AAInfo);
3042 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3045 SmallVector<EVT, 4> ValueVTs;
3046 SmallVector<uint64_t, 4> Offsets;
3047 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3048 unsigned NumValues = ValueVTs.size();
3053 bool ConstantMemory = false;
3054 if (isVolatile || NumValues > MaxParallelChains)
3055 // Serialize volatile loads with other side effects.
3057 else if (AA->pointsToConstantMemory(MemoryLocation(
3058 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3059 // Do not serialize (non-volatile) loads of constant memory with anything.
3060 Root = DAG.getEntryNode();
3061 ConstantMemory = true;
3063 // Do not serialize non-volatile loads against each other.
3064 Root = DAG.getRoot();
3067 SDLoc dl = getCurSDLoc();
3070 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3072 SmallVector<SDValue, 4> Values(NumValues);
3073 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3074 EVT PtrVT = Ptr.getValueType();
3075 unsigned ChainI = 0;
3076 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3077 // Serializing loads here may result in excessive register pressure, and
3078 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3079 // could recover a bit by hoisting nodes upward in the chain by recognizing
3080 // they are side-effect free or do not alias. The optimizer should really
3081 // avoid this case by converting large object/array copies to llvm.memcpy
3082 // (MaxParallelChains should always remain as failsafe).
3083 if (ChainI == MaxParallelChains) {
3084 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3085 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3086 makeArrayRef(Chains.data(), ChainI));
3090 SDValue A = DAG.getNode(ISD::ADD, dl,
3092 DAG.getConstant(Offsets[i], dl, PtrVT));
3093 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3094 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3095 isNonTemporal, isInvariant, Alignment, AAInfo,
3099 Chains[ChainI] = L.getValue(1);
3102 if (!ConstantMemory) {
3103 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3104 makeArrayRef(Chains.data(), ChainI));
3108 PendingLoads.push_back(Chain);
3111 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3112 DAG.getVTList(ValueVTs), Values));
3115 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3117 return visitAtomicStore(I);
3119 const Value *SrcV = I.getOperand(0);
3120 const Value *PtrV = I.getOperand(1);
3122 SmallVector<EVT, 4> ValueVTs;
3123 SmallVector<uint64_t, 4> Offsets;
3124 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3125 SrcV->getType(), ValueVTs, &Offsets);
3126 unsigned NumValues = ValueVTs.size();
3130 // Get the lowered operands. Note that we do this after
3131 // checking if NumResults is zero, because with zero results
3132 // the operands won't have values in the map.
3133 SDValue Src = getValue(SrcV);
3134 SDValue Ptr = getValue(PtrV);
3136 SDValue Root = getRoot();
3137 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3138 EVT PtrVT = Ptr.getValueType();
3139 bool isVolatile = I.isVolatile();
3140 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3141 unsigned Alignment = I.getAlignment();
3142 SDLoc dl = getCurSDLoc();
3145 I.getAAMetadata(AAInfo);
3147 unsigned ChainI = 0;
3148 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3149 // See visitLoad comments.
3150 if (ChainI == MaxParallelChains) {
3151 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3152 makeArrayRef(Chains.data(), ChainI));
3156 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3157 DAG.getConstant(Offsets[i], dl, PtrVT));
3158 SDValue St = DAG.getStore(Root, dl,
3159 SDValue(Src.getNode(), Src.getResNo() + i),
3160 Add, MachinePointerInfo(PtrV, Offsets[i]),
3161 isVolatile, isNonTemporal, Alignment, AAInfo);
3162 Chains[ChainI] = St;
3165 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3166 makeArrayRef(Chains.data(), ChainI));
3167 DAG.setRoot(StoreNode);
3170 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3171 SDLoc sdl = getCurSDLoc();
3173 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3174 Value *PtrOperand = I.getArgOperand(1);
3175 SDValue Ptr = getValue(PtrOperand);
3176 SDValue Src0 = getValue(I.getArgOperand(0));
3177 SDValue Mask = getValue(I.getArgOperand(3));
3178 EVT VT = Src0.getValueType();
3179 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3181 Alignment = DAG.getEVTAlignment(VT);
3184 I.getAAMetadata(AAInfo);
3186 MachineMemOperand *MMO =
3187 DAG.getMachineFunction().
3188 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3189 MachineMemOperand::MOStore, VT.getStoreSize(),
3191 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3193 DAG.setRoot(StoreNode);
3194 setValue(&I, StoreNode);
3197 // Get a uniform base for the Gather/Scatter intrinsic.
3198 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3199 // We try to represent it as a base pointer + vector of indices.
3200 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3201 // The first operand of the GEP may be a single pointer or a vector of pointers
3203 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3205 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3206 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3208 // When the first GEP operand is a single pointer - it is the uniform base we
3209 // are looking for. If first operand of the GEP is a splat vector - we
3210 // extract the spalt value and use it as a uniform base.
3211 // In all other cases the function returns 'false'.
3213 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3214 SelectionDAGBuilder* SDB) {
3216 SelectionDAG& DAG = SDB->DAG;
3217 LLVMContext &Context = *DAG.getContext();
3219 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3220 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3221 if (!GEP || GEP->getNumOperands() > 2)
3224 Value *GEPPtr = GEP->getPointerOperand();
3225 if (!GEPPtr->getType()->isVectorTy())
3227 else if (!(Ptr = getSplatValue(GEPPtr)))
3230 Value *IndexVal = GEP->getOperand(1);
3232 // The operands of the GEP may be defined in another basic block.
3233 // In this case we'll not find nodes for the operands.
3234 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3237 Base = SDB->getValue(Ptr);
3238 Index = SDB->getValue(IndexVal);
3240 // Suppress sign extension.
3241 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3242 if (SDB->findValue(Sext->getOperand(0))) {
3243 IndexVal = Sext->getOperand(0);
3244 Index = SDB->getValue(IndexVal);
3247 if (!Index.getValueType().isVector()) {
3248 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3249 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3250 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3251 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3256 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3257 SDLoc sdl = getCurSDLoc();
3259 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3260 Value *Ptr = I.getArgOperand(1);
3261 SDValue Src0 = getValue(I.getArgOperand(0));
3262 SDValue Mask = getValue(I.getArgOperand(3));
3263 EVT VT = Src0.getValueType();
3264 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3266 Alignment = DAG.getEVTAlignment(VT);
3267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3270 I.getAAMetadata(AAInfo);
3274 Value *BasePtr = Ptr;
3275 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3277 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3278 MachineMemOperand *MMO = DAG.getMachineFunction().
3279 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3280 MachineMemOperand::MOStore, VT.getStoreSize(),
3283 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3284 Index = getValue(Ptr);
3286 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3287 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3289 DAG.setRoot(Scatter);
3290 setValue(&I, Scatter);
3293 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3294 SDLoc sdl = getCurSDLoc();
3296 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3297 Value *PtrOperand = I.getArgOperand(0);
3298 SDValue Ptr = getValue(PtrOperand);
3299 SDValue Src0 = getValue(I.getArgOperand(3));
3300 SDValue Mask = getValue(I.getArgOperand(2));
3302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3303 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3304 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3306 Alignment = DAG.getEVTAlignment(VT);
3309 I.getAAMetadata(AAInfo);
3310 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3312 SDValue InChain = DAG.getRoot();
3313 if (AA->pointsToConstantMemory(MemoryLocation(
3314 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3316 // Do not serialize (non-volatile) loads of constant memory with anything.
3317 InChain = DAG.getEntryNode();
3320 MachineMemOperand *MMO =
3321 DAG.getMachineFunction().
3322 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3323 MachineMemOperand::MOLoad, VT.getStoreSize(),
3324 Alignment, AAInfo, Ranges);
3326 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3328 SDValue OutChain = Load.getValue(1);
3329 DAG.setRoot(OutChain);
3333 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3334 SDLoc sdl = getCurSDLoc();
3336 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3337 Value *Ptr = I.getArgOperand(0);
3338 SDValue Src0 = getValue(I.getArgOperand(3));
3339 SDValue Mask = getValue(I.getArgOperand(2));
3341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3342 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3343 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3345 Alignment = DAG.getEVTAlignment(VT);
3348 I.getAAMetadata(AAInfo);
3349 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3351 SDValue Root = DAG.getRoot();
3354 Value *BasePtr = Ptr;
3355 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3356 bool ConstantMemory = false;
3358 AA->pointsToConstantMemory(MemoryLocation(
3359 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3361 // Do not serialize (non-volatile) loads of constant memory with anything.
3362 Root = DAG.getEntryNode();
3363 ConstantMemory = true;
3366 MachineMemOperand *MMO =
3367 DAG.getMachineFunction().
3368 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3369 MachineMemOperand::MOLoad, VT.getStoreSize(),
3370 Alignment, AAInfo, Ranges);
3373 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3374 Index = getValue(Ptr);
3376 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3377 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3380 SDValue OutChain = Gather.getValue(1);
3381 if (!ConstantMemory)
3382 PendingLoads.push_back(OutChain);
3383 setValue(&I, Gather);
3386 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3387 SDLoc dl = getCurSDLoc();
3388 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3389 AtomicOrdering FailureOrder = I.getFailureOrdering();
3390 SynchronizationScope Scope = I.getSynchScope();
3392 SDValue InChain = getRoot();
3394 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3395 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3396 SDValue L = DAG.getAtomicCmpSwap(
3397 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3398 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3399 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3400 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3402 SDValue OutChain = L.getValue(2);
3405 DAG.setRoot(OutChain);
3408 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3409 SDLoc dl = getCurSDLoc();
3411 switch (I.getOperation()) {
3412 default: llvm_unreachable("Unknown atomicrmw operation");
3413 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3414 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3415 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3416 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3417 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3418 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3419 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3420 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3421 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3422 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3423 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3425 AtomicOrdering Order = I.getOrdering();
3426 SynchronizationScope Scope = I.getSynchScope();
3428 SDValue InChain = getRoot();
3431 DAG.getAtomic(NT, dl,
3432 getValue(I.getValOperand()).getSimpleValueType(),
3434 getValue(I.getPointerOperand()),
3435 getValue(I.getValOperand()),
3436 I.getPointerOperand(),
3437 /* Alignment=*/ 0, Order, Scope);
3439 SDValue OutChain = L.getValue(1);
3442 DAG.setRoot(OutChain);
3445 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3446 SDLoc dl = getCurSDLoc();
3447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3450 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3451 TLI.getPointerTy(DAG.getDataLayout()));
3452 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3453 TLI.getPointerTy(DAG.getDataLayout()));
3454 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3457 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3458 SDLoc dl = getCurSDLoc();
3459 AtomicOrdering Order = I.getOrdering();
3460 SynchronizationScope Scope = I.getSynchScope();
3462 SDValue InChain = getRoot();
3464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3465 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3467 if (I.getAlignment() < VT.getSizeInBits() / 8)
3468 report_fatal_error("Cannot generate unaligned atomic load");
3470 MachineMemOperand *MMO =
3471 DAG.getMachineFunction().
3472 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3473 MachineMemOperand::MOVolatile |
3474 MachineMemOperand::MOLoad,
3476 I.getAlignment() ? I.getAlignment() :
3477 DAG.getEVTAlignment(VT));
3479 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3481 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3482 getValue(I.getPointerOperand()), MMO,
3485 SDValue OutChain = L.getValue(1);
3488 DAG.setRoot(OutChain);
3491 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3492 SDLoc dl = getCurSDLoc();
3494 AtomicOrdering Order = I.getOrdering();
3495 SynchronizationScope Scope = I.getSynchScope();
3497 SDValue InChain = getRoot();
3499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3501 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3503 if (I.getAlignment() < VT.getSizeInBits() / 8)
3504 report_fatal_error("Cannot generate unaligned atomic store");
3507 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3509 getValue(I.getPointerOperand()),
3510 getValue(I.getValueOperand()),
3511 I.getPointerOperand(), I.getAlignment(),
3514 DAG.setRoot(OutChain);
3517 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3519 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3520 unsigned Intrinsic) {
3521 bool HasChain = !I.doesNotAccessMemory();
3522 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3524 // Build the operand list.
3525 SmallVector<SDValue, 8> Ops;
3526 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3528 // We don't need to serialize loads against other loads.
3529 Ops.push_back(DAG.getRoot());
3531 Ops.push_back(getRoot());
3535 // Info is set by getTgtMemInstrinsic
3536 TargetLowering::IntrinsicInfo Info;
3537 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3538 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3540 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3541 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3542 Info.opc == ISD::INTRINSIC_W_CHAIN)
3543 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3544 TLI.getPointerTy(DAG.getDataLayout())));
3546 // Add all operands of the call to the operand list.
3547 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3548 SDValue Op = getValue(I.getArgOperand(i));
3552 SmallVector<EVT, 4> ValueVTs;
3553 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3556 ValueVTs.push_back(MVT::Other);
3558 SDVTList VTs = DAG.getVTList(ValueVTs);
3562 if (IsTgtIntrinsic) {
3563 // This is target intrinsic that touches memory
3564 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3565 VTs, Ops, Info.memVT,
3566 MachinePointerInfo(Info.ptrVal, Info.offset),
3567 Info.align, Info.vol,
3568 Info.readMem, Info.writeMem, Info.size);
3569 } else if (!HasChain) {
3570 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3571 } else if (!I.getType()->isVoidTy()) {
3572 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3574 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3578 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3580 PendingLoads.push_back(Chain);
3585 if (!I.getType()->isVoidTy()) {
3586 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3587 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3588 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3591 setValue(&I, Result);
3595 /// GetSignificand - Get the significand and build it into a floating-point
3596 /// number with exponent of 1:
3598 /// Op = (Op & 0x007fffff) | 0x3f800000;
3600 /// where Op is the hexadecimal representation of floating point value.
3602 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3603 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3604 DAG.getConstant(0x007fffff, dl, MVT::i32));
3605 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3606 DAG.getConstant(0x3f800000, dl, MVT::i32));
3607 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3610 /// GetExponent - Get the exponent:
3612 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3614 /// where Op is the hexadecimal representation of floating point value.
3616 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3618 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3619 DAG.getConstant(0x7f800000, dl, MVT::i32));
3620 SDValue t1 = DAG.getNode(
3621 ISD::SRL, dl, MVT::i32, t0,
3622 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3623 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3624 DAG.getConstant(127, dl, MVT::i32));
3625 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3628 /// getF32Constant - Get 32-bit floating point constant.
3630 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3631 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3635 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3636 SelectionDAG &DAG) {
3637 // TODO: What fast-math-flags should be set on the floating-point nodes?
3639 // IntegerPartOfX = ((int32_t)(t0);
3640 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3642 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3643 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3644 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3646 // IntegerPartOfX <<= 23;
3647 IntegerPartOfX = DAG.getNode(
3648 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3649 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3650 DAG.getDataLayout())));
3652 SDValue TwoToFractionalPartOfX;
3653 if (LimitFloatPrecision <= 6) {
3654 // For floating-point precision of 6:
3656 // TwoToFractionalPartOfX =
3658 // (0.735607626f + 0.252464424f * x) * x;
3660 // error 0.0144103317, which is 6 bits
3661 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3662 getF32Constant(DAG, 0x3e814304, dl));
3663 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3664 getF32Constant(DAG, 0x3f3c50c8, dl));
3665 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3666 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3667 getF32Constant(DAG, 0x3f7f5e7e, dl));
3668 } else if (LimitFloatPrecision <= 12) {
3669 // For floating-point precision of 12:
3671 // TwoToFractionalPartOfX =
3674 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3676 // error 0.000107046256, which is 13 to 14 bits
3677 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3678 getF32Constant(DAG, 0x3da235e3, dl));
3679 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3680 getF32Constant(DAG, 0x3e65b8f3, dl));
3681 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3682 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3683 getF32Constant(DAG, 0x3f324b07, dl));
3684 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3685 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3686 getF32Constant(DAG, 0x3f7ff8fd, dl));
3687 } else { // LimitFloatPrecision <= 18
3688 // For floating-point precision of 18:
3690 // TwoToFractionalPartOfX =
3694 // (0.554906021e-1f +
3695 // (0.961591928e-2f +
3696 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3697 // error 2.47208000*10^(-7), which is better than 18 bits
3698 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3699 getF32Constant(DAG, 0x3924b03e, dl));
3700 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3701 getF32Constant(DAG, 0x3ab24b87, dl));
3702 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3703 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3704 getF32Constant(DAG, 0x3c1d8c17, dl));
3705 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3706 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3707 getF32Constant(DAG, 0x3d634a1d, dl));
3708 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3709 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3710 getF32Constant(DAG, 0x3e75fe14, dl));
3711 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3712 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3713 getF32Constant(DAG, 0x3f317234, dl));
3714 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3715 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3716 getF32Constant(DAG, 0x3f800000, dl));
3719 // Add the exponent into the result in integer domain.
3720 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3721 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3722 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3725 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3726 /// limited-precision mode.
3727 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3728 const TargetLowering &TLI) {
3729 if (Op.getValueType() == MVT::f32 &&
3730 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3732 // Put the exponent in the right bit position for later addition to the
3735 // #define LOG2OFe 1.4426950f
3736 // t0 = Op * LOG2OFe
3738 // TODO: What fast-math-flags should be set here?
3739 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3740 getF32Constant(DAG, 0x3fb8aa3b, dl));
3741 return getLimitedPrecisionExp2(t0, dl, DAG);
3744 // No special expansion.
3745 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3748 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3749 /// limited-precision mode.
3750 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3751 const TargetLowering &TLI) {
3753 // TODO: What fast-math-flags should be set on the floating-point nodes?
3755 if (Op.getValueType() == MVT::f32 &&
3756 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3757 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3759 // Scale the exponent by log(2) [0.69314718f].
3760 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3761 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3762 getF32Constant(DAG, 0x3f317218, dl));
3764 // Get the significand and build it into a floating-point number with
3766 SDValue X = GetSignificand(DAG, Op1, dl);
3768 SDValue LogOfMantissa;
3769 if (LimitFloatPrecision <= 6) {
3770 // For floating-point precision of 6:
3774 // (1.4034025f - 0.23903021f * x) * x;
3776 // error 0.0034276066, which is better than 8 bits
3777 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3778 getF32Constant(DAG, 0xbe74c456, dl));
3779 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3780 getF32Constant(DAG, 0x3fb3a2b1, dl));
3781 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3782 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3783 getF32Constant(DAG, 0x3f949a29, dl));
3784 } else if (LimitFloatPrecision <= 12) {
3785 // For floating-point precision of 12:
3791 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3793 // error 0.000061011436, which is 14 bits
3794 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3795 getF32Constant(DAG, 0xbd67b6d6, dl));
3796 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3797 getF32Constant(DAG, 0x3ee4f4b8, dl));
3798 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3799 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3800 getF32Constant(DAG, 0x3fbc278b, dl));
3801 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3802 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3803 getF32Constant(DAG, 0x40348e95, dl));
3804 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3805 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3806 getF32Constant(DAG, 0x3fdef31a, dl));
3807 } else { // LimitFloatPrecision <= 18
3808 // For floating-point precision of 18:
3816 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3818 // error 0.0000023660568, which is better than 18 bits
3819 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3820 getF32Constant(DAG, 0xbc91e5ac, dl));
3821 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3822 getF32Constant(DAG, 0x3e4350aa, dl));
3823 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3824 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3825 getF32Constant(DAG, 0x3f60d3e3, dl));
3826 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3827 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3828 getF32Constant(DAG, 0x4011cdf0, dl));
3829 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3830 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3831 getF32Constant(DAG, 0x406cfd1c, dl));
3832 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3833 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3834 getF32Constant(DAG, 0x408797cb, dl));
3835 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3836 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3837 getF32Constant(DAG, 0x4006dcab, dl));
3840 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3843 // No special expansion.
3844 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3847 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3848 /// limited-precision mode.
3849 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3850 const TargetLowering &TLI) {
3852 // TODO: What fast-math-flags should be set on the floating-point nodes?
3854 if (Op.getValueType() == MVT::f32 &&
3855 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3856 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3858 // Get the exponent.
3859 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3861 // Get the significand and build it into a floating-point number with
3863 SDValue X = GetSignificand(DAG, Op1, dl);
3865 // Different possible minimax approximations of significand in
3866 // floating-point for various degrees of accuracy over [1,2].
3867 SDValue Log2ofMantissa;
3868 if (LimitFloatPrecision <= 6) {
3869 // For floating-point precision of 6:
3871 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3873 // error 0.0049451742, which is more than 7 bits
3874 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3875 getF32Constant(DAG, 0xbeb08fe0, dl));
3876 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3877 getF32Constant(DAG, 0x40019463, dl));
3878 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3879 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3880 getF32Constant(DAG, 0x3fd6633d, dl));
3881 } else if (LimitFloatPrecision <= 12) {
3882 // For floating-point precision of 12:
3888 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3890 // error 0.0000876136000, which is better than 13 bits
3891 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3892 getF32Constant(DAG, 0xbda7262e, dl));
3893 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3894 getF32Constant(DAG, 0x3f25280b, dl));
3895 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3896 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3897 getF32Constant(DAG, 0x4007b923, dl));
3898 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3899 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3900 getF32Constant(DAG, 0x40823e2f, dl));
3901 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3902 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3903 getF32Constant(DAG, 0x4020d29c, dl));
3904 } else { // LimitFloatPrecision <= 18
3905 // For floating-point precision of 18:
3914 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3916 // error 0.0000018516, which is better than 18 bits
3917 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3918 getF32Constant(DAG, 0xbcd2769e, dl));
3919 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3920 getF32Constant(DAG, 0x3e8ce0b9, dl));
3921 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3922 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3923 getF32Constant(DAG, 0x3fa22ae7, dl));
3924 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3925 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3926 getF32Constant(DAG, 0x40525723, dl));
3927 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3928 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3929 getF32Constant(DAG, 0x40aaf200, dl));
3930 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3931 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3932 getF32Constant(DAG, 0x40c39dad, dl));
3933 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3934 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3935 getF32Constant(DAG, 0x4042902c, dl));
3938 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3941 // No special expansion.
3942 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3945 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3946 /// limited-precision mode.
3947 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3948 const TargetLowering &TLI) {
3950 // TODO: What fast-math-flags should be set on the floating-point nodes?
3952 if (Op.getValueType() == MVT::f32 &&
3953 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3954 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3956 // Scale the exponent by log10(2) [0.30102999f].
3957 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3958 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3959 getF32Constant(DAG, 0x3e9a209a, dl));
3961 // Get the significand and build it into a floating-point number with
3963 SDValue X = GetSignificand(DAG, Op1, dl);
3965 SDValue Log10ofMantissa;
3966 if (LimitFloatPrecision <= 6) {
3967 // For floating-point precision of 6:
3969 // Log10ofMantissa =
3971 // (0.60948995f - 0.10380950f * x) * x;
3973 // error 0.0014886165, which is 6 bits
3974 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3975 getF32Constant(DAG, 0xbdd49a13, dl));
3976 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3977 getF32Constant(DAG, 0x3f1c0789, dl));
3978 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3979 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3980 getF32Constant(DAG, 0x3f011300, dl));
3981 } else if (LimitFloatPrecision <= 12) {
3982 // For floating-point precision of 12:
3984 // Log10ofMantissa =
3987 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3989 // error 0.00019228036, which is better than 12 bits
3990 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3991 getF32Constant(DAG, 0x3d431f31, dl));
3992 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3993 getF32Constant(DAG, 0x3ea21fb2, dl));
3994 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3995 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3996 getF32Constant(DAG, 0x3f6ae232, dl));
3997 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3998 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3999 getF32Constant(DAG, 0x3f25f7c3, dl));
4000 } else { // LimitFloatPrecision <= 18
4001 // For floating-point precision of 18:
4003 // Log10ofMantissa =
4008 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4010 // error 0.0000037995730, which is better than 18 bits
4011 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4012 getF32Constant(DAG, 0x3c5d51ce, dl));
4013 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4014 getF32Constant(DAG, 0x3e00685a, dl));
4015 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4016 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4017 getF32Constant(DAG, 0x3efb6798, dl));
4018 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4019 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4020 getF32Constant(DAG, 0x3f88d192, dl));
4021 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4022 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4023 getF32Constant(DAG, 0x3fc4316c, dl));
4024 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4025 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4026 getF32Constant(DAG, 0x3f57ce70, dl));
4029 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4032 // No special expansion.
4033 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4036 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4037 /// limited-precision mode.
4038 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4039 const TargetLowering &TLI) {
4040 if (Op.getValueType() == MVT::f32 &&
4041 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4042 return getLimitedPrecisionExp2(Op, dl, DAG);
4044 // No special expansion.
4045 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4048 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4049 /// limited-precision mode with x == 10.0f.
4050 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4051 SelectionDAG &DAG, const TargetLowering &TLI) {
4052 bool IsExp10 = false;
4053 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4054 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4055 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4057 IsExp10 = LHSC->isExactlyValue(Ten);
4061 // TODO: What fast-math-flags should be set on the FMUL node?
4063 // Put the exponent in the right bit position for later addition to the
4066 // #define LOG2OF10 3.3219281f
4067 // t0 = Op * LOG2OF10;
4068 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4069 getF32Constant(DAG, 0x40549a78, dl));
4070 return getLimitedPrecisionExp2(t0, dl, DAG);
4073 // No special expansion.
4074 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4078 /// ExpandPowI - Expand a llvm.powi intrinsic.
4079 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4080 SelectionDAG &DAG) {
4081 // If RHS is a constant, we can expand this out to a multiplication tree,
4082 // otherwise we end up lowering to a call to __powidf2 (for example). When
4083 // optimizing for size, we only want to do this if the expansion would produce
4084 // a small number of multiplies, otherwise we do the full expansion.
4085 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4086 // Get the exponent as a positive value.
4087 unsigned Val = RHSC->getSExtValue();
4088 if ((int)Val < 0) Val = -Val;
4090 // powi(x, 0) -> 1.0
4092 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4094 const Function *F = DAG.getMachineFunction().getFunction();
4095 if (!F->optForSize() ||
4096 // If optimizing for size, don't insert too many multiplies.
4097 // This inserts up to 5 multiplies.
4098 countPopulation(Val) + Log2_32(Val) < 7) {
4099 // We use the simple binary decomposition method to generate the multiply
4100 // sequence. There are more optimal ways to do this (for example,
4101 // powi(x,15) generates one more multiply than it should), but this has
4102 // the benefit of being both really simple and much better than a libcall.
4103 SDValue Res; // Logically starts equal to 1.0
4104 SDValue CurSquare = LHS;
4105 // TODO: Intrinsics should have fast-math-flags that propagate to these
4110 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4112 Res = CurSquare; // 1.0*CurSquare.
4115 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4116 CurSquare, CurSquare);
4120 // If the original was negative, invert the result, producing 1/(x*x*x).
4121 if (RHSC->getSExtValue() < 0)
4122 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4123 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4128 // Otherwise, expand to a libcall.
4129 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4132 // getTruncatedArgReg - Find underlying register used for an truncated
4134 static unsigned getTruncatedArgReg(const SDValue &N) {
4135 if (N.getOpcode() != ISD::TRUNCATE)
4138 const SDValue &Ext = N.getOperand(0);
4139 if (Ext.getOpcode() == ISD::AssertZext ||
4140 Ext.getOpcode() == ISD::AssertSext) {
4141 const SDValue &CFR = Ext.getOperand(0);
4142 if (CFR.getOpcode() == ISD::CopyFromReg)
4143 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4144 if (CFR.getOpcode() == ISD::TRUNCATE)
4145 return getTruncatedArgReg(CFR);
4150 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4151 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4152 /// At the end of instruction selection, they will be inserted to the entry BB.
4153 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4154 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4155 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4156 const Argument *Arg = dyn_cast<Argument>(V);
4160 MachineFunction &MF = DAG.getMachineFunction();
4161 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4163 // Ignore inlined function arguments here.
4165 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4166 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4169 Optional<MachineOperand> Op;
4170 // Some arguments' frame index is recorded during argument lowering.
4171 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4172 Op = MachineOperand::CreateFI(FI);
4174 if (!Op && N.getNode()) {
4176 if (N.getOpcode() == ISD::CopyFromReg)
4177 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4179 Reg = getTruncatedArgReg(N);
4180 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4181 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4182 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4187 Op = MachineOperand::CreateReg(Reg, false);
4191 // Check if ValueMap has reg number.
4192 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4193 if (VMI != FuncInfo.ValueMap.end())
4194 Op = MachineOperand::CreateReg(VMI->second, false);
4197 if (!Op && N.getNode())
4198 // Check if frame index is available.
4199 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4200 if (FrameIndexSDNode *FINode =
4201 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4202 Op = MachineOperand::CreateFI(FINode->getIndex());
4207 assert(Variable->isValidLocationForIntrinsic(DL) &&
4208 "Expected inlined-at fields to agree");
4210 FuncInfo.ArgDbgValues.push_back(
4211 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4212 Op->getReg(), Offset, Variable, Expr));
4214 FuncInfo.ArgDbgValues.push_back(
4215 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4218 .addMetadata(Variable)
4219 .addMetadata(Expr));
4224 // VisualStudio defines setjmp as _setjmp
4225 #if defined(_MSC_VER) && defined(setjmp) && \
4226 !defined(setjmp_undefined_for_msvc)
4227 # pragma push_macro("setjmp")
4229 # define setjmp_undefined_for_msvc
4232 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4233 /// we want to emit this as a call to a named external function, return the name
4234 /// otherwise lower it and return null.
4236 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4238 SDLoc sdl = getCurSDLoc();
4239 DebugLoc dl = getCurDebugLoc();
4242 switch (Intrinsic) {
4244 // By default, turn this into a target intrinsic node.
4245 visitTargetIntrinsic(I, Intrinsic);
4247 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4248 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4249 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4250 case Intrinsic::returnaddress:
4251 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4252 TLI.getPointerTy(DAG.getDataLayout()),
4253 getValue(I.getArgOperand(0))));
4255 case Intrinsic::frameaddress:
4256 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4257 TLI.getPointerTy(DAG.getDataLayout()),
4258 getValue(I.getArgOperand(0))));
4260 case Intrinsic::read_register: {
4261 Value *Reg = I.getArgOperand(0);
4262 SDValue Chain = getRoot();
4264 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4265 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4266 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4267 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4269 DAG.setRoot(Res.getValue(1));
4272 case Intrinsic::write_register: {
4273 Value *Reg = I.getArgOperand(0);
4274 Value *RegValue = I.getArgOperand(1);
4275 SDValue Chain = getRoot();
4277 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4278 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4279 RegName, getValue(RegValue)));
4282 case Intrinsic::setjmp:
4283 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4284 case Intrinsic::longjmp:
4285 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4286 case Intrinsic::memcpy: {
4287 // FIXME: this definition of "user defined address space" is x86-specific
4288 // Assert for address < 256 since we support only user defined address
4290 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4292 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4294 "Unknown address space");
4295 SDValue Op1 = getValue(I.getArgOperand(0));
4296 SDValue Op2 = getValue(I.getArgOperand(1));
4297 SDValue Op3 = getValue(I.getArgOperand(2));
4298 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4300 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4301 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4302 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4303 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4305 MachinePointerInfo(I.getArgOperand(0)),
4306 MachinePointerInfo(I.getArgOperand(1)));
4307 updateDAGForMaybeTailCall(MC);
4310 case Intrinsic::memset: {
4311 // FIXME: this definition of "user defined address space" is x86-specific
4312 // Assert for address < 256 since we support only user defined address
4314 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4316 "Unknown address space");
4317 SDValue Op1 = getValue(I.getArgOperand(0));
4318 SDValue Op2 = getValue(I.getArgOperand(1));
4319 SDValue Op3 = getValue(I.getArgOperand(2));
4320 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4322 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4323 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4324 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4325 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4326 isTC, MachinePointerInfo(I.getArgOperand(0)));
4327 updateDAGForMaybeTailCall(MS);
4330 case Intrinsic::memmove: {
4331 // FIXME: this definition of "user defined address space" is x86-specific
4332 // Assert for address < 256 since we support only user defined address
4334 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4336 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4338 "Unknown address space");
4339 SDValue Op1 = getValue(I.getArgOperand(0));
4340 SDValue Op2 = getValue(I.getArgOperand(1));
4341 SDValue Op3 = getValue(I.getArgOperand(2));
4342 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4344 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4345 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4346 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4347 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4348 isTC, MachinePointerInfo(I.getArgOperand(0)),
4349 MachinePointerInfo(I.getArgOperand(1)));
4350 updateDAGForMaybeTailCall(MM);
4353 case Intrinsic::dbg_declare: {
4354 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4355 DILocalVariable *Variable = DI.getVariable();
4356 DIExpression *Expression = DI.getExpression();
4357 const Value *Address = DI.getAddress();
4358 assert(Variable && "Missing variable");
4360 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4364 // Check if address has undef value.
4365 if (isa<UndefValue>(Address) ||
4366 (Address->use_empty() && !isa<Argument>(Address))) {
4367 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4371 SDValue &N = NodeMap[Address];
4372 if (!N.getNode() && isa<Argument>(Address))
4373 // Check unused arguments map.
4374 N = UnusedArgNodeMap[Address];
4377 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4378 Address = BCI->getOperand(0);
4379 // Parameters are handled specially.
4380 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4382 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4384 if (isParameter && !AI) {
4385 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4387 // Byval parameter. We have a frame index at this point.
4388 SDV = DAG.getFrameIndexDbgValue(
4389 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4391 // Address is an argument, so try to emit its dbg value using
4392 // virtual register info from the FuncInfo.ValueMap.
4393 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4398 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4399 true, 0, dl, SDNodeOrder);
4401 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4403 // If Address is an argument then try to emit its dbg value using
4404 // virtual register info from the FuncInfo.ValueMap.
4405 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4407 // If variable is pinned by a alloca in dominating bb then
4408 // use StaticAllocaMap.
4409 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4410 if (AI->getParent() != DI.getParent()) {
4411 DenseMap<const AllocaInst*, int>::iterator SI =
4412 FuncInfo.StaticAllocaMap.find(AI);
4413 if (SI != FuncInfo.StaticAllocaMap.end()) {
4414 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4415 0, dl, SDNodeOrder);
4416 DAG.AddDbgValue(SDV, nullptr, false);
4421 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4426 case Intrinsic::dbg_value: {
4427 const DbgValueInst &DI = cast<DbgValueInst>(I);
4428 assert(DI.getVariable() && "Missing variable");
4430 DILocalVariable *Variable = DI.getVariable();
4431 DIExpression *Expression = DI.getExpression();
4432 uint64_t Offset = DI.getOffset();
4433 const Value *V = DI.getValue();
4438 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4439 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4441 DAG.AddDbgValue(SDV, nullptr, false);
4443 // Do not use getValue() in here; we don't want to generate code at
4444 // this point if it hasn't been done yet.
4445 SDValue N = NodeMap[V];
4446 if (!N.getNode() && isa<Argument>(V))
4447 // Check unused arguments map.
4448 N = UnusedArgNodeMap[V];
4450 // A dbg.value for an alloca is always indirect.
4451 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4452 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4454 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4455 IsIndirect, Offset, dl, SDNodeOrder);
4456 DAG.AddDbgValue(SDV, N.getNode(), false);
4458 } else if (!V->use_empty() ) {
4459 // Do not call getValue(V) yet, as we don't want to generate code.
4460 // Remember it for later.
4461 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4462 DanglingDebugInfoMap[V] = DDI;
4464 // We may expand this to cover more cases. One case where we have no
4465 // data available is an unreferenced parameter.
4466 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4470 // Build a debug info table entry.
4471 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4472 V = BCI->getOperand(0);
4473 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4474 // Don't handle byval struct arguments or VLAs, for example.
4476 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4477 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4480 DenseMap<const AllocaInst*, int>::iterator SI =
4481 FuncInfo.StaticAllocaMap.find(AI);
4482 if (SI == FuncInfo.StaticAllocaMap.end())
4483 return nullptr; // VLAs.
4487 case Intrinsic::eh_typeid_for: {
4488 // Find the type id for the given typeinfo.
4489 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4490 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4491 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4496 case Intrinsic::eh_return_i32:
4497 case Intrinsic::eh_return_i64:
4498 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4499 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4502 getValue(I.getArgOperand(0)),
4503 getValue(I.getArgOperand(1))));
4505 case Intrinsic::eh_unwind_init:
4506 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4508 case Intrinsic::eh_dwarf_cfa: {
4509 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4510 TLI.getPointerTy(DAG.getDataLayout()));
4511 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4512 CfaArg.getValueType(),
4513 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4514 CfaArg.getValueType()),
4516 SDValue FA = DAG.getNode(
4517 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4518 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4519 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4523 case Intrinsic::eh_sjlj_callsite: {
4524 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4525 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4526 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4527 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4529 MMI.setCurrentCallSite(CI->getZExtValue());
4532 case Intrinsic::eh_sjlj_functioncontext: {
4533 // Get and store the index of the function context.
4534 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4536 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4537 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4538 MFI->setFunctionContextIndex(FI);
4541 case Intrinsic::eh_sjlj_setjmp: {
4544 Ops[1] = getValue(I.getArgOperand(0));
4545 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4546 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4547 setValue(&I, Op.getValue(0));
4548 DAG.setRoot(Op.getValue(1));
4551 case Intrinsic::eh_sjlj_longjmp: {
4552 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4553 getRoot(), getValue(I.getArgOperand(0))));
4556 case Intrinsic::eh_sjlj_setup_dispatch: {
4557 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4562 case Intrinsic::masked_gather:
4563 visitMaskedGather(I);
4565 case Intrinsic::masked_load:
4568 case Intrinsic::masked_scatter:
4569 visitMaskedScatter(I);
4571 case Intrinsic::masked_store:
4572 visitMaskedStore(I);
4574 case Intrinsic::x86_mmx_pslli_w:
4575 case Intrinsic::x86_mmx_pslli_d:
4576 case Intrinsic::x86_mmx_pslli_q:
4577 case Intrinsic::x86_mmx_psrli_w:
4578 case Intrinsic::x86_mmx_psrli_d:
4579 case Intrinsic::x86_mmx_psrli_q:
4580 case Intrinsic::x86_mmx_psrai_w:
4581 case Intrinsic::x86_mmx_psrai_d: {
4582 SDValue ShAmt = getValue(I.getArgOperand(1));
4583 if (isa<ConstantSDNode>(ShAmt)) {
4584 visitTargetIntrinsic(I, Intrinsic);
4587 unsigned NewIntrinsic = 0;
4588 EVT ShAmtVT = MVT::v2i32;
4589 switch (Intrinsic) {
4590 case Intrinsic::x86_mmx_pslli_w:
4591 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4593 case Intrinsic::x86_mmx_pslli_d:
4594 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4596 case Intrinsic::x86_mmx_pslli_q:
4597 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4599 case Intrinsic::x86_mmx_psrli_w:
4600 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4602 case Intrinsic::x86_mmx_psrli_d:
4603 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4605 case Intrinsic::x86_mmx_psrli_q:
4606 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4608 case Intrinsic::x86_mmx_psrai_w:
4609 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4611 case Intrinsic::x86_mmx_psrai_d:
4612 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4614 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4617 // The vector shift intrinsics with scalars uses 32b shift amounts but
4618 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4620 // We must do this early because v2i32 is not a legal type.
4623 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4624 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4625 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4626 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4627 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4628 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4629 getValue(I.getArgOperand(0)), ShAmt);
4633 case Intrinsic::convertff:
4634 case Intrinsic::convertfsi:
4635 case Intrinsic::convertfui:
4636 case Intrinsic::convertsif:
4637 case Intrinsic::convertuif:
4638 case Intrinsic::convertss:
4639 case Intrinsic::convertsu:
4640 case Intrinsic::convertus:
4641 case Intrinsic::convertuu: {
4642 ISD::CvtCode Code = ISD::CVT_INVALID;
4643 switch (Intrinsic) {
4644 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4645 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4646 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4647 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4648 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4649 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4650 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4651 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4652 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4653 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4655 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4656 const Value *Op1 = I.getArgOperand(0);
4657 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4658 DAG.getValueType(DestVT),
4659 DAG.getValueType(getValue(Op1).getValueType()),
4660 getValue(I.getArgOperand(1)),
4661 getValue(I.getArgOperand(2)),
4666 case Intrinsic::powi:
4667 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4668 getValue(I.getArgOperand(1)), DAG));
4670 case Intrinsic::log:
4671 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4673 case Intrinsic::log2:
4674 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4676 case Intrinsic::log10:
4677 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4679 case Intrinsic::exp:
4680 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4682 case Intrinsic::exp2:
4683 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4685 case Intrinsic::pow:
4686 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4687 getValue(I.getArgOperand(1)), DAG, TLI));
4689 case Intrinsic::sqrt:
4690 case Intrinsic::fabs:
4691 case Intrinsic::sin:
4692 case Intrinsic::cos:
4693 case Intrinsic::floor:
4694 case Intrinsic::ceil:
4695 case Intrinsic::trunc:
4696 case Intrinsic::rint:
4697 case Intrinsic::nearbyint:
4698 case Intrinsic::round: {
4700 switch (Intrinsic) {
4701 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4702 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4703 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4704 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4705 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4706 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4707 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4708 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4709 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4710 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4711 case Intrinsic::round: Opcode = ISD::FROUND; break;
4714 setValue(&I, DAG.getNode(Opcode, sdl,
4715 getValue(I.getArgOperand(0)).getValueType(),
4716 getValue(I.getArgOperand(0))));
4719 case Intrinsic::minnum:
4720 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4721 getValue(I.getArgOperand(0)).getValueType(),
4722 getValue(I.getArgOperand(0)),
4723 getValue(I.getArgOperand(1))));
4725 case Intrinsic::maxnum:
4726 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4727 getValue(I.getArgOperand(0)).getValueType(),
4728 getValue(I.getArgOperand(0)),
4729 getValue(I.getArgOperand(1))));
4731 case Intrinsic::copysign:
4732 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4733 getValue(I.getArgOperand(0)).getValueType(),
4734 getValue(I.getArgOperand(0)),
4735 getValue(I.getArgOperand(1))));
4737 case Intrinsic::fma:
4738 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4739 getValue(I.getArgOperand(0)).getValueType(),
4740 getValue(I.getArgOperand(0)),
4741 getValue(I.getArgOperand(1)),
4742 getValue(I.getArgOperand(2))));
4744 case Intrinsic::fmuladd: {
4745 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4746 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4747 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4748 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4749 getValue(I.getArgOperand(0)).getValueType(),
4750 getValue(I.getArgOperand(0)),
4751 getValue(I.getArgOperand(1)),
4752 getValue(I.getArgOperand(2))));
4754 // TODO: Intrinsic calls should have fast-math-flags.
4755 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4756 getValue(I.getArgOperand(0)).getValueType(),
4757 getValue(I.getArgOperand(0)),
4758 getValue(I.getArgOperand(1)));
4759 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4760 getValue(I.getArgOperand(0)).getValueType(),
4762 getValue(I.getArgOperand(2)));
4767 case Intrinsic::convert_to_fp16:
4768 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4769 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4770 getValue(I.getArgOperand(0)),
4771 DAG.getTargetConstant(0, sdl,
4774 case Intrinsic::convert_from_fp16:
4775 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4776 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4777 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4778 getValue(I.getArgOperand(0)))));
4780 case Intrinsic::pcmarker: {
4781 SDValue Tmp = getValue(I.getArgOperand(0));
4782 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4785 case Intrinsic::readcyclecounter: {
4786 SDValue Op = getRoot();
4787 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4788 DAG.getVTList(MVT::i64, MVT::Other), Op);
4790 DAG.setRoot(Res.getValue(1));
4793 case Intrinsic::bswap:
4794 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4795 getValue(I.getArgOperand(0)).getValueType(),
4796 getValue(I.getArgOperand(0))));
4798 case Intrinsic::uabsdiff:
4799 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4800 getValue(I.getArgOperand(0)).getValueType(),
4801 getValue(I.getArgOperand(0)),
4802 getValue(I.getArgOperand(1))));
4804 case Intrinsic::sabsdiff:
4805 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4806 getValue(I.getArgOperand(0)).getValueType(),
4807 getValue(I.getArgOperand(0)),
4808 getValue(I.getArgOperand(1))));
4810 case Intrinsic::cttz: {
4811 SDValue Arg = getValue(I.getArgOperand(0));
4812 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4813 EVT Ty = Arg.getValueType();
4814 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4818 case Intrinsic::ctlz: {
4819 SDValue Arg = getValue(I.getArgOperand(0));
4820 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4821 EVT Ty = Arg.getValueType();
4822 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4826 case Intrinsic::ctpop: {
4827 SDValue Arg = getValue(I.getArgOperand(0));
4828 EVT Ty = Arg.getValueType();
4829 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4832 case Intrinsic::stacksave: {
4833 SDValue Op = getRoot();
4835 ISD::STACKSAVE, sdl,
4836 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4838 DAG.setRoot(Res.getValue(1));
4841 case Intrinsic::stackrestore: {
4842 Res = getValue(I.getArgOperand(0));
4843 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4846 case Intrinsic::stackprotector: {
4847 // Emit code into the DAG to store the stack guard onto the stack.
4848 MachineFunction &MF = DAG.getMachineFunction();
4849 MachineFrameInfo *MFI = MF.getFrameInfo();
4850 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4851 SDValue Src, Chain = getRoot();
4852 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4853 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4855 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4856 // global variable __stack_chk_guard.
4858 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4859 if (BC->getOpcode() == Instruction::BitCast)
4860 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4862 if (GV && TLI.useLoadStackGuardNode()) {
4863 // Emit a LOAD_STACK_GUARD node.
4864 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4866 MachinePointerInfo MPInfo(GV);
4867 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4868 unsigned Flags = MachineMemOperand::MOLoad |
4869 MachineMemOperand::MOInvariant;
4870 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4871 PtrTy.getSizeInBits() / 8,
4872 DAG.getEVTAlignment(PtrTy));
4873 Node->setMemRefs(MemRefs, MemRefs + 1);
4875 // Copy the guard value to a virtual register so that it can be
4876 // retrieved in the epilogue.
4877 Src = SDValue(Node, 0);
4878 const TargetRegisterClass *RC =
4879 TLI.getRegClassFor(Src.getSimpleValueType());
4880 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4882 SPDescriptor.setGuardReg(Reg);
4883 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4885 Src = getValue(I.getArgOperand(0)); // The guard's value.
4888 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4890 int FI = FuncInfo.StaticAllocaMap[Slot];
4891 MFI->setStackProtectorIndex(FI);
4893 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4895 // Store the stack protector onto the stack.
4896 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4897 DAG.getMachineFunction(), FI),
4903 case Intrinsic::objectsize: {
4904 // If we don't know by now, we're never going to know.
4905 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4907 assert(CI && "Non-constant type in __builtin_object_size?");
4909 SDValue Arg = getValue(I.getCalledValue());
4910 EVT Ty = Arg.getValueType();
4913 Res = DAG.getConstant(-1ULL, sdl, Ty);
4915 Res = DAG.getConstant(0, sdl, Ty);
4920 case Intrinsic::annotation:
4921 case Intrinsic::ptr_annotation:
4922 // Drop the intrinsic, but forward the value
4923 setValue(&I, getValue(I.getOperand(0)));
4925 case Intrinsic::assume:
4926 case Intrinsic::var_annotation:
4927 // Discard annotate attributes and assumptions
4930 case Intrinsic::init_trampoline: {
4931 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4935 Ops[1] = getValue(I.getArgOperand(0));
4936 Ops[2] = getValue(I.getArgOperand(1));
4937 Ops[3] = getValue(I.getArgOperand(2));
4938 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4939 Ops[5] = DAG.getSrcValue(F);
4941 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4946 case Intrinsic::adjust_trampoline: {
4947 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4948 TLI.getPointerTy(DAG.getDataLayout()),
4949 getValue(I.getArgOperand(0))));
4952 case Intrinsic::gcroot:
4954 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4955 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4957 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4958 GFI->addStackRoot(FI->getIndex(), TypeMap);
4961 case Intrinsic::gcread:
4962 case Intrinsic::gcwrite:
4963 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4964 case Intrinsic::flt_rounds:
4965 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4968 case Intrinsic::expect: {
4969 // Just replace __builtin_expect(exp, c) with EXP.
4970 setValue(&I, getValue(I.getArgOperand(0)));
4974 case Intrinsic::debugtrap:
4975 case Intrinsic::trap: {
4976 StringRef TrapFuncName =
4978 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4979 .getValueAsString();
4980 if (TrapFuncName.empty()) {
4981 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4982 ISD::TRAP : ISD::DEBUGTRAP;
4983 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4986 TargetLowering::ArgListTy Args;
4988 TargetLowering::CallLoweringInfo CLI(DAG);
4989 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4990 CallingConv::C, I.getType(),
4991 DAG.getExternalSymbol(TrapFuncName.data(),
4992 TLI.getPointerTy(DAG.getDataLayout())),
4993 std::move(Args), 0);
4995 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4996 DAG.setRoot(Result.second);
5000 case Intrinsic::uadd_with_overflow:
5001 case Intrinsic::sadd_with_overflow:
5002 case Intrinsic::usub_with_overflow:
5003 case Intrinsic::ssub_with_overflow:
5004 case Intrinsic::umul_with_overflow:
5005 case Intrinsic::smul_with_overflow: {
5007 switch (Intrinsic) {
5008 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5009 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5010 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5011 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5012 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5013 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5014 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5016 SDValue Op1 = getValue(I.getArgOperand(0));
5017 SDValue Op2 = getValue(I.getArgOperand(1));
5019 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5020 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5023 case Intrinsic::prefetch: {
5025 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5027 Ops[1] = getValue(I.getArgOperand(0));
5028 Ops[2] = getValue(I.getArgOperand(1));
5029 Ops[3] = getValue(I.getArgOperand(2));
5030 Ops[4] = getValue(I.getArgOperand(3));
5031 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5032 DAG.getVTList(MVT::Other), Ops,
5033 EVT::getIntegerVT(*Context, 8),
5034 MachinePointerInfo(I.getArgOperand(0)),
5036 false, /* volatile */
5038 rw==1)); /* write */
5041 case Intrinsic::lifetime_start:
5042 case Intrinsic::lifetime_end: {
5043 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5044 // Stack coloring is not enabled in O0, discard region information.
5045 if (TM.getOptLevel() == CodeGenOpt::None)
5048 SmallVector<Value *, 4> Allocas;
5049 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5051 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5052 E = Allocas.end(); Object != E; ++Object) {
5053 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5055 // Could not find an Alloca.
5056 if (!LifetimeObject)
5059 // First check that the Alloca is static, otherwise it won't have a
5060 // valid frame index.
5061 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5062 if (SI == FuncInfo.StaticAllocaMap.end())
5065 int FI = SI->second;
5070 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5071 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5073 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5078 case Intrinsic::invariant_start:
5079 // Discard region information.
5080 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5082 case Intrinsic::invariant_end:
5083 // Discard region information.
5085 case Intrinsic::stackprotectorcheck: {
5086 // Do not actually emit anything for this basic block. Instead we initialize
5087 // the stack protector descriptor and export the guard variable so we can
5088 // access it in FinishBasicBlock.
5089 const BasicBlock *BB = I.getParent();
5090 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5091 ExportFromCurrentBlock(SPDescriptor.getGuard());
5093 // Flush our exports since we are going to process a terminator.
5094 (void)getControlRoot();
5097 case Intrinsic::clear_cache:
5098 return TLI.getClearCacheBuiltinName();
5099 case Intrinsic::eh_actions:
5100 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5102 case Intrinsic::donothing:
5105 case Intrinsic::experimental_stackmap: {
5109 case Intrinsic::experimental_patchpoint_void:
5110 case Intrinsic::experimental_patchpoint_i64: {
5111 visitPatchpoint(&I);
5114 case Intrinsic::experimental_gc_statepoint: {
5118 case Intrinsic::experimental_gc_result_int:
5119 case Intrinsic::experimental_gc_result_float:
5120 case Intrinsic::experimental_gc_result_ptr:
5121 case Intrinsic::experimental_gc_result: {
5125 case Intrinsic::experimental_gc_relocate: {
5129 case Intrinsic::instrprof_increment:
5130 llvm_unreachable("instrprof failed to lower an increment");
5132 case Intrinsic::localescape: {
5133 MachineFunction &MF = DAG.getMachineFunction();
5134 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5136 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5137 // is the same on all targets.
5138 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5139 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5140 if (isa<ConstantPointerNull>(Arg))
5141 continue; // Skip null pointers. They represent a hole in index space.
5142 AllocaInst *Slot = cast<AllocaInst>(Arg);
5143 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5144 "can only escape static allocas");
5145 int FI = FuncInfo.StaticAllocaMap[Slot];
5146 MCSymbol *FrameAllocSym =
5147 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5148 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5149 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5150 TII->get(TargetOpcode::LOCAL_ESCAPE))
5151 .addSym(FrameAllocSym)
5158 case Intrinsic::localrecover: {
5159 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5160 MachineFunction &MF = DAG.getMachineFunction();
5161 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5163 // Get the symbol that defines the frame offset.
5164 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5165 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5166 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5167 MCSymbol *FrameAllocSym =
5168 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5169 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5171 // Create a MCSymbol for the label to avoid any target lowering
5172 // that would make this PC relative.
5173 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5175 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5177 // Add the offset to the FP.
5178 Value *FP = I.getArgOperand(1);
5179 SDValue FPVal = getValue(FP);
5180 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5185 case Intrinsic::eh_begincatch:
5186 case Intrinsic::eh_endcatch:
5187 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5188 case Intrinsic::eh_exceptioncode: {
5189 unsigned Reg = TLI.getExceptionPointerRegister();
5190 assert(Reg && "cannot get exception code on this platform");
5191 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5192 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5193 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5194 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5196 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5197 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5204 std::pair<SDValue, SDValue>
5205 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5206 const BasicBlock *EHPadBB) {
5207 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5208 MCSymbol *BeginLabel = nullptr;
5211 // Insert a label before the invoke call to mark the try range. This can be
5212 // used to detect deletion of the invoke via the MachineModuleInfo.
5213 BeginLabel = MMI.getContext().createTempSymbol();
5215 // For SjLj, keep track of which landing pads go with which invokes
5216 // so as to maintain the ordering of pads in the LSDA.
5217 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5218 if (CallSiteIndex) {
5219 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5220 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5222 // Now that the call site is handled, stop tracking it.
5223 MMI.setCurrentCallSite(0);
5226 // Both PendingLoads and PendingExports must be flushed here;
5227 // this call might not return.
5229 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5231 CLI.setChain(getRoot());
5233 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5234 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5236 assert((CLI.IsTailCall || Result.second.getNode()) &&
5237 "Non-null chain expected with non-tail call!");
5238 assert((Result.second.getNode() || !Result.first.getNode()) &&
5239 "Null value expected with tail call!");
5241 if (!Result.second.getNode()) {
5242 // As a special case, a null chain means that a tail call has been emitted
5243 // and the DAG root is already updated.
5246 // Since there's no actual continuation from this block, nothing can be
5247 // relying on us setting vregs for them.
5248 PendingExports.clear();
5250 DAG.setRoot(Result.second);
5254 // Insert a label at the end of the invoke call to mark the try range. This
5255 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5256 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5257 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5259 // Inform MachineModuleInfo of range.
5260 if (MMI.hasEHFunclets()) {
5261 WinEHFuncInfo &EHInfo =
5262 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5263 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5265 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5272 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5274 const BasicBlock *EHPadBB) {
5275 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5276 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5277 Type *RetTy = FTy->getReturnType();
5279 TargetLowering::ArgListTy Args;
5280 TargetLowering::ArgListEntry Entry;
5281 Args.reserve(CS.arg_size());
5283 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5285 const Value *V = *i;
5288 if (V->getType()->isEmptyTy())
5291 SDValue ArgNode = getValue(V);
5292 Entry.Node = ArgNode; Entry.Ty = V->getType();
5294 // Skip the first return-type Attribute to get to params.
5295 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5296 Args.push_back(Entry);
5298 // If we have an explicit sret argument that is an Instruction, (i.e., it
5299 // might point to function-local memory), we can't meaningfully tail-call.
5300 if (Entry.isSRet && isa<Instruction>(V))
5304 // Check if target-independent constraints permit a tail call here.
5305 // Target-dependent constraints are checked within TLI->LowerCallTo.
5306 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5309 TargetLowering::CallLoweringInfo CLI(DAG);
5310 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5311 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5312 .setTailCall(isTailCall);
5313 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5315 if (Result.first.getNode())
5316 setValue(CS.getInstruction(), Result.first);
5319 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5320 /// value is equal or not-equal to zero.
5321 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5322 for (const User *U : V->users()) {
5323 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5324 if (IC->isEquality())
5325 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5326 if (C->isNullValue())
5328 // Unknown instruction.
5334 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5336 SelectionDAGBuilder &Builder) {
5338 // Check to see if this load can be trivially constant folded, e.g. if the
5339 // input is from a string literal.
5340 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5341 // Cast pointer to the type we really want to load.
5342 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5343 PointerType::getUnqual(LoadTy));
5345 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5346 const_cast<Constant *>(LoadInput), *Builder.DL))
5347 return Builder.getValue(LoadCst);
5350 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5351 // still constant memory, the input chain can be the entry node.
5353 bool ConstantMemory = false;
5355 // Do not serialize (non-volatile) loads of constant memory with anything.
5356 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5357 Root = Builder.DAG.getEntryNode();
5358 ConstantMemory = true;
5360 // Do not serialize non-volatile loads against each other.
5361 Root = Builder.DAG.getRoot();
5364 SDValue Ptr = Builder.getValue(PtrVal);
5365 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5366 Ptr, MachinePointerInfo(PtrVal),
5368 false /*nontemporal*/,
5369 false /*isinvariant*/, 1 /* align=1 */);
5371 if (!ConstantMemory)
5372 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5376 /// processIntegerCallValue - Record the value for an instruction that
5377 /// produces an integer result, converting the type where necessary.
5378 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5381 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5384 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5386 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5387 setValue(&I, Value);
5390 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5391 /// If so, return true and lower it, otherwise return false and it will be
5392 /// lowered like a normal call.
5393 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5394 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5395 if (I.getNumArgOperands() != 3)
5398 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5399 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5400 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5401 !I.getType()->isIntegerTy())
5404 const Value *Size = I.getArgOperand(2);
5405 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5406 if (CSize && CSize->getZExtValue() == 0) {
5407 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5409 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5413 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5414 std::pair<SDValue, SDValue> Res =
5415 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5416 getValue(LHS), getValue(RHS), getValue(Size),
5417 MachinePointerInfo(LHS),
5418 MachinePointerInfo(RHS));
5419 if (Res.first.getNode()) {
5420 processIntegerCallValue(I, Res.first, true);
5421 PendingLoads.push_back(Res.second);
5425 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5426 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5427 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5428 bool ActuallyDoIt = true;
5431 switch (CSize->getZExtValue()) {
5433 LoadVT = MVT::Other;
5435 ActuallyDoIt = false;
5439 LoadTy = Type::getInt16Ty(CSize->getContext());
5443 LoadTy = Type::getInt32Ty(CSize->getContext());
5447 LoadTy = Type::getInt64Ty(CSize->getContext());
5451 LoadVT = MVT::v4i32;
5452 LoadTy = Type::getInt32Ty(CSize->getContext());
5453 LoadTy = VectorType::get(LoadTy, 4);
5458 // This turns into unaligned loads. We only do this if the target natively
5459 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5460 // we'll only produce a small number of byte loads.
5462 // Require that we can find a legal MVT, and only do this if the target
5463 // supports unaligned loads of that type. Expanding into byte loads would
5465 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5466 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5467 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5468 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5469 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5470 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5471 // TODO: Check alignment of src and dest ptrs.
5472 if (!TLI.isTypeLegal(LoadVT) ||
5473 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5474 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5475 ActuallyDoIt = false;
5479 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5480 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5482 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5484 processIntegerCallValue(I, Res, false);
5493 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5494 /// form. If so, return true and lower it, otherwise return false and it
5495 /// will be lowered like a normal call.
5496 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5497 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5498 if (I.getNumArgOperands() != 3)
5501 const Value *Src = I.getArgOperand(0);
5502 const Value *Char = I.getArgOperand(1);
5503 const Value *Length = I.getArgOperand(2);
5504 if (!Src->getType()->isPointerTy() ||
5505 !Char->getType()->isIntegerTy() ||
5506 !Length->getType()->isIntegerTy() ||
5507 !I.getType()->isPointerTy())
5510 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5511 std::pair<SDValue, SDValue> Res =
5512 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5513 getValue(Src), getValue(Char), getValue(Length),
5514 MachinePointerInfo(Src));
5515 if (Res.first.getNode()) {
5516 setValue(&I, Res.first);
5517 PendingLoads.push_back(Res.second);
5524 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5525 /// optimized form. If so, return true and lower it, otherwise return false
5526 /// and it will be lowered like a normal call.
5527 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5528 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5529 if (I.getNumArgOperands() != 2)
5532 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5533 if (!Arg0->getType()->isPointerTy() ||
5534 !Arg1->getType()->isPointerTy() ||
5535 !I.getType()->isPointerTy())
5538 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5539 std::pair<SDValue, SDValue> Res =
5540 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5541 getValue(Arg0), getValue(Arg1),
5542 MachinePointerInfo(Arg0),
5543 MachinePointerInfo(Arg1), isStpcpy);
5544 if (Res.first.getNode()) {
5545 setValue(&I, Res.first);
5546 DAG.setRoot(Res.second);
5553 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5554 /// If so, return true and lower it, otherwise return false and it will be
5555 /// lowered like a normal call.
5556 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5557 // Verify that the prototype makes sense. int strcmp(void*,void*)
5558 if (I.getNumArgOperands() != 2)
5561 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5562 if (!Arg0->getType()->isPointerTy() ||
5563 !Arg1->getType()->isPointerTy() ||
5564 !I.getType()->isIntegerTy())
5567 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5568 std::pair<SDValue, SDValue> Res =
5569 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5570 getValue(Arg0), getValue(Arg1),
5571 MachinePointerInfo(Arg0),
5572 MachinePointerInfo(Arg1));
5573 if (Res.first.getNode()) {
5574 processIntegerCallValue(I, Res.first, true);
5575 PendingLoads.push_back(Res.second);
5582 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5583 /// form. If so, return true and lower it, otherwise return false and it
5584 /// will be lowered like a normal call.
5585 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5586 // Verify that the prototype makes sense. size_t strlen(char *)
5587 if (I.getNumArgOperands() != 1)
5590 const Value *Arg0 = I.getArgOperand(0);
5591 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5594 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5595 std::pair<SDValue, SDValue> Res =
5596 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5597 getValue(Arg0), MachinePointerInfo(Arg0));
5598 if (Res.first.getNode()) {
5599 processIntegerCallValue(I, Res.first, false);
5600 PendingLoads.push_back(Res.second);
5607 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5608 /// form. If so, return true and lower it, otherwise return false and it
5609 /// will be lowered like a normal call.
5610 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5611 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5612 if (I.getNumArgOperands() != 2)
5615 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5616 if (!Arg0->getType()->isPointerTy() ||
5617 !Arg1->getType()->isIntegerTy() ||
5618 !I.getType()->isIntegerTy())
5621 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5622 std::pair<SDValue, SDValue> Res =
5623 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5624 getValue(Arg0), getValue(Arg1),
5625 MachinePointerInfo(Arg0));
5626 if (Res.first.getNode()) {
5627 processIntegerCallValue(I, Res.first, false);
5628 PendingLoads.push_back(Res.second);
5635 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5636 /// operation (as expected), translate it to an SDNode with the specified opcode
5637 /// and return true.
5638 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5640 // Sanity check that it really is a unary floating-point call.
5641 if (I.getNumArgOperands() != 1 ||
5642 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5643 I.getType() != I.getArgOperand(0)->getType() ||
5644 !I.onlyReadsMemory())
5647 SDValue Tmp = getValue(I.getArgOperand(0));
5648 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5652 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5653 /// operation (as expected), translate it to an SDNode with the specified opcode
5654 /// and return true.
5655 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5657 // Sanity check that it really is a binary floating-point call.
5658 if (I.getNumArgOperands() != 2 ||
5659 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5660 I.getType() != I.getArgOperand(0)->getType() ||
5661 I.getType() != I.getArgOperand(1)->getType() ||
5662 !I.onlyReadsMemory())
5665 SDValue Tmp0 = getValue(I.getArgOperand(0));
5666 SDValue Tmp1 = getValue(I.getArgOperand(1));
5667 EVT VT = Tmp0.getValueType();
5668 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5672 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5673 // Handle inline assembly differently.
5674 if (isa<InlineAsm>(I.getCalledValue())) {
5679 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5680 ComputeUsesVAFloatArgument(I, &MMI);
5682 const char *RenameFn = nullptr;
5683 if (Function *F = I.getCalledFunction()) {
5684 if (F->isDeclaration()) {
5685 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5686 if (unsigned IID = II->getIntrinsicID(F)) {
5687 RenameFn = visitIntrinsicCall(I, IID);
5692 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5693 RenameFn = visitIntrinsicCall(I, IID);
5699 // Check for well-known libc/libm calls. If the function is internal, it
5700 // can't be a library call.
5702 if (!F->hasLocalLinkage() && F->hasName() &&
5703 LibInfo->getLibFunc(F->getName(), Func) &&
5704 LibInfo->hasOptimizedCodeGen(Func)) {
5707 case LibFunc::copysign:
5708 case LibFunc::copysignf:
5709 case LibFunc::copysignl:
5710 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5711 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5712 I.getType() == I.getArgOperand(0)->getType() &&
5713 I.getType() == I.getArgOperand(1)->getType() &&
5714 I.onlyReadsMemory()) {
5715 SDValue LHS = getValue(I.getArgOperand(0));
5716 SDValue RHS = getValue(I.getArgOperand(1));
5717 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5718 LHS.getValueType(), LHS, RHS));
5723 case LibFunc::fabsf:
5724 case LibFunc::fabsl:
5725 if (visitUnaryFloatCall(I, ISD::FABS))
5729 case LibFunc::fminf:
5730 case LibFunc::fminl:
5731 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5735 case LibFunc::fmaxf:
5736 case LibFunc::fmaxl:
5737 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5743 if (visitUnaryFloatCall(I, ISD::FSIN))
5749 if (visitUnaryFloatCall(I, ISD::FCOS))
5753 case LibFunc::sqrtf:
5754 case LibFunc::sqrtl:
5755 case LibFunc::sqrt_finite:
5756 case LibFunc::sqrtf_finite:
5757 case LibFunc::sqrtl_finite:
5758 if (visitUnaryFloatCall(I, ISD::FSQRT))
5761 case LibFunc::floor:
5762 case LibFunc::floorf:
5763 case LibFunc::floorl:
5764 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5767 case LibFunc::nearbyint:
5768 case LibFunc::nearbyintf:
5769 case LibFunc::nearbyintl:
5770 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5774 case LibFunc::ceilf:
5775 case LibFunc::ceill:
5776 if (visitUnaryFloatCall(I, ISD::FCEIL))
5780 case LibFunc::rintf:
5781 case LibFunc::rintl:
5782 if (visitUnaryFloatCall(I, ISD::FRINT))
5785 case LibFunc::round:
5786 case LibFunc::roundf:
5787 case LibFunc::roundl:
5788 if (visitUnaryFloatCall(I, ISD::FROUND))
5791 case LibFunc::trunc:
5792 case LibFunc::truncf:
5793 case LibFunc::truncl:
5794 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5798 case LibFunc::log2f:
5799 case LibFunc::log2l:
5800 if (visitUnaryFloatCall(I, ISD::FLOG2))
5804 case LibFunc::exp2f:
5805 case LibFunc::exp2l:
5806 if (visitUnaryFloatCall(I, ISD::FEXP2))
5809 case LibFunc::memcmp:
5810 if (visitMemCmpCall(I))
5813 case LibFunc::memchr:
5814 if (visitMemChrCall(I))
5817 case LibFunc::strcpy:
5818 if (visitStrCpyCall(I, false))
5821 case LibFunc::stpcpy:
5822 if (visitStrCpyCall(I, true))
5825 case LibFunc::strcmp:
5826 if (visitStrCmpCall(I))
5829 case LibFunc::strlen:
5830 if (visitStrLenCall(I))
5833 case LibFunc::strnlen:
5834 if (visitStrNLenCall(I))
5843 Callee = getValue(I.getCalledValue());
5845 Callee = DAG.getExternalSymbol(
5847 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5849 // Check if we can potentially perform a tail call. More detailed checking is
5850 // be done within LowerCallTo, after more information about the call is known.
5851 LowerCallTo(&I, Callee, I.isTailCall());
5856 /// AsmOperandInfo - This contains information for each constraint that we are
5858 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5860 /// CallOperand - If this is the result output operand or a clobber
5861 /// this is null, otherwise it is the incoming operand to the CallInst.
5862 /// This gets modified as the asm is processed.
5863 SDValue CallOperand;
5865 /// AssignedRegs - If this is a register or register class operand, this
5866 /// contains the set of register corresponding to the operand.
5867 RegsForValue AssignedRegs;
5869 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5870 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5873 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5874 /// corresponds to. If there is no Value* for this operand, it returns
5876 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5877 const DataLayout &DL) const {
5878 if (!CallOperandVal) return MVT::Other;
5880 if (isa<BasicBlock>(CallOperandVal))
5881 return TLI.getPointerTy(DL);
5883 llvm::Type *OpTy = CallOperandVal->getType();
5885 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5886 // If this is an indirect operand, the operand is a pointer to the
5889 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5891 report_fatal_error("Indirect operand for inline asm not a pointer!");
5892 OpTy = PtrTy->getElementType();
5895 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5896 if (StructType *STy = dyn_cast<StructType>(OpTy))
5897 if (STy->getNumElements() == 1)
5898 OpTy = STy->getElementType(0);
5900 // If OpTy is not a single value, it may be a struct/union that we
5901 // can tile with integers.
5902 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5903 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5912 OpTy = IntegerType::get(Context, BitSize);
5917 return TLI.getValueType(DL, OpTy, true);
5921 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5923 } // end anonymous namespace
5925 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5926 /// specified operand. We prefer to assign virtual registers, to allow the
5927 /// register allocator to handle the assignment process. However, if the asm
5928 /// uses features that we can't model on machineinstrs, we have SDISel do the
5929 /// allocation. This produces generally horrible, but correct, code.
5931 /// OpInfo describes the operand.
5933 static void GetRegistersForValue(SelectionDAG &DAG,
5934 const TargetLowering &TLI,
5936 SDISelAsmOperandInfo &OpInfo) {
5937 LLVMContext &Context = *DAG.getContext();
5939 MachineFunction &MF = DAG.getMachineFunction();
5940 SmallVector<unsigned, 4> Regs;
5942 // If this is a constraint for a single physreg, or a constraint for a
5943 // register class, find it.
5944 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5945 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5946 OpInfo.ConstraintCode,
5947 OpInfo.ConstraintVT);
5949 unsigned NumRegs = 1;
5950 if (OpInfo.ConstraintVT != MVT::Other) {
5951 // If this is a FP input in an integer register (or visa versa) insert a bit
5952 // cast of the input value. More generally, handle any case where the input
5953 // value disagrees with the register class we plan to stick this in.
5954 if (OpInfo.Type == InlineAsm::isInput &&
5955 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5956 // Try to convert to the first EVT that the reg class contains. If the
5957 // types are identical size, use a bitcast to convert (e.g. two differing
5959 MVT RegVT = *PhysReg.second->vt_begin();
5960 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5961 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5962 RegVT, OpInfo.CallOperand);
5963 OpInfo.ConstraintVT = RegVT;
5964 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5965 // If the input is a FP value and we want it in FP registers, do a
5966 // bitcast to the corresponding integer type. This turns an f64 value
5967 // into i64, which can be passed with two i32 values on a 32-bit
5969 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5970 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5971 RegVT, OpInfo.CallOperand);
5972 OpInfo.ConstraintVT = RegVT;
5976 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5980 EVT ValueVT = OpInfo.ConstraintVT;
5982 // If this is a constraint for a specific physical register, like {r17},
5984 if (unsigned AssignedReg = PhysReg.first) {
5985 const TargetRegisterClass *RC = PhysReg.second;
5986 if (OpInfo.ConstraintVT == MVT::Other)
5987 ValueVT = *RC->vt_begin();
5989 // Get the actual register value type. This is important, because the user
5990 // may have asked for (e.g.) the AX register in i32 type. We need to
5991 // remember that AX is actually i16 to get the right extension.
5992 RegVT = *RC->vt_begin();
5994 // This is a explicit reference to a physical register.
5995 Regs.push_back(AssignedReg);
5997 // If this is an expanded reference, add the rest of the regs to Regs.
5999 TargetRegisterClass::iterator I = RC->begin();
6000 for (; *I != AssignedReg; ++I)
6001 assert(I != RC->end() && "Didn't find reg!");
6003 // Already added the first reg.
6005 for (; NumRegs; --NumRegs, ++I) {
6006 assert(I != RC->end() && "Ran out of registers to allocate!");
6011 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6015 // Otherwise, if this was a reference to an LLVM register class, create vregs
6016 // for this reference.
6017 if (const TargetRegisterClass *RC = PhysReg.second) {
6018 RegVT = *RC->vt_begin();
6019 if (OpInfo.ConstraintVT == MVT::Other)
6022 // Create the appropriate number of virtual registers.
6023 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6024 for (; NumRegs; --NumRegs)
6025 Regs.push_back(RegInfo.createVirtualRegister(RC));
6027 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6031 // Otherwise, we couldn't allocate enough registers for this.
6034 /// visitInlineAsm - Handle a call to an InlineAsm object.
6036 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6037 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6039 /// ConstraintOperands - Information about all of the constraints.
6040 SDISelAsmOperandInfoVector ConstraintOperands;
6042 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6043 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6044 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6046 bool hasMemory = false;
6048 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6049 unsigned ResNo = 0; // ResNo - The result number of the next output.
6050 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6051 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6052 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6054 MVT OpVT = MVT::Other;
6056 // Compute the value type for each operand.
6057 switch (OpInfo.Type) {
6058 case InlineAsm::isOutput:
6059 // Indirect outputs just consume an argument.
6060 if (OpInfo.isIndirect) {
6061 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6065 // The return value of the call is this value. As such, there is no
6066 // corresponding argument.
6067 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6068 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6069 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6070 STy->getElementType(ResNo));
6072 assert(ResNo == 0 && "Asm only has one result!");
6073 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6077 case InlineAsm::isInput:
6078 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6080 case InlineAsm::isClobber:
6085 // If this is an input or an indirect output, process the call argument.
6086 // BasicBlocks are labels, currently appearing only in asm's.
6087 if (OpInfo.CallOperandVal) {
6088 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6089 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6091 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6094 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6095 DAG.getDataLayout()).getSimpleVT();
6098 OpInfo.ConstraintVT = OpVT;
6100 // Indirect operand accesses access memory.
6101 if (OpInfo.isIndirect)
6104 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6105 TargetLowering::ConstraintType
6106 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6107 if (CType == TargetLowering::C_Memory) {
6115 SDValue Chain, Flag;
6117 // We won't need to flush pending loads if this asm doesn't touch
6118 // memory and is nonvolatile.
6119 if (hasMemory || IA->hasSideEffects())
6122 Chain = DAG.getRoot();
6124 // Second pass over the constraints: compute which constraint option to use
6125 // and assign registers to constraints that want a specific physreg.
6126 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6127 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6129 // If this is an output operand with a matching input operand, look up the
6130 // matching input. If their types mismatch, e.g. one is an integer, the
6131 // other is floating point, or their sizes are different, flag it as an
6133 if (OpInfo.hasMatchingInput()) {
6134 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6136 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6137 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6138 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6139 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6140 OpInfo.ConstraintVT);
6141 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6142 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6143 Input.ConstraintVT);
6144 if ((OpInfo.ConstraintVT.isInteger() !=
6145 Input.ConstraintVT.isInteger()) ||
6146 (MatchRC.second != InputRC.second)) {
6147 report_fatal_error("Unsupported asm: input constraint"
6148 " with a matching output constraint of"
6149 " incompatible type!");
6151 Input.ConstraintVT = OpInfo.ConstraintVT;
6155 // Compute the constraint code and ConstraintType to use.
6156 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6158 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6159 OpInfo.Type == InlineAsm::isClobber)
6162 // If this is a memory input, and if the operand is not indirect, do what we
6163 // need to to provide an address for the memory input.
6164 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6165 !OpInfo.isIndirect) {
6166 assert((OpInfo.isMultipleAlternative ||
6167 (OpInfo.Type == InlineAsm::isInput)) &&
6168 "Can only indirectify direct input operands!");
6170 // Memory operands really want the address of the value. If we don't have
6171 // an indirect input, put it in the constpool if we can, otherwise spill
6172 // it to a stack slot.
6173 // TODO: This isn't quite right. We need to handle these according to
6174 // the addressing mode that the constraint wants. Also, this may take
6175 // an additional register for the computation and we don't want that
6178 // If the operand is a float, integer, or vector constant, spill to a
6179 // constant pool entry to get its address.
6180 const Value *OpVal = OpInfo.CallOperandVal;
6181 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6182 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6183 OpInfo.CallOperand = DAG.getConstantPool(
6184 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6186 // Otherwise, create a stack slot and emit a store to it before the
6188 Type *Ty = OpVal->getType();
6189 auto &DL = DAG.getDataLayout();
6190 uint64_t TySize = DL.getTypeAllocSize(Ty);
6191 unsigned Align = DL.getPrefTypeAlignment(Ty);
6192 MachineFunction &MF = DAG.getMachineFunction();
6193 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6195 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6196 Chain = DAG.getStore(
6197 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6198 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6200 OpInfo.CallOperand = StackSlot;
6203 // There is no longer a Value* corresponding to this operand.
6204 OpInfo.CallOperandVal = nullptr;
6206 // It is now an indirect operand.
6207 OpInfo.isIndirect = true;
6210 // If this constraint is for a specific register, allocate it before
6212 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6213 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6216 // Second pass - Loop over all of the operands, assigning virtual or physregs
6217 // to register class operands.
6218 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6219 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6221 // C_Register operands have already been allocated, Other/Memory don't need
6223 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6224 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6227 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6228 std::vector<SDValue> AsmNodeOperands;
6229 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6230 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6231 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6233 // If we have a !srcloc metadata node associated with it, we want to attach
6234 // this to the ultimately generated inline asm machineinstr. To do this, we
6235 // pass in the third operand as this (potentially null) inline asm MDNode.
6236 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6237 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6239 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6240 // bits as operand 3.
6241 unsigned ExtraInfo = 0;
6242 if (IA->hasSideEffects())
6243 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6244 if (IA->isAlignStack())
6245 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6246 // Set the asm dialect.
6247 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6249 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6250 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6251 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6253 // Compute the constraint code and ConstraintType to use.
6254 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6256 // Ideally, we would only check against memory constraints. However, the
6257 // meaning of an other constraint can be target-specific and we can't easily
6258 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6259 // for other constriants as well.
6260 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6261 OpInfo.ConstraintType == TargetLowering::C_Other) {
6262 if (OpInfo.Type == InlineAsm::isInput)
6263 ExtraInfo |= InlineAsm::Extra_MayLoad;
6264 else if (OpInfo.Type == InlineAsm::isOutput)
6265 ExtraInfo |= InlineAsm::Extra_MayStore;
6266 else if (OpInfo.Type == InlineAsm::isClobber)
6267 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6271 AsmNodeOperands.push_back(DAG.getTargetConstant(
6272 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6274 // Loop over all of the inputs, copying the operand values into the
6275 // appropriate registers and processing the output regs.
6276 RegsForValue RetValRegs;
6278 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6279 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6281 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6282 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6284 switch (OpInfo.Type) {
6285 case InlineAsm::isOutput: {
6286 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6287 OpInfo.ConstraintType != TargetLowering::C_Register) {
6288 // Memory output, or 'other' output (e.g. 'X' constraint).
6289 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6291 unsigned ConstraintID =
6292 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6293 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6294 "Failed to convert memory constraint code to constraint id.");
6296 // Add information to the INLINEASM node to know about this output.
6297 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6298 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6299 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6301 AsmNodeOperands.push_back(OpInfo.CallOperand);
6305 // Otherwise, this is a register or register class output.
6307 // Copy the output from the appropriate register. Find a register that
6309 if (OpInfo.AssignedRegs.Regs.empty()) {
6310 LLVMContext &Ctx = *DAG.getContext();
6311 Ctx.emitError(CS.getInstruction(),
6312 "couldn't allocate output register for constraint '" +
6313 Twine(OpInfo.ConstraintCode) + "'");
6317 // If this is an indirect operand, store through the pointer after the
6319 if (OpInfo.isIndirect) {
6320 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6321 OpInfo.CallOperandVal));
6323 // This is the result value of the call.
6324 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6325 // Concatenate this output onto the outputs list.
6326 RetValRegs.append(OpInfo.AssignedRegs);
6329 // Add information to the INLINEASM node to know that this register is
6332 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6333 ? InlineAsm::Kind_RegDefEarlyClobber
6334 : InlineAsm::Kind_RegDef,
6335 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6338 case InlineAsm::isInput: {
6339 SDValue InOperandVal = OpInfo.CallOperand;
6341 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6342 // If this is required to match an output register we have already set,
6343 // just use its register.
6344 unsigned OperandNo = OpInfo.getMatchedOperand();
6346 // Scan until we find the definition we already emitted of this operand.
6347 // When we find it, create a RegsForValue operand.
6348 unsigned CurOp = InlineAsm::Op_FirstOperand;
6349 for (; OperandNo; --OperandNo) {
6350 // Advance to the next operand.
6352 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6353 assert((InlineAsm::isRegDefKind(OpFlag) ||
6354 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6355 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6356 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6360 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6361 if (InlineAsm::isRegDefKind(OpFlag) ||
6362 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6363 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6364 if (OpInfo.isIndirect) {
6365 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6366 LLVMContext &Ctx = *DAG.getContext();
6367 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6368 " don't know how to handle tied "
6369 "indirect register inputs");
6373 RegsForValue MatchedRegs;
6374 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6375 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6376 MatchedRegs.RegVTs.push_back(RegVT);
6377 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6378 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6380 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6381 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6383 LLVMContext &Ctx = *DAG.getContext();
6384 Ctx.emitError(CS.getInstruction(),
6385 "inline asm error: This value"
6386 " type register class is not natively supported!");
6390 SDLoc dl = getCurSDLoc();
6391 // Use the produced MatchedRegs object to
6392 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6393 Chain, &Flag, CS.getInstruction());
6394 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6395 true, OpInfo.getMatchedOperand(), dl,
6396 DAG, AsmNodeOperands);
6400 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6401 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6402 "Unexpected number of operands");
6403 // Add information to the INLINEASM node to know about this input.
6404 // See InlineAsm.h isUseOperandTiedToDef.
6405 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6406 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6407 OpInfo.getMatchedOperand());
6408 AsmNodeOperands.push_back(DAG.getTargetConstant(
6409 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6410 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6414 // Treat indirect 'X' constraint as memory.
6415 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6417 OpInfo.ConstraintType = TargetLowering::C_Memory;
6419 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6420 std::vector<SDValue> Ops;
6421 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6424 LLVMContext &Ctx = *DAG.getContext();
6425 Ctx.emitError(CS.getInstruction(),
6426 "invalid operand for inline asm constraint '" +
6427 Twine(OpInfo.ConstraintCode) + "'");
6431 // Add information to the INLINEASM node to know about this input.
6432 unsigned ResOpType =
6433 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6434 AsmNodeOperands.push_back(DAG.getTargetConstant(
6435 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6436 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6440 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6441 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6442 assert(InOperandVal.getValueType() ==
6443 TLI.getPointerTy(DAG.getDataLayout()) &&
6444 "Memory operands expect pointer values");
6446 unsigned ConstraintID =
6447 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6448 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6449 "Failed to convert memory constraint code to constraint id.");
6451 // Add information to the INLINEASM node to know about this input.
6452 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6453 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6454 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6457 AsmNodeOperands.push_back(InOperandVal);
6461 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6462 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6463 "Unknown constraint type!");
6465 // TODO: Support this.
6466 if (OpInfo.isIndirect) {
6467 LLVMContext &Ctx = *DAG.getContext();
6468 Ctx.emitError(CS.getInstruction(),
6469 "Don't know how to handle indirect register inputs yet "
6470 "for constraint '" +
6471 Twine(OpInfo.ConstraintCode) + "'");
6475 // Copy the input into the appropriate registers.
6476 if (OpInfo.AssignedRegs.Regs.empty()) {
6477 LLVMContext &Ctx = *DAG.getContext();
6478 Ctx.emitError(CS.getInstruction(),
6479 "couldn't allocate input reg for constraint '" +
6480 Twine(OpInfo.ConstraintCode) + "'");
6484 SDLoc dl = getCurSDLoc();
6486 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6487 Chain, &Flag, CS.getInstruction());
6489 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6490 dl, DAG, AsmNodeOperands);
6493 case InlineAsm::isClobber: {
6494 // Add the clobbered value to the operand list, so that the register
6495 // allocator is aware that the physreg got clobbered.
6496 if (!OpInfo.AssignedRegs.Regs.empty())
6497 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6498 false, 0, getCurSDLoc(), DAG,
6505 // Finish up input operands. Set the input chain and add the flag last.
6506 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6507 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6509 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6510 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6511 Flag = Chain.getValue(1);
6513 // If this asm returns a register value, copy the result from that register
6514 // and set it as the value of the call.
6515 if (!RetValRegs.Regs.empty()) {
6516 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6517 Chain, &Flag, CS.getInstruction());
6519 // FIXME: Why don't we do this for inline asms with MRVs?
6520 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6521 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6523 // If any of the results of the inline asm is a vector, it may have the
6524 // wrong width/num elts. This can happen for register classes that can
6525 // contain multiple different value types. The preg or vreg allocated may
6526 // not have the same VT as was expected. Convert it to the right type
6527 // with bit_convert.
6528 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6529 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6532 } else if (ResultType != Val.getValueType() &&
6533 ResultType.isInteger() && Val.getValueType().isInteger()) {
6534 // If a result value was tied to an input value, the computed result may
6535 // have a wider width than the expected result. Extract the relevant
6537 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6540 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6543 setValue(CS.getInstruction(), Val);
6544 // Don't need to use this as a chain in this case.
6545 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6549 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6551 // Process indirect outputs, first output all of the flagged copies out of
6553 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6554 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6555 const Value *Ptr = IndirectStoresToEmit[i].second;
6556 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6558 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6561 // Emit the non-flagged stores from the physregs.
6562 SmallVector<SDValue, 8> OutChains;
6563 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6564 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6565 StoresToEmit[i].first,
6566 getValue(StoresToEmit[i].second),
6567 MachinePointerInfo(StoresToEmit[i].second),
6569 OutChains.push_back(Val);
6572 if (!OutChains.empty())
6573 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6578 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6579 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6580 MVT::Other, getRoot(),
6581 getValue(I.getArgOperand(0)),
6582 DAG.getSrcValue(I.getArgOperand(0))));
6585 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6587 const DataLayout &DL = DAG.getDataLayout();
6588 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6589 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6590 DAG.getSrcValue(I.getOperand(0)),
6591 DL.getABITypeAlignment(I.getType()));
6593 DAG.setRoot(V.getValue(1));
6596 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6597 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6598 MVT::Other, getRoot(),
6599 getValue(I.getArgOperand(0)),
6600 DAG.getSrcValue(I.getArgOperand(0))));
6603 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6604 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6605 MVT::Other, getRoot(),
6606 getValue(I.getArgOperand(0)),
6607 getValue(I.getArgOperand(1)),
6608 DAG.getSrcValue(I.getArgOperand(0)),
6609 DAG.getSrcValue(I.getArgOperand(1))));
6612 /// \brief Lower an argument list according to the target calling convention.
6614 /// \return A tuple of <return-value, token-chain>
6616 /// This is a helper for lowering intrinsics that follow a target calling
6617 /// convention or require stack pointer adjustment. Only a subset of the
6618 /// intrinsic's operands need to participate in the calling convention.
6619 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6620 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6621 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6622 TargetLowering::ArgListTy Args;
6623 Args.reserve(NumArgs);
6625 // Populate the argument list.
6626 // Attributes for args start at offset 1, after the return attribute.
6627 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6628 ArgI != ArgE; ++ArgI) {
6629 const Value *V = CS->getOperand(ArgI);
6631 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6633 TargetLowering::ArgListEntry Entry;
6634 Entry.Node = getValue(V);
6635 Entry.Ty = V->getType();
6636 Entry.setAttributes(&CS, AttrI);
6637 Args.push_back(Entry);
6640 TargetLowering::CallLoweringInfo CLI(DAG);
6641 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6642 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6643 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6645 return lowerInvokable(CLI, EHPadBB);
6648 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6649 /// or patchpoint target node's operand list.
6651 /// Constants are converted to TargetConstants purely as an optimization to
6652 /// avoid constant materialization and register allocation.
6654 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6655 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6656 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6657 /// address materialization and register allocation, but may also be required
6658 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6659 /// alloca in the entry block, then the runtime may assume that the alloca's
6660 /// StackMap location can be read immediately after compilation and that the
6661 /// location is valid at any point during execution (this is similar to the
6662 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6663 /// only available in a register, then the runtime would need to trap when
6664 /// execution reaches the StackMap in order to read the alloca's location.
6665 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6666 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6667 SelectionDAGBuilder &Builder) {
6668 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6669 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6670 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6672 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6674 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6675 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6676 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6677 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6678 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6680 Ops.push_back(OpVal);
6684 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6685 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6686 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6687 // [live variables...])
6689 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6691 SDValue Chain, InFlag, Callee, NullPtr;
6692 SmallVector<SDValue, 32> Ops;
6694 SDLoc DL = getCurSDLoc();
6695 Callee = getValue(CI.getCalledValue());
6696 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6698 // The stackmap intrinsic only records the live variables (the arguemnts
6699 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6700 // intrinsic, this won't be lowered to a function call. This means we don't
6701 // have to worry about calling conventions and target specific lowering code.
6702 // Instead we perform the call lowering right here.
6704 // chain, flag = CALLSEQ_START(chain, 0)
6705 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6706 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6708 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6709 InFlag = Chain.getValue(1);
6711 // Add the <id> and <numBytes> constants.
6712 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6713 Ops.push_back(DAG.getTargetConstant(
6714 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6715 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6716 Ops.push_back(DAG.getTargetConstant(
6717 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6720 // Push live variables for the stack map.
6721 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6723 // We are not pushing any register mask info here on the operands list,
6724 // because the stackmap doesn't clobber anything.
6726 // Push the chain and the glue flag.
6727 Ops.push_back(Chain);
6728 Ops.push_back(InFlag);
6730 // Create the STACKMAP node.
6731 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6732 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6733 Chain = SDValue(SM, 0);
6734 InFlag = Chain.getValue(1);
6736 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6738 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6740 // Set the root to the target-lowered call chain.
6743 // Inform the Frame Information that we have a stackmap in this function.
6744 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6747 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6748 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6749 const BasicBlock *EHPadBB) {
6750 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6755 // [live variables...])
6757 CallingConv::ID CC = CS.getCallingConv();
6758 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6759 bool HasDef = !CS->getType()->isVoidTy();
6760 SDLoc dl = getCurSDLoc();
6761 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6763 // Handle immediate and symbolic callees.
6764 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6765 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6767 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6768 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6769 SDLoc(SymbolicCallee),
6770 SymbolicCallee->getValueType(0));
6772 // Get the real number of arguments participating in the call <numArgs>
6773 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6774 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6776 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6777 // Intrinsics include all meta-operands up to but not including CC.
6778 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6779 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6780 "Not enough arguments provided to the patchpoint intrinsic");
6782 // For AnyRegCC the arguments are lowered later on manually.
6783 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6785 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6786 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6787 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6789 SDNode *CallEnd = Result.second.getNode();
6790 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6791 CallEnd = CallEnd->getOperand(0).getNode();
6793 /// Get a call instruction from the call sequence chain.
6794 /// Tail calls are not allowed.
6795 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6796 "Expected a callseq node.");
6797 SDNode *Call = CallEnd->getOperand(0).getNode();
6798 bool HasGlue = Call->getGluedNode();
6800 // Replace the target specific call node with the patchable intrinsic.
6801 SmallVector<SDValue, 8> Ops;
6803 // Add the <id> and <numBytes> constants.
6804 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6805 Ops.push_back(DAG.getTargetConstant(
6806 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6807 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6808 Ops.push_back(DAG.getTargetConstant(
6809 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6813 Ops.push_back(Callee);
6815 // Adjust <numArgs> to account for any arguments that have been passed on the
6817 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6818 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6819 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6820 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6822 // Add the calling convention
6823 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6825 // Add the arguments we omitted previously. The register allocator should
6826 // place these in any free register.
6828 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6829 Ops.push_back(getValue(CS.getArgument(i)));
6831 // Push the arguments from the call instruction up to the register mask.
6832 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6833 Ops.append(Call->op_begin() + 2, e);
6835 // Push live variables for the stack map.
6836 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6838 // Push the register mask info.
6840 Ops.push_back(*(Call->op_end()-2));
6842 Ops.push_back(*(Call->op_end()-1));
6844 // Push the chain (this is originally the first operand of the call, but
6845 // becomes now the last or second to last operand).
6846 Ops.push_back(*(Call->op_begin()));
6848 // Push the glue flag (last operand).
6850 Ops.push_back(*(Call->op_end()-1));
6853 if (IsAnyRegCC && HasDef) {
6854 // Create the return types based on the intrinsic definition
6855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6856 SmallVector<EVT, 3> ValueVTs;
6857 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6858 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6860 // There is always a chain and a glue type at the end
6861 ValueVTs.push_back(MVT::Other);
6862 ValueVTs.push_back(MVT::Glue);
6863 NodeTys = DAG.getVTList(ValueVTs);
6865 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6867 // Replace the target specific call node with a PATCHPOINT node.
6868 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6871 // Update the NodeMap.
6874 setValue(CS.getInstruction(), SDValue(MN, 0));
6876 setValue(CS.getInstruction(), Result.first);
6879 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6880 // call sequence. Furthermore the location of the chain and glue can change
6881 // when the AnyReg calling convention is used and the intrinsic returns a
6883 if (IsAnyRegCC && HasDef) {
6884 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6885 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6886 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6888 DAG.ReplaceAllUsesWith(Call, MN);
6889 DAG.DeleteNode(Call);
6891 // Inform the Frame Information that we have a patchpoint in this function.
6892 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6895 /// Returns an AttributeSet representing the attributes applied to the return
6896 /// value of the given call.
6897 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6898 SmallVector<Attribute::AttrKind, 2> Attrs;
6900 Attrs.push_back(Attribute::SExt);
6902 Attrs.push_back(Attribute::ZExt);
6904 Attrs.push_back(Attribute::InReg);
6906 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6910 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6911 /// implementation, which just calls LowerCall.
6912 /// FIXME: When all targets are
6913 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6914 std::pair<SDValue, SDValue>
6915 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6916 // Handle the incoming return values from the call.
6918 Type *OrigRetTy = CLI.RetTy;
6919 SmallVector<EVT, 4> RetTys;
6920 SmallVector<uint64_t, 4> Offsets;
6921 auto &DL = CLI.DAG.getDataLayout();
6922 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6924 SmallVector<ISD::OutputArg, 4> Outs;
6925 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6927 bool CanLowerReturn =
6928 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6929 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6931 SDValue DemoteStackSlot;
6932 int DemoteStackIdx = -100;
6933 if (!CanLowerReturn) {
6934 // FIXME: equivalent assert?
6935 // assert(!CS.hasInAllocaArgument() &&
6936 // "sret demotion is incompatible with inalloca");
6937 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6938 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6939 MachineFunction &MF = CLI.DAG.getMachineFunction();
6940 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6941 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6943 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6945 Entry.Node = DemoteStackSlot;
6946 Entry.Ty = StackSlotPtrType;
6947 Entry.isSExt = false;
6948 Entry.isZExt = false;
6949 Entry.isInReg = false;
6950 Entry.isSRet = true;
6951 Entry.isNest = false;
6952 Entry.isByVal = false;
6953 Entry.isReturned = false;
6954 Entry.Alignment = Align;
6955 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6956 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6958 // sret demotion isn't compatible with tail-calls, since the sret argument
6959 // points into the callers stack frame.
6960 CLI.IsTailCall = false;
6962 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6964 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6965 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6966 for (unsigned i = 0; i != NumRegs; ++i) {
6967 ISD::InputArg MyFlags;
6968 MyFlags.VT = RegisterVT;
6970 MyFlags.Used = CLI.IsReturnValueUsed;
6972 MyFlags.Flags.setSExt();
6974 MyFlags.Flags.setZExt();
6976 MyFlags.Flags.setInReg();
6977 CLI.Ins.push_back(MyFlags);
6982 // Handle all of the outgoing arguments.
6984 CLI.OutVals.clear();
6985 ArgListTy &Args = CLI.getArgs();
6986 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6987 SmallVector<EVT, 4> ValueVTs;
6988 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6989 Type *FinalType = Args[i].Ty;
6990 if (Args[i].isByVal)
6991 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6992 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6993 FinalType, CLI.CallConv, CLI.IsVarArg);
6994 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6996 EVT VT = ValueVTs[Value];
6997 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6998 SDValue Op = SDValue(Args[i].Node.getNode(),
6999 Args[i].Node.getResNo() + Value);
7000 ISD::ArgFlagsTy Flags;
7001 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7007 if (Args[i].isInReg)
7011 if (Args[i].isByVal)
7013 if (Args[i].isInAlloca) {
7014 Flags.setInAlloca();
7015 // Set the byval flag for CCAssignFn callbacks that don't know about
7016 // inalloca. This way we can know how many bytes we should've allocated
7017 // and how many bytes a callee cleanup function will pop. If we port
7018 // inalloca to more targets, we'll have to add custom inalloca handling
7019 // in the various CC lowering callbacks.
7022 if (Args[i].isByVal || Args[i].isInAlloca) {
7023 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7024 Type *ElementTy = Ty->getElementType();
7025 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7026 // For ByVal, alignment should come from FE. BE will guess if this
7027 // info is not there but there are cases it cannot get right.
7028 unsigned FrameAlign;
7029 if (Args[i].Alignment)
7030 FrameAlign = Args[i].Alignment;
7032 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7033 Flags.setByValAlign(FrameAlign);
7038 Flags.setInConsecutiveRegs();
7039 Flags.setOrigAlign(OriginalAlignment);
7041 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7042 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7043 SmallVector<SDValue, 4> Parts(NumParts);
7044 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7047 ExtendKind = ISD::SIGN_EXTEND;
7048 else if (Args[i].isZExt)
7049 ExtendKind = ISD::ZERO_EXTEND;
7051 // Conservatively only handle 'returned' on non-vectors for now
7052 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7053 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7054 "unexpected use of 'returned'");
7055 // Before passing 'returned' to the target lowering code, ensure that
7056 // either the register MVT and the actual EVT are the same size or that
7057 // the return value and argument are extended in the same way; in these
7058 // cases it's safe to pass the argument register value unchanged as the
7059 // return register value (although it's at the target's option whether
7061 // TODO: allow code generation to take advantage of partially preserved
7062 // registers rather than clobbering the entire register when the
7063 // parameter extension method is not compatible with the return
7065 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7066 (ExtendKind != ISD::ANY_EXTEND &&
7067 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7068 Flags.setReturned();
7071 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7072 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7074 for (unsigned j = 0; j != NumParts; ++j) {
7075 // if it isn't first piece, alignment must be 1
7076 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7077 i < CLI.NumFixedArgs,
7078 i, j*Parts[j].getValueType().getStoreSize());
7079 if (NumParts > 1 && j == 0)
7080 MyFlags.Flags.setSplit();
7082 MyFlags.Flags.setOrigAlign(1);
7084 CLI.Outs.push_back(MyFlags);
7085 CLI.OutVals.push_back(Parts[j]);
7088 if (NeedsRegBlock && Value == NumValues - 1)
7089 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7093 SmallVector<SDValue, 4> InVals;
7094 CLI.Chain = LowerCall(CLI, InVals);
7096 // Verify that the target's LowerCall behaved as expected.
7097 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7098 "LowerCall didn't return a valid chain!");
7099 assert((!CLI.IsTailCall || InVals.empty()) &&
7100 "LowerCall emitted a return value for a tail call!");
7101 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7102 "LowerCall didn't emit the correct number of values!");
7104 // For a tail call, the return value is merely live-out and there aren't
7105 // any nodes in the DAG representing it. Return a special value to
7106 // indicate that a tail call has been emitted and no more Instructions
7107 // should be processed in the current block.
7108 if (CLI.IsTailCall) {
7109 CLI.DAG.setRoot(CLI.Chain);
7110 return std::make_pair(SDValue(), SDValue());
7113 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7114 assert(InVals[i].getNode() &&
7115 "LowerCall emitted a null value!");
7116 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7117 "LowerCall emitted a value with the wrong type!");
7120 SmallVector<SDValue, 4> ReturnValues;
7121 if (!CanLowerReturn) {
7122 // The instruction result is the result of loading from the
7123 // hidden sret parameter.
7124 SmallVector<EVT, 1> PVTs;
7125 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7127 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7128 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7129 EVT PtrVT = PVTs[0];
7131 unsigned NumValues = RetTys.size();
7132 ReturnValues.resize(NumValues);
7133 SmallVector<SDValue, 4> Chains(NumValues);
7135 for (unsigned i = 0; i < NumValues; ++i) {
7136 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7137 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7139 SDValue L = CLI.DAG.getLoad(
7140 RetTys[i], CLI.DL, CLI.Chain, Add,
7141 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7142 DemoteStackIdx, Offsets[i]),
7143 false, false, false, 1);
7144 ReturnValues[i] = L;
7145 Chains[i] = L.getValue(1);
7148 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7150 // Collect the legal value parts into potentially illegal values
7151 // that correspond to the original function's return values.
7152 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7154 AssertOp = ISD::AssertSext;
7155 else if (CLI.RetZExt)
7156 AssertOp = ISD::AssertZext;
7157 unsigned CurReg = 0;
7158 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7160 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7161 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7163 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7164 NumRegs, RegisterVT, VT, nullptr,
7169 // For a function returning void, there is no return value. We can't create
7170 // such a node, so we just return a null return value in that case. In
7171 // that case, nothing will actually look at the value.
7172 if (ReturnValues.empty())
7173 return std::make_pair(SDValue(), CLI.Chain);
7176 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7177 CLI.DAG.getVTList(RetTys), ReturnValues);
7178 return std::make_pair(Res, CLI.Chain);
7181 void TargetLowering::LowerOperationWrapper(SDNode *N,
7182 SmallVectorImpl<SDValue> &Results,
7183 SelectionDAG &DAG) const {
7184 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7186 Results.push_back(Res);
7189 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7190 llvm_unreachable("LowerOperation not implemented for this target!");
7194 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7195 SDValue Op = getNonRegisterValue(V);
7196 assert((Op.getOpcode() != ISD::CopyFromReg ||
7197 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7198 "Copy from a reg to the same reg!");
7199 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7202 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7204 SDValue Chain = DAG.getEntryNode();
7206 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7207 FuncInfo.PreferredExtendType.end())
7209 : FuncInfo.PreferredExtendType[V];
7210 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7211 PendingExports.push_back(Chain);
7214 #include "llvm/CodeGen/SelectionDAGISel.h"
7216 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7217 /// entry block, return true. This includes arguments used by switches, since
7218 /// the switch may expand into multiple basic blocks.
7219 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7220 // With FastISel active, we may be splitting blocks, so force creation
7221 // of virtual registers for all non-dead arguments.
7223 return A->use_empty();
7225 const BasicBlock *Entry = A->getParent()->begin();
7226 for (const User *U : A->users())
7227 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7228 return false; // Use not in entry block.
7233 void SelectionDAGISel::LowerArguments(const Function &F) {
7234 SelectionDAG &DAG = SDB->DAG;
7235 SDLoc dl = SDB->getCurSDLoc();
7236 const DataLayout &DL = DAG.getDataLayout();
7237 SmallVector<ISD::InputArg, 16> Ins;
7239 if (!FuncInfo->CanLowerReturn) {
7240 // Put in an sret pointer parameter before all the other parameters.
7241 SmallVector<EVT, 1> ValueVTs;
7242 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7243 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7245 // NOTE: Assuming that a pointer will never break down to more than one VT
7247 ISD::ArgFlagsTy Flags;
7249 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7250 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7251 ISD::InputArg::NoArgIndex, 0);
7252 Ins.push_back(RetArg);
7255 // Set up the incoming argument description vector.
7257 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7258 I != E; ++I, ++Idx) {
7259 SmallVector<EVT, 4> ValueVTs;
7260 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7261 bool isArgValueUsed = !I->use_empty();
7262 unsigned PartBase = 0;
7263 Type *FinalType = I->getType();
7264 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7265 FinalType = cast<PointerType>(FinalType)->getElementType();
7266 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7267 FinalType, F.getCallingConv(), F.isVarArg());
7268 for (unsigned Value = 0, NumValues = ValueVTs.size();
7269 Value != NumValues; ++Value) {
7270 EVT VT = ValueVTs[Value];
7271 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7272 ISD::ArgFlagsTy Flags;
7273 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7275 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7277 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7279 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7281 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7283 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7285 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7286 Flags.setInAlloca();
7287 // Set the byval flag for CCAssignFn callbacks that don't know about
7288 // inalloca. This way we can know how many bytes we should've allocated
7289 // and how many bytes a callee cleanup function will pop. If we port
7290 // inalloca to more targets, we'll have to add custom inalloca handling
7291 // in the various CC lowering callbacks.
7294 if (Flags.isByVal() || Flags.isInAlloca()) {
7295 PointerType *Ty = cast<PointerType>(I->getType());
7296 Type *ElementTy = Ty->getElementType();
7297 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7298 // For ByVal, alignment should be passed from FE. BE will guess if
7299 // this info is not there but there are cases it cannot get right.
7300 unsigned FrameAlign;
7301 if (F.getParamAlignment(Idx))
7302 FrameAlign = F.getParamAlignment(Idx);
7304 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7305 Flags.setByValAlign(FrameAlign);
7307 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7310 Flags.setInConsecutiveRegs();
7311 Flags.setOrigAlign(OriginalAlignment);
7313 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7314 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7315 for (unsigned i = 0; i != NumRegs; ++i) {
7316 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7317 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7318 if (NumRegs > 1 && i == 0)
7319 MyFlags.Flags.setSplit();
7320 // if it isn't first piece, alignment must be 1
7322 MyFlags.Flags.setOrigAlign(1);
7323 Ins.push_back(MyFlags);
7325 if (NeedsRegBlock && Value == NumValues - 1)
7326 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7327 PartBase += VT.getStoreSize();
7331 // Call the target to set up the argument values.
7332 SmallVector<SDValue, 8> InVals;
7333 SDValue NewRoot = TLI->LowerFormalArguments(
7334 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7336 // Verify that the target's LowerFormalArguments behaved as expected.
7337 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7338 "LowerFormalArguments didn't return a valid chain!");
7339 assert(InVals.size() == Ins.size() &&
7340 "LowerFormalArguments didn't emit the correct number of values!");
7342 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7343 assert(InVals[i].getNode() &&
7344 "LowerFormalArguments emitted a null value!");
7345 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7346 "LowerFormalArguments emitted a value with the wrong type!");
7350 // Update the DAG with the new chain value resulting from argument lowering.
7351 DAG.setRoot(NewRoot);
7353 // Set up the argument values.
7356 if (!FuncInfo->CanLowerReturn) {
7357 // Create a virtual register for the sret pointer, and put in a copy
7358 // from the sret argument into it.
7359 SmallVector<EVT, 1> ValueVTs;
7360 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7361 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7362 MVT VT = ValueVTs[0].getSimpleVT();
7363 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7364 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7365 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7366 RegVT, VT, nullptr, AssertOp);
7368 MachineFunction& MF = SDB->DAG.getMachineFunction();
7369 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7370 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7371 FuncInfo->DemoteRegister = SRetReg;
7373 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7374 DAG.setRoot(NewRoot);
7376 // i indexes lowered arguments. Bump it past the hidden sret argument.
7377 // Idx indexes LLVM arguments. Don't touch it.
7381 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7383 SmallVector<SDValue, 4> ArgValues;
7384 SmallVector<EVT, 4> ValueVTs;
7385 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7386 unsigned NumValues = ValueVTs.size();
7388 // If this argument is unused then remember its value. It is used to generate
7389 // debugging information.
7390 if (I->use_empty() && NumValues) {
7391 SDB->setUnusedArgValue(I, InVals[i]);
7393 // Also remember any frame index for use in FastISel.
7394 if (FrameIndexSDNode *FI =
7395 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7396 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7399 for (unsigned Val = 0; Val != NumValues; ++Val) {
7400 EVT VT = ValueVTs[Val];
7401 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7402 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7404 if (!I->use_empty()) {
7405 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7406 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7407 AssertOp = ISD::AssertSext;
7408 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7409 AssertOp = ISD::AssertZext;
7411 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7412 NumParts, PartVT, VT,
7413 nullptr, AssertOp));
7419 // We don't need to do anything else for unused arguments.
7420 if (ArgValues.empty())
7423 // Note down frame index.
7424 if (FrameIndexSDNode *FI =
7425 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7426 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7428 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7429 SDB->getCurSDLoc());
7431 SDB->setValue(I, Res);
7432 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7433 if (LoadSDNode *LNode =
7434 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7435 if (FrameIndexSDNode *FI =
7436 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7437 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7440 // If this argument is live outside of the entry block, insert a copy from
7441 // wherever we got it to the vreg that other BB's will reference it as.
7442 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7443 // If we can, though, try to skip creating an unnecessary vreg.
7444 // FIXME: This isn't very clean... it would be nice to make this more
7445 // general. It's also subtly incompatible with the hacks FastISel
7447 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7448 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7449 FuncInfo->ValueMap[I] = Reg;
7453 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7454 FuncInfo->InitializeRegForValue(I);
7455 SDB->CopyToExportRegsIfNeeded(I);
7459 assert(i == InVals.size() && "Argument register count mismatch!");
7461 // Finally, if the target has anything special to do, allow it to do so.
7462 EmitFunctionEntryCode();
7465 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7466 /// ensure constants are generated when needed. Remember the virtual registers
7467 /// that need to be added to the Machine PHI nodes as input. We cannot just
7468 /// directly add them, because expansion might result in multiple MBB's for one
7469 /// BB. As such, the start of the BB might correspond to a different MBB than
7473 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7474 const TerminatorInst *TI = LLVMBB->getTerminator();
7476 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7478 // Check PHI nodes in successors that expect a value to be available from this
7480 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7481 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7482 if (!isa<PHINode>(SuccBB->begin())) continue;
7483 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7485 // If this terminator has multiple identical successors (common for
7486 // switches), only handle each succ once.
7487 if (!SuccsHandled.insert(SuccMBB).second)
7490 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7492 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7493 // nodes and Machine PHI nodes, but the incoming operands have not been
7495 for (BasicBlock::const_iterator I = SuccBB->begin();
7496 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7497 // Ignore dead phi's.
7498 if (PN->use_empty()) continue;
7501 if (PN->getType()->isEmptyTy())
7505 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7507 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7508 unsigned &RegOut = ConstantsOut[C];
7510 RegOut = FuncInfo.CreateRegs(C->getType());
7511 CopyValueToVirtualRegister(C, RegOut);
7515 DenseMap<const Value *, unsigned>::iterator I =
7516 FuncInfo.ValueMap.find(PHIOp);
7517 if (I != FuncInfo.ValueMap.end())
7520 assert(isa<AllocaInst>(PHIOp) &&
7521 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7522 "Didn't codegen value into a register!??");
7523 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7524 CopyValueToVirtualRegister(PHIOp, Reg);
7528 // Remember that this register needs to added to the machine PHI node as
7529 // the input for this MBB.
7530 SmallVector<EVT, 4> ValueVTs;
7531 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7532 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7533 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7534 EVT VT = ValueVTs[vti];
7535 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7536 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7537 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7538 Reg += NumRegisters;
7543 ConstantsOut.clear();
7546 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7549 SelectionDAGBuilder::StackProtectorDescriptor::
7550 AddSuccessorMBB(const BasicBlock *BB,
7551 MachineBasicBlock *ParentMBB,
7553 MachineBasicBlock *SuccMBB) {
7554 // If SuccBB has not been created yet, create it.
7556 MachineFunction *MF = ParentMBB->getParent();
7557 MachineFunction::iterator BBI = ParentMBB;
7558 SuccMBB = MF->CreateMachineBasicBlock(BB);
7559 MF->insert(++BBI, SuccMBB);
7561 // Add it as a successor of ParentMBB.
7562 ParentMBB->addSuccessor(
7563 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7567 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7568 MachineFunction::iterator I = MBB;
7569 if (++I == FuncInfo.MF->end())
7574 /// During lowering new call nodes can be created (such as memset, etc.).
7575 /// Those will become new roots of the current DAG, but complications arise
7576 /// when they are tail calls. In such cases, the call lowering will update
7577 /// the root, but the builder still needs to know that a tail call has been
7578 /// lowered in order to avoid generating an additional return.
7579 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7580 // If the node is null, we do have a tail call.
7581 if (MaybeTC.getNode() != nullptr)
7582 DAG.setRoot(MaybeTC);
7587 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7588 unsigned *TotalCases, unsigned First,
7590 assert(Last >= First);
7591 assert(TotalCases[Last] >= TotalCases[First]);
7593 APInt LowCase = Clusters[First].Low->getValue();
7594 APInt HighCase = Clusters[Last].High->getValue();
7595 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7597 // FIXME: A range of consecutive cases has 100% density, but only requires one
7598 // comparison to lower. We should discriminate against such consecutive ranges
7601 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7602 uint64_t Range = Diff + 1;
7605 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7607 assert(NumCases < UINT64_MAX / 100);
7608 assert(Range >= NumCases);
7610 return NumCases * 100 >= Range * MinJumpTableDensity;
7613 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7614 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7615 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7618 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7619 unsigned First, unsigned Last,
7620 const SwitchInst *SI,
7621 MachineBasicBlock *DefaultMBB,
7622 CaseCluster &JTCluster) {
7623 assert(First <= Last);
7625 uint32_t Weight = 0;
7626 unsigned NumCmps = 0;
7627 std::vector<MachineBasicBlock*> Table;
7628 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7629 for (unsigned I = First; I <= Last; ++I) {
7630 assert(Clusters[I].Kind == CC_Range);
7631 Weight += Clusters[I].Weight;
7632 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7633 APInt Low = Clusters[I].Low->getValue();
7634 APInt High = Clusters[I].High->getValue();
7635 NumCmps += (Low == High) ? 1 : 2;
7637 // Fill the gap between this and the previous cluster.
7638 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7639 assert(PreviousHigh.slt(Low));
7640 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7641 for (uint64_t J = 0; J < Gap; J++)
7642 Table.push_back(DefaultMBB);
7644 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7645 for (uint64_t J = 0; J < ClusterSize; ++J)
7646 Table.push_back(Clusters[I].MBB);
7647 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7650 unsigned NumDests = JTWeights.size();
7651 if (isSuitableForBitTests(NumDests, NumCmps,
7652 Clusters[First].Low->getValue(),
7653 Clusters[Last].High->getValue())) {
7654 // Clusters[First..Last] should be lowered as bit tests instead.
7658 // Create the MBB that will load from and jump through the table.
7659 // Note: We create it here, but it's not inserted into the function yet.
7660 MachineFunction *CurMF = FuncInfo.MF;
7661 MachineBasicBlock *JumpTableMBB =
7662 CurMF->CreateMachineBasicBlock(SI->getParent());
7664 // Add successors. Note: use table order for determinism.
7665 SmallPtrSet<MachineBasicBlock *, 8> Done;
7666 for (MachineBasicBlock *Succ : Table) {
7667 if (Done.count(Succ))
7669 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7674 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7675 ->createJumpTableIndex(Table);
7677 // Set up the jump table info.
7678 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7679 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7680 Clusters[Last].High->getValue(), SI->getCondition(),
7682 JTCases.emplace_back(std::move(JTH), std::move(JT));
7684 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7685 JTCases.size() - 1, Weight);
7689 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7690 const SwitchInst *SI,
7691 MachineBasicBlock *DefaultMBB) {
7693 // Clusters must be non-empty, sorted, and only contain Range clusters.
7694 assert(!Clusters.empty());
7695 for (CaseCluster &C : Clusters)
7696 assert(C.Kind == CC_Range);
7697 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7698 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7702 if (!areJTsAllowed(TLI))
7705 const int64_t N = Clusters.size();
7706 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7708 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7709 SmallVector<unsigned, 8> TotalCases(N);
7711 for (unsigned i = 0; i < N; ++i) {
7712 APInt Hi = Clusters[i].High->getValue();
7713 APInt Lo = Clusters[i].Low->getValue();
7714 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7716 TotalCases[i] += TotalCases[i - 1];
7719 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7720 // Cheap case: the whole range might be suitable for jump table.
7721 CaseCluster JTCluster;
7722 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7723 Clusters[0] = JTCluster;
7729 // The algorithm below is not suitable for -O0.
7730 if (TM.getOptLevel() == CodeGenOpt::None)
7733 // Split Clusters into minimum number of dense partitions. The algorithm uses
7734 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7735 // for the Case Statement'" (1994), but builds the MinPartitions array in
7736 // reverse order to make it easier to reconstruct the partitions in ascending
7737 // order. In the choice between two optimal partitionings, it picks the one
7738 // which yields more jump tables.
7740 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7741 SmallVector<unsigned, 8> MinPartitions(N);
7742 // LastElement[i] is the last element of the partition starting at i.
7743 SmallVector<unsigned, 8> LastElement(N);
7744 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7745 SmallVector<unsigned, 8> NumTables(N);
7747 // Base case: There is only one way to partition Clusters[N-1].
7748 MinPartitions[N - 1] = 1;
7749 LastElement[N - 1] = N - 1;
7750 assert(MinJumpTableSize > 1);
7751 NumTables[N - 1] = 0;
7753 // Note: loop indexes are signed to avoid underflow.
7754 for (int64_t i = N - 2; i >= 0; i--) {
7755 // Find optimal partitioning of Clusters[i..N-1].
7756 // Baseline: Put Clusters[i] into a partition on its own.
7757 MinPartitions[i] = MinPartitions[i + 1] + 1;
7759 NumTables[i] = NumTables[i + 1];
7761 // Search for a solution that results in fewer partitions.
7762 for (int64_t j = N - 1; j > i; j--) {
7763 // Try building a partition from Clusters[i..j].
7764 if (isDense(Clusters, &TotalCases[0], i, j)) {
7765 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7766 bool IsTable = j - i + 1 >= MinJumpTableSize;
7767 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7769 // If this j leads to fewer partitions, or same number of partitions
7770 // with more lookup tables, it is a better partitioning.
7771 if (NumPartitions < MinPartitions[i] ||
7772 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7773 MinPartitions[i] = NumPartitions;
7775 NumTables[i] = Tables;
7781 // Iterate over the partitions, replacing some with jump tables in-place.
7782 unsigned DstIndex = 0;
7783 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7784 Last = LastElement[First];
7785 assert(Last >= First);
7786 assert(DstIndex <= First);
7787 unsigned NumClusters = Last - First + 1;
7789 CaseCluster JTCluster;
7790 if (NumClusters >= MinJumpTableSize &&
7791 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7792 Clusters[DstIndex++] = JTCluster;
7794 for (unsigned I = First; I <= Last; ++I)
7795 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7798 Clusters.resize(DstIndex);
7801 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7802 // FIXME: Using the pointer type doesn't seem ideal.
7803 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7804 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7808 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7811 const APInt &High) {
7812 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7813 // range of cases both require only one branch to lower. Just looking at the
7814 // number of clusters and destinations should be enough to decide whether to
7817 // To lower a range with bit tests, the range must fit the bitwidth of a
7819 if (!rangeFitsInWord(Low, High))
7822 // Decide whether it's profitable to lower this range with bit tests. Each
7823 // destination requires a bit test and branch, and there is an overall range
7824 // check branch. For a small number of clusters, separate comparisons might be
7825 // cheaper, and for many destinations, splitting the range might be better.
7826 return (NumDests == 1 && NumCmps >= 3) ||
7827 (NumDests == 2 && NumCmps >= 5) ||
7828 (NumDests == 3 && NumCmps >= 6);
7831 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7832 unsigned First, unsigned Last,
7833 const SwitchInst *SI,
7834 CaseCluster &BTCluster) {
7835 assert(First <= Last);
7839 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7840 unsigned NumCmps = 0;
7841 for (int64_t I = First; I <= Last; ++I) {
7842 assert(Clusters[I].Kind == CC_Range);
7843 Dests.set(Clusters[I].MBB->getNumber());
7844 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7846 unsigned NumDests = Dests.count();
7848 APInt Low = Clusters[First].Low->getValue();
7849 APInt High = Clusters[Last].High->getValue();
7850 assert(Low.slt(High));
7852 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7858 const int BitWidth = DAG.getTargetLoweringInfo()
7859 .getPointerTy(DAG.getDataLayout())
7861 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7863 // Check if the clusters cover a contiguous range such that no value in the
7864 // range will jump to the default statement.
7865 bool ContiguousRange = true;
7866 for (int64_t I = First + 1; I <= Last; ++I) {
7867 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7868 ContiguousRange = false;
7873 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7874 // Optimize the case where all the case values fit in a word without having
7875 // to subtract minValue. In this case, we can optimize away the subtraction.
7876 LowBound = APInt::getNullValue(Low.getBitWidth());
7878 ContiguousRange = false;
7881 CmpRange = High - Low;
7885 uint32_t TotalWeight = 0;
7886 for (unsigned i = First; i <= Last; ++i) {
7887 // Find the CaseBits for this destination.
7889 for (j = 0; j < CBV.size(); ++j)
7890 if (CBV[j].BB == Clusters[i].MBB)
7892 if (j == CBV.size())
7893 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7894 CaseBits *CB = &CBV[j];
7896 // Update Mask, Bits and ExtraWeight.
7897 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7898 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7899 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7900 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7901 CB->Bits += Hi - Lo + 1;
7902 CB->ExtraWeight += Clusters[i].Weight;
7903 TotalWeight += Clusters[i].Weight;
7904 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7908 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7909 // Sort by weight first, number of bits second.
7910 if (a.ExtraWeight != b.ExtraWeight)
7911 return a.ExtraWeight > b.ExtraWeight;
7912 return a.Bits > b.Bits;
7915 for (auto &CB : CBV) {
7916 MachineBasicBlock *BitTestBB =
7917 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7918 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7920 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7921 SI->getCondition(), -1U, MVT::Other, false,
7922 ContiguousRange, nullptr, nullptr, std::move(BTI),
7925 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7926 BitTestCases.size() - 1, TotalWeight);
7930 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7931 const SwitchInst *SI) {
7932 // Partition Clusters into as few subsets as possible, where each subset has a
7933 // range that fits in a machine word and has <= 3 unique destinations.
7936 // Clusters must be sorted and contain Range or JumpTable clusters.
7937 assert(!Clusters.empty());
7938 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7939 for (const CaseCluster &C : Clusters)
7940 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7941 for (unsigned i = 1; i < Clusters.size(); ++i)
7942 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7945 // The algorithm below is not suitable for -O0.
7946 if (TM.getOptLevel() == CodeGenOpt::None)
7949 // If target does not have legal shift left, do not emit bit tests at all.
7950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7951 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7952 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7955 int BitWidth = PTy.getSizeInBits();
7956 const int64_t N = Clusters.size();
7958 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7959 SmallVector<unsigned, 8> MinPartitions(N);
7960 // LastElement[i] is the last element of the partition starting at i.
7961 SmallVector<unsigned, 8> LastElement(N);
7963 // FIXME: This might not be the best algorithm for finding bit test clusters.
7965 // Base case: There is only one way to partition Clusters[N-1].
7966 MinPartitions[N - 1] = 1;
7967 LastElement[N - 1] = N - 1;
7969 // Note: loop indexes are signed to avoid underflow.
7970 for (int64_t i = N - 2; i >= 0; --i) {
7971 // Find optimal partitioning of Clusters[i..N-1].
7972 // Baseline: Put Clusters[i] into a partition on its own.
7973 MinPartitions[i] = MinPartitions[i + 1] + 1;
7976 // Search for a solution that results in fewer partitions.
7977 // Note: the search is limited by BitWidth, reducing time complexity.
7978 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7979 // Try building a partition from Clusters[i..j].
7982 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7983 Clusters[j].High->getValue()))
7986 // Check nbr of destinations and cluster types.
7987 // FIXME: This works, but doesn't seem very efficient.
7988 bool RangesOnly = true;
7989 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7990 for (int64_t k = i; k <= j; k++) {
7991 if (Clusters[k].Kind != CC_Range) {
7995 Dests.set(Clusters[k].MBB->getNumber());
7997 if (!RangesOnly || Dests.count() > 3)
8000 // Check if it's a better partition.
8001 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8002 if (NumPartitions < MinPartitions[i]) {
8003 // Found a better partition.
8004 MinPartitions[i] = NumPartitions;
8010 // Iterate over the partitions, replacing with bit-test clusters in-place.
8011 unsigned DstIndex = 0;
8012 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8013 Last = LastElement[First];
8014 assert(First <= Last);
8015 assert(DstIndex <= First);
8017 CaseCluster BitTestCluster;
8018 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8019 Clusters[DstIndex++] = BitTestCluster;
8021 size_t NumClusters = Last - First + 1;
8022 std::memmove(&Clusters[DstIndex], &Clusters[First],
8023 sizeof(Clusters[0]) * NumClusters);
8024 DstIndex += NumClusters;
8027 Clusters.resize(DstIndex);
8030 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8031 MachineBasicBlock *SwitchMBB,
8032 MachineBasicBlock *DefaultMBB) {
8033 MachineFunction *CurMF = FuncInfo.MF;
8034 MachineBasicBlock *NextMBB = nullptr;
8035 MachineFunction::iterator BBI = W.MBB;
8036 if (++BBI != FuncInfo.MF->end())
8039 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8041 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8043 if (Size == 2 && W.MBB == SwitchMBB) {
8044 // If any two of the cases has the same destination, and if one value
8045 // is the same as the other, but has one bit unset that the other has set,
8046 // use bit manipulation to do two compares at once. For example:
8047 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8048 // TODO: This could be extended to merge any 2 cases in switches with 3
8050 // TODO: Handle cases where W.CaseBB != SwitchBB.
8051 CaseCluster &Small = *W.FirstCluster;
8052 CaseCluster &Big = *W.LastCluster;
8054 if (Small.Low == Small.High && Big.Low == Big.High &&
8055 Small.MBB == Big.MBB) {
8056 const APInt &SmallValue = Small.Low->getValue();
8057 const APInt &BigValue = Big.Low->getValue();
8059 // Check that there is only one bit different.
8060 APInt CommonBit = BigValue ^ SmallValue;
8061 if (CommonBit.isPowerOf2()) {
8062 SDValue CondLHS = getValue(Cond);
8063 EVT VT = CondLHS.getValueType();
8064 SDLoc DL = getCurSDLoc();
8066 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8067 DAG.getConstant(CommonBit, DL, VT));
8068 SDValue Cond = DAG.getSetCC(
8069 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8072 // Update successor info.
8073 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8074 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8075 addSuccessorWithWeight(
8076 SwitchMBB, DefaultMBB,
8077 // The default destination is the first successor in IR.
8078 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8081 // Insert the true branch.
8083 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8084 DAG.getBasicBlock(Small.MBB));
8085 // Insert the false branch.
8086 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8087 DAG.getBasicBlock(DefaultMBB));
8089 DAG.setRoot(BrCond);
8095 if (TM.getOptLevel() != CodeGenOpt::None) {
8096 // Order cases by weight so the most likely case will be checked first.
8097 std::sort(W.FirstCluster, W.LastCluster + 1,
8098 [](const CaseCluster &a, const CaseCluster &b) {
8099 return a.Weight > b.Weight;
8102 // Rearrange the case blocks so that the last one falls through if possible
8103 // without without changing the order of weights.
8104 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8106 if (I->Weight > W.LastCluster->Weight)
8108 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8109 std::swap(*I, *W.LastCluster);
8115 // Compute total weight.
8116 uint32_t DefaultWeight = W.DefaultWeight;
8117 uint32_t UnhandledWeights = DefaultWeight;
8118 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8119 UnhandledWeights += I->Weight;
8120 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8123 MachineBasicBlock *CurMBB = W.MBB;
8124 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8125 MachineBasicBlock *Fallthrough;
8126 if (I == W.LastCluster) {
8127 // For the last cluster, fall through to the default destination.
8128 Fallthrough = DefaultMBB;
8130 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8131 CurMF->insert(BBI, Fallthrough);
8132 // Put Cond in a virtual register to make it available from the new blocks.
8133 ExportFromCurrentBlock(Cond);
8135 UnhandledWeights -= I->Weight;
8138 case CC_JumpTable: {
8139 // FIXME: Optimize away range check based on pivot comparisons.
8140 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8141 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8143 // The jump block hasn't been inserted yet; insert it here.
8144 MachineBasicBlock *JumpMBB = JT->MBB;
8145 CurMF->insert(BBI, JumpMBB);
8147 uint32_t JumpWeight = I->Weight;
8148 uint32_t FallthroughWeight = UnhandledWeights;
8150 // If the default statement is a target of the jump table, we evenly
8151 // distribute the default weight to successors of CurMBB. Also update
8152 // the weight on the edge from JumpMBB to Fallthrough.
8153 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8154 SE = JumpMBB->succ_end();
8156 if (*SI == DefaultMBB) {
8157 JumpWeight += DefaultWeight / 2;
8158 FallthroughWeight -= DefaultWeight / 2;
8159 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8164 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8165 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8167 // The jump table header will be inserted in our current block, do the
8168 // range check, and fall through to our fallthrough block.
8169 JTH->HeaderBB = CurMBB;
8170 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8172 // If we're in the right place, emit the jump table header right now.
8173 if (CurMBB == SwitchMBB) {
8174 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8175 JTH->Emitted = true;
8180 // FIXME: Optimize away range check based on pivot comparisons.
8181 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8183 // The bit test blocks haven't been inserted yet; insert them here.
8184 for (BitTestCase &BTC : BTB->Cases)
8185 CurMF->insert(BBI, BTC.ThisBB);
8187 // Fill in fields of the BitTestBlock.
8188 BTB->Parent = CurMBB;
8189 BTB->Default = Fallthrough;
8191 BTB->DefaultWeight = UnhandledWeights;
8192 // If the cases in bit test don't form a contiguous range, we evenly
8193 // distribute the weight on the edge to Fallthrough to two successors
8195 if (!BTB->ContiguousRange) {
8196 BTB->Weight += DefaultWeight / 2;
8197 BTB->DefaultWeight -= DefaultWeight / 2;
8200 // If we're in the right place, emit the bit test header right now.
8201 if (CurMBB == SwitchMBB) {
8202 visitBitTestHeader(*BTB, SwitchMBB);
8203 BTB->Emitted = true;
8208 const Value *RHS, *LHS, *MHS;
8210 if (I->Low == I->High) {
8211 // Check Cond == I->Low.
8217 // Check I->Low <= Cond <= I->High.
8224 // The false weight is the sum of all unhandled cases.
8225 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8228 if (CurMBB == SwitchMBB)
8229 visitSwitchCase(CB, SwitchMBB);
8231 SwitchCases.push_back(CB);
8236 CurMBB = Fallthrough;
8240 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8241 CaseClusterIt First,
8242 CaseClusterIt Last) {
8243 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8244 if (X.Weight != CC.Weight)
8245 return X.Weight > CC.Weight;
8247 // Ties are broken by comparing the case value.
8248 return X.Low->getValue().slt(CC.Low->getValue());
8252 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8253 const SwitchWorkListItem &W,
8255 MachineBasicBlock *SwitchMBB) {
8256 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8257 "Clusters not sorted?");
8259 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8261 // Balance the tree based on branch weights to create a near-optimal (in terms
8262 // of search time given key frequency) binary search tree. See e.g. Kurt
8263 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8264 CaseClusterIt LastLeft = W.FirstCluster;
8265 CaseClusterIt FirstRight = W.LastCluster;
8266 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8267 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8269 // Move LastLeft and FirstRight towards each other from opposite directions to
8270 // find a partitioning of the clusters which balances the weight on both
8271 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8272 // taken to ensure 0-weight nodes are distributed evenly.
8274 while (LastLeft + 1 < FirstRight) {
8275 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8276 LeftWeight += (++LastLeft)->Weight;
8278 RightWeight += (--FirstRight)->Weight;
8283 // Our binary search tree differs from a typical BST in that ours can have up
8284 // to three values in each leaf. The pivot selection above doesn't take that
8285 // into account, which means the tree might require more nodes and be less
8286 // efficient. We compensate for this here.
8288 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8289 unsigned NumRight = W.LastCluster - FirstRight + 1;
8291 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8292 // If one side has less than 3 clusters, and the other has more than 3,
8293 // consider taking a cluster from the other side.
8295 if (NumLeft < NumRight) {
8296 // Consider moving the first cluster on the right to the left side.
8297 CaseCluster &CC = *FirstRight;
8298 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8299 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8300 if (LeftSideRank <= RightSideRank) {
8301 // Moving the cluster to the left does not demote it.
8307 assert(NumRight < NumLeft);
8308 // Consider moving the last element on the left to the right side.
8309 CaseCluster &CC = *LastLeft;
8310 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8311 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8312 if (RightSideRank <= LeftSideRank) {
8313 // Moving the cluster to the right does not demot it.
8323 assert(LastLeft + 1 == FirstRight);
8324 assert(LastLeft >= W.FirstCluster);
8325 assert(FirstRight <= W.LastCluster);
8327 // Use the first element on the right as pivot since we will make less-than
8328 // comparisons against it.
8329 CaseClusterIt PivotCluster = FirstRight;
8330 assert(PivotCluster > W.FirstCluster);
8331 assert(PivotCluster <= W.LastCluster);
8333 CaseClusterIt FirstLeft = W.FirstCluster;
8334 CaseClusterIt LastRight = W.LastCluster;
8336 const ConstantInt *Pivot = PivotCluster->Low;
8338 // New blocks will be inserted immediately after the current one.
8339 MachineFunction::iterator BBI = W.MBB;
8342 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8343 // we can branch to its destination directly if it's squeezed exactly in
8344 // between the known lower bound and Pivot - 1.
8345 MachineBasicBlock *LeftMBB;
8346 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8347 FirstLeft->Low == W.GE &&
8348 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8349 LeftMBB = FirstLeft->MBB;
8351 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8352 FuncInfo.MF->insert(BBI, LeftMBB);
8354 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8355 // Put Cond in a virtual register to make it available from the new blocks.
8356 ExportFromCurrentBlock(Cond);
8359 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8360 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8361 // directly if RHS.High equals the current upper bound.
8362 MachineBasicBlock *RightMBB;
8363 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8364 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8365 RightMBB = FirstRight->MBB;
8367 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8368 FuncInfo.MF->insert(BBI, RightMBB);
8370 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8371 // Put Cond in a virtual register to make it available from the new blocks.
8372 ExportFromCurrentBlock(Cond);
8375 // Create the CaseBlock record that will be used to lower the branch.
8376 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8377 LeftWeight, RightWeight);
8379 if (W.MBB == SwitchMBB)
8380 visitSwitchCase(CB, SwitchMBB);
8382 SwitchCases.push_back(CB);
8385 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8386 // Extract cases from the switch.
8387 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8388 CaseClusterVector Clusters;
8389 Clusters.reserve(SI.getNumCases());
8390 for (auto I : SI.cases()) {
8391 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8392 const ConstantInt *CaseVal = I.getCaseValue();
8394 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8395 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8398 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8400 // Cluster adjacent cases with the same destination. We do this at all
8401 // optimization levels because it's cheap to do and will make codegen faster
8402 // if there are many clusters.
8403 sortAndRangeify(Clusters);
8405 if (TM.getOptLevel() != CodeGenOpt::None) {
8406 // Replace an unreachable default with the most popular destination.
8407 // FIXME: Exploit unreachable default more aggressively.
8408 bool UnreachableDefault =
8409 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8410 if (UnreachableDefault && !Clusters.empty()) {
8411 DenseMap<const BasicBlock *, unsigned> Popularity;
8412 unsigned MaxPop = 0;
8413 const BasicBlock *MaxBB = nullptr;
8414 for (auto I : SI.cases()) {
8415 const BasicBlock *BB = I.getCaseSuccessor();
8416 if (++Popularity[BB] > MaxPop) {
8417 MaxPop = Popularity[BB];
8422 assert(MaxPop > 0 && MaxBB);
8423 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8425 // Remove cases that were pointing to the destination that is now the
8427 CaseClusterVector New;
8428 New.reserve(Clusters.size());
8429 for (CaseCluster &CC : Clusters) {
8430 if (CC.MBB != DefaultMBB)
8433 Clusters = std::move(New);
8437 // If there is only the default destination, jump there directly.
8438 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8439 if (Clusters.empty()) {
8440 SwitchMBB->addSuccessor(DefaultMBB);
8441 if (DefaultMBB != NextBlock(SwitchMBB)) {
8442 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8443 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8448 findJumpTables(Clusters, &SI, DefaultMBB);
8449 findBitTestClusters(Clusters, &SI);
8452 dbgs() << "Case clusters: ";
8453 for (const CaseCluster &C : Clusters) {
8454 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8455 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8457 C.Low->getValue().print(dbgs(), true);
8458 if (C.Low != C.High) {
8460 C.High->getValue().print(dbgs(), true);
8467 assert(!Clusters.empty());
8468 SwitchWorkList WorkList;
8469 CaseClusterIt First = Clusters.begin();
8470 CaseClusterIt Last = Clusters.end() - 1;
8471 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8472 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8474 while (!WorkList.empty()) {
8475 SwitchWorkListItem W = WorkList.back();
8476 WorkList.pop_back();
8477 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8479 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8480 // For optimized builds, lower large range as a balanced binary tree.
8481 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8485 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);