1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 // Update machine-CFG edges.
1164 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1165 MachineBasicBlock *CatchingMBB = FuncInfo.MBBMap[I.getNormalDest()];
1166 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1167 PadMBB->addSuccessor(CatchingMBB);
1168 PadMBB->addSuccessor(UnwindMBB);
1170 CatchingMBB->setIsEHFuncletEntry();
1171 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1172 MMI.setHasEHFunclets(true);
1175 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1176 // Update machine-CFG edge.
1177 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1178 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1179 PadMBB->addSuccessor(TargetMBB);
1181 // Create the terminator node.
1182 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1183 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1187 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1188 // If this unwinds to caller, we don't need a DAG node hanging around.
1189 if (!I.hasUnwindDest())
1192 // Update machine-CFG edge.
1193 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1194 MachineBasicBlock *UnwindMBB = FuncInfo.MBBMap[I.getUnwindDest()];
1195 PadMBB->addSuccessor(UnwindMBB);
1198 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1199 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1200 MMI.setHasEHFunclets(true);
1201 report_fatal_error("visitCleanupPad not yet implemented!");
1204 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1205 report_fatal_error("visitCleanupRet not yet implemented!");
1208 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1209 report_fatal_error("visitTerminatePad not yet implemented!");
1212 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1214 auto &DL = DAG.getDataLayout();
1215 SDValue Chain = getControlRoot();
1216 SmallVector<ISD::OutputArg, 8> Outs;
1217 SmallVector<SDValue, 8> OutVals;
1219 if (!FuncInfo.CanLowerReturn) {
1220 unsigned DemoteReg = FuncInfo.DemoteRegister;
1221 const Function *F = I.getParent()->getParent();
1223 // Emit a store of the return value through the virtual register.
1224 // Leave Outs empty so that LowerReturn won't try to load return
1225 // registers the usual way.
1226 SmallVector<EVT, 1> PtrValueVTs;
1227 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1230 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1231 SDValue RetOp = getValue(I.getOperand(0));
1233 SmallVector<EVT, 4> ValueVTs;
1234 SmallVector<uint64_t, 4> Offsets;
1235 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1236 unsigned NumValues = ValueVTs.size();
1238 SmallVector<SDValue, 4> Chains(NumValues);
1239 for (unsigned i = 0; i != NumValues; ++i) {
1240 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1241 RetPtr.getValueType(), RetPtr,
1242 DAG.getIntPtrConstant(Offsets[i],
1245 DAG.getStore(Chain, getCurSDLoc(),
1246 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1247 // FIXME: better loc info would be nice.
1248 Add, MachinePointerInfo(), false, false, 0);
1251 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1252 MVT::Other, Chains);
1253 } else if (I.getNumOperands() != 0) {
1254 SmallVector<EVT, 4> ValueVTs;
1255 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1256 unsigned NumValues = ValueVTs.size();
1258 SDValue RetOp = getValue(I.getOperand(0));
1260 const Function *F = I.getParent()->getParent();
1262 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1263 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1265 ExtendKind = ISD::SIGN_EXTEND;
1266 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1268 ExtendKind = ISD::ZERO_EXTEND;
1270 LLVMContext &Context = F->getContext();
1271 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1274 for (unsigned j = 0; j != NumValues; ++j) {
1275 EVT VT = ValueVTs[j];
1277 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1278 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1280 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1281 MVT PartVT = TLI.getRegisterType(Context, VT);
1282 SmallVector<SDValue, 4> Parts(NumParts);
1283 getCopyToParts(DAG, getCurSDLoc(),
1284 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1285 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1287 // 'inreg' on function refers to return value
1288 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1292 // Propagate extension type if any
1293 if (ExtendKind == ISD::SIGN_EXTEND)
1295 else if (ExtendKind == ISD::ZERO_EXTEND)
1298 for (unsigned i = 0; i < NumParts; ++i) {
1299 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1300 VT, /*isfixed=*/true, 0, 0));
1301 OutVals.push_back(Parts[i]);
1307 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1308 CallingConv::ID CallConv =
1309 DAG.getMachineFunction().getFunction()->getCallingConv();
1310 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1311 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1313 // Verify that the target's LowerReturn behaved as expected.
1314 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1315 "LowerReturn didn't return a valid chain!");
1317 // Update the DAG with the new chain value resulting from return lowering.
1321 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1322 /// created for it, emit nodes to copy the value into the virtual
1324 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1326 if (V->getType()->isEmptyTy())
1329 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1330 if (VMI != FuncInfo.ValueMap.end()) {
1331 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1332 CopyValueToVirtualRegister(V, VMI->second);
1336 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1337 /// the current basic block, add it to ValueMap now so that we'll get a
1339 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1340 // No need to export constants.
1341 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1343 // Already exported?
1344 if (FuncInfo.isExportedInst(V)) return;
1346 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1347 CopyValueToVirtualRegister(V, Reg);
1350 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1351 const BasicBlock *FromBB) {
1352 // The operands of the setcc have to be in this block. We don't know
1353 // how to export them from some other block.
1354 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1355 // Can export from current BB.
1356 if (VI->getParent() == FromBB)
1359 // Is already exported, noop.
1360 return FuncInfo.isExportedInst(V);
1363 // If this is an argument, we can export it if the BB is the entry block or
1364 // if it is already exported.
1365 if (isa<Argument>(V)) {
1366 if (FromBB == &FromBB->getParent()->getEntryBlock())
1369 // Otherwise, can only export this if it is already exported.
1370 return FuncInfo.isExportedInst(V);
1373 // Otherwise, constants can always be exported.
1377 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1378 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1379 const MachineBasicBlock *Dst) const {
1380 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1383 const BasicBlock *SrcBB = Src->getBasicBlock();
1384 const BasicBlock *DstBB = Dst->getBasicBlock();
1385 return BPI->getEdgeWeight(SrcBB, DstBB);
1388 void SelectionDAGBuilder::
1389 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1390 uint32_t Weight /* = 0 */) {
1392 Weight = getEdgeWeight(Src, Dst);
1393 Src->addSuccessor(Dst, Weight);
1397 static bool InBlock(const Value *V, const BasicBlock *BB) {
1398 if (const Instruction *I = dyn_cast<Instruction>(V))
1399 return I->getParent() == BB;
1403 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1404 /// This function emits a branch and is used at the leaves of an OR or an
1405 /// AND operator tree.
1408 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1409 MachineBasicBlock *TBB,
1410 MachineBasicBlock *FBB,
1411 MachineBasicBlock *CurBB,
1412 MachineBasicBlock *SwitchBB,
1415 const BasicBlock *BB = CurBB->getBasicBlock();
1417 // If the leaf of the tree is a comparison, merge the condition into
1419 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1420 // The operands of the cmp have to be in this block. We don't know
1421 // how to export them from some other block. If this is the first block
1422 // of the sequence, no exporting is needed.
1423 if (CurBB == SwitchBB ||
1424 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1425 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1426 ISD::CondCode Condition;
1427 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1428 Condition = getICmpCondCode(IC->getPredicate());
1430 const FCmpInst *FC = cast<FCmpInst>(Cond);
1431 Condition = getFCmpCondCode(FC->getPredicate());
1432 if (TM.Options.NoNaNsFPMath)
1433 Condition = getFCmpCodeWithoutNaN(Condition);
1436 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1437 TBB, FBB, CurBB, TWeight, FWeight);
1438 SwitchCases.push_back(CB);
1443 // Create a CaseBlock record representing this branch.
1444 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1445 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1446 SwitchCases.push_back(CB);
1449 /// Scale down both weights to fit into uint32_t.
1450 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1451 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1452 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1453 NewTrue = NewTrue / Scale;
1454 NewFalse = NewFalse / Scale;
1457 /// FindMergedConditions - If Cond is an expression like
1458 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1459 MachineBasicBlock *TBB,
1460 MachineBasicBlock *FBB,
1461 MachineBasicBlock *CurBB,
1462 MachineBasicBlock *SwitchBB,
1463 Instruction::BinaryOps Opc,
1466 // If this node is not part of the or/and tree, emit it as a branch.
1467 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1468 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1469 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1470 BOp->getParent() != CurBB->getBasicBlock() ||
1471 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1472 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1473 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1478 // Create TmpBB after CurBB.
1479 MachineFunction::iterator BBI = CurBB;
1480 MachineFunction &MF = DAG.getMachineFunction();
1481 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1482 CurBB->getParent()->insert(++BBI, TmpBB);
1484 if (Opc == Instruction::Or) {
1485 // Codegen X | Y as:
1494 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1495 // The requirement is that
1496 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1497 // = TrueProb for original BB.
1498 // Assuming the original weights are A and B, one choice is to set BB1's
1499 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1501 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1502 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1503 // TmpBB, but the math is more complicated.
1505 uint64_t NewTrueWeight = TWeight;
1506 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1507 ScaleWeights(NewTrueWeight, NewFalseWeight);
1508 // Emit the LHS condition.
1509 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1510 NewTrueWeight, NewFalseWeight);
1512 NewTrueWeight = TWeight;
1513 NewFalseWeight = 2 * (uint64_t)FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the RHS condition into TmpBB.
1516 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 assert(Opc == Instruction::And && "Unknown merge op!");
1520 // Codegen X & Y as:
1528 // This requires creation of TmpBB after CurBB.
1530 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1531 // The requirement is that
1532 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1533 // = FalseProb for original BB.
1534 // Assuming the original weights are A and B, one choice is to set BB1's
1535 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1537 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1539 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1540 uint64_t NewFalseWeight = FWeight;
1541 ScaleWeights(NewTrueWeight, NewFalseWeight);
1542 // Emit the LHS condition.
1543 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1544 NewTrueWeight, NewFalseWeight);
1546 NewTrueWeight = 2 * (uint64_t)TWeight;
1547 NewFalseWeight = FWeight;
1548 ScaleWeights(NewTrueWeight, NewFalseWeight);
1549 // Emit the RHS condition into TmpBB.
1550 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1551 NewTrueWeight, NewFalseWeight);
1555 /// If the set of cases should be emitted as a series of branches, return true.
1556 /// If we should emit this as a bunch of and/or'd together conditions, return
1559 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1560 if (Cases.size() != 2) return true;
1562 // If this is two comparisons of the same values or'd or and'd together, they
1563 // will get folded into a single comparison, so don't emit two blocks.
1564 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1565 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1566 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1567 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1571 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1572 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1573 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1574 Cases[0].CC == Cases[1].CC &&
1575 isa<Constant>(Cases[0].CmpRHS) &&
1576 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1577 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1579 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1586 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1587 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1589 // Update machine-CFG edges.
1590 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1592 if (I.isUnconditional()) {
1593 // Update machine-CFG edges.
1594 BrMBB->addSuccessor(Succ0MBB);
1596 // If this is not a fall-through branch or optimizations are switched off,
1598 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1599 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1600 MVT::Other, getControlRoot(),
1601 DAG.getBasicBlock(Succ0MBB)));
1606 // If this condition is one of the special cases we handle, do special stuff
1608 const Value *CondVal = I.getCondition();
1609 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1611 // If this is a series of conditions that are or'd or and'd together, emit
1612 // this as a sequence of branches instead of setcc's with and/or operations.
1613 // As long as jumps are not expensive, this should improve performance.
1614 // For example, instead of something like:
1627 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1628 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1629 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1630 BOp->getOpcode() == Instruction::Or)) {
1631 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1632 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1633 getEdgeWeight(BrMBB, Succ1MBB));
1634 // If the compares in later blocks need to use values not currently
1635 // exported from this block, export them now. This block should always
1636 // be the first entry.
1637 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1639 // Allow some cases to be rejected.
1640 if (ShouldEmitAsBranches(SwitchCases)) {
1641 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1642 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1643 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1646 // Emit the branch for this block.
1647 visitSwitchCase(SwitchCases[0], BrMBB);
1648 SwitchCases.erase(SwitchCases.begin());
1652 // Okay, we decided not to do this, remove any inserted MBB's and clear
1654 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1655 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1657 SwitchCases.clear();
1661 // Create a CaseBlock record representing this branch.
1662 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1663 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1665 // Use visitSwitchCase to actually insert the fast branch sequence for this
1667 visitSwitchCase(CB, BrMBB);
1670 /// visitSwitchCase - Emits the necessary code to represent a single node in
1671 /// the binary search tree resulting from lowering a switch instruction.
1672 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1673 MachineBasicBlock *SwitchBB) {
1675 SDValue CondLHS = getValue(CB.CmpLHS);
1676 SDLoc dl = getCurSDLoc();
1678 // Build the setcc now.
1680 // Fold "(X == true)" to X and "(X == false)" to !X to
1681 // handle common cases produced by branch lowering.
1682 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1683 CB.CC == ISD::SETEQ)
1685 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1686 CB.CC == ISD::SETEQ) {
1687 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1688 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1690 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1692 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1694 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1695 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1697 SDValue CmpOp = getValue(CB.CmpMHS);
1698 EVT VT = CmpOp.getValueType();
1700 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1701 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1704 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1705 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1706 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1707 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1711 // Update successor info
1712 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1713 // TrueBB and FalseBB are always different unless the incoming IR is
1714 // degenerate. This only happens when running llc on weird IR.
1715 if (CB.TrueBB != CB.FalseBB)
1716 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1718 // If the lhs block is the next block, invert the condition so that we can
1719 // fall through to the lhs instead of the rhs block.
1720 if (CB.TrueBB == NextBlock(SwitchBB)) {
1721 std::swap(CB.TrueBB, CB.FalseBB);
1722 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1723 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1726 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1727 MVT::Other, getControlRoot(), Cond,
1728 DAG.getBasicBlock(CB.TrueBB));
1730 // Insert the false branch. Do this even if it's a fall through branch,
1731 // this makes it easier to do DAG optimizations which require inverting
1732 // the branch condition.
1733 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1734 DAG.getBasicBlock(CB.FalseBB));
1736 DAG.setRoot(BrCond);
1739 /// visitJumpTable - Emit JumpTable node in the current MBB
1740 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1741 // Emit the code for the jump table
1742 assert(JT.Reg != -1U && "Should lower JT Header first!");
1743 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1744 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1746 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1747 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1748 MVT::Other, Index.getValue(1),
1750 DAG.setRoot(BrJumpTable);
1753 /// visitJumpTableHeader - This function emits necessary code to produce index
1754 /// in the JumpTable from switch case.
1755 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1756 JumpTableHeader &JTH,
1757 MachineBasicBlock *SwitchBB) {
1758 SDLoc dl = getCurSDLoc();
1760 // Subtract the lowest switch case value from the value being switched on and
1761 // conditional branch to default mbb if the result is greater than the
1762 // difference between smallest and largest cases.
1763 SDValue SwitchOp = getValue(JTH.SValue);
1764 EVT VT = SwitchOp.getValueType();
1765 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1766 DAG.getConstant(JTH.First, dl, VT));
1768 // The SDNode we just created, which holds the value being switched on minus
1769 // the smallest case value, needs to be copied to a virtual register so it
1770 // can be used as an index into the jump table in a subsequent basic block.
1771 // This value may be smaller or larger than the target's pointer type, and
1772 // therefore require extension or truncating.
1773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1774 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1776 unsigned JumpTableReg =
1777 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1778 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1779 JumpTableReg, SwitchOp);
1780 JT.Reg = JumpTableReg;
1782 // Emit the range check for the jump table, and branch to the default block
1783 // for the switch statement if the value being switched on exceeds the largest
1784 // case in the switch.
1785 SDValue CMP = DAG.getSetCC(
1786 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1787 Sub.getValueType()),
1788 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1790 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1791 MVT::Other, CopyTo, CMP,
1792 DAG.getBasicBlock(JT.Default));
1794 // Avoid emitting unnecessary branches to the next block.
1795 if (JT.MBB != NextBlock(SwitchBB))
1796 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1797 DAG.getBasicBlock(JT.MBB));
1799 DAG.setRoot(BrCond);
1802 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1803 /// tail spliced into a stack protector check success bb.
1805 /// For a high level explanation of how this fits into the stack protector
1806 /// generation see the comment on the declaration of class
1807 /// StackProtectorDescriptor.
1808 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1809 MachineBasicBlock *ParentBB) {
1811 // First create the loads to the guard/stack slot for the comparison.
1812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1813 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1815 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1816 int FI = MFI->getStackProtectorIndex();
1818 const Value *IRGuard = SPD.getGuard();
1819 SDValue GuardPtr = getValue(IRGuard);
1820 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1822 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1825 SDLoc dl = getCurSDLoc();
1827 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1828 // guard value from the virtual register holding the value. Otherwise, emit a
1829 // volatile load to retrieve the stack guard value.
1830 unsigned GuardReg = SPD.getGuardReg();
1832 if (GuardReg && TLI.useLoadStackGuardNode())
1833 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1836 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1837 GuardPtr, MachinePointerInfo(IRGuard, 0),
1838 true, false, false, Align);
1840 SDValue StackSlot = DAG.getLoad(
1841 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1842 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1843 false, false, Align);
1845 // Perform the comparison via a subtract/getsetcc.
1846 EVT VT = Guard.getValueType();
1847 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1849 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1851 Sub.getValueType()),
1852 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1854 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1855 // branch to failure MBB.
1856 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1857 MVT::Other, StackSlot.getOperand(0),
1858 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1859 // Otherwise branch to success MBB.
1860 SDValue Br = DAG.getNode(ISD::BR, dl,
1862 DAG.getBasicBlock(SPD.getSuccessMBB()));
1867 /// Codegen the failure basic block for a stack protector check.
1869 /// A failure stack protector machine basic block consists simply of a call to
1870 /// __stack_chk_fail().
1872 /// For a high level explanation of how this fits into the stack protector
1873 /// generation see the comment on the declaration of class
1874 /// StackProtectorDescriptor.
1876 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1877 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1879 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1880 nullptr, 0, false, getCurSDLoc(), false, false).second;
1884 /// visitBitTestHeader - This function emits necessary code to produce value
1885 /// suitable for "bit tests"
1886 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1887 MachineBasicBlock *SwitchBB) {
1888 SDLoc dl = getCurSDLoc();
1890 // Subtract the minimum value
1891 SDValue SwitchOp = getValue(B.SValue);
1892 EVT VT = SwitchOp.getValueType();
1893 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1894 DAG.getConstant(B.First, dl, VT));
1897 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1898 SDValue RangeCmp = DAG.getSetCC(
1899 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1900 Sub.getValueType()),
1901 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1903 // Determine the type of the test operands.
1904 bool UsePtrType = false;
1905 if (!TLI.isTypeLegal(VT))
1908 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1909 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1910 // Switch table case range are encoded into series of masks.
1911 // Just use pointer type, it's guaranteed to fit.
1917 VT = TLI.getPointerTy(DAG.getDataLayout());
1918 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1921 B.RegVT = VT.getSimpleVT();
1922 B.Reg = FuncInfo.CreateReg(B.RegVT);
1923 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1925 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1927 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1928 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1930 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1931 MVT::Other, CopyTo, RangeCmp,
1932 DAG.getBasicBlock(B.Default));
1934 // Avoid emitting unnecessary branches to the next block.
1935 if (MBB != NextBlock(SwitchBB))
1936 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1937 DAG.getBasicBlock(MBB));
1939 DAG.setRoot(BrRange);
1942 /// visitBitTestCase - this function produces one "bit test"
1943 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1944 MachineBasicBlock* NextMBB,
1945 uint32_t BranchWeightToNext,
1948 MachineBasicBlock *SwitchBB) {
1949 SDLoc dl = getCurSDLoc();
1951 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1953 unsigned PopCount = countPopulation(B.Mask);
1954 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1955 if (PopCount == 1) {
1956 // Testing for a single bit; just compare the shift count with what it
1957 // would need to be to shift a 1 bit in that position.
1959 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1960 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1962 } else if (PopCount == BB.Range) {
1963 // There is only one zero bit in the range, test for it directly.
1965 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1966 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1969 // Make desired shift
1970 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1971 DAG.getConstant(1, dl, VT), ShiftOp);
1973 // Emit bit tests and jumps
1974 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1975 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1977 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1978 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1981 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1982 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1983 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1984 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1986 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1987 MVT::Other, getControlRoot(),
1988 Cmp, DAG.getBasicBlock(B.TargetBB));
1990 // Avoid emitting unnecessary branches to the next block.
1991 if (NextMBB != NextBlock(SwitchBB))
1992 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1993 DAG.getBasicBlock(NextMBB));
1998 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1999 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2001 // Retrieve successors.
2002 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2003 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2005 const Value *Callee(I.getCalledValue());
2006 const Function *Fn = dyn_cast<Function>(Callee);
2007 if (isa<InlineAsm>(Callee))
2009 else if (Fn && Fn->isIntrinsic()) {
2010 switch (Fn->getIntrinsicID()) {
2012 llvm_unreachable("Cannot invoke this intrinsic");
2013 case Intrinsic::donothing:
2014 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2016 case Intrinsic::experimental_patchpoint_void:
2017 case Intrinsic::experimental_patchpoint_i64:
2018 visitPatchpoint(&I, LandingPad);
2020 case Intrinsic::experimental_gc_statepoint:
2021 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2025 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2027 // If the value of the invoke is used outside of its defining block, make it
2028 // available as a virtual register.
2029 // We already took care of the exported value for the statepoint instruction
2030 // during call to the LowerStatepoint.
2031 if (!isStatepoint(I)) {
2032 CopyToExportRegsIfNeeded(&I);
2035 // Update successor info
2036 addSuccessorWithWeight(InvokeMBB, Return);
2037 addSuccessorWithWeight(InvokeMBB, LandingPad);
2039 // Drop into normal successor.
2040 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2041 MVT::Other, getControlRoot(),
2042 DAG.getBasicBlock(Return)));
2045 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2046 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2049 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2050 assert(FuncInfo.MBB->isEHPad() &&
2051 "Call to landingpad not in landing pad!");
2053 MachineBasicBlock *MBB = FuncInfo.MBB;
2054 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2055 AddLandingPadInfo(LP, MMI, MBB);
2057 // If there aren't registers to copy the values into (e.g., during SjLj
2058 // exceptions), then don't bother to create these DAG nodes.
2059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2060 if (TLI.getExceptionPointerRegister() == 0 &&
2061 TLI.getExceptionSelectorRegister() == 0)
2064 SmallVector<EVT, 2> ValueVTs;
2065 SDLoc dl = getCurSDLoc();
2066 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2067 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2069 // Get the two live-in registers as SDValues. The physregs have already been
2070 // copied into virtual registers.
2072 if (FuncInfo.ExceptionPointerVirtReg) {
2073 Ops[0] = DAG.getZExtOrTrunc(
2074 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2075 FuncInfo.ExceptionPointerVirtReg,
2076 TLI.getPointerTy(DAG.getDataLayout())),
2079 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2081 Ops[1] = DAG.getZExtOrTrunc(
2082 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2083 FuncInfo.ExceptionSelectorVirtReg,
2084 TLI.getPointerTy(DAG.getDataLayout())),
2088 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2089 DAG.getVTList(ValueVTs), Ops);
2093 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2095 for (const CaseCluster &CC : Clusters)
2096 assert(CC.Low == CC.High && "Input clusters must be single-case");
2099 std::sort(Clusters.begin(), Clusters.end(),
2100 [](const CaseCluster &a, const CaseCluster &b) {
2101 return a.Low->getValue().slt(b.Low->getValue());
2104 // Merge adjacent clusters with the same destination.
2105 const unsigned N = Clusters.size();
2106 unsigned DstIndex = 0;
2107 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2108 CaseCluster &CC = Clusters[SrcIndex];
2109 const ConstantInt *CaseVal = CC.Low;
2110 MachineBasicBlock *Succ = CC.MBB;
2112 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2113 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2114 // If this case has the same successor and is a neighbour, merge it into
2115 // the previous cluster.
2116 Clusters[DstIndex - 1].High = CaseVal;
2117 Clusters[DstIndex - 1].Weight += CC.Weight;
2118 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2120 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2121 sizeof(Clusters[SrcIndex]));
2124 Clusters.resize(DstIndex);
2127 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2128 MachineBasicBlock *Last) {
2130 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2131 if (JTCases[i].first.HeaderBB == First)
2132 JTCases[i].first.HeaderBB = Last;
2134 // Update BitTestCases.
2135 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2136 if (BitTestCases[i].Parent == First)
2137 BitTestCases[i].Parent = Last;
2140 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2141 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2143 // Update machine-CFG edges with unique successors.
2144 SmallSet<BasicBlock*, 32> Done;
2145 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2146 BasicBlock *BB = I.getSuccessor(i);
2147 bool Inserted = Done.insert(BB).second;
2151 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2152 addSuccessorWithWeight(IndirectBrMBB, Succ);
2155 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2156 MVT::Other, getControlRoot(),
2157 getValue(I.getAddress())));
2160 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2161 if (DAG.getTarget().Options.TrapUnreachable)
2162 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2165 void SelectionDAGBuilder::visitFSub(const User &I) {
2166 // -0.0 - X --> fneg
2167 Type *Ty = I.getType();
2168 if (isa<Constant>(I.getOperand(0)) &&
2169 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2170 SDValue Op2 = getValue(I.getOperand(1));
2171 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2172 Op2.getValueType(), Op2));
2176 visitBinary(I, ISD::FSUB);
2179 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2180 SDValue Op1 = getValue(I.getOperand(0));
2181 SDValue Op2 = getValue(I.getOperand(1));
2188 if (const OverflowingBinaryOperator *OFBinOp =
2189 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2190 nuw = OFBinOp->hasNoUnsignedWrap();
2191 nsw = OFBinOp->hasNoSignedWrap();
2193 if (const PossiblyExactOperator *ExactOp =
2194 dyn_cast<const PossiblyExactOperator>(&I))
2195 exact = ExactOp->isExact();
2196 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2197 FMF = FPOp->getFastMathFlags();
2200 Flags.setExact(exact);
2201 Flags.setNoSignedWrap(nsw);
2202 Flags.setNoUnsignedWrap(nuw);
2203 if (EnableFMFInDAG) {
2204 Flags.setAllowReciprocal(FMF.allowReciprocal());
2205 Flags.setNoInfs(FMF.noInfs());
2206 Flags.setNoNaNs(FMF.noNaNs());
2207 Flags.setNoSignedZeros(FMF.noSignedZeros());
2208 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2210 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2212 setValue(&I, BinNodeValue);
2215 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2216 SDValue Op1 = getValue(I.getOperand(0));
2217 SDValue Op2 = getValue(I.getOperand(1));
2219 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2220 Op2.getValueType(), DAG.getDataLayout());
2222 // Coerce the shift amount to the right type if we can.
2223 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2224 unsigned ShiftSize = ShiftTy.getSizeInBits();
2225 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2226 SDLoc DL = getCurSDLoc();
2228 // If the operand is smaller than the shift count type, promote it.
2229 if (ShiftSize > Op2Size)
2230 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2232 // If the operand is larger than the shift count type but the shift
2233 // count type has enough bits to represent any shift value, truncate
2234 // it now. This is a common case and it exposes the truncate to
2235 // optimization early.
2236 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2237 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2238 // Otherwise we'll need to temporarily settle for some other convenient
2239 // type. Type legalization will make adjustments once the shiftee is split.
2241 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2248 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2250 if (const OverflowingBinaryOperator *OFBinOp =
2251 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2252 nuw = OFBinOp->hasNoUnsignedWrap();
2253 nsw = OFBinOp->hasNoSignedWrap();
2255 if (const PossiblyExactOperator *ExactOp =
2256 dyn_cast<const PossiblyExactOperator>(&I))
2257 exact = ExactOp->isExact();
2260 Flags.setExact(exact);
2261 Flags.setNoSignedWrap(nsw);
2262 Flags.setNoUnsignedWrap(nuw);
2263 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2268 void SelectionDAGBuilder::visitSDiv(const User &I) {
2269 SDValue Op1 = getValue(I.getOperand(0));
2270 SDValue Op2 = getValue(I.getOperand(1));
2273 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2274 cast<PossiblyExactOperator>(&I)->isExact());
2275 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2279 void SelectionDAGBuilder::visitICmp(const User &I) {
2280 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2281 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2282 predicate = IC->getPredicate();
2283 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2284 predicate = ICmpInst::Predicate(IC->getPredicate());
2285 SDValue Op1 = getValue(I.getOperand(0));
2286 SDValue Op2 = getValue(I.getOperand(1));
2287 ISD::CondCode Opcode = getICmpCondCode(predicate);
2289 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2291 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2294 void SelectionDAGBuilder::visitFCmp(const User &I) {
2295 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2296 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2297 predicate = FC->getPredicate();
2298 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2299 predicate = FCmpInst::Predicate(FC->getPredicate());
2300 SDValue Op1 = getValue(I.getOperand(0));
2301 SDValue Op2 = getValue(I.getOperand(1));
2302 ISD::CondCode Condition = getFCmpCondCode(predicate);
2303 if (TM.Options.NoNaNsFPMath)
2304 Condition = getFCmpCodeWithoutNaN(Condition);
2305 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2307 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2310 void SelectionDAGBuilder::visitSelect(const User &I) {
2311 SmallVector<EVT, 4> ValueVTs;
2312 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2314 unsigned NumValues = ValueVTs.size();
2315 if (NumValues == 0) return;
2317 SmallVector<SDValue, 4> Values(NumValues);
2318 SDValue Cond = getValue(I.getOperand(0));
2319 SDValue LHSVal = getValue(I.getOperand(1));
2320 SDValue RHSVal = getValue(I.getOperand(2));
2321 auto BaseOps = {Cond};
2322 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2323 ISD::VSELECT : ISD::SELECT;
2325 // Min/max matching is only viable if all output VTs are the same.
2326 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2327 EVT VT = ValueVTs[0];
2328 LLVMContext &Ctx = *DAG.getContext();
2329 auto &TLI = DAG.getTargetLoweringInfo();
2330 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2331 VT = TLI.getTypeToTransformTo(Ctx, VT);
2334 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2335 ISD::NodeType Opc = ISD::DELETED_NODE;
2336 switch (SPR.Flavor) {
2337 case SPF_UMAX: Opc = ISD::UMAX; break;
2338 case SPF_UMIN: Opc = ISD::UMIN; break;
2339 case SPF_SMAX: Opc = ISD::SMAX; break;
2340 case SPF_SMIN: Opc = ISD::SMIN; break;
2342 switch (SPR.NaNBehavior) {
2343 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2344 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2345 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2346 case SPNB_RETURNS_ANY:
2347 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2353 switch (SPR.NaNBehavior) {
2354 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2355 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2356 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2357 case SPNB_RETURNS_ANY:
2358 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2366 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2367 // If the underlying comparison instruction is used by any other instruction,
2368 // the consumed instructions won't be destroyed, so it is not profitable
2369 // to convert to a min/max.
2370 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2372 LHSVal = getValue(LHS);
2373 RHSVal = getValue(RHS);
2378 for (unsigned i = 0; i != NumValues; ++i) {
2379 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2380 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2381 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2382 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2383 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2387 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2388 DAG.getVTList(ValueVTs), Values));
2391 void SelectionDAGBuilder::visitTrunc(const User &I) {
2392 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2393 SDValue N = getValue(I.getOperand(0));
2394 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2396 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2399 void SelectionDAGBuilder::visitZExt(const User &I) {
2400 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2401 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2402 SDValue N = getValue(I.getOperand(0));
2403 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2405 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2408 void SelectionDAGBuilder::visitSExt(const User &I) {
2409 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2410 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2411 SDValue N = getValue(I.getOperand(0));
2412 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2414 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2417 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2418 // FPTrunc is never a no-op cast, no need to check
2419 SDValue N = getValue(I.getOperand(0));
2420 SDLoc dl = getCurSDLoc();
2421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2422 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2423 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2424 DAG.getTargetConstant(
2425 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2428 void SelectionDAGBuilder::visitFPExt(const User &I) {
2429 // FPExt is never a no-op cast, no need to check
2430 SDValue N = getValue(I.getOperand(0));
2431 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2433 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2436 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2437 // FPToUI is never a no-op cast, no need to check
2438 SDValue N = getValue(I.getOperand(0));
2439 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2441 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2444 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2445 // FPToSI is never a no-op cast, no need to check
2446 SDValue N = getValue(I.getOperand(0));
2447 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2449 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2452 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2453 // UIToFP is never a no-op cast, no need to check
2454 SDValue N = getValue(I.getOperand(0));
2455 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2457 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2460 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2461 // SIToFP is never a no-op cast, no need to check
2462 SDValue N = getValue(I.getOperand(0));
2463 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2465 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2468 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2469 // What to do depends on the size of the integer and the size of the pointer.
2470 // We can either truncate, zero extend, or no-op, accordingly.
2471 SDValue N = getValue(I.getOperand(0));
2472 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2474 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2477 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2478 // What to do depends on the size of the integer and the size of the pointer.
2479 // We can either truncate, zero extend, or no-op, accordingly.
2480 SDValue N = getValue(I.getOperand(0));
2481 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2483 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2486 void SelectionDAGBuilder::visitBitCast(const User &I) {
2487 SDValue N = getValue(I.getOperand(0));
2488 SDLoc dl = getCurSDLoc();
2489 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2492 // BitCast assures us that source and destination are the same size so this is
2493 // either a BITCAST or a no-op.
2494 if (DestVT != N.getValueType())
2495 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2496 DestVT, N)); // convert types.
2497 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2498 // might fold any kind of constant expression to an integer constant and that
2499 // is not what we are looking for. Only regcognize a bitcast of a genuine
2500 // constant integer as an opaque constant.
2501 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2502 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2505 setValue(&I, N); // noop cast.
2508 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2510 const Value *SV = I.getOperand(0);
2511 SDValue N = getValue(SV);
2512 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2514 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2515 unsigned DestAS = I.getType()->getPointerAddressSpace();
2517 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2518 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2523 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2524 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2525 SDValue InVec = getValue(I.getOperand(0));
2526 SDValue InVal = getValue(I.getOperand(1));
2527 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2528 TLI.getVectorIdxTy(DAG.getDataLayout()));
2529 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2530 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2531 InVec, InVal, InIdx));
2534 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2536 SDValue InVec = getValue(I.getOperand(0));
2537 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2538 TLI.getVectorIdxTy(DAG.getDataLayout()));
2539 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2540 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2544 // Utility for visitShuffleVector - Return true if every element in Mask,
2545 // beginning from position Pos and ending in Pos+Size, falls within the
2546 // specified sequential range [L, L+Pos). or is undef.
2547 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2548 unsigned Pos, unsigned Size, int Low) {
2549 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2550 if (Mask[i] >= 0 && Mask[i] != Low)
2555 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2556 SDValue Src1 = getValue(I.getOperand(0));
2557 SDValue Src2 = getValue(I.getOperand(1));
2559 SmallVector<int, 8> Mask;
2560 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2561 unsigned MaskNumElts = Mask.size();
2563 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2564 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2565 EVT SrcVT = Src1.getValueType();
2566 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2568 if (SrcNumElts == MaskNumElts) {
2569 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2574 // Normalize the shuffle vector since mask and vector length don't match.
2575 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2576 // Mask is longer than the source vectors and is a multiple of the source
2577 // vectors. We can use concatenate vector to make the mask and vectors
2579 if (SrcNumElts*2 == MaskNumElts) {
2580 // First check for Src1 in low and Src2 in high
2581 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2582 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2583 // The shuffle is concatenating two vectors together.
2584 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2588 // Then check for Src2 in low and Src1 in high
2589 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2590 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2591 // The shuffle is concatenating two vectors together.
2592 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2598 // Pad both vectors with undefs to make them the same length as the mask.
2599 unsigned NumConcat = MaskNumElts / SrcNumElts;
2600 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2601 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2602 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2604 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2605 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2609 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2610 getCurSDLoc(), VT, MOps1);
2611 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2612 getCurSDLoc(), VT, MOps2);
2614 // Readjust mask for new input vector length.
2615 SmallVector<int, 8> MappedOps;
2616 for (unsigned i = 0; i != MaskNumElts; ++i) {
2618 if (Idx >= (int)SrcNumElts)
2619 Idx -= SrcNumElts - MaskNumElts;
2620 MappedOps.push_back(Idx);
2623 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2628 if (SrcNumElts > MaskNumElts) {
2629 // Analyze the access pattern of the vector to see if we can extract
2630 // two subvectors and do the shuffle. The analysis is done by calculating
2631 // the range of elements the mask access on both vectors.
2632 int MinRange[2] = { static_cast<int>(SrcNumElts),
2633 static_cast<int>(SrcNumElts)};
2634 int MaxRange[2] = {-1, -1};
2636 for (unsigned i = 0; i != MaskNumElts; ++i) {
2642 if (Idx >= (int)SrcNumElts) {
2646 if (Idx > MaxRange[Input])
2647 MaxRange[Input] = Idx;
2648 if (Idx < MinRange[Input])
2649 MinRange[Input] = Idx;
2652 // Check if the access is smaller than the vector size and can we find
2653 // a reasonable extract index.
2654 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2656 int StartIdx[2]; // StartIdx to extract from
2657 for (unsigned Input = 0; Input < 2; ++Input) {
2658 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2659 RangeUse[Input] = 0; // Unused
2660 StartIdx[Input] = 0;
2664 // Find a good start index that is a multiple of the mask length. Then
2665 // see if the rest of the elements are in range.
2666 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2667 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2668 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2669 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2672 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2673 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2676 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2677 // Extract appropriate subvector and generate a vector shuffle
2678 for (unsigned Input = 0; Input < 2; ++Input) {
2679 SDValue &Src = Input == 0 ? Src1 : Src2;
2680 if (RangeUse[Input] == 0)
2681 Src = DAG.getUNDEF(VT);
2683 SDLoc dl = getCurSDLoc();
2685 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2686 DAG.getConstant(StartIdx[Input], dl,
2687 TLI.getVectorIdxTy(DAG.getDataLayout())));
2691 // Calculate new mask.
2692 SmallVector<int, 8> MappedOps;
2693 for (unsigned i = 0; i != MaskNumElts; ++i) {
2696 if (Idx < (int)SrcNumElts)
2699 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2701 MappedOps.push_back(Idx);
2704 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2710 // We can't use either concat vectors or extract subvectors so fall back to
2711 // replacing the shuffle with extract and build vector.
2712 // to insert and build vector.
2713 EVT EltVT = VT.getVectorElementType();
2714 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2715 SDLoc dl = getCurSDLoc();
2716 SmallVector<SDValue,8> Ops;
2717 for (unsigned i = 0; i != MaskNumElts; ++i) {
2722 Res = DAG.getUNDEF(EltVT);
2724 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2725 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2727 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2728 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2734 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2737 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2738 const Value *Op0 = I.getOperand(0);
2739 const Value *Op1 = I.getOperand(1);
2740 Type *AggTy = I.getType();
2741 Type *ValTy = Op1->getType();
2742 bool IntoUndef = isa<UndefValue>(Op0);
2743 bool FromUndef = isa<UndefValue>(Op1);
2745 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2747 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2748 SmallVector<EVT, 4> AggValueVTs;
2749 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2750 SmallVector<EVT, 4> ValValueVTs;
2751 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2753 unsigned NumAggValues = AggValueVTs.size();
2754 unsigned NumValValues = ValValueVTs.size();
2755 SmallVector<SDValue, 4> Values(NumAggValues);
2757 // Ignore an insertvalue that produces an empty object
2758 if (!NumAggValues) {
2759 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2763 SDValue Agg = getValue(Op0);
2765 // Copy the beginning value(s) from the original aggregate.
2766 for (; i != LinearIndex; ++i)
2767 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2768 SDValue(Agg.getNode(), Agg.getResNo() + i);
2769 // Copy values from the inserted value(s).
2771 SDValue Val = getValue(Op1);
2772 for (; i != LinearIndex + NumValValues; ++i)
2773 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2774 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2776 // Copy remaining value(s) from the original aggregate.
2777 for (; i != NumAggValues; ++i)
2778 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2779 SDValue(Agg.getNode(), Agg.getResNo() + i);
2781 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2782 DAG.getVTList(AggValueVTs), Values));
2785 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2786 const Value *Op0 = I.getOperand(0);
2787 Type *AggTy = Op0->getType();
2788 Type *ValTy = I.getType();
2789 bool OutOfUndef = isa<UndefValue>(Op0);
2791 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2793 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2794 SmallVector<EVT, 4> ValValueVTs;
2795 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2797 unsigned NumValValues = ValValueVTs.size();
2799 // Ignore a extractvalue that produces an empty object
2800 if (!NumValValues) {
2801 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2805 SmallVector<SDValue, 4> Values(NumValValues);
2807 SDValue Agg = getValue(Op0);
2808 // Copy out the selected value(s).
2809 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2810 Values[i - LinearIndex] =
2812 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2813 SDValue(Agg.getNode(), Agg.getResNo() + i);
2815 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2816 DAG.getVTList(ValValueVTs), Values));
2819 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2820 Value *Op0 = I.getOperand(0);
2821 // Note that the pointer operand may be a vector of pointers. Take the scalar
2822 // element which holds a pointer.
2823 Type *Ty = Op0->getType()->getScalarType();
2824 unsigned AS = Ty->getPointerAddressSpace();
2825 SDValue N = getValue(Op0);
2826 SDLoc dl = getCurSDLoc();
2828 // Normalize Vector GEP - all scalar operands should be converted to the
2830 unsigned VectorWidth = I.getType()->isVectorTy() ?
2831 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2833 if (VectorWidth && !N.getValueType().isVector()) {
2834 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2835 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2836 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2838 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2840 const Value *Idx = *OI;
2841 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2842 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2845 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2846 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2847 DAG.getConstant(Offset, dl, N.getValueType()));
2850 Ty = StTy->getElementType(Field);
2852 Ty = cast<SequentialType>(Ty)->getElementType();
2854 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2855 unsigned PtrSize = PtrTy.getSizeInBits();
2856 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2858 // If this is a scalar constant or a splat vector of constants,
2859 // handle it quickly.
2860 const auto *CI = dyn_cast<ConstantInt>(Idx);
2861 if (!CI && isa<ConstantDataVector>(Idx) &&
2862 cast<ConstantDataVector>(Idx)->getSplatValue())
2863 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2868 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2869 SDValue OffsVal = VectorWidth ?
2870 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2871 DAG.getConstant(Offs, dl, PtrTy);
2872 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2876 // N = N + Idx * ElementSize;
2877 SDValue IdxN = getValue(Idx);
2879 if (!IdxN.getValueType().isVector() && VectorWidth) {
2880 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2881 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2882 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2884 // If the index is smaller or larger than intptr_t, truncate or extend
2886 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2888 // If this is a multiply by a power of two, turn it into a shl
2889 // immediately. This is a very common case.
2890 if (ElementSize != 1) {
2891 if (ElementSize.isPowerOf2()) {
2892 unsigned Amt = ElementSize.logBase2();
2893 IdxN = DAG.getNode(ISD::SHL, dl,
2894 N.getValueType(), IdxN,
2895 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2897 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2898 IdxN = DAG.getNode(ISD::MUL, dl,
2899 N.getValueType(), IdxN, Scale);
2903 N = DAG.getNode(ISD::ADD, dl,
2904 N.getValueType(), N, IdxN);
2911 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2912 // If this is a fixed sized alloca in the entry block of the function,
2913 // allocate it statically on the stack.
2914 if (FuncInfo.StaticAllocaMap.count(&I))
2915 return; // getValue will auto-populate this.
2917 SDLoc dl = getCurSDLoc();
2918 Type *Ty = I.getAllocatedType();
2919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2920 auto &DL = DAG.getDataLayout();
2921 uint64_t TySize = DL.getTypeAllocSize(Ty);
2923 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2925 SDValue AllocSize = getValue(I.getArraySize());
2927 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2928 if (AllocSize.getValueType() != IntPtr)
2929 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2931 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2933 DAG.getConstant(TySize, dl, IntPtr));
2935 // Handle alignment. If the requested alignment is less than or equal to
2936 // the stack alignment, ignore it. If the size is greater than or equal to
2937 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2938 unsigned StackAlign =
2939 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2940 if (Align <= StackAlign)
2943 // Round the size of the allocation up to the stack alignment size
2944 // by add SA-1 to the size.
2945 AllocSize = DAG.getNode(ISD::ADD, dl,
2946 AllocSize.getValueType(), AllocSize,
2947 DAG.getIntPtrConstant(StackAlign - 1, dl));
2949 // Mask out the low bits for alignment purposes.
2950 AllocSize = DAG.getNode(ISD::AND, dl,
2951 AllocSize.getValueType(), AllocSize,
2952 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2955 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2956 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2957 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2959 DAG.setRoot(DSA.getValue(1));
2961 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2964 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2966 return visitAtomicLoad(I);
2968 const Value *SV = I.getOperand(0);
2969 SDValue Ptr = getValue(SV);
2971 Type *Ty = I.getType();
2973 bool isVolatile = I.isVolatile();
2974 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2976 // The IR notion of invariant_load only guarantees that all *non-faulting*
2977 // invariant loads result in the same value. The MI notion of invariant load
2978 // guarantees that the load can be legally moved to any location within its
2979 // containing function. The MI notion of invariant_load is stronger than the
2980 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2981 // with a guarantee that the location being loaded from is dereferenceable
2982 // throughout the function's lifetime.
2984 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2985 isDereferenceablePointer(SV, DAG.getDataLayout());
2986 unsigned Alignment = I.getAlignment();
2989 I.getAAMetadata(AAInfo);
2990 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2993 SmallVector<EVT, 4> ValueVTs;
2994 SmallVector<uint64_t, 4> Offsets;
2995 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2996 unsigned NumValues = ValueVTs.size();
3001 bool ConstantMemory = false;
3002 if (isVolatile || NumValues > MaxParallelChains)
3003 // Serialize volatile loads with other side effects.
3005 else if (AA->pointsToConstantMemory(MemoryLocation(
3006 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3007 // Do not serialize (non-volatile) loads of constant memory with anything.
3008 Root = DAG.getEntryNode();
3009 ConstantMemory = true;
3011 // Do not serialize non-volatile loads against each other.
3012 Root = DAG.getRoot();
3015 SDLoc dl = getCurSDLoc();
3018 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3020 SmallVector<SDValue, 4> Values(NumValues);
3021 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3022 EVT PtrVT = Ptr.getValueType();
3023 unsigned ChainI = 0;
3024 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3025 // Serializing loads here may result in excessive register pressure, and
3026 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3027 // could recover a bit by hoisting nodes upward in the chain by recognizing
3028 // they are side-effect free or do not alias. The optimizer should really
3029 // avoid this case by converting large object/array copies to llvm.memcpy
3030 // (MaxParallelChains should always remain as failsafe).
3031 if (ChainI == MaxParallelChains) {
3032 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3033 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3034 makeArrayRef(Chains.data(), ChainI));
3038 SDValue A = DAG.getNode(ISD::ADD, dl,
3040 DAG.getConstant(Offsets[i], dl, PtrVT));
3041 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3042 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3043 isNonTemporal, isInvariant, Alignment, AAInfo,
3047 Chains[ChainI] = L.getValue(1);
3050 if (!ConstantMemory) {
3051 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3052 makeArrayRef(Chains.data(), ChainI));
3056 PendingLoads.push_back(Chain);
3059 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3060 DAG.getVTList(ValueVTs), Values));
3063 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3065 return visitAtomicStore(I);
3067 const Value *SrcV = I.getOperand(0);
3068 const Value *PtrV = I.getOperand(1);
3070 SmallVector<EVT, 4> ValueVTs;
3071 SmallVector<uint64_t, 4> Offsets;
3072 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3073 SrcV->getType(), ValueVTs, &Offsets);
3074 unsigned NumValues = ValueVTs.size();
3078 // Get the lowered operands. Note that we do this after
3079 // checking if NumResults is zero, because with zero results
3080 // the operands won't have values in the map.
3081 SDValue Src = getValue(SrcV);
3082 SDValue Ptr = getValue(PtrV);
3084 SDValue Root = getRoot();
3085 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3086 EVT PtrVT = Ptr.getValueType();
3087 bool isVolatile = I.isVolatile();
3088 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3089 unsigned Alignment = I.getAlignment();
3090 SDLoc dl = getCurSDLoc();
3093 I.getAAMetadata(AAInfo);
3095 unsigned ChainI = 0;
3096 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3097 // See visitLoad comments.
3098 if (ChainI == MaxParallelChains) {
3099 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3100 makeArrayRef(Chains.data(), ChainI));
3104 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3105 DAG.getConstant(Offsets[i], dl, PtrVT));
3106 SDValue St = DAG.getStore(Root, dl,
3107 SDValue(Src.getNode(), Src.getResNo() + i),
3108 Add, MachinePointerInfo(PtrV, Offsets[i]),
3109 isVolatile, isNonTemporal, Alignment, AAInfo);
3110 Chains[ChainI] = St;
3113 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3114 makeArrayRef(Chains.data(), ChainI));
3115 DAG.setRoot(StoreNode);
3118 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3119 SDLoc sdl = getCurSDLoc();
3121 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3122 Value *PtrOperand = I.getArgOperand(1);
3123 SDValue Ptr = getValue(PtrOperand);
3124 SDValue Src0 = getValue(I.getArgOperand(0));
3125 SDValue Mask = getValue(I.getArgOperand(3));
3126 EVT VT = Src0.getValueType();
3127 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3129 Alignment = DAG.getEVTAlignment(VT);
3132 I.getAAMetadata(AAInfo);
3134 MachineMemOperand *MMO =
3135 DAG.getMachineFunction().
3136 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3137 MachineMemOperand::MOStore, VT.getStoreSize(),
3139 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3141 DAG.setRoot(StoreNode);
3142 setValue(&I, StoreNode);
3145 // Gather/scatter receive a vector of pointers.
3146 // This vector of pointers may be represented as a base pointer + vector of
3147 // indices, it depends on GEP and instruction preceding GEP
3148 // that calculates indices
3149 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3150 SelectionDAGBuilder* SDB) {
3152 assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
3153 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3154 if (!GEP || GEP->getNumOperands() > 2)
3156 Value *GEPPtrs = GEP->getPointerOperand();
3157 if (!(Ptr = getSplatValue(GEPPtrs)))
3160 SelectionDAG& DAG = SDB->DAG;
3161 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3162 // Check is the Ptr is inside current basic block
3163 // If not, look for the shuffle instruction
3164 if (SDB->findValue(Ptr))
3165 Base = SDB->getValue(Ptr);
3166 else if (SDB->findValue(GEPPtrs)) {
3167 SDValue GEPPtrsVal = SDB->getValue(GEPPtrs);
3168 SDLoc sdl = GEPPtrsVal;
3169 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
3170 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3171 GEPPtrsVal.getValueType().getScalarType(), GEPPtrsVal,
3172 DAG.getConstant(0, sdl, IdxVT));
3173 SDB->setValue(Ptr, Base);
3178 Value *IndexVal = GEP->getOperand(1);
3179 if (SDB->findValue(IndexVal)) {
3180 Index = SDB->getValue(IndexVal);
3182 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3183 IndexVal = Sext->getOperand(0);
3184 if (SDB->findValue(IndexVal))
3185 Index = SDB->getValue(IndexVal);
3192 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3193 SDLoc sdl = getCurSDLoc();
3195 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3196 Value *Ptr = I.getArgOperand(1);
3197 SDValue Src0 = getValue(I.getArgOperand(0));
3198 SDValue Mask = getValue(I.getArgOperand(3));
3199 EVT VT = Src0.getValueType();
3200 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3202 Alignment = DAG.getEVTAlignment(VT);
3203 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3206 I.getAAMetadata(AAInfo);
3210 Value *BasePtr = Ptr;
3211 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3213 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3214 MachineMemOperand *MMO = DAG.getMachineFunction().
3215 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3216 MachineMemOperand::MOStore, VT.getStoreSize(),
3219 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3220 Index = getValue(Ptr);
3222 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3223 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3225 DAG.setRoot(Scatter);
3226 setValue(&I, Scatter);
3229 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3230 SDLoc sdl = getCurSDLoc();
3232 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3233 Value *PtrOperand = I.getArgOperand(0);
3234 SDValue Ptr = getValue(PtrOperand);
3235 SDValue Src0 = getValue(I.getArgOperand(3));
3236 SDValue Mask = getValue(I.getArgOperand(2));
3238 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3239 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3240 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3242 Alignment = DAG.getEVTAlignment(VT);
3245 I.getAAMetadata(AAInfo);
3246 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3248 SDValue InChain = DAG.getRoot();
3249 if (AA->pointsToConstantMemory(MemoryLocation(
3250 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3252 // Do not serialize (non-volatile) loads of constant memory with anything.
3253 InChain = DAG.getEntryNode();
3256 MachineMemOperand *MMO =
3257 DAG.getMachineFunction().
3258 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3259 MachineMemOperand::MOLoad, VT.getStoreSize(),
3260 Alignment, AAInfo, Ranges);
3262 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3264 SDValue OutChain = Load.getValue(1);
3265 DAG.setRoot(OutChain);
3269 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3270 SDLoc sdl = getCurSDLoc();
3272 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3273 Value *Ptr = I.getArgOperand(0);
3274 SDValue Src0 = getValue(I.getArgOperand(3));
3275 SDValue Mask = getValue(I.getArgOperand(2));
3277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3278 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3279 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3281 Alignment = DAG.getEVTAlignment(VT);
3284 I.getAAMetadata(AAInfo);
3285 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3287 SDValue Root = DAG.getRoot();
3290 Value *BasePtr = Ptr;
3291 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3292 bool ConstantMemory = false;
3294 AA->pointsToConstantMemory(MemoryLocation(
3295 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3297 // Do not serialize (non-volatile) loads of constant memory with anything.
3298 Root = DAG.getEntryNode();
3299 ConstantMemory = true;
3302 MachineMemOperand *MMO =
3303 DAG.getMachineFunction().
3304 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3305 MachineMemOperand::MOLoad, VT.getStoreSize(),
3306 Alignment, AAInfo, Ranges);
3309 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3310 Index = getValue(Ptr);
3312 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3313 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3316 SDValue OutChain = Gather.getValue(1);
3317 if (!ConstantMemory)
3318 PendingLoads.push_back(OutChain);
3319 setValue(&I, Gather);
3322 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3323 SDLoc dl = getCurSDLoc();
3324 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3325 AtomicOrdering FailureOrder = I.getFailureOrdering();
3326 SynchronizationScope Scope = I.getSynchScope();
3328 SDValue InChain = getRoot();
3330 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3331 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3332 SDValue L = DAG.getAtomicCmpSwap(
3333 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3334 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3335 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3336 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3338 SDValue OutChain = L.getValue(2);
3341 DAG.setRoot(OutChain);
3344 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3345 SDLoc dl = getCurSDLoc();
3347 switch (I.getOperation()) {
3348 default: llvm_unreachable("Unknown atomicrmw operation");
3349 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3350 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3351 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3352 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3353 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3354 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3355 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3356 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3357 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3358 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3359 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3361 AtomicOrdering Order = I.getOrdering();
3362 SynchronizationScope Scope = I.getSynchScope();
3364 SDValue InChain = getRoot();
3367 DAG.getAtomic(NT, dl,
3368 getValue(I.getValOperand()).getSimpleValueType(),
3370 getValue(I.getPointerOperand()),
3371 getValue(I.getValOperand()),
3372 I.getPointerOperand(),
3373 /* Alignment=*/ 0, Order, Scope);
3375 SDValue OutChain = L.getValue(1);
3378 DAG.setRoot(OutChain);
3381 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3382 SDLoc dl = getCurSDLoc();
3383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3386 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3387 TLI.getPointerTy(DAG.getDataLayout()));
3388 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3389 TLI.getPointerTy(DAG.getDataLayout()));
3390 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3393 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3394 SDLoc dl = getCurSDLoc();
3395 AtomicOrdering Order = I.getOrdering();
3396 SynchronizationScope Scope = I.getSynchScope();
3398 SDValue InChain = getRoot();
3400 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3401 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3403 if (I.getAlignment() < VT.getSizeInBits() / 8)
3404 report_fatal_error("Cannot generate unaligned atomic load");
3406 MachineMemOperand *MMO =
3407 DAG.getMachineFunction().
3408 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3409 MachineMemOperand::MOVolatile |
3410 MachineMemOperand::MOLoad,
3412 I.getAlignment() ? I.getAlignment() :
3413 DAG.getEVTAlignment(VT));
3415 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3417 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3418 getValue(I.getPointerOperand()), MMO,
3421 SDValue OutChain = L.getValue(1);
3424 DAG.setRoot(OutChain);
3427 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3428 SDLoc dl = getCurSDLoc();
3430 AtomicOrdering Order = I.getOrdering();
3431 SynchronizationScope Scope = I.getSynchScope();
3433 SDValue InChain = getRoot();
3435 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3437 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3439 if (I.getAlignment() < VT.getSizeInBits() / 8)
3440 report_fatal_error("Cannot generate unaligned atomic store");
3443 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3445 getValue(I.getPointerOperand()),
3446 getValue(I.getValueOperand()),
3447 I.getPointerOperand(), I.getAlignment(),
3450 DAG.setRoot(OutChain);
3453 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3455 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3456 unsigned Intrinsic) {
3457 bool HasChain = !I.doesNotAccessMemory();
3458 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3460 // Build the operand list.
3461 SmallVector<SDValue, 8> Ops;
3462 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3464 // We don't need to serialize loads against other loads.
3465 Ops.push_back(DAG.getRoot());
3467 Ops.push_back(getRoot());
3471 // Info is set by getTgtMemInstrinsic
3472 TargetLowering::IntrinsicInfo Info;
3473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3474 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3476 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3477 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3478 Info.opc == ISD::INTRINSIC_W_CHAIN)
3479 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3480 TLI.getPointerTy(DAG.getDataLayout())));
3482 // Add all operands of the call to the operand list.
3483 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3484 SDValue Op = getValue(I.getArgOperand(i));
3488 SmallVector<EVT, 4> ValueVTs;
3489 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3492 ValueVTs.push_back(MVT::Other);
3494 SDVTList VTs = DAG.getVTList(ValueVTs);
3498 if (IsTgtIntrinsic) {
3499 // This is target intrinsic that touches memory
3500 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3501 VTs, Ops, Info.memVT,
3502 MachinePointerInfo(Info.ptrVal, Info.offset),
3503 Info.align, Info.vol,
3504 Info.readMem, Info.writeMem, Info.size);
3505 } else if (!HasChain) {
3506 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3507 } else if (!I.getType()->isVoidTy()) {
3508 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3510 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3514 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3516 PendingLoads.push_back(Chain);
3521 if (!I.getType()->isVoidTy()) {
3522 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3523 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3524 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3527 setValue(&I, Result);
3531 /// GetSignificand - Get the significand and build it into a floating-point
3532 /// number with exponent of 1:
3534 /// Op = (Op & 0x007fffff) | 0x3f800000;
3536 /// where Op is the hexadecimal representation of floating point value.
3538 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3539 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3540 DAG.getConstant(0x007fffff, dl, MVT::i32));
3541 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3542 DAG.getConstant(0x3f800000, dl, MVT::i32));
3543 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3546 /// GetExponent - Get the exponent:
3548 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3550 /// where Op is the hexadecimal representation of floating point value.
3552 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3554 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3555 DAG.getConstant(0x7f800000, dl, MVT::i32));
3556 SDValue t1 = DAG.getNode(
3557 ISD::SRL, dl, MVT::i32, t0,
3558 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3559 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3560 DAG.getConstant(127, dl, MVT::i32));
3561 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3564 /// getF32Constant - Get 32-bit floating point constant.
3566 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3567 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3571 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3572 SelectionDAG &DAG) {
3573 // IntegerPartOfX = ((int32_t)(t0);
3574 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3576 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3577 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3578 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3580 // IntegerPartOfX <<= 23;
3581 IntegerPartOfX = DAG.getNode(
3582 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3583 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3584 DAG.getDataLayout())));
3586 SDValue TwoToFractionalPartOfX;
3587 if (LimitFloatPrecision <= 6) {
3588 // For floating-point precision of 6:
3590 // TwoToFractionalPartOfX =
3592 // (0.735607626f + 0.252464424f * x) * x;
3594 // error 0.0144103317, which is 6 bits
3595 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3596 getF32Constant(DAG, 0x3e814304, dl));
3597 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3598 getF32Constant(DAG, 0x3f3c50c8, dl));
3599 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3600 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3601 getF32Constant(DAG, 0x3f7f5e7e, dl));
3602 } else if (LimitFloatPrecision <= 12) {
3603 // For floating-point precision of 12:
3605 // TwoToFractionalPartOfX =
3608 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3610 // error 0.000107046256, which is 13 to 14 bits
3611 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3612 getF32Constant(DAG, 0x3da235e3, dl));
3613 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3614 getF32Constant(DAG, 0x3e65b8f3, dl));
3615 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3616 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3617 getF32Constant(DAG, 0x3f324b07, dl));
3618 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3619 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3620 getF32Constant(DAG, 0x3f7ff8fd, dl));
3621 } else { // LimitFloatPrecision <= 18
3622 // For floating-point precision of 18:
3624 // TwoToFractionalPartOfX =
3628 // (0.554906021e-1f +
3629 // (0.961591928e-2f +
3630 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3631 // error 2.47208000*10^(-7), which is better than 18 bits
3632 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3633 getF32Constant(DAG, 0x3924b03e, dl));
3634 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3635 getF32Constant(DAG, 0x3ab24b87, dl));
3636 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3637 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3638 getF32Constant(DAG, 0x3c1d8c17, dl));
3639 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3640 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3641 getF32Constant(DAG, 0x3d634a1d, dl));
3642 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3643 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3644 getF32Constant(DAG, 0x3e75fe14, dl));
3645 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3646 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3647 getF32Constant(DAG, 0x3f317234, dl));
3648 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3649 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3650 getF32Constant(DAG, 0x3f800000, dl));
3653 // Add the exponent into the result in integer domain.
3654 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3655 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3656 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3659 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3660 /// limited-precision mode.
3661 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3662 const TargetLowering &TLI) {
3663 if (Op.getValueType() == MVT::f32 &&
3664 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3666 // Put the exponent in the right bit position for later addition to the
3669 // #define LOG2OFe 1.4426950f
3670 // t0 = Op * LOG2OFe
3671 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3672 getF32Constant(DAG, 0x3fb8aa3b, dl));
3673 return getLimitedPrecisionExp2(t0, dl, DAG);
3676 // No special expansion.
3677 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3680 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3681 /// limited-precision mode.
3682 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3683 const TargetLowering &TLI) {
3684 if (Op.getValueType() == MVT::f32 &&
3685 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3686 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3688 // Scale the exponent by log(2) [0.69314718f].
3689 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3690 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3691 getF32Constant(DAG, 0x3f317218, dl));
3693 // Get the significand and build it into a floating-point number with
3695 SDValue X = GetSignificand(DAG, Op1, dl);
3697 SDValue LogOfMantissa;
3698 if (LimitFloatPrecision <= 6) {
3699 // For floating-point precision of 6:
3703 // (1.4034025f - 0.23903021f * x) * x;
3705 // error 0.0034276066, which is better than 8 bits
3706 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3707 getF32Constant(DAG, 0xbe74c456, dl));
3708 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3709 getF32Constant(DAG, 0x3fb3a2b1, dl));
3710 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3711 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3712 getF32Constant(DAG, 0x3f949a29, dl));
3713 } else if (LimitFloatPrecision <= 12) {
3714 // For floating-point precision of 12:
3720 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3722 // error 0.000061011436, which is 14 bits
3723 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3724 getF32Constant(DAG, 0xbd67b6d6, dl));
3725 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3726 getF32Constant(DAG, 0x3ee4f4b8, dl));
3727 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3728 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3729 getF32Constant(DAG, 0x3fbc278b, dl));
3730 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3731 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3732 getF32Constant(DAG, 0x40348e95, dl));
3733 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3734 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3735 getF32Constant(DAG, 0x3fdef31a, dl));
3736 } else { // LimitFloatPrecision <= 18
3737 // For floating-point precision of 18:
3745 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3747 // error 0.0000023660568, which is better than 18 bits
3748 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3749 getF32Constant(DAG, 0xbc91e5ac, dl));
3750 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3751 getF32Constant(DAG, 0x3e4350aa, dl));
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3753 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3754 getF32Constant(DAG, 0x3f60d3e3, dl));
3755 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3756 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3757 getF32Constant(DAG, 0x4011cdf0, dl));
3758 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3759 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3760 getF32Constant(DAG, 0x406cfd1c, dl));
3761 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3762 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3763 getF32Constant(DAG, 0x408797cb, dl));
3764 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3765 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3766 getF32Constant(DAG, 0x4006dcab, dl));
3769 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3772 // No special expansion.
3773 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3776 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3777 /// limited-precision mode.
3778 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3779 const TargetLowering &TLI) {
3780 if (Op.getValueType() == MVT::f32 &&
3781 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3782 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3784 // Get the exponent.
3785 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3787 // Get the significand and build it into a floating-point number with
3789 SDValue X = GetSignificand(DAG, Op1, dl);
3791 // Different possible minimax approximations of significand in
3792 // floating-point for various degrees of accuracy over [1,2].
3793 SDValue Log2ofMantissa;
3794 if (LimitFloatPrecision <= 6) {
3795 // For floating-point precision of 6:
3797 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3799 // error 0.0049451742, which is more than 7 bits
3800 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3801 getF32Constant(DAG, 0xbeb08fe0, dl));
3802 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3803 getF32Constant(DAG, 0x40019463, dl));
3804 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3805 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3806 getF32Constant(DAG, 0x3fd6633d, dl));
3807 } else if (LimitFloatPrecision <= 12) {
3808 // For floating-point precision of 12:
3814 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3816 // error 0.0000876136000, which is better than 13 bits
3817 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3818 getF32Constant(DAG, 0xbda7262e, dl));
3819 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3820 getF32Constant(DAG, 0x3f25280b, dl));
3821 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3822 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3823 getF32Constant(DAG, 0x4007b923, dl));
3824 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3825 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3826 getF32Constant(DAG, 0x40823e2f, dl));
3827 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3828 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3829 getF32Constant(DAG, 0x4020d29c, dl));
3830 } else { // LimitFloatPrecision <= 18
3831 // For floating-point precision of 18:
3840 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3842 // error 0.0000018516, which is better than 18 bits
3843 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3844 getF32Constant(DAG, 0xbcd2769e, dl));
3845 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3846 getF32Constant(DAG, 0x3e8ce0b9, dl));
3847 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3848 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3849 getF32Constant(DAG, 0x3fa22ae7, dl));
3850 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3851 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3852 getF32Constant(DAG, 0x40525723, dl));
3853 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3854 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3855 getF32Constant(DAG, 0x40aaf200, dl));
3856 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3857 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3858 getF32Constant(DAG, 0x40c39dad, dl));
3859 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3860 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3861 getF32Constant(DAG, 0x4042902c, dl));
3864 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3867 // No special expansion.
3868 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3871 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3872 /// limited-precision mode.
3873 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3874 const TargetLowering &TLI) {
3875 if (Op.getValueType() == MVT::f32 &&
3876 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3877 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3879 // Scale the exponent by log10(2) [0.30102999f].
3880 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3881 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3882 getF32Constant(DAG, 0x3e9a209a, dl));
3884 // Get the significand and build it into a floating-point number with
3886 SDValue X = GetSignificand(DAG, Op1, dl);
3888 SDValue Log10ofMantissa;
3889 if (LimitFloatPrecision <= 6) {
3890 // For floating-point precision of 6:
3892 // Log10ofMantissa =
3894 // (0.60948995f - 0.10380950f * x) * x;
3896 // error 0.0014886165, which is 6 bits
3897 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3898 getF32Constant(DAG, 0xbdd49a13, dl));
3899 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3900 getF32Constant(DAG, 0x3f1c0789, dl));
3901 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3902 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3903 getF32Constant(DAG, 0x3f011300, dl));
3904 } else if (LimitFloatPrecision <= 12) {
3905 // For floating-point precision of 12:
3907 // Log10ofMantissa =
3910 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3912 // error 0.00019228036, which is better than 12 bits
3913 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3914 getF32Constant(DAG, 0x3d431f31, dl));
3915 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3916 getF32Constant(DAG, 0x3ea21fb2, dl));
3917 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3918 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3919 getF32Constant(DAG, 0x3f6ae232, dl));
3920 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3921 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3922 getF32Constant(DAG, 0x3f25f7c3, dl));
3923 } else { // LimitFloatPrecision <= 18
3924 // For floating-point precision of 18:
3926 // Log10ofMantissa =
3931 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3933 // error 0.0000037995730, which is better than 18 bits
3934 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3935 getF32Constant(DAG, 0x3c5d51ce, dl));
3936 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3937 getF32Constant(DAG, 0x3e00685a, dl));
3938 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3939 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3940 getF32Constant(DAG, 0x3efb6798, dl));
3941 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3942 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3943 getF32Constant(DAG, 0x3f88d192, dl));
3944 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3945 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3946 getF32Constant(DAG, 0x3fc4316c, dl));
3947 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3948 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3949 getF32Constant(DAG, 0x3f57ce70, dl));
3952 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3955 // No special expansion.
3956 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3959 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3960 /// limited-precision mode.
3961 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3962 const TargetLowering &TLI) {
3963 if (Op.getValueType() == MVT::f32 &&
3964 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3965 return getLimitedPrecisionExp2(Op, dl, DAG);
3967 // No special expansion.
3968 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3971 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3972 /// limited-precision mode with x == 10.0f.
3973 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3974 SelectionDAG &DAG, const TargetLowering &TLI) {
3975 bool IsExp10 = false;
3976 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3977 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3978 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3980 IsExp10 = LHSC->isExactlyValue(Ten);
3985 // Put the exponent in the right bit position for later addition to the
3988 // #define LOG2OF10 3.3219281f
3989 // t0 = Op * LOG2OF10;
3990 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3991 getF32Constant(DAG, 0x40549a78, dl));
3992 return getLimitedPrecisionExp2(t0, dl, DAG);
3995 // No special expansion.
3996 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4000 /// ExpandPowI - Expand a llvm.powi intrinsic.
4001 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4002 SelectionDAG &DAG) {
4003 // If RHS is a constant, we can expand this out to a multiplication tree,
4004 // otherwise we end up lowering to a call to __powidf2 (for example). When
4005 // optimizing for size, we only want to do this if the expansion would produce
4006 // a small number of multiplies, otherwise we do the full expansion.
4007 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4008 // Get the exponent as a positive value.
4009 unsigned Val = RHSC->getSExtValue();
4010 if ((int)Val < 0) Val = -Val;
4012 // powi(x, 0) -> 1.0
4014 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4016 const Function *F = DAG.getMachineFunction().getFunction();
4017 if (!F->optForSize() ||
4018 // If optimizing for size, don't insert too many multiplies.
4019 // This inserts up to 5 multiplies.
4020 countPopulation(Val) + Log2_32(Val) < 7) {
4021 // We use the simple binary decomposition method to generate the multiply
4022 // sequence. There are more optimal ways to do this (for example,
4023 // powi(x,15) generates one more multiply than it should), but this has
4024 // the benefit of being both really simple and much better than a libcall.
4025 SDValue Res; // Logically starts equal to 1.0
4026 SDValue CurSquare = LHS;
4030 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4032 Res = CurSquare; // 1.0*CurSquare.
4035 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4036 CurSquare, CurSquare);
4040 // If the original was negative, invert the result, producing 1/(x*x*x).
4041 if (RHSC->getSExtValue() < 0)
4042 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4043 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4048 // Otherwise, expand to a libcall.
4049 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4052 // getTruncatedArgReg - Find underlying register used for an truncated
4054 static unsigned getTruncatedArgReg(const SDValue &N) {
4055 if (N.getOpcode() != ISD::TRUNCATE)
4058 const SDValue &Ext = N.getOperand(0);
4059 if (Ext.getOpcode() == ISD::AssertZext ||
4060 Ext.getOpcode() == ISD::AssertSext) {
4061 const SDValue &CFR = Ext.getOperand(0);
4062 if (CFR.getOpcode() == ISD::CopyFromReg)
4063 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4064 if (CFR.getOpcode() == ISD::TRUNCATE)
4065 return getTruncatedArgReg(CFR);
4070 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4071 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4072 /// At the end of instruction selection, they will be inserted to the entry BB.
4073 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4074 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4075 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4076 const Argument *Arg = dyn_cast<Argument>(V);
4080 MachineFunction &MF = DAG.getMachineFunction();
4081 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4083 // Ignore inlined function arguments here.
4085 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4086 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4089 Optional<MachineOperand> Op;
4090 // Some arguments' frame index is recorded during argument lowering.
4091 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4092 Op = MachineOperand::CreateFI(FI);
4094 if (!Op && N.getNode()) {
4096 if (N.getOpcode() == ISD::CopyFromReg)
4097 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4099 Reg = getTruncatedArgReg(N);
4100 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4101 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4102 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4107 Op = MachineOperand::CreateReg(Reg, false);
4111 // Check if ValueMap has reg number.
4112 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4113 if (VMI != FuncInfo.ValueMap.end())
4114 Op = MachineOperand::CreateReg(VMI->second, false);
4117 if (!Op && N.getNode())
4118 // Check if frame index is available.
4119 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4120 if (FrameIndexSDNode *FINode =
4121 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4122 Op = MachineOperand::CreateFI(FINode->getIndex());
4127 assert(Variable->isValidLocationForIntrinsic(DL) &&
4128 "Expected inlined-at fields to agree");
4130 FuncInfo.ArgDbgValues.push_back(
4131 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4132 Op->getReg(), Offset, Variable, Expr));
4134 FuncInfo.ArgDbgValues.push_back(
4135 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4138 .addMetadata(Variable)
4139 .addMetadata(Expr));
4144 // VisualStudio defines setjmp as _setjmp
4145 #if defined(_MSC_VER) && defined(setjmp) && \
4146 !defined(setjmp_undefined_for_msvc)
4147 # pragma push_macro("setjmp")
4149 # define setjmp_undefined_for_msvc
4152 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4153 /// we want to emit this as a call to a named external function, return the name
4154 /// otherwise lower it and return null.
4156 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4157 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4158 SDLoc sdl = getCurSDLoc();
4159 DebugLoc dl = getCurDebugLoc();
4162 switch (Intrinsic) {
4164 // By default, turn this into a target intrinsic node.
4165 visitTargetIntrinsic(I, Intrinsic);
4167 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4168 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4169 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4170 case Intrinsic::returnaddress:
4171 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4172 TLI.getPointerTy(DAG.getDataLayout()),
4173 getValue(I.getArgOperand(0))));
4175 case Intrinsic::frameaddress:
4176 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4177 TLI.getPointerTy(DAG.getDataLayout()),
4178 getValue(I.getArgOperand(0))));
4180 case Intrinsic::read_register: {
4181 Value *Reg = I.getArgOperand(0);
4182 SDValue Chain = getRoot();
4184 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4185 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4186 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4187 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4189 DAG.setRoot(Res.getValue(1));
4192 case Intrinsic::write_register: {
4193 Value *Reg = I.getArgOperand(0);
4194 Value *RegValue = I.getArgOperand(1);
4195 SDValue Chain = getRoot();
4197 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4198 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4199 RegName, getValue(RegValue)));
4202 case Intrinsic::setjmp:
4203 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4204 case Intrinsic::longjmp:
4205 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4206 case Intrinsic::memcpy: {
4207 // FIXME: this definition of "user defined address space" is x86-specific
4208 // Assert for address < 256 since we support only user defined address
4210 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4212 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4214 "Unknown address space");
4215 SDValue Op1 = getValue(I.getArgOperand(0));
4216 SDValue Op2 = getValue(I.getArgOperand(1));
4217 SDValue Op3 = getValue(I.getArgOperand(2));
4218 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4220 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4221 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4222 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4223 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4225 MachinePointerInfo(I.getArgOperand(0)),
4226 MachinePointerInfo(I.getArgOperand(1)));
4227 updateDAGForMaybeTailCall(MC);
4230 case Intrinsic::memset: {
4231 // FIXME: this definition of "user defined address space" is x86-specific
4232 // Assert for address < 256 since we support only user defined address
4234 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4236 "Unknown address space");
4237 SDValue Op1 = getValue(I.getArgOperand(0));
4238 SDValue Op2 = getValue(I.getArgOperand(1));
4239 SDValue Op3 = getValue(I.getArgOperand(2));
4240 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4242 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4243 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4244 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4245 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4246 isTC, MachinePointerInfo(I.getArgOperand(0)));
4247 updateDAGForMaybeTailCall(MS);
4250 case Intrinsic::memmove: {
4251 // FIXME: this definition of "user defined address space" is x86-specific
4252 // Assert for address < 256 since we support only user defined address
4254 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4256 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4258 "Unknown address space");
4259 SDValue Op1 = getValue(I.getArgOperand(0));
4260 SDValue Op2 = getValue(I.getArgOperand(1));
4261 SDValue Op3 = getValue(I.getArgOperand(2));
4262 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4264 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4265 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4266 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4267 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4268 isTC, MachinePointerInfo(I.getArgOperand(0)),
4269 MachinePointerInfo(I.getArgOperand(1)));
4270 updateDAGForMaybeTailCall(MM);
4273 case Intrinsic::dbg_declare: {
4274 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4275 DILocalVariable *Variable = DI.getVariable();
4276 DIExpression *Expression = DI.getExpression();
4277 const Value *Address = DI.getAddress();
4278 assert(Variable && "Missing variable");
4280 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4284 // Check if address has undef value.
4285 if (isa<UndefValue>(Address) ||
4286 (Address->use_empty() && !isa<Argument>(Address))) {
4287 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4291 SDValue &N = NodeMap[Address];
4292 if (!N.getNode() && isa<Argument>(Address))
4293 // Check unused arguments map.
4294 N = UnusedArgNodeMap[Address];
4297 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4298 Address = BCI->getOperand(0);
4299 // Parameters are handled specially.
4300 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4302 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4304 if (isParameter && !AI) {
4305 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4307 // Byval parameter. We have a frame index at this point.
4308 SDV = DAG.getFrameIndexDbgValue(
4309 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4311 // Address is an argument, so try to emit its dbg value using
4312 // virtual register info from the FuncInfo.ValueMap.
4313 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4318 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4319 true, 0, dl, SDNodeOrder);
4321 // Can't do anything with other non-AI cases yet.
4322 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4323 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4324 DEBUG(Address->dump());
4327 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4329 // If Address is an argument then try to emit its dbg value using
4330 // virtual register info from the FuncInfo.ValueMap.
4331 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4333 // If variable is pinned by a alloca in dominating bb then
4334 // use StaticAllocaMap.
4335 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4336 if (AI->getParent() != DI.getParent()) {
4337 DenseMap<const AllocaInst*, int>::iterator SI =
4338 FuncInfo.StaticAllocaMap.find(AI);
4339 if (SI != FuncInfo.StaticAllocaMap.end()) {
4340 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4341 0, dl, SDNodeOrder);
4342 DAG.AddDbgValue(SDV, nullptr, false);
4347 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4352 case Intrinsic::dbg_value: {
4353 const DbgValueInst &DI = cast<DbgValueInst>(I);
4354 assert(DI.getVariable() && "Missing variable");
4356 DILocalVariable *Variable = DI.getVariable();
4357 DIExpression *Expression = DI.getExpression();
4358 uint64_t Offset = DI.getOffset();
4359 const Value *V = DI.getValue();
4364 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4365 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4367 DAG.AddDbgValue(SDV, nullptr, false);
4369 // Do not use getValue() in here; we don't want to generate code at
4370 // this point if it hasn't been done yet.
4371 SDValue N = NodeMap[V];
4372 if (!N.getNode() && isa<Argument>(V))
4373 // Check unused arguments map.
4374 N = UnusedArgNodeMap[V];
4376 // A dbg.value for an alloca is always indirect.
4377 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4378 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4380 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4381 IsIndirect, Offset, dl, SDNodeOrder);
4382 DAG.AddDbgValue(SDV, N.getNode(), false);
4384 } else if (!V->use_empty() ) {
4385 // Do not call getValue(V) yet, as we don't want to generate code.
4386 // Remember it for later.
4387 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4388 DanglingDebugInfoMap[V] = DDI;
4390 // We may expand this to cover more cases. One case where we have no
4391 // data available is an unreferenced parameter.
4392 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4396 // Build a debug info table entry.
4397 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4398 V = BCI->getOperand(0);
4399 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4400 // Don't handle byval struct arguments or VLAs, for example.
4402 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4403 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4406 DenseMap<const AllocaInst*, int>::iterator SI =
4407 FuncInfo.StaticAllocaMap.find(AI);
4408 if (SI == FuncInfo.StaticAllocaMap.end())
4409 return nullptr; // VLAs.
4413 case Intrinsic::eh_typeid_for: {
4414 // Find the type id for the given typeinfo.
4415 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4416 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4417 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4422 case Intrinsic::eh_return_i32:
4423 case Intrinsic::eh_return_i64:
4424 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4425 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4428 getValue(I.getArgOperand(0)),
4429 getValue(I.getArgOperand(1))));
4431 case Intrinsic::eh_unwind_init:
4432 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4434 case Intrinsic::eh_dwarf_cfa: {
4435 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4436 TLI.getPointerTy(DAG.getDataLayout()));
4437 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4438 CfaArg.getValueType(),
4439 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4440 CfaArg.getValueType()),
4442 SDValue FA = DAG.getNode(
4443 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4444 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4445 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4449 case Intrinsic::eh_sjlj_callsite: {
4450 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4451 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4452 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4453 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4455 MMI.setCurrentCallSite(CI->getZExtValue());
4458 case Intrinsic::eh_sjlj_functioncontext: {
4459 // Get and store the index of the function context.
4460 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4462 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4463 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4464 MFI->setFunctionContextIndex(FI);
4467 case Intrinsic::eh_sjlj_setjmp: {
4470 Ops[1] = getValue(I.getArgOperand(0));
4471 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4472 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4473 setValue(&I, Op.getValue(0));
4474 DAG.setRoot(Op.getValue(1));
4477 case Intrinsic::eh_sjlj_longjmp: {
4478 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4479 getRoot(), getValue(I.getArgOperand(0))));
4482 case Intrinsic::eh_sjlj_setup_dispatch: {
4483 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4488 case Intrinsic::masked_gather:
4489 visitMaskedGather(I);
4491 case Intrinsic::masked_load:
4494 case Intrinsic::masked_scatter:
4495 visitMaskedScatter(I);
4497 case Intrinsic::masked_store:
4498 visitMaskedStore(I);
4500 case Intrinsic::x86_mmx_pslli_w:
4501 case Intrinsic::x86_mmx_pslli_d:
4502 case Intrinsic::x86_mmx_pslli_q:
4503 case Intrinsic::x86_mmx_psrli_w:
4504 case Intrinsic::x86_mmx_psrli_d:
4505 case Intrinsic::x86_mmx_psrli_q:
4506 case Intrinsic::x86_mmx_psrai_w:
4507 case Intrinsic::x86_mmx_psrai_d: {
4508 SDValue ShAmt = getValue(I.getArgOperand(1));
4509 if (isa<ConstantSDNode>(ShAmt)) {
4510 visitTargetIntrinsic(I, Intrinsic);
4513 unsigned NewIntrinsic = 0;
4514 EVT ShAmtVT = MVT::v2i32;
4515 switch (Intrinsic) {
4516 case Intrinsic::x86_mmx_pslli_w:
4517 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4519 case Intrinsic::x86_mmx_pslli_d:
4520 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4522 case Intrinsic::x86_mmx_pslli_q:
4523 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4525 case Intrinsic::x86_mmx_psrli_w:
4526 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4528 case Intrinsic::x86_mmx_psrli_d:
4529 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4531 case Intrinsic::x86_mmx_psrli_q:
4532 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4534 case Intrinsic::x86_mmx_psrai_w:
4535 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4537 case Intrinsic::x86_mmx_psrai_d:
4538 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4540 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4543 // The vector shift intrinsics with scalars uses 32b shift amounts but
4544 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4546 // We must do this early because v2i32 is not a legal type.
4549 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4550 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4551 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4552 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4553 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4554 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4555 getValue(I.getArgOperand(0)), ShAmt);
4559 case Intrinsic::convertff:
4560 case Intrinsic::convertfsi:
4561 case Intrinsic::convertfui:
4562 case Intrinsic::convertsif:
4563 case Intrinsic::convertuif:
4564 case Intrinsic::convertss:
4565 case Intrinsic::convertsu:
4566 case Intrinsic::convertus:
4567 case Intrinsic::convertuu: {
4568 ISD::CvtCode Code = ISD::CVT_INVALID;
4569 switch (Intrinsic) {
4570 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4571 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4572 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4573 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4574 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4575 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4576 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4577 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4578 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4579 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4581 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4582 const Value *Op1 = I.getArgOperand(0);
4583 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4584 DAG.getValueType(DestVT),
4585 DAG.getValueType(getValue(Op1).getValueType()),
4586 getValue(I.getArgOperand(1)),
4587 getValue(I.getArgOperand(2)),
4592 case Intrinsic::powi:
4593 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4594 getValue(I.getArgOperand(1)), DAG));
4596 case Intrinsic::log:
4597 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4599 case Intrinsic::log2:
4600 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4602 case Intrinsic::log10:
4603 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4605 case Intrinsic::exp:
4606 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4608 case Intrinsic::exp2:
4609 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4611 case Intrinsic::pow:
4612 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4613 getValue(I.getArgOperand(1)), DAG, TLI));
4615 case Intrinsic::sqrt:
4616 case Intrinsic::fabs:
4617 case Intrinsic::sin:
4618 case Intrinsic::cos:
4619 case Intrinsic::floor:
4620 case Intrinsic::ceil:
4621 case Intrinsic::trunc:
4622 case Intrinsic::rint:
4623 case Intrinsic::nearbyint:
4624 case Intrinsic::round: {
4626 switch (Intrinsic) {
4627 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4628 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4629 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4630 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4631 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4632 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4633 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4634 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4635 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4636 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4637 case Intrinsic::round: Opcode = ISD::FROUND; break;
4640 setValue(&I, DAG.getNode(Opcode, sdl,
4641 getValue(I.getArgOperand(0)).getValueType(),
4642 getValue(I.getArgOperand(0))));
4645 case Intrinsic::minnum:
4646 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4647 getValue(I.getArgOperand(0)).getValueType(),
4648 getValue(I.getArgOperand(0)),
4649 getValue(I.getArgOperand(1))));
4651 case Intrinsic::maxnum:
4652 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4653 getValue(I.getArgOperand(0)).getValueType(),
4654 getValue(I.getArgOperand(0)),
4655 getValue(I.getArgOperand(1))));
4657 case Intrinsic::copysign:
4658 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4659 getValue(I.getArgOperand(0)).getValueType(),
4660 getValue(I.getArgOperand(0)),
4661 getValue(I.getArgOperand(1))));
4663 case Intrinsic::fma:
4664 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4665 getValue(I.getArgOperand(0)).getValueType(),
4666 getValue(I.getArgOperand(0)),
4667 getValue(I.getArgOperand(1)),
4668 getValue(I.getArgOperand(2))));
4670 case Intrinsic::fmuladd: {
4671 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4672 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4673 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4674 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4675 getValue(I.getArgOperand(0)).getValueType(),
4676 getValue(I.getArgOperand(0)),
4677 getValue(I.getArgOperand(1)),
4678 getValue(I.getArgOperand(2))));
4680 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4681 getValue(I.getArgOperand(0)).getValueType(),
4682 getValue(I.getArgOperand(0)),
4683 getValue(I.getArgOperand(1)));
4684 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4685 getValue(I.getArgOperand(0)).getValueType(),
4687 getValue(I.getArgOperand(2)));
4692 case Intrinsic::convert_to_fp16:
4693 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4694 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4695 getValue(I.getArgOperand(0)),
4696 DAG.getTargetConstant(0, sdl,
4699 case Intrinsic::convert_from_fp16:
4700 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4701 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4702 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4703 getValue(I.getArgOperand(0)))));
4705 case Intrinsic::pcmarker: {
4706 SDValue Tmp = getValue(I.getArgOperand(0));
4707 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4710 case Intrinsic::readcyclecounter: {
4711 SDValue Op = getRoot();
4712 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4713 DAG.getVTList(MVT::i64, MVT::Other), Op);
4715 DAG.setRoot(Res.getValue(1));
4718 case Intrinsic::bswap:
4719 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4720 getValue(I.getArgOperand(0)).getValueType(),
4721 getValue(I.getArgOperand(0))));
4723 case Intrinsic::uabsdiff:
4724 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4725 getValue(I.getArgOperand(0)).getValueType(),
4726 getValue(I.getArgOperand(0)),
4727 getValue(I.getArgOperand(1))));
4729 case Intrinsic::sabsdiff:
4730 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4731 getValue(I.getArgOperand(0)).getValueType(),
4732 getValue(I.getArgOperand(0)),
4733 getValue(I.getArgOperand(1))));
4735 case Intrinsic::cttz: {
4736 SDValue Arg = getValue(I.getArgOperand(0));
4737 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4738 EVT Ty = Arg.getValueType();
4739 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4743 case Intrinsic::ctlz: {
4744 SDValue Arg = getValue(I.getArgOperand(0));
4745 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4746 EVT Ty = Arg.getValueType();
4747 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4751 case Intrinsic::ctpop: {
4752 SDValue Arg = getValue(I.getArgOperand(0));
4753 EVT Ty = Arg.getValueType();
4754 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4757 case Intrinsic::stacksave: {
4758 SDValue Op = getRoot();
4760 ISD::STACKSAVE, sdl,
4761 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4763 DAG.setRoot(Res.getValue(1));
4766 case Intrinsic::stackrestore: {
4767 Res = getValue(I.getArgOperand(0));
4768 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4771 case Intrinsic::stackprotector: {
4772 // Emit code into the DAG to store the stack guard onto the stack.
4773 MachineFunction &MF = DAG.getMachineFunction();
4774 MachineFrameInfo *MFI = MF.getFrameInfo();
4775 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4776 SDValue Src, Chain = getRoot();
4777 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4778 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4780 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4781 // global variable __stack_chk_guard.
4783 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4784 if (BC->getOpcode() == Instruction::BitCast)
4785 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4787 if (GV && TLI.useLoadStackGuardNode()) {
4788 // Emit a LOAD_STACK_GUARD node.
4789 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4791 MachinePointerInfo MPInfo(GV);
4792 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4793 unsigned Flags = MachineMemOperand::MOLoad |
4794 MachineMemOperand::MOInvariant;
4795 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4796 PtrTy.getSizeInBits() / 8,
4797 DAG.getEVTAlignment(PtrTy));
4798 Node->setMemRefs(MemRefs, MemRefs + 1);
4800 // Copy the guard value to a virtual register so that it can be
4801 // retrieved in the epilogue.
4802 Src = SDValue(Node, 0);
4803 const TargetRegisterClass *RC =
4804 TLI.getRegClassFor(Src.getSimpleValueType());
4805 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4807 SPDescriptor.setGuardReg(Reg);
4808 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4810 Src = getValue(I.getArgOperand(0)); // The guard's value.
4813 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4815 int FI = FuncInfo.StaticAllocaMap[Slot];
4816 MFI->setStackProtectorIndex(FI);
4818 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4820 // Store the stack protector onto the stack.
4821 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4822 DAG.getMachineFunction(), FI),
4828 case Intrinsic::objectsize: {
4829 // If we don't know by now, we're never going to know.
4830 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4832 assert(CI && "Non-constant type in __builtin_object_size?");
4834 SDValue Arg = getValue(I.getCalledValue());
4835 EVT Ty = Arg.getValueType();
4838 Res = DAG.getConstant(-1ULL, sdl, Ty);
4840 Res = DAG.getConstant(0, sdl, Ty);
4845 case Intrinsic::annotation:
4846 case Intrinsic::ptr_annotation:
4847 // Drop the intrinsic, but forward the value
4848 setValue(&I, getValue(I.getOperand(0)));
4850 case Intrinsic::assume:
4851 case Intrinsic::var_annotation:
4852 // Discard annotate attributes and assumptions
4855 case Intrinsic::init_trampoline: {
4856 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4860 Ops[1] = getValue(I.getArgOperand(0));
4861 Ops[2] = getValue(I.getArgOperand(1));
4862 Ops[3] = getValue(I.getArgOperand(2));
4863 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4864 Ops[5] = DAG.getSrcValue(F);
4866 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4871 case Intrinsic::adjust_trampoline: {
4872 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4873 TLI.getPointerTy(DAG.getDataLayout()),
4874 getValue(I.getArgOperand(0))));
4877 case Intrinsic::gcroot:
4879 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4880 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4882 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4883 GFI->addStackRoot(FI->getIndex(), TypeMap);
4886 case Intrinsic::gcread:
4887 case Intrinsic::gcwrite:
4888 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4889 case Intrinsic::flt_rounds:
4890 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4893 case Intrinsic::expect: {
4894 // Just replace __builtin_expect(exp, c) with EXP.
4895 setValue(&I, getValue(I.getArgOperand(0)));
4899 case Intrinsic::debugtrap:
4900 case Intrinsic::trap: {
4901 StringRef TrapFuncName =
4903 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4904 .getValueAsString();
4905 if (TrapFuncName.empty()) {
4906 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4907 ISD::TRAP : ISD::DEBUGTRAP;
4908 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4911 TargetLowering::ArgListTy Args;
4913 TargetLowering::CallLoweringInfo CLI(DAG);
4914 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4915 CallingConv::C, I.getType(),
4916 DAG.getExternalSymbol(TrapFuncName.data(),
4917 TLI.getPointerTy(DAG.getDataLayout())),
4918 std::move(Args), 0);
4920 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4921 DAG.setRoot(Result.second);
4925 case Intrinsic::uadd_with_overflow:
4926 case Intrinsic::sadd_with_overflow:
4927 case Intrinsic::usub_with_overflow:
4928 case Intrinsic::ssub_with_overflow:
4929 case Intrinsic::umul_with_overflow:
4930 case Intrinsic::smul_with_overflow: {
4932 switch (Intrinsic) {
4933 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4934 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4935 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4936 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4937 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4938 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4939 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4941 SDValue Op1 = getValue(I.getArgOperand(0));
4942 SDValue Op2 = getValue(I.getArgOperand(1));
4944 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4945 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4948 case Intrinsic::prefetch: {
4950 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4952 Ops[1] = getValue(I.getArgOperand(0));
4953 Ops[2] = getValue(I.getArgOperand(1));
4954 Ops[3] = getValue(I.getArgOperand(2));
4955 Ops[4] = getValue(I.getArgOperand(3));
4956 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4957 DAG.getVTList(MVT::Other), Ops,
4958 EVT::getIntegerVT(*Context, 8),
4959 MachinePointerInfo(I.getArgOperand(0)),
4961 false, /* volatile */
4963 rw==1)); /* write */
4966 case Intrinsic::lifetime_start:
4967 case Intrinsic::lifetime_end: {
4968 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4969 // Stack coloring is not enabled in O0, discard region information.
4970 if (TM.getOptLevel() == CodeGenOpt::None)
4973 SmallVector<Value *, 4> Allocas;
4974 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4976 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4977 E = Allocas.end(); Object != E; ++Object) {
4978 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4980 // Could not find an Alloca.
4981 if (!LifetimeObject)
4984 // First check that the Alloca is static, otherwise it won't have a
4985 // valid frame index.
4986 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4987 if (SI == FuncInfo.StaticAllocaMap.end())
4990 int FI = SI->second;
4995 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
4996 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4998 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5003 case Intrinsic::invariant_start:
5004 // Discard region information.
5005 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5007 case Intrinsic::invariant_end:
5008 // Discard region information.
5010 case Intrinsic::stackprotectorcheck: {
5011 // Do not actually emit anything for this basic block. Instead we initialize
5012 // the stack protector descriptor and export the guard variable so we can
5013 // access it in FinishBasicBlock.
5014 const BasicBlock *BB = I.getParent();
5015 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5016 ExportFromCurrentBlock(SPDescriptor.getGuard());
5018 // Flush our exports since we are going to process a terminator.
5019 (void)getControlRoot();
5022 case Intrinsic::clear_cache:
5023 return TLI.getClearCacheBuiltinName();
5024 case Intrinsic::eh_actions:
5025 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5027 case Intrinsic::donothing:
5030 case Intrinsic::experimental_stackmap: {
5034 case Intrinsic::experimental_patchpoint_void:
5035 case Intrinsic::experimental_patchpoint_i64: {
5036 visitPatchpoint(&I);
5039 case Intrinsic::experimental_gc_statepoint: {
5043 case Intrinsic::experimental_gc_result_int:
5044 case Intrinsic::experimental_gc_result_float:
5045 case Intrinsic::experimental_gc_result_ptr:
5046 case Intrinsic::experimental_gc_result: {
5050 case Intrinsic::experimental_gc_relocate: {
5054 case Intrinsic::instrprof_increment:
5055 llvm_unreachable("instrprof failed to lower an increment");
5057 case Intrinsic::localescape: {
5058 MachineFunction &MF = DAG.getMachineFunction();
5059 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5061 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5062 // is the same on all targets.
5063 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5064 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5065 if (isa<ConstantPointerNull>(Arg))
5066 continue; // Skip null pointers. They represent a hole in index space.
5067 AllocaInst *Slot = cast<AllocaInst>(Arg);
5068 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5069 "can only escape static allocas");
5070 int FI = FuncInfo.StaticAllocaMap[Slot];
5071 MCSymbol *FrameAllocSym =
5072 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5073 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5074 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5075 TII->get(TargetOpcode::LOCAL_ESCAPE))
5076 .addSym(FrameAllocSym)
5083 case Intrinsic::localrecover: {
5084 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5085 MachineFunction &MF = DAG.getMachineFunction();
5086 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5088 // Get the symbol that defines the frame offset.
5089 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5090 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5091 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5092 MCSymbol *FrameAllocSym =
5093 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5094 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5096 // Create a MCSymbol for the label to avoid any target lowering
5097 // that would make this PC relative.
5098 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5100 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5102 // Add the offset to the FP.
5103 Value *FP = I.getArgOperand(1);
5104 SDValue FPVal = getValue(FP);
5105 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5110 case Intrinsic::eh_begincatch:
5111 case Intrinsic::eh_endcatch:
5112 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5113 case Intrinsic::eh_exceptioncode: {
5114 unsigned Reg = TLI.getExceptionPointerRegister();
5115 assert(Reg && "cannot get exception code on this platform");
5116 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5117 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5118 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5119 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5121 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5122 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5129 std::pair<SDValue, SDValue>
5130 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5131 MachineBasicBlock *LandingPad) {
5132 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5133 MCSymbol *BeginLabel = nullptr;
5136 // Insert a label before the invoke call to mark the try range. This can be
5137 // used to detect deletion of the invoke via the MachineModuleInfo.
5138 BeginLabel = MMI.getContext().createTempSymbol();
5140 // For SjLj, keep track of which landing pads go with which invokes
5141 // so as to maintain the ordering of pads in the LSDA.
5142 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5143 if (CallSiteIndex) {
5144 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5145 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5147 // Now that the call site is handled, stop tracking it.
5148 MMI.setCurrentCallSite(0);
5151 // Both PendingLoads and PendingExports must be flushed here;
5152 // this call might not return.
5154 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5156 CLI.setChain(getRoot());
5158 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5159 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5161 assert((CLI.IsTailCall || Result.second.getNode()) &&
5162 "Non-null chain expected with non-tail call!");
5163 assert((Result.second.getNode() || !Result.first.getNode()) &&
5164 "Null value expected with tail call!");
5166 if (!Result.second.getNode()) {
5167 // As a special case, a null chain means that a tail call has been emitted
5168 // and the DAG root is already updated.
5171 // Since there's no actual continuation from this block, nothing can be
5172 // relying on us setting vregs for them.
5173 PendingExports.clear();
5175 DAG.setRoot(Result.second);
5179 // Insert a label at the end of the invoke call to mark the try range. This
5180 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5181 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5182 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5184 // Inform MachineModuleInfo of range.
5185 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5191 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5193 MachineBasicBlock *LandingPad) {
5194 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5195 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5196 Type *RetTy = FTy->getReturnType();
5198 TargetLowering::ArgListTy Args;
5199 TargetLowering::ArgListEntry Entry;
5200 Args.reserve(CS.arg_size());
5202 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5204 const Value *V = *i;
5207 if (V->getType()->isEmptyTy())
5210 SDValue ArgNode = getValue(V);
5211 Entry.Node = ArgNode; Entry.Ty = V->getType();
5213 // Skip the first return-type Attribute to get to params.
5214 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5215 Args.push_back(Entry);
5217 // If we have an explicit sret argument that is an Instruction, (i.e., it
5218 // might point to function-local memory), we can't meaningfully tail-call.
5219 if (Entry.isSRet && isa<Instruction>(V))
5223 // Check if target-independent constraints permit a tail call here.
5224 // Target-dependent constraints are checked within TLI->LowerCallTo.
5225 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5228 TargetLowering::CallLoweringInfo CLI(DAG);
5229 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5230 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5231 .setTailCall(isTailCall);
5232 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5234 if (Result.first.getNode())
5235 setValue(CS.getInstruction(), Result.first);
5238 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5239 /// value is equal or not-equal to zero.
5240 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5241 for (const User *U : V->users()) {
5242 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5243 if (IC->isEquality())
5244 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5245 if (C->isNullValue())
5247 // Unknown instruction.
5253 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5255 SelectionDAGBuilder &Builder) {
5257 // Check to see if this load can be trivially constant folded, e.g. if the
5258 // input is from a string literal.
5259 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5260 // Cast pointer to the type we really want to load.
5261 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5262 PointerType::getUnqual(LoadTy));
5264 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5265 const_cast<Constant *>(LoadInput), *Builder.DL))
5266 return Builder.getValue(LoadCst);
5269 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5270 // still constant memory, the input chain can be the entry node.
5272 bool ConstantMemory = false;
5274 // Do not serialize (non-volatile) loads of constant memory with anything.
5275 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5276 Root = Builder.DAG.getEntryNode();
5277 ConstantMemory = true;
5279 // Do not serialize non-volatile loads against each other.
5280 Root = Builder.DAG.getRoot();
5283 SDValue Ptr = Builder.getValue(PtrVal);
5284 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5285 Ptr, MachinePointerInfo(PtrVal),
5287 false /*nontemporal*/,
5288 false /*isinvariant*/, 1 /* align=1 */);
5290 if (!ConstantMemory)
5291 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5295 /// processIntegerCallValue - Record the value for an instruction that
5296 /// produces an integer result, converting the type where necessary.
5297 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5300 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5303 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5305 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5306 setValue(&I, Value);
5309 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5310 /// If so, return true and lower it, otherwise return false and it will be
5311 /// lowered like a normal call.
5312 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5313 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5314 if (I.getNumArgOperands() != 3)
5317 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5318 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5319 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5320 !I.getType()->isIntegerTy())
5323 const Value *Size = I.getArgOperand(2);
5324 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5325 if (CSize && CSize->getZExtValue() == 0) {
5326 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5328 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5332 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5333 std::pair<SDValue, SDValue> Res =
5334 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5335 getValue(LHS), getValue(RHS), getValue(Size),
5336 MachinePointerInfo(LHS),
5337 MachinePointerInfo(RHS));
5338 if (Res.first.getNode()) {
5339 processIntegerCallValue(I, Res.first, true);
5340 PendingLoads.push_back(Res.second);
5344 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5345 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5346 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5347 bool ActuallyDoIt = true;
5350 switch (CSize->getZExtValue()) {
5352 LoadVT = MVT::Other;
5354 ActuallyDoIt = false;
5358 LoadTy = Type::getInt16Ty(CSize->getContext());
5362 LoadTy = Type::getInt32Ty(CSize->getContext());
5366 LoadTy = Type::getInt64Ty(CSize->getContext());
5370 LoadVT = MVT::v4i32;
5371 LoadTy = Type::getInt32Ty(CSize->getContext());
5372 LoadTy = VectorType::get(LoadTy, 4);
5377 // This turns into unaligned loads. We only do this if the target natively
5378 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5379 // we'll only produce a small number of byte loads.
5381 // Require that we can find a legal MVT, and only do this if the target
5382 // supports unaligned loads of that type. Expanding into byte loads would
5384 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5385 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5386 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5387 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5388 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5389 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5390 // TODO: Check alignment of src and dest ptrs.
5391 if (!TLI.isTypeLegal(LoadVT) ||
5392 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5393 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5394 ActuallyDoIt = false;
5398 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5399 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5401 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5403 processIntegerCallValue(I, Res, false);
5412 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5413 /// form. If so, return true and lower it, otherwise return false and it
5414 /// will be lowered like a normal call.
5415 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5416 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5417 if (I.getNumArgOperands() != 3)
5420 const Value *Src = I.getArgOperand(0);
5421 const Value *Char = I.getArgOperand(1);
5422 const Value *Length = I.getArgOperand(2);
5423 if (!Src->getType()->isPointerTy() ||
5424 !Char->getType()->isIntegerTy() ||
5425 !Length->getType()->isIntegerTy() ||
5426 !I.getType()->isPointerTy())
5429 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5430 std::pair<SDValue, SDValue> Res =
5431 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5432 getValue(Src), getValue(Char), getValue(Length),
5433 MachinePointerInfo(Src));
5434 if (Res.first.getNode()) {
5435 setValue(&I, Res.first);
5436 PendingLoads.push_back(Res.second);
5443 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5444 /// optimized form. If so, return true and lower it, otherwise return false
5445 /// and it will be lowered like a normal call.
5446 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5447 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5448 if (I.getNumArgOperands() != 2)
5451 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5452 if (!Arg0->getType()->isPointerTy() ||
5453 !Arg1->getType()->isPointerTy() ||
5454 !I.getType()->isPointerTy())
5457 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5458 std::pair<SDValue, SDValue> Res =
5459 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5460 getValue(Arg0), getValue(Arg1),
5461 MachinePointerInfo(Arg0),
5462 MachinePointerInfo(Arg1), isStpcpy);
5463 if (Res.first.getNode()) {
5464 setValue(&I, Res.first);
5465 DAG.setRoot(Res.second);
5472 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5473 /// If so, return true and lower it, otherwise return false and it will be
5474 /// lowered like a normal call.
5475 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5476 // Verify that the prototype makes sense. int strcmp(void*,void*)
5477 if (I.getNumArgOperands() != 2)
5480 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5481 if (!Arg0->getType()->isPointerTy() ||
5482 !Arg1->getType()->isPointerTy() ||
5483 !I.getType()->isIntegerTy())
5486 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5487 std::pair<SDValue, SDValue> Res =
5488 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5489 getValue(Arg0), getValue(Arg1),
5490 MachinePointerInfo(Arg0),
5491 MachinePointerInfo(Arg1));
5492 if (Res.first.getNode()) {
5493 processIntegerCallValue(I, Res.first, true);
5494 PendingLoads.push_back(Res.second);
5501 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5502 /// form. If so, return true and lower it, otherwise return false and it
5503 /// will be lowered like a normal call.
5504 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5505 // Verify that the prototype makes sense. size_t strlen(char *)
5506 if (I.getNumArgOperands() != 1)
5509 const Value *Arg0 = I.getArgOperand(0);
5510 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5513 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5514 std::pair<SDValue, SDValue> Res =
5515 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5516 getValue(Arg0), MachinePointerInfo(Arg0));
5517 if (Res.first.getNode()) {
5518 processIntegerCallValue(I, Res.first, false);
5519 PendingLoads.push_back(Res.second);
5526 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5527 /// form. If so, return true and lower it, otherwise return false and it
5528 /// will be lowered like a normal call.
5529 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5530 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5531 if (I.getNumArgOperands() != 2)
5534 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5535 if (!Arg0->getType()->isPointerTy() ||
5536 !Arg1->getType()->isIntegerTy() ||
5537 !I.getType()->isIntegerTy())
5540 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5541 std::pair<SDValue, SDValue> Res =
5542 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5543 getValue(Arg0), getValue(Arg1),
5544 MachinePointerInfo(Arg0));
5545 if (Res.first.getNode()) {
5546 processIntegerCallValue(I, Res.first, false);
5547 PendingLoads.push_back(Res.second);
5554 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5555 /// operation (as expected), translate it to an SDNode with the specified opcode
5556 /// and return true.
5557 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5559 // Sanity check that it really is a unary floating-point call.
5560 if (I.getNumArgOperands() != 1 ||
5561 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5562 I.getType() != I.getArgOperand(0)->getType() ||
5563 !I.onlyReadsMemory())
5566 SDValue Tmp = getValue(I.getArgOperand(0));
5567 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5571 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5572 /// operation (as expected), translate it to an SDNode with the specified opcode
5573 /// and return true.
5574 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5576 // Sanity check that it really is a binary floating-point call.
5577 if (I.getNumArgOperands() != 2 ||
5578 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5579 I.getType() != I.getArgOperand(0)->getType() ||
5580 I.getType() != I.getArgOperand(1)->getType() ||
5581 !I.onlyReadsMemory())
5584 SDValue Tmp0 = getValue(I.getArgOperand(0));
5585 SDValue Tmp1 = getValue(I.getArgOperand(1));
5586 EVT VT = Tmp0.getValueType();
5587 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5591 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5592 // Handle inline assembly differently.
5593 if (isa<InlineAsm>(I.getCalledValue())) {
5598 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5599 ComputeUsesVAFloatArgument(I, &MMI);
5601 const char *RenameFn = nullptr;
5602 if (Function *F = I.getCalledFunction()) {
5603 if (F->isDeclaration()) {
5604 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5605 if (unsigned IID = II->getIntrinsicID(F)) {
5606 RenameFn = visitIntrinsicCall(I, IID);
5611 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5612 RenameFn = visitIntrinsicCall(I, IID);
5618 // Check for well-known libc/libm calls. If the function is internal, it
5619 // can't be a library call.
5621 if (!F->hasLocalLinkage() && F->hasName() &&
5622 LibInfo->getLibFunc(F->getName(), Func) &&
5623 LibInfo->hasOptimizedCodeGen(Func)) {
5626 case LibFunc::copysign:
5627 case LibFunc::copysignf:
5628 case LibFunc::copysignl:
5629 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5630 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5631 I.getType() == I.getArgOperand(0)->getType() &&
5632 I.getType() == I.getArgOperand(1)->getType() &&
5633 I.onlyReadsMemory()) {
5634 SDValue LHS = getValue(I.getArgOperand(0));
5635 SDValue RHS = getValue(I.getArgOperand(1));
5636 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5637 LHS.getValueType(), LHS, RHS));
5642 case LibFunc::fabsf:
5643 case LibFunc::fabsl:
5644 if (visitUnaryFloatCall(I, ISD::FABS))
5648 case LibFunc::fminf:
5649 case LibFunc::fminl:
5650 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5654 case LibFunc::fmaxf:
5655 case LibFunc::fmaxl:
5656 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5662 if (visitUnaryFloatCall(I, ISD::FSIN))
5668 if (visitUnaryFloatCall(I, ISD::FCOS))
5672 case LibFunc::sqrtf:
5673 case LibFunc::sqrtl:
5674 case LibFunc::sqrt_finite:
5675 case LibFunc::sqrtf_finite:
5676 case LibFunc::sqrtl_finite:
5677 if (visitUnaryFloatCall(I, ISD::FSQRT))
5680 case LibFunc::floor:
5681 case LibFunc::floorf:
5682 case LibFunc::floorl:
5683 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5686 case LibFunc::nearbyint:
5687 case LibFunc::nearbyintf:
5688 case LibFunc::nearbyintl:
5689 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5693 case LibFunc::ceilf:
5694 case LibFunc::ceill:
5695 if (visitUnaryFloatCall(I, ISD::FCEIL))
5699 case LibFunc::rintf:
5700 case LibFunc::rintl:
5701 if (visitUnaryFloatCall(I, ISD::FRINT))
5704 case LibFunc::round:
5705 case LibFunc::roundf:
5706 case LibFunc::roundl:
5707 if (visitUnaryFloatCall(I, ISD::FROUND))
5710 case LibFunc::trunc:
5711 case LibFunc::truncf:
5712 case LibFunc::truncl:
5713 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5717 case LibFunc::log2f:
5718 case LibFunc::log2l:
5719 if (visitUnaryFloatCall(I, ISD::FLOG2))
5723 case LibFunc::exp2f:
5724 case LibFunc::exp2l:
5725 if (visitUnaryFloatCall(I, ISD::FEXP2))
5728 case LibFunc::memcmp:
5729 if (visitMemCmpCall(I))
5732 case LibFunc::memchr:
5733 if (visitMemChrCall(I))
5736 case LibFunc::strcpy:
5737 if (visitStrCpyCall(I, false))
5740 case LibFunc::stpcpy:
5741 if (visitStrCpyCall(I, true))
5744 case LibFunc::strcmp:
5745 if (visitStrCmpCall(I))
5748 case LibFunc::strlen:
5749 if (visitStrLenCall(I))
5752 case LibFunc::strnlen:
5753 if (visitStrNLenCall(I))
5762 Callee = getValue(I.getCalledValue());
5764 Callee = DAG.getExternalSymbol(
5766 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5768 // Check if we can potentially perform a tail call. More detailed checking is
5769 // be done within LowerCallTo, after more information about the call is known.
5770 LowerCallTo(&I, Callee, I.isTailCall());
5775 /// AsmOperandInfo - This contains information for each constraint that we are
5777 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5779 /// CallOperand - If this is the result output operand or a clobber
5780 /// this is null, otherwise it is the incoming operand to the CallInst.
5781 /// This gets modified as the asm is processed.
5782 SDValue CallOperand;
5784 /// AssignedRegs - If this is a register or register class operand, this
5785 /// contains the set of register corresponding to the operand.
5786 RegsForValue AssignedRegs;
5788 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5789 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5792 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5793 /// corresponds to. If there is no Value* for this operand, it returns
5795 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5796 const DataLayout &DL) const {
5797 if (!CallOperandVal) return MVT::Other;
5799 if (isa<BasicBlock>(CallOperandVal))
5800 return TLI.getPointerTy(DL);
5802 llvm::Type *OpTy = CallOperandVal->getType();
5804 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5805 // If this is an indirect operand, the operand is a pointer to the
5808 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5810 report_fatal_error("Indirect operand for inline asm not a pointer!");
5811 OpTy = PtrTy->getElementType();
5814 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5815 if (StructType *STy = dyn_cast<StructType>(OpTy))
5816 if (STy->getNumElements() == 1)
5817 OpTy = STy->getElementType(0);
5819 // If OpTy is not a single value, it may be a struct/union that we
5820 // can tile with integers.
5821 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5822 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5831 OpTy = IntegerType::get(Context, BitSize);
5836 return TLI.getValueType(DL, OpTy, true);
5840 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5842 } // end anonymous namespace
5844 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5845 /// specified operand. We prefer to assign virtual registers, to allow the
5846 /// register allocator to handle the assignment process. However, if the asm
5847 /// uses features that we can't model on machineinstrs, we have SDISel do the
5848 /// allocation. This produces generally horrible, but correct, code.
5850 /// OpInfo describes the operand.
5852 static void GetRegistersForValue(SelectionDAG &DAG,
5853 const TargetLowering &TLI,
5855 SDISelAsmOperandInfo &OpInfo) {
5856 LLVMContext &Context = *DAG.getContext();
5858 MachineFunction &MF = DAG.getMachineFunction();
5859 SmallVector<unsigned, 4> Regs;
5861 // If this is a constraint for a single physreg, or a constraint for a
5862 // register class, find it.
5863 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5864 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5865 OpInfo.ConstraintCode,
5866 OpInfo.ConstraintVT);
5868 unsigned NumRegs = 1;
5869 if (OpInfo.ConstraintVT != MVT::Other) {
5870 // If this is a FP input in an integer register (or visa versa) insert a bit
5871 // cast of the input value. More generally, handle any case where the input
5872 // value disagrees with the register class we plan to stick this in.
5873 if (OpInfo.Type == InlineAsm::isInput &&
5874 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5875 // Try to convert to the first EVT that the reg class contains. If the
5876 // types are identical size, use a bitcast to convert (e.g. two differing
5878 MVT RegVT = *PhysReg.second->vt_begin();
5879 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5880 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5881 RegVT, OpInfo.CallOperand);
5882 OpInfo.ConstraintVT = RegVT;
5883 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5884 // If the input is a FP value and we want it in FP registers, do a
5885 // bitcast to the corresponding integer type. This turns an f64 value
5886 // into i64, which can be passed with two i32 values on a 32-bit
5888 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5889 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5890 RegVT, OpInfo.CallOperand);
5891 OpInfo.ConstraintVT = RegVT;
5895 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5899 EVT ValueVT = OpInfo.ConstraintVT;
5901 // If this is a constraint for a specific physical register, like {r17},
5903 if (unsigned AssignedReg = PhysReg.first) {
5904 const TargetRegisterClass *RC = PhysReg.second;
5905 if (OpInfo.ConstraintVT == MVT::Other)
5906 ValueVT = *RC->vt_begin();
5908 // Get the actual register value type. This is important, because the user
5909 // may have asked for (e.g.) the AX register in i32 type. We need to
5910 // remember that AX is actually i16 to get the right extension.
5911 RegVT = *RC->vt_begin();
5913 // This is a explicit reference to a physical register.
5914 Regs.push_back(AssignedReg);
5916 // If this is an expanded reference, add the rest of the regs to Regs.
5918 TargetRegisterClass::iterator I = RC->begin();
5919 for (; *I != AssignedReg; ++I)
5920 assert(I != RC->end() && "Didn't find reg!");
5922 // Already added the first reg.
5924 for (; NumRegs; --NumRegs, ++I) {
5925 assert(I != RC->end() && "Ran out of registers to allocate!");
5930 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5934 // Otherwise, if this was a reference to an LLVM register class, create vregs
5935 // for this reference.
5936 if (const TargetRegisterClass *RC = PhysReg.second) {
5937 RegVT = *RC->vt_begin();
5938 if (OpInfo.ConstraintVT == MVT::Other)
5941 // Create the appropriate number of virtual registers.
5942 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5943 for (; NumRegs; --NumRegs)
5944 Regs.push_back(RegInfo.createVirtualRegister(RC));
5946 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5950 // Otherwise, we couldn't allocate enough registers for this.
5953 /// visitInlineAsm - Handle a call to an InlineAsm object.
5955 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5956 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5958 /// ConstraintOperands - Information about all of the constraints.
5959 SDISelAsmOperandInfoVector ConstraintOperands;
5961 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5962 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5963 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5965 bool hasMemory = false;
5967 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5968 unsigned ResNo = 0; // ResNo - The result number of the next output.
5969 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5970 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5971 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5973 MVT OpVT = MVT::Other;
5975 // Compute the value type for each operand.
5976 switch (OpInfo.Type) {
5977 case InlineAsm::isOutput:
5978 // Indirect outputs just consume an argument.
5979 if (OpInfo.isIndirect) {
5980 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5984 // The return value of the call is this value. As such, there is no
5985 // corresponding argument.
5986 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5987 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5988 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
5989 STy->getElementType(ResNo));
5991 assert(ResNo == 0 && "Asm only has one result!");
5992 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
5996 case InlineAsm::isInput:
5997 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5999 case InlineAsm::isClobber:
6004 // If this is an input or an indirect output, process the call argument.
6005 // BasicBlocks are labels, currently appearing only in asm's.
6006 if (OpInfo.CallOperandVal) {
6007 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6008 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6010 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6013 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6014 DAG.getDataLayout()).getSimpleVT();
6017 OpInfo.ConstraintVT = OpVT;
6019 // Indirect operand accesses access memory.
6020 if (OpInfo.isIndirect)
6023 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6024 TargetLowering::ConstraintType
6025 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6026 if (CType == TargetLowering::C_Memory) {
6034 SDValue Chain, Flag;
6036 // We won't need to flush pending loads if this asm doesn't touch
6037 // memory and is nonvolatile.
6038 if (hasMemory || IA->hasSideEffects())
6041 Chain = DAG.getRoot();
6043 // Second pass over the constraints: compute which constraint option to use
6044 // and assign registers to constraints that want a specific physreg.
6045 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6046 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6048 // If this is an output operand with a matching input operand, look up the
6049 // matching input. If their types mismatch, e.g. one is an integer, the
6050 // other is floating point, or their sizes are different, flag it as an
6052 if (OpInfo.hasMatchingInput()) {
6053 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6055 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6056 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6057 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6058 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6059 OpInfo.ConstraintVT);
6060 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6061 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6062 Input.ConstraintVT);
6063 if ((OpInfo.ConstraintVT.isInteger() !=
6064 Input.ConstraintVT.isInteger()) ||
6065 (MatchRC.second != InputRC.second)) {
6066 report_fatal_error("Unsupported asm: input constraint"
6067 " with a matching output constraint of"
6068 " incompatible type!");
6070 Input.ConstraintVT = OpInfo.ConstraintVT;
6074 // Compute the constraint code and ConstraintType to use.
6075 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6077 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6078 OpInfo.Type == InlineAsm::isClobber)
6081 // If this is a memory input, and if the operand is not indirect, do what we
6082 // need to to provide an address for the memory input.
6083 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6084 !OpInfo.isIndirect) {
6085 assert((OpInfo.isMultipleAlternative ||
6086 (OpInfo.Type == InlineAsm::isInput)) &&
6087 "Can only indirectify direct input operands!");
6089 // Memory operands really want the address of the value. If we don't have
6090 // an indirect input, put it in the constpool if we can, otherwise spill
6091 // it to a stack slot.
6092 // TODO: This isn't quite right. We need to handle these according to
6093 // the addressing mode that the constraint wants. Also, this may take
6094 // an additional register for the computation and we don't want that
6097 // If the operand is a float, integer, or vector constant, spill to a
6098 // constant pool entry to get its address.
6099 const Value *OpVal = OpInfo.CallOperandVal;
6100 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6101 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6102 OpInfo.CallOperand = DAG.getConstantPool(
6103 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6105 // Otherwise, create a stack slot and emit a store to it before the
6107 Type *Ty = OpVal->getType();
6108 auto &DL = DAG.getDataLayout();
6109 uint64_t TySize = DL.getTypeAllocSize(Ty);
6110 unsigned Align = DL.getPrefTypeAlignment(Ty);
6111 MachineFunction &MF = DAG.getMachineFunction();
6112 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6114 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6115 Chain = DAG.getStore(
6116 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6117 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6119 OpInfo.CallOperand = StackSlot;
6122 // There is no longer a Value* corresponding to this operand.
6123 OpInfo.CallOperandVal = nullptr;
6125 // It is now an indirect operand.
6126 OpInfo.isIndirect = true;
6129 // If this constraint is for a specific register, allocate it before
6131 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6132 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6135 // Second pass - Loop over all of the operands, assigning virtual or physregs
6136 // to register class operands.
6137 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6138 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6140 // C_Register operands have already been allocated, Other/Memory don't need
6142 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6143 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6146 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6147 std::vector<SDValue> AsmNodeOperands;
6148 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6149 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6150 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6152 // If we have a !srcloc metadata node associated with it, we want to attach
6153 // this to the ultimately generated inline asm machineinstr. To do this, we
6154 // pass in the third operand as this (potentially null) inline asm MDNode.
6155 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6156 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6158 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6159 // bits as operand 3.
6160 unsigned ExtraInfo = 0;
6161 if (IA->hasSideEffects())
6162 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6163 if (IA->isAlignStack())
6164 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6165 // Set the asm dialect.
6166 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6168 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6169 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6170 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6172 // Compute the constraint code and ConstraintType to use.
6173 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6175 // Ideally, we would only check against memory constraints. However, the
6176 // meaning of an other constraint can be target-specific and we can't easily
6177 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6178 // for other constriants as well.
6179 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6180 OpInfo.ConstraintType == TargetLowering::C_Other) {
6181 if (OpInfo.Type == InlineAsm::isInput)
6182 ExtraInfo |= InlineAsm::Extra_MayLoad;
6183 else if (OpInfo.Type == InlineAsm::isOutput)
6184 ExtraInfo |= InlineAsm::Extra_MayStore;
6185 else if (OpInfo.Type == InlineAsm::isClobber)
6186 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6190 AsmNodeOperands.push_back(DAG.getTargetConstant(
6191 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6193 // Loop over all of the inputs, copying the operand values into the
6194 // appropriate registers and processing the output regs.
6195 RegsForValue RetValRegs;
6197 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6198 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6200 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6201 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6203 switch (OpInfo.Type) {
6204 case InlineAsm::isOutput: {
6205 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6206 OpInfo.ConstraintType != TargetLowering::C_Register) {
6207 // Memory output, or 'other' output (e.g. 'X' constraint).
6208 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6210 unsigned ConstraintID =
6211 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6212 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6213 "Failed to convert memory constraint code to constraint id.");
6215 // Add information to the INLINEASM node to know about this output.
6216 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6217 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6218 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6220 AsmNodeOperands.push_back(OpInfo.CallOperand);
6224 // Otherwise, this is a register or register class output.
6226 // Copy the output from the appropriate register. Find a register that
6228 if (OpInfo.AssignedRegs.Regs.empty()) {
6229 LLVMContext &Ctx = *DAG.getContext();
6230 Ctx.emitError(CS.getInstruction(),
6231 "couldn't allocate output register for constraint '" +
6232 Twine(OpInfo.ConstraintCode) + "'");
6236 // If this is an indirect operand, store through the pointer after the
6238 if (OpInfo.isIndirect) {
6239 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6240 OpInfo.CallOperandVal));
6242 // This is the result value of the call.
6243 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6244 // Concatenate this output onto the outputs list.
6245 RetValRegs.append(OpInfo.AssignedRegs);
6248 // Add information to the INLINEASM node to know that this register is
6251 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6252 ? InlineAsm::Kind_RegDefEarlyClobber
6253 : InlineAsm::Kind_RegDef,
6254 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6257 case InlineAsm::isInput: {
6258 SDValue InOperandVal = OpInfo.CallOperand;
6260 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6261 // If this is required to match an output register we have already set,
6262 // just use its register.
6263 unsigned OperandNo = OpInfo.getMatchedOperand();
6265 // Scan until we find the definition we already emitted of this operand.
6266 // When we find it, create a RegsForValue operand.
6267 unsigned CurOp = InlineAsm::Op_FirstOperand;
6268 for (; OperandNo; --OperandNo) {
6269 // Advance to the next operand.
6271 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6272 assert((InlineAsm::isRegDefKind(OpFlag) ||
6273 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6274 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6275 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6279 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6280 if (InlineAsm::isRegDefKind(OpFlag) ||
6281 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6282 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6283 if (OpInfo.isIndirect) {
6284 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6285 LLVMContext &Ctx = *DAG.getContext();
6286 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6287 " don't know how to handle tied "
6288 "indirect register inputs");
6292 RegsForValue MatchedRegs;
6293 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6294 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6295 MatchedRegs.RegVTs.push_back(RegVT);
6296 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6297 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6299 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6300 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6302 LLVMContext &Ctx = *DAG.getContext();
6303 Ctx.emitError(CS.getInstruction(),
6304 "inline asm error: This value"
6305 " type register class is not natively supported!");
6309 SDLoc dl = getCurSDLoc();
6310 // Use the produced MatchedRegs object to
6311 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6312 Chain, &Flag, CS.getInstruction());
6313 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6314 true, OpInfo.getMatchedOperand(), dl,
6315 DAG, AsmNodeOperands);
6319 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6320 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6321 "Unexpected number of operands");
6322 // Add information to the INLINEASM node to know about this input.
6323 // See InlineAsm.h isUseOperandTiedToDef.
6324 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6325 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6326 OpInfo.getMatchedOperand());
6327 AsmNodeOperands.push_back(DAG.getTargetConstant(
6328 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6329 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6333 // Treat indirect 'X' constraint as memory.
6334 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6336 OpInfo.ConstraintType = TargetLowering::C_Memory;
6338 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6339 std::vector<SDValue> Ops;
6340 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6343 LLVMContext &Ctx = *DAG.getContext();
6344 Ctx.emitError(CS.getInstruction(),
6345 "invalid operand for inline asm constraint '" +
6346 Twine(OpInfo.ConstraintCode) + "'");
6350 // Add information to the INLINEASM node to know about this input.
6351 unsigned ResOpType =
6352 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6353 AsmNodeOperands.push_back(DAG.getTargetConstant(
6354 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6355 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6359 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6360 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6361 assert(InOperandVal.getValueType() ==
6362 TLI.getPointerTy(DAG.getDataLayout()) &&
6363 "Memory operands expect pointer values");
6365 unsigned ConstraintID =
6366 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6367 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6368 "Failed to convert memory constraint code to constraint id.");
6370 // Add information to the INLINEASM node to know about this input.
6371 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6372 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6373 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6376 AsmNodeOperands.push_back(InOperandVal);
6380 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6381 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6382 "Unknown constraint type!");
6384 // TODO: Support this.
6385 if (OpInfo.isIndirect) {
6386 LLVMContext &Ctx = *DAG.getContext();
6387 Ctx.emitError(CS.getInstruction(),
6388 "Don't know how to handle indirect register inputs yet "
6389 "for constraint '" +
6390 Twine(OpInfo.ConstraintCode) + "'");
6394 // Copy the input into the appropriate registers.
6395 if (OpInfo.AssignedRegs.Regs.empty()) {
6396 LLVMContext &Ctx = *DAG.getContext();
6397 Ctx.emitError(CS.getInstruction(),
6398 "couldn't allocate input reg for constraint '" +
6399 Twine(OpInfo.ConstraintCode) + "'");
6403 SDLoc dl = getCurSDLoc();
6405 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6406 Chain, &Flag, CS.getInstruction());
6408 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6409 dl, DAG, AsmNodeOperands);
6412 case InlineAsm::isClobber: {
6413 // Add the clobbered value to the operand list, so that the register
6414 // allocator is aware that the physreg got clobbered.
6415 if (!OpInfo.AssignedRegs.Regs.empty())
6416 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6417 false, 0, getCurSDLoc(), DAG,
6424 // Finish up input operands. Set the input chain and add the flag last.
6425 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6426 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6428 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6429 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6430 Flag = Chain.getValue(1);
6432 // If this asm returns a register value, copy the result from that register
6433 // and set it as the value of the call.
6434 if (!RetValRegs.Regs.empty()) {
6435 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6436 Chain, &Flag, CS.getInstruction());
6438 // FIXME: Why don't we do this for inline asms with MRVs?
6439 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6440 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6442 // If any of the results of the inline asm is a vector, it may have the
6443 // wrong width/num elts. This can happen for register classes that can
6444 // contain multiple different value types. The preg or vreg allocated may
6445 // not have the same VT as was expected. Convert it to the right type
6446 // with bit_convert.
6447 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6448 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6451 } else if (ResultType != Val.getValueType() &&
6452 ResultType.isInteger() && Val.getValueType().isInteger()) {
6453 // If a result value was tied to an input value, the computed result may
6454 // have a wider width than the expected result. Extract the relevant
6456 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6459 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6462 setValue(CS.getInstruction(), Val);
6463 // Don't need to use this as a chain in this case.
6464 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6468 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6470 // Process indirect outputs, first output all of the flagged copies out of
6472 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6473 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6474 const Value *Ptr = IndirectStoresToEmit[i].second;
6475 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6477 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6480 // Emit the non-flagged stores from the physregs.
6481 SmallVector<SDValue, 8> OutChains;
6482 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6483 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6484 StoresToEmit[i].first,
6485 getValue(StoresToEmit[i].second),
6486 MachinePointerInfo(StoresToEmit[i].second),
6488 OutChains.push_back(Val);
6491 if (!OutChains.empty())
6492 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6497 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6498 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6499 MVT::Other, getRoot(),
6500 getValue(I.getArgOperand(0)),
6501 DAG.getSrcValue(I.getArgOperand(0))));
6504 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6506 const DataLayout &DL = DAG.getDataLayout();
6507 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6508 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6509 DAG.getSrcValue(I.getOperand(0)),
6510 DL.getABITypeAlignment(I.getType()));
6512 DAG.setRoot(V.getValue(1));
6515 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6516 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6517 MVT::Other, getRoot(),
6518 getValue(I.getArgOperand(0)),
6519 DAG.getSrcValue(I.getArgOperand(0))));
6522 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6523 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6524 MVT::Other, getRoot(),
6525 getValue(I.getArgOperand(0)),
6526 getValue(I.getArgOperand(1)),
6527 DAG.getSrcValue(I.getArgOperand(0)),
6528 DAG.getSrcValue(I.getArgOperand(1))));
6531 /// \brief Lower an argument list according to the target calling convention.
6533 /// \return A tuple of <return-value, token-chain>
6535 /// This is a helper for lowering intrinsics that follow a target calling
6536 /// convention or require stack pointer adjustment. Only a subset of the
6537 /// intrinsic's operands need to participate in the calling convention.
6538 std::pair<SDValue, SDValue>
6539 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6540 unsigned NumArgs, SDValue Callee,
6542 MachineBasicBlock *LandingPad,
6543 bool IsPatchPoint) {
6544 TargetLowering::ArgListTy Args;
6545 Args.reserve(NumArgs);
6547 // Populate the argument list.
6548 // Attributes for args start at offset 1, after the return attribute.
6549 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6550 ArgI != ArgE; ++ArgI) {
6551 const Value *V = CS->getOperand(ArgI);
6553 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6555 TargetLowering::ArgListEntry Entry;
6556 Entry.Node = getValue(V);
6557 Entry.Ty = V->getType();
6558 Entry.setAttributes(&CS, AttrI);
6559 Args.push_back(Entry);
6562 TargetLowering::CallLoweringInfo CLI(DAG);
6563 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6564 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6565 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6567 return lowerInvokable(CLI, LandingPad);
6570 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6571 /// or patchpoint target node's operand list.
6573 /// Constants are converted to TargetConstants purely as an optimization to
6574 /// avoid constant materialization and register allocation.
6576 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6577 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6578 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6579 /// address materialization and register allocation, but may also be required
6580 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6581 /// alloca in the entry block, then the runtime may assume that the alloca's
6582 /// StackMap location can be read immediately after compilation and that the
6583 /// location is valid at any point during execution (this is similar to the
6584 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6585 /// only available in a register, then the runtime would need to trap when
6586 /// execution reaches the StackMap in order to read the alloca's location.
6587 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6588 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6589 SelectionDAGBuilder &Builder) {
6590 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6591 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6592 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6594 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6596 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6597 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6598 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6599 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6600 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6602 Ops.push_back(OpVal);
6606 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6607 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6608 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6609 // [live variables...])
6611 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6613 SDValue Chain, InFlag, Callee, NullPtr;
6614 SmallVector<SDValue, 32> Ops;
6616 SDLoc DL = getCurSDLoc();
6617 Callee = getValue(CI.getCalledValue());
6618 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6620 // The stackmap intrinsic only records the live variables (the arguemnts
6621 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6622 // intrinsic, this won't be lowered to a function call. This means we don't
6623 // have to worry about calling conventions and target specific lowering code.
6624 // Instead we perform the call lowering right here.
6626 // chain, flag = CALLSEQ_START(chain, 0)
6627 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6628 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6630 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6631 InFlag = Chain.getValue(1);
6633 // Add the <id> and <numBytes> constants.
6634 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6635 Ops.push_back(DAG.getTargetConstant(
6636 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6637 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6638 Ops.push_back(DAG.getTargetConstant(
6639 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6642 // Push live variables for the stack map.
6643 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6645 // We are not pushing any register mask info here on the operands list,
6646 // because the stackmap doesn't clobber anything.
6648 // Push the chain and the glue flag.
6649 Ops.push_back(Chain);
6650 Ops.push_back(InFlag);
6652 // Create the STACKMAP node.
6653 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6654 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6655 Chain = SDValue(SM, 0);
6656 InFlag = Chain.getValue(1);
6658 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6660 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6662 // Set the root to the target-lowered call chain.
6665 // Inform the Frame Information that we have a stackmap in this function.
6666 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6669 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6670 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6671 MachineBasicBlock *LandingPad) {
6672 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6677 // [live variables...])
6679 CallingConv::ID CC = CS.getCallingConv();
6680 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6681 bool HasDef = !CS->getType()->isVoidTy();
6682 SDLoc dl = getCurSDLoc();
6683 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6685 // Handle immediate and symbolic callees.
6686 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6687 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6689 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6690 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6691 SDLoc(SymbolicCallee),
6692 SymbolicCallee->getValueType(0));
6694 // Get the real number of arguments participating in the call <numArgs>
6695 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6696 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6698 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6699 // Intrinsics include all meta-operands up to but not including CC.
6700 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6701 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6702 "Not enough arguments provided to the patchpoint intrinsic");
6704 // For AnyRegCC the arguments are lowered later on manually.
6705 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6707 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6708 std::pair<SDValue, SDValue> Result =
6709 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6712 SDNode *CallEnd = Result.second.getNode();
6713 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6714 CallEnd = CallEnd->getOperand(0).getNode();
6716 /// Get a call instruction from the call sequence chain.
6717 /// Tail calls are not allowed.
6718 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6719 "Expected a callseq node.");
6720 SDNode *Call = CallEnd->getOperand(0).getNode();
6721 bool HasGlue = Call->getGluedNode();
6723 // Replace the target specific call node with the patchable intrinsic.
6724 SmallVector<SDValue, 8> Ops;
6726 // Add the <id> and <numBytes> constants.
6727 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6728 Ops.push_back(DAG.getTargetConstant(
6729 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6730 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6731 Ops.push_back(DAG.getTargetConstant(
6732 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6736 Ops.push_back(Callee);
6738 // Adjust <numArgs> to account for any arguments that have been passed on the
6740 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6741 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6742 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6743 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6745 // Add the calling convention
6746 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6748 // Add the arguments we omitted previously. The register allocator should
6749 // place these in any free register.
6751 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6752 Ops.push_back(getValue(CS.getArgument(i)));
6754 // Push the arguments from the call instruction up to the register mask.
6755 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6756 Ops.append(Call->op_begin() + 2, e);
6758 // Push live variables for the stack map.
6759 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6761 // Push the register mask info.
6763 Ops.push_back(*(Call->op_end()-2));
6765 Ops.push_back(*(Call->op_end()-1));
6767 // Push the chain (this is originally the first operand of the call, but
6768 // becomes now the last or second to last operand).
6769 Ops.push_back(*(Call->op_begin()));
6771 // Push the glue flag (last operand).
6773 Ops.push_back(*(Call->op_end()-1));
6776 if (IsAnyRegCC && HasDef) {
6777 // Create the return types based on the intrinsic definition
6778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6779 SmallVector<EVT, 3> ValueVTs;
6780 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6781 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6783 // There is always a chain and a glue type at the end
6784 ValueVTs.push_back(MVT::Other);
6785 ValueVTs.push_back(MVT::Glue);
6786 NodeTys = DAG.getVTList(ValueVTs);
6788 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6790 // Replace the target specific call node with a PATCHPOINT node.
6791 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6794 // Update the NodeMap.
6797 setValue(CS.getInstruction(), SDValue(MN, 0));
6799 setValue(CS.getInstruction(), Result.first);
6802 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6803 // call sequence. Furthermore the location of the chain and glue can change
6804 // when the AnyReg calling convention is used and the intrinsic returns a
6806 if (IsAnyRegCC && HasDef) {
6807 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6808 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6809 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6811 DAG.ReplaceAllUsesWith(Call, MN);
6812 DAG.DeleteNode(Call);
6814 // Inform the Frame Information that we have a patchpoint in this function.
6815 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6818 /// Returns an AttributeSet representing the attributes applied to the return
6819 /// value of the given call.
6820 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6821 SmallVector<Attribute::AttrKind, 2> Attrs;
6823 Attrs.push_back(Attribute::SExt);
6825 Attrs.push_back(Attribute::ZExt);
6827 Attrs.push_back(Attribute::InReg);
6829 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6833 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6834 /// implementation, which just calls LowerCall.
6835 /// FIXME: When all targets are
6836 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6837 std::pair<SDValue, SDValue>
6838 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6839 // Handle the incoming return values from the call.
6841 Type *OrigRetTy = CLI.RetTy;
6842 SmallVector<EVT, 4> RetTys;
6843 SmallVector<uint64_t, 4> Offsets;
6844 auto &DL = CLI.DAG.getDataLayout();
6845 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6847 SmallVector<ISD::OutputArg, 4> Outs;
6848 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6850 bool CanLowerReturn =
6851 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6852 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6854 SDValue DemoteStackSlot;
6855 int DemoteStackIdx = -100;
6856 if (!CanLowerReturn) {
6857 // FIXME: equivalent assert?
6858 // assert(!CS.hasInAllocaArgument() &&
6859 // "sret demotion is incompatible with inalloca");
6860 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6861 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6862 MachineFunction &MF = CLI.DAG.getMachineFunction();
6863 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6864 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6866 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6868 Entry.Node = DemoteStackSlot;
6869 Entry.Ty = StackSlotPtrType;
6870 Entry.isSExt = false;
6871 Entry.isZExt = false;
6872 Entry.isInReg = false;
6873 Entry.isSRet = true;
6874 Entry.isNest = false;
6875 Entry.isByVal = false;
6876 Entry.isReturned = false;
6877 Entry.Alignment = Align;
6878 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6879 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6881 // sret demotion isn't compatible with tail-calls, since the sret argument
6882 // points into the callers stack frame.
6883 CLI.IsTailCall = false;
6885 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6887 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6888 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6889 for (unsigned i = 0; i != NumRegs; ++i) {
6890 ISD::InputArg MyFlags;
6891 MyFlags.VT = RegisterVT;
6893 MyFlags.Used = CLI.IsReturnValueUsed;
6895 MyFlags.Flags.setSExt();
6897 MyFlags.Flags.setZExt();
6899 MyFlags.Flags.setInReg();
6900 CLI.Ins.push_back(MyFlags);
6905 // Handle all of the outgoing arguments.
6907 CLI.OutVals.clear();
6908 ArgListTy &Args = CLI.getArgs();
6909 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6910 SmallVector<EVT, 4> ValueVTs;
6911 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6912 Type *FinalType = Args[i].Ty;
6913 if (Args[i].isByVal)
6914 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6915 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6916 FinalType, CLI.CallConv, CLI.IsVarArg);
6917 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6919 EVT VT = ValueVTs[Value];
6920 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6921 SDValue Op = SDValue(Args[i].Node.getNode(),
6922 Args[i].Node.getResNo() + Value);
6923 ISD::ArgFlagsTy Flags;
6924 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6930 if (Args[i].isInReg)
6934 if (Args[i].isByVal)
6936 if (Args[i].isInAlloca) {
6937 Flags.setInAlloca();
6938 // Set the byval flag for CCAssignFn callbacks that don't know about
6939 // inalloca. This way we can know how many bytes we should've allocated
6940 // and how many bytes a callee cleanup function will pop. If we port
6941 // inalloca to more targets, we'll have to add custom inalloca handling
6942 // in the various CC lowering callbacks.
6945 if (Args[i].isByVal || Args[i].isInAlloca) {
6946 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6947 Type *ElementTy = Ty->getElementType();
6948 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6949 // For ByVal, alignment should come from FE. BE will guess if this
6950 // info is not there but there are cases it cannot get right.
6951 unsigned FrameAlign;
6952 if (Args[i].Alignment)
6953 FrameAlign = Args[i].Alignment;
6955 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6956 Flags.setByValAlign(FrameAlign);
6961 Flags.setInConsecutiveRegs();
6962 Flags.setOrigAlign(OriginalAlignment);
6964 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6965 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6966 SmallVector<SDValue, 4> Parts(NumParts);
6967 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6970 ExtendKind = ISD::SIGN_EXTEND;
6971 else if (Args[i].isZExt)
6972 ExtendKind = ISD::ZERO_EXTEND;
6974 // Conservatively only handle 'returned' on non-vectors for now
6975 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6976 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6977 "unexpected use of 'returned'");
6978 // Before passing 'returned' to the target lowering code, ensure that
6979 // either the register MVT and the actual EVT are the same size or that
6980 // the return value and argument are extended in the same way; in these
6981 // cases it's safe to pass the argument register value unchanged as the
6982 // return register value (although it's at the target's option whether
6984 // TODO: allow code generation to take advantage of partially preserved
6985 // registers rather than clobbering the entire register when the
6986 // parameter extension method is not compatible with the return
6988 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6989 (ExtendKind != ISD::ANY_EXTEND &&
6990 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6991 Flags.setReturned();
6994 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6995 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6997 for (unsigned j = 0; j != NumParts; ++j) {
6998 // if it isn't first piece, alignment must be 1
6999 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7000 i < CLI.NumFixedArgs,
7001 i, j*Parts[j].getValueType().getStoreSize());
7002 if (NumParts > 1 && j == 0)
7003 MyFlags.Flags.setSplit();
7005 MyFlags.Flags.setOrigAlign(1);
7007 CLI.Outs.push_back(MyFlags);
7008 CLI.OutVals.push_back(Parts[j]);
7011 if (NeedsRegBlock && Value == NumValues - 1)
7012 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7016 SmallVector<SDValue, 4> InVals;
7017 CLI.Chain = LowerCall(CLI, InVals);
7019 // Verify that the target's LowerCall behaved as expected.
7020 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7021 "LowerCall didn't return a valid chain!");
7022 assert((!CLI.IsTailCall || InVals.empty()) &&
7023 "LowerCall emitted a return value for a tail call!");
7024 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7025 "LowerCall didn't emit the correct number of values!");
7027 // For a tail call, the return value is merely live-out and there aren't
7028 // any nodes in the DAG representing it. Return a special value to
7029 // indicate that a tail call has been emitted and no more Instructions
7030 // should be processed in the current block.
7031 if (CLI.IsTailCall) {
7032 CLI.DAG.setRoot(CLI.Chain);
7033 return std::make_pair(SDValue(), SDValue());
7036 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7037 assert(InVals[i].getNode() &&
7038 "LowerCall emitted a null value!");
7039 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7040 "LowerCall emitted a value with the wrong type!");
7043 SmallVector<SDValue, 4> ReturnValues;
7044 if (!CanLowerReturn) {
7045 // The instruction result is the result of loading from the
7046 // hidden sret parameter.
7047 SmallVector<EVT, 1> PVTs;
7048 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7050 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7051 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7052 EVT PtrVT = PVTs[0];
7054 unsigned NumValues = RetTys.size();
7055 ReturnValues.resize(NumValues);
7056 SmallVector<SDValue, 4> Chains(NumValues);
7058 for (unsigned i = 0; i < NumValues; ++i) {
7059 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7060 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7062 SDValue L = CLI.DAG.getLoad(
7063 RetTys[i], CLI.DL, CLI.Chain, Add,
7064 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7065 DemoteStackIdx, Offsets[i]),
7066 false, false, false, 1);
7067 ReturnValues[i] = L;
7068 Chains[i] = L.getValue(1);
7071 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7073 // Collect the legal value parts into potentially illegal values
7074 // that correspond to the original function's return values.
7075 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7077 AssertOp = ISD::AssertSext;
7078 else if (CLI.RetZExt)
7079 AssertOp = ISD::AssertZext;
7080 unsigned CurReg = 0;
7081 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7083 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7084 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7086 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7087 NumRegs, RegisterVT, VT, nullptr,
7092 // For a function returning void, there is no return value. We can't create
7093 // such a node, so we just return a null return value in that case. In
7094 // that case, nothing will actually look at the value.
7095 if (ReturnValues.empty())
7096 return std::make_pair(SDValue(), CLI.Chain);
7099 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7100 CLI.DAG.getVTList(RetTys), ReturnValues);
7101 return std::make_pair(Res, CLI.Chain);
7104 void TargetLowering::LowerOperationWrapper(SDNode *N,
7105 SmallVectorImpl<SDValue> &Results,
7106 SelectionDAG &DAG) const {
7107 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7109 Results.push_back(Res);
7112 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7113 llvm_unreachable("LowerOperation not implemented for this target!");
7117 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7118 SDValue Op = getNonRegisterValue(V);
7119 assert((Op.getOpcode() != ISD::CopyFromReg ||
7120 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7121 "Copy from a reg to the same reg!");
7122 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7124 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7125 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7127 SDValue Chain = DAG.getEntryNode();
7129 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7130 FuncInfo.PreferredExtendType.end())
7132 : FuncInfo.PreferredExtendType[V];
7133 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7134 PendingExports.push_back(Chain);
7137 #include "llvm/CodeGen/SelectionDAGISel.h"
7139 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7140 /// entry block, return true. This includes arguments used by switches, since
7141 /// the switch may expand into multiple basic blocks.
7142 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7143 // With FastISel active, we may be splitting blocks, so force creation
7144 // of virtual registers for all non-dead arguments.
7146 return A->use_empty();
7148 const BasicBlock *Entry = A->getParent()->begin();
7149 for (const User *U : A->users())
7150 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7151 return false; // Use not in entry block.
7156 void SelectionDAGISel::LowerArguments(const Function &F) {
7157 SelectionDAG &DAG = SDB->DAG;
7158 SDLoc dl = SDB->getCurSDLoc();
7159 const DataLayout &DL = DAG.getDataLayout();
7160 SmallVector<ISD::InputArg, 16> Ins;
7162 if (!FuncInfo->CanLowerReturn) {
7163 // Put in an sret pointer parameter before all the other parameters.
7164 SmallVector<EVT, 1> ValueVTs;
7165 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7166 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7168 // NOTE: Assuming that a pointer will never break down to more than one VT
7170 ISD::ArgFlagsTy Flags;
7172 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7173 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7174 ISD::InputArg::NoArgIndex, 0);
7175 Ins.push_back(RetArg);
7178 // Set up the incoming argument description vector.
7180 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7181 I != E; ++I, ++Idx) {
7182 SmallVector<EVT, 4> ValueVTs;
7183 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7184 bool isArgValueUsed = !I->use_empty();
7185 unsigned PartBase = 0;
7186 Type *FinalType = I->getType();
7187 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7188 FinalType = cast<PointerType>(FinalType)->getElementType();
7189 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7190 FinalType, F.getCallingConv(), F.isVarArg());
7191 for (unsigned Value = 0, NumValues = ValueVTs.size();
7192 Value != NumValues; ++Value) {
7193 EVT VT = ValueVTs[Value];
7194 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7195 ISD::ArgFlagsTy Flags;
7196 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7198 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7200 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7202 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7204 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7206 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7208 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7209 Flags.setInAlloca();
7210 // Set the byval flag for CCAssignFn callbacks that don't know about
7211 // inalloca. This way we can know how many bytes we should've allocated
7212 // and how many bytes a callee cleanup function will pop. If we port
7213 // inalloca to more targets, we'll have to add custom inalloca handling
7214 // in the various CC lowering callbacks.
7217 if (Flags.isByVal() || Flags.isInAlloca()) {
7218 PointerType *Ty = cast<PointerType>(I->getType());
7219 Type *ElementTy = Ty->getElementType();
7220 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7221 // For ByVal, alignment should be passed from FE. BE will guess if
7222 // this info is not there but there are cases it cannot get right.
7223 unsigned FrameAlign;
7224 if (F.getParamAlignment(Idx))
7225 FrameAlign = F.getParamAlignment(Idx);
7227 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7228 Flags.setByValAlign(FrameAlign);
7230 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7233 Flags.setInConsecutiveRegs();
7234 Flags.setOrigAlign(OriginalAlignment);
7236 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7237 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7238 for (unsigned i = 0; i != NumRegs; ++i) {
7239 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7240 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7241 if (NumRegs > 1 && i == 0)
7242 MyFlags.Flags.setSplit();
7243 // if it isn't first piece, alignment must be 1
7245 MyFlags.Flags.setOrigAlign(1);
7246 Ins.push_back(MyFlags);
7248 if (NeedsRegBlock && Value == NumValues - 1)
7249 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7250 PartBase += VT.getStoreSize();
7254 // Call the target to set up the argument values.
7255 SmallVector<SDValue, 8> InVals;
7256 SDValue NewRoot = TLI->LowerFormalArguments(
7257 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7259 // Verify that the target's LowerFormalArguments behaved as expected.
7260 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7261 "LowerFormalArguments didn't return a valid chain!");
7262 assert(InVals.size() == Ins.size() &&
7263 "LowerFormalArguments didn't emit the correct number of values!");
7265 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7266 assert(InVals[i].getNode() &&
7267 "LowerFormalArguments emitted a null value!");
7268 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7269 "LowerFormalArguments emitted a value with the wrong type!");
7273 // Update the DAG with the new chain value resulting from argument lowering.
7274 DAG.setRoot(NewRoot);
7276 // Set up the argument values.
7279 if (!FuncInfo->CanLowerReturn) {
7280 // Create a virtual register for the sret pointer, and put in a copy
7281 // from the sret argument into it.
7282 SmallVector<EVT, 1> ValueVTs;
7283 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7284 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7285 MVT VT = ValueVTs[0].getSimpleVT();
7286 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7287 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7288 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7289 RegVT, VT, nullptr, AssertOp);
7291 MachineFunction& MF = SDB->DAG.getMachineFunction();
7292 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7293 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7294 FuncInfo->DemoteRegister = SRetReg;
7296 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7297 DAG.setRoot(NewRoot);
7299 // i indexes lowered arguments. Bump it past the hidden sret argument.
7300 // Idx indexes LLVM arguments. Don't touch it.
7304 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7306 SmallVector<SDValue, 4> ArgValues;
7307 SmallVector<EVT, 4> ValueVTs;
7308 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7309 unsigned NumValues = ValueVTs.size();
7311 // If this argument is unused then remember its value. It is used to generate
7312 // debugging information.
7313 if (I->use_empty() && NumValues) {
7314 SDB->setUnusedArgValue(I, InVals[i]);
7316 // Also remember any frame index for use in FastISel.
7317 if (FrameIndexSDNode *FI =
7318 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7319 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7322 for (unsigned Val = 0; Val != NumValues; ++Val) {
7323 EVT VT = ValueVTs[Val];
7324 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7325 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7327 if (!I->use_empty()) {
7328 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7329 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7330 AssertOp = ISD::AssertSext;
7331 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7332 AssertOp = ISD::AssertZext;
7334 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7335 NumParts, PartVT, VT,
7336 nullptr, AssertOp));
7342 // We don't need to do anything else for unused arguments.
7343 if (ArgValues.empty())
7346 // Note down frame index.
7347 if (FrameIndexSDNode *FI =
7348 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7349 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7351 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7352 SDB->getCurSDLoc());
7354 SDB->setValue(I, Res);
7355 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7356 if (LoadSDNode *LNode =
7357 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7358 if (FrameIndexSDNode *FI =
7359 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7360 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7363 // If this argument is live outside of the entry block, insert a copy from
7364 // wherever we got it to the vreg that other BB's will reference it as.
7365 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7366 // If we can, though, try to skip creating an unnecessary vreg.
7367 // FIXME: This isn't very clean... it would be nice to make this more
7368 // general. It's also subtly incompatible with the hacks FastISel
7370 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7371 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7372 FuncInfo->ValueMap[I] = Reg;
7376 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7377 FuncInfo->InitializeRegForValue(I);
7378 SDB->CopyToExportRegsIfNeeded(I);
7382 assert(i == InVals.size() && "Argument register count mismatch!");
7384 // Finally, if the target has anything special to do, allow it to do so.
7385 EmitFunctionEntryCode();
7388 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7389 /// ensure constants are generated when needed. Remember the virtual registers
7390 /// that need to be added to the Machine PHI nodes as input. We cannot just
7391 /// directly add them, because expansion might result in multiple MBB's for one
7392 /// BB. As such, the start of the BB might correspond to a different MBB than
7396 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7397 const TerminatorInst *TI = LLVMBB->getTerminator();
7399 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7401 // Check PHI nodes in successors that expect a value to be available from this
7403 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7404 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7405 if (!isa<PHINode>(SuccBB->begin())) continue;
7406 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7408 // If this terminator has multiple identical successors (common for
7409 // switches), only handle each succ once.
7410 if (!SuccsHandled.insert(SuccMBB).second)
7413 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7415 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7416 // nodes and Machine PHI nodes, but the incoming operands have not been
7418 for (BasicBlock::const_iterator I = SuccBB->begin();
7419 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7420 // Ignore dead phi's.
7421 if (PN->use_empty()) continue;
7424 if (PN->getType()->isEmptyTy())
7428 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7430 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7431 unsigned &RegOut = ConstantsOut[C];
7433 RegOut = FuncInfo.CreateRegs(C->getType());
7434 CopyValueToVirtualRegister(C, RegOut);
7438 DenseMap<const Value *, unsigned>::iterator I =
7439 FuncInfo.ValueMap.find(PHIOp);
7440 if (I != FuncInfo.ValueMap.end())
7443 assert(isa<AllocaInst>(PHIOp) &&
7444 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7445 "Didn't codegen value into a register!??");
7446 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7447 CopyValueToVirtualRegister(PHIOp, Reg);
7451 // Remember that this register needs to added to the machine PHI node as
7452 // the input for this MBB.
7453 SmallVector<EVT, 4> ValueVTs;
7454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7455 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7456 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7457 EVT VT = ValueVTs[vti];
7458 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7459 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7460 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7461 Reg += NumRegisters;
7466 ConstantsOut.clear();
7469 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7472 SelectionDAGBuilder::StackProtectorDescriptor::
7473 AddSuccessorMBB(const BasicBlock *BB,
7474 MachineBasicBlock *ParentMBB,
7476 MachineBasicBlock *SuccMBB) {
7477 // If SuccBB has not been created yet, create it.
7479 MachineFunction *MF = ParentMBB->getParent();
7480 MachineFunction::iterator BBI = ParentMBB;
7481 SuccMBB = MF->CreateMachineBasicBlock(BB);
7482 MF->insert(++BBI, SuccMBB);
7484 // Add it as a successor of ParentMBB.
7485 ParentMBB->addSuccessor(
7486 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7490 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7491 MachineFunction::iterator I = MBB;
7492 if (++I == FuncInfo.MF->end())
7497 /// During lowering new call nodes can be created (such as memset, etc.).
7498 /// Those will become new roots of the current DAG, but complications arise
7499 /// when they are tail calls. In such cases, the call lowering will update
7500 /// the root, but the builder still needs to know that a tail call has been
7501 /// lowered in order to avoid generating an additional return.
7502 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7503 // If the node is null, we do have a tail call.
7504 if (MaybeTC.getNode() != nullptr)
7505 DAG.setRoot(MaybeTC);
7510 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7511 unsigned *TotalCases, unsigned First,
7513 assert(Last >= First);
7514 assert(TotalCases[Last] >= TotalCases[First]);
7516 APInt LowCase = Clusters[First].Low->getValue();
7517 APInt HighCase = Clusters[Last].High->getValue();
7518 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7520 // FIXME: A range of consecutive cases has 100% density, but only requires one
7521 // comparison to lower. We should discriminate against such consecutive ranges
7524 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7525 uint64_t Range = Diff + 1;
7528 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7530 assert(NumCases < UINT64_MAX / 100);
7531 assert(Range >= NumCases);
7533 return NumCases * 100 >= Range * MinJumpTableDensity;
7536 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7537 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7538 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7541 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7542 unsigned First, unsigned Last,
7543 const SwitchInst *SI,
7544 MachineBasicBlock *DefaultMBB,
7545 CaseCluster &JTCluster) {
7546 assert(First <= Last);
7548 uint32_t Weight = 0;
7549 unsigned NumCmps = 0;
7550 std::vector<MachineBasicBlock*> Table;
7551 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7552 for (unsigned I = First; I <= Last; ++I) {
7553 assert(Clusters[I].Kind == CC_Range);
7554 Weight += Clusters[I].Weight;
7555 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7556 APInt Low = Clusters[I].Low->getValue();
7557 APInt High = Clusters[I].High->getValue();
7558 NumCmps += (Low == High) ? 1 : 2;
7560 // Fill the gap between this and the previous cluster.
7561 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7562 assert(PreviousHigh.slt(Low));
7563 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7564 for (uint64_t J = 0; J < Gap; J++)
7565 Table.push_back(DefaultMBB);
7567 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7568 for (uint64_t J = 0; J < ClusterSize; ++J)
7569 Table.push_back(Clusters[I].MBB);
7570 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7573 unsigned NumDests = JTWeights.size();
7574 if (isSuitableForBitTests(NumDests, NumCmps,
7575 Clusters[First].Low->getValue(),
7576 Clusters[Last].High->getValue())) {
7577 // Clusters[First..Last] should be lowered as bit tests instead.
7581 // Create the MBB that will load from and jump through the table.
7582 // Note: We create it here, but it's not inserted into the function yet.
7583 MachineFunction *CurMF = FuncInfo.MF;
7584 MachineBasicBlock *JumpTableMBB =
7585 CurMF->CreateMachineBasicBlock(SI->getParent());
7587 // Add successors. Note: use table order for determinism.
7588 SmallPtrSet<MachineBasicBlock *, 8> Done;
7589 for (MachineBasicBlock *Succ : Table) {
7590 if (Done.count(Succ))
7592 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7596 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7597 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7598 ->createJumpTableIndex(Table);
7600 // Set up the jump table info.
7601 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7602 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7603 Clusters[Last].High->getValue(), SI->getCondition(),
7605 JTCases.emplace_back(std::move(JTH), std::move(JT));
7607 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7608 JTCases.size() - 1, Weight);
7612 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7613 const SwitchInst *SI,
7614 MachineBasicBlock *DefaultMBB) {
7616 // Clusters must be non-empty, sorted, and only contain Range clusters.
7617 assert(!Clusters.empty());
7618 for (CaseCluster &C : Clusters)
7619 assert(C.Kind == CC_Range);
7620 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7621 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7624 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7625 if (!areJTsAllowed(TLI))
7628 const int64_t N = Clusters.size();
7629 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7631 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7632 SmallVector<unsigned, 8> TotalCases(N);
7634 for (unsigned i = 0; i < N; ++i) {
7635 APInt Hi = Clusters[i].High->getValue();
7636 APInt Lo = Clusters[i].Low->getValue();
7637 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7639 TotalCases[i] += TotalCases[i - 1];
7642 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7643 // Cheap case: the whole range might be suitable for jump table.
7644 CaseCluster JTCluster;
7645 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7646 Clusters[0] = JTCluster;
7652 // The algorithm below is not suitable for -O0.
7653 if (TM.getOptLevel() == CodeGenOpt::None)
7656 // Split Clusters into minimum number of dense partitions. The algorithm uses
7657 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7658 // for the Case Statement'" (1994), but builds the MinPartitions array in
7659 // reverse order to make it easier to reconstruct the partitions in ascending
7660 // order. In the choice between two optimal partitionings, it picks the one
7661 // which yields more jump tables.
7663 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7664 SmallVector<unsigned, 8> MinPartitions(N);
7665 // LastElement[i] is the last element of the partition starting at i.
7666 SmallVector<unsigned, 8> LastElement(N);
7667 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7668 SmallVector<unsigned, 8> NumTables(N);
7670 // Base case: There is only one way to partition Clusters[N-1].
7671 MinPartitions[N - 1] = 1;
7672 LastElement[N - 1] = N - 1;
7673 assert(MinJumpTableSize > 1);
7674 NumTables[N - 1] = 0;
7676 // Note: loop indexes are signed to avoid underflow.
7677 for (int64_t i = N - 2; i >= 0; i--) {
7678 // Find optimal partitioning of Clusters[i..N-1].
7679 // Baseline: Put Clusters[i] into a partition on its own.
7680 MinPartitions[i] = MinPartitions[i + 1] + 1;
7682 NumTables[i] = NumTables[i + 1];
7684 // Search for a solution that results in fewer partitions.
7685 for (int64_t j = N - 1; j > i; j--) {
7686 // Try building a partition from Clusters[i..j].
7687 if (isDense(Clusters, &TotalCases[0], i, j)) {
7688 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7689 bool IsTable = j - i + 1 >= MinJumpTableSize;
7690 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7692 // If this j leads to fewer partitions, or same number of partitions
7693 // with more lookup tables, it is a better partitioning.
7694 if (NumPartitions < MinPartitions[i] ||
7695 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7696 MinPartitions[i] = NumPartitions;
7698 NumTables[i] = Tables;
7704 // Iterate over the partitions, replacing some with jump tables in-place.
7705 unsigned DstIndex = 0;
7706 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7707 Last = LastElement[First];
7708 assert(Last >= First);
7709 assert(DstIndex <= First);
7710 unsigned NumClusters = Last - First + 1;
7712 CaseCluster JTCluster;
7713 if (NumClusters >= MinJumpTableSize &&
7714 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7715 Clusters[DstIndex++] = JTCluster;
7717 for (unsigned I = First; I <= Last; ++I)
7718 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7721 Clusters.resize(DstIndex);
7724 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7725 // FIXME: Using the pointer type doesn't seem ideal.
7726 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7727 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7731 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7734 const APInt &High) {
7735 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7736 // range of cases both require only one branch to lower. Just looking at the
7737 // number of clusters and destinations should be enough to decide whether to
7740 // To lower a range with bit tests, the range must fit the bitwidth of a
7742 if (!rangeFitsInWord(Low, High))
7745 // Decide whether it's profitable to lower this range with bit tests. Each
7746 // destination requires a bit test and branch, and there is an overall range
7747 // check branch. For a small number of clusters, separate comparisons might be
7748 // cheaper, and for many destinations, splitting the range might be better.
7749 return (NumDests == 1 && NumCmps >= 3) ||
7750 (NumDests == 2 && NumCmps >= 5) ||
7751 (NumDests == 3 && NumCmps >= 6);
7754 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7755 unsigned First, unsigned Last,
7756 const SwitchInst *SI,
7757 CaseCluster &BTCluster) {
7758 assert(First <= Last);
7762 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7763 unsigned NumCmps = 0;
7764 for (int64_t I = First; I <= Last; ++I) {
7765 assert(Clusters[I].Kind == CC_Range);
7766 Dests.set(Clusters[I].MBB->getNumber());
7767 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7769 unsigned NumDests = Dests.count();
7771 APInt Low = Clusters[First].Low->getValue();
7772 APInt High = Clusters[Last].High->getValue();
7773 assert(Low.slt(High));
7775 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7781 const int BitWidth = DAG.getTargetLoweringInfo()
7782 .getPointerTy(DAG.getDataLayout())
7784 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7786 // Check if the clusters cover a contiguous range such that no value in the
7787 // range will jump to the default statement.
7788 bool ContiguousRange = true;
7789 for (int64_t I = First + 1; I <= Last; ++I) {
7790 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7791 ContiguousRange = false;
7796 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7797 // Optimize the case where all the case values fit in a word without having
7798 // to subtract minValue. In this case, we can optimize away the subtraction.
7799 LowBound = APInt::getNullValue(Low.getBitWidth());
7801 ContiguousRange = false;
7804 CmpRange = High - Low;
7808 uint32_t TotalWeight = 0;
7809 for (unsigned i = First; i <= Last; ++i) {
7810 // Find the CaseBits for this destination.
7812 for (j = 0; j < CBV.size(); ++j)
7813 if (CBV[j].BB == Clusters[i].MBB)
7815 if (j == CBV.size())
7816 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7817 CaseBits *CB = &CBV[j];
7819 // Update Mask, Bits and ExtraWeight.
7820 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7821 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7822 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7823 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7824 CB->Bits += Hi - Lo + 1;
7825 CB->ExtraWeight += Clusters[i].Weight;
7826 TotalWeight += Clusters[i].Weight;
7827 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7831 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7832 // Sort by weight first, number of bits second.
7833 if (a.ExtraWeight != b.ExtraWeight)
7834 return a.ExtraWeight > b.ExtraWeight;
7835 return a.Bits > b.Bits;
7838 for (auto &CB : CBV) {
7839 MachineBasicBlock *BitTestBB =
7840 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7841 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7843 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7844 SI->getCondition(), -1U, MVT::Other, false,
7845 ContiguousRange, nullptr, nullptr, std::move(BTI),
7848 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7849 BitTestCases.size() - 1, TotalWeight);
7853 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7854 const SwitchInst *SI) {
7855 // Partition Clusters into as few subsets as possible, where each subset has a
7856 // range that fits in a machine word and has <= 3 unique destinations.
7859 // Clusters must be sorted and contain Range or JumpTable clusters.
7860 assert(!Clusters.empty());
7861 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7862 for (const CaseCluster &C : Clusters)
7863 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7864 for (unsigned i = 1; i < Clusters.size(); ++i)
7865 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7868 // The algorithm below is not suitable for -O0.
7869 if (TM.getOptLevel() == CodeGenOpt::None)
7872 // If target does not have legal shift left, do not emit bit tests at all.
7873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7874 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7875 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7878 int BitWidth = PTy.getSizeInBits();
7879 const int64_t N = Clusters.size();
7881 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7882 SmallVector<unsigned, 8> MinPartitions(N);
7883 // LastElement[i] is the last element of the partition starting at i.
7884 SmallVector<unsigned, 8> LastElement(N);
7886 // FIXME: This might not be the best algorithm for finding bit test clusters.
7888 // Base case: There is only one way to partition Clusters[N-1].
7889 MinPartitions[N - 1] = 1;
7890 LastElement[N - 1] = N - 1;
7892 // Note: loop indexes are signed to avoid underflow.
7893 for (int64_t i = N - 2; i >= 0; --i) {
7894 // Find optimal partitioning of Clusters[i..N-1].
7895 // Baseline: Put Clusters[i] into a partition on its own.
7896 MinPartitions[i] = MinPartitions[i + 1] + 1;
7899 // Search for a solution that results in fewer partitions.
7900 // Note: the search is limited by BitWidth, reducing time complexity.
7901 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7902 // Try building a partition from Clusters[i..j].
7905 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7906 Clusters[j].High->getValue()))
7909 // Check nbr of destinations and cluster types.
7910 // FIXME: This works, but doesn't seem very efficient.
7911 bool RangesOnly = true;
7912 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7913 for (int64_t k = i; k <= j; k++) {
7914 if (Clusters[k].Kind != CC_Range) {
7918 Dests.set(Clusters[k].MBB->getNumber());
7920 if (!RangesOnly || Dests.count() > 3)
7923 // Check if it's a better partition.
7924 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7925 if (NumPartitions < MinPartitions[i]) {
7926 // Found a better partition.
7927 MinPartitions[i] = NumPartitions;
7933 // Iterate over the partitions, replacing with bit-test clusters in-place.
7934 unsigned DstIndex = 0;
7935 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7936 Last = LastElement[First];
7937 assert(First <= Last);
7938 assert(DstIndex <= First);
7940 CaseCluster BitTestCluster;
7941 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7942 Clusters[DstIndex++] = BitTestCluster;
7944 size_t NumClusters = Last - First + 1;
7945 std::memmove(&Clusters[DstIndex], &Clusters[First],
7946 sizeof(Clusters[0]) * NumClusters);
7947 DstIndex += NumClusters;
7950 Clusters.resize(DstIndex);
7953 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7954 MachineBasicBlock *SwitchMBB,
7955 MachineBasicBlock *DefaultMBB) {
7956 MachineFunction *CurMF = FuncInfo.MF;
7957 MachineBasicBlock *NextMBB = nullptr;
7958 MachineFunction::iterator BBI = W.MBB;
7959 if (++BBI != FuncInfo.MF->end())
7962 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7964 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7966 if (Size == 2 && W.MBB == SwitchMBB) {
7967 // If any two of the cases has the same destination, and if one value
7968 // is the same as the other, but has one bit unset that the other has set,
7969 // use bit manipulation to do two compares at once. For example:
7970 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7971 // TODO: This could be extended to merge any 2 cases in switches with 3
7973 // TODO: Handle cases where W.CaseBB != SwitchBB.
7974 CaseCluster &Small = *W.FirstCluster;
7975 CaseCluster &Big = *W.LastCluster;
7977 if (Small.Low == Small.High && Big.Low == Big.High &&
7978 Small.MBB == Big.MBB) {
7979 const APInt &SmallValue = Small.Low->getValue();
7980 const APInt &BigValue = Big.Low->getValue();
7982 // Check that there is only one bit different.
7983 APInt CommonBit = BigValue ^ SmallValue;
7984 if (CommonBit.isPowerOf2()) {
7985 SDValue CondLHS = getValue(Cond);
7986 EVT VT = CondLHS.getValueType();
7987 SDLoc DL = getCurSDLoc();
7989 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7990 DAG.getConstant(CommonBit, DL, VT));
7991 SDValue Cond = DAG.getSetCC(
7992 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7995 // Update successor info.
7996 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7997 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7998 addSuccessorWithWeight(
7999 SwitchMBB, DefaultMBB,
8000 // The default destination is the first successor in IR.
8001 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8004 // Insert the true branch.
8006 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8007 DAG.getBasicBlock(Small.MBB));
8008 // Insert the false branch.
8009 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8010 DAG.getBasicBlock(DefaultMBB));
8012 DAG.setRoot(BrCond);
8018 if (TM.getOptLevel() != CodeGenOpt::None) {
8019 // Order cases by weight so the most likely case will be checked first.
8020 std::sort(W.FirstCluster, W.LastCluster + 1,
8021 [](const CaseCluster &a, const CaseCluster &b) {
8022 return a.Weight > b.Weight;
8025 // Rearrange the case blocks so that the last one falls through if possible
8026 // without without changing the order of weights.
8027 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8029 if (I->Weight > W.LastCluster->Weight)
8031 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8032 std::swap(*I, *W.LastCluster);
8038 // Compute total weight.
8039 uint32_t DefaultWeight = W.DefaultWeight;
8040 uint32_t UnhandledWeights = DefaultWeight;
8041 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8042 UnhandledWeights += I->Weight;
8043 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8046 MachineBasicBlock *CurMBB = W.MBB;
8047 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8048 MachineBasicBlock *Fallthrough;
8049 if (I == W.LastCluster) {
8050 // For the last cluster, fall through to the default destination.
8051 Fallthrough = DefaultMBB;
8053 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8054 CurMF->insert(BBI, Fallthrough);
8055 // Put Cond in a virtual register to make it available from the new blocks.
8056 ExportFromCurrentBlock(Cond);
8058 UnhandledWeights -= I->Weight;
8061 case CC_JumpTable: {
8062 // FIXME: Optimize away range check based on pivot comparisons.
8063 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8064 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8066 // The jump block hasn't been inserted yet; insert it here.
8067 MachineBasicBlock *JumpMBB = JT->MBB;
8068 CurMF->insert(BBI, JumpMBB);
8070 uint32_t JumpWeight = I->Weight;
8071 uint32_t FallthroughWeight = UnhandledWeights;
8073 // If Fallthrough is a target of the jump table, we evenly distribute
8074 // the weight on the edge to Fallthrough to successors of CurMBB.
8075 // Also update the weight on the edge from JumpMBB to Fallthrough.
8076 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8077 SE = JumpMBB->succ_end();
8079 if (*SI == Fallthrough) {
8080 JumpWeight += DefaultWeight / 2;
8081 FallthroughWeight -= DefaultWeight / 2;
8082 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8087 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8088 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8090 // The jump table header will be inserted in our current block, do the
8091 // range check, and fall through to our fallthrough block.
8092 JTH->HeaderBB = CurMBB;
8093 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8095 // If we're in the right place, emit the jump table header right now.
8096 if (CurMBB == SwitchMBB) {
8097 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8098 JTH->Emitted = true;
8103 // FIXME: Optimize away range check based on pivot comparisons.
8104 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8106 // The bit test blocks haven't been inserted yet; insert them here.
8107 for (BitTestCase &BTC : BTB->Cases)
8108 CurMF->insert(BBI, BTC.ThisBB);
8110 // Fill in fields of the BitTestBlock.
8111 BTB->Parent = CurMBB;
8112 BTB->Default = Fallthrough;
8114 BTB->DefaultWeight = UnhandledWeights;
8115 // If the cases in bit test don't form a contiguous range, we evenly
8116 // distribute the weight on the edge to Fallthrough to two successors
8118 if (!BTB->ContiguousRange) {
8119 BTB->Weight += DefaultWeight / 2;
8120 BTB->DefaultWeight -= DefaultWeight / 2;
8123 // If we're in the right place, emit the bit test header right now.
8124 if (CurMBB == SwitchMBB) {
8125 visitBitTestHeader(*BTB, SwitchMBB);
8126 BTB->Emitted = true;
8131 const Value *RHS, *LHS, *MHS;
8133 if (I->Low == I->High) {
8134 // Check Cond == I->Low.
8140 // Check I->Low <= Cond <= I->High.
8147 // The false weight is the sum of all unhandled cases.
8148 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8151 if (CurMBB == SwitchMBB)
8152 visitSwitchCase(CB, SwitchMBB);
8154 SwitchCases.push_back(CB);
8159 CurMBB = Fallthrough;
8163 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8164 CaseClusterIt First,
8165 CaseClusterIt Last) {
8166 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8167 if (X.Weight != CC.Weight)
8168 return X.Weight > CC.Weight;
8170 // Ties are broken by comparing the case value.
8171 return X.Low->getValue().slt(CC.Low->getValue());
8175 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8176 const SwitchWorkListItem &W,
8178 MachineBasicBlock *SwitchMBB) {
8179 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8180 "Clusters not sorted?");
8182 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8184 // Balance the tree based on branch weights to create a near-optimal (in terms
8185 // of search time given key frequency) binary search tree. See e.g. Kurt
8186 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8187 CaseClusterIt LastLeft = W.FirstCluster;
8188 CaseClusterIt FirstRight = W.LastCluster;
8189 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8190 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8192 // Move LastLeft and FirstRight towards each other from opposite directions to
8193 // find a partitioning of the clusters which balances the weight on both
8194 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8195 // taken to ensure 0-weight nodes are distributed evenly.
8197 while (LastLeft + 1 < FirstRight) {
8198 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8199 LeftWeight += (++LastLeft)->Weight;
8201 RightWeight += (--FirstRight)->Weight;
8206 // Our binary search tree differs from a typical BST in that ours can have up
8207 // to three values in each leaf. The pivot selection above doesn't take that
8208 // into account, which means the tree might require more nodes and be less
8209 // efficient. We compensate for this here.
8211 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8212 unsigned NumRight = W.LastCluster - FirstRight + 1;
8214 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8215 // If one side has less than 3 clusters, and the other has more than 3,
8216 // consider taking a cluster from the other side.
8218 if (NumLeft < NumRight) {
8219 // Consider moving the first cluster on the right to the left side.
8220 CaseCluster &CC = *FirstRight;
8221 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8222 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8223 if (LeftSideRank <= RightSideRank) {
8224 // Moving the cluster to the left does not demote it.
8230 assert(NumRight < NumLeft);
8231 // Consider moving the last element on the left to the right side.
8232 CaseCluster &CC = *LastLeft;
8233 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8234 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8235 if (RightSideRank <= LeftSideRank) {
8236 // Moving the cluster to the right does not demot it.
8246 assert(LastLeft + 1 == FirstRight);
8247 assert(LastLeft >= W.FirstCluster);
8248 assert(FirstRight <= W.LastCluster);
8250 // Use the first element on the right as pivot since we will make less-than
8251 // comparisons against it.
8252 CaseClusterIt PivotCluster = FirstRight;
8253 assert(PivotCluster > W.FirstCluster);
8254 assert(PivotCluster <= W.LastCluster);
8256 CaseClusterIt FirstLeft = W.FirstCluster;
8257 CaseClusterIt LastRight = W.LastCluster;
8259 const ConstantInt *Pivot = PivotCluster->Low;
8261 // New blocks will be inserted immediately after the current one.
8262 MachineFunction::iterator BBI = W.MBB;
8265 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8266 // we can branch to its destination directly if it's squeezed exactly in
8267 // between the known lower bound and Pivot - 1.
8268 MachineBasicBlock *LeftMBB;
8269 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8270 FirstLeft->Low == W.GE &&
8271 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8272 LeftMBB = FirstLeft->MBB;
8274 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8275 FuncInfo.MF->insert(BBI, LeftMBB);
8277 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8278 // Put Cond in a virtual register to make it available from the new blocks.
8279 ExportFromCurrentBlock(Cond);
8282 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8283 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8284 // directly if RHS.High equals the current upper bound.
8285 MachineBasicBlock *RightMBB;
8286 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8287 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8288 RightMBB = FirstRight->MBB;
8290 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8291 FuncInfo.MF->insert(BBI, RightMBB);
8293 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8294 // Put Cond in a virtual register to make it available from the new blocks.
8295 ExportFromCurrentBlock(Cond);
8298 // Create the CaseBlock record that will be used to lower the branch.
8299 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8300 LeftWeight, RightWeight);
8302 if (W.MBB == SwitchMBB)
8303 visitSwitchCase(CB, SwitchMBB);
8305 SwitchCases.push_back(CB);
8308 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8309 // Extract cases from the switch.
8310 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8311 CaseClusterVector Clusters;
8312 Clusters.reserve(SI.getNumCases());
8313 for (auto I : SI.cases()) {
8314 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8315 const ConstantInt *CaseVal = I.getCaseValue();
8317 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8318 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8321 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8323 // Cluster adjacent cases with the same destination. We do this at all
8324 // optimization levels because it's cheap to do and will make codegen faster
8325 // if there are many clusters.
8326 sortAndRangeify(Clusters);
8328 if (TM.getOptLevel() != CodeGenOpt::None) {
8329 // Replace an unreachable default with the most popular destination.
8330 // FIXME: Exploit unreachable default more aggressively.
8331 bool UnreachableDefault =
8332 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8333 if (UnreachableDefault && !Clusters.empty()) {
8334 DenseMap<const BasicBlock *, unsigned> Popularity;
8335 unsigned MaxPop = 0;
8336 const BasicBlock *MaxBB = nullptr;
8337 for (auto I : SI.cases()) {
8338 const BasicBlock *BB = I.getCaseSuccessor();
8339 if (++Popularity[BB] > MaxPop) {
8340 MaxPop = Popularity[BB];
8345 assert(MaxPop > 0 && MaxBB);
8346 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8348 // Remove cases that were pointing to the destination that is now the
8350 CaseClusterVector New;
8351 New.reserve(Clusters.size());
8352 for (CaseCluster &CC : Clusters) {
8353 if (CC.MBB != DefaultMBB)
8356 Clusters = std::move(New);
8360 // If there is only the default destination, jump there directly.
8361 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8362 if (Clusters.empty()) {
8363 SwitchMBB->addSuccessor(DefaultMBB);
8364 if (DefaultMBB != NextBlock(SwitchMBB)) {
8365 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8366 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8371 findJumpTables(Clusters, &SI, DefaultMBB);
8372 findBitTestClusters(Clusters, &SI);
8375 dbgs() << "Case clusters: ";
8376 for (const CaseCluster &C : Clusters) {
8377 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8378 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8380 C.Low->getValue().print(dbgs(), true);
8381 if (C.Low != C.High) {
8383 C.High->getValue().print(dbgs(), true);
8390 assert(!Clusters.empty());
8391 SwitchWorkList WorkList;
8392 CaseClusterIt First = Clusters.begin();
8393 CaseClusterIt Last = Clusters.end() - 1;
8394 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8395 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8397 while (!WorkList.empty()) {
8398 SwitchWorkListItem W = WorkList.back();
8399 WorkList.pop_back();
8400 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8402 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8403 // For optimized builds, lower large range as a balanced binary tree.
8404 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8408 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);