1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetData.h"
49 #include "llvm/Target/TargetFrameInfo.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Support/Compiler.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Support/ErrorHandling.h"
58 #include "llvm/Support/MathExtras.h"
59 #include "llvm/Support/raw_ostream.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs. See
80 // 2010-11-11-ReturnBigBuffer.ll.
82 // MaxParallelChains default is arbitrarily high to avoid affecting
83 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
84 // sequence over this should have been converted to llvm.memcpy by the frontend.
85 static cl::opt<unsigned>
86 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
87 cl::init(64), cl::Hidden);
89 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
90 const SDValue *Parts, unsigned NumParts,
91 EVT PartVT, EVT ValueVT);
93 /// getCopyFromParts - Create a value that contains the specified legal parts
94 /// combined into the value they represent. If the parts combine to a type
95 /// larger then ValueVT then AssertOp can be used to specify whether the extra
96 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
97 /// (ISD::AssertSext).
98 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
102 if (ValueVT.isVector())
103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 assert(NumParts > 0 && "No parts to assemble!");
106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
107 SDValue Val = Parts[0];
110 // Assemble the value from multiple parts.
111 if (ValueVT.isInteger()) {
112 unsigned PartBits = PartVT.getSizeInBits();
113 unsigned ValueBits = ValueVT.getSizeInBits();
115 // Assemble the power of 2 part.
116 unsigned RoundParts = NumParts & (NumParts - 1) ?
117 1 << Log2_32(NumParts) : NumParts;
118 unsigned RoundBits = PartBits * RoundParts;
119 EVT RoundVT = RoundBits == ValueBits ?
120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
125 if (RoundParts > 2) {
126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
129 RoundParts / 2, PartVT, HalfVT);
131 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]);
132 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]);
135 if (TLI.isBigEndian())
138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
140 if (RoundParts < NumParts) {
141 // Assemble the trailing non-power-of-2 part.
142 unsigned OddParts = NumParts - RoundParts;
143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
144 Hi = getCopyFromParts(DAG, DL,
145 Parts + RoundParts, OddParts, PartVT, OddVT);
147 // Combine the round and odd parts.
149 if (TLI.isBigEndian())
151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
154 DAG.getConstant(Lo.getValueType().getSizeInBits(),
155 TLI.getPointerTy()));
156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
159 } else if (PartVT.isFloatingPoint()) {
160 // FP split into multiple FP parts (for ppcf128)
161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
164 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]);
165 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]);
166 if (TLI.isBigEndian())
168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
170 // FP split into integer parts (soft fp)
171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
172 !PartVT.isVector() && "Unexpected split");
173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
178 // There is now one part, held in Val. Correct it to match ValueVT.
179 PartVT = Val.getValueType();
181 if (PartVT == ValueVT)
184 if (PartVT.isInteger() && ValueVT.isInteger()) {
185 if (ValueVT.bitsLT(PartVT)) {
186 // For a truncate, see if we have any information to
187 // indicate whether the truncated bits will always be
188 // zero or sign-extension.
189 if (AssertOp != ISD::DELETED_NODE)
190 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
191 DAG.getValueType(ValueVT));
192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
198 // FP_ROUND's are always exact here.
199 if (ValueVT.bitsLT(Val.getValueType()))
200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
201 DAG.getIntPtrConstant(1));
203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
207 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
209 llvm_unreachable("Unknown mismatch!");
213 /// getCopyFromParts - Create a value that contains the specified legal parts
214 /// combined into the value they represent. If the parts combine to a type
215 /// larger then ValueVT then AssertOp can be used to specify whether the extra
216 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
217 /// (ISD::AssertSext).
218 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
219 const SDValue *Parts, unsigned NumParts,
220 EVT PartVT, EVT ValueVT) {
221 assert(ValueVT.isVector() && "Not a vector value");
222 assert(NumParts > 0 && "No parts to assemble!");
223 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
224 SDValue Val = Parts[0];
226 // Handle a multi-element vector.
228 EVT IntermediateVT, RegisterVT;
229 unsigned NumIntermediates;
231 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
232 NumIntermediates, RegisterVT);
233 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
234 NumParts = NumRegs; // Silence a compiler warning.
235 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
236 assert(RegisterVT == Parts[0].getValueType() &&
237 "Part type doesn't match part!");
239 // Assemble the parts into intermediate operands.
240 SmallVector<SDValue, 8> Ops(NumIntermediates);
241 if (NumIntermediates == NumParts) {
242 // If the register was not expanded, truncate or copy the value,
244 for (unsigned i = 0; i != NumParts; ++i)
245 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
246 PartVT, IntermediateVT);
247 } else if (NumParts > 0) {
248 // If the intermediate type was expanded, build the intermediate
249 // operands from the parts.
250 assert(NumParts % NumIntermediates == 0 &&
251 "Must expand into a divisible number of parts!");
252 unsigned Factor = NumParts / NumIntermediates;
253 for (unsigned i = 0; i != NumIntermediates; ++i)
254 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
255 PartVT, IntermediateVT);
258 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
259 // intermediate operands.
260 Val = DAG.getNode(IntermediateVT.isVector() ?
261 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
262 ValueVT, &Ops[0], NumIntermediates);
265 // There is now one part, held in Val. Correct it to match ValueVT.
266 PartVT = Val.getValueType();
268 if (PartVT == ValueVT)
271 if (PartVT.isVector()) {
272 // If the element type of the source/dest vectors are the same, but the
273 // parts vector has more elements than the value vector, then we have a
274 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
276 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
277 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
278 "Cannot narrow, it would be a lossy transformation");
279 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
280 DAG.getIntPtrConstant(0));
283 // Vector/Vector bitcast.
284 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
287 assert(ValueVT.getVectorElementType() == PartVT &&
288 ValueVT.getVectorNumElements() == 1 &&
289 "Only trivial scalar-to-vector conversions should get here!");
290 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
296 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
297 SDValue Val, SDValue *Parts, unsigned NumParts,
300 /// getCopyToParts - Create a series of nodes that contain the specified value
301 /// split into legal parts. If the parts contain more bits than Val, then, for
302 /// integers, ExtendKind can be used to specify how to generate the extra bits.
303 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
304 SDValue Val, SDValue *Parts, unsigned NumParts,
306 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
307 EVT ValueVT = Val.getValueType();
309 // Handle the vector case separately.
310 if (ValueVT.isVector())
311 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
314 unsigned PartBits = PartVT.getSizeInBits();
315 unsigned OrigNumParts = NumParts;
316 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
321 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
322 if (PartVT == ValueVT) {
323 assert(NumParts == 1 && "No-op copy with multiple parts!");
328 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
329 // If the parts cover more bits than the value has, promote the value.
330 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
331 assert(NumParts == 1 && "Do not know what to promote to!");
332 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
334 assert(PartVT.isInteger() && ValueVT.isInteger() &&
335 "Unknown mismatch!");
336 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
337 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
339 } else if (PartBits == ValueVT.getSizeInBits()) {
340 // Different types of the same size.
341 assert(NumParts == 1 && PartVT != ValueVT);
342 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
343 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
344 // If the parts cover less bits than value has, truncate the value.
345 assert(PartVT.isInteger() && ValueVT.isInteger() &&
346 "Unknown mismatch!");
347 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
348 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
351 // The value may have changed - recompute ValueVT.
352 ValueVT = Val.getValueType();
353 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
354 "Failed to tile the value with PartVT!");
357 assert(PartVT == ValueVT && "Type conversion failed!");
362 // Expand the value into multiple parts.
363 if (NumParts & (NumParts - 1)) {
364 // The number of parts is not a power of 2. Split off and copy the tail.
365 assert(PartVT.isInteger() && ValueVT.isInteger() &&
366 "Do not know what to expand to!");
367 unsigned RoundParts = 1 << Log2_32(NumParts);
368 unsigned RoundBits = RoundParts * PartBits;
369 unsigned OddParts = NumParts - RoundParts;
370 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
371 DAG.getIntPtrConstant(RoundBits));
372 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
374 if (TLI.isBigEndian())
375 // The odd parts were reversed by getCopyToParts - unreverse them.
376 std::reverse(Parts + RoundParts, Parts + NumParts);
378 NumParts = RoundParts;
379 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
380 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
383 // The number of parts is a power of 2. Repeatedly bisect the value using
385 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL,
386 EVT::getIntegerVT(*DAG.getContext(),
387 ValueVT.getSizeInBits()),
390 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
391 for (unsigned i = 0; i < NumParts; i += StepSize) {
392 unsigned ThisBits = StepSize * PartBits / 2;
393 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
394 SDValue &Part0 = Parts[i];
395 SDValue &Part1 = Parts[i+StepSize/2];
397 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
398 ThisVT, Part0, DAG.getIntPtrConstant(1));
399 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
400 ThisVT, Part0, DAG.getIntPtrConstant(0));
402 if (ThisBits == PartBits && ThisVT != PartVT) {
403 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0);
404 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1);
409 if (TLI.isBigEndian())
410 std::reverse(Parts, Parts + OrigNumParts);
414 /// getCopyToPartsVector - Create a series of nodes that contain the specified
415 /// value split into legal parts.
416 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
417 SDValue Val, SDValue *Parts, unsigned NumParts,
419 EVT ValueVT = Val.getValueType();
420 assert(ValueVT.isVector() && "Not a vector");
421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
424 if (PartVT == ValueVT) {
426 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
427 // Bitconvert vector->vector case.
428 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
429 } else if (PartVT.isVector() &&
430 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
431 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
432 EVT ElementVT = PartVT.getVectorElementType();
433 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
435 SmallVector<SDValue, 16> Ops;
436 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
437 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
438 ElementVT, Val, DAG.getIntPtrConstant(i)));
440 for (unsigned i = ValueVT.getVectorNumElements(),
441 e = PartVT.getVectorNumElements(); i != e; ++i)
442 Ops.push_back(DAG.getUNDEF(ElementVT));
444 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
446 // FIXME: Use CONCAT for 2x -> 4x.
448 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
449 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
451 // Vector -> scalar conversion.
452 assert(ValueVT.getVectorElementType() == PartVT &&
453 ValueVT.getVectorNumElements() == 1 &&
454 "Only trivial vector-to-scalar conversions should get here!");
455 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
456 PartVT, Val, DAG.getIntPtrConstant(0));
463 // Handle a multi-element vector.
464 EVT IntermediateVT, RegisterVT;
465 unsigned NumIntermediates;
466 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
468 NumIntermediates, RegisterVT);
469 unsigned NumElements = ValueVT.getVectorNumElements();
471 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
472 NumParts = NumRegs; // Silence a compiler warning.
473 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
475 // Split the vector into intermediate operands.
476 SmallVector<SDValue, 8> Ops(NumIntermediates);
477 for (unsigned i = 0; i != NumIntermediates; ++i) {
478 if (IntermediateVT.isVector())
479 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
481 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
483 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
484 IntermediateVT, Val, DAG.getIntPtrConstant(i));
487 // Split the intermediate operands into legal parts.
488 if (NumParts == NumIntermediates) {
489 // If the register was not expanded, promote or copy the value,
491 for (unsigned i = 0; i != NumParts; ++i)
492 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
493 } else if (NumParts > 0) {
494 // If the intermediate type was expanded, split each the value into
496 assert(NumParts % NumIntermediates == 0 &&
497 "Must expand into a divisible number of parts!");
498 unsigned Factor = NumParts / NumIntermediates;
499 for (unsigned i = 0; i != NumIntermediates; ++i)
500 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
508 /// RegsForValue - This struct represents the registers (physical or virtual)
509 /// that a particular set of values is assigned, and the type information
510 /// about the value. The most common situation is to represent one value at a
511 /// time, but struct or array values are handled element-wise as multiple
512 /// values. The splitting of aggregates is performed recursively, so that we
513 /// never have aggregate-typed registers. The values at this point do not
514 /// necessarily have legal types, so each value may require one or more
515 /// registers of some legal type.
517 struct RegsForValue {
518 /// ValueVTs - The value types of the values, which may not be legal, and
519 /// may need be promoted or synthesized from one or more registers.
521 SmallVector<EVT, 4> ValueVTs;
523 /// RegVTs - The value types of the registers. This is the same size as
524 /// ValueVTs and it records, for each value, what the type of the assigned
525 /// register or registers are. (Individual values are never synthesized
526 /// from more than one type of register.)
528 /// With virtual registers, the contents of RegVTs is redundant with TLI's
529 /// getRegisterType member function, however when with physical registers
530 /// it is necessary to have a separate record of the types.
532 SmallVector<EVT, 4> RegVTs;
534 /// Regs - This list holds the registers assigned to the values.
535 /// Each legal or promoted value requires one register, and each
536 /// expanded value requires multiple registers.
538 SmallVector<unsigned, 4> Regs;
542 RegsForValue(const SmallVector<unsigned, 4> ®s,
543 EVT regvt, EVT valuevt)
544 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
546 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
547 unsigned Reg, const Type *Ty) {
548 ComputeValueVTs(tli, Ty, ValueVTs);
550 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
551 EVT ValueVT = ValueVTs[Value];
552 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
553 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
554 for (unsigned i = 0; i != NumRegs; ++i)
555 Regs.push_back(Reg + i);
556 RegVTs.push_back(RegisterVT);
561 /// areValueTypesLegal - Return true if types of all the values are legal.
562 bool areValueTypesLegal(const TargetLowering &TLI) {
563 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
564 EVT RegisterVT = RegVTs[Value];
565 if (!TLI.isTypeLegal(RegisterVT))
571 /// append - Add the specified values to this one.
572 void append(const RegsForValue &RHS) {
573 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
574 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
575 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
578 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
579 /// this value and returns the result as a ValueVTs value. This uses
580 /// Chain/Flag as the input and updates them for the output Chain/Flag.
581 /// If the Flag pointer is NULL, no flag is used.
582 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
584 SDValue &Chain, SDValue *Flag) const;
586 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
587 /// specified value into the registers specified by this object. This uses
588 /// Chain/Flag as the input and updates them for the output Chain/Flag.
589 /// If the Flag pointer is NULL, no flag is used.
590 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
591 SDValue &Chain, SDValue *Flag) const;
593 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
594 /// operand list. This adds the code marker, matching input operand index
595 /// (if applicable), and includes the number of values added into it.
596 void AddInlineAsmOperands(unsigned Kind,
597 bool HasMatching, unsigned MatchingIdx,
599 std::vector<SDValue> &Ops) const;
603 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
604 /// this value and returns the result as a ValueVT value. This uses
605 /// Chain/Flag as the input and updates them for the output Chain/Flag.
606 /// If the Flag pointer is NULL, no flag is used.
607 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
608 FunctionLoweringInfo &FuncInfo,
610 SDValue &Chain, SDValue *Flag) const {
611 // A Value with type {} or [0 x %t] needs no registers.
612 if (ValueVTs.empty())
615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
617 // Assemble the legal parts into the final values.
618 SmallVector<SDValue, 4> Values(ValueVTs.size());
619 SmallVector<SDValue, 8> Parts;
620 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
621 // Copy the legal parts from the registers.
622 EVT ValueVT = ValueVTs[Value];
623 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
624 EVT RegisterVT = RegVTs[Value];
626 Parts.resize(NumRegs);
627 for (unsigned i = 0; i != NumRegs; ++i) {
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
633 *Flag = P.getValue(2);
636 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
641 RegisterVT.isInteger() && !RegisterVT.isVector()) {
642 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
643 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
644 const FunctionLoweringInfo::LiveOutInfo &LOI =
645 FuncInfo.LiveOutRegInfo[SlotNo];
647 unsigned RegSize = RegisterVT.getSizeInBits();
648 unsigned NumSignBits = LOI.NumSignBits;
649 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
651 // FIXME: We capture more information than the dag can represent. For
652 // now, just use the tightest assertzext/assertsext possible.
654 EVT FromVT(MVT::Other);
655 if (NumSignBits == RegSize)
656 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
657 else if (NumZeroBits >= RegSize-1)
658 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
659 else if (NumSignBits > RegSize-8)
660 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
661 else if (NumZeroBits >= RegSize-8)
662 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
663 else if (NumSignBits > RegSize-16)
664 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
665 else if (NumZeroBits >= RegSize-16)
666 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
667 else if (NumSignBits > RegSize-32)
668 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
669 else if (NumZeroBits >= RegSize-32)
670 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
672 if (FromVT != MVT::Other)
673 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
674 RegisterVT, P, DAG.getValueType(FromVT));
681 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
682 NumRegs, RegisterVT, ValueVT);
687 return DAG.getNode(ISD::MERGE_VALUES, dl,
688 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
689 &Values[0], ValueVTs.size());
692 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
693 /// specified value into the registers specified by this object. This uses
694 /// Chain/Flag as the input and updates them for the output Chain/Flag.
695 /// If the Flag pointer is NULL, no flag is used.
696 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
697 SDValue &Chain, SDValue *Flag) const {
698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
700 // Get the list of the values's legal parts.
701 unsigned NumRegs = Regs.size();
702 SmallVector<SDValue, 8> Parts(NumRegs);
703 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
704 EVT ValueVT = ValueVTs[Value];
705 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
706 EVT RegisterVT = RegVTs[Value];
708 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
709 &Parts[Part], NumParts, RegisterVT);
713 // Copy the parts into the registers.
714 SmallVector<SDValue, 8> Chains(NumRegs);
715 for (unsigned i = 0; i != NumRegs; ++i) {
718 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
720 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
721 *Flag = Part.getValue(1);
724 Chains[i] = Part.getValue(0);
727 if (NumRegs == 1 || Flag)
728 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
729 // flagged to it. That is the CopyToReg nodes and the user are considered
730 // a single scheduling unit. If we create a TokenFactor and return it as
731 // chain, then the TokenFactor is both a predecessor (operand) of the
732 // user as well as a successor (the TF operands are flagged to the user).
733 // c1, f1 = CopyToReg
734 // c2, f2 = CopyToReg
735 // c3 = TokenFactor c1, c2
738 Chain = Chains[NumRegs-1];
740 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
743 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
744 /// operand list. This adds the code marker and includes the number of
745 /// values added into it.
746 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
747 unsigned MatchingIdx,
749 std::vector<SDValue> &Ops) const {
750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
752 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
754 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
755 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
758 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
759 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
760 EVT RegisterVT = RegVTs[Value];
761 for (unsigned i = 0; i != NumRegs; ++i) {
762 assert(Reg < Regs.size() && "Mismatch in # registers expected");
763 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
768 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
771 TD = DAG.getTarget().getTargetData();
774 /// clear - Clear out the current SelectionDAG and the associated
775 /// state and prepare this SelectionDAGBuilder object to be used
776 /// for a new block. This doesn't clear out information about
777 /// additional blocks that are needed to complete switch lowering
778 /// or PHI node updating; that information is cleared out as it is
780 void SelectionDAGBuilder::clear() {
782 UnusedArgNodeMap.clear();
783 PendingLoads.clear();
784 PendingExports.clear();
785 DanglingDebugInfoMap.clear();
786 CurDebugLoc = DebugLoc();
790 /// getRoot - Return the current virtual root of the Selection DAG,
791 /// flushing any PendingLoad items. This must be done before emitting
792 /// a store or any other node that may need to be ordered after any
793 /// prior load instructions.
795 SDValue SelectionDAGBuilder::getRoot() {
796 if (PendingLoads.empty())
797 return DAG.getRoot();
799 if (PendingLoads.size() == 1) {
800 SDValue Root = PendingLoads[0];
802 PendingLoads.clear();
806 // Otherwise, we have to make a token factor node.
807 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
808 &PendingLoads[0], PendingLoads.size());
809 PendingLoads.clear();
814 /// getControlRoot - Similar to getRoot, but instead of flushing all the
815 /// PendingLoad items, flush all the PendingExports items. It is necessary
816 /// to do this before emitting a terminator instruction.
818 SDValue SelectionDAGBuilder::getControlRoot() {
819 SDValue Root = DAG.getRoot();
821 if (PendingExports.empty())
824 // Turn all of the CopyToReg chains into one factored node.
825 if (Root.getOpcode() != ISD::EntryToken) {
826 unsigned i = 0, e = PendingExports.size();
827 for (; i != e; ++i) {
828 assert(PendingExports[i].getNode()->getNumOperands() > 1);
829 if (PendingExports[i].getNode()->getOperand(0) == Root)
830 break; // Don't add the root if we already indirectly depend on it.
834 PendingExports.push_back(Root);
837 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
839 PendingExports.size());
840 PendingExports.clear();
845 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
846 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
847 DAG.AssignOrdering(Node, SDNodeOrder);
849 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
850 AssignOrderingToNode(Node->getOperand(I).getNode());
853 void SelectionDAGBuilder::visit(const Instruction &I) {
854 // Set up outgoing PHI node register values before emitting the terminator.
855 if (isa<TerminatorInst>(&I))
856 HandlePHINodesInSuccessorBlocks(I.getParent());
858 CurDebugLoc = I.getDebugLoc();
860 visit(I.getOpcode(), I);
862 if (!isa<TerminatorInst>(&I) && !HasTailCall)
863 CopyToExportRegsIfNeeded(&I);
865 CurDebugLoc = DebugLoc();
868 void SelectionDAGBuilder::visitPHI(const PHINode &) {
869 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
872 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
873 // Note: this doesn't use InstVisitor, because it has to work with
874 // ConstantExpr's in addition to instructions.
876 default: llvm_unreachable("Unknown instruction type encountered!");
877 // Build the switch statement using the Instruction.def file.
878 #define HANDLE_INST(NUM, OPCODE, CLASS) \
879 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
880 #include "llvm/Instruction.def"
883 // Assign the ordering to the freshly created DAG nodes.
884 if (NodeMap.count(&I)) {
886 AssignOrderingToNode(getValue(&I).getNode());
890 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
891 // generate the debug data structures now that we've seen its definition.
892 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
894 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
896 const DbgValueInst *DI = DDI.getDI();
897 DebugLoc dl = DDI.getdl();
898 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
899 MDNode *Variable = DI->getVariable();
900 uint64_t Offset = DI->getOffset();
903 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
904 SDV = DAG.getDbgValue(Variable, Val.getNode(),
905 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
906 DAG.AddDbgValue(SDV, Val.getNode(), false);
909 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
910 Offset, dl, SDNodeOrder);
911 DAG.AddDbgValue(SDV, 0, false);
913 DanglingDebugInfoMap[V] = DanglingDebugInfo();
917 // getValue - Return an SDValue for the given Value.
918 SDValue SelectionDAGBuilder::getValue(const Value *V) {
919 // If we already have an SDValue for this value, use it. It's important
920 // to do this first, so that we don't create a CopyFromReg if we already
921 // have a regular SDValue.
922 SDValue &N = NodeMap[V];
923 if (N.getNode()) return N;
925 // If there's a virtual register allocated and initialized for this
927 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
928 if (It != FuncInfo.ValueMap.end()) {
929 unsigned InReg = It->second;
930 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
931 SDValue Chain = DAG.getEntryNode();
932 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
935 // Otherwise create a new SDValue and remember it.
936 SDValue Val = getValueImpl(V);
938 resolveDanglingDebugInfo(V, Val);
942 /// getNonRegisterValue - Return an SDValue for the given Value, but
943 /// don't look in FuncInfo.ValueMap for a virtual register.
944 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
945 // If we already have an SDValue for this value, use it.
946 SDValue &N = NodeMap[V];
947 if (N.getNode()) return N;
949 // Otherwise create a new SDValue and remember it.
950 SDValue Val = getValueImpl(V);
952 resolveDanglingDebugInfo(V, Val);
956 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
957 /// Create an SDValue for the given value.
958 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
959 if (const Constant *C = dyn_cast<Constant>(V)) {
960 EVT VT = TLI.getValueType(V->getType(), true);
962 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
963 return DAG.getConstant(*CI, VT);
965 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
966 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
968 if (isa<ConstantPointerNull>(C))
969 return DAG.getConstant(0, TLI.getPointerTy());
971 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
972 return DAG.getConstantFP(*CFP, VT);
974 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
975 return DAG.getUNDEF(VT);
977 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
978 visit(CE->getOpcode(), *CE);
979 SDValue N1 = NodeMap[V];
980 assert(N1.getNode() && "visit didn't populate the NodeMap!");
984 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
985 SmallVector<SDValue, 4> Constants;
986 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
988 SDNode *Val = getValue(*OI).getNode();
989 // If the operand is an empty aggregate, there are no values.
991 // Add each leaf value from the operand to the Constants list
992 // to form a flattened list of all the values.
993 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
994 Constants.push_back(SDValue(Val, i));
997 return DAG.getMergeValues(&Constants[0], Constants.size(),
1001 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1002 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1003 "Unknown struct or array constant!");
1005 SmallVector<EVT, 4> ValueVTs;
1006 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1007 unsigned NumElts = ValueVTs.size();
1009 return SDValue(); // empty struct
1010 SmallVector<SDValue, 4> Constants(NumElts);
1011 for (unsigned i = 0; i != NumElts; ++i) {
1012 EVT EltVT = ValueVTs[i];
1013 if (isa<UndefValue>(C))
1014 Constants[i] = DAG.getUNDEF(EltVT);
1015 else if (EltVT.isFloatingPoint())
1016 Constants[i] = DAG.getConstantFP(0, EltVT);
1018 Constants[i] = DAG.getConstant(0, EltVT);
1021 return DAG.getMergeValues(&Constants[0], NumElts,
1025 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1026 return DAG.getBlockAddress(BA, VT);
1028 const VectorType *VecTy = cast<VectorType>(V->getType());
1029 unsigned NumElements = VecTy->getNumElements();
1031 // Now that we know the number and type of the elements, get that number of
1032 // elements into the Ops array based on what kind of constant it is.
1033 SmallVector<SDValue, 16> Ops;
1034 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1035 for (unsigned i = 0; i != NumElements; ++i)
1036 Ops.push_back(getValue(CP->getOperand(i)));
1038 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1039 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1042 if (EltVT.isFloatingPoint())
1043 Op = DAG.getConstantFP(0, EltVT);
1045 Op = DAG.getConstant(0, EltVT);
1046 Ops.assign(NumElements, Op);
1049 // Create a BUILD_VECTOR node.
1050 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1051 VT, &Ops[0], Ops.size());
1054 // If this is a static alloca, generate it as the frameindex instead of
1056 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1057 DenseMap<const AllocaInst*, int>::iterator SI =
1058 FuncInfo.StaticAllocaMap.find(AI);
1059 if (SI != FuncInfo.StaticAllocaMap.end())
1060 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1063 // If this is an instruction which fast-isel has deferred, select it now.
1064 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1065 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1066 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1067 SDValue Chain = DAG.getEntryNode();
1068 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1071 llvm_unreachable("Can't get register for value!");
1075 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1076 SDValue Chain = getControlRoot();
1077 SmallVector<ISD::OutputArg, 8> Outs;
1078 SmallVector<SDValue, 8> OutVals;
1080 if (!FuncInfo.CanLowerReturn) {
1081 unsigned DemoteReg = FuncInfo.DemoteRegister;
1082 const Function *F = I.getParent()->getParent();
1084 // Emit a store of the return value through the virtual register.
1085 // Leave Outs empty so that LowerReturn won't try to load return
1086 // registers the usual way.
1087 SmallVector<EVT, 1> PtrValueVTs;
1088 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1091 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1092 SDValue RetOp = getValue(I.getOperand(0));
1094 SmallVector<EVT, 4> ValueVTs;
1095 SmallVector<uint64_t, 4> Offsets;
1096 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1097 unsigned NumValues = ValueVTs.size();
1099 SmallVector<SDValue, 4> Chains(NumValues);
1100 for (unsigned i = 0; i != NumValues; ++i) {
1101 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1102 RetPtr.getValueType(), RetPtr,
1103 DAG.getIntPtrConstant(Offsets[i]));
1105 DAG.getStore(Chain, getCurDebugLoc(),
1106 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1107 // FIXME: better loc info would be nice.
1108 Add, MachinePointerInfo(), false, false, 0);
1111 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1112 MVT::Other, &Chains[0], NumValues);
1113 } else if (I.getNumOperands() != 0) {
1114 SmallVector<EVT, 4> ValueVTs;
1115 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1116 unsigned NumValues = ValueVTs.size();
1118 SDValue RetOp = getValue(I.getOperand(0));
1119 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1120 EVT VT = ValueVTs[j];
1122 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1124 const Function *F = I.getParent()->getParent();
1125 if (F->paramHasAttr(0, Attribute::SExt))
1126 ExtendKind = ISD::SIGN_EXTEND;
1127 else if (F->paramHasAttr(0, Attribute::ZExt))
1128 ExtendKind = ISD::ZERO_EXTEND;
1130 // FIXME: C calling convention requires the return type to be promoted
1131 // to at least 32-bit. But this is not necessary for non-C calling
1132 // conventions. The frontend should mark functions whose return values
1133 // require promoting with signext or zeroext attributes.
1134 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1135 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1136 if (VT.bitsLT(MinVT))
1140 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1141 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1142 SmallVector<SDValue, 4> Parts(NumParts);
1143 getCopyToParts(DAG, getCurDebugLoc(),
1144 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1145 &Parts[0], NumParts, PartVT, ExtendKind);
1147 // 'inreg' on function refers to return value
1148 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1149 if (F->paramHasAttr(0, Attribute::InReg))
1152 // Propagate extension type if any
1153 if (F->paramHasAttr(0, Attribute::SExt))
1155 else if (F->paramHasAttr(0, Attribute::ZExt))
1158 for (unsigned i = 0; i < NumParts; ++i) {
1159 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1161 OutVals.push_back(Parts[i]);
1167 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1168 CallingConv::ID CallConv =
1169 DAG.getMachineFunction().getFunction()->getCallingConv();
1170 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1171 Outs, OutVals, getCurDebugLoc(), DAG);
1173 // Verify that the target's LowerReturn behaved as expected.
1174 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1175 "LowerReturn didn't return a valid chain!");
1177 // Update the DAG with the new chain value resulting from return lowering.
1181 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1182 /// created for it, emit nodes to copy the value into the virtual
1184 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1185 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1186 if (VMI != FuncInfo.ValueMap.end()) {
1187 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1188 CopyValueToVirtualRegister(V, VMI->second);
1192 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1193 /// the current basic block, add it to ValueMap now so that we'll get a
1195 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1196 // No need to export constants.
1197 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1199 // Already exported?
1200 if (FuncInfo.isExportedInst(V)) return;
1202 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1203 CopyValueToVirtualRegister(V, Reg);
1206 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1207 const BasicBlock *FromBB) {
1208 // The operands of the setcc have to be in this block. We don't know
1209 // how to export them from some other block.
1210 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1211 // Can export from current BB.
1212 if (VI->getParent() == FromBB)
1215 // Is already exported, noop.
1216 return FuncInfo.isExportedInst(V);
1219 // If this is an argument, we can export it if the BB is the entry block or
1220 // if it is already exported.
1221 if (isa<Argument>(V)) {
1222 if (FromBB == &FromBB->getParent()->getEntryBlock())
1225 // Otherwise, can only export this if it is already exported.
1226 return FuncInfo.isExportedInst(V);
1229 // Otherwise, constants can always be exported.
1233 static bool InBlock(const Value *V, const BasicBlock *BB) {
1234 if (const Instruction *I = dyn_cast<Instruction>(V))
1235 return I->getParent() == BB;
1239 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1240 /// This function emits a branch and is used at the leaves of an OR or an
1241 /// AND operator tree.
1244 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1245 MachineBasicBlock *TBB,
1246 MachineBasicBlock *FBB,
1247 MachineBasicBlock *CurBB,
1248 MachineBasicBlock *SwitchBB) {
1249 const BasicBlock *BB = CurBB->getBasicBlock();
1251 // If the leaf of the tree is a comparison, merge the condition into
1253 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1254 // The operands of the cmp have to be in this block. We don't know
1255 // how to export them from some other block. If this is the first block
1256 // of the sequence, no exporting is needed.
1257 if (CurBB == SwitchBB ||
1258 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1259 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1260 ISD::CondCode Condition;
1261 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1262 Condition = getICmpCondCode(IC->getPredicate());
1263 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1264 Condition = getFCmpCondCode(FC->getPredicate());
1266 Condition = ISD::SETEQ; // silence warning.
1267 llvm_unreachable("Unknown compare instruction");
1270 CaseBlock CB(Condition, BOp->getOperand(0),
1271 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1272 SwitchCases.push_back(CB);
1277 // Create a CaseBlock record representing this branch.
1278 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1279 NULL, TBB, FBB, CurBB);
1280 SwitchCases.push_back(CB);
1283 /// FindMergedConditions - If Cond is an expression like
1284 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1285 MachineBasicBlock *TBB,
1286 MachineBasicBlock *FBB,
1287 MachineBasicBlock *CurBB,
1288 MachineBasicBlock *SwitchBB,
1290 // If this node is not part of the or/and tree, emit it as a branch.
1291 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1292 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1293 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1294 BOp->getParent() != CurBB->getBasicBlock() ||
1295 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1296 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1297 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1301 // Create TmpBB after CurBB.
1302 MachineFunction::iterator BBI = CurBB;
1303 MachineFunction &MF = DAG.getMachineFunction();
1304 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1305 CurBB->getParent()->insert(++BBI, TmpBB);
1307 if (Opc == Instruction::Or) {
1308 // Codegen X | Y as:
1316 // Emit the LHS condition.
1317 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1319 // Emit the RHS condition into TmpBB.
1320 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1322 assert(Opc == Instruction::And && "Unknown merge op!");
1323 // Codegen X & Y as:
1330 // This requires creation of TmpBB after CurBB.
1332 // Emit the LHS condition.
1333 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1335 // Emit the RHS condition into TmpBB.
1336 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1340 /// If the set of cases should be emitted as a series of branches, return true.
1341 /// If we should emit this as a bunch of and/or'd together conditions, return
1344 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1345 if (Cases.size() != 2) return true;
1347 // If this is two comparisons of the same values or'd or and'd together, they
1348 // will get folded into a single comparison, so don't emit two blocks.
1349 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1350 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1351 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1352 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1356 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1357 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1358 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1359 Cases[0].CC == Cases[1].CC &&
1360 isa<Constant>(Cases[0].CmpRHS) &&
1361 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1362 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1364 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1371 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1372 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1374 // Update machine-CFG edges.
1375 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1377 // Figure out which block is immediately after the current one.
1378 MachineBasicBlock *NextBlock = 0;
1379 MachineFunction::iterator BBI = BrMBB;
1380 if (++BBI != FuncInfo.MF->end())
1383 if (I.isUnconditional()) {
1384 // Update machine-CFG edges.
1385 BrMBB->addSuccessor(Succ0MBB);
1387 // If this is not a fall-through branch, emit the branch.
1388 if (Succ0MBB != NextBlock)
1389 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1390 MVT::Other, getControlRoot(),
1391 DAG.getBasicBlock(Succ0MBB)));
1396 // If this condition is one of the special cases we handle, do special stuff
1398 const Value *CondVal = I.getCondition();
1399 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1401 // If this is a series of conditions that are or'd or and'd together, emit
1402 // this as a sequence of branches instead of setcc's with and/or operations.
1403 // For example, instead of something like:
1416 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1417 if (BOp->hasOneUse() &&
1418 (BOp->getOpcode() == Instruction::And ||
1419 BOp->getOpcode() == Instruction::Or)) {
1420 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1422 // If the compares in later blocks need to use values not currently
1423 // exported from this block, export them now. This block should always
1424 // be the first entry.
1425 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1427 // Allow some cases to be rejected.
1428 if (ShouldEmitAsBranches(SwitchCases)) {
1429 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1430 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1431 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1434 // Emit the branch for this block.
1435 visitSwitchCase(SwitchCases[0], BrMBB);
1436 SwitchCases.erase(SwitchCases.begin());
1440 // Okay, we decided not to do this, remove any inserted MBB's and clear
1442 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1443 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1445 SwitchCases.clear();
1449 // Create a CaseBlock record representing this branch.
1450 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1451 NULL, Succ0MBB, Succ1MBB, BrMBB);
1453 // Use visitSwitchCase to actually insert the fast branch sequence for this
1455 visitSwitchCase(CB, BrMBB);
1458 /// visitSwitchCase - Emits the necessary code to represent a single node in
1459 /// the binary search tree resulting from lowering a switch instruction.
1460 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1461 MachineBasicBlock *SwitchBB) {
1463 SDValue CondLHS = getValue(CB.CmpLHS);
1464 DebugLoc dl = getCurDebugLoc();
1466 // Build the setcc now.
1467 if (CB.CmpMHS == NULL) {
1468 // Fold "(X == true)" to X and "(X == false)" to !X to
1469 // handle common cases produced by branch lowering.
1470 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1471 CB.CC == ISD::SETEQ)
1473 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1474 CB.CC == ISD::SETEQ) {
1475 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1476 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1478 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1480 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1482 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1483 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1485 SDValue CmpOp = getValue(CB.CmpMHS);
1486 EVT VT = CmpOp.getValueType();
1488 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1489 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1492 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1493 VT, CmpOp, DAG.getConstant(Low, VT));
1494 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1495 DAG.getConstant(High-Low, VT), ISD::SETULE);
1499 // Update successor info
1500 SwitchBB->addSuccessor(CB.TrueBB);
1501 SwitchBB->addSuccessor(CB.FalseBB);
1503 // Set NextBlock to be the MBB immediately after the current one, if any.
1504 // This is used to avoid emitting unnecessary branches to the next block.
1505 MachineBasicBlock *NextBlock = 0;
1506 MachineFunction::iterator BBI = SwitchBB;
1507 if (++BBI != FuncInfo.MF->end())
1510 // If the lhs block is the next block, invert the condition so that we can
1511 // fall through to the lhs instead of the rhs block.
1512 if (CB.TrueBB == NextBlock) {
1513 std::swap(CB.TrueBB, CB.FalseBB);
1514 SDValue True = DAG.getConstant(1, Cond.getValueType());
1515 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1518 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1519 MVT::Other, getControlRoot(), Cond,
1520 DAG.getBasicBlock(CB.TrueBB));
1522 // Insert the false branch. Do this even if it's a fall through branch,
1523 // this makes it easier to do DAG optimizations which require inverting
1524 // the branch condition.
1525 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1526 DAG.getBasicBlock(CB.FalseBB));
1528 DAG.setRoot(BrCond);
1531 /// visitJumpTable - Emit JumpTable node in the current MBB
1532 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1533 // Emit the code for the jump table
1534 assert(JT.Reg != -1U && "Should lower JT Header first!");
1535 EVT PTy = TLI.getPointerTy();
1536 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1538 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1539 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1540 MVT::Other, Index.getValue(1),
1542 DAG.setRoot(BrJumpTable);
1545 /// visitJumpTableHeader - This function emits necessary code to produce index
1546 /// in the JumpTable from switch case.
1547 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1548 JumpTableHeader &JTH,
1549 MachineBasicBlock *SwitchBB) {
1550 // Subtract the lowest switch case value from the value being switched on and
1551 // conditional branch to default mbb if the result is greater than the
1552 // difference between smallest and largest cases.
1553 SDValue SwitchOp = getValue(JTH.SValue);
1554 EVT VT = SwitchOp.getValueType();
1555 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1556 DAG.getConstant(JTH.First, VT));
1558 // The SDNode we just created, which holds the value being switched on minus
1559 // the smallest case value, needs to be copied to a virtual register so it
1560 // can be used as an index into the jump table in a subsequent basic block.
1561 // This value may be smaller or larger than the target's pointer type, and
1562 // therefore require extension or truncating.
1563 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1565 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1566 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1567 JumpTableReg, SwitchOp);
1568 JT.Reg = JumpTableReg;
1570 // Emit the range check for the jump table, and branch to the default block
1571 // for the switch statement if the value being switched on exceeds the largest
1572 // case in the switch.
1573 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1574 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1575 DAG.getConstant(JTH.Last-JTH.First,VT),
1578 // Set NextBlock to be the MBB immediately after the current one, if any.
1579 // This is used to avoid emitting unnecessary branches to the next block.
1580 MachineBasicBlock *NextBlock = 0;
1581 MachineFunction::iterator BBI = SwitchBB;
1583 if (++BBI != FuncInfo.MF->end())
1586 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1587 MVT::Other, CopyTo, CMP,
1588 DAG.getBasicBlock(JT.Default));
1590 if (JT.MBB != NextBlock)
1591 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1592 DAG.getBasicBlock(JT.MBB));
1594 DAG.setRoot(BrCond);
1597 /// visitBitTestHeader - This function emits necessary code to produce value
1598 /// suitable for "bit tests"
1599 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1600 MachineBasicBlock *SwitchBB) {
1601 // Subtract the minimum value
1602 SDValue SwitchOp = getValue(B.SValue);
1603 EVT VT = SwitchOp.getValueType();
1604 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1605 DAG.getConstant(B.First, VT));
1608 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1609 TLI.getSetCCResultType(Sub.getValueType()),
1610 Sub, DAG.getConstant(B.Range, VT),
1613 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1614 TLI.getPointerTy());
1616 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
1617 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1620 // Set NextBlock to be the MBB immediately after the current one, if any.
1621 // This is used to avoid emitting unnecessary branches to the next block.
1622 MachineBasicBlock *NextBlock = 0;
1623 MachineFunction::iterator BBI = SwitchBB;
1624 if (++BBI != FuncInfo.MF->end())
1627 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1629 SwitchBB->addSuccessor(B.Default);
1630 SwitchBB->addSuccessor(MBB);
1632 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1633 MVT::Other, CopyTo, RangeCmp,
1634 DAG.getBasicBlock(B.Default));
1636 if (MBB != NextBlock)
1637 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1638 DAG.getBasicBlock(MBB));
1640 DAG.setRoot(BrRange);
1643 /// visitBitTestCase - this function produces one "bit test"
1644 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1647 MachineBasicBlock *SwitchBB) {
1648 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1649 TLI.getPointerTy());
1651 if (CountPopulation_64(B.Mask) == 1) {
1652 // Testing for a single bit; just compare the shift count with what it
1653 // would need to be to shift a 1 bit in that position.
1654 Cmp = DAG.getSetCC(getCurDebugLoc(),
1655 TLI.getSetCCResultType(ShiftOp.getValueType()),
1657 DAG.getConstant(CountTrailingZeros_64(B.Mask),
1658 TLI.getPointerTy()),
1661 // Make desired shift
1662 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1664 DAG.getConstant(1, TLI.getPointerTy()),
1667 // Emit bit tests and jumps
1668 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1669 TLI.getPointerTy(), SwitchVal,
1670 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1671 Cmp = DAG.getSetCC(getCurDebugLoc(),
1672 TLI.getSetCCResultType(AndOp.getValueType()),
1673 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1677 SwitchBB->addSuccessor(B.TargetBB);
1678 SwitchBB->addSuccessor(NextMBB);
1680 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1681 MVT::Other, getControlRoot(),
1682 Cmp, DAG.getBasicBlock(B.TargetBB));
1684 // Set NextBlock to be the MBB immediately after the current one, if any.
1685 // This is used to avoid emitting unnecessary branches to the next block.
1686 MachineBasicBlock *NextBlock = 0;
1687 MachineFunction::iterator BBI = SwitchBB;
1688 if (++BBI != FuncInfo.MF->end())
1691 if (NextMBB != NextBlock)
1692 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1693 DAG.getBasicBlock(NextMBB));
1698 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1699 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1701 // Retrieve successors.
1702 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1703 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1705 const Value *Callee(I.getCalledValue());
1706 if (isa<InlineAsm>(Callee))
1709 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1711 // If the value of the invoke is used outside of its defining block, make it
1712 // available as a virtual register.
1713 CopyToExportRegsIfNeeded(&I);
1715 // Update successor info
1716 InvokeMBB->addSuccessor(Return);
1717 InvokeMBB->addSuccessor(LandingPad);
1719 // Drop into normal successor.
1720 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1721 MVT::Other, getControlRoot(),
1722 DAG.getBasicBlock(Return)));
1725 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1728 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1729 /// small case ranges).
1730 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1731 CaseRecVector& WorkList,
1733 MachineBasicBlock *Default,
1734 MachineBasicBlock *SwitchBB) {
1735 Case& BackCase = *(CR.Range.second-1);
1737 // Size is the number of Cases represented by this range.
1738 size_t Size = CR.Range.second - CR.Range.first;
1742 // Get the MachineFunction which holds the current MBB. This is used when
1743 // inserting any additional MBBs necessary to represent the switch.
1744 MachineFunction *CurMF = FuncInfo.MF;
1746 // Figure out which block is immediately after the current one.
1747 MachineBasicBlock *NextBlock = 0;
1748 MachineFunction::iterator BBI = CR.CaseBB;
1750 if (++BBI != FuncInfo.MF->end())
1753 // TODO: If any two of the cases has the same destination, and if one value
1754 // is the same as the other, but has one bit unset that the other has set,
1755 // use bit manipulation to do two compares at once. For example:
1756 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1758 // Rearrange the case blocks so that the last one falls through if possible.
1759 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1760 // The last case block won't fall through into 'NextBlock' if we emit the
1761 // branches in this order. See if rearranging a case value would help.
1762 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1763 if (I->BB == NextBlock) {
1764 std::swap(*I, BackCase);
1770 // Create a CaseBlock record representing a conditional branch to
1771 // the Case's target mbb if the value being switched on SV is equal
1773 MachineBasicBlock *CurBlock = CR.CaseBB;
1774 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1775 MachineBasicBlock *FallThrough;
1777 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1778 CurMF->insert(BBI, FallThrough);
1780 // Put SV in a virtual register to make it available from the new blocks.
1781 ExportFromCurrentBlock(SV);
1783 // If the last case doesn't match, go to the default block.
1784 FallThrough = Default;
1787 const Value *RHS, *LHS, *MHS;
1789 if (I->High == I->Low) {
1790 // This is just small small case range :) containing exactly 1 case
1792 LHS = SV; RHS = I->High; MHS = NULL;
1795 LHS = I->Low; MHS = SV; RHS = I->High;
1797 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1799 // If emitting the first comparison, just call visitSwitchCase to emit the
1800 // code into the current block. Otherwise, push the CaseBlock onto the
1801 // vector to be later processed by SDISel, and insert the node's MBB
1802 // before the next MBB.
1803 if (CurBlock == SwitchBB)
1804 visitSwitchCase(CB, SwitchBB);
1806 SwitchCases.push_back(CB);
1808 CurBlock = FallThrough;
1814 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1815 return !DisableJumpTables &&
1816 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1817 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1820 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1821 APInt LastExt(Last), FirstExt(First);
1822 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1823 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1824 return (LastExt - FirstExt + 1ULL);
1827 /// handleJTSwitchCase - Emit jumptable for current switch case range
1828 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1829 CaseRecVector& WorkList,
1831 MachineBasicBlock* Default,
1832 MachineBasicBlock *SwitchBB) {
1833 Case& FrontCase = *CR.Range.first;
1834 Case& BackCase = *(CR.Range.second-1);
1836 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1837 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1839 APInt TSize(First.getBitWidth(), 0);
1840 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1844 if (!areJTsAllowed(TLI) || TSize.ult(4))
1847 APInt Range = ComputeRange(First, Last);
1848 double Density = TSize.roundToDouble() / Range.roundToDouble();
1852 DEBUG(dbgs() << "Lowering jump table\n"
1853 << "First entry: " << First << ". Last entry: " << Last << '\n'
1854 << "Range: " << Range
1855 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1857 // Get the MachineFunction which holds the current MBB. This is used when
1858 // inserting any additional MBBs necessary to represent the switch.
1859 MachineFunction *CurMF = FuncInfo.MF;
1861 // Figure out which block is immediately after the current one.
1862 MachineFunction::iterator BBI = CR.CaseBB;
1865 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1867 // Create a new basic block to hold the code for loading the address
1868 // of the jump table, and jumping to it. Update successor information;
1869 // we will either branch to the default case for the switch, or the jump
1871 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1872 CurMF->insert(BBI, JumpTableBB);
1873 CR.CaseBB->addSuccessor(Default);
1874 CR.CaseBB->addSuccessor(JumpTableBB);
1876 // Build a vector of destination BBs, corresponding to each target
1877 // of the jump table. If the value of the jump table slot corresponds to
1878 // a case statement, push the case's BB onto the vector, otherwise, push
1880 std::vector<MachineBasicBlock*> DestBBs;
1882 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1883 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1884 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1886 if (Low.sle(TEI) && TEI.sle(High)) {
1887 DestBBs.push_back(I->BB);
1891 DestBBs.push_back(Default);
1895 // Update successor info. Add one edge to each unique successor.
1896 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1897 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1898 E = DestBBs.end(); I != E; ++I) {
1899 if (!SuccsHandled[(*I)->getNumber()]) {
1900 SuccsHandled[(*I)->getNumber()] = true;
1901 JumpTableBB->addSuccessor(*I);
1905 // Create a jump table index for this jump table.
1906 unsigned JTEncoding = TLI.getJumpTableEncoding();
1907 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1908 ->createJumpTableIndex(DestBBs);
1910 // Set the jump table information so that we can codegen it as a second
1911 // MachineBasicBlock
1912 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1913 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1914 if (CR.CaseBB == SwitchBB)
1915 visitJumpTableHeader(JT, JTH, SwitchBB);
1917 JTCases.push_back(JumpTableBlock(JTH, JT));
1922 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1924 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1925 CaseRecVector& WorkList,
1927 MachineBasicBlock *Default,
1928 MachineBasicBlock *SwitchBB) {
1929 // Get the MachineFunction which holds the current MBB. This is used when
1930 // inserting any additional MBBs necessary to represent the switch.
1931 MachineFunction *CurMF = FuncInfo.MF;
1933 // Figure out which block is immediately after the current one.
1934 MachineFunction::iterator BBI = CR.CaseBB;
1937 Case& FrontCase = *CR.Range.first;
1938 Case& BackCase = *(CR.Range.second-1);
1939 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1941 // Size is the number of Cases represented by this range.
1942 unsigned Size = CR.Range.second - CR.Range.first;
1944 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1945 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1947 CaseItr Pivot = CR.Range.first + Size/2;
1949 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1950 // (heuristically) allow us to emit JumpTable's later.
1951 APInt TSize(First.getBitWidth(), 0);
1952 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1956 APInt LSize = FrontCase.size();
1957 APInt RSize = TSize-LSize;
1958 DEBUG(dbgs() << "Selecting best pivot: \n"
1959 << "First: " << First << ", Last: " << Last <<'\n'
1960 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1961 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1963 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1964 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1965 APInt Range = ComputeRange(LEnd, RBegin);
1966 assert((Range - 2ULL).isNonNegative() &&
1967 "Invalid case distance");
1968 double LDensity = (double)LSize.roundToDouble() /
1969 (LEnd - First + 1ULL).roundToDouble();
1970 double RDensity = (double)RSize.roundToDouble() /
1971 (Last - RBegin + 1ULL).roundToDouble();
1972 double Metric = Range.logBase2()*(LDensity+RDensity);
1973 // Should always split in some non-trivial place
1974 DEBUG(dbgs() <<"=>Step\n"
1975 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1976 << "LDensity: " << LDensity
1977 << ", RDensity: " << RDensity << '\n'
1978 << "Metric: " << Metric << '\n');
1979 if (FMetric < Metric) {
1982 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1988 if (areJTsAllowed(TLI)) {
1989 // If our case is dense we *really* should handle it earlier!
1990 assert((FMetric > 0) && "Should handle dense range earlier!");
1992 Pivot = CR.Range.first + Size/2;
1995 CaseRange LHSR(CR.Range.first, Pivot);
1996 CaseRange RHSR(Pivot, CR.Range.second);
1997 Constant *C = Pivot->Low;
1998 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2000 // We know that we branch to the LHS if the Value being switched on is
2001 // less than the Pivot value, C. We use this to optimize our binary
2002 // tree a bit, by recognizing that if SV is greater than or equal to the
2003 // LHS's Case Value, and that Case Value is exactly one less than the
2004 // Pivot's Value, then we can branch directly to the LHS's Target,
2005 // rather than creating a leaf node for it.
2006 if ((LHSR.second - LHSR.first) == 1 &&
2007 LHSR.first->High == CR.GE &&
2008 cast<ConstantInt>(C)->getValue() ==
2009 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2010 TrueBB = LHSR.first->BB;
2012 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2013 CurMF->insert(BBI, TrueBB);
2014 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2016 // Put SV in a virtual register to make it available from the new blocks.
2017 ExportFromCurrentBlock(SV);
2020 // Similar to the optimization above, if the Value being switched on is
2021 // known to be less than the Constant CR.LT, and the current Case Value
2022 // is CR.LT - 1, then we can branch directly to the target block for
2023 // the current Case Value, rather than emitting a RHS leaf node for it.
2024 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2025 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2026 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2027 FalseBB = RHSR.first->BB;
2029 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2030 CurMF->insert(BBI, FalseBB);
2031 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2033 // Put SV in a virtual register to make it available from the new blocks.
2034 ExportFromCurrentBlock(SV);
2037 // Create a CaseBlock record representing a conditional branch to
2038 // the LHS node if the value being switched on SV is less than C.
2039 // Otherwise, branch to LHS.
2040 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2042 if (CR.CaseBB == SwitchBB)
2043 visitSwitchCase(CB, SwitchBB);
2045 SwitchCases.push_back(CB);
2050 /// handleBitTestsSwitchCase - if current case range has few destination and
2051 /// range span less, than machine word bitwidth, encode case range into series
2052 /// of masks and emit bit tests with these masks.
2053 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2054 CaseRecVector& WorkList,
2056 MachineBasicBlock* Default,
2057 MachineBasicBlock *SwitchBB){
2058 EVT PTy = TLI.getPointerTy();
2059 unsigned IntPtrBits = PTy.getSizeInBits();
2061 Case& FrontCase = *CR.Range.first;
2062 Case& BackCase = *(CR.Range.second-1);
2064 // Get the MachineFunction which holds the current MBB. This is used when
2065 // inserting any additional MBBs necessary to represent the switch.
2066 MachineFunction *CurMF = FuncInfo.MF;
2068 // If target does not have legal shift left, do not emit bit tests at all.
2069 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2073 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2075 // Single case counts one, case range - two.
2076 numCmps += (I->Low == I->High ? 1 : 2);
2079 // Count unique destinations
2080 SmallSet<MachineBasicBlock*, 4> Dests;
2081 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2082 Dests.insert(I->BB);
2083 if (Dests.size() > 3)
2084 // Don't bother the code below, if there are too much unique destinations
2087 DEBUG(dbgs() << "Total number of unique destinations: "
2088 << Dests.size() << '\n'
2089 << "Total number of comparisons: " << numCmps << '\n');
2091 // Compute span of values.
2092 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2093 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2094 APInt cmpRange = maxValue - minValue;
2096 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2097 << "Low bound: " << minValue << '\n'
2098 << "High bound: " << maxValue << '\n');
2100 if (cmpRange.uge(IntPtrBits) ||
2101 (!(Dests.size() == 1 && numCmps >= 3) &&
2102 !(Dests.size() == 2 && numCmps >= 5) &&
2103 !(Dests.size() >= 3 && numCmps >= 6)))
2106 DEBUG(dbgs() << "Emitting bit tests\n");
2107 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2109 // Optimize the case where all the case values fit in a
2110 // word without having to subtract minValue. In this case,
2111 // we can optimize away the subtraction.
2112 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2113 cmpRange = maxValue;
2115 lowBound = minValue;
2118 CaseBitsVector CasesBits;
2119 unsigned i, count = 0;
2121 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2122 MachineBasicBlock* Dest = I->BB;
2123 for (i = 0; i < count; ++i)
2124 if (Dest == CasesBits[i].BB)
2128 assert((count < 3) && "Too much destinations to test!");
2129 CasesBits.push_back(CaseBits(0, Dest, 0));
2133 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2134 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2136 uint64_t lo = (lowValue - lowBound).getZExtValue();
2137 uint64_t hi = (highValue - lowBound).getZExtValue();
2139 for (uint64_t j = lo; j <= hi; j++) {
2140 CasesBits[i].Mask |= 1ULL << j;
2141 CasesBits[i].Bits++;
2145 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2149 // Figure out which block is immediately after the current one.
2150 MachineFunction::iterator BBI = CR.CaseBB;
2153 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2155 DEBUG(dbgs() << "Cases:\n");
2156 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2157 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2158 << ", Bits: " << CasesBits[i].Bits
2159 << ", BB: " << CasesBits[i].BB << '\n');
2161 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2162 CurMF->insert(BBI, CaseBB);
2163 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2167 // Put SV in a virtual register to make it available from the new blocks.
2168 ExportFromCurrentBlock(SV);
2171 BitTestBlock BTB(lowBound, cmpRange, SV,
2172 -1U, (CR.CaseBB == SwitchBB),
2173 CR.CaseBB, Default, BTC);
2175 if (CR.CaseBB == SwitchBB)
2176 visitBitTestHeader(BTB, SwitchBB);
2178 BitTestCases.push_back(BTB);
2183 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2184 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2185 const SwitchInst& SI) {
2188 // Start with "simple" cases
2189 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2190 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2191 Cases.push_back(Case(SI.getSuccessorValue(i),
2192 SI.getSuccessorValue(i),
2195 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2197 // Merge case into clusters
2198 if (Cases.size() >= 2)
2199 // Must recompute end() each iteration because it may be
2200 // invalidated by erase if we hold on to it
2201 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2202 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2203 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2204 MachineBasicBlock* nextBB = J->BB;
2205 MachineBasicBlock* currentBB = I->BB;
2207 // If the two neighboring cases go to the same destination, merge them
2208 // into a single case.
2209 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2217 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2218 if (I->Low != I->High)
2219 // A range counts double, since it requires two compares.
2226 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2227 MachineBasicBlock *Last) {
2229 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2230 if (JTCases[i].first.HeaderBB == First)
2231 JTCases[i].first.HeaderBB = Last;
2233 // Update BitTestCases.
2234 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2235 if (BitTestCases[i].Parent == First)
2236 BitTestCases[i].Parent = Last;
2239 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2240 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2242 // Figure out which block is immediately after the current one.
2243 MachineBasicBlock *NextBlock = 0;
2244 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2246 // If there is only the default destination, branch to it if it is not the
2247 // next basic block. Otherwise, just fall through.
2248 if (SI.getNumOperands() == 2) {
2249 // Update machine-CFG edges.
2251 // If this is not a fall-through branch, emit the branch.
2252 SwitchMBB->addSuccessor(Default);
2253 if (Default != NextBlock)
2254 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2255 MVT::Other, getControlRoot(),
2256 DAG.getBasicBlock(Default)));
2261 // If there are any non-default case statements, create a vector of Cases
2262 // representing each one, and sort the vector so that we can efficiently
2263 // create a binary search tree from them.
2265 size_t numCmps = Clusterify(Cases, SI);
2266 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2267 << ". Total compares: " << numCmps << '\n');
2270 // Get the Value to be switched on and default basic blocks, which will be
2271 // inserted into CaseBlock records, representing basic blocks in the binary
2273 const Value *SV = SI.getOperand(0);
2275 // Push the initial CaseRec onto the worklist
2276 CaseRecVector WorkList;
2277 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2278 CaseRange(Cases.begin(),Cases.end())));
2280 while (!WorkList.empty()) {
2281 // Grab a record representing a case range to process off the worklist
2282 CaseRec CR = WorkList.back();
2283 WorkList.pop_back();
2285 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2288 // If the range has few cases (two or less) emit a series of specific
2290 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2293 // If the switch has more than 5 blocks, and at least 40% dense, and the
2294 // target supports indirect branches, then emit a jump table rather than
2295 // lowering the switch to a binary tree of conditional branches.
2296 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2299 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2300 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2301 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2305 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2306 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2308 // Update machine-CFG edges with unique successors.
2309 SmallVector<BasicBlock*, 32> succs;
2310 succs.reserve(I.getNumSuccessors());
2311 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2312 succs.push_back(I.getSuccessor(i));
2313 array_pod_sort(succs.begin(), succs.end());
2314 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2315 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2316 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2318 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2319 MVT::Other, getControlRoot(),
2320 getValue(I.getAddress())));
2323 void SelectionDAGBuilder::visitFSub(const User &I) {
2324 // -0.0 - X --> fneg
2325 const Type *Ty = I.getType();
2326 if (Ty->isVectorTy()) {
2327 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2328 const VectorType *DestTy = cast<VectorType>(I.getType());
2329 const Type *ElTy = DestTy->getElementType();
2330 unsigned VL = DestTy->getNumElements();
2331 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2332 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2334 SDValue Op2 = getValue(I.getOperand(1));
2335 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2336 Op2.getValueType(), Op2));
2342 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2343 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2344 SDValue Op2 = getValue(I.getOperand(1));
2345 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2346 Op2.getValueType(), Op2));
2350 visitBinary(I, ISD::FSUB);
2353 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2354 SDValue Op1 = getValue(I.getOperand(0));
2355 SDValue Op2 = getValue(I.getOperand(1));
2356 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2357 Op1.getValueType(), Op1, Op2));
2360 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2361 SDValue Op1 = getValue(I.getOperand(0));
2362 SDValue Op2 = getValue(I.getOperand(1));
2363 if (!I.getType()->isVectorTy() &&
2364 Op2.getValueType() != TLI.getShiftAmountTy()) {
2365 // If the operand is smaller than the shift count type, promote it.
2366 EVT PTy = TLI.getPointerTy();
2367 EVT STy = TLI.getShiftAmountTy();
2368 if (STy.bitsGT(Op2.getValueType()))
2369 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2370 TLI.getShiftAmountTy(), Op2);
2371 // If the operand is larger than the shift count type but the shift
2372 // count type has enough bits to represent any shift value, truncate
2373 // it now. This is a common case and it exposes the truncate to
2374 // optimization early.
2375 else if (STy.getSizeInBits() >=
2376 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2377 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2378 TLI.getShiftAmountTy(), Op2);
2379 // Otherwise we'll need to temporarily settle for some other
2380 // convenient type; type legalization will make adjustments as
2382 else if (PTy.bitsLT(Op2.getValueType()))
2383 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2384 TLI.getPointerTy(), Op2);
2385 else if (PTy.bitsGT(Op2.getValueType()))
2386 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2387 TLI.getPointerTy(), Op2);
2390 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2391 Op1.getValueType(), Op1, Op2));
2394 void SelectionDAGBuilder::visitICmp(const User &I) {
2395 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2396 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2397 predicate = IC->getPredicate();
2398 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2399 predicate = ICmpInst::Predicate(IC->getPredicate());
2400 SDValue Op1 = getValue(I.getOperand(0));
2401 SDValue Op2 = getValue(I.getOperand(1));
2402 ISD::CondCode Opcode = getICmpCondCode(predicate);
2404 EVT DestVT = TLI.getValueType(I.getType());
2405 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2408 void SelectionDAGBuilder::visitFCmp(const User &I) {
2409 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2410 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2411 predicate = FC->getPredicate();
2412 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2413 predicate = FCmpInst::Predicate(FC->getPredicate());
2414 SDValue Op1 = getValue(I.getOperand(0));
2415 SDValue Op2 = getValue(I.getOperand(1));
2416 ISD::CondCode Condition = getFCmpCondCode(predicate);
2417 EVT DestVT = TLI.getValueType(I.getType());
2418 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2421 void SelectionDAGBuilder::visitSelect(const User &I) {
2422 SmallVector<EVT, 4> ValueVTs;
2423 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2424 unsigned NumValues = ValueVTs.size();
2425 if (NumValues == 0) return;
2427 SmallVector<SDValue, 4> Values(NumValues);
2428 SDValue Cond = getValue(I.getOperand(0));
2429 SDValue TrueVal = getValue(I.getOperand(1));
2430 SDValue FalseVal = getValue(I.getOperand(2));
2432 for (unsigned i = 0; i != NumValues; ++i)
2433 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2434 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2436 SDValue(TrueVal.getNode(),
2437 TrueVal.getResNo() + i),
2438 SDValue(FalseVal.getNode(),
2439 FalseVal.getResNo() + i));
2441 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2442 DAG.getVTList(&ValueVTs[0], NumValues),
2443 &Values[0], NumValues));
2446 void SelectionDAGBuilder::visitTrunc(const User &I) {
2447 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2448 SDValue N = getValue(I.getOperand(0));
2449 EVT DestVT = TLI.getValueType(I.getType());
2450 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2453 void SelectionDAGBuilder::visitZExt(const User &I) {
2454 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2455 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2456 SDValue N = getValue(I.getOperand(0));
2457 EVT DestVT = TLI.getValueType(I.getType());
2458 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2461 void SelectionDAGBuilder::visitSExt(const User &I) {
2462 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2463 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2464 SDValue N = getValue(I.getOperand(0));
2465 EVT DestVT = TLI.getValueType(I.getType());
2466 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2469 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2470 // FPTrunc is never a no-op cast, no need to check
2471 SDValue N = getValue(I.getOperand(0));
2472 EVT DestVT = TLI.getValueType(I.getType());
2473 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2474 DestVT, N, DAG.getIntPtrConstant(0)));
2477 void SelectionDAGBuilder::visitFPExt(const User &I){
2478 // FPTrunc is never a no-op cast, no need to check
2479 SDValue N = getValue(I.getOperand(0));
2480 EVT DestVT = TLI.getValueType(I.getType());
2481 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2484 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2485 // FPToUI is never a no-op cast, no need to check
2486 SDValue N = getValue(I.getOperand(0));
2487 EVT DestVT = TLI.getValueType(I.getType());
2488 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2491 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2492 // FPToSI is never a no-op cast, no need to check
2493 SDValue N = getValue(I.getOperand(0));
2494 EVT DestVT = TLI.getValueType(I.getType());
2495 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2498 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2499 // UIToFP is never a no-op cast, no need to check
2500 SDValue N = getValue(I.getOperand(0));
2501 EVT DestVT = TLI.getValueType(I.getType());
2502 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2505 void SelectionDAGBuilder::visitSIToFP(const User &I){
2506 // SIToFP is never a no-op cast, no need to check
2507 SDValue N = getValue(I.getOperand(0));
2508 EVT DestVT = TLI.getValueType(I.getType());
2509 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2512 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2513 // What to do depends on the size of the integer and the size of the pointer.
2514 // We can either truncate, zero extend, or no-op, accordingly.
2515 SDValue N = getValue(I.getOperand(0));
2516 EVT DestVT = TLI.getValueType(I.getType());
2517 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2520 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2521 // What to do depends on the size of the integer and the size of the pointer.
2522 // We can either truncate, zero extend, or no-op, accordingly.
2523 SDValue N = getValue(I.getOperand(0));
2524 EVT DestVT = TLI.getValueType(I.getType());
2525 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2528 void SelectionDAGBuilder::visitBitCast(const User &I) {
2529 SDValue N = getValue(I.getOperand(0));
2530 EVT DestVT = TLI.getValueType(I.getType());
2532 // BitCast assures us that source and destination are the same size so this is
2533 // either a BIT_CONVERT or a no-op.
2534 if (DestVT != N.getValueType())
2535 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2536 DestVT, N)); // convert types.
2538 setValue(&I, N); // noop cast.
2541 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2542 SDValue InVec = getValue(I.getOperand(0));
2543 SDValue InVal = getValue(I.getOperand(1));
2544 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2546 getValue(I.getOperand(2)));
2547 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2548 TLI.getValueType(I.getType()),
2549 InVec, InVal, InIdx));
2552 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2553 SDValue InVec = getValue(I.getOperand(0));
2554 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2556 getValue(I.getOperand(1)));
2557 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2558 TLI.getValueType(I.getType()), InVec, InIdx));
2561 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2562 // from SIndx and increasing to the element length (undefs are allowed).
2563 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2564 unsigned MaskNumElts = Mask.size();
2565 for (unsigned i = 0; i != MaskNumElts; ++i)
2566 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2571 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2572 SmallVector<int, 8> Mask;
2573 SDValue Src1 = getValue(I.getOperand(0));
2574 SDValue Src2 = getValue(I.getOperand(1));
2576 // Convert the ConstantVector mask operand into an array of ints, with -1
2577 // representing undef values.
2578 SmallVector<Constant*, 8> MaskElts;
2579 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2580 unsigned MaskNumElts = MaskElts.size();
2581 for (unsigned i = 0; i != MaskNumElts; ++i) {
2582 if (isa<UndefValue>(MaskElts[i]))
2585 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2588 EVT VT = TLI.getValueType(I.getType());
2589 EVT SrcVT = Src1.getValueType();
2590 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2592 if (SrcNumElts == MaskNumElts) {
2593 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2598 // Normalize the shuffle vector since mask and vector length don't match.
2599 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2600 // Mask is longer than the source vectors and is a multiple of the source
2601 // vectors. We can use concatenate vector to make the mask and vectors
2603 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2604 // The shuffle is concatenating two vectors together.
2605 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2610 // Pad both vectors with undefs to make them the same length as the mask.
2611 unsigned NumConcat = MaskNumElts / SrcNumElts;
2612 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2613 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2614 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2616 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2617 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2621 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2622 getCurDebugLoc(), VT,
2623 &MOps1[0], NumConcat);
2624 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2625 getCurDebugLoc(), VT,
2626 &MOps2[0], NumConcat);
2628 // Readjust mask for new input vector length.
2629 SmallVector<int, 8> MappedOps;
2630 for (unsigned i = 0; i != MaskNumElts; ++i) {
2632 if (Idx < (int)SrcNumElts)
2633 MappedOps.push_back(Idx);
2635 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2638 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2643 if (SrcNumElts > MaskNumElts) {
2644 // Analyze the access pattern of the vector to see if we can extract
2645 // two subvectors and do the shuffle. The analysis is done by calculating
2646 // the range of elements the mask access on both vectors.
2647 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2648 int MaxRange[2] = {-1, -1};
2650 for (unsigned i = 0; i != MaskNumElts; ++i) {
2656 if (Idx >= (int)SrcNumElts) {
2660 if (Idx > MaxRange[Input])
2661 MaxRange[Input] = Idx;
2662 if (Idx < MinRange[Input])
2663 MinRange[Input] = Idx;
2666 // Check if the access is smaller than the vector size and can we find
2667 // a reasonable extract index.
2668 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2670 int StartIdx[2]; // StartIdx to extract from
2671 for (int Input=0; Input < 2; ++Input) {
2672 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2673 RangeUse[Input] = 0; // Unused
2674 StartIdx[Input] = 0;
2675 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2676 // Fits within range but we should see if we can find a good
2677 // start index that is a multiple of the mask length.
2678 if (MaxRange[Input] < (int)MaskNumElts) {
2679 RangeUse[Input] = 1; // Extract from beginning of the vector
2680 StartIdx[Input] = 0;
2682 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2683 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2684 StartIdx[Input] + MaskNumElts < SrcNumElts)
2685 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2690 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2691 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2694 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2695 // Extract appropriate subvector and generate a vector shuffle
2696 for (int Input=0; Input < 2; ++Input) {
2697 SDValue &Src = Input == 0 ? Src1 : Src2;
2698 if (RangeUse[Input] == 0)
2699 Src = DAG.getUNDEF(VT);
2701 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2702 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2705 // Calculate new mask.
2706 SmallVector<int, 8> MappedOps;
2707 for (unsigned i = 0; i != MaskNumElts; ++i) {
2710 MappedOps.push_back(Idx);
2711 else if (Idx < (int)SrcNumElts)
2712 MappedOps.push_back(Idx - StartIdx[0]);
2714 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2717 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2723 // We can't use either concat vectors or extract subvectors so fall back to
2724 // replacing the shuffle with extract and build vector.
2725 // to insert and build vector.
2726 EVT EltVT = VT.getVectorElementType();
2727 EVT PtrVT = TLI.getPointerTy();
2728 SmallVector<SDValue,8> Ops;
2729 for (unsigned i = 0; i != MaskNumElts; ++i) {
2731 Ops.push_back(DAG.getUNDEF(EltVT));
2736 if (Idx < (int)SrcNumElts)
2737 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2738 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2740 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2742 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2748 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2749 VT, &Ops[0], Ops.size()));
2752 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2753 const Value *Op0 = I.getOperand(0);
2754 const Value *Op1 = I.getOperand(1);
2755 const Type *AggTy = I.getType();
2756 const Type *ValTy = Op1->getType();
2757 bool IntoUndef = isa<UndefValue>(Op0);
2758 bool FromUndef = isa<UndefValue>(Op1);
2760 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2762 SmallVector<EVT, 4> AggValueVTs;
2763 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2764 SmallVector<EVT, 4> ValValueVTs;
2765 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2767 unsigned NumAggValues = AggValueVTs.size();
2768 unsigned NumValValues = ValValueVTs.size();
2769 SmallVector<SDValue, 4> Values(NumAggValues);
2771 SDValue Agg = getValue(Op0);
2772 SDValue Val = getValue(Op1);
2774 // Copy the beginning value(s) from the original aggregate.
2775 for (; i != LinearIndex; ++i)
2776 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2777 SDValue(Agg.getNode(), Agg.getResNo() + i);
2778 // Copy values from the inserted value(s).
2779 for (; i != LinearIndex + NumValValues; ++i)
2780 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2781 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2782 // Copy remaining value(s) from the original aggregate.
2783 for (; i != NumAggValues; ++i)
2784 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2785 SDValue(Agg.getNode(), Agg.getResNo() + i);
2787 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2788 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2789 &Values[0], NumAggValues));
2792 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2793 const Value *Op0 = I.getOperand(0);
2794 const Type *AggTy = Op0->getType();
2795 const Type *ValTy = I.getType();
2796 bool OutOfUndef = isa<UndefValue>(Op0);
2798 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2800 SmallVector<EVT, 4> ValValueVTs;
2801 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2803 unsigned NumValValues = ValValueVTs.size();
2804 SmallVector<SDValue, 4> Values(NumValValues);
2806 SDValue Agg = getValue(Op0);
2807 // Copy out the selected value(s).
2808 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2809 Values[i - LinearIndex] =
2811 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2812 SDValue(Agg.getNode(), Agg.getResNo() + i);
2814 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2815 DAG.getVTList(&ValValueVTs[0], NumValValues),
2816 &Values[0], NumValValues));
2819 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2820 SDValue N = getValue(I.getOperand(0));
2821 const Type *Ty = I.getOperand(0)->getType();
2823 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2825 const Value *Idx = *OI;
2826 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2827 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2830 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2831 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2832 DAG.getIntPtrConstant(Offset));
2835 Ty = StTy->getElementType(Field);
2837 Ty = cast<SequentialType>(Ty)->getElementType();
2839 // If this is a constant subscript, handle it quickly.
2840 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2841 if (CI->isZero()) continue;
2843 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2845 EVT PTy = TLI.getPointerTy();
2846 unsigned PtrBits = PTy.getSizeInBits();
2848 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2850 DAG.getConstant(Offs, MVT::i64));
2852 OffsVal = DAG.getIntPtrConstant(Offs);
2854 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2859 // N = N + Idx * ElementSize;
2860 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2861 TD->getTypeAllocSize(Ty));
2862 SDValue IdxN = getValue(Idx);
2864 // If the index is smaller or larger than intptr_t, truncate or extend
2866 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2868 // If this is a multiply by a power of two, turn it into a shl
2869 // immediately. This is a very common case.
2870 if (ElementSize != 1) {
2871 if (ElementSize.isPowerOf2()) {
2872 unsigned Amt = ElementSize.logBase2();
2873 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2874 N.getValueType(), IdxN,
2875 DAG.getConstant(Amt, TLI.getPointerTy()));
2877 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2878 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2879 N.getValueType(), IdxN, Scale);
2883 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2884 N.getValueType(), N, IdxN);
2891 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2892 // If this is a fixed sized alloca in the entry block of the function,
2893 // allocate it statically on the stack.
2894 if (FuncInfo.StaticAllocaMap.count(&I))
2895 return; // getValue will auto-populate this.
2897 const Type *Ty = I.getAllocatedType();
2898 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2900 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2903 SDValue AllocSize = getValue(I.getArraySize());
2905 EVT IntPtr = TLI.getPointerTy();
2906 if (AllocSize.getValueType() != IntPtr)
2907 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2909 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2911 DAG.getConstant(TySize, IntPtr));
2913 // Handle alignment. If the requested alignment is less than or equal to
2914 // the stack alignment, ignore it. If the size is greater than or equal to
2915 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2916 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2917 if (Align <= StackAlign)
2920 // Round the size of the allocation up to the stack alignment size
2921 // by add SA-1 to the size.
2922 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2923 AllocSize.getValueType(), AllocSize,
2924 DAG.getIntPtrConstant(StackAlign-1));
2926 // Mask out the low bits for alignment purposes.
2927 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2928 AllocSize.getValueType(), AllocSize,
2929 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2931 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2932 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2933 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2936 DAG.setRoot(DSA.getValue(1));
2938 // Inform the Frame Information that we have just allocated a variable-sized
2940 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2943 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2944 const Value *SV = I.getOperand(0);
2945 SDValue Ptr = getValue(SV);
2947 const Type *Ty = I.getType();
2949 bool isVolatile = I.isVolatile();
2950 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2951 unsigned Alignment = I.getAlignment();
2952 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
2954 SmallVector<EVT, 4> ValueVTs;
2955 SmallVector<uint64_t, 4> Offsets;
2956 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2957 unsigned NumValues = ValueVTs.size();
2962 bool ConstantMemory = false;
2963 if (I.isVolatile() || NumValues > MaxParallelChains)
2964 // Serialize volatile loads with other side effects.
2966 else if (AA->pointsToConstantMemory(
2967 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
2968 // Do not serialize (non-volatile) loads of constant memory with anything.
2969 Root = DAG.getEntryNode();
2970 ConstantMemory = true;
2972 // Do not serialize non-volatile loads against each other.
2973 Root = DAG.getRoot();
2976 SmallVector<SDValue, 4> Values(NumValues);
2977 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2979 EVT PtrVT = Ptr.getValueType();
2980 unsigned ChainI = 0;
2981 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2982 // Serializing loads here may result in excessive register pressure, and
2983 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2984 // could recover a bit by hoisting nodes upward in the chain by recognizing
2985 // they are side-effect free or do not alias. The optimizer should really
2986 // avoid this case by converting large object/array copies to llvm.memcpy
2987 // (MaxParallelChains should always remain as failsafe).
2988 if (ChainI == MaxParallelChains) {
2989 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2990 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2991 MVT::Other, &Chains[0], ChainI);
2995 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2997 DAG.getConstant(Offsets[i], PtrVT));
2998 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2999 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3000 isNonTemporal, Alignment, TBAAInfo);
3003 Chains[ChainI] = L.getValue(1);
3006 if (!ConstantMemory) {
3007 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3008 MVT::Other, &Chains[0], ChainI);
3012 PendingLoads.push_back(Chain);
3015 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3016 DAG.getVTList(&ValueVTs[0], NumValues),
3017 &Values[0], NumValues));
3020 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3021 const Value *SrcV = I.getOperand(0);
3022 const Value *PtrV = I.getOperand(1);
3024 SmallVector<EVT, 4> ValueVTs;
3025 SmallVector<uint64_t, 4> Offsets;
3026 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3027 unsigned NumValues = ValueVTs.size();
3031 // Get the lowered operands. Note that we do this after
3032 // checking if NumResults is zero, because with zero results
3033 // the operands won't have values in the map.
3034 SDValue Src = getValue(SrcV);
3035 SDValue Ptr = getValue(PtrV);
3037 SDValue Root = getRoot();
3038 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3040 EVT PtrVT = Ptr.getValueType();
3041 bool isVolatile = I.isVolatile();
3042 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3043 unsigned Alignment = I.getAlignment();
3044 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3046 unsigned ChainI = 0;
3047 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3048 // See visitLoad comments.
3049 if (ChainI == MaxParallelChains) {
3050 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3051 MVT::Other, &Chains[0], ChainI);
3055 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3056 DAG.getConstant(Offsets[i], PtrVT));
3057 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3058 SDValue(Src.getNode(), Src.getResNo() + i),
3059 Add, MachinePointerInfo(PtrV, Offsets[i]),
3060 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3061 Chains[ChainI] = St;
3064 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3065 MVT::Other, &Chains[0], ChainI);
3067 AssignOrderingToNode(StoreNode.getNode());
3068 DAG.setRoot(StoreNode);
3071 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3073 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3074 unsigned Intrinsic) {
3075 bool HasChain = !I.doesNotAccessMemory();
3076 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3078 // Build the operand list.
3079 SmallVector<SDValue, 8> Ops;
3080 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3082 // We don't need to serialize loads against other loads.
3083 Ops.push_back(DAG.getRoot());
3085 Ops.push_back(getRoot());
3089 // Info is set by getTgtMemInstrinsic
3090 TargetLowering::IntrinsicInfo Info;
3091 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3093 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3094 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3095 Info.opc == ISD::INTRINSIC_W_CHAIN)
3096 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3098 // Add all operands of the call to the operand list.
3099 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3100 SDValue Op = getValue(I.getArgOperand(i));
3101 assert(TLI.isTypeLegal(Op.getValueType()) &&
3102 "Intrinsic uses a non-legal type?");
3106 SmallVector<EVT, 4> ValueVTs;
3107 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3109 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3110 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3111 "Intrinsic uses a non-legal type?");
3116 ValueVTs.push_back(MVT::Other);
3118 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3122 if (IsTgtIntrinsic) {
3123 // This is target intrinsic that touches memory
3124 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3125 VTs, &Ops[0], Ops.size(),
3127 MachinePointerInfo(Info.ptrVal, Info.offset),
3128 Info.align, Info.vol,
3129 Info.readMem, Info.writeMem);
3130 } else if (!HasChain) {
3131 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3132 VTs, &Ops[0], Ops.size());
3133 } else if (!I.getType()->isVoidTy()) {
3134 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3135 VTs, &Ops[0], Ops.size());
3137 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3138 VTs, &Ops[0], Ops.size());
3142 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3144 PendingLoads.push_back(Chain);
3149 if (!I.getType()->isVoidTy()) {
3150 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3151 EVT VT = TLI.getValueType(PTy);
3152 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3155 setValue(&I, Result);
3159 /// GetSignificand - Get the significand and build it into a floating-point
3160 /// number with exponent of 1:
3162 /// Op = (Op & 0x007fffff) | 0x3f800000;
3164 /// where Op is the hexidecimal representation of floating point value.
3166 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3167 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3168 DAG.getConstant(0x007fffff, MVT::i32));
3169 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3170 DAG.getConstant(0x3f800000, MVT::i32));
3171 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3174 /// GetExponent - Get the exponent:
3176 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3178 /// where Op is the hexidecimal representation of floating point value.
3180 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3182 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3183 DAG.getConstant(0x7f800000, MVT::i32));
3184 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3185 DAG.getConstant(23, TLI.getPointerTy()));
3186 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3187 DAG.getConstant(127, MVT::i32));
3188 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3191 /// getF32Constant - Get 32-bit floating point constant.
3193 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3194 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3197 /// Inlined utility function to implement binary input atomic intrinsics for
3198 /// visitIntrinsicCall: I is a call instruction
3199 /// Op is the associated NodeType for I
3201 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3203 SDValue Root = getRoot();
3205 DAG.getAtomic(Op, getCurDebugLoc(),
3206 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3208 getValue(I.getArgOperand(0)),
3209 getValue(I.getArgOperand(1)),
3210 I.getArgOperand(0));
3212 DAG.setRoot(L.getValue(1));
3216 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3218 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3219 SDValue Op1 = getValue(I.getArgOperand(0));
3220 SDValue Op2 = getValue(I.getArgOperand(1));
3222 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3223 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3227 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3228 /// limited-precision mode.
3230 SelectionDAGBuilder::visitExp(const CallInst &I) {
3232 DebugLoc dl = getCurDebugLoc();
3234 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3235 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3236 SDValue Op = getValue(I.getArgOperand(0));
3238 // Put the exponent in the right bit position for later addition to the
3241 // #define LOG2OFe 1.4426950f
3242 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3243 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3244 getF32Constant(DAG, 0x3fb8aa3b));
3245 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3247 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3248 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3249 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3251 // IntegerPartOfX <<= 23;
3252 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3253 DAG.getConstant(23, TLI.getPointerTy()));
3255 if (LimitFloatPrecision <= 6) {
3256 // For floating-point precision of 6:
3258 // TwoToFractionalPartOfX =
3260 // (0.735607626f + 0.252464424f * x) * x;
3262 // error 0.0144103317, which is 6 bits
3263 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3264 getF32Constant(DAG, 0x3e814304));
3265 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3266 getF32Constant(DAG, 0x3f3c50c8));
3267 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3268 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3269 getF32Constant(DAG, 0x3f7f5e7e));
3270 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3272 // Add the exponent into the result in integer domain.
3273 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3274 TwoToFracPartOfX, IntegerPartOfX);
3276 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3277 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3278 // For floating-point precision of 12:
3280 // TwoToFractionalPartOfX =
3283 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3285 // 0.000107046256 error, which is 13 to 14 bits
3286 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3287 getF32Constant(DAG, 0x3da235e3));
3288 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3289 getF32Constant(DAG, 0x3e65b8f3));
3290 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3291 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3292 getF32Constant(DAG, 0x3f324b07));
3293 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3294 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3295 getF32Constant(DAG, 0x3f7ff8fd));
3296 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3298 // Add the exponent into the result in integer domain.
3299 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3300 TwoToFracPartOfX, IntegerPartOfX);
3302 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3303 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3304 // For floating-point precision of 18:
3306 // TwoToFractionalPartOfX =
3310 // (0.554906021e-1f +
3311 // (0.961591928e-2f +
3312 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3314 // error 2.47208000*10^(-7), which is better than 18 bits
3315 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3316 getF32Constant(DAG, 0x3924b03e));
3317 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3318 getF32Constant(DAG, 0x3ab24b87));
3319 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3320 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3321 getF32Constant(DAG, 0x3c1d8c17));
3322 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3323 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3324 getF32Constant(DAG, 0x3d634a1d));
3325 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3326 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3327 getF32Constant(DAG, 0x3e75fe14));
3328 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3329 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3330 getF32Constant(DAG, 0x3f317234));
3331 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3332 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3333 getF32Constant(DAG, 0x3f800000));
3334 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3337 // Add the exponent into the result in integer domain.
3338 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3339 TwoToFracPartOfX, IntegerPartOfX);
3341 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3344 // No special expansion.
3345 result = DAG.getNode(ISD::FEXP, dl,
3346 getValue(I.getArgOperand(0)).getValueType(),
3347 getValue(I.getArgOperand(0)));
3350 setValue(&I, result);
3353 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3354 /// limited-precision mode.
3356 SelectionDAGBuilder::visitLog(const CallInst &I) {
3358 DebugLoc dl = getCurDebugLoc();
3360 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3361 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3362 SDValue Op = getValue(I.getArgOperand(0));
3363 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3365 // Scale the exponent by log(2) [0.69314718f].
3366 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3367 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3368 getF32Constant(DAG, 0x3f317218));
3370 // Get the significand and build it into a floating-point number with
3372 SDValue X = GetSignificand(DAG, Op1, dl);
3374 if (LimitFloatPrecision <= 6) {
3375 // For floating-point precision of 6:
3379 // (1.4034025f - 0.23903021f * x) * x;
3381 // error 0.0034276066, which is better than 8 bits
3382 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3383 getF32Constant(DAG, 0xbe74c456));
3384 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3385 getF32Constant(DAG, 0x3fb3a2b1));
3386 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3387 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3388 getF32Constant(DAG, 0x3f949a29));
3390 result = DAG.getNode(ISD::FADD, dl,
3391 MVT::f32, LogOfExponent, LogOfMantissa);
3392 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3393 // For floating-point precision of 12:
3399 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3401 // error 0.000061011436, which is 14 bits
3402 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3403 getF32Constant(DAG, 0xbd67b6d6));
3404 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3405 getF32Constant(DAG, 0x3ee4f4b8));
3406 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3407 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3408 getF32Constant(DAG, 0x3fbc278b));
3409 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3410 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3411 getF32Constant(DAG, 0x40348e95));
3412 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3413 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3414 getF32Constant(DAG, 0x3fdef31a));
3416 result = DAG.getNode(ISD::FADD, dl,
3417 MVT::f32, LogOfExponent, LogOfMantissa);
3418 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3419 // For floating-point precision of 18:
3427 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3429 // error 0.0000023660568, which is better than 18 bits
3430 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3431 getF32Constant(DAG, 0xbc91e5ac));
3432 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3433 getF32Constant(DAG, 0x3e4350aa));
3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3435 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3436 getF32Constant(DAG, 0x3f60d3e3));
3437 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3438 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3439 getF32Constant(DAG, 0x4011cdf0));
3440 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3441 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3442 getF32Constant(DAG, 0x406cfd1c));
3443 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3444 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3445 getF32Constant(DAG, 0x408797cb));
3446 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3447 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3448 getF32Constant(DAG, 0x4006dcab));
3450 result = DAG.getNode(ISD::FADD, dl,
3451 MVT::f32, LogOfExponent, LogOfMantissa);
3454 // No special expansion.
3455 result = DAG.getNode(ISD::FLOG, dl,
3456 getValue(I.getArgOperand(0)).getValueType(),
3457 getValue(I.getArgOperand(0)));
3460 setValue(&I, result);
3463 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3464 /// limited-precision mode.
3466 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3468 DebugLoc dl = getCurDebugLoc();
3470 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3471 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3472 SDValue Op = getValue(I.getArgOperand(0));
3473 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3475 // Get the exponent.
3476 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3478 // Get the significand and build it into a floating-point number with
3480 SDValue X = GetSignificand(DAG, Op1, dl);
3482 // Different possible minimax approximations of significand in
3483 // floating-point for various degrees of accuracy over [1,2].
3484 if (LimitFloatPrecision <= 6) {
3485 // For floating-point precision of 6:
3487 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3489 // error 0.0049451742, which is more than 7 bits
3490 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3491 getF32Constant(DAG, 0xbeb08fe0));
3492 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3493 getF32Constant(DAG, 0x40019463));
3494 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3495 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3496 getF32Constant(DAG, 0x3fd6633d));
3498 result = DAG.getNode(ISD::FADD, dl,
3499 MVT::f32, LogOfExponent, Log2ofMantissa);
3500 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3501 // For floating-point precision of 12:
3507 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3509 // error 0.0000876136000, which is better than 13 bits
3510 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3511 getF32Constant(DAG, 0xbda7262e));
3512 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3513 getF32Constant(DAG, 0x3f25280b));
3514 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3515 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3516 getF32Constant(DAG, 0x4007b923));
3517 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3518 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3519 getF32Constant(DAG, 0x40823e2f));
3520 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3521 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3522 getF32Constant(DAG, 0x4020d29c));
3524 result = DAG.getNode(ISD::FADD, dl,
3525 MVT::f32, LogOfExponent, Log2ofMantissa);
3526 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3527 // For floating-point precision of 18:
3536 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3538 // error 0.0000018516, which is better than 18 bits
3539 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3540 getF32Constant(DAG, 0xbcd2769e));
3541 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3542 getF32Constant(DAG, 0x3e8ce0b9));
3543 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3544 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3545 getF32Constant(DAG, 0x3fa22ae7));
3546 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3547 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3548 getF32Constant(DAG, 0x40525723));
3549 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3550 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3551 getF32Constant(DAG, 0x40aaf200));
3552 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3553 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3554 getF32Constant(DAG, 0x40c39dad));
3555 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3556 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3557 getF32Constant(DAG, 0x4042902c));
3559 result = DAG.getNode(ISD::FADD, dl,
3560 MVT::f32, LogOfExponent, Log2ofMantissa);
3563 // No special expansion.
3564 result = DAG.getNode(ISD::FLOG2, dl,
3565 getValue(I.getArgOperand(0)).getValueType(),
3566 getValue(I.getArgOperand(0)));
3569 setValue(&I, result);
3572 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3573 /// limited-precision mode.
3575 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3577 DebugLoc dl = getCurDebugLoc();
3579 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3580 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3581 SDValue Op = getValue(I.getArgOperand(0));
3582 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3584 // Scale the exponent by log10(2) [0.30102999f].
3585 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3586 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3587 getF32Constant(DAG, 0x3e9a209a));
3589 // Get the significand and build it into a floating-point number with
3591 SDValue X = GetSignificand(DAG, Op1, dl);
3593 if (LimitFloatPrecision <= 6) {
3594 // For floating-point precision of 6:
3596 // Log10ofMantissa =
3598 // (0.60948995f - 0.10380950f * x) * x;
3600 // error 0.0014886165, which is 6 bits
3601 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3602 getF32Constant(DAG, 0xbdd49a13));
3603 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3604 getF32Constant(DAG, 0x3f1c0789));
3605 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3606 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3607 getF32Constant(DAG, 0x3f011300));
3609 result = DAG.getNode(ISD::FADD, dl,
3610 MVT::f32, LogOfExponent, Log10ofMantissa);
3611 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3612 // For floating-point precision of 12:
3614 // Log10ofMantissa =
3617 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3619 // error 0.00019228036, which is better than 12 bits
3620 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3621 getF32Constant(DAG, 0x3d431f31));
3622 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3623 getF32Constant(DAG, 0x3ea21fb2));
3624 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3625 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3626 getF32Constant(DAG, 0x3f6ae232));
3627 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3628 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3629 getF32Constant(DAG, 0x3f25f7c3));
3631 result = DAG.getNode(ISD::FADD, dl,
3632 MVT::f32, LogOfExponent, Log10ofMantissa);
3633 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3634 // For floating-point precision of 18:
3636 // Log10ofMantissa =
3641 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3643 // error 0.0000037995730, which is better than 18 bits
3644 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3645 getF32Constant(DAG, 0x3c5d51ce));
3646 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3647 getF32Constant(DAG, 0x3e00685a));
3648 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3649 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3650 getF32Constant(DAG, 0x3efb6798));
3651 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3652 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3653 getF32Constant(DAG, 0x3f88d192));
3654 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3655 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3656 getF32Constant(DAG, 0x3fc4316c));
3657 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3658 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3659 getF32Constant(DAG, 0x3f57ce70));
3661 result = DAG.getNode(ISD::FADD, dl,
3662 MVT::f32, LogOfExponent, Log10ofMantissa);
3665 // No special expansion.
3666 result = DAG.getNode(ISD::FLOG10, dl,
3667 getValue(I.getArgOperand(0)).getValueType(),
3668 getValue(I.getArgOperand(0)));
3671 setValue(&I, result);
3674 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3675 /// limited-precision mode.
3677 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3679 DebugLoc dl = getCurDebugLoc();
3681 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3682 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3683 SDValue Op = getValue(I.getArgOperand(0));
3685 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3687 // FractionalPartOfX = x - (float)IntegerPartOfX;
3688 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3689 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3691 // IntegerPartOfX <<= 23;
3692 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3693 DAG.getConstant(23, TLI.getPointerTy()));
3695 if (LimitFloatPrecision <= 6) {
3696 // For floating-point precision of 6:
3698 // TwoToFractionalPartOfX =
3700 // (0.735607626f + 0.252464424f * x) * x;
3702 // error 0.0144103317, which is 6 bits
3703 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3704 getF32Constant(DAG, 0x3e814304));
3705 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3706 getF32Constant(DAG, 0x3f3c50c8));
3707 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3708 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3709 getF32Constant(DAG, 0x3f7f5e7e));
3710 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3711 SDValue TwoToFractionalPartOfX =
3712 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3714 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3715 MVT::f32, TwoToFractionalPartOfX);
3716 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3717 // For floating-point precision of 12:
3719 // TwoToFractionalPartOfX =
3722 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3724 // error 0.000107046256, which is 13 to 14 bits
3725 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3726 getF32Constant(DAG, 0x3da235e3));
3727 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3728 getF32Constant(DAG, 0x3e65b8f3));
3729 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3730 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3731 getF32Constant(DAG, 0x3f324b07));
3732 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3733 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3734 getF32Constant(DAG, 0x3f7ff8fd));
3735 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3736 SDValue TwoToFractionalPartOfX =
3737 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3739 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3740 MVT::f32, TwoToFractionalPartOfX);
3741 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3742 // For floating-point precision of 18:
3744 // TwoToFractionalPartOfX =
3748 // (0.554906021e-1f +
3749 // (0.961591928e-2f +
3750 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3751 // error 2.47208000*10^(-7), which is better than 18 bits
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0x3924b03e));
3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3ab24b87));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x3c1d8c17));
3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3760 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3761 getF32Constant(DAG, 0x3d634a1d));
3762 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3763 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3764 getF32Constant(DAG, 0x3e75fe14));
3765 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3766 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3767 getF32Constant(DAG, 0x3f317234));
3768 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3769 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3770 getF32Constant(DAG, 0x3f800000));
3771 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3772 SDValue TwoToFractionalPartOfX =
3773 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3775 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3776 MVT::f32, TwoToFractionalPartOfX);
3779 // No special expansion.
3780 result = DAG.getNode(ISD::FEXP2, dl,
3781 getValue(I.getArgOperand(0)).getValueType(),
3782 getValue(I.getArgOperand(0)));
3785 setValue(&I, result);
3788 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3789 /// limited-precision mode with x == 10.0f.
3791 SelectionDAGBuilder::visitPow(const CallInst &I) {
3793 const Value *Val = I.getArgOperand(0);
3794 DebugLoc dl = getCurDebugLoc();
3795 bool IsExp10 = false;
3797 if (getValue(Val).getValueType() == MVT::f32 &&
3798 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3799 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3800 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3801 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3803 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3808 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3809 SDValue Op = getValue(I.getArgOperand(1));
3811 // Put the exponent in the right bit position for later addition to the
3814 // #define LOG2OF10 3.3219281f
3815 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3816 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3817 getF32Constant(DAG, 0x40549a78));
3818 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3820 // FractionalPartOfX = x - (float)IntegerPartOfX;
3821 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3822 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3824 // IntegerPartOfX <<= 23;
3825 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3826 DAG.getConstant(23, TLI.getPointerTy()));
3828 if (LimitFloatPrecision <= 6) {
3829 // For floating-point precision of 6:
3831 // twoToFractionalPartOfX =
3833 // (0.735607626f + 0.252464424f * x) * x;
3835 // error 0.0144103317, which is 6 bits
3836 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3837 getF32Constant(DAG, 0x3e814304));
3838 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3839 getF32Constant(DAG, 0x3f3c50c8));
3840 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3841 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3842 getF32Constant(DAG, 0x3f7f5e7e));
3843 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3844 SDValue TwoToFractionalPartOfX =
3845 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3847 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3848 MVT::f32, TwoToFractionalPartOfX);
3849 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3850 // For floating-point precision of 12:
3852 // TwoToFractionalPartOfX =
3855 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3857 // error 0.000107046256, which is 13 to 14 bits
3858 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3859 getF32Constant(DAG, 0x3da235e3));
3860 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3861 getF32Constant(DAG, 0x3e65b8f3));
3862 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3863 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3864 getF32Constant(DAG, 0x3f324b07));
3865 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3866 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3867 getF32Constant(DAG, 0x3f7ff8fd));
3868 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3869 SDValue TwoToFractionalPartOfX =
3870 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3872 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3873 MVT::f32, TwoToFractionalPartOfX);
3874 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3875 // For floating-point precision of 18:
3877 // TwoToFractionalPartOfX =
3881 // (0.554906021e-1f +
3882 // (0.961591928e-2f +
3883 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3884 // error 2.47208000*10^(-7), which is better than 18 bits
3885 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3886 getF32Constant(DAG, 0x3924b03e));
3887 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3888 getF32Constant(DAG, 0x3ab24b87));
3889 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3890 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3891 getF32Constant(DAG, 0x3c1d8c17));
3892 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3893 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3894 getF32Constant(DAG, 0x3d634a1d));
3895 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3896 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3897 getF32Constant(DAG, 0x3e75fe14));
3898 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3899 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3900 getF32Constant(DAG, 0x3f317234));
3901 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3902 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3903 getF32Constant(DAG, 0x3f800000));
3904 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3905 SDValue TwoToFractionalPartOfX =
3906 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3908 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3909 MVT::f32, TwoToFractionalPartOfX);
3912 // No special expansion.
3913 result = DAG.getNode(ISD::FPOW, dl,
3914 getValue(I.getArgOperand(0)).getValueType(),
3915 getValue(I.getArgOperand(0)),
3916 getValue(I.getArgOperand(1)));
3919 setValue(&I, result);
3923 /// ExpandPowI - Expand a llvm.powi intrinsic.
3924 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3925 SelectionDAG &DAG) {
3926 // If RHS is a constant, we can expand this out to a multiplication tree,
3927 // otherwise we end up lowering to a call to __powidf2 (for example). When
3928 // optimizing for size, we only want to do this if the expansion would produce
3929 // a small number of multiplies, otherwise we do the full expansion.
3930 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3931 // Get the exponent as a positive value.
3932 unsigned Val = RHSC->getSExtValue();
3933 if ((int)Val < 0) Val = -Val;
3935 // powi(x, 0) -> 1.0
3937 return DAG.getConstantFP(1.0, LHS.getValueType());
3939 const Function *F = DAG.getMachineFunction().getFunction();
3940 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3941 // If optimizing for size, don't insert too many multiplies. This
3942 // inserts up to 5 multiplies.
3943 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3944 // We use the simple binary decomposition method to generate the multiply
3945 // sequence. There are more optimal ways to do this (for example,
3946 // powi(x,15) generates one more multiply than it should), but this has
3947 // the benefit of being both really simple and much better than a libcall.
3948 SDValue Res; // Logically starts equal to 1.0
3949 SDValue CurSquare = LHS;
3953 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3955 Res = CurSquare; // 1.0*CurSquare.
3958 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3959 CurSquare, CurSquare);
3963 // If the original was negative, invert the result, producing 1/(x*x*x).
3964 if (RHSC->getSExtValue() < 0)
3965 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3966 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3971 // Otherwise, expand to a libcall.
3972 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3975 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3976 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3977 /// At the end of instruction selection, they will be inserted to the entry BB.
3979 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
3982 const Argument *Arg = dyn_cast<Argument>(V);
3986 MachineFunction &MF = DAG.getMachineFunction();
3987 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
3988 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3990 // Ignore inlined function arguments here.
3991 DIVariable DV(Variable);
3992 if (DV.isInlinedFnArgument(MF.getFunction()))
3995 MachineBasicBlock *MBB = FuncInfo.MBB;
3996 if (MBB != &MF.front())
4000 if (Arg->hasByValAttr()) {
4001 // Byval arguments' frame index is recorded during argument lowering.
4002 // Use this info directly.
4003 Reg = TRI->getFrameRegister(MF);
4004 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4005 // If byval argument ofset is not recorded then ignore this.
4010 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4011 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4012 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4013 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4014 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4021 // Check if ValueMap has reg number.
4022 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4023 if (VMI != FuncInfo.ValueMap.end())
4027 if (!Reg && N.getNode()) {
4028 // Check if frame index is available.
4029 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4030 if (FrameIndexSDNode *FINode =
4031 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4032 Reg = TRI->getFrameRegister(MF);
4033 Offset = FINode->getIndex();
4040 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4041 TII->get(TargetOpcode::DBG_VALUE))
4042 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4043 FuncInfo.ArgDbgValues.push_back(&*MIB);
4047 // VisualStudio defines setjmp as _setjmp
4048 #if defined(_MSC_VER) && defined(setjmp) && \
4049 !defined(setjmp_undefined_for_msvc)
4050 # pragma push_macro("setjmp")
4052 # define setjmp_undefined_for_msvc
4055 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4056 /// we want to emit this as a call to a named external function, return the name
4057 /// otherwise lower it and return null.
4059 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4060 DebugLoc dl = getCurDebugLoc();
4063 switch (Intrinsic) {
4065 // By default, turn this into a target intrinsic node.
4066 visitTargetIntrinsic(I, Intrinsic);
4068 case Intrinsic::vastart: visitVAStart(I); return 0;
4069 case Intrinsic::vaend: visitVAEnd(I); return 0;
4070 case Intrinsic::vacopy: visitVACopy(I); return 0;
4071 case Intrinsic::returnaddress:
4072 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4073 getValue(I.getArgOperand(0))));
4075 case Intrinsic::frameaddress:
4076 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4077 getValue(I.getArgOperand(0))));
4079 case Intrinsic::setjmp:
4080 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4081 case Intrinsic::longjmp:
4082 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4083 case Intrinsic::memcpy: {
4084 // Assert for address < 256 since we support only user defined address
4086 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4088 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4090 "Unknown address space");
4091 SDValue Op1 = getValue(I.getArgOperand(0));
4092 SDValue Op2 = getValue(I.getArgOperand(1));
4093 SDValue Op3 = getValue(I.getArgOperand(2));
4094 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4095 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4096 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4097 MachinePointerInfo(I.getArgOperand(0)),
4098 MachinePointerInfo(I.getArgOperand(1))));
4101 case Intrinsic::memset: {
4102 // Assert for address < 256 since we support only user defined address
4104 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4106 "Unknown address space");
4107 SDValue Op1 = getValue(I.getArgOperand(0));
4108 SDValue Op2 = getValue(I.getArgOperand(1));
4109 SDValue Op3 = getValue(I.getArgOperand(2));
4110 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4111 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4112 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4113 MachinePointerInfo(I.getArgOperand(0))));
4116 case Intrinsic::memmove: {
4117 // Assert for address < 256 since we support only user defined address
4119 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4121 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4123 "Unknown address space");
4124 SDValue Op1 = getValue(I.getArgOperand(0));
4125 SDValue Op2 = getValue(I.getArgOperand(1));
4126 SDValue Op3 = getValue(I.getArgOperand(2));
4127 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4128 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4129 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4130 MachinePointerInfo(I.getArgOperand(0)),
4131 MachinePointerInfo(I.getArgOperand(1))));
4134 case Intrinsic::dbg_declare: {
4135 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4136 MDNode *Variable = DI.getVariable();
4137 const Value *Address = DI.getAddress();
4138 if (!Address || !DIVariable(DI.getVariable()).Verify())
4141 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4142 // but do not always have a corresponding SDNode built. The SDNodeOrder
4143 // absolute, but not relative, values are different depending on whether
4144 // debug info exists.
4147 // Check if address has undef value.
4148 if (isa<UndefValue>(Address) ||
4149 (Address->use_empty() && !isa<Argument>(Address))) {
4151 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4152 0, dl, SDNodeOrder);
4153 DAG.AddDbgValue(SDV, 0, false);
4157 SDValue &N = NodeMap[Address];
4158 if (!N.getNode() && isa<Argument>(Address))
4159 // Check unused arguments map.
4160 N = UnusedArgNodeMap[Address];
4163 // Parameters are handled specially.
4165 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4166 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4167 Address = BCI->getOperand(0);
4168 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4170 if (isParameter && !AI) {
4171 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4173 // Byval parameter. We have a frame index at this point.
4174 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4175 0, dl, SDNodeOrder);
4177 // Can't do anything with other non-AI cases yet. This might be a
4178 // parameter of a callee function that got inlined, for example.
4181 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4182 0, dl, SDNodeOrder);
4184 // Can't do anything with other non-AI cases yet.
4186 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4188 // If Address is an argument then try to emit its dbg value using
4189 // virtual register info from the FuncInfo.ValueMap.
4190 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4191 // If variable is pinned by a alloca in dominating bb then
4192 // use StaticAllocaMap.
4193 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4194 if (AI->getParent() != DI.getParent()) {
4195 DenseMap<const AllocaInst*, int>::iterator SI =
4196 FuncInfo.StaticAllocaMap.find(AI);
4197 if (SI != FuncInfo.StaticAllocaMap.end()) {
4198 SDV = DAG.getDbgValue(Variable, SI->second,
4199 0, dl, SDNodeOrder);
4200 DAG.AddDbgValue(SDV, 0, false);
4205 // Otherwise add undef to help track missing debug info.
4206 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4207 0, dl, SDNodeOrder);
4208 DAG.AddDbgValue(SDV, 0, false);
4213 case Intrinsic::dbg_value: {
4214 const DbgValueInst &DI = cast<DbgValueInst>(I);
4215 if (!DIVariable(DI.getVariable()).Verify())
4218 MDNode *Variable = DI.getVariable();
4219 uint64_t Offset = DI.getOffset();
4220 const Value *V = DI.getValue();
4224 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4225 // but do not always have a corresponding SDNode built. The SDNodeOrder
4226 // absolute, but not relative, values are different depending on whether
4227 // debug info exists.
4230 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4231 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4232 DAG.AddDbgValue(SDV, 0, false);
4234 // Do not use getValue() in here; we don't want to generate code at
4235 // this point if it hasn't been done yet.
4236 SDValue N = NodeMap[V];
4237 if (!N.getNode() && isa<Argument>(V))
4238 // Check unused arguments map.
4239 N = UnusedArgNodeMap[V];
4241 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4242 SDV = DAG.getDbgValue(Variable, N.getNode(),
4243 N.getResNo(), Offset, dl, SDNodeOrder);
4244 DAG.AddDbgValue(SDV, N.getNode(), false);
4246 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4247 // Do not call getValue(V) yet, as we don't want to generate code.
4248 // Remember it for later.
4249 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4250 DanglingDebugInfoMap[V] = DDI;
4252 // We may expand this to cover more cases. One case where we have no
4253 // data available is an unreferenced parameter; we need this fallback.
4254 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
4255 Offset, dl, SDNodeOrder);
4256 DAG.AddDbgValue(SDV, 0, false);
4260 // Build a debug info table entry.
4261 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4262 V = BCI->getOperand(0);
4263 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4264 // Don't handle byval struct arguments or VLAs, for example.
4267 DenseMap<const AllocaInst*, int>::iterator SI =
4268 FuncInfo.StaticAllocaMap.find(AI);
4269 if (SI == FuncInfo.StaticAllocaMap.end())
4271 int FI = SI->second;
4273 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4274 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4275 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4278 case Intrinsic::eh_exception: {
4279 // Insert the EXCEPTIONADDR instruction.
4280 assert(FuncInfo.MBB->isLandingPad() &&
4281 "Call to eh.exception not in landing pad!");
4282 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4284 Ops[0] = DAG.getRoot();
4285 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4287 DAG.setRoot(Op.getValue(1));
4291 case Intrinsic::eh_selector: {
4292 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4293 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4294 if (CallMBB->isLandingPad())
4295 AddCatchInfo(I, &MMI, CallMBB);
4298 FuncInfo.CatchInfoLost.insert(&I);
4300 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4301 unsigned Reg = TLI.getExceptionSelectorRegister();
4302 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4305 // Insert the EHSELECTION instruction.
4306 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4308 Ops[0] = getValue(I.getArgOperand(0));
4310 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4311 DAG.setRoot(Op.getValue(1));
4312 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4316 case Intrinsic::eh_typeid_for: {
4317 // Find the type id for the given typeinfo.
4318 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4319 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4320 Res = DAG.getConstant(TypeID, MVT::i32);
4325 case Intrinsic::eh_return_i32:
4326 case Intrinsic::eh_return_i64:
4327 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4328 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4331 getValue(I.getArgOperand(0)),
4332 getValue(I.getArgOperand(1))));
4334 case Intrinsic::eh_unwind_init:
4335 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4337 case Intrinsic::eh_dwarf_cfa: {
4338 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4339 TLI.getPointerTy());
4340 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4342 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4343 TLI.getPointerTy()),
4345 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4347 DAG.getConstant(0, TLI.getPointerTy()));
4348 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4352 case Intrinsic::eh_sjlj_callsite: {
4353 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4354 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4355 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4356 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4358 MMI.setCurrentCallSite(CI->getZExtValue());
4361 case Intrinsic::eh_sjlj_setjmp: {
4362 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4363 getValue(I.getArgOperand(0))));
4366 case Intrinsic::eh_sjlj_longjmp: {
4367 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4368 getRoot(), getValue(I.getArgOperand(0))));
4371 case Intrinsic::eh_sjlj_dispatch_setup: {
4372 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4373 getRoot(), getValue(I.getArgOperand(0))));
4377 case Intrinsic::x86_mmx_pslli_w:
4378 case Intrinsic::x86_mmx_pslli_d:
4379 case Intrinsic::x86_mmx_pslli_q:
4380 case Intrinsic::x86_mmx_psrli_w:
4381 case Intrinsic::x86_mmx_psrli_d:
4382 case Intrinsic::x86_mmx_psrli_q:
4383 case Intrinsic::x86_mmx_psrai_w:
4384 case Intrinsic::x86_mmx_psrai_d: {
4385 SDValue ShAmt = getValue(I.getArgOperand(1));
4386 if (isa<ConstantSDNode>(ShAmt)) {
4387 visitTargetIntrinsic(I, Intrinsic);
4390 unsigned NewIntrinsic = 0;
4391 EVT ShAmtVT = MVT::v2i32;
4392 switch (Intrinsic) {
4393 case Intrinsic::x86_mmx_pslli_w:
4394 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4396 case Intrinsic::x86_mmx_pslli_d:
4397 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4399 case Intrinsic::x86_mmx_pslli_q:
4400 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4402 case Intrinsic::x86_mmx_psrli_w:
4403 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4405 case Intrinsic::x86_mmx_psrli_d:
4406 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4408 case Intrinsic::x86_mmx_psrli_q:
4409 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4411 case Intrinsic::x86_mmx_psrai_w:
4412 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4414 case Intrinsic::x86_mmx_psrai_d:
4415 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4417 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4420 // The vector shift intrinsics with scalars uses 32b shift amounts but
4421 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4423 // We must do this early because v2i32 is not a legal type.
4424 DebugLoc dl = getCurDebugLoc();
4427 ShOps[1] = DAG.getConstant(0, MVT::i32);
4428 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4429 EVT DestVT = TLI.getValueType(I.getType());
4430 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, DestVT, ShAmt);
4431 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4432 DAG.getConstant(NewIntrinsic, MVT::i32),
4433 getValue(I.getArgOperand(0)), ShAmt);
4437 case Intrinsic::convertff:
4438 case Intrinsic::convertfsi:
4439 case Intrinsic::convertfui:
4440 case Intrinsic::convertsif:
4441 case Intrinsic::convertuif:
4442 case Intrinsic::convertss:
4443 case Intrinsic::convertsu:
4444 case Intrinsic::convertus:
4445 case Intrinsic::convertuu: {
4446 ISD::CvtCode Code = ISD::CVT_INVALID;
4447 switch (Intrinsic) {
4448 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4449 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4450 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4451 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4452 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4453 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4454 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4455 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4456 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4458 EVT DestVT = TLI.getValueType(I.getType());
4459 const Value *Op1 = I.getArgOperand(0);
4460 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4461 DAG.getValueType(DestVT),
4462 DAG.getValueType(getValue(Op1).getValueType()),
4463 getValue(I.getArgOperand(1)),
4464 getValue(I.getArgOperand(2)),
4469 case Intrinsic::sqrt:
4470 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4471 getValue(I.getArgOperand(0)).getValueType(),
4472 getValue(I.getArgOperand(0))));
4474 case Intrinsic::powi:
4475 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4476 getValue(I.getArgOperand(1)), DAG));
4478 case Intrinsic::sin:
4479 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4480 getValue(I.getArgOperand(0)).getValueType(),
4481 getValue(I.getArgOperand(0))));
4483 case Intrinsic::cos:
4484 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4485 getValue(I.getArgOperand(0)).getValueType(),
4486 getValue(I.getArgOperand(0))));
4488 case Intrinsic::log:
4491 case Intrinsic::log2:
4494 case Intrinsic::log10:
4497 case Intrinsic::exp:
4500 case Intrinsic::exp2:
4503 case Intrinsic::pow:
4506 case Intrinsic::convert_to_fp16:
4507 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4508 MVT::i16, getValue(I.getArgOperand(0))));
4510 case Intrinsic::convert_from_fp16:
4511 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4512 MVT::f32, getValue(I.getArgOperand(0))));
4514 case Intrinsic::pcmarker: {
4515 SDValue Tmp = getValue(I.getArgOperand(0));
4516 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4519 case Intrinsic::readcyclecounter: {
4520 SDValue Op = getRoot();
4521 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4522 DAG.getVTList(MVT::i64, MVT::Other),
4525 DAG.setRoot(Res.getValue(1));
4528 case Intrinsic::bswap:
4529 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4530 getValue(I.getArgOperand(0)).getValueType(),
4531 getValue(I.getArgOperand(0))));
4533 case Intrinsic::cttz: {
4534 SDValue Arg = getValue(I.getArgOperand(0));
4535 EVT Ty = Arg.getValueType();
4536 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4539 case Intrinsic::ctlz: {
4540 SDValue Arg = getValue(I.getArgOperand(0));
4541 EVT Ty = Arg.getValueType();
4542 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4545 case Intrinsic::ctpop: {
4546 SDValue Arg = getValue(I.getArgOperand(0));
4547 EVT Ty = Arg.getValueType();
4548 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4551 case Intrinsic::stacksave: {
4552 SDValue Op = getRoot();
4553 Res = DAG.getNode(ISD::STACKSAVE, dl,
4554 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4556 DAG.setRoot(Res.getValue(1));
4559 case Intrinsic::stackrestore: {
4560 Res = getValue(I.getArgOperand(0));
4561 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4564 case Intrinsic::stackprotector: {
4565 // Emit code into the DAG to store the stack guard onto the stack.
4566 MachineFunction &MF = DAG.getMachineFunction();
4567 MachineFrameInfo *MFI = MF.getFrameInfo();
4568 EVT PtrTy = TLI.getPointerTy();
4570 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4571 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4573 int FI = FuncInfo.StaticAllocaMap[Slot];
4574 MFI->setStackProtectorIndex(FI);
4576 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4578 // Store the stack protector onto the stack.
4579 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4580 MachinePointerInfo::getFixedStack(FI),
4586 case Intrinsic::objectsize: {
4587 // If we don't know by now, we're never going to know.
4588 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4590 assert(CI && "Non-constant type in __builtin_object_size?");
4592 SDValue Arg = getValue(I.getCalledValue());
4593 EVT Ty = Arg.getValueType();
4596 Res = DAG.getConstant(-1ULL, Ty);
4598 Res = DAG.getConstant(0, Ty);
4603 case Intrinsic::var_annotation:
4604 // Discard annotate attributes
4607 case Intrinsic::init_trampoline: {
4608 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4612 Ops[1] = getValue(I.getArgOperand(0));
4613 Ops[2] = getValue(I.getArgOperand(1));
4614 Ops[3] = getValue(I.getArgOperand(2));
4615 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4616 Ops[5] = DAG.getSrcValue(F);
4618 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4619 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4623 DAG.setRoot(Res.getValue(1));
4626 case Intrinsic::gcroot:
4628 const Value *Alloca = I.getArgOperand(0);
4629 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4631 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4632 GFI->addStackRoot(FI->getIndex(), TypeMap);
4635 case Intrinsic::gcread:
4636 case Intrinsic::gcwrite:
4637 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4639 case Intrinsic::flt_rounds:
4640 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4642 case Intrinsic::trap:
4643 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4645 case Intrinsic::uadd_with_overflow:
4646 return implVisitAluOverflow(I, ISD::UADDO);
4647 case Intrinsic::sadd_with_overflow:
4648 return implVisitAluOverflow(I, ISD::SADDO);
4649 case Intrinsic::usub_with_overflow:
4650 return implVisitAluOverflow(I, ISD::USUBO);
4651 case Intrinsic::ssub_with_overflow:
4652 return implVisitAluOverflow(I, ISD::SSUBO);
4653 case Intrinsic::umul_with_overflow:
4654 return implVisitAluOverflow(I, ISD::UMULO);
4655 case Intrinsic::smul_with_overflow:
4656 return implVisitAluOverflow(I, ISD::SMULO);
4658 case Intrinsic::prefetch: {
4660 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4662 Ops[1] = getValue(I.getArgOperand(0));
4663 Ops[2] = getValue(I.getArgOperand(1));
4664 Ops[3] = getValue(I.getArgOperand(2));
4665 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4666 DAG.getVTList(MVT::Other),
4668 EVT::getIntegerVT(*Context, 8),
4669 MachinePointerInfo(I.getArgOperand(0)),
4671 false, /* volatile */
4673 rw==1)); /* write */
4676 case Intrinsic::memory_barrier: {
4679 for (int x = 1; x < 6; ++x)
4680 Ops[x] = getValue(I.getArgOperand(x - 1));
4682 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4685 case Intrinsic::atomic_cmp_swap: {
4686 SDValue Root = getRoot();
4688 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4689 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4691 getValue(I.getArgOperand(0)),
4692 getValue(I.getArgOperand(1)),
4693 getValue(I.getArgOperand(2)),
4694 MachinePointerInfo(I.getArgOperand(0)));
4696 DAG.setRoot(L.getValue(1));
4699 case Intrinsic::atomic_load_add:
4700 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4701 case Intrinsic::atomic_load_sub:
4702 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4703 case Intrinsic::atomic_load_or:
4704 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4705 case Intrinsic::atomic_load_xor:
4706 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4707 case Intrinsic::atomic_load_and:
4708 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4709 case Intrinsic::atomic_load_nand:
4710 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4711 case Intrinsic::atomic_load_max:
4712 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4713 case Intrinsic::atomic_load_min:
4714 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4715 case Intrinsic::atomic_load_umin:
4716 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4717 case Intrinsic::atomic_load_umax:
4718 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4719 case Intrinsic::atomic_swap:
4720 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4722 case Intrinsic::invariant_start:
4723 case Intrinsic::lifetime_start:
4724 // Discard region information.
4725 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4727 case Intrinsic::invariant_end:
4728 case Intrinsic::lifetime_end:
4729 // Discard region information.
4734 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4736 MachineBasicBlock *LandingPad) {
4737 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4738 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4739 const Type *RetTy = FTy->getReturnType();
4740 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4741 MCSymbol *BeginLabel = 0;
4743 TargetLowering::ArgListTy Args;
4744 TargetLowering::ArgListEntry Entry;
4745 Args.reserve(CS.arg_size());
4747 // Check whether the function can return without sret-demotion.
4748 SmallVector<ISD::OutputArg, 4> Outs;
4749 SmallVector<uint64_t, 4> Offsets;
4750 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4751 Outs, TLI, &Offsets);
4753 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4754 FTy->isVarArg(), Outs, FTy->getContext());
4756 SDValue DemoteStackSlot;
4757 int DemoteStackIdx = -100;
4759 if (!CanLowerReturn) {
4760 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4761 FTy->getReturnType());
4762 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4763 FTy->getReturnType());
4764 MachineFunction &MF = DAG.getMachineFunction();
4765 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4766 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4768 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4769 Entry.Node = DemoteStackSlot;
4770 Entry.Ty = StackSlotPtrType;
4771 Entry.isSExt = false;
4772 Entry.isZExt = false;
4773 Entry.isInReg = false;
4774 Entry.isSRet = true;
4775 Entry.isNest = false;
4776 Entry.isByVal = false;
4777 Entry.Alignment = Align;
4778 Args.push_back(Entry);
4779 RetTy = Type::getVoidTy(FTy->getContext());
4782 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4784 SDValue ArgNode = getValue(*i);
4785 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4787 unsigned attrInd = i - CS.arg_begin() + 1;
4788 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4789 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4790 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4791 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4792 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4793 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4794 Entry.Alignment = CS.getParamAlignment(attrInd);
4795 Args.push_back(Entry);
4799 // Insert a label before the invoke call to mark the try range. This can be
4800 // used to detect deletion of the invoke via the MachineModuleInfo.
4801 BeginLabel = MMI.getContext().CreateTempSymbol();
4803 // For SjLj, keep track of which landing pads go with which invokes
4804 // so as to maintain the ordering of pads in the LSDA.
4805 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4806 if (CallSiteIndex) {
4807 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4808 // Now that the call site is handled, stop tracking it.
4809 MMI.setCurrentCallSite(0);
4812 // Both PendingLoads and PendingExports must be flushed here;
4813 // this call might not return.
4815 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4818 // Check if target-independent constraints permit a tail call here.
4819 // Target-dependent constraints are checked within TLI.LowerCallTo.
4821 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4824 // If there's a possibility that fast-isel has already selected some amount
4825 // of the current basic block, don't emit a tail call.
4826 if (isTailCall && EnableFastISel)
4829 std::pair<SDValue,SDValue> Result =
4830 TLI.LowerCallTo(getRoot(), RetTy,
4831 CS.paramHasAttr(0, Attribute::SExt),
4832 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4833 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4834 CS.getCallingConv(),
4836 !CS.getInstruction()->use_empty(),
4837 Callee, Args, DAG, getCurDebugLoc());
4838 assert((isTailCall || Result.second.getNode()) &&
4839 "Non-null chain expected with non-tail call!");
4840 assert((Result.second.getNode() || !Result.first.getNode()) &&
4841 "Null value expected with tail call!");
4842 if (Result.first.getNode()) {
4843 setValue(CS.getInstruction(), Result.first);
4844 } else if (!CanLowerReturn && Result.second.getNode()) {
4845 // The instruction result is the result of loading from the
4846 // hidden sret parameter.
4847 SmallVector<EVT, 1> PVTs;
4848 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4850 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4851 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4852 EVT PtrVT = PVTs[0];
4853 unsigned NumValues = Outs.size();
4854 SmallVector<SDValue, 4> Values(NumValues);
4855 SmallVector<SDValue, 4> Chains(NumValues);
4857 for (unsigned i = 0; i < NumValues; ++i) {
4858 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4860 DAG.getConstant(Offsets[i], PtrVT));
4861 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4863 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4866 Chains[i] = L.getValue(1);
4869 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4870 MVT::Other, &Chains[0], NumValues);
4871 PendingLoads.push_back(Chain);
4873 // Collect the legal value parts into potentially illegal values
4874 // that correspond to the original function's return values.
4875 SmallVector<EVT, 4> RetTys;
4876 RetTy = FTy->getReturnType();
4877 ComputeValueVTs(TLI, RetTy, RetTys);
4878 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4879 SmallVector<SDValue, 4> ReturnValues;
4880 unsigned CurReg = 0;
4881 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4883 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4884 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4886 SDValue ReturnValue =
4887 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4888 RegisterVT, VT, AssertOp);
4889 ReturnValues.push_back(ReturnValue);
4893 setValue(CS.getInstruction(),
4894 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4895 DAG.getVTList(&RetTys[0], RetTys.size()),
4896 &ReturnValues[0], ReturnValues.size()));
4900 // As a special case, a null chain means that a tail call has been emitted and
4901 // the DAG root is already updated.
4902 if (Result.second.getNode())
4903 DAG.setRoot(Result.second);
4908 // Insert a label at the end of the invoke call to mark the try range. This
4909 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4910 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4911 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4913 // Inform MachineModuleInfo of range.
4914 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4918 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4919 /// value is equal or not-equal to zero.
4920 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4921 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4923 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4924 if (IC->isEquality())
4925 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4926 if (C->isNullValue())
4928 // Unknown instruction.
4934 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4936 SelectionDAGBuilder &Builder) {
4938 // Check to see if this load can be trivially constant folded, e.g. if the
4939 // input is from a string literal.
4940 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4941 // Cast pointer to the type we really want to load.
4942 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4943 PointerType::getUnqual(LoadTy));
4945 if (const Constant *LoadCst =
4946 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4948 return Builder.getValue(LoadCst);
4951 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4952 // still constant memory, the input chain can be the entry node.
4954 bool ConstantMemory = false;
4956 // Do not serialize (non-volatile) loads of constant memory with anything.
4957 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4958 Root = Builder.DAG.getEntryNode();
4959 ConstantMemory = true;
4961 // Do not serialize non-volatile loads against each other.
4962 Root = Builder.DAG.getRoot();
4965 SDValue Ptr = Builder.getValue(PtrVal);
4966 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4967 Ptr, MachinePointerInfo(PtrVal),
4969 false /*nontemporal*/, 1 /* align=1 */);
4971 if (!ConstantMemory)
4972 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4977 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4978 /// If so, return true and lower it, otherwise return false and it will be
4979 /// lowered like a normal call.
4980 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4981 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4982 if (I.getNumArgOperands() != 3)
4985 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
4986 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4987 !I.getArgOperand(2)->getType()->isIntegerTy() ||
4988 !I.getType()->isIntegerTy())
4991 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
4993 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4994 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4995 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4996 bool ActuallyDoIt = true;
4999 switch (Size->getZExtValue()) {
5001 LoadVT = MVT::Other;
5003 ActuallyDoIt = false;
5007 LoadTy = Type::getInt16Ty(Size->getContext());
5011 LoadTy = Type::getInt32Ty(Size->getContext());
5015 LoadTy = Type::getInt64Ty(Size->getContext());
5019 LoadVT = MVT::v4i32;
5020 LoadTy = Type::getInt32Ty(Size->getContext());
5021 LoadTy = VectorType::get(LoadTy, 4);
5026 // This turns into unaligned loads. We only do this if the target natively
5027 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5028 // we'll only produce a small number of byte loads.
5030 // Require that we can find a legal MVT, and only do this if the target
5031 // supports unaligned loads of that type. Expanding into byte loads would
5033 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5034 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5035 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5036 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5037 ActuallyDoIt = false;
5041 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5042 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5044 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5046 EVT CallVT = TLI.getValueType(I.getType(), true);
5047 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5057 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5058 // Handle inline assembly differently.
5059 if (isa<InlineAsm>(I.getCalledValue())) {
5064 // See if any floating point values are being passed to this function. This is
5065 // used to emit an undefined reference to fltused on Windows.
5066 const FunctionType *FT =
5067 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5068 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5069 if (FT->isVarArg() &&
5070 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5071 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5072 const Type* T = I.getArgOperand(i)->getType();
5073 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5075 if (!i->isFloatingPointTy()) continue;
5076 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5082 const char *RenameFn = 0;
5083 if (Function *F = I.getCalledFunction()) {
5084 if (F->isDeclaration()) {
5085 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5086 if (unsigned IID = II->getIntrinsicID(F)) {
5087 RenameFn = visitIntrinsicCall(I, IID);
5092 if (unsigned IID = F->getIntrinsicID()) {
5093 RenameFn = visitIntrinsicCall(I, IID);
5099 // Check for well-known libc/libm calls. If the function is internal, it
5100 // can't be a library call.
5101 if (!F->hasLocalLinkage() && F->hasName()) {
5102 StringRef Name = F->getName();
5103 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5104 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5105 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5106 I.getType() == I.getArgOperand(0)->getType() &&
5107 I.getType() == I.getArgOperand(1)->getType()) {
5108 SDValue LHS = getValue(I.getArgOperand(0));
5109 SDValue RHS = getValue(I.getArgOperand(1));
5110 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5111 LHS.getValueType(), LHS, RHS));
5114 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5115 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5116 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5117 I.getType() == I.getArgOperand(0)->getType()) {
5118 SDValue Tmp = getValue(I.getArgOperand(0));
5119 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5120 Tmp.getValueType(), Tmp));
5123 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5124 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5125 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5126 I.getType() == I.getArgOperand(0)->getType() &&
5127 I.onlyReadsMemory()) {
5128 SDValue Tmp = getValue(I.getArgOperand(0));
5129 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5130 Tmp.getValueType(), Tmp));
5133 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5134 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5135 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5136 I.getType() == I.getArgOperand(0)->getType() &&
5137 I.onlyReadsMemory()) {
5138 SDValue Tmp = getValue(I.getArgOperand(0));
5139 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5140 Tmp.getValueType(), Tmp));
5143 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5144 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5145 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5146 I.getType() == I.getArgOperand(0)->getType() &&
5147 I.onlyReadsMemory()) {
5148 SDValue Tmp = getValue(I.getArgOperand(0));
5149 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5150 Tmp.getValueType(), Tmp));
5153 } else if (Name == "memcmp") {
5154 if (visitMemCmpCall(I))
5162 Callee = getValue(I.getCalledValue());
5164 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5166 // Check if we can potentially perform a tail call. More detailed checking is
5167 // be done within LowerCallTo, after more information about the call is known.
5168 LowerCallTo(&I, Callee, I.isTailCall());
5173 /// AsmOperandInfo - This contains information for each constraint that we are
5175 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5176 public TargetLowering::AsmOperandInfo {
5178 /// CallOperand - If this is the result output operand or a clobber
5179 /// this is null, otherwise it is the incoming operand to the CallInst.
5180 /// This gets modified as the asm is processed.
5181 SDValue CallOperand;
5183 /// AssignedRegs - If this is a register or register class operand, this
5184 /// contains the set of register corresponding to the operand.
5185 RegsForValue AssignedRegs;
5187 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5188 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5191 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5192 /// busy in OutputRegs/InputRegs.
5193 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5194 std::set<unsigned> &OutputRegs,
5195 std::set<unsigned> &InputRegs,
5196 const TargetRegisterInfo &TRI) const {
5198 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5199 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5202 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5203 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5207 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5208 /// corresponds to. If there is no Value* for this operand, it returns
5210 EVT getCallOperandValEVT(LLVMContext &Context,
5211 const TargetLowering &TLI,
5212 const TargetData *TD) const {
5213 if (CallOperandVal == 0) return MVT::Other;
5215 if (isa<BasicBlock>(CallOperandVal))
5216 return TLI.getPointerTy();
5218 const llvm::Type *OpTy = CallOperandVal->getType();
5220 // If this is an indirect operand, the operand is a pointer to the
5223 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5225 report_fatal_error("Indirect operand for inline asm not a pointer!");
5226 OpTy = PtrTy->getElementType();
5229 // If OpTy is not a single value, it may be a struct/union that we
5230 // can tile with integers.
5231 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5232 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5241 OpTy = IntegerType::get(Context, BitSize);
5246 return TLI.getValueType(OpTy, true);
5250 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5252 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5253 const TargetRegisterInfo &TRI) {
5254 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5256 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5257 for (; *Aliases; ++Aliases)
5258 Regs.insert(*Aliases);
5262 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5264 } // end llvm namespace.
5266 /// isAllocatableRegister - If the specified register is safe to allocate,
5267 /// i.e. it isn't a stack pointer or some other special register, return the
5268 /// register class for the register. Otherwise, return null.
5269 static const TargetRegisterClass *
5270 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5271 const TargetLowering &TLI,
5272 const TargetRegisterInfo *TRI) {
5273 EVT FoundVT = MVT::Other;
5274 const TargetRegisterClass *FoundRC = 0;
5275 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5276 E = TRI->regclass_end(); RCI != E; ++RCI) {
5277 EVT ThisVT = MVT::Other;
5279 const TargetRegisterClass *RC = *RCI;
5280 // If none of the value types for this register class are valid, we
5281 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5282 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5284 if (TLI.isTypeLegal(*I)) {
5285 // If we have already found this register in a different register class,
5286 // choose the one with the largest VT specified. For example, on
5287 // PowerPC, we favor f64 register classes over f32.
5288 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5295 if (ThisVT == MVT::Other) continue;
5297 // NOTE: This isn't ideal. In particular, this might allocate the
5298 // frame pointer in functions that need it (due to them not being taken
5299 // out of allocation, because a variable sized allocation hasn't been seen
5300 // yet). This is a slight code pessimization, but should still work.
5301 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5302 E = RC->allocation_order_end(MF); I != E; ++I)
5304 // We found a matching register class. Keep looking at others in case
5305 // we find one with larger registers that this physreg is also in.
5314 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5315 /// specified operand. We prefer to assign virtual registers, to allow the
5316 /// register allocator to handle the assignment process. However, if the asm
5317 /// uses features that we can't model on machineinstrs, we have SDISel do the
5318 /// allocation. This produces generally horrible, but correct, code.
5320 /// OpInfo describes the operand.
5321 /// Input and OutputRegs are the set of already allocated physical registers.
5323 void SelectionDAGBuilder::
5324 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5325 std::set<unsigned> &OutputRegs,
5326 std::set<unsigned> &InputRegs) {
5327 LLVMContext &Context = FuncInfo.Fn->getContext();
5329 // Compute whether this value requires an input register, an output register,
5331 bool isOutReg = false;
5332 bool isInReg = false;
5333 switch (OpInfo.Type) {
5334 case InlineAsm::isOutput:
5337 // If there is an input constraint that matches this, we need to reserve
5338 // the input register so no other inputs allocate to it.
5339 isInReg = OpInfo.hasMatchingInput();
5341 case InlineAsm::isInput:
5345 case InlineAsm::isClobber:
5352 MachineFunction &MF = DAG.getMachineFunction();
5353 SmallVector<unsigned, 4> Regs;
5355 // If this is a constraint for a single physreg, or a constraint for a
5356 // register class, find it.
5357 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5358 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5359 OpInfo.ConstraintVT);
5361 unsigned NumRegs = 1;
5362 if (OpInfo.ConstraintVT != MVT::Other) {
5363 // If this is a FP input in an integer register (or visa versa) insert a bit
5364 // cast of the input value. More generally, handle any case where the input
5365 // value disagrees with the register class we plan to stick this in.
5366 if (OpInfo.Type == InlineAsm::isInput &&
5367 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5368 // Try to convert to the first EVT that the reg class contains. If the
5369 // types are identical size, use a bitcast to convert (e.g. two differing
5371 EVT RegVT = *PhysReg.second->vt_begin();
5372 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5373 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5374 RegVT, OpInfo.CallOperand);
5375 OpInfo.ConstraintVT = RegVT;
5376 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5377 // If the input is a FP value and we want it in FP registers, do a
5378 // bitcast to the corresponding integer type. This turns an f64 value
5379 // into i64, which can be passed with two i32 values on a 32-bit
5381 RegVT = EVT::getIntegerVT(Context,
5382 OpInfo.ConstraintVT.getSizeInBits());
5383 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5384 RegVT, OpInfo.CallOperand);
5385 OpInfo.ConstraintVT = RegVT;
5389 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5393 EVT ValueVT = OpInfo.ConstraintVT;
5395 // If this is a constraint for a specific physical register, like {r17},
5397 if (unsigned AssignedReg = PhysReg.first) {
5398 const TargetRegisterClass *RC = PhysReg.second;
5399 if (OpInfo.ConstraintVT == MVT::Other)
5400 ValueVT = *RC->vt_begin();
5402 // Get the actual register value type. This is important, because the user
5403 // may have asked for (e.g.) the AX register in i32 type. We need to
5404 // remember that AX is actually i16 to get the right extension.
5405 RegVT = *RC->vt_begin();
5407 // This is a explicit reference to a physical register.
5408 Regs.push_back(AssignedReg);
5410 // If this is an expanded reference, add the rest of the regs to Regs.
5412 TargetRegisterClass::iterator I = RC->begin();
5413 for (; *I != AssignedReg; ++I)
5414 assert(I != RC->end() && "Didn't find reg!");
5416 // Already added the first reg.
5418 for (; NumRegs; --NumRegs, ++I) {
5419 assert(I != RC->end() && "Ran out of registers to allocate!");
5424 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5425 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5426 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5430 // Otherwise, if this was a reference to an LLVM register class, create vregs
5431 // for this reference.
5432 if (const TargetRegisterClass *RC = PhysReg.second) {
5433 RegVT = *RC->vt_begin();
5434 if (OpInfo.ConstraintVT == MVT::Other)
5437 // Create the appropriate number of virtual registers.
5438 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5439 for (; NumRegs; --NumRegs)
5440 Regs.push_back(RegInfo.createVirtualRegister(RC));
5442 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5446 // This is a reference to a register class that doesn't directly correspond
5447 // to an LLVM register class. Allocate NumRegs consecutive, available,
5448 // registers from the class.
5449 std::vector<unsigned> RegClassRegs
5450 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5451 OpInfo.ConstraintVT);
5453 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5454 unsigned NumAllocated = 0;
5455 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5456 unsigned Reg = RegClassRegs[i];
5457 // See if this register is available.
5458 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5459 (isInReg && InputRegs.count(Reg))) { // Already used.
5460 // Make sure we find consecutive registers.
5465 // Check to see if this register is allocatable (i.e. don't give out the
5467 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5468 if (!RC) { // Couldn't allocate this register.
5469 // Reset NumAllocated to make sure we return consecutive registers.
5474 // Okay, this register is good, we can use it.
5477 // If we allocated enough consecutive registers, succeed.
5478 if (NumAllocated == NumRegs) {
5479 unsigned RegStart = (i-NumAllocated)+1;
5480 unsigned RegEnd = i+1;
5481 // Mark all of the allocated registers used.
5482 for (unsigned i = RegStart; i != RegEnd; ++i)
5483 Regs.push_back(RegClassRegs[i]);
5485 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5486 OpInfo.ConstraintVT);
5487 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5492 // Otherwise, we couldn't allocate enough registers for this.
5495 /// visitInlineAsm - Handle a call to an InlineAsm object.
5497 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5498 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5500 /// ConstraintOperands - Information about all of the constraints.
5501 SDISelAsmOperandInfoVector ConstraintOperands;
5503 std::set<unsigned> OutputRegs, InputRegs;
5505 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5506 bool hasMemory = false;
5508 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5509 unsigned ResNo = 0; // ResNo - The result number of the next output.
5510 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5511 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5512 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5514 EVT OpVT = MVT::Other;
5516 // Compute the value type for each operand.
5517 switch (OpInfo.Type) {
5518 case InlineAsm::isOutput:
5519 // Indirect outputs just consume an argument.
5520 if (OpInfo.isIndirect) {
5521 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5525 // The return value of the call is this value. As such, there is no
5526 // corresponding argument.
5527 assert(!CS.getType()->isVoidTy() &&
5529 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5530 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5532 assert(ResNo == 0 && "Asm only has one result!");
5533 OpVT = TLI.getValueType(CS.getType());
5537 case InlineAsm::isInput:
5538 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5540 case InlineAsm::isClobber:
5545 // If this is an input or an indirect output, process the call argument.
5546 // BasicBlocks are labels, currently appearing only in asm's.
5547 if (OpInfo.CallOperandVal) {
5548 // Strip bitcasts, if any. This mostly comes up for functions.
5549 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5551 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5552 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5554 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5557 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5560 OpInfo.ConstraintVT = OpVT;
5562 // Indirect operand accesses access memory.
5563 if (OpInfo.isIndirect)
5566 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5567 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5568 if (CType == TargetLowering::C_Memory) {
5576 SDValue Chain, Flag;
5578 // We won't need to flush pending loads if this asm doesn't touch
5579 // memory and is nonvolatile.
5580 if (hasMemory || IA->hasSideEffects())
5583 Chain = DAG.getRoot();
5585 // Second pass over the constraints: compute which constraint option to use
5586 // and assign registers to constraints that want a specific physreg.
5587 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5588 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5590 // If this is an output operand with a matching input operand, look up the
5591 // matching input. If their types mismatch, e.g. one is an integer, the
5592 // other is floating point, or their sizes are different, flag it as an
5594 if (OpInfo.hasMatchingInput()) {
5595 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5597 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5598 if ((OpInfo.ConstraintVT.isInteger() !=
5599 Input.ConstraintVT.isInteger()) ||
5600 (OpInfo.ConstraintVT.getSizeInBits() !=
5601 Input.ConstraintVT.getSizeInBits())) {
5602 report_fatal_error("Unsupported asm: input constraint"
5603 " with a matching output constraint of"
5604 " incompatible type!");
5606 Input.ConstraintVT = OpInfo.ConstraintVT;
5610 // Compute the constraint code and ConstraintType to use.
5611 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5613 // If this is a memory input, and if the operand is not indirect, do what we
5614 // need to to provide an address for the memory input.
5615 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5616 !OpInfo.isIndirect) {
5617 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5618 "Can only indirectify direct input operands!");
5620 // Memory operands really want the address of the value. If we don't have
5621 // an indirect input, put it in the constpool if we can, otherwise spill
5622 // it to a stack slot.
5624 // If the operand is a float, integer, or vector constant, spill to a
5625 // constant pool entry to get its address.
5626 const Value *OpVal = OpInfo.CallOperandVal;
5627 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5628 isa<ConstantVector>(OpVal)) {
5629 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5630 TLI.getPointerTy());
5632 // Otherwise, create a stack slot and emit a store to it before the
5634 const Type *Ty = OpVal->getType();
5635 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5636 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5637 MachineFunction &MF = DAG.getMachineFunction();
5638 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5639 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5640 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5641 OpInfo.CallOperand, StackSlot,
5642 MachinePointerInfo::getFixedStack(SSFI),
5644 OpInfo.CallOperand = StackSlot;
5647 // There is no longer a Value* corresponding to this operand.
5648 OpInfo.CallOperandVal = 0;
5650 // It is now an indirect operand.
5651 OpInfo.isIndirect = true;
5654 // If this constraint is for a specific register, allocate it before
5656 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5657 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5660 // Second pass - Loop over all of the operands, assigning virtual or physregs
5661 // to register class operands.
5662 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5663 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5665 // C_Register operands have already been allocated, Other/Memory don't need
5667 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5668 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5671 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5672 std::vector<SDValue> AsmNodeOperands;
5673 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5674 AsmNodeOperands.push_back(
5675 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5676 TLI.getPointerTy()));
5678 // If we have a !srcloc metadata node associated with it, we want to attach
5679 // this to the ultimately generated inline asm machineinstr. To do this, we
5680 // pass in the third operand as this (potentially null) inline asm MDNode.
5681 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5682 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5684 // Remember the AlignStack bit as operand 3.
5685 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
5688 // Loop over all of the inputs, copying the operand values into the
5689 // appropriate registers and processing the output regs.
5690 RegsForValue RetValRegs;
5692 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5693 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5695 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5696 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5698 switch (OpInfo.Type) {
5699 case InlineAsm::isOutput: {
5700 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5701 OpInfo.ConstraintType != TargetLowering::C_Register) {
5702 // Memory output, or 'other' output (e.g. 'X' constraint).
5703 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5705 // Add information to the INLINEASM node to know about this output.
5706 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5707 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5708 TLI.getPointerTy()));
5709 AsmNodeOperands.push_back(OpInfo.CallOperand);
5713 // Otherwise, this is a register or register class output.
5715 // Copy the output from the appropriate register. Find a register that
5717 if (OpInfo.AssignedRegs.Regs.empty())
5718 report_fatal_error("Couldn't allocate output reg for constraint '" +
5719 Twine(OpInfo.ConstraintCode) + "'!");
5721 // If this is an indirect operand, store through the pointer after the
5723 if (OpInfo.isIndirect) {
5724 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5725 OpInfo.CallOperandVal));
5727 // This is the result value of the call.
5728 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5729 // Concatenate this output onto the outputs list.
5730 RetValRegs.append(OpInfo.AssignedRegs);
5733 // Add information to the INLINEASM node to know that this register is
5735 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5736 InlineAsm::Kind_RegDefEarlyClobber :
5737 InlineAsm::Kind_RegDef,
5744 case InlineAsm::isInput: {
5745 SDValue InOperandVal = OpInfo.CallOperand;
5747 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5748 // If this is required to match an output register we have already set,
5749 // just use its register.
5750 unsigned OperandNo = OpInfo.getMatchedOperand();
5752 // Scan until we find the definition we already emitted of this operand.
5753 // When we find it, create a RegsForValue operand.
5754 unsigned CurOp = InlineAsm::Op_FirstOperand;
5755 for (; OperandNo; --OperandNo) {
5756 // Advance to the next operand.
5758 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5759 assert((InlineAsm::isRegDefKind(OpFlag) ||
5760 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5761 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5762 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5766 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5767 if (InlineAsm::isRegDefKind(OpFlag) ||
5768 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5769 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5770 if (OpInfo.isIndirect) {
5771 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5772 LLVMContext &Ctx = *DAG.getContext();
5773 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5774 " don't know how to handle tied "
5775 "indirect register inputs");
5778 RegsForValue MatchedRegs;
5779 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5780 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5781 MatchedRegs.RegVTs.push_back(RegVT);
5782 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5783 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5785 MatchedRegs.Regs.push_back
5786 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5788 // Use the produced MatchedRegs object to
5789 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5791 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5792 true, OpInfo.getMatchedOperand(),
5793 DAG, AsmNodeOperands);
5797 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5798 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5799 "Unexpected number of operands");
5800 // Add information to the INLINEASM node to know about this input.
5801 // See InlineAsm.h isUseOperandTiedToDef.
5802 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5803 OpInfo.getMatchedOperand());
5804 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5805 TLI.getPointerTy()));
5806 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5810 // Treat indirect 'X' constraint as memory.
5811 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5813 OpInfo.ConstraintType = TargetLowering::C_Memory;
5815 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5816 std::vector<SDValue> Ops;
5817 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5820 report_fatal_error("Invalid operand for inline asm constraint '" +
5821 Twine(OpInfo.ConstraintCode) + "'!");
5823 // Add information to the INLINEASM node to know about this input.
5824 unsigned ResOpType =
5825 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5826 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5827 TLI.getPointerTy()));
5828 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5832 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5833 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5834 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5835 "Memory operands expect pointer values");
5837 // Add information to the INLINEASM node to know about this input.
5838 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5839 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5840 TLI.getPointerTy()));
5841 AsmNodeOperands.push_back(InOperandVal);
5845 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5846 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5847 "Unknown constraint type!");
5848 assert(!OpInfo.isIndirect &&
5849 "Don't know how to handle indirect register inputs yet!");
5851 // Copy the input into the appropriate registers.
5852 if (OpInfo.AssignedRegs.Regs.empty() ||
5853 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5854 report_fatal_error("Couldn't allocate input reg for constraint '" +
5855 Twine(OpInfo.ConstraintCode) + "'!");
5857 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5860 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5861 DAG, AsmNodeOperands);
5864 case InlineAsm::isClobber: {
5865 // Add the clobbered value to the operand list, so that the register
5866 // allocator is aware that the physreg got clobbered.
5867 if (!OpInfo.AssignedRegs.Regs.empty())
5868 OpInfo.AssignedRegs.AddInlineAsmOperands(
5869 InlineAsm::Kind_RegDefEarlyClobber,
5877 // Finish up input operands. Set the input chain and add the flag last.
5878 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5879 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5881 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5882 DAG.getVTList(MVT::Other, MVT::Flag),
5883 &AsmNodeOperands[0], AsmNodeOperands.size());
5884 Flag = Chain.getValue(1);
5886 // If this asm returns a register value, copy the result from that register
5887 // and set it as the value of the call.
5888 if (!RetValRegs.Regs.empty()) {
5889 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5892 // FIXME: Why don't we do this for inline asms with MRVs?
5893 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5894 EVT ResultType = TLI.getValueType(CS.getType());
5896 // If any of the results of the inline asm is a vector, it may have the
5897 // wrong width/num elts. This can happen for register classes that can
5898 // contain multiple different value types. The preg or vreg allocated may
5899 // not have the same VT as was expected. Convert it to the right type
5900 // with bit_convert.
5901 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5902 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5905 } else if (ResultType != Val.getValueType() &&
5906 ResultType.isInteger() && Val.getValueType().isInteger()) {
5907 // If a result value was tied to an input value, the computed result may
5908 // have a wider width than the expected result. Extract the relevant
5910 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5913 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5916 setValue(CS.getInstruction(), Val);
5917 // Don't need to use this as a chain in this case.
5918 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5922 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5924 // Process indirect outputs, first output all of the flagged copies out of
5926 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5927 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5928 const Value *Ptr = IndirectStoresToEmit[i].second;
5929 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5931 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5934 // Emit the non-flagged stores from the physregs.
5935 SmallVector<SDValue, 8> OutChains;
5936 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5937 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5938 StoresToEmit[i].first,
5939 getValue(StoresToEmit[i].second),
5940 MachinePointerInfo(StoresToEmit[i].second),
5942 OutChains.push_back(Val);
5945 if (!OutChains.empty())
5946 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5947 &OutChains[0], OutChains.size());
5952 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5953 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5954 MVT::Other, getRoot(),
5955 getValue(I.getArgOperand(0)),
5956 DAG.getSrcValue(I.getArgOperand(0))));
5959 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5960 const TargetData &TD = *TLI.getTargetData();
5961 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5962 getRoot(), getValue(I.getOperand(0)),
5963 DAG.getSrcValue(I.getOperand(0)),
5964 TD.getABITypeAlignment(I.getType()));
5966 DAG.setRoot(V.getValue(1));
5969 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5970 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5971 MVT::Other, getRoot(),
5972 getValue(I.getArgOperand(0)),
5973 DAG.getSrcValue(I.getArgOperand(0))));
5976 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5977 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5978 MVT::Other, getRoot(),
5979 getValue(I.getArgOperand(0)),
5980 getValue(I.getArgOperand(1)),
5981 DAG.getSrcValue(I.getArgOperand(0)),
5982 DAG.getSrcValue(I.getArgOperand(1))));
5985 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5986 /// implementation, which just calls LowerCall.
5987 /// FIXME: When all targets are
5988 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5989 std::pair<SDValue, SDValue>
5990 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5991 bool RetSExt, bool RetZExt, bool isVarArg,
5992 bool isInreg, unsigned NumFixedArgs,
5993 CallingConv::ID CallConv, bool isTailCall,
5994 bool isReturnValueUsed,
5996 ArgListTy &Args, SelectionDAG &DAG,
5997 DebugLoc dl) const {
5998 // Handle all of the outgoing arguments.
5999 SmallVector<ISD::OutputArg, 32> Outs;
6000 SmallVector<SDValue, 32> OutVals;
6001 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6002 SmallVector<EVT, 4> ValueVTs;
6003 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6004 for (unsigned Value = 0, NumValues = ValueVTs.size();
6005 Value != NumValues; ++Value) {
6006 EVT VT = ValueVTs[Value];
6007 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6008 SDValue Op = SDValue(Args[i].Node.getNode(),
6009 Args[i].Node.getResNo() + Value);
6010 ISD::ArgFlagsTy Flags;
6011 unsigned OriginalAlignment =
6012 getTargetData()->getABITypeAlignment(ArgTy);
6018 if (Args[i].isInReg)
6022 if (Args[i].isByVal) {
6024 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6025 const Type *ElementTy = Ty->getElementType();
6026 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6027 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6028 // For ByVal, alignment should come from FE. BE will guess if this
6029 // info is not there but there are cases it cannot get right.
6030 if (Args[i].Alignment)
6031 FrameAlign = Args[i].Alignment;
6032 Flags.setByValAlign(FrameAlign);
6033 Flags.setByValSize(FrameSize);
6037 Flags.setOrigAlign(OriginalAlignment);
6039 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6040 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6041 SmallVector<SDValue, 4> Parts(NumParts);
6042 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6045 ExtendKind = ISD::SIGN_EXTEND;
6046 else if (Args[i].isZExt)
6047 ExtendKind = ISD::ZERO_EXTEND;
6049 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6050 PartVT, ExtendKind);
6052 for (unsigned j = 0; j != NumParts; ++j) {
6053 // if it isn't first piece, alignment must be 1
6054 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6056 if (NumParts > 1 && j == 0)
6057 MyFlags.Flags.setSplit();
6059 MyFlags.Flags.setOrigAlign(1);
6061 Outs.push_back(MyFlags);
6062 OutVals.push_back(Parts[j]);
6067 // Handle the incoming return values from the call.
6068 SmallVector<ISD::InputArg, 32> Ins;
6069 SmallVector<EVT, 4> RetTys;
6070 ComputeValueVTs(*this, RetTy, RetTys);
6071 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6073 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6074 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6075 for (unsigned i = 0; i != NumRegs; ++i) {
6076 ISD::InputArg MyFlags;
6077 MyFlags.VT = RegisterVT.getSimpleVT();
6078 MyFlags.Used = isReturnValueUsed;
6080 MyFlags.Flags.setSExt();
6082 MyFlags.Flags.setZExt();
6084 MyFlags.Flags.setInReg();
6085 Ins.push_back(MyFlags);
6089 SmallVector<SDValue, 4> InVals;
6090 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6091 Outs, OutVals, Ins, dl, DAG, InVals);
6093 // Verify that the target's LowerCall behaved as expected.
6094 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6095 "LowerCall didn't return a valid chain!");
6096 assert((!isTailCall || InVals.empty()) &&
6097 "LowerCall emitted a return value for a tail call!");
6098 assert((isTailCall || InVals.size() == Ins.size()) &&
6099 "LowerCall didn't emit the correct number of values!");
6101 // For a tail call, the return value is merely live-out and there aren't
6102 // any nodes in the DAG representing it. Return a special value to
6103 // indicate that a tail call has been emitted and no more Instructions
6104 // should be processed in the current block.
6107 return std::make_pair(SDValue(), SDValue());
6110 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6111 assert(InVals[i].getNode() &&
6112 "LowerCall emitted a null value!");
6113 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6114 "LowerCall emitted a value with the wrong type!");
6117 // Collect the legal value parts into potentially illegal values
6118 // that correspond to the original function's return values.
6119 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6121 AssertOp = ISD::AssertSext;
6123 AssertOp = ISD::AssertZext;
6124 SmallVector<SDValue, 4> ReturnValues;
6125 unsigned CurReg = 0;
6126 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6128 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6129 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6131 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6132 NumRegs, RegisterVT, VT,
6137 // For a function returning void, there is no return value. We can't create
6138 // such a node, so we just return a null return value in that case. In
6139 // that case, nothing will actualy look at the value.
6140 if (ReturnValues.empty())
6141 return std::make_pair(SDValue(), Chain);
6143 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6144 DAG.getVTList(&RetTys[0], RetTys.size()),
6145 &ReturnValues[0], ReturnValues.size());
6146 return std::make_pair(Res, Chain);
6149 void TargetLowering::LowerOperationWrapper(SDNode *N,
6150 SmallVectorImpl<SDValue> &Results,
6151 SelectionDAG &DAG) const {
6152 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6154 Results.push_back(Res);
6157 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6158 llvm_unreachable("LowerOperation not implemented for this target!");
6163 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6164 SDValue Op = getNonRegisterValue(V);
6165 assert((Op.getOpcode() != ISD::CopyFromReg ||
6166 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6167 "Copy from a reg to the same reg!");
6168 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6170 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6171 SDValue Chain = DAG.getEntryNode();
6172 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6173 PendingExports.push_back(Chain);
6176 #include "llvm/CodeGen/SelectionDAGISel.h"
6178 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6179 // If this is the entry block, emit arguments.
6180 const Function &F = *LLVMBB->getParent();
6181 SelectionDAG &DAG = SDB->DAG;
6182 DebugLoc dl = SDB->getCurDebugLoc();
6183 const TargetData *TD = TLI.getTargetData();
6184 SmallVector<ISD::InputArg, 16> Ins;
6186 // Check whether the function can return without sret-demotion.
6187 SmallVector<ISD::OutputArg, 4> Outs;
6188 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6191 if (!FuncInfo->CanLowerReturn) {
6192 // Put in an sret pointer parameter before all the other parameters.
6193 SmallVector<EVT, 1> ValueVTs;
6194 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6196 // NOTE: Assuming that a pointer will never break down to more than one VT
6198 ISD::ArgFlagsTy Flags;
6200 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6201 ISD::InputArg RetArg(Flags, RegisterVT, true);
6202 Ins.push_back(RetArg);
6205 // Set up the incoming argument description vector.
6207 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6208 I != E; ++I, ++Idx) {
6209 SmallVector<EVT, 4> ValueVTs;
6210 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6211 bool isArgValueUsed = !I->use_empty();
6212 for (unsigned Value = 0, NumValues = ValueVTs.size();
6213 Value != NumValues; ++Value) {
6214 EVT VT = ValueVTs[Value];
6215 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6216 ISD::ArgFlagsTy Flags;
6217 unsigned OriginalAlignment =
6218 TD->getABITypeAlignment(ArgTy);
6220 if (F.paramHasAttr(Idx, Attribute::ZExt))
6222 if (F.paramHasAttr(Idx, Attribute::SExt))
6224 if (F.paramHasAttr(Idx, Attribute::InReg))
6226 if (F.paramHasAttr(Idx, Attribute::StructRet))
6228 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6230 const PointerType *Ty = cast<PointerType>(I->getType());
6231 const Type *ElementTy = Ty->getElementType();
6232 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6233 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6234 // For ByVal, alignment should be passed from FE. BE will guess if
6235 // this info is not there but there are cases it cannot get right.
6236 if (F.getParamAlignment(Idx))
6237 FrameAlign = F.getParamAlignment(Idx);
6238 Flags.setByValAlign(FrameAlign);
6239 Flags.setByValSize(FrameSize);
6241 if (F.paramHasAttr(Idx, Attribute::Nest))
6243 Flags.setOrigAlign(OriginalAlignment);
6245 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6246 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6247 for (unsigned i = 0; i != NumRegs; ++i) {
6248 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6249 if (NumRegs > 1 && i == 0)
6250 MyFlags.Flags.setSplit();
6251 // if it isn't first piece, alignment must be 1
6253 MyFlags.Flags.setOrigAlign(1);
6254 Ins.push_back(MyFlags);
6259 // Call the target to set up the argument values.
6260 SmallVector<SDValue, 8> InVals;
6261 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6265 // Verify that the target's LowerFormalArguments behaved as expected.
6266 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6267 "LowerFormalArguments didn't return a valid chain!");
6268 assert(InVals.size() == Ins.size() &&
6269 "LowerFormalArguments didn't emit the correct number of values!");
6271 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6272 assert(InVals[i].getNode() &&
6273 "LowerFormalArguments emitted a null value!");
6274 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6275 "LowerFormalArguments emitted a value with the wrong type!");
6279 // Update the DAG with the new chain value resulting from argument lowering.
6280 DAG.setRoot(NewRoot);
6282 // Set up the argument values.
6285 if (!FuncInfo->CanLowerReturn) {
6286 // Create a virtual register for the sret pointer, and put in a copy
6287 // from the sret argument into it.
6288 SmallVector<EVT, 1> ValueVTs;
6289 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6290 EVT VT = ValueVTs[0];
6291 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6292 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6293 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6294 RegVT, VT, AssertOp);
6296 MachineFunction& MF = SDB->DAG.getMachineFunction();
6297 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6298 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6299 FuncInfo->DemoteRegister = SRetReg;
6300 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6302 DAG.setRoot(NewRoot);
6304 // i indexes lowered arguments. Bump it past the hidden sret argument.
6305 // Idx indexes LLVM arguments. Don't touch it.
6309 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6311 SmallVector<SDValue, 4> ArgValues;
6312 SmallVector<EVT, 4> ValueVTs;
6313 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6314 unsigned NumValues = ValueVTs.size();
6316 // If this argument is unused then remember its value. It is used to generate
6317 // debugging information.
6318 if (I->use_empty() && NumValues)
6319 SDB->setUnusedArgValue(I, InVals[i]);
6321 for (unsigned Value = 0; Value != NumValues; ++Value) {
6322 EVT VT = ValueVTs[Value];
6323 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6324 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6326 if (!I->use_empty()) {
6327 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6328 if (F.paramHasAttr(Idx, Attribute::SExt))
6329 AssertOp = ISD::AssertSext;
6330 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6331 AssertOp = ISD::AssertZext;
6333 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6334 NumParts, PartVT, VT,
6341 // Note down frame index for byval arguments.
6342 if (I->hasByValAttr() && !ArgValues.empty())
6343 if (FrameIndexSDNode *FI =
6344 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6345 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6347 if (!I->use_empty()) {
6349 if (!ArgValues.empty())
6350 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6351 SDB->getCurDebugLoc());
6352 SDB->setValue(I, Res);
6354 // If this argument is live outside of the entry block, insert a copy from
6355 // whereever we got it to the vreg that other BB's will reference it as.
6356 SDB->CopyToExportRegsIfNeeded(I);
6360 assert(i == InVals.size() && "Argument register count mismatch!");
6362 // Finally, if the target has anything special to do, allow it to do so.
6363 // FIXME: this should insert code into the DAG!
6364 EmitFunctionEntryCode();
6367 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6368 /// ensure constants are generated when needed. Remember the virtual registers
6369 /// that need to be added to the Machine PHI nodes as input. We cannot just
6370 /// directly add them, because expansion might result in multiple MBB's for one
6371 /// BB. As such, the start of the BB might correspond to a different MBB than
6375 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6376 const TerminatorInst *TI = LLVMBB->getTerminator();
6378 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6380 // Check successor nodes' PHI nodes that expect a constant to be available
6382 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6383 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6384 if (!isa<PHINode>(SuccBB->begin())) continue;
6385 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6387 // If this terminator has multiple identical successors (common for
6388 // switches), only handle each succ once.
6389 if (!SuccsHandled.insert(SuccMBB)) continue;
6391 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6393 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6394 // nodes and Machine PHI nodes, but the incoming operands have not been
6396 for (BasicBlock::const_iterator I = SuccBB->begin();
6397 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6398 // Ignore dead phi's.
6399 if (PN->use_empty()) continue;
6402 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6404 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6405 unsigned &RegOut = ConstantsOut[C];
6407 RegOut = FuncInfo.CreateRegs(C->getType());
6408 CopyValueToVirtualRegister(C, RegOut);
6412 DenseMap<const Value *, unsigned>::iterator I =
6413 FuncInfo.ValueMap.find(PHIOp);
6414 if (I != FuncInfo.ValueMap.end())
6417 assert(isa<AllocaInst>(PHIOp) &&
6418 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6419 "Didn't codegen value into a register!??");
6420 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6421 CopyValueToVirtualRegister(PHIOp, Reg);
6425 // Remember that this register needs to added to the machine PHI node as
6426 // the input for this MBB.
6427 SmallVector<EVT, 4> ValueVTs;
6428 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6429 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6430 EVT VT = ValueVTs[vti];
6431 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6432 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6433 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6434 Reg += NumRegisters;
6438 ConstantsOut.clear();