1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "FunctionLoweringInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ConstantFolding.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/Module.h"
31 #include "llvm/CodeGen/FastISel.h"
32 #include "llvm/CodeGen/GCStrategy.h"
33 #include "llvm/CodeGen/GCMetadata.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineJumpTableInfo.h"
38 #include "llvm/CodeGen/MachineModuleInfo.h"
39 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/PseudoSourceValue.h"
41 #include "llvm/CodeGen/SelectionDAG.h"
42 #include "llvm/CodeGen/DwarfWriter.h"
43 #include "llvm/Analysis/DebugInfo.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetFrameInfo.h"
47 #include "llvm/Target/TargetInstrInfo.h"
48 #include "llvm/Target/TargetIntrinsicInfo.h"
49 #include "llvm/Target/TargetLowering.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MathExtras.h"
56 #include "llvm/Support/raw_ostream.h"
60 /// LimitFloatPrecision - Generate low-precision inline sequences for
61 /// some float libcalls (6, 8 or 12 bits).
62 static unsigned LimitFloatPrecision;
64 static cl::opt<unsigned, true>
65 LimitFPPrecision("limit-float-precision",
66 cl::desc("Generate low-precision inline sequences "
67 "for some float libcalls"),
68 cl::location(LimitFloatPrecision),
72 /// RegsForValue - This struct represents the registers (physical or virtual)
73 /// that a particular set of values is assigned, and the type information
74 /// about the value. The most common situation is to represent one value at a
75 /// time, but struct or array values are handled element-wise as multiple
76 /// values. The splitting of aggregates is performed recursively, so that we
77 /// never have aggregate-typed registers. The values at this point do not
78 /// necessarily have legal types, so each value may require one or more
79 /// registers of some legal type.
82 /// TLI - The TargetLowering object.
84 const TargetLowering *TLI;
86 /// ValueVTs - The value types of the values, which may not be legal, and
87 /// may need be promoted or synthesized from one or more registers.
89 SmallVector<EVT, 4> ValueVTs;
91 /// RegVTs - The value types of the registers. This is the same size as
92 /// ValueVTs and it records, for each value, what the type of the assigned
93 /// register or registers are. (Individual values are never synthesized
94 /// from more than one type of register.)
96 /// With virtual registers, the contents of RegVTs is redundant with TLI's
97 /// getRegisterType member function, however when with physical registers
98 /// it is necessary to have a separate record of the types.
100 SmallVector<EVT, 4> RegVTs;
102 /// Regs - This list holds the registers assigned to the values.
103 /// Each legal or promoted value requires one register, and each
104 /// expanded value requires multiple registers.
106 SmallVector<unsigned, 4> Regs;
108 RegsForValue() : TLI(0) {}
110 RegsForValue(const TargetLowering &tli,
111 const SmallVector<unsigned, 4> ®s,
112 EVT regvt, EVT valuevt)
113 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
114 RegsForValue(const TargetLowering &tli,
115 const SmallVector<unsigned, 4> ®s,
116 const SmallVector<EVT, 4> ®vts,
117 const SmallVector<EVT, 4> &valuevts)
118 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
119 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
120 unsigned Reg, const Type *Ty) : TLI(&tli) {
121 ComputeValueVTs(tli, Ty, ValueVTs);
123 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
124 EVT ValueVT = ValueVTs[Value];
125 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
126 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
127 for (unsigned i = 0; i != NumRegs; ++i)
128 Regs.push_back(Reg + i);
129 RegVTs.push_back(RegisterVT);
134 /// append - Add the specified values to this one.
135 void append(const RegsForValue &RHS) {
137 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
138 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
139 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
143 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
144 /// this value and returns the result as a ValueVTs value. This uses
145 /// Chain/Flag as the input and updates them for the output Chain/Flag.
146 /// If the Flag pointer is NULL, no flag is used.
147 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
148 SDValue &Chain, SDValue *Flag) const;
150 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
151 /// specified value into the registers specified by this object. This uses
152 /// Chain/Flag as the input and updates them for the output Chain/Flag.
153 /// If the Flag pointer is NULL, no flag is used.
154 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
155 unsigned Order, SDValue &Chain, SDValue *Flag) const;
157 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
158 /// operand list. This adds the code marker, matching input operand index
159 /// (if applicable), and includes the number of values added into it.
160 void AddInlineAsmOperands(unsigned Code,
161 bool HasMatching, unsigned MatchingIdx,
162 SelectionDAG &DAG, unsigned Order,
163 std::vector<SDValue> &Ops) const;
167 /// getCopyFromParts - Create a value that contains the specified legal parts
168 /// combined into the value they represent. If the parts combine to a type
169 /// larger then ValueVT then AssertOp can be used to specify whether the extra
170 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
171 /// (ISD::AssertSext).
172 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
173 const SDValue *Parts,
174 unsigned NumParts, EVT PartVT, EVT ValueVT,
175 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
176 assert(NumParts > 0 && "No parts to assemble!");
177 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
178 SDValue Val = Parts[0];
181 // Assemble the value from multiple parts.
182 if (!ValueVT.isVector() && ValueVT.isInteger()) {
183 unsigned PartBits = PartVT.getSizeInBits();
184 unsigned ValueBits = ValueVT.getSizeInBits();
186 // Assemble the power of 2 part.
187 unsigned RoundParts = NumParts & (NumParts - 1) ?
188 1 << Log2_32(NumParts) : NumParts;
189 unsigned RoundBits = PartBits * RoundParts;
190 EVT RoundVT = RoundBits == ValueBits ?
191 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
194 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
196 if (RoundParts > 2) {
197 Lo = getCopyFromParts(DAG, dl, Order, Parts, RoundParts / 2,
199 Hi = getCopyFromParts(DAG, dl, Order, Parts + RoundParts / 2,
200 RoundParts / 2, PartVT, HalfVT);
202 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
203 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
206 if (TLI.isBigEndian())
209 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
211 if (RoundParts < NumParts) {
212 // Assemble the trailing non-power-of-2 part.
213 unsigned OddParts = NumParts - RoundParts;
214 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
215 Hi = getCopyFromParts(DAG, dl, Order,
216 Parts + RoundParts, OddParts, PartVT, OddVT);
218 // Combine the round and odd parts.
220 if (TLI.isBigEndian())
222 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
223 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
224 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
225 DAG.getConstant(Lo.getValueType().getSizeInBits(),
226 TLI.getPointerTy()));
227 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
228 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
230 } else if (ValueVT.isVector()) {
231 // Handle a multi-element vector.
232 EVT IntermediateVT, RegisterVT;
233 unsigned NumIntermediates;
235 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
236 NumIntermediates, RegisterVT);
237 assert(NumRegs == NumParts
238 && "Part count doesn't match vector breakdown!");
239 NumParts = NumRegs; // Silence a compiler warning.
240 assert(RegisterVT == PartVT
241 && "Part type doesn't match vector breakdown!");
242 assert(RegisterVT == Parts[0].getValueType() &&
243 "Part type doesn't match part!");
245 // Assemble the parts into intermediate operands.
246 SmallVector<SDValue, 8> Ops(NumIntermediates);
247 if (NumIntermediates == NumParts) {
248 // If the register was not expanded, truncate or copy the value,
250 for (unsigned i = 0; i != NumParts; ++i)
251 Ops[i] = getCopyFromParts(DAG, dl, Order, &Parts[i], 1,
252 PartVT, IntermediateVT);
253 } else if (NumParts > 0) {
254 // If the intermediate type was expanded, build the intermediate
255 // operands from the parts.
256 assert(NumParts % NumIntermediates == 0 &&
257 "Must expand into a divisible number of parts!");
258 unsigned Factor = NumParts / NumIntermediates;
259 for (unsigned i = 0; i != NumIntermediates; ++i)
260 Ops[i] = getCopyFromParts(DAG, dl, Order, &Parts[i * Factor], Factor,
261 PartVT, IntermediateVT);
264 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
265 // intermediate operands.
266 Val = DAG.getNode(IntermediateVT.isVector() ?
267 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
268 ValueVT, &Ops[0], NumIntermediates);
269 } else if (PartVT.isFloatingPoint()) {
270 // FP split into multiple FP parts (for ppcf128)
271 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
274 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
275 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
276 if (TLI.isBigEndian())
278 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
280 // FP split into integer parts (soft fp)
281 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
282 !PartVT.isVector() && "Unexpected split");
283 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
284 Val = getCopyFromParts(DAG, dl, Order, Parts, NumParts, PartVT, IntVT);
288 // There is now one part, held in Val. Correct it to match ValueVT.
289 PartVT = Val.getValueType();
291 if (PartVT == ValueVT)
294 if (PartVT.isVector()) {
295 assert(ValueVT.isVector() && "Unknown vector conversion!");
296 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
299 if (ValueVT.isVector()) {
300 assert(ValueVT.getVectorElementType() == PartVT &&
301 ValueVT.getVectorNumElements() == 1 &&
302 "Only trivial scalar-to-vector conversions should get here!");
303 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
306 if (PartVT.isInteger() &&
307 ValueVT.isInteger()) {
308 if (ValueVT.bitsLT(PartVT)) {
309 // For a truncate, see if we have any information to
310 // indicate whether the truncated bits will always be
311 // zero or sign-extension.
312 if (AssertOp != ISD::DELETED_NODE)
313 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
314 DAG.getValueType(ValueVT));
315 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
317 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
321 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
322 if (ValueVT.bitsLT(Val.getValueType())) {
323 // FP_ROUND's are always exact here.
324 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
325 DAG.getIntPtrConstant(1));
328 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
331 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
332 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
334 llvm_unreachable("Unknown mismatch!");
338 /// getCopyToParts - Create a series of nodes that contain the specified value
339 /// split into legal parts. If the parts contain more bits than Val, then, for
340 /// integers, ExtendKind can be used to specify how to generate the extra bits.
341 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, unsigned Order,
342 SDValue Val, SDValue *Parts, unsigned NumParts,
344 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
346 EVT PtrVT = TLI.getPointerTy();
347 EVT ValueVT = Val.getValueType();
348 unsigned PartBits = PartVT.getSizeInBits();
349 unsigned OrigNumParts = NumParts;
350 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
355 if (!ValueVT.isVector()) {
356 if (PartVT == ValueVT) {
357 assert(NumParts == 1 && "No-op copy with multiple parts!");
362 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
363 // If the parts cover more bits than the value has, promote the value.
364 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
365 assert(NumParts == 1 && "Do not know what to promote to!");
366 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
367 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
368 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
369 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
371 llvm_unreachable("Unknown mismatch!");
373 } else if (PartBits == ValueVT.getSizeInBits()) {
374 // Different types of the same size.
375 assert(NumParts == 1 && PartVT != ValueVT);
376 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
377 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
378 // If the parts cover less bits than value has, truncate the value.
379 if (PartVT.isInteger() && ValueVT.isInteger()) {
380 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
381 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
383 llvm_unreachable("Unknown mismatch!");
387 // The value may have changed - recompute ValueVT.
388 ValueVT = Val.getValueType();
389 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
390 "Failed to tile the value with PartVT!");
393 assert(PartVT == ValueVT && "Type conversion failed!");
398 // Expand the value into multiple parts.
399 if (NumParts & (NumParts - 1)) {
400 // The number of parts is not a power of 2. Split off and copy the tail.
401 assert(PartVT.isInteger() && ValueVT.isInteger() &&
402 "Do not know what to expand to!");
403 unsigned RoundParts = 1 << Log2_32(NumParts);
404 unsigned RoundBits = RoundParts * PartBits;
405 unsigned OddParts = NumParts - RoundParts;
406 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
407 DAG.getConstant(RoundBits,
408 TLI.getPointerTy()));
409 getCopyToParts(DAG, dl, Order, OddVal, Parts + RoundParts,
412 if (TLI.isBigEndian())
413 // The odd parts were reversed by getCopyToParts - unreverse them.
414 std::reverse(Parts + RoundParts, Parts + NumParts);
416 NumParts = RoundParts;
417 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
418 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
421 // The number of parts is a power of 2. Repeatedly bisect the value using
423 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
424 EVT::getIntegerVT(*DAG.getContext(),
425 ValueVT.getSizeInBits()),
428 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
429 for (unsigned i = 0; i < NumParts; i += StepSize) {
430 unsigned ThisBits = StepSize * PartBits / 2;
431 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
432 SDValue &Part0 = Parts[i];
433 SDValue &Part1 = Parts[i+StepSize/2];
435 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
437 DAG.getConstant(1, PtrVT));
438 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
440 DAG.getConstant(0, PtrVT));
442 if (ThisBits == PartBits && ThisVT != PartVT) {
443 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
445 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
451 if (TLI.isBigEndian())
452 std::reverse(Parts, Parts + OrigNumParts);
459 if (PartVT != ValueVT) {
460 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
461 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
463 assert(ValueVT.getVectorElementType() == PartVT &&
464 ValueVT.getVectorNumElements() == 1 &&
465 "Only trivial vector-to-scalar conversions should get here!");
466 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
468 DAG.getConstant(0, PtrVT));
476 // Handle a multi-element vector.
477 EVT IntermediateVT, RegisterVT;
478 unsigned NumIntermediates;
479 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
480 IntermediateVT, NumIntermediates, RegisterVT);
481 unsigned NumElements = ValueVT.getVectorNumElements();
483 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
484 NumParts = NumRegs; // Silence a compiler warning.
485 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
487 // Split the vector into intermediate operands.
488 SmallVector<SDValue, 8> Ops(NumIntermediates);
489 for (unsigned i = 0; i != NumIntermediates; ++i) {
490 if (IntermediateVT.isVector())
491 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
493 DAG.getConstant(i * (NumElements / NumIntermediates),
496 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
498 DAG.getConstant(i, PtrVT));
501 // Split the intermediate operands into legal parts.
502 if (NumParts == NumIntermediates) {
503 // If the register was not expanded, promote or copy the value,
505 for (unsigned i = 0; i != NumParts; ++i)
506 getCopyToParts(DAG, dl, Order, Ops[i], &Parts[i], 1, PartVT);
507 } else if (NumParts > 0) {
508 // If the intermediate type was expanded, split each the value into
510 assert(NumParts % NumIntermediates == 0 &&
511 "Must expand into a divisible number of parts!");
512 unsigned Factor = NumParts / NumIntermediates;
513 for (unsigned i = 0; i != NumIntermediates; ++i)
514 getCopyToParts(DAG, dl, Order, Ops[i], &Parts[i*Factor], Factor, PartVT);
519 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
522 TD = DAG.getTarget().getTargetData();
525 /// clear - Clear out the curret SelectionDAG and the associated
526 /// state and prepare this SelectionDAGBuilder object to be used
527 /// for a new block. This doesn't clear out information about
528 /// additional blocks that are needed to complete switch lowering
529 /// or PHI node updating; that information is cleared out as it is
531 void SelectionDAGBuilder::clear() {
533 PendingLoads.clear();
534 PendingExports.clear();
537 CurDebugLoc = DebugLoc::getUnknownLoc();
541 /// getRoot - Return the current virtual root of the Selection DAG,
542 /// flushing any PendingLoad items. This must be done before emitting
543 /// a store or any other node that may need to be ordered after any
544 /// prior load instructions.
546 SDValue SelectionDAGBuilder::getRoot() {
547 if (PendingLoads.empty())
548 return DAG.getRoot();
550 if (PendingLoads.size() == 1) {
551 SDValue Root = PendingLoads[0];
553 PendingLoads.clear();
557 // Otherwise, we have to make a token factor node.
558 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
559 &PendingLoads[0], PendingLoads.size());
560 PendingLoads.clear();
565 /// getControlRoot - Similar to getRoot, but instead of flushing all the
566 /// PendingLoad items, flush all the PendingExports items. It is necessary
567 /// to do this before emitting a terminator instruction.
569 SDValue SelectionDAGBuilder::getControlRoot() {
570 SDValue Root = DAG.getRoot();
572 if (PendingExports.empty())
575 // Turn all of the CopyToReg chains into one factored node.
576 if (Root.getOpcode() != ISD::EntryToken) {
577 unsigned i = 0, e = PendingExports.size();
578 for (; i != e; ++i) {
579 assert(PendingExports[i].getNode()->getNumOperands() > 1);
580 if (PendingExports[i].getNode()->getOperand(0) == Root)
581 break; // Don't add the root if we already indirectly depend on it.
585 PendingExports.push_back(Root);
588 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
590 PendingExports.size());
591 PendingExports.clear();
596 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
597 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
598 DAG.AssignOrdering(Node, SDNodeOrder);
600 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
601 AssignOrderingToNode(Node->getOperand(I).getNode());
604 void SelectionDAGBuilder::visit(Instruction &I) {
605 visit(I.getOpcode(), I);
608 void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
609 // Note: this doesn't use InstVisitor, because it has to work with
610 // ConstantExpr's in addition to instructions.
612 default: llvm_unreachable("Unknown instruction type encountered!");
613 // Build the switch statement using the Instruction.def file.
614 #define HANDLE_INST(NUM, OPCODE, CLASS) \
615 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
616 #include "llvm/Instruction.def"
619 // Assign the ordering to the freshly created DAG nodes.
620 if (NodeMap.count(&I)) {
622 AssignOrderingToNode(getValue(&I).getNode());
626 SDValue SelectionDAGBuilder::getValue(const Value *V) {
627 SDValue &N = NodeMap[V];
628 if (N.getNode()) return N;
630 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
631 EVT VT = TLI.getValueType(V->getType(), true);
633 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
634 return N = DAG.getConstant(*CI, VT);
636 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
637 return N = DAG.getGlobalAddress(GV, VT);
639 if (isa<ConstantPointerNull>(C))
640 return N = DAG.getConstant(0, TLI.getPointerTy());
642 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
643 return N = DAG.getConstantFP(*CFP, VT);
645 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
646 return N = DAG.getUNDEF(VT);
648 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
649 visit(CE->getOpcode(), *CE);
650 SDValue N1 = NodeMap[V];
651 assert(N1.getNode() && "visit didn't populate the ValueMap!");
655 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
656 SmallVector<SDValue, 4> Constants;
657 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
659 SDNode *Val = getValue(*OI).getNode();
660 // If the operand is an empty aggregate, there are no values.
662 // Add each leaf value from the operand to the Constants list
663 // to form a flattened list of all the values.
664 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
665 Constants.push_back(SDValue(Val, i));
668 return DAG.getMergeValues(&Constants[0], Constants.size(),
672 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
673 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
674 "Unknown struct or array constant!");
676 SmallVector<EVT, 4> ValueVTs;
677 ComputeValueVTs(TLI, C->getType(), ValueVTs);
678 unsigned NumElts = ValueVTs.size();
680 return SDValue(); // empty struct
681 SmallVector<SDValue, 4> Constants(NumElts);
682 for (unsigned i = 0; i != NumElts; ++i) {
683 EVT EltVT = ValueVTs[i];
684 if (isa<UndefValue>(C))
685 Constants[i] = DAG.getUNDEF(EltVT);
686 else if (EltVT.isFloatingPoint())
687 Constants[i] = DAG.getConstantFP(0, EltVT);
689 Constants[i] = DAG.getConstant(0, EltVT);
692 return DAG.getMergeValues(&Constants[0], NumElts,
696 if (BlockAddress *BA = dyn_cast<BlockAddress>(C))
697 return DAG.getBlockAddress(BA, VT);
699 const VectorType *VecTy = cast<VectorType>(V->getType());
700 unsigned NumElements = VecTy->getNumElements();
702 // Now that we know the number and type of the elements, get that number of
703 // elements into the Ops array based on what kind of constant it is.
704 SmallVector<SDValue, 16> Ops;
705 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
706 for (unsigned i = 0; i != NumElements; ++i)
707 Ops.push_back(getValue(CP->getOperand(i)));
709 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
710 EVT EltVT = TLI.getValueType(VecTy->getElementType());
713 if (EltVT.isFloatingPoint())
714 Op = DAG.getConstantFP(0, EltVT);
716 Op = DAG.getConstant(0, EltVT);
717 Ops.assign(NumElements, Op);
720 // Create a BUILD_VECTOR node.
721 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
722 VT, &Ops[0], Ops.size());
725 // If this is a static alloca, generate it as the frameindex instead of
727 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
728 DenseMap<const AllocaInst*, int>::iterator SI =
729 FuncInfo.StaticAllocaMap.find(AI);
730 if (SI != FuncInfo.StaticAllocaMap.end())
731 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
734 unsigned InReg = FuncInfo.ValueMap[V];
735 assert(InReg && "Value not in map!");
737 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
738 SDValue Chain = DAG.getEntryNode();
739 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(),
740 SDNodeOrder, Chain, NULL);
743 /// Get the EVTs and ArgFlags collections that represent the legalized return
744 /// type of the given function. This does not require a DAG or a return value,
745 /// and is suitable for use before any DAGs for the function are constructed.
746 static void getReturnInfo(const Type* ReturnType,
747 Attributes attr, SmallVectorImpl<EVT> &OutVTs,
748 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
750 SmallVectorImpl<uint64_t> *Offsets = 0) {
751 SmallVector<EVT, 4> ValueVTs;
752 ComputeValueVTs(TLI, ReturnType, ValueVTs);
753 unsigned NumValues = ValueVTs.size();
754 if (NumValues == 0) return;
757 for (unsigned j = 0, f = NumValues; j != f; ++j) {
758 EVT VT = ValueVTs[j];
759 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
761 if (attr & Attribute::SExt)
762 ExtendKind = ISD::SIGN_EXTEND;
763 else if (attr & Attribute::ZExt)
764 ExtendKind = ISD::ZERO_EXTEND;
766 // FIXME: C calling convention requires the return type to be promoted to
767 // at least 32-bit. But this is not necessary for non-C calling
768 // conventions. The frontend should mark functions whose return values
769 // require promoting with signext or zeroext attributes.
770 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
771 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
772 if (VT.bitsLT(MinVT))
776 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
777 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
778 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
779 PartVT.getTypeForEVT(ReturnType->getContext()));
781 // 'inreg' on function refers to return value
782 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
783 if (attr & Attribute::InReg)
786 // Propagate extension type if any
787 if (attr & Attribute::SExt)
789 else if (attr & Attribute::ZExt)
792 for (unsigned i = 0; i < NumParts; ++i) {
793 OutVTs.push_back(PartVT);
794 OutFlags.push_back(Flags);
797 Offsets->push_back(Offset);
804 void SelectionDAGBuilder::visitRet(ReturnInst &I) {
805 SDValue Chain = getControlRoot();
806 SmallVector<ISD::OutputArg, 8> Outs;
807 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
809 if (!FLI.CanLowerReturn) {
810 unsigned DemoteReg = FLI.DemoteRegister;
811 const Function *F = I.getParent()->getParent();
813 // Emit a store of the return value through the virtual register.
814 // Leave Outs empty so that LowerReturn won't try to load return
815 // registers the usual way.
816 SmallVector<EVT, 1> PtrValueVTs;
817 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
820 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
821 SDValue RetOp = getValue(I.getOperand(0));
823 SmallVector<EVT, 4> ValueVTs;
824 SmallVector<uint64_t, 4> Offsets;
825 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
826 unsigned NumValues = ValueVTs.size();
828 SmallVector<SDValue, 4> Chains(NumValues);
829 EVT PtrVT = PtrValueVTs[0];
830 for (unsigned i = 0; i != NumValues; ++i) {
831 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
832 DAG.getConstant(Offsets[i], PtrVT));
834 DAG.getStore(Chain, getCurDebugLoc(),
835 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
836 Add, NULL, Offsets[i], false, 0);
839 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
840 MVT::Other, &Chains[0], NumValues);
842 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
843 SmallVector<EVT, 4> ValueVTs;
844 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
845 unsigned NumValues = ValueVTs.size();
846 if (NumValues == 0) continue;
848 SDValue RetOp = getValue(I.getOperand(i));
849 for (unsigned j = 0, f = NumValues; j != f; ++j) {
850 EVT VT = ValueVTs[j];
852 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
854 const Function *F = I.getParent()->getParent();
855 if (F->paramHasAttr(0, Attribute::SExt))
856 ExtendKind = ISD::SIGN_EXTEND;
857 else if (F->paramHasAttr(0, Attribute::ZExt))
858 ExtendKind = ISD::ZERO_EXTEND;
860 // FIXME: C calling convention requires the return type to be promoted
861 // to at least 32-bit. But this is not necessary for non-C calling
862 // conventions. The frontend should mark functions whose return values
863 // require promoting with signext or zeroext attributes.
864 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
865 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
866 if (VT.bitsLT(MinVT))
870 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
871 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
872 SmallVector<SDValue, 4> Parts(NumParts);
873 getCopyToParts(DAG, getCurDebugLoc(), SDNodeOrder,
874 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
875 &Parts[0], NumParts, PartVT, ExtendKind);
877 // 'inreg' on function refers to return value
878 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
879 if (F->paramHasAttr(0, Attribute::InReg))
882 // Propagate extension type if any
883 if (F->paramHasAttr(0, Attribute::SExt))
885 else if (F->paramHasAttr(0, Attribute::ZExt))
888 for (unsigned i = 0; i < NumParts; ++i)
889 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
894 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
895 CallingConv::ID CallConv =
896 DAG.getMachineFunction().getFunction()->getCallingConv();
897 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
898 Outs, getCurDebugLoc(), DAG);
900 // Verify that the target's LowerReturn behaved as expected.
901 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
902 "LowerReturn didn't return a valid chain!");
904 // Update the DAG with the new chain value resulting from return lowering.
908 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
909 /// created for it, emit nodes to copy the value into the virtual
911 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(Value *V) {
912 if (!V->use_empty()) {
913 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
914 if (VMI != FuncInfo.ValueMap.end())
915 CopyValueToVirtualRegister(V, VMI->second);
919 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
920 /// the current basic block, add it to ValueMap now so that we'll get a
922 void SelectionDAGBuilder::ExportFromCurrentBlock(Value *V) {
923 // No need to export constants.
924 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
927 if (FuncInfo.isExportedInst(V)) return;
929 unsigned Reg = FuncInfo.InitializeRegForValue(V);
930 CopyValueToVirtualRegister(V, Reg);
933 bool SelectionDAGBuilder::isExportableFromCurrentBlock(Value *V,
934 const BasicBlock *FromBB) {
935 // The operands of the setcc have to be in this block. We don't know
936 // how to export them from some other block.
937 if (Instruction *VI = dyn_cast<Instruction>(V)) {
938 // Can export from current BB.
939 if (VI->getParent() == FromBB)
942 // Is already exported, noop.
943 return FuncInfo.isExportedInst(V);
946 // If this is an argument, we can export it if the BB is the entry block or
947 // if it is already exported.
948 if (isa<Argument>(V)) {
949 if (FromBB == &FromBB->getParent()->getEntryBlock())
952 // Otherwise, can only export this if it is already exported.
953 return FuncInfo.isExportedInst(V);
956 // Otherwise, constants can always be exported.
960 static bool InBlock(const Value *V, const BasicBlock *BB) {
961 if (const Instruction *I = dyn_cast<Instruction>(V))
962 return I->getParent() == BB;
966 /// getFCmpCondCode - Return the ISD condition code corresponding to
967 /// the given LLVM IR floating-point condition code. This includes
968 /// consideration of global floating-point math flags.
970 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
971 ISD::CondCode FPC, FOC;
973 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
974 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
975 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
976 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
977 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
978 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
979 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
980 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
981 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
982 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
983 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
984 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
985 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
986 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
987 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
988 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
990 llvm_unreachable("Invalid FCmp predicate opcode!");
991 FOC = FPC = ISD::SETFALSE;
994 if (FiniteOnlyFPMath())
1000 /// getICmpCondCode - Return the ISD condition code corresponding to
1001 /// the given LLVM IR integer condition code.
1003 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1005 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1006 case ICmpInst::ICMP_NE: return ISD::SETNE;
1007 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1008 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1009 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1010 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1011 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1012 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1013 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1014 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1016 llvm_unreachable("Invalid ICmp predicate opcode!");
1021 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1022 /// This function emits a branch and is used at the leaves of an OR or an
1023 /// AND operator tree.
1026 SelectionDAGBuilder::EmitBranchForMergedCondition(Value *Cond,
1027 MachineBasicBlock *TBB,
1028 MachineBasicBlock *FBB,
1029 MachineBasicBlock *CurBB) {
1030 const BasicBlock *BB = CurBB->getBasicBlock();
1032 // If the leaf of the tree is a comparison, merge the condition into
1034 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1035 // The operands of the cmp have to be in this block. We don't know
1036 // how to export them from some other block. If this is the first block
1037 // of the sequence, no exporting is needed.
1038 if (CurBB == CurMBB ||
1039 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1040 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1041 ISD::CondCode Condition;
1042 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1043 Condition = getICmpCondCode(IC->getPredicate());
1044 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1045 Condition = getFCmpCondCode(FC->getPredicate());
1047 Condition = ISD::SETEQ; // silence warning.
1048 llvm_unreachable("Unknown compare instruction");
1051 CaseBlock CB(Condition, BOp->getOperand(0),
1052 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1053 SwitchCases.push_back(CB);
1058 // Create a CaseBlock record representing this branch.
1059 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1060 NULL, TBB, FBB, CurBB);
1061 SwitchCases.push_back(CB);
1064 /// FindMergedConditions - If Cond is an expression like
1065 void SelectionDAGBuilder::FindMergedConditions(Value *Cond,
1066 MachineBasicBlock *TBB,
1067 MachineBasicBlock *FBB,
1068 MachineBasicBlock *CurBB,
1070 // If this node is not part of the or/and tree, emit it as a branch.
1071 Instruction *BOp = dyn_cast<Instruction>(Cond);
1072 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1073 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1074 BOp->getParent() != CurBB->getBasicBlock() ||
1075 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1076 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1077 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1081 // Create TmpBB after CurBB.
1082 MachineFunction::iterator BBI = CurBB;
1083 MachineFunction &MF = DAG.getMachineFunction();
1084 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1085 CurBB->getParent()->insert(++BBI, TmpBB);
1087 if (Opc == Instruction::Or) {
1088 // Codegen X | Y as:
1096 // Emit the LHS condition.
1097 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1099 // Emit the RHS condition into TmpBB.
1100 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1102 assert(Opc == Instruction::And && "Unknown merge op!");
1103 // Codegen X & Y as:
1110 // This requires creation of TmpBB after CurBB.
1112 // Emit the LHS condition.
1113 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1115 // Emit the RHS condition into TmpBB.
1116 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1120 /// If the set of cases should be emitted as a series of branches, return true.
1121 /// If we should emit this as a bunch of and/or'd together conditions, return
1124 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1125 if (Cases.size() != 2) return true;
1127 // If this is two comparisons of the same values or'd or and'd together, they
1128 // will get folded into a single comparison, so don't emit two blocks.
1129 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1130 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1131 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1132 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1136 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1137 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1138 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1139 Cases[0].CC == Cases[1].CC &&
1140 isa<Constant>(Cases[0].CmpRHS) &&
1141 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1142 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1144 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1151 void SelectionDAGBuilder::visitBr(BranchInst &I) {
1152 // Update machine-CFG edges.
1153 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1155 // Figure out which block is immediately after the current one.
1156 MachineBasicBlock *NextBlock = 0;
1157 MachineFunction::iterator BBI = CurMBB;
1158 if (++BBI != FuncInfo.MF->end())
1161 if (I.isUnconditional()) {
1162 // Update machine-CFG edges.
1163 CurMBB->addSuccessor(Succ0MBB);
1165 // If this is not a fall-through branch, emit the branch.
1166 if (Succ0MBB != NextBlock)
1167 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1168 MVT::Other, getControlRoot(),
1169 DAG.getBasicBlock(Succ0MBB)));
1174 // If this condition is one of the special cases we handle, do special stuff
1176 Value *CondVal = I.getCondition();
1177 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1179 // If this is a series of conditions that are or'd or and'd together, emit
1180 // this as a sequence of branches instead of setcc's with and/or operations.
1181 // For example, instead of something like:
1194 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1195 if (BOp->hasOneUse() &&
1196 (BOp->getOpcode() == Instruction::And ||
1197 BOp->getOpcode() == Instruction::Or)) {
1198 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1199 // If the compares in later blocks need to use values not currently
1200 // exported from this block, export them now. This block should always
1201 // be the first entry.
1202 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1204 // Allow some cases to be rejected.
1205 if (ShouldEmitAsBranches(SwitchCases)) {
1206 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1207 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1208 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1211 // Emit the branch for this block.
1212 visitSwitchCase(SwitchCases[0]);
1213 SwitchCases.erase(SwitchCases.begin());
1217 // Okay, we decided not to do this, remove any inserted MBB's and clear
1219 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1220 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1222 SwitchCases.clear();
1226 // Create a CaseBlock record representing this branch.
1227 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1228 NULL, Succ0MBB, Succ1MBB, CurMBB);
1230 // Use visitSwitchCase to actually insert the fast branch sequence for this
1232 visitSwitchCase(CB);
1235 /// visitSwitchCase - Emits the necessary code to represent a single node in
1236 /// the binary search tree resulting from lowering a switch instruction.
1237 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
1239 SDValue CondLHS = getValue(CB.CmpLHS);
1240 DebugLoc dl = getCurDebugLoc();
1242 // Build the setcc now.
1243 if (CB.CmpMHS == NULL) {
1244 // Fold "(X == true)" to X and "(X == false)" to !X to
1245 // handle common cases produced by branch lowering.
1246 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1247 CB.CC == ISD::SETEQ)
1249 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1250 CB.CC == ISD::SETEQ) {
1251 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1252 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1254 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1256 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1258 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1259 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1261 SDValue CmpOp = getValue(CB.CmpMHS);
1262 EVT VT = CmpOp.getValueType();
1264 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1265 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1268 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1269 VT, CmpOp, DAG.getConstant(Low, VT));
1270 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1271 DAG.getConstant(High-Low, VT), ISD::SETULE);
1275 // Update successor info
1276 CurMBB->addSuccessor(CB.TrueBB);
1277 CurMBB->addSuccessor(CB.FalseBB);
1279 // Set NextBlock to be the MBB immediately after the current one, if any.
1280 // This is used to avoid emitting unnecessary branches to the next block.
1281 MachineBasicBlock *NextBlock = 0;
1282 MachineFunction::iterator BBI = CurMBB;
1283 if (++BBI != FuncInfo.MF->end())
1286 // If the lhs block is the next block, invert the condition so that we can
1287 // fall through to the lhs instead of the rhs block.
1288 if (CB.TrueBB == NextBlock) {
1289 std::swap(CB.TrueBB, CB.FalseBB);
1290 SDValue True = DAG.getConstant(1, Cond.getValueType());
1291 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1294 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1295 MVT::Other, getControlRoot(), Cond,
1296 DAG.getBasicBlock(CB.TrueBB));
1298 // If the branch was constant folded, fix up the CFG.
1299 if (BrCond.getOpcode() == ISD::BR) {
1300 CurMBB->removeSuccessor(CB.FalseBB);
1302 // Otherwise, go ahead and insert the false branch.
1303 if (BrCond == getControlRoot())
1304 CurMBB->removeSuccessor(CB.TrueBB);
1306 if (CB.FalseBB != NextBlock)
1307 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1308 DAG.getBasicBlock(CB.FalseBB));
1311 DAG.setRoot(BrCond);
1314 /// visitJumpTable - Emit JumpTable node in the current MBB
1315 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1316 // Emit the code for the jump table
1317 assert(JT.Reg != -1U && "Should lower JT Header first!");
1318 EVT PTy = TLI.getPointerTy();
1319 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1321 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1322 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1323 MVT::Other, Index.getValue(1),
1325 DAG.setRoot(BrJumpTable);
1328 /// visitJumpTableHeader - This function emits necessary code to produce index
1329 /// in the JumpTable from switch case.
1330 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1331 JumpTableHeader &JTH) {
1332 // Subtract the lowest switch case value from the value being switched on and
1333 // conditional branch to default mbb if the result is greater than the
1334 // difference between smallest and largest cases.
1335 SDValue SwitchOp = getValue(JTH.SValue);
1336 EVT VT = SwitchOp.getValueType();
1337 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1338 DAG.getConstant(JTH.First, VT));
1340 // The SDNode we just created, which holds the value being switched on minus
1341 // the the smallest case value, needs to be copied to a virtual register so it
1342 // can be used as an index into the jump table in a subsequent basic block.
1343 // This value may be smaller or larger than the target's pointer type, and
1344 // therefore require extension or truncating.
1345 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1347 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1348 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1349 JumpTableReg, SwitchOp);
1350 JT.Reg = JumpTableReg;
1352 // Emit the range check for the jump table, and branch to the default block
1353 // for the switch statement if the value being switched on exceeds the largest
1354 // case in the switch.
1355 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1356 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1357 DAG.getConstant(JTH.Last-JTH.First,VT),
1360 // Set NextBlock to be the MBB immediately after the current one, if any.
1361 // This is used to avoid emitting unnecessary branches to the next block.
1362 MachineBasicBlock *NextBlock = 0;
1363 MachineFunction::iterator BBI = CurMBB;
1365 if (++BBI != FuncInfo.MF->end())
1368 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1369 MVT::Other, CopyTo, CMP,
1370 DAG.getBasicBlock(JT.Default));
1372 if (JT.MBB != NextBlock)
1373 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1374 DAG.getBasicBlock(JT.MBB));
1376 DAG.setRoot(BrCond);
1379 /// visitBitTestHeader - This function emits necessary code to produce value
1380 /// suitable for "bit tests"
1381 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
1382 // Subtract the minimum value
1383 SDValue SwitchOp = getValue(B.SValue);
1384 EVT VT = SwitchOp.getValueType();
1385 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1386 DAG.getConstant(B.First, VT));
1389 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1390 TLI.getSetCCResultType(Sub.getValueType()),
1391 Sub, DAG.getConstant(B.Range, VT),
1394 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1395 TLI.getPointerTy());
1397 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1398 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1401 // Set NextBlock to be the MBB immediately after the current one, if any.
1402 // This is used to avoid emitting unnecessary branches to the next block.
1403 MachineBasicBlock *NextBlock = 0;
1404 MachineFunction::iterator BBI = CurMBB;
1405 if (++BBI != FuncInfo.MF->end())
1408 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1410 CurMBB->addSuccessor(B.Default);
1411 CurMBB->addSuccessor(MBB);
1413 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1414 MVT::Other, CopyTo, RangeCmp,
1415 DAG.getBasicBlock(B.Default));
1417 if (MBB != NextBlock)
1418 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1419 DAG.getBasicBlock(MBB));
1421 DAG.setRoot(BrRange);
1424 /// visitBitTestCase - this function produces one "bit test"
1425 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1428 // Make desired shift
1429 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1430 TLI.getPointerTy());
1431 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1433 DAG.getConstant(1, TLI.getPointerTy()),
1436 // Emit bit tests and jumps
1437 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1438 TLI.getPointerTy(), SwitchVal,
1439 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1440 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1441 TLI.getSetCCResultType(AndOp.getValueType()),
1442 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1445 CurMBB->addSuccessor(B.TargetBB);
1446 CurMBB->addSuccessor(NextMBB);
1448 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1449 MVT::Other, getControlRoot(),
1450 AndCmp, DAG.getBasicBlock(B.TargetBB));
1452 // Set NextBlock to be the MBB immediately after the current one, if any.
1453 // This is used to avoid emitting unnecessary branches to the next block.
1454 MachineBasicBlock *NextBlock = 0;
1455 MachineFunction::iterator BBI = CurMBB;
1456 if (++BBI != FuncInfo.MF->end())
1459 if (NextMBB != NextBlock)
1460 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1461 DAG.getBasicBlock(NextMBB));
1466 void SelectionDAGBuilder::visitInvoke(InvokeInst &I) {
1467 // Retrieve successors.
1468 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1469 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1471 const Value *Callee(I.getCalledValue());
1472 if (isa<InlineAsm>(Callee))
1475 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1477 // If the value of the invoke is used outside of its defining block, make it
1478 // available as a virtual register.
1479 CopyToExportRegsIfNeeded(&I);
1481 // Update successor info
1482 CurMBB->addSuccessor(Return);
1483 CurMBB->addSuccessor(LandingPad);
1485 // Drop into normal successor.
1486 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1487 MVT::Other, getControlRoot(),
1488 DAG.getBasicBlock(Return)));
1491 void SelectionDAGBuilder::visitUnwind(UnwindInst &I) {
1494 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1495 /// small case ranges).
1496 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1497 CaseRecVector& WorkList,
1499 MachineBasicBlock* Default) {
1500 Case& BackCase = *(CR.Range.second-1);
1502 // Size is the number of Cases represented by this range.
1503 size_t Size = CR.Range.second - CR.Range.first;
1507 // Get the MachineFunction which holds the current MBB. This is used when
1508 // inserting any additional MBBs necessary to represent the switch.
1509 MachineFunction *CurMF = FuncInfo.MF;
1511 // Figure out which block is immediately after the current one.
1512 MachineBasicBlock *NextBlock = 0;
1513 MachineFunction::iterator BBI = CR.CaseBB;
1515 if (++BBI != FuncInfo.MF->end())
1518 // TODO: If any two of the cases has the same destination, and if one value
1519 // is the same as the other, but has one bit unset that the other has set,
1520 // use bit manipulation to do two compares at once. For example:
1521 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1523 // Rearrange the case blocks so that the last one falls through if possible.
1524 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1525 // The last case block won't fall through into 'NextBlock' if we emit the
1526 // branches in this order. See if rearranging a case value would help.
1527 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1528 if (I->BB == NextBlock) {
1529 std::swap(*I, BackCase);
1535 // Create a CaseBlock record representing a conditional branch to
1536 // the Case's target mbb if the value being switched on SV is equal
1538 MachineBasicBlock *CurBlock = CR.CaseBB;
1539 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1540 MachineBasicBlock *FallThrough;
1542 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1543 CurMF->insert(BBI, FallThrough);
1545 // Put SV in a virtual register to make it available from the new blocks.
1546 ExportFromCurrentBlock(SV);
1548 // If the last case doesn't match, go to the default block.
1549 FallThrough = Default;
1552 Value *RHS, *LHS, *MHS;
1554 if (I->High == I->Low) {
1555 // This is just small small case range :) containing exactly 1 case
1557 LHS = SV; RHS = I->High; MHS = NULL;
1560 LHS = I->Low; MHS = SV; RHS = I->High;
1562 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1564 // If emitting the first comparison, just call visitSwitchCase to emit the
1565 // code into the current block. Otherwise, push the CaseBlock onto the
1566 // vector to be later processed by SDISel, and insert the node's MBB
1567 // before the next MBB.
1568 if (CurBlock == CurMBB)
1569 visitSwitchCase(CB);
1571 SwitchCases.push_back(CB);
1573 CurBlock = FallThrough;
1579 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1580 return !DisableJumpTables &&
1581 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1582 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1585 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1586 APInt LastExt(Last), FirstExt(First);
1587 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1588 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1589 return (LastExt - FirstExt + 1ULL);
1592 /// handleJTSwitchCase - Emit jumptable for current switch case range
1593 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1594 CaseRecVector& WorkList,
1596 MachineBasicBlock* Default) {
1597 Case& FrontCase = *CR.Range.first;
1598 Case& BackCase = *(CR.Range.second-1);
1600 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1601 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1603 APInt TSize(First.getBitWidth(), 0);
1604 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1608 if (!areJTsAllowed(TLI) || TSize.ult(APInt(First.getBitWidth(), 4)))
1611 APInt Range = ComputeRange(First, Last);
1612 double Density = TSize.roundToDouble() / Range.roundToDouble();
1616 DEBUG(dbgs() << "Lowering jump table\n"
1617 << "First entry: " << First << ". Last entry: " << Last << '\n'
1618 << "Range: " << Range
1619 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1621 // Get the MachineFunction which holds the current MBB. This is used when
1622 // inserting any additional MBBs necessary to represent the switch.
1623 MachineFunction *CurMF = FuncInfo.MF;
1625 // Figure out which block is immediately after the current one.
1626 MachineFunction::iterator BBI = CR.CaseBB;
1629 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1631 // Create a new basic block to hold the code for loading the address
1632 // of the jump table, and jumping to it. Update successor information;
1633 // we will either branch to the default case for the switch, or the jump
1635 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1636 CurMF->insert(BBI, JumpTableBB);
1637 CR.CaseBB->addSuccessor(Default);
1638 CR.CaseBB->addSuccessor(JumpTableBB);
1640 // Build a vector of destination BBs, corresponding to each target
1641 // of the jump table. If the value of the jump table slot corresponds to
1642 // a case statement, push the case's BB onto the vector, otherwise, push
1644 std::vector<MachineBasicBlock*> DestBBs;
1646 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1647 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1648 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1650 if (Low.sle(TEI) && TEI.sle(High)) {
1651 DestBBs.push_back(I->BB);
1655 DestBBs.push_back(Default);
1659 // Update successor info. Add one edge to each unique successor.
1660 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1661 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1662 E = DestBBs.end(); I != E; ++I) {
1663 if (!SuccsHandled[(*I)->getNumber()]) {
1664 SuccsHandled[(*I)->getNumber()] = true;
1665 JumpTableBB->addSuccessor(*I);
1669 // Create a jump table index for this jump table, or return an existing
1671 unsigned JTEncoding = TLI.getJumpTableEncoding();
1672 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1673 ->getJumpTableIndex(DestBBs);
1675 // Set the jump table information so that we can codegen it as a second
1676 // MachineBasicBlock
1677 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1678 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1679 if (CR.CaseBB == CurMBB)
1680 visitJumpTableHeader(JT, JTH);
1682 JTCases.push_back(JumpTableBlock(JTH, JT));
1687 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1689 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1690 CaseRecVector& WorkList,
1692 MachineBasicBlock* Default) {
1693 // Get the MachineFunction which holds the current MBB. This is used when
1694 // inserting any additional MBBs necessary to represent the switch.
1695 MachineFunction *CurMF = FuncInfo.MF;
1697 // Figure out which block is immediately after the current one.
1698 MachineFunction::iterator BBI = CR.CaseBB;
1701 Case& FrontCase = *CR.Range.first;
1702 Case& BackCase = *(CR.Range.second-1);
1703 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1705 // Size is the number of Cases represented by this range.
1706 unsigned Size = CR.Range.second - CR.Range.first;
1708 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1709 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1711 CaseItr Pivot = CR.Range.first + Size/2;
1713 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1714 // (heuristically) allow us to emit JumpTable's later.
1715 APInt TSize(First.getBitWidth(), 0);
1716 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1720 APInt LSize = FrontCase.size();
1721 APInt RSize = TSize-LSize;
1722 DEBUG(dbgs() << "Selecting best pivot: \n"
1723 << "First: " << First << ", Last: " << Last <<'\n'
1724 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1725 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1727 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1728 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1729 APInt Range = ComputeRange(LEnd, RBegin);
1730 assert((Range - 2ULL).isNonNegative() &&
1731 "Invalid case distance");
1732 double LDensity = (double)LSize.roundToDouble() /
1733 (LEnd - First + 1ULL).roundToDouble();
1734 double RDensity = (double)RSize.roundToDouble() /
1735 (Last - RBegin + 1ULL).roundToDouble();
1736 double Metric = Range.logBase2()*(LDensity+RDensity);
1737 // Should always split in some non-trivial place
1738 DEBUG(dbgs() <<"=>Step\n"
1739 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1740 << "LDensity: " << LDensity
1741 << ", RDensity: " << RDensity << '\n'
1742 << "Metric: " << Metric << '\n');
1743 if (FMetric < Metric) {
1746 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1752 if (areJTsAllowed(TLI)) {
1753 // If our case is dense we *really* should handle it earlier!
1754 assert((FMetric > 0) && "Should handle dense range earlier!");
1756 Pivot = CR.Range.first + Size/2;
1759 CaseRange LHSR(CR.Range.first, Pivot);
1760 CaseRange RHSR(Pivot, CR.Range.second);
1761 Constant *C = Pivot->Low;
1762 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1764 // We know that we branch to the LHS if the Value being switched on is
1765 // less than the Pivot value, C. We use this to optimize our binary
1766 // tree a bit, by recognizing that if SV is greater than or equal to the
1767 // LHS's Case Value, and that Case Value is exactly one less than the
1768 // Pivot's Value, then we can branch directly to the LHS's Target,
1769 // rather than creating a leaf node for it.
1770 if ((LHSR.second - LHSR.first) == 1 &&
1771 LHSR.first->High == CR.GE &&
1772 cast<ConstantInt>(C)->getValue() ==
1773 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1774 TrueBB = LHSR.first->BB;
1776 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1777 CurMF->insert(BBI, TrueBB);
1778 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1780 // Put SV in a virtual register to make it available from the new blocks.
1781 ExportFromCurrentBlock(SV);
1784 // Similar to the optimization above, if the Value being switched on is
1785 // known to be less than the Constant CR.LT, and the current Case Value
1786 // is CR.LT - 1, then we can branch directly to the target block for
1787 // the current Case Value, rather than emitting a RHS leaf node for it.
1788 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1789 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1790 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1791 FalseBB = RHSR.first->BB;
1793 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1794 CurMF->insert(BBI, FalseBB);
1795 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1797 // Put SV in a virtual register to make it available from the new blocks.
1798 ExportFromCurrentBlock(SV);
1801 // Create a CaseBlock record representing a conditional branch to
1802 // the LHS node if the value being switched on SV is less than C.
1803 // Otherwise, branch to LHS.
1804 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1806 if (CR.CaseBB == CurMBB)
1807 visitSwitchCase(CB);
1809 SwitchCases.push_back(CB);
1814 /// handleBitTestsSwitchCase - if current case range has few destination and
1815 /// range span less, than machine word bitwidth, encode case range into series
1816 /// of masks and emit bit tests with these masks.
1817 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1818 CaseRecVector& WorkList,
1820 MachineBasicBlock* Default){
1821 EVT PTy = TLI.getPointerTy();
1822 unsigned IntPtrBits = PTy.getSizeInBits();
1824 Case& FrontCase = *CR.Range.first;
1825 Case& BackCase = *(CR.Range.second-1);
1827 // Get the MachineFunction which holds the current MBB. This is used when
1828 // inserting any additional MBBs necessary to represent the switch.
1829 MachineFunction *CurMF = FuncInfo.MF;
1831 // If target does not have legal shift left, do not emit bit tests at all.
1832 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1836 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1838 // Single case counts one, case range - two.
1839 numCmps += (I->Low == I->High ? 1 : 2);
1842 // Count unique destinations
1843 SmallSet<MachineBasicBlock*, 4> Dests;
1844 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1845 Dests.insert(I->BB);
1846 if (Dests.size() > 3)
1847 // Don't bother the code below, if there are too much unique destinations
1850 DEBUG(dbgs() << "Total number of unique destinations: "
1851 << Dests.size() << '\n'
1852 << "Total number of comparisons: " << numCmps << '\n');
1854 // Compute span of values.
1855 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1856 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1857 APInt cmpRange = maxValue - minValue;
1859 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
1860 << "Low bound: " << minValue << '\n'
1861 << "High bound: " << maxValue << '\n');
1863 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1864 (!(Dests.size() == 1 && numCmps >= 3) &&
1865 !(Dests.size() == 2 && numCmps >= 5) &&
1866 !(Dests.size() >= 3 && numCmps >= 6)))
1869 DEBUG(dbgs() << "Emitting bit tests\n");
1870 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1872 // Optimize the case where all the case values fit in a
1873 // word without having to subtract minValue. In this case,
1874 // we can optimize away the subtraction.
1875 if (minValue.isNonNegative() &&
1876 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1877 cmpRange = maxValue;
1879 lowBound = minValue;
1882 CaseBitsVector CasesBits;
1883 unsigned i, count = 0;
1885 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1886 MachineBasicBlock* Dest = I->BB;
1887 for (i = 0; i < count; ++i)
1888 if (Dest == CasesBits[i].BB)
1892 assert((count < 3) && "Too much destinations to test!");
1893 CasesBits.push_back(CaseBits(0, Dest, 0));
1897 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1898 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1900 uint64_t lo = (lowValue - lowBound).getZExtValue();
1901 uint64_t hi = (highValue - lowBound).getZExtValue();
1903 for (uint64_t j = lo; j <= hi; j++) {
1904 CasesBits[i].Mask |= 1ULL << j;
1905 CasesBits[i].Bits++;
1909 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1913 // Figure out which block is immediately after the current one.
1914 MachineFunction::iterator BBI = CR.CaseBB;
1917 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1919 DEBUG(dbgs() << "Cases:\n");
1920 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1921 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
1922 << ", Bits: " << CasesBits[i].Bits
1923 << ", BB: " << CasesBits[i].BB << '\n');
1925 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1926 CurMF->insert(BBI, CaseBB);
1927 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1931 // Put SV in a virtual register to make it available from the new blocks.
1932 ExportFromCurrentBlock(SV);
1935 BitTestBlock BTB(lowBound, cmpRange, SV,
1936 -1U, (CR.CaseBB == CurMBB),
1937 CR.CaseBB, Default, BTC);
1939 if (CR.CaseBB == CurMBB)
1940 visitBitTestHeader(BTB);
1942 BitTestCases.push_back(BTB);
1947 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1948 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
1949 const SwitchInst& SI) {
1952 // Start with "simple" cases
1953 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1954 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1955 Cases.push_back(Case(SI.getSuccessorValue(i),
1956 SI.getSuccessorValue(i),
1959 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1961 // Merge case into clusters
1962 if (Cases.size() >= 2)
1963 // Must recompute end() each iteration because it may be
1964 // invalidated by erase if we hold on to it
1965 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1966 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1967 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1968 MachineBasicBlock* nextBB = J->BB;
1969 MachineBasicBlock* currentBB = I->BB;
1971 // If the two neighboring cases go to the same destination, merge them
1972 // into a single case.
1973 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
1981 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1982 if (I->Low != I->High)
1983 // A range counts double, since it requires two compares.
1990 void SelectionDAGBuilder::visitSwitch(SwitchInst &SI) {
1991 // Figure out which block is immediately after the current one.
1992 MachineBasicBlock *NextBlock = 0;
1993 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1995 // If there is only the default destination, branch to it if it is not the
1996 // next basic block. Otherwise, just fall through.
1997 if (SI.getNumOperands() == 2) {
1998 // Update machine-CFG edges.
2000 // If this is not a fall-through branch, emit the branch.
2001 CurMBB->addSuccessor(Default);
2002 if (Default != NextBlock)
2003 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2004 MVT::Other, getControlRoot(),
2005 DAG.getBasicBlock(Default)));
2010 // If there are any non-default case statements, create a vector of Cases
2011 // representing each one, and sort the vector so that we can efficiently
2012 // create a binary search tree from them.
2014 size_t numCmps = Clusterify(Cases, SI);
2015 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2016 << ". Total compares: " << numCmps << '\n');
2019 // Get the Value to be switched on and default basic blocks, which will be
2020 // inserted into CaseBlock records, representing basic blocks in the binary
2022 Value *SV = SI.getOperand(0);
2024 // Push the initial CaseRec onto the worklist
2025 CaseRecVector WorkList;
2026 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2028 while (!WorkList.empty()) {
2029 // Grab a record representing a case range to process off the worklist
2030 CaseRec CR = WorkList.back();
2031 WorkList.pop_back();
2033 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2036 // If the range has few cases (two or less) emit a series of specific
2038 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2041 // If the switch has more than 5 blocks, and at least 40% dense, and the
2042 // target supports indirect branches, then emit a jump table rather than
2043 // lowering the switch to a binary tree of conditional branches.
2044 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2047 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2048 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2049 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2053 void SelectionDAGBuilder::visitIndirectBr(IndirectBrInst &I) {
2054 // Update machine-CFG edges.
2055 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2056 CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);
2058 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2059 MVT::Other, getControlRoot(),
2060 getValue(I.getAddress())));
2063 void SelectionDAGBuilder::visitFSub(User &I) {
2064 // -0.0 - X --> fneg
2065 const Type *Ty = I.getType();
2066 if (isa<VectorType>(Ty)) {
2067 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2068 const VectorType *DestTy = cast<VectorType>(I.getType());
2069 const Type *ElTy = DestTy->getElementType();
2070 unsigned VL = DestTy->getNumElements();
2071 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2072 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2074 SDValue Op2 = getValue(I.getOperand(1));
2075 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2076 Op2.getValueType(), Op2));
2082 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2083 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2084 SDValue Op2 = getValue(I.getOperand(1));
2085 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2086 Op2.getValueType(), Op2));
2090 visitBinary(I, ISD::FSUB);
2093 void SelectionDAGBuilder::visitBinary(User &I, unsigned OpCode) {
2094 SDValue Op1 = getValue(I.getOperand(0));
2095 SDValue Op2 = getValue(I.getOperand(1));
2096 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2097 Op1.getValueType(), Op1, Op2));
2100 void SelectionDAGBuilder::visitShift(User &I, unsigned Opcode) {
2101 SDValue Op1 = getValue(I.getOperand(0));
2102 SDValue Op2 = getValue(I.getOperand(1));
2103 if (!isa<VectorType>(I.getType()) &&
2104 Op2.getValueType() != TLI.getShiftAmountTy()) {
2105 // If the operand is smaller than the shift count type, promote it.
2106 EVT PTy = TLI.getPointerTy();
2107 EVT STy = TLI.getShiftAmountTy();
2108 if (STy.bitsGT(Op2.getValueType()))
2109 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2110 TLI.getShiftAmountTy(), Op2);
2111 // If the operand is larger than the shift count type but the shift
2112 // count type has enough bits to represent any shift value, truncate
2113 // it now. This is a common case and it exposes the truncate to
2114 // optimization early.
2115 else if (STy.getSizeInBits() >=
2116 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2117 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2118 TLI.getShiftAmountTy(), Op2);
2119 // Otherwise we'll need to temporarily settle for some other
2120 // convenient type; type legalization will make adjustments as
2122 else if (PTy.bitsLT(Op2.getValueType()))
2123 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2124 TLI.getPointerTy(), Op2);
2125 else if (PTy.bitsGT(Op2.getValueType()))
2126 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2127 TLI.getPointerTy(), Op2);
2130 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2131 Op1.getValueType(), Op1, Op2));
2134 void SelectionDAGBuilder::visitICmp(User &I) {
2135 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2136 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2137 predicate = IC->getPredicate();
2138 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2139 predicate = ICmpInst::Predicate(IC->getPredicate());
2140 SDValue Op1 = getValue(I.getOperand(0));
2141 SDValue Op2 = getValue(I.getOperand(1));
2142 ISD::CondCode Opcode = getICmpCondCode(predicate);
2144 EVT DestVT = TLI.getValueType(I.getType());
2145 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2148 void SelectionDAGBuilder::visitFCmp(User &I) {
2149 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2150 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2151 predicate = FC->getPredicate();
2152 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2153 predicate = FCmpInst::Predicate(FC->getPredicate());
2154 SDValue Op1 = getValue(I.getOperand(0));
2155 SDValue Op2 = getValue(I.getOperand(1));
2156 ISD::CondCode Condition = getFCmpCondCode(predicate);
2157 EVT DestVT = TLI.getValueType(I.getType());
2158 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2161 void SelectionDAGBuilder::visitSelect(User &I) {
2162 SmallVector<EVT, 4> ValueVTs;
2163 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2164 unsigned NumValues = ValueVTs.size();
2165 if (NumValues == 0) return;
2167 SmallVector<SDValue, 4> Values(NumValues);
2168 SDValue Cond = getValue(I.getOperand(0));
2169 SDValue TrueVal = getValue(I.getOperand(1));
2170 SDValue FalseVal = getValue(I.getOperand(2));
2172 for (unsigned i = 0; i != NumValues; ++i)
2173 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2174 TrueVal.getNode()->getValueType(i), Cond,
2175 SDValue(TrueVal.getNode(),
2176 TrueVal.getResNo() + i),
2177 SDValue(FalseVal.getNode(),
2178 FalseVal.getResNo() + i));
2180 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2181 DAG.getVTList(&ValueVTs[0], NumValues),
2182 &Values[0], NumValues));
2185 void SelectionDAGBuilder::visitTrunc(User &I) {
2186 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2187 SDValue N = getValue(I.getOperand(0));
2188 EVT DestVT = TLI.getValueType(I.getType());
2189 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2192 void SelectionDAGBuilder::visitZExt(User &I) {
2193 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2194 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2195 SDValue N = getValue(I.getOperand(0));
2196 EVT DestVT = TLI.getValueType(I.getType());
2197 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2200 void SelectionDAGBuilder::visitSExt(User &I) {
2201 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2202 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2203 SDValue N = getValue(I.getOperand(0));
2204 EVT DestVT = TLI.getValueType(I.getType());
2205 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2208 void SelectionDAGBuilder::visitFPTrunc(User &I) {
2209 // FPTrunc is never a no-op cast, no need to check
2210 SDValue N = getValue(I.getOperand(0));
2211 EVT DestVT = TLI.getValueType(I.getType());
2212 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2213 DestVT, N, DAG.getIntPtrConstant(0)));
2216 void SelectionDAGBuilder::visitFPExt(User &I){
2217 // FPTrunc is never a no-op cast, no need to check
2218 SDValue N = getValue(I.getOperand(0));
2219 EVT DestVT = TLI.getValueType(I.getType());
2220 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2223 void SelectionDAGBuilder::visitFPToUI(User &I) {
2224 // FPToUI is never a no-op cast, no need to check
2225 SDValue N = getValue(I.getOperand(0));
2226 EVT DestVT = TLI.getValueType(I.getType());
2227 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2230 void SelectionDAGBuilder::visitFPToSI(User &I) {
2231 // FPToSI is never a no-op cast, no need to check
2232 SDValue N = getValue(I.getOperand(0));
2233 EVT DestVT = TLI.getValueType(I.getType());
2234 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2237 void SelectionDAGBuilder::visitUIToFP(User &I) {
2238 // UIToFP is never a no-op cast, no need to check
2239 SDValue N = getValue(I.getOperand(0));
2240 EVT DestVT = TLI.getValueType(I.getType());
2241 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2244 void SelectionDAGBuilder::visitSIToFP(User &I){
2245 // SIToFP is never a no-op cast, no need to check
2246 SDValue N = getValue(I.getOperand(0));
2247 EVT DestVT = TLI.getValueType(I.getType());
2248 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2251 void SelectionDAGBuilder::visitPtrToInt(User &I) {
2252 // What to do depends on the size of the integer and the size of the pointer.
2253 // We can either truncate, zero extend, or no-op, accordingly.
2254 SDValue N = getValue(I.getOperand(0));
2255 EVT SrcVT = N.getValueType();
2256 EVT DestVT = TLI.getValueType(I.getType());
2257 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2260 void SelectionDAGBuilder::visitIntToPtr(User &I) {
2261 // What to do depends on the size of the integer and the size of the pointer.
2262 // We can either truncate, zero extend, or no-op, accordingly.
2263 SDValue N = getValue(I.getOperand(0));
2264 EVT SrcVT = N.getValueType();
2265 EVT DestVT = TLI.getValueType(I.getType());
2266 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2269 void SelectionDAGBuilder::visitBitCast(User &I) {
2270 SDValue N = getValue(I.getOperand(0));
2271 EVT DestVT = TLI.getValueType(I.getType());
2273 // BitCast assures us that source and destination are the same size so this is
2274 // either a BIT_CONVERT or a no-op.
2275 if (DestVT != N.getValueType())
2276 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2277 DestVT, N)); // convert types.
2279 setValue(&I, N); // noop cast.
2282 void SelectionDAGBuilder::visitInsertElement(User &I) {
2283 SDValue InVec = getValue(I.getOperand(0));
2284 SDValue InVal = getValue(I.getOperand(1));
2285 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2287 getValue(I.getOperand(2)));
2288 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2289 TLI.getValueType(I.getType()),
2290 InVec, InVal, InIdx));
2293 void SelectionDAGBuilder::visitExtractElement(User &I) {
2294 SDValue InVec = getValue(I.getOperand(0));
2295 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2297 getValue(I.getOperand(1)));
2298 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2299 TLI.getValueType(I.getType()), InVec, InIdx));
2302 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2303 // from SIndx and increasing to the element length (undefs are allowed).
2304 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2305 unsigned MaskNumElts = Mask.size();
2306 for (unsigned i = 0; i != MaskNumElts; ++i)
2307 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2312 void SelectionDAGBuilder::visitShuffleVector(User &I) {
2313 SmallVector<int, 8> Mask;
2314 SDValue Src1 = getValue(I.getOperand(0));
2315 SDValue Src2 = getValue(I.getOperand(1));
2317 // Convert the ConstantVector mask operand into an array of ints, with -1
2318 // representing undef values.
2319 SmallVector<Constant*, 8> MaskElts;
2320 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2322 unsigned MaskNumElts = MaskElts.size();
2323 for (unsigned i = 0; i != MaskNumElts; ++i) {
2324 if (isa<UndefValue>(MaskElts[i]))
2327 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2330 EVT VT = TLI.getValueType(I.getType());
2331 EVT SrcVT = Src1.getValueType();
2332 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2334 if (SrcNumElts == MaskNumElts) {
2335 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2340 // Normalize the shuffle vector since mask and vector length don't match.
2341 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2342 // Mask is longer than the source vectors and is a multiple of the source
2343 // vectors. We can use concatenate vector to make the mask and vectors
2345 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2346 // The shuffle is concatenating two vectors together.
2347 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2352 // Pad both vectors with undefs to make them the same length as the mask.
2353 unsigned NumConcat = MaskNumElts / SrcNumElts;
2354 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2355 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2356 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2358 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2359 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2363 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2364 getCurDebugLoc(), VT,
2365 &MOps1[0], NumConcat);
2366 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2367 getCurDebugLoc(), VT,
2368 &MOps2[0], NumConcat);
2370 // Readjust mask for new input vector length.
2371 SmallVector<int, 8> MappedOps;
2372 for (unsigned i = 0; i != MaskNumElts; ++i) {
2374 if (Idx < (int)SrcNumElts)
2375 MappedOps.push_back(Idx);
2377 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2380 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2385 if (SrcNumElts > MaskNumElts) {
2386 // Analyze the access pattern of the vector to see if we can extract
2387 // two subvectors and do the shuffle. The analysis is done by calculating
2388 // the range of elements the mask access on both vectors.
2389 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2390 int MaxRange[2] = {-1, -1};
2392 for (unsigned i = 0; i != MaskNumElts; ++i) {
2398 if (Idx >= (int)SrcNumElts) {
2402 if (Idx > MaxRange[Input])
2403 MaxRange[Input] = Idx;
2404 if (Idx < MinRange[Input])
2405 MinRange[Input] = Idx;
2408 // Check if the access is smaller than the vector size and can we find
2409 // a reasonable extract index.
2410 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2412 int StartIdx[2]; // StartIdx to extract from
2413 for (int Input=0; Input < 2; ++Input) {
2414 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2415 RangeUse[Input] = 0; // Unused
2416 StartIdx[Input] = 0;
2417 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2418 // Fits within range but we should see if we can find a good
2419 // start index that is a multiple of the mask length.
2420 if (MaxRange[Input] < (int)MaskNumElts) {
2421 RangeUse[Input] = 1; // Extract from beginning of the vector
2422 StartIdx[Input] = 0;
2424 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2425 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2426 StartIdx[Input] + MaskNumElts < SrcNumElts)
2427 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2432 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2433 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2436 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2437 // Extract appropriate subvector and generate a vector shuffle
2438 for (int Input=0; Input < 2; ++Input) {
2439 SDValue &Src = Input == 0 ? Src1 : Src2;
2440 if (RangeUse[Input] == 0)
2441 Src = DAG.getUNDEF(VT);
2443 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2444 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2447 // Calculate new mask.
2448 SmallVector<int, 8> MappedOps;
2449 for (unsigned i = 0; i != MaskNumElts; ++i) {
2452 MappedOps.push_back(Idx);
2453 else if (Idx < (int)SrcNumElts)
2454 MappedOps.push_back(Idx - StartIdx[0]);
2456 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2459 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2465 // We can't use either concat vectors or extract subvectors so fall back to
2466 // replacing the shuffle with extract and build vector.
2467 // to insert and build vector.
2468 EVT EltVT = VT.getVectorElementType();
2469 EVT PtrVT = TLI.getPointerTy();
2470 SmallVector<SDValue,8> Ops;
2471 for (unsigned i = 0; i != MaskNumElts; ++i) {
2473 Ops.push_back(DAG.getUNDEF(EltVT));
2478 if (Idx < (int)SrcNumElts)
2479 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2480 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2482 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2484 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2490 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2491 VT, &Ops[0], Ops.size()));
2494 void SelectionDAGBuilder::visitInsertValue(InsertValueInst &I) {
2495 const Value *Op0 = I.getOperand(0);
2496 const Value *Op1 = I.getOperand(1);
2497 const Type *AggTy = I.getType();
2498 const Type *ValTy = Op1->getType();
2499 bool IntoUndef = isa<UndefValue>(Op0);
2500 bool FromUndef = isa<UndefValue>(Op1);
2502 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2503 I.idx_begin(), I.idx_end());
2505 SmallVector<EVT, 4> AggValueVTs;
2506 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2507 SmallVector<EVT, 4> ValValueVTs;
2508 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2510 unsigned NumAggValues = AggValueVTs.size();
2511 unsigned NumValValues = ValValueVTs.size();
2512 SmallVector<SDValue, 4> Values(NumAggValues);
2514 SDValue Agg = getValue(Op0);
2515 SDValue Val = getValue(Op1);
2517 // Copy the beginning value(s) from the original aggregate.
2518 for (; i != LinearIndex; ++i)
2519 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2520 SDValue(Agg.getNode(), Agg.getResNo() + i);
2521 // Copy values from the inserted value(s).
2522 for (; i != LinearIndex + NumValValues; ++i)
2523 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2524 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2525 // Copy remaining value(s) from the original aggregate.
2526 for (; i != NumAggValues; ++i)
2527 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2528 SDValue(Agg.getNode(), Agg.getResNo() + i);
2530 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2531 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2532 &Values[0], NumAggValues));
2535 void SelectionDAGBuilder::visitExtractValue(ExtractValueInst &I) {
2536 const Value *Op0 = I.getOperand(0);
2537 const Type *AggTy = Op0->getType();
2538 const Type *ValTy = I.getType();
2539 bool OutOfUndef = isa<UndefValue>(Op0);
2541 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2542 I.idx_begin(), I.idx_end());
2544 SmallVector<EVT, 4> ValValueVTs;
2545 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2547 unsigned NumValValues = ValValueVTs.size();
2548 SmallVector<SDValue, 4> Values(NumValValues);
2550 SDValue Agg = getValue(Op0);
2551 // Copy out the selected value(s).
2552 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2553 Values[i - LinearIndex] =
2555 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2556 SDValue(Agg.getNode(), Agg.getResNo() + i);
2558 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2559 DAG.getVTList(&ValValueVTs[0], NumValValues),
2560 &Values[0], NumValValues));
2563 void SelectionDAGBuilder::visitGetElementPtr(User &I) {
2564 SDValue N = getValue(I.getOperand(0));
2565 const Type *Ty = I.getOperand(0)->getType();
2567 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2570 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2571 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2574 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2575 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2576 DAG.getIntPtrConstant(Offset));
2579 Ty = StTy->getElementType(Field);
2581 Ty = cast<SequentialType>(Ty)->getElementType();
2583 // If this is a constant subscript, handle it quickly.
2584 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2585 if (CI->getZExtValue() == 0) continue;
2587 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2589 EVT PTy = TLI.getPointerTy();
2590 unsigned PtrBits = PTy.getSizeInBits();
2592 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2594 DAG.getConstant(Offs, MVT::i64));
2596 OffsVal = DAG.getIntPtrConstant(Offs);
2598 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2603 // N = N + Idx * ElementSize;
2604 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2605 TD->getTypeAllocSize(Ty));
2606 SDValue IdxN = getValue(Idx);
2608 // If the index is smaller or larger than intptr_t, truncate or extend
2610 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2612 // If this is a multiply by a power of two, turn it into a shl
2613 // immediately. This is a very common case.
2614 if (ElementSize != 1) {
2615 if (ElementSize.isPowerOf2()) {
2616 unsigned Amt = ElementSize.logBase2();
2617 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2618 N.getValueType(), IdxN,
2619 DAG.getConstant(Amt, TLI.getPointerTy()));
2621 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2622 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2623 N.getValueType(), IdxN, Scale);
2627 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2628 N.getValueType(), N, IdxN);
2635 void SelectionDAGBuilder::visitAlloca(AllocaInst &I) {
2636 // If this is a fixed sized alloca in the entry block of the function,
2637 // allocate it statically on the stack.
2638 if (FuncInfo.StaticAllocaMap.count(&I))
2639 return; // getValue will auto-populate this.
2641 const Type *Ty = I.getAllocatedType();
2642 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2644 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2647 SDValue AllocSize = getValue(I.getArraySize());
2649 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2651 DAG.getConstant(TySize, AllocSize.getValueType()));
2653 EVT IntPtr = TLI.getPointerTy();
2654 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2656 // Handle alignment. If the requested alignment is less than or equal to
2657 // the stack alignment, ignore it. If the size is greater than or equal to
2658 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2659 unsigned StackAlign =
2660 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2661 if (Align <= StackAlign)
2664 // Round the size of the allocation up to the stack alignment size
2665 // by add SA-1 to the size.
2666 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2667 AllocSize.getValueType(), AllocSize,
2668 DAG.getIntPtrConstant(StackAlign-1));
2670 // Mask out the low bits for alignment purposes.
2671 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2672 AllocSize.getValueType(), AllocSize,
2673 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2675 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2676 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2677 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2680 DAG.setRoot(DSA.getValue(1));
2682 // Inform the Frame Information that we have just allocated a variable-sized
2684 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2687 void SelectionDAGBuilder::visitLoad(LoadInst &I) {
2688 const Value *SV = I.getOperand(0);
2689 SDValue Ptr = getValue(SV);
2691 const Type *Ty = I.getType();
2692 bool isVolatile = I.isVolatile();
2693 unsigned Alignment = I.getAlignment();
2695 SmallVector<EVT, 4> ValueVTs;
2696 SmallVector<uint64_t, 4> Offsets;
2697 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2698 unsigned NumValues = ValueVTs.size();
2703 bool ConstantMemory = false;
2705 // Serialize volatile loads with other side effects.
2707 else if (AA->pointsToConstantMemory(SV)) {
2708 // Do not serialize (non-volatile) loads of constant memory with anything.
2709 Root = DAG.getEntryNode();
2710 ConstantMemory = true;
2712 // Do not serialize non-volatile loads against each other.
2713 Root = DAG.getRoot();
2716 SmallVector<SDValue, 4> Values(NumValues);
2717 SmallVector<SDValue, 4> Chains(NumValues);
2718 EVT PtrVT = Ptr.getValueType();
2719 for (unsigned i = 0; i != NumValues; ++i) {
2720 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2722 DAG.getConstant(Offsets[i], PtrVT));
2723 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2724 A, SV, Offsets[i], isVolatile, Alignment);
2727 Chains[i] = L.getValue(1);
2730 if (!ConstantMemory) {
2731 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2732 MVT::Other, &Chains[0], NumValues);
2736 PendingLoads.push_back(Chain);
2739 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2740 DAG.getVTList(&ValueVTs[0], NumValues),
2741 &Values[0], NumValues));
2744 void SelectionDAGBuilder::visitStore(StoreInst &I) {
2745 Value *SrcV = I.getOperand(0);
2746 Value *PtrV = I.getOperand(1);
2748 SmallVector<EVT, 4> ValueVTs;
2749 SmallVector<uint64_t, 4> Offsets;
2750 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2751 unsigned NumValues = ValueVTs.size();
2755 // Get the lowered operands. Note that we do this after
2756 // checking if NumResults is zero, because with zero results
2757 // the operands won't have values in the map.
2758 SDValue Src = getValue(SrcV);
2759 SDValue Ptr = getValue(PtrV);
2761 SDValue Root = getRoot();
2762 SmallVector<SDValue, 4> Chains(NumValues);
2763 EVT PtrVT = Ptr.getValueType();
2764 bool isVolatile = I.isVolatile();
2765 unsigned Alignment = I.getAlignment();
2767 for (unsigned i = 0; i != NumValues; ++i) {
2768 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
2769 DAG.getConstant(Offsets[i], PtrVT));
2770 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2771 SDValue(Src.getNode(), Src.getResNo() + i),
2772 Add, PtrV, Offsets[i], isVolatile, Alignment);
2775 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2776 MVT::Other, &Chains[0], NumValues));
2779 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2781 void SelectionDAGBuilder::visitTargetIntrinsic(CallInst &I,
2782 unsigned Intrinsic) {
2783 bool HasChain = !I.doesNotAccessMemory();
2784 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2786 // Build the operand list.
2787 SmallVector<SDValue, 8> Ops;
2788 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2790 // We don't need to serialize loads against other loads.
2791 Ops.push_back(DAG.getRoot());
2793 Ops.push_back(getRoot());
2797 // Info is set by getTgtMemInstrinsic
2798 TargetLowering::IntrinsicInfo Info;
2799 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2801 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2802 if (!IsTgtIntrinsic)
2803 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2805 // Add all operands of the call to the operand list.
2806 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2807 SDValue Op = getValue(I.getOperand(i));
2808 assert(TLI.isTypeLegal(Op.getValueType()) &&
2809 "Intrinsic uses a non-legal type?");
2813 SmallVector<EVT, 4> ValueVTs;
2814 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2816 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2817 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2818 "Intrinsic uses a non-legal type?");
2823 ValueVTs.push_back(MVT::Other);
2825 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2829 if (IsTgtIntrinsic) {
2830 // This is target intrinsic that touches memory
2831 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2832 VTs, &Ops[0], Ops.size(),
2833 Info.memVT, Info.ptrVal, Info.offset,
2834 Info.align, Info.vol,
2835 Info.readMem, Info.writeMem);
2836 } else if (!HasChain) {
2837 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2838 VTs, &Ops[0], Ops.size());
2839 } else if (!I.getType()->isVoidTy()) {
2840 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2841 VTs, &Ops[0], Ops.size());
2843 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2844 VTs, &Ops[0], Ops.size());
2848 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2850 PendingLoads.push_back(Chain);
2855 if (!I.getType()->isVoidTy()) {
2856 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2857 EVT VT = TLI.getValueType(PTy);
2858 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2861 setValue(&I, Result);
2865 /// GetSignificand - Get the significand and build it into a floating-point
2866 /// number with exponent of 1:
2868 /// Op = (Op & 0x007fffff) | 0x3f800000;
2870 /// where Op is the hexidecimal representation of floating point value.
2872 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl, unsigned Order) {
2873 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2874 DAG.getConstant(0x007fffff, MVT::i32));
2875 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
2876 DAG.getConstant(0x3f800000, MVT::i32));
2877 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
2880 /// GetExponent - Get the exponent:
2882 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
2884 /// where Op is the hexidecimal representation of floating point value.
2886 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
2887 DebugLoc dl, unsigned Order) {
2888 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2889 DAG.getConstant(0x7f800000, MVT::i32));
2890 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
2891 DAG.getConstant(23, TLI.getPointerTy()));
2892 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
2893 DAG.getConstant(127, MVT::i32));
2894 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
2897 /// getF32Constant - Get 32-bit floating point constant.
2899 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2900 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2903 /// Inlined utility function to implement binary input atomic intrinsics for
2904 /// visitIntrinsicCall: I is a call instruction
2905 /// Op is the associated NodeType for I
2907 SelectionDAGBuilder::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
2908 SDValue Root = getRoot();
2910 DAG.getAtomic(Op, getCurDebugLoc(),
2911 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
2913 getValue(I.getOperand(1)),
2914 getValue(I.getOperand(2)),
2917 DAG.setRoot(L.getValue(1));
2921 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
2923 SelectionDAGBuilder::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
2924 SDValue Op1 = getValue(I.getOperand(1));
2925 SDValue Op2 = getValue(I.getOperand(2));
2927 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
2928 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
2932 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2933 /// limited-precision mode.
2935 SelectionDAGBuilder::visitExp(CallInst &I) {
2937 DebugLoc dl = getCurDebugLoc();
2939 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2940 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2941 SDValue Op = getValue(I.getOperand(1));
2943 // Put the exponent in the right bit position for later addition to the
2946 // #define LOG2OFe 1.4426950f
2947 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2948 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
2949 getF32Constant(DAG, 0x3fb8aa3b));
2950 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
2952 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2953 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
2954 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
2956 // IntegerPartOfX <<= 23;
2957 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
2958 DAG.getConstant(23, TLI.getPointerTy()));
2960 if (LimitFloatPrecision <= 6) {
2961 // For floating-point precision of 6:
2963 // TwoToFractionalPartOfX =
2965 // (0.735607626f + 0.252464424f * x) * x;
2967 // error 0.0144103317, which is 6 bits
2968 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2969 getF32Constant(DAG, 0x3e814304));
2970 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2971 getF32Constant(DAG, 0x3f3c50c8));
2972 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2973 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2974 getF32Constant(DAG, 0x3f7f5e7e));
2975 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
2977 // Add the exponent into the result in integer domain.
2978 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2979 TwoToFracPartOfX, IntegerPartOfX);
2981 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
2982 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2983 // For floating-point precision of 12:
2985 // TwoToFractionalPartOfX =
2988 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2990 // 0.000107046256 error, which is 13 to 14 bits
2991 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2992 getF32Constant(DAG, 0x3da235e3));
2993 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2994 getF32Constant(DAG, 0x3e65b8f3));
2995 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2996 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2997 getF32Constant(DAG, 0x3f324b07));
2998 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
2999 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3000 getF32Constant(DAG, 0x3f7ff8fd));
3001 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3003 // Add the exponent into the result in integer domain.
3004 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3005 TwoToFracPartOfX, IntegerPartOfX);
3007 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3008 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3009 // For floating-point precision of 18:
3011 // TwoToFractionalPartOfX =
3015 // (0.554906021e-1f +
3016 // (0.961591928e-2f +
3017 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3019 // error 2.47208000*10^(-7), which is better than 18 bits
3020 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3021 getF32Constant(DAG, 0x3924b03e));
3022 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3023 getF32Constant(DAG, 0x3ab24b87));
3024 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3025 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3026 getF32Constant(DAG, 0x3c1d8c17));
3027 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3028 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3029 getF32Constant(DAG, 0x3d634a1d));
3030 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3031 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3032 getF32Constant(DAG, 0x3e75fe14));
3033 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3034 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3035 getF32Constant(DAG, 0x3f317234));
3036 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3037 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3038 getF32Constant(DAG, 0x3f800000));
3039 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3042 // Add the exponent into the result in integer domain.
3043 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3044 TwoToFracPartOfX, IntegerPartOfX);
3046 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3049 // No special expansion.
3050 result = DAG.getNode(ISD::FEXP, dl,
3051 getValue(I.getOperand(1)).getValueType(),
3052 getValue(I.getOperand(1)));
3055 setValue(&I, result);
3058 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3059 /// limited-precision mode.
3061 SelectionDAGBuilder::visitLog(CallInst &I) {
3063 DebugLoc dl = getCurDebugLoc();
3065 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3066 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3067 SDValue Op = getValue(I.getOperand(1));
3068 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3070 // Scale the exponent by log(2) [0.69314718f].
3071 SDValue Exp = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
3072 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3073 getF32Constant(DAG, 0x3f317218));
3075 // Get the significand and build it into a floating-point number with
3077 SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
3079 if (LimitFloatPrecision <= 6) {
3080 // For floating-point precision of 6:
3084 // (1.4034025f - 0.23903021f * x) * x;
3086 // error 0.0034276066, which is better than 8 bits
3087 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3088 getF32Constant(DAG, 0xbe74c456));
3089 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3090 getF32Constant(DAG, 0x3fb3a2b1));
3091 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3092 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3093 getF32Constant(DAG, 0x3f949a29));
3095 result = DAG.getNode(ISD::FADD, dl,
3096 MVT::f32, LogOfExponent, LogOfMantissa);
3097 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3098 // For floating-point precision of 12:
3104 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3106 // error 0.000061011436, which is 14 bits
3107 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3108 getF32Constant(DAG, 0xbd67b6d6));
3109 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3110 getF32Constant(DAG, 0x3ee4f4b8));
3111 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3112 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3113 getF32Constant(DAG, 0x3fbc278b));
3114 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3115 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3116 getF32Constant(DAG, 0x40348e95));
3117 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3118 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3119 getF32Constant(DAG, 0x3fdef31a));
3121 result = DAG.getNode(ISD::FADD, dl,
3122 MVT::f32, LogOfExponent, LogOfMantissa);
3123 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3124 // For floating-point precision of 18:
3132 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3134 // error 0.0000023660568, which is better than 18 bits
3135 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3136 getF32Constant(DAG, 0xbc91e5ac));
3137 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3138 getF32Constant(DAG, 0x3e4350aa));
3139 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3140 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3141 getF32Constant(DAG, 0x3f60d3e3));
3142 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3143 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3144 getF32Constant(DAG, 0x4011cdf0));
3145 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3146 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3147 getF32Constant(DAG, 0x406cfd1c));
3148 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3149 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3150 getF32Constant(DAG, 0x408797cb));
3151 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3152 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3153 getF32Constant(DAG, 0x4006dcab));
3155 result = DAG.getNode(ISD::FADD, dl,
3156 MVT::f32, LogOfExponent, LogOfMantissa);
3159 // No special expansion.
3160 result = DAG.getNode(ISD::FLOG, dl,
3161 getValue(I.getOperand(1)).getValueType(),
3162 getValue(I.getOperand(1)));
3165 setValue(&I, result);
3168 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3169 /// limited-precision mode.
3171 SelectionDAGBuilder::visitLog2(CallInst &I) {
3173 DebugLoc dl = getCurDebugLoc();
3175 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3176 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3177 SDValue Op = getValue(I.getOperand(1));
3178 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3180 // Get the exponent.
3181 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
3183 // Get the significand and build it into a floating-point number with
3185 SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
3187 // Different possible minimax approximations of significand in
3188 // floating-point for various degrees of accuracy over [1,2].
3189 if (LimitFloatPrecision <= 6) {
3190 // For floating-point precision of 6:
3192 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3194 // error 0.0049451742, which is more than 7 bits
3195 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3196 getF32Constant(DAG, 0xbeb08fe0));
3197 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3198 getF32Constant(DAG, 0x40019463));
3199 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3200 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3201 getF32Constant(DAG, 0x3fd6633d));
3203 result = DAG.getNode(ISD::FADD, dl,
3204 MVT::f32, LogOfExponent, Log2ofMantissa);
3205 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3206 // For floating-point precision of 12:
3212 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3214 // error 0.0000876136000, which is better than 13 bits
3215 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3216 getF32Constant(DAG, 0xbda7262e));
3217 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3218 getF32Constant(DAG, 0x3f25280b));
3219 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3220 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3221 getF32Constant(DAG, 0x4007b923));
3222 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3223 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3224 getF32Constant(DAG, 0x40823e2f));
3225 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3226 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3227 getF32Constant(DAG, 0x4020d29c));
3229 result = DAG.getNode(ISD::FADD, dl,
3230 MVT::f32, LogOfExponent, Log2ofMantissa);
3231 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3232 // For floating-point precision of 18:
3241 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3243 // error 0.0000018516, which is better than 18 bits
3244 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3245 getF32Constant(DAG, 0xbcd2769e));
3246 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3247 getF32Constant(DAG, 0x3e8ce0b9));
3248 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3249 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3250 getF32Constant(DAG, 0x3fa22ae7));
3251 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3252 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3253 getF32Constant(DAG, 0x40525723));
3254 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3255 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3256 getF32Constant(DAG, 0x40aaf200));
3257 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3258 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3259 getF32Constant(DAG, 0x40c39dad));
3260 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3261 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3262 getF32Constant(DAG, 0x4042902c));
3264 result = DAG.getNode(ISD::FADD, dl,
3265 MVT::f32, LogOfExponent, Log2ofMantissa);
3268 // No special expansion.
3269 result = DAG.getNode(ISD::FLOG2, dl,
3270 getValue(I.getOperand(1)).getValueType(),
3271 getValue(I.getOperand(1)));
3274 setValue(&I, result);
3277 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3278 /// limited-precision mode.
3280 SelectionDAGBuilder::visitLog10(CallInst &I) {
3282 DebugLoc dl = getCurDebugLoc();
3284 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3285 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3286 SDValue Op = getValue(I.getOperand(1));
3287 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3289 // Scale the exponent by log10(2) [0.30102999f].
3290 SDValue Exp = GetExponent(DAG, Op1, TLI, dl, SDNodeOrder);
3291 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3292 getF32Constant(DAG, 0x3e9a209a));
3294 // Get the significand and build it into a floating-point number with
3296 SDValue X = GetSignificand(DAG, Op1, dl, SDNodeOrder);
3298 if (LimitFloatPrecision <= 6) {
3299 // For floating-point precision of 6:
3301 // Log10ofMantissa =
3303 // (0.60948995f - 0.10380950f * x) * x;
3305 // error 0.0014886165, which is 6 bits
3306 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3307 getF32Constant(DAG, 0xbdd49a13));
3308 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3309 getF32Constant(DAG, 0x3f1c0789));
3310 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3311 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3312 getF32Constant(DAG, 0x3f011300));
3314 result = DAG.getNode(ISD::FADD, dl,
3315 MVT::f32, LogOfExponent, Log10ofMantissa);
3316 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3317 // For floating-point precision of 12:
3319 // Log10ofMantissa =
3322 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3324 // error 0.00019228036, which is better than 12 bits
3325 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3326 getF32Constant(DAG, 0x3d431f31));
3327 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3328 getF32Constant(DAG, 0x3ea21fb2));
3329 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3330 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3331 getF32Constant(DAG, 0x3f6ae232));
3332 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3333 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3334 getF32Constant(DAG, 0x3f25f7c3));
3336 result = DAG.getNode(ISD::FADD, dl,
3337 MVT::f32, LogOfExponent, Log10ofMantissa);
3338 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3339 // For floating-point precision of 18:
3341 // Log10ofMantissa =
3346 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3348 // error 0.0000037995730, which is better than 18 bits
3349 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3350 getF32Constant(DAG, 0x3c5d51ce));
3351 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3352 getF32Constant(DAG, 0x3e00685a));
3353 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3354 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3355 getF32Constant(DAG, 0x3efb6798));
3356 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3357 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3358 getF32Constant(DAG, 0x3f88d192));
3359 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3360 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3361 getF32Constant(DAG, 0x3fc4316c));
3362 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3363 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3364 getF32Constant(DAG, 0x3f57ce70));
3366 result = DAG.getNode(ISD::FADD, dl,
3367 MVT::f32, LogOfExponent, Log10ofMantissa);
3370 // No special expansion.
3371 result = DAG.getNode(ISD::FLOG10, dl,
3372 getValue(I.getOperand(1)).getValueType(),
3373 getValue(I.getOperand(1)));
3376 setValue(&I, result);
3379 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3380 /// limited-precision mode.
3382 SelectionDAGBuilder::visitExp2(CallInst &I) {
3384 DebugLoc dl = getCurDebugLoc();
3386 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3387 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3388 SDValue Op = getValue(I.getOperand(1));
3390 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3392 // FractionalPartOfX = x - (float)IntegerPartOfX;
3393 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3394 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3396 // IntegerPartOfX <<= 23;
3397 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3398 DAG.getConstant(23, TLI.getPointerTy()));
3400 if (LimitFloatPrecision <= 6) {
3401 // For floating-point precision of 6:
3403 // TwoToFractionalPartOfX =
3405 // (0.735607626f + 0.252464424f * x) * x;
3407 // error 0.0144103317, which is 6 bits
3408 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3409 getF32Constant(DAG, 0x3e814304));
3410 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3411 getF32Constant(DAG, 0x3f3c50c8));
3412 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3413 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3414 getF32Constant(DAG, 0x3f7f5e7e));
3415 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3416 SDValue TwoToFractionalPartOfX =
3417 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3419 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3420 MVT::f32, TwoToFractionalPartOfX);
3421 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3422 // For floating-point precision of 12:
3424 // TwoToFractionalPartOfX =
3427 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3429 // error 0.000107046256, which is 13 to 14 bits
3430 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3431 getF32Constant(DAG, 0x3da235e3));
3432 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3433 getF32Constant(DAG, 0x3e65b8f3));
3434 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3435 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3436 getF32Constant(DAG, 0x3f324b07));
3437 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3438 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3439 getF32Constant(DAG, 0x3f7ff8fd));
3440 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3441 SDValue TwoToFractionalPartOfX =
3442 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3444 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3445 MVT::f32, TwoToFractionalPartOfX);
3446 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3447 // For floating-point precision of 18:
3449 // TwoToFractionalPartOfX =
3453 // (0.554906021e-1f +
3454 // (0.961591928e-2f +
3455 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3456 // error 2.47208000*10^(-7), which is better than 18 bits
3457 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3458 getF32Constant(DAG, 0x3924b03e));
3459 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3460 getF32Constant(DAG, 0x3ab24b87));
3461 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3462 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3463 getF32Constant(DAG, 0x3c1d8c17));
3464 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3465 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3466 getF32Constant(DAG, 0x3d634a1d));
3467 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3468 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3469 getF32Constant(DAG, 0x3e75fe14));
3470 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3471 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3472 getF32Constant(DAG, 0x3f317234));
3473 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3474 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3475 getF32Constant(DAG, 0x3f800000));
3476 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3477 SDValue TwoToFractionalPartOfX =
3478 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3480 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3481 MVT::f32, TwoToFractionalPartOfX);
3484 // No special expansion.
3485 result = DAG.getNode(ISD::FEXP2, dl,
3486 getValue(I.getOperand(1)).getValueType(),
3487 getValue(I.getOperand(1)));
3490 setValue(&I, result);
3493 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3494 /// limited-precision mode with x == 10.0f.
3496 SelectionDAGBuilder::visitPow(CallInst &I) {
3498 Value *Val = I.getOperand(1);
3499 DebugLoc dl = getCurDebugLoc();
3500 bool IsExp10 = false;
3502 if (getValue(Val).getValueType() == MVT::f32 &&
3503 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3504 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3505 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3506 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3508 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3513 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3514 SDValue Op = getValue(I.getOperand(2));
3516 // Put the exponent in the right bit position for later addition to the
3519 // #define LOG2OF10 3.3219281f
3520 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3521 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3522 getF32Constant(DAG, 0x40549a78));
3523 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3525 // FractionalPartOfX = x - (float)IntegerPartOfX;
3526 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3527 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3529 // IntegerPartOfX <<= 23;
3530 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3531 DAG.getConstant(23, TLI.getPointerTy()));
3533 if (LimitFloatPrecision <= 6) {
3534 // For floating-point precision of 6:
3536 // twoToFractionalPartOfX =
3538 // (0.735607626f + 0.252464424f * x) * x;
3540 // error 0.0144103317, which is 6 bits
3541 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3542 getF32Constant(DAG, 0x3e814304));
3543 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3544 getF32Constant(DAG, 0x3f3c50c8));
3545 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3546 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3547 getF32Constant(DAG, 0x3f7f5e7e));
3548 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3549 SDValue TwoToFractionalPartOfX =
3550 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3552 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3553 MVT::f32, TwoToFractionalPartOfX);
3554 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3555 // For floating-point precision of 12:
3557 // TwoToFractionalPartOfX =
3560 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3562 // error 0.000107046256, which is 13 to 14 bits
3563 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3564 getF32Constant(DAG, 0x3da235e3));
3565 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3566 getF32Constant(DAG, 0x3e65b8f3));
3567 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3568 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3569 getF32Constant(DAG, 0x3f324b07));
3570 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3571 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3572 getF32Constant(DAG, 0x3f7ff8fd));
3573 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3574 SDValue TwoToFractionalPartOfX =
3575 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3577 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3578 MVT::f32, TwoToFractionalPartOfX);
3579 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3580 // For floating-point precision of 18:
3582 // TwoToFractionalPartOfX =
3586 // (0.554906021e-1f +
3587 // (0.961591928e-2f +
3588 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3589 // error 2.47208000*10^(-7), which is better than 18 bits
3590 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3591 getF32Constant(DAG, 0x3924b03e));
3592 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3593 getF32Constant(DAG, 0x3ab24b87));
3594 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3595 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3596 getF32Constant(DAG, 0x3c1d8c17));
3597 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3598 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3599 getF32Constant(DAG, 0x3d634a1d));
3600 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3601 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3602 getF32Constant(DAG, 0x3e75fe14));
3603 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3604 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3605 getF32Constant(DAG, 0x3f317234));
3606 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3607 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3608 getF32Constant(DAG, 0x3f800000));
3609 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3610 SDValue TwoToFractionalPartOfX =
3611 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3613 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3614 MVT::f32, TwoToFractionalPartOfX);
3617 // No special expansion.
3618 result = DAG.getNode(ISD::FPOW, dl,
3619 getValue(I.getOperand(1)).getValueType(),
3620 getValue(I.getOperand(1)),
3621 getValue(I.getOperand(2)));
3624 setValue(&I, result);
3628 /// ExpandPowI - Expand a llvm.powi intrinsic.
3629 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3630 SelectionDAG &DAG) {
3631 // If RHS is a constant, we can expand this out to a multiplication tree,
3632 // otherwise we end up lowering to a call to __powidf2 (for example). When
3633 // optimizing for size, we only want to do this if the expansion would produce
3634 // a small number of multiplies, otherwise we do the full expansion.
3635 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3636 // Get the exponent as a positive value.
3637 unsigned Val = RHSC->getSExtValue();
3638 if ((int)Val < 0) Val = -Val;
3640 // powi(x, 0) -> 1.0
3642 return DAG.getConstantFP(1.0, LHS.getValueType());
3644 Function *F = DAG.getMachineFunction().getFunction();
3645 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3646 // If optimizing for size, don't insert too many multiplies. This
3647 // inserts up to 5 multiplies.
3648 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3649 // We use the simple binary decomposition method to generate the multiply
3650 // sequence. There are more optimal ways to do this (for example,
3651 // powi(x,15) generates one more multiply than it should), but this has
3652 // the benefit of being both really simple and much better than a libcall.
3653 SDValue Res; // Logically starts equal to 1.0
3654 SDValue CurSquare = LHS;
3658 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3660 Res = CurSquare; // 1.0*CurSquare.
3663 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3664 CurSquare, CurSquare);
3668 // If the original was negative, invert the result, producing 1/(x*x*x).
3669 if (RHSC->getSExtValue() < 0)
3670 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3671 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3676 // Otherwise, expand to a libcall.
3677 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3681 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3682 /// we want to emit this as a call to a named external function, return the name
3683 /// otherwise lower it and return null.
3685 SelectionDAGBuilder::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3686 DebugLoc dl = getCurDebugLoc();
3689 switch (Intrinsic) {
3691 // By default, turn this into a target intrinsic node.
3692 visitTargetIntrinsic(I, Intrinsic);
3694 case Intrinsic::vastart: visitVAStart(I); return 0;
3695 case Intrinsic::vaend: visitVAEnd(I); return 0;
3696 case Intrinsic::vacopy: visitVACopy(I); return 0;
3697 case Intrinsic::returnaddress:
3698 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3699 getValue(I.getOperand(1))));
3701 case Intrinsic::frameaddress:
3702 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3703 getValue(I.getOperand(1))));
3705 case Intrinsic::setjmp:
3706 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3707 case Intrinsic::longjmp:
3708 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3709 case Intrinsic::memcpy: {
3710 SDValue Op1 = getValue(I.getOperand(1));
3711 SDValue Op2 = getValue(I.getOperand(2));
3712 SDValue Op3 = getValue(I.getOperand(3));
3713 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3714 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3715 I.getOperand(1), 0, I.getOperand(2), 0));
3718 case Intrinsic::memset: {
3719 SDValue Op1 = getValue(I.getOperand(1));
3720 SDValue Op2 = getValue(I.getOperand(2));
3721 SDValue Op3 = getValue(I.getOperand(3));
3722 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3723 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3724 I.getOperand(1), 0));
3727 case Intrinsic::memmove: {
3728 SDValue Op1 = getValue(I.getOperand(1));
3729 SDValue Op2 = getValue(I.getOperand(2));
3730 SDValue Op3 = getValue(I.getOperand(3));
3731 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3733 // If the source and destination are known to not be aliases, we can
3734 // lower memmove as memcpy.
3735 uint64_t Size = -1ULL;
3736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3737 Size = C->getZExtValue();
3738 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3739 AliasAnalysis::NoAlias) {
3740 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3741 I.getOperand(1), 0, I.getOperand(2), 0));
3745 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3746 I.getOperand(1), 0, I.getOperand(2), 0));
3749 case Intrinsic::dbg_declare: {
3750 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None.
3751 // The real handling of this intrinsic is in FastISel.
3752 if (OptLevel != CodeGenOpt::None)
3753 // FIXME: Variable debug info is not supported here.
3755 DwarfWriter *DW = DAG.getDwarfWriter();
3758 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3759 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3762 MDNode *Variable = DI.getVariable();
3763 Value *Address = DI.getAddress();
3764 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3765 Address = BCI->getOperand(0);
3766 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3767 // Don't handle byval struct arguments or VLAs, for example.
3770 DenseMap<const AllocaInst*, int>::iterator SI =
3771 FuncInfo.StaticAllocaMap.find(AI);
3772 if (SI == FuncInfo.StaticAllocaMap.end())
3774 int FI = SI->second;
3776 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo())
3777 if (MDNode *Dbg = DI.getMetadata("dbg"))
3778 MMI->setVariableDbgInfo(Variable, FI, Dbg);
3781 case Intrinsic::dbg_value: {
3782 // FIXME: currently, we get here only if OptLevel != CodeGenOpt::None.
3783 // The real handling of this intrinsic is in FastISel.
3784 if (OptLevel != CodeGenOpt::None)
3785 // FIXME: Variable debug info is not supported here.
3787 DwarfWriter *DW = DAG.getDwarfWriter();
3790 DbgValueInst &DI = cast<DbgValueInst>(I);
3791 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3794 MDNode *Variable = DI.getVariable();
3795 Value *V = DI.getValue();
3798 if (BitCastInst *BCI = dyn_cast<BitCastInst>(V))
3799 V = BCI->getOperand(0);
3800 AllocaInst *AI = dyn_cast<AllocaInst>(V);
3801 // Don't handle byval struct arguments or VLAs, for example.
3804 DenseMap<const AllocaInst*, int>::iterator SI =
3805 FuncInfo.StaticAllocaMap.find(AI);
3806 if (SI == FuncInfo.StaticAllocaMap.end())
3808 int FI = SI->second;
3809 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo())
3810 if (MDNode *Dbg = DI.getMetadata("dbg"))
3811 MMI->setVariableDbgInfo(Variable, FI, Dbg);
3814 case Intrinsic::eh_exception: {
3815 // Insert the EXCEPTIONADDR instruction.
3816 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3817 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3819 Ops[0] = DAG.getRoot();
3820 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3822 DAG.setRoot(Op.getValue(1));
3826 case Intrinsic::eh_selector: {
3827 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3829 if (CurMBB->isLandingPad())
3830 AddCatchInfo(I, MMI, CurMBB);
3833 FuncInfo.CatchInfoLost.insert(&I);
3835 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3836 unsigned Reg = TLI.getExceptionSelectorRegister();
3837 if (Reg) CurMBB->addLiveIn(Reg);
3840 // Insert the EHSELECTION instruction.
3841 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3843 Ops[0] = getValue(I.getOperand(1));
3845 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3846 DAG.setRoot(Op.getValue(1));
3847 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
3851 case Intrinsic::eh_typeid_for: {
3852 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3855 // Find the type id for the given typeinfo.
3856 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3857 unsigned TypeID = MMI->getTypeIDFor(GV);
3858 Res = DAG.getConstant(TypeID, MVT::i32);
3860 // Return something different to eh_selector.
3861 Res = DAG.getConstant(1, MVT::i32);
3868 case Intrinsic::eh_return_i32:
3869 case Intrinsic::eh_return_i64:
3870 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3871 MMI->setCallsEHReturn(true);
3872 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3875 getValue(I.getOperand(1)),
3876 getValue(I.getOperand(2))));
3878 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
3882 case Intrinsic::eh_unwind_init:
3883 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
3884 MMI->setCallsUnwindInit(true);
3887 case Intrinsic::eh_dwarf_cfa: {
3888 EVT VT = getValue(I.getOperand(1)).getValueType();
3889 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
3890 TLI.getPointerTy());
3891 SDValue Offset = DAG.getNode(ISD::ADD, dl,
3893 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
3894 TLI.getPointerTy()),
3896 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
3898 DAG.getConstant(0, TLI.getPointerTy()));
3899 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
3903 case Intrinsic::eh_sjlj_callsite: {
3904 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3905 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
3906 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
3907 assert(MMI->getCurrentCallSite() == 0 && "Overlapping call sites!");
3909 MMI->setCurrentCallSite(CI->getZExtValue());
3913 case Intrinsic::convertff:
3914 case Intrinsic::convertfsi:
3915 case Intrinsic::convertfui:
3916 case Intrinsic::convertsif:
3917 case Intrinsic::convertuif:
3918 case Intrinsic::convertss:
3919 case Intrinsic::convertsu:
3920 case Intrinsic::convertus:
3921 case Intrinsic::convertuu: {
3922 ISD::CvtCode Code = ISD::CVT_INVALID;
3923 switch (Intrinsic) {
3924 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
3925 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
3926 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
3927 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
3928 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
3929 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
3930 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
3931 case Intrinsic::convertus: Code = ISD::CVT_US; break;
3932 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
3934 EVT DestVT = TLI.getValueType(I.getType());
3935 Value *Op1 = I.getOperand(1);
3936 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
3937 DAG.getValueType(DestVT),
3938 DAG.getValueType(getValue(Op1).getValueType()),
3939 getValue(I.getOperand(2)),
3940 getValue(I.getOperand(3)),
3945 case Intrinsic::sqrt:
3946 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
3947 getValue(I.getOperand(1)).getValueType(),
3948 getValue(I.getOperand(1))));
3950 case Intrinsic::powi:
3951 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)),
3952 getValue(I.getOperand(2)), DAG));
3954 case Intrinsic::sin:
3955 setValue(&I, DAG.getNode(ISD::FSIN, dl,
3956 getValue(I.getOperand(1)).getValueType(),
3957 getValue(I.getOperand(1))));
3959 case Intrinsic::cos:
3960 setValue(&I, DAG.getNode(ISD::FCOS, dl,
3961 getValue(I.getOperand(1)).getValueType(),
3962 getValue(I.getOperand(1))));
3964 case Intrinsic::log:
3967 case Intrinsic::log2:
3970 case Intrinsic::log10:
3973 case Intrinsic::exp:
3976 case Intrinsic::exp2:
3979 case Intrinsic::pow:
3982 case Intrinsic::pcmarker: {
3983 SDValue Tmp = getValue(I.getOperand(1));
3984 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
3987 case Intrinsic::readcyclecounter: {
3988 SDValue Op = getRoot();
3989 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
3990 DAG.getVTList(MVT::i64, MVT::Other),
3993 DAG.setRoot(Res.getValue(1));
3996 case Intrinsic::bswap:
3997 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
3998 getValue(I.getOperand(1)).getValueType(),
3999 getValue(I.getOperand(1))));
4001 case Intrinsic::cttz: {
4002 SDValue Arg = getValue(I.getOperand(1));
4003 EVT Ty = Arg.getValueType();
4004 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4007 case Intrinsic::ctlz: {
4008 SDValue Arg = getValue(I.getOperand(1));
4009 EVT Ty = Arg.getValueType();
4010 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4013 case Intrinsic::ctpop: {
4014 SDValue Arg = getValue(I.getOperand(1));
4015 EVT Ty = Arg.getValueType();
4016 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4019 case Intrinsic::stacksave: {
4020 SDValue Op = getRoot();
4021 Res = DAG.getNode(ISD::STACKSAVE, dl,
4022 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4024 DAG.setRoot(Res.getValue(1));
4027 case Intrinsic::stackrestore: {
4028 Res = getValue(I.getOperand(1));
4029 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4032 case Intrinsic::stackprotector: {
4033 // Emit code into the DAG to store the stack guard onto the stack.
4034 MachineFunction &MF = DAG.getMachineFunction();
4035 MachineFrameInfo *MFI = MF.getFrameInfo();
4036 EVT PtrTy = TLI.getPointerTy();
4038 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4039 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4041 int FI = FuncInfo.StaticAllocaMap[Slot];
4042 MFI->setStackProtectorIndex(FI);
4044 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4046 // Store the stack protector onto the stack.
4047 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4048 PseudoSourceValue::getFixedStack(FI),
4054 case Intrinsic::objectsize: {
4055 // If we don't know by now, we're never going to know.
4056 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4058 assert(CI && "Non-constant type in __builtin_object_size?");
4060 SDValue Arg = getValue(I.getOperand(0));
4061 EVT Ty = Arg.getValueType();
4063 if (CI->getZExtValue() == 0)
4064 Res = DAG.getConstant(-1ULL, Ty);
4066 Res = DAG.getConstant(0, Ty);
4071 case Intrinsic::var_annotation:
4072 // Discard annotate attributes
4075 case Intrinsic::init_trampoline: {
4076 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4080 Ops[1] = getValue(I.getOperand(1));
4081 Ops[2] = getValue(I.getOperand(2));
4082 Ops[3] = getValue(I.getOperand(3));
4083 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4084 Ops[5] = DAG.getSrcValue(F);
4086 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4087 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4091 DAG.setRoot(Res.getValue(1));
4094 case Intrinsic::gcroot:
4096 Value *Alloca = I.getOperand(1);
4097 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4099 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4100 GFI->addStackRoot(FI->getIndex(), TypeMap);
4103 case Intrinsic::gcread:
4104 case Intrinsic::gcwrite:
4105 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4107 case Intrinsic::flt_rounds:
4108 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4110 case Intrinsic::trap:
4111 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4113 case Intrinsic::uadd_with_overflow:
4114 return implVisitAluOverflow(I, ISD::UADDO);
4115 case Intrinsic::sadd_with_overflow:
4116 return implVisitAluOverflow(I, ISD::SADDO);
4117 case Intrinsic::usub_with_overflow:
4118 return implVisitAluOverflow(I, ISD::USUBO);
4119 case Intrinsic::ssub_with_overflow:
4120 return implVisitAluOverflow(I, ISD::SSUBO);
4121 case Intrinsic::umul_with_overflow:
4122 return implVisitAluOverflow(I, ISD::UMULO);
4123 case Intrinsic::smul_with_overflow:
4124 return implVisitAluOverflow(I, ISD::SMULO);
4126 case Intrinsic::prefetch: {
4129 Ops[1] = getValue(I.getOperand(1));
4130 Ops[2] = getValue(I.getOperand(2));
4131 Ops[3] = getValue(I.getOperand(3));
4132 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4136 case Intrinsic::memory_barrier: {
4139 for (int x = 1; x < 6; ++x)
4140 Ops[x] = getValue(I.getOperand(x));
4142 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4145 case Intrinsic::atomic_cmp_swap: {
4146 SDValue Root = getRoot();
4148 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4149 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4151 getValue(I.getOperand(1)),
4152 getValue(I.getOperand(2)),
4153 getValue(I.getOperand(3)),
4156 DAG.setRoot(L.getValue(1));
4159 case Intrinsic::atomic_load_add:
4160 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4161 case Intrinsic::atomic_load_sub:
4162 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4163 case Intrinsic::atomic_load_or:
4164 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4165 case Intrinsic::atomic_load_xor:
4166 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4167 case Intrinsic::atomic_load_and:
4168 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4169 case Intrinsic::atomic_load_nand:
4170 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4171 case Intrinsic::atomic_load_max:
4172 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4173 case Intrinsic::atomic_load_min:
4174 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4175 case Intrinsic::atomic_load_umin:
4176 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4177 case Intrinsic::atomic_load_umax:
4178 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4179 case Intrinsic::atomic_swap:
4180 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4182 case Intrinsic::invariant_start:
4183 case Intrinsic::lifetime_start:
4184 // Discard region information.
4185 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4187 case Intrinsic::invariant_end:
4188 case Intrinsic::lifetime_end:
4189 // Discard region information.
4194 /// Test if the given instruction is in a position to be optimized
4195 /// with a tail-call. This roughly means that it's in a block with
4196 /// a return and there's nothing that needs to be scheduled
4197 /// between it and the return.
4199 /// This function only tests target-independent requirements.
4201 isInTailCallPosition(const Instruction *I, Attributes CalleeRetAttr,
4202 const TargetLowering &TLI) {
4203 const BasicBlock *ExitBB = I->getParent();
4204 const TerminatorInst *Term = ExitBB->getTerminator();
4205 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4206 const Function *F = ExitBB->getParent();
4208 // The block must end in a return statement or an unreachable.
4209 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4211 // If I will have a chain, make sure no other instruction that will have a
4212 // chain interposes between I and the return.
4213 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4214 !I->isSafeToSpeculativelyExecute())
4215 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4219 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4220 !BBI->isSafeToSpeculativelyExecute())
4224 // If the block ends with a void return or unreachable, it doesn't matter
4225 // what the call's return type is.
4226 if (!Ret || Ret->getNumOperands() == 0) return true;
4228 // If the return value is undef, it doesn't matter what the call's
4230 if (isa<UndefValue>(Ret->getOperand(0))) return true;
4232 // Conservatively require the attributes of the call to match those of
4233 // the return. Ignore noalias because it doesn't affect the call sequence.
4234 unsigned CallerRetAttr = F->getAttributes().getRetAttributes();
4235 if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias)
4238 // Otherwise, make sure the unmodified return value of I is the return value.
4239 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4240 U = dyn_cast<Instruction>(U->getOperand(0))) {
4243 if (!U->hasOneUse())
4247 // Check for a truly no-op truncate.
4248 if (isa<TruncInst>(U) &&
4249 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4251 // Check for a truly no-op bitcast.
4252 if (isa<BitCastInst>(U) &&
4253 (U->getOperand(0)->getType() == U->getType() ||
4254 (isa<PointerType>(U->getOperand(0)->getType()) &&
4255 isa<PointerType>(U->getType()))))
4257 // Otherwise it's not a true no-op.
4264 void SelectionDAGBuilder::LowerCallTo(CallSite CS, SDValue Callee,
4266 MachineBasicBlock *LandingPad) {
4267 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4268 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4269 const Type *RetTy = FTy->getReturnType();
4270 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4271 unsigned BeginLabel = 0, EndLabel = 0;
4273 TargetLowering::ArgListTy Args;
4274 TargetLowering::ArgListEntry Entry;
4275 Args.reserve(CS.arg_size());
4277 // Check whether the function can return without sret-demotion.
4278 SmallVector<EVT, 4> OutVTs;
4279 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4280 SmallVector<uint64_t, 4> Offsets;
4281 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4282 OutVTs, OutsFlags, TLI, &Offsets);
4284 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4285 FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4287 SDValue DemoteStackSlot;
4289 if (!CanLowerReturn) {
4290 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4291 FTy->getReturnType());
4292 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4293 FTy->getReturnType());
4294 MachineFunction &MF = DAG.getMachineFunction();
4295 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4296 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4298 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4299 Entry.Node = DemoteStackSlot;
4300 Entry.Ty = StackSlotPtrType;
4301 Entry.isSExt = false;
4302 Entry.isZExt = false;
4303 Entry.isInReg = false;
4304 Entry.isSRet = true;
4305 Entry.isNest = false;
4306 Entry.isByVal = false;
4307 Entry.Alignment = Align;
4308 Args.push_back(Entry);
4309 RetTy = Type::getVoidTy(FTy->getContext());
4312 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4314 SDValue ArgNode = getValue(*i);
4315 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4317 unsigned attrInd = i - CS.arg_begin() + 1;
4318 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4319 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4320 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4321 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4322 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4323 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4324 Entry.Alignment = CS.getParamAlignment(attrInd);
4325 Args.push_back(Entry);
4328 if (LandingPad && MMI) {
4329 // Insert a label before the invoke call to mark the try range. This can be
4330 // used to detect deletion of the invoke via the MachineModuleInfo.
4331 BeginLabel = MMI->NextLabelID();
4333 // For SjLj, keep track of which landing pads go with which invokes
4334 // so as to maintain the ordering of pads in the LSDA.
4335 unsigned CallSiteIndex = MMI->getCurrentCallSite();
4336 if (CallSiteIndex) {
4337 MMI->setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4338 // Now that the call site is handled, stop tracking it.
4339 MMI->setCurrentCallSite(0);
4342 // Both PendingLoads and PendingExports must be flushed here;
4343 // this call might not return.
4345 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4346 getControlRoot(), BeginLabel));
4349 // Check if target-independent constraints permit a tail call here.
4350 // Target-dependent constraints are checked within TLI.LowerCallTo.
4352 !isInTailCallPosition(CS.getInstruction(),
4353 CS.getAttributes().getRetAttributes(),
4357 std::pair<SDValue,SDValue> Result =
4358 TLI.LowerCallTo(getRoot(), RetTy,
4359 CS.paramHasAttr(0, Attribute::SExt),
4360 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4361 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4362 CS.getCallingConv(),
4364 !CS.getInstruction()->use_empty(),
4365 Callee, Args, DAG, getCurDebugLoc(), SDNodeOrder);
4366 assert((isTailCall || Result.second.getNode()) &&
4367 "Non-null chain expected with non-tail call!");
4368 assert((Result.second.getNode() || !Result.first.getNode()) &&
4369 "Null value expected with tail call!");
4370 if (Result.first.getNode()) {
4371 setValue(CS.getInstruction(), Result.first);
4372 } else if (!CanLowerReturn && Result.second.getNode()) {
4373 // The instruction result is the result of loading from the
4374 // hidden sret parameter.
4375 SmallVector<EVT, 1> PVTs;
4376 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4378 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4379 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4380 EVT PtrVT = PVTs[0];
4381 unsigned NumValues = OutVTs.size();
4382 SmallVector<SDValue, 4> Values(NumValues);
4383 SmallVector<SDValue, 4> Chains(NumValues);
4385 for (unsigned i = 0; i < NumValues; ++i) {
4386 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4388 DAG.getConstant(Offsets[i], PtrVT));
4389 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4390 Add, NULL, Offsets[i], false, 1);
4392 Chains[i] = L.getValue(1);
4395 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4396 MVT::Other, &Chains[0], NumValues);
4397 PendingLoads.push_back(Chain);
4399 // Collect the legal value parts into potentially illegal values
4400 // that correspond to the original function's return values.
4401 SmallVector<EVT, 4> RetTys;
4402 RetTy = FTy->getReturnType();
4403 ComputeValueVTs(TLI, RetTy, RetTys);
4404 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4405 SmallVector<SDValue, 4> ReturnValues;
4406 unsigned CurReg = 0;
4407 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4409 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4410 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4412 SDValue ReturnValue =
4413 getCopyFromParts(DAG, getCurDebugLoc(), SDNodeOrder, &Values[CurReg], NumRegs,
4414 RegisterVT, VT, AssertOp);
4415 ReturnValues.push_back(ReturnValue);
4419 setValue(CS.getInstruction(),
4420 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4421 DAG.getVTList(&RetTys[0], RetTys.size()),
4422 &ReturnValues[0], ReturnValues.size()));
4426 // As a special case, a null chain means that a tail call has been emitted and
4427 // the DAG root is already updated.
4428 if (Result.second.getNode())
4429 DAG.setRoot(Result.second);
4433 if (LandingPad && MMI) {
4434 // Insert a label at the end of the invoke call to mark the try range. This
4435 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4436 EndLabel = MMI->NextLabelID();
4437 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4438 getRoot(), EndLabel));
4440 // Inform MachineModuleInfo of range.
4441 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4445 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4446 /// value is equal or not-equal to zero.
4447 static bool IsOnlyUsedInZeroEqualityComparison(Value *V) {
4448 for (Value::use_iterator UI = V->use_begin(), E = V->use_end();
4450 if (ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4451 if (IC->isEquality())
4452 if (Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4453 if (C->isNullValue())
4455 // Unknown instruction.
4461 static SDValue getMemCmpLoad(Value *PtrVal, MVT LoadVT, const Type *LoadTy,
4462 SelectionDAGBuilder &Builder) {
4464 // Check to see if this load can be trivially constant folded, e.g. if the
4465 // input is from a string literal.
4466 if (Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4467 // Cast pointer to the type we really want to load.
4468 LoadInput = ConstantExpr::getBitCast(LoadInput,
4469 PointerType::getUnqual(LoadTy));
4471 if (Constant *LoadCst = ConstantFoldLoadFromConstPtr(LoadInput, Builder.TD))
4472 return Builder.getValue(LoadCst);
4475 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4476 // still constant memory, the input chain can be the entry node.
4478 bool ConstantMemory = false;
4480 // Do not serialize (non-volatile) loads of constant memory with anything.
4481 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4482 Root = Builder.DAG.getEntryNode();
4483 ConstantMemory = true;
4485 // Do not serialize non-volatile loads against each other.
4486 Root = Builder.DAG.getRoot();
4489 SDValue Ptr = Builder.getValue(PtrVal);
4490 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4491 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4492 false /*volatile*/, 1 /* align=1 */);
4494 if (!ConstantMemory)
4495 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4500 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4501 /// If so, return true and lower it, otherwise return false and it will be
4502 /// lowered like a normal call.
4503 bool SelectionDAGBuilder::visitMemCmpCall(CallInst &I) {
4504 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4505 if (I.getNumOperands() != 4)
4508 Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
4509 if (!isa<PointerType>(LHS->getType()) || !isa<PointerType>(RHS->getType()) ||
4510 !isa<IntegerType>(I.getOperand(3)->getType()) ||
4511 !isa<IntegerType>(I.getType()))
4514 ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
4516 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4517 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4518 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4519 bool ActuallyDoIt = true;
4522 switch (Size->getZExtValue()) {
4524 LoadVT = MVT::Other;
4526 ActuallyDoIt = false;
4530 LoadTy = Type::getInt16Ty(Size->getContext());
4534 LoadTy = Type::getInt32Ty(Size->getContext());
4538 LoadTy = Type::getInt64Ty(Size->getContext());
4542 LoadVT = MVT::v4i32;
4543 LoadTy = Type::getInt32Ty(Size->getContext());
4544 LoadTy = VectorType::get(LoadTy, 4);
4549 // This turns into unaligned loads. We only do this if the target natively
4550 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4551 // we'll only produce a small number of byte loads.
4553 // Require that we can find a legal MVT, and only do this if the target
4554 // supports unaligned loads of that type. Expanding into byte loads would
4556 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4557 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4558 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4559 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4560 ActuallyDoIt = false;
4564 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4565 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4567 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4569 EVT CallVT = TLI.getValueType(I.getType(), true);
4570 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4580 void SelectionDAGBuilder::visitCall(CallInst &I) {
4581 const char *RenameFn = 0;
4582 if (Function *F = I.getCalledFunction()) {
4583 if (F->isDeclaration()) {
4584 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4586 if (unsigned IID = II->getIntrinsicID(F)) {
4587 RenameFn = visitIntrinsicCall(I, IID);
4592 if (unsigned IID = F->getIntrinsicID()) {
4593 RenameFn = visitIntrinsicCall(I, IID);
4599 // Check for well-known libc/libm calls. If the function is internal, it
4600 // can't be a library call.
4601 if (!F->hasLocalLinkage() && F->hasName()) {
4602 StringRef Name = F->getName();
4603 if (Name == "copysign" || Name == "copysignf") {
4604 if (I.getNumOperands() == 3 && // Basic sanity checks.
4605 I.getOperand(1)->getType()->isFloatingPoint() &&
4606 I.getType() == I.getOperand(1)->getType() &&
4607 I.getType() == I.getOperand(2)->getType()) {
4608 SDValue LHS = getValue(I.getOperand(1));
4609 SDValue RHS = getValue(I.getOperand(2));
4610 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4611 LHS.getValueType(), LHS, RHS));
4614 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4615 if (I.getNumOperands() == 2 && // Basic sanity checks.
4616 I.getOperand(1)->getType()->isFloatingPoint() &&
4617 I.getType() == I.getOperand(1)->getType()) {
4618 SDValue Tmp = getValue(I.getOperand(1));
4619 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4620 Tmp.getValueType(), Tmp));
4623 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4624 if (I.getNumOperands() == 2 && // Basic sanity checks.
4625 I.getOperand(1)->getType()->isFloatingPoint() &&
4626 I.getType() == I.getOperand(1)->getType() &&
4627 I.onlyReadsMemory()) {
4628 SDValue Tmp = getValue(I.getOperand(1));
4629 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4630 Tmp.getValueType(), Tmp));
4633 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4634 if (I.getNumOperands() == 2 && // Basic sanity checks.
4635 I.getOperand(1)->getType()->isFloatingPoint() &&
4636 I.getType() == I.getOperand(1)->getType() &&
4637 I.onlyReadsMemory()) {
4638 SDValue Tmp = getValue(I.getOperand(1));
4639 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4640 Tmp.getValueType(), Tmp));
4643 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4644 if (I.getNumOperands() == 2 && // Basic sanity checks.
4645 I.getOperand(1)->getType()->isFloatingPoint() &&
4646 I.getType() == I.getOperand(1)->getType() &&
4647 I.onlyReadsMemory()) {
4648 SDValue Tmp = getValue(I.getOperand(1));
4649 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4650 Tmp.getValueType(), Tmp));
4653 } else if (Name == "memcmp") {
4654 if (visitMemCmpCall(I))
4658 } else if (isa<InlineAsm>(I.getOperand(0))) {
4665 Callee = getValue(I.getOperand(0));
4667 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4669 // Check if we can potentially perform a tail call. More detailed checking is
4670 // be done within LowerCallTo, after more information about the call is known.
4671 LowerCallTo(&I, Callee, I.isTailCall());
4674 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4675 /// this value and returns the result as a ValueVT value. This uses
4676 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4677 /// If the Flag pointer is NULL, no flag is used.
4678 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4679 unsigned Order, SDValue &Chain,
4680 SDValue *Flag) const {
4681 // Assemble the legal parts into the final values.
4682 SmallVector<SDValue, 4> Values(ValueVTs.size());
4683 SmallVector<SDValue, 8> Parts;
4684 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4685 // Copy the legal parts from the registers.
4686 EVT ValueVT = ValueVTs[Value];
4687 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4688 EVT RegisterVT = RegVTs[Value];
4690 Parts.resize(NumRegs);
4691 for (unsigned i = 0; i != NumRegs; ++i) {
4694 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4697 *Flag = P.getValue(2);
4700 Chain = P.getValue(1);
4702 // If the source register was virtual and if we know something about it,
4703 // add an assert node.
4704 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4705 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4706 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4707 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4708 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4709 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4711 unsigned RegSize = RegisterVT.getSizeInBits();
4712 unsigned NumSignBits = LOI.NumSignBits;
4713 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4715 // FIXME: We capture more information than the dag can represent. For
4716 // now, just use the tightest assertzext/assertsext possible.
4718 EVT FromVT(MVT::Other);
4719 if (NumSignBits == RegSize)
4720 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4721 else if (NumZeroBits >= RegSize-1)
4722 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4723 else if (NumSignBits > RegSize-8)
4724 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4725 else if (NumZeroBits >= RegSize-8)
4726 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4727 else if (NumSignBits > RegSize-16)
4728 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4729 else if (NumZeroBits >= RegSize-16)
4730 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4731 else if (NumSignBits > RegSize-32)
4732 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4733 else if (NumZeroBits >= RegSize-32)
4734 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4736 if (FromVT != MVT::Other)
4737 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4738 RegisterVT, P, DAG.getValueType(FromVT));
4745 Values[Value] = getCopyFromParts(DAG, dl, Order, Parts.begin(),
4746 NumRegs, RegisterVT, ValueVT);
4751 return DAG.getNode(ISD::MERGE_VALUES, dl,
4752 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4753 &Values[0], ValueVTs.size());
4756 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4757 /// specified value into the registers specified by this object. This uses
4758 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4759 /// If the Flag pointer is NULL, no flag is used.
4760 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4761 unsigned Order, SDValue &Chain,
4762 SDValue *Flag) const {
4763 // Get the list of the values's legal parts.
4764 unsigned NumRegs = Regs.size();
4765 SmallVector<SDValue, 8> Parts(NumRegs);
4766 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4767 EVT ValueVT = ValueVTs[Value];
4768 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4769 EVT RegisterVT = RegVTs[Value];
4771 getCopyToParts(DAG, dl, Order,
4772 Val.getValue(Val.getResNo() + Value),
4773 &Parts[Part], NumParts, RegisterVT);
4777 // Copy the parts into the registers.
4778 SmallVector<SDValue, 8> Chains(NumRegs);
4779 for (unsigned i = 0; i != NumRegs; ++i) {
4782 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4784 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4785 *Flag = Part.getValue(1);
4788 Chains[i] = Part.getValue(0);
4791 if (NumRegs == 1 || Flag)
4792 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4793 // flagged to it. That is the CopyToReg nodes and the user are considered
4794 // a single scheduling unit. If we create a TokenFactor and return it as
4795 // chain, then the TokenFactor is both a predecessor (operand) of the
4796 // user as well as a successor (the TF operands are flagged to the user).
4797 // c1, f1 = CopyToReg
4798 // c2, f2 = CopyToReg
4799 // c3 = TokenFactor c1, c2
4802 Chain = Chains[NumRegs-1];
4804 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4807 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4808 /// operand list. This adds the code marker and includes the number of
4809 /// values added into it.
4810 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4811 bool HasMatching,unsigned MatchingIdx,
4812 SelectionDAG &DAG, unsigned Order,
4813 std::vector<SDValue> &Ops) const {
4814 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4815 unsigned Flag = Code | (Regs.size() << 3);
4817 Flag |= 0x80000000 | (MatchingIdx << 16);
4818 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
4821 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4822 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4823 EVT RegisterVT = RegVTs[Value];
4824 for (unsigned i = 0; i != NumRegs; ++i) {
4825 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4826 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4831 /// isAllocatableRegister - If the specified register is safe to allocate,
4832 /// i.e. it isn't a stack pointer or some other special register, return the
4833 /// register class for the register. Otherwise, return null.
4834 static const TargetRegisterClass *
4835 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4836 const TargetLowering &TLI,
4837 const TargetRegisterInfo *TRI) {
4838 EVT FoundVT = MVT::Other;
4839 const TargetRegisterClass *FoundRC = 0;
4840 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4841 E = TRI->regclass_end(); RCI != E; ++RCI) {
4842 EVT ThisVT = MVT::Other;
4844 const TargetRegisterClass *RC = *RCI;
4845 // If none of the the value types for this register class are valid, we
4846 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4847 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4849 if (TLI.isTypeLegal(*I)) {
4850 // If we have already found this register in a different register class,
4851 // choose the one with the largest VT specified. For example, on
4852 // PowerPC, we favor f64 register classes over f32.
4853 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4860 if (ThisVT == MVT::Other) continue;
4862 // NOTE: This isn't ideal. In particular, this might allocate the
4863 // frame pointer in functions that need it (due to them not being taken
4864 // out of allocation, because a variable sized allocation hasn't been seen
4865 // yet). This is a slight code pessimization, but should still work.
4866 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4867 E = RC->allocation_order_end(MF); I != E; ++I)
4869 // We found a matching register class. Keep looking at others in case
4870 // we find one with larger registers that this physreg is also in.
4881 /// AsmOperandInfo - This contains information for each constraint that we are
4883 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4884 public TargetLowering::AsmOperandInfo {
4886 /// CallOperand - If this is the result output operand or a clobber
4887 /// this is null, otherwise it is the incoming operand to the CallInst.
4888 /// This gets modified as the asm is processed.
4889 SDValue CallOperand;
4891 /// AssignedRegs - If this is a register or register class operand, this
4892 /// contains the set of register corresponding to the operand.
4893 RegsForValue AssignedRegs;
4895 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4896 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4899 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4900 /// busy in OutputRegs/InputRegs.
4901 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4902 std::set<unsigned> &OutputRegs,
4903 std::set<unsigned> &InputRegs,
4904 const TargetRegisterInfo &TRI) const {
4906 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4907 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4910 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4911 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4915 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4916 /// corresponds to. If there is no Value* for this operand, it returns
4918 EVT getCallOperandValEVT(LLVMContext &Context,
4919 const TargetLowering &TLI,
4920 const TargetData *TD) const {
4921 if (CallOperandVal == 0) return MVT::Other;
4923 if (isa<BasicBlock>(CallOperandVal))
4924 return TLI.getPointerTy();
4926 const llvm::Type *OpTy = CallOperandVal->getType();
4928 // If this is an indirect operand, the operand is a pointer to the
4931 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4933 llvm_report_error("Indirect operand for inline asm not a pointer!");
4934 OpTy = PtrTy->getElementType();
4937 // If OpTy is not a single value, it may be a struct/union that we
4938 // can tile with integers.
4939 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4940 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4949 OpTy = IntegerType::get(Context, BitSize);
4954 return TLI.getValueType(OpTy, true);
4958 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4960 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4961 const TargetRegisterInfo &TRI) {
4962 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4964 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4965 for (; *Aliases; ++Aliases)
4966 Regs.insert(*Aliases);
4969 } // end llvm namespace.
4972 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4973 /// specified operand. We prefer to assign virtual registers, to allow the
4974 /// register allocator to handle the assignment process. However, if the asm
4975 /// uses features that we can't model on machineinstrs, we have SDISel do the
4976 /// allocation. This produces generally horrible, but correct, code.
4978 /// OpInfo describes the operand.
4979 /// Input and OutputRegs are the set of already allocated physical registers.
4981 void SelectionDAGBuilder::
4982 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4983 std::set<unsigned> &OutputRegs,
4984 std::set<unsigned> &InputRegs) {
4985 LLVMContext &Context = FuncInfo.Fn->getContext();
4987 // Compute whether this value requires an input register, an output register,
4989 bool isOutReg = false;
4990 bool isInReg = false;
4991 switch (OpInfo.Type) {
4992 case InlineAsm::isOutput:
4995 // If there is an input constraint that matches this, we need to reserve
4996 // the input register so no other inputs allocate to it.
4997 isInReg = OpInfo.hasMatchingInput();
4999 case InlineAsm::isInput:
5003 case InlineAsm::isClobber:
5010 MachineFunction &MF = DAG.getMachineFunction();
5011 SmallVector<unsigned, 4> Regs;
5013 // If this is a constraint for a single physreg, or a constraint for a
5014 // register class, find it.
5015 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5016 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5017 OpInfo.ConstraintVT);
5019 unsigned NumRegs = 1;
5020 if (OpInfo.ConstraintVT != MVT::Other) {
5021 // If this is a FP input in an integer register (or visa versa) insert a bit
5022 // cast of the input value. More generally, handle any case where the input
5023 // value disagrees with the register class we plan to stick this in.
5024 if (OpInfo.Type == InlineAsm::isInput &&
5025 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5026 // Try to convert to the first EVT that the reg class contains. If the
5027 // types are identical size, use a bitcast to convert (e.g. two differing
5029 EVT RegVT = *PhysReg.second->vt_begin();
5030 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5031 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5032 RegVT, OpInfo.CallOperand);
5033 OpInfo.ConstraintVT = RegVT;
5034 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5035 // If the input is a FP value and we want it in FP registers, do a
5036 // bitcast to the corresponding integer type. This turns an f64 value
5037 // into i64, which can be passed with two i32 values on a 32-bit
5039 RegVT = EVT::getIntegerVT(Context,
5040 OpInfo.ConstraintVT.getSizeInBits());
5041 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5042 RegVT, OpInfo.CallOperand);
5043 OpInfo.ConstraintVT = RegVT;
5047 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5051 EVT ValueVT = OpInfo.ConstraintVT;
5053 // If this is a constraint for a specific physical register, like {r17},
5055 if (unsigned AssignedReg = PhysReg.first) {
5056 const TargetRegisterClass *RC = PhysReg.second;
5057 if (OpInfo.ConstraintVT == MVT::Other)
5058 ValueVT = *RC->vt_begin();
5060 // Get the actual register value type. This is important, because the user
5061 // may have asked for (e.g.) the AX register in i32 type. We need to
5062 // remember that AX is actually i16 to get the right extension.
5063 RegVT = *RC->vt_begin();
5065 // This is a explicit reference to a physical register.
5066 Regs.push_back(AssignedReg);
5068 // If this is an expanded reference, add the rest of the regs to Regs.
5070 TargetRegisterClass::iterator I = RC->begin();
5071 for (; *I != AssignedReg; ++I)
5072 assert(I != RC->end() && "Didn't find reg!");
5074 // Already added the first reg.
5076 for (; NumRegs; --NumRegs, ++I) {
5077 assert(I != RC->end() && "Ran out of registers to allocate!");
5082 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5083 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5084 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5088 // Otherwise, if this was a reference to an LLVM register class, create vregs
5089 // for this reference.
5090 if (const TargetRegisterClass *RC = PhysReg.second) {
5091 RegVT = *RC->vt_begin();
5092 if (OpInfo.ConstraintVT == MVT::Other)
5095 // Create the appropriate number of virtual registers.
5096 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5097 for (; NumRegs; --NumRegs)
5098 Regs.push_back(RegInfo.createVirtualRegister(RC));
5100 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5104 // This is a reference to a register class that doesn't directly correspond
5105 // to an LLVM register class. Allocate NumRegs consecutive, available,
5106 // registers from the class.
5107 std::vector<unsigned> RegClassRegs
5108 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5109 OpInfo.ConstraintVT);
5111 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5112 unsigned NumAllocated = 0;
5113 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5114 unsigned Reg = RegClassRegs[i];
5115 // See if this register is available.
5116 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5117 (isInReg && InputRegs.count(Reg))) { // Already used.
5118 // Make sure we find consecutive registers.
5123 // Check to see if this register is allocatable (i.e. don't give out the
5125 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5126 if (!RC) { // Couldn't allocate this register.
5127 // Reset NumAllocated to make sure we return consecutive registers.
5132 // Okay, this register is good, we can use it.
5135 // If we allocated enough consecutive registers, succeed.
5136 if (NumAllocated == NumRegs) {
5137 unsigned RegStart = (i-NumAllocated)+1;
5138 unsigned RegEnd = i+1;
5139 // Mark all of the allocated registers used.
5140 for (unsigned i = RegStart; i != RegEnd; ++i)
5141 Regs.push_back(RegClassRegs[i]);
5143 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5144 OpInfo.ConstraintVT);
5145 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5150 // Otherwise, we couldn't allocate enough registers for this.
5153 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5154 /// processed uses a memory 'm' constraint.
5156 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5157 const TargetLowering &TLI) {
5158 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5159 InlineAsm::ConstraintInfo &CI = CInfos[i];
5160 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5161 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5162 if (CType == TargetLowering::C_Memory)
5166 // Indirect operand accesses access memory.
5174 /// visitInlineAsm - Handle a call to an InlineAsm object.
5176 void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
5177 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5179 /// ConstraintOperands - Information about all of the constraints.
5180 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5182 std::set<unsigned> OutputRegs, InputRegs;
5184 // Do a prepass over the constraints, canonicalizing them, and building up the
5185 // ConstraintOperands list.
5186 std::vector<InlineAsm::ConstraintInfo>
5187 ConstraintInfos = IA->ParseConstraints();
5189 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5191 SDValue Chain, Flag;
5193 // We won't need to flush pending loads if this asm doesn't touch
5194 // memory and is nonvolatile.
5195 if (hasMemory || IA->hasSideEffects())
5198 Chain = DAG.getRoot();
5200 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5201 unsigned ResNo = 0; // ResNo - The result number of the next output.
5202 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5203 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5204 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5206 EVT OpVT = MVT::Other;
5208 // Compute the value type for each operand.
5209 switch (OpInfo.Type) {
5210 case InlineAsm::isOutput:
5211 // Indirect outputs just consume an argument.
5212 if (OpInfo.isIndirect) {
5213 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5217 // The return value of the call is this value. As such, there is no
5218 // corresponding argument.
5219 assert(!CS.getType()->isVoidTy() &&
5221 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5222 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5224 assert(ResNo == 0 && "Asm only has one result!");
5225 OpVT = TLI.getValueType(CS.getType());
5229 case InlineAsm::isInput:
5230 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5232 case InlineAsm::isClobber:
5237 // If this is an input or an indirect output, process the call argument.
5238 // BasicBlocks are labels, currently appearing only in asm's.
5239 if (OpInfo.CallOperandVal) {
5240 // Strip bitcasts, if any. This mostly comes up for functions.
5241 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5243 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5244 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5246 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5249 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5252 OpInfo.ConstraintVT = OpVT;
5255 // Second pass over the constraints: compute which constraint option to use
5256 // and assign registers to constraints that want a specific physreg.
5257 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5258 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5260 // If this is an output operand with a matching input operand, look up the
5261 // matching input. If their types mismatch, e.g. one is an integer, the
5262 // other is floating point, or their sizes are different, flag it as an
5264 if (OpInfo.hasMatchingInput()) {
5265 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5266 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5267 if ((OpInfo.ConstraintVT.isInteger() !=
5268 Input.ConstraintVT.isInteger()) ||
5269 (OpInfo.ConstraintVT.getSizeInBits() !=
5270 Input.ConstraintVT.getSizeInBits())) {
5271 llvm_report_error("Unsupported asm: input constraint"
5272 " with a matching output constraint of incompatible"
5275 Input.ConstraintVT = OpInfo.ConstraintVT;
5279 // Compute the constraint code and ConstraintType to use.
5280 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5282 // If this is a memory input, and if the operand is not indirect, do what we
5283 // need to to provide an address for the memory input.
5284 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5285 !OpInfo.isIndirect) {
5286 assert(OpInfo.Type == InlineAsm::isInput &&
5287 "Can only indirectify direct input operands!");
5289 // Memory operands really want the address of the value. If we don't have
5290 // an indirect input, put it in the constpool if we can, otherwise spill
5291 // it to a stack slot.
5293 // If the operand is a float, integer, or vector constant, spill to a
5294 // constant pool entry to get its address.
5295 Value *OpVal = OpInfo.CallOperandVal;
5296 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5297 isa<ConstantVector>(OpVal)) {
5298 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5299 TLI.getPointerTy());
5301 // Otherwise, create a stack slot and emit a store to it before the
5303 const Type *Ty = OpVal->getType();
5304 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5305 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5306 MachineFunction &MF = DAG.getMachineFunction();
5307 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5308 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5309 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5310 OpInfo.CallOperand, StackSlot, NULL, 0);
5311 OpInfo.CallOperand = StackSlot;
5314 // There is no longer a Value* corresponding to this operand.
5315 OpInfo.CallOperandVal = 0;
5317 // It is now an indirect operand.
5318 OpInfo.isIndirect = true;
5321 // If this constraint is for a specific register, allocate it before
5323 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5324 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5327 ConstraintInfos.clear();
5329 // Second pass - Loop over all of the operands, assigning virtual or physregs
5330 // to register class operands.
5331 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5332 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5334 // C_Register operands have already been allocated, Other/Memory don't need
5336 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5337 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5340 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5341 std::vector<SDValue> AsmNodeOperands;
5342 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5343 AsmNodeOperands.push_back(
5344 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5345 TLI.getPointerTy()));
5348 // Loop over all of the inputs, copying the operand values into the
5349 // appropriate registers and processing the output regs.
5350 RegsForValue RetValRegs;
5352 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5353 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5355 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5356 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5358 switch (OpInfo.Type) {
5359 case InlineAsm::isOutput: {
5360 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5361 OpInfo.ConstraintType != TargetLowering::C_Register) {
5362 // Memory output, or 'other' output (e.g. 'X' constraint).
5363 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5365 // Add information to the INLINEASM node to know about this output.
5366 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5367 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5368 TLI.getPointerTy()));
5369 AsmNodeOperands.push_back(OpInfo.CallOperand);
5373 // Otherwise, this is a register or register class output.
5375 // Copy the output from the appropriate register. Find a register that
5377 if (OpInfo.AssignedRegs.Regs.empty()) {
5378 llvm_report_error("Couldn't allocate output reg for"
5379 " constraint '" + OpInfo.ConstraintCode + "'!");
5382 // If this is an indirect operand, store through the pointer after the
5384 if (OpInfo.isIndirect) {
5385 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5386 OpInfo.CallOperandVal));
5388 // This is the result value of the call.
5389 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5390 // Concatenate this output onto the outputs list.
5391 RetValRegs.append(OpInfo.AssignedRegs);
5394 // Add information to the INLINEASM node to know that this register is
5396 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5397 6 /* EARLYCLOBBER REGDEF */ :
5405 case InlineAsm::isInput: {
5406 SDValue InOperandVal = OpInfo.CallOperand;
5408 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5409 // If this is required to match an output register we have already set,
5410 // just use its register.
5411 unsigned OperandNo = OpInfo.getMatchedOperand();
5413 // Scan until we find the definition we already emitted of this operand.
5414 // When we find it, create a RegsForValue operand.
5415 unsigned CurOp = 2; // The first operand.
5416 for (; OperandNo; --OperandNo) {
5417 // Advance to the next operand.
5419 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5420 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5421 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5422 (OpFlag & 7) == 4 /*MEM*/) &&
5423 "Skipped past definitions?");
5424 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5428 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5429 if ((OpFlag & 7) == 2 /*REGDEF*/
5430 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5431 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5432 if (OpInfo.isIndirect) {
5433 llvm_report_error("Don't know how to handle tied indirect "
5434 "register inputs yet!");
5436 RegsForValue MatchedRegs;
5437 MatchedRegs.TLI = &TLI;
5438 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5439 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5440 MatchedRegs.RegVTs.push_back(RegVT);
5441 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5442 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5444 MatchedRegs.Regs.push_back
5445 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5447 // Use the produced MatchedRegs object to
5448 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5449 SDNodeOrder, Chain, &Flag);
5450 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5451 true, OpInfo.getMatchedOperand(),
5452 DAG, SDNodeOrder, AsmNodeOperands);
5455 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5456 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5457 "Unexpected number of operands");
5458 // Add information to the INLINEASM node to know about this input.
5459 // See InlineAsm.h isUseOperandTiedToDef.
5460 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5461 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5462 TLI.getPointerTy()));
5463 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5468 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5469 assert(!OpInfo.isIndirect &&
5470 "Don't know how to handle indirect other inputs yet!");
5472 std::vector<SDValue> Ops;
5473 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5474 hasMemory, Ops, DAG);
5476 llvm_report_error("Invalid operand for inline asm"
5477 " constraint '" + OpInfo.ConstraintCode + "'!");
5480 // Add information to the INLINEASM node to know about this input.
5481 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5482 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5483 TLI.getPointerTy()));
5484 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5486 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5487 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5488 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5489 "Memory operands expect pointer values");
5491 // Add information to the INLINEASM node to know about this input.
5492 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5493 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5494 TLI.getPointerTy()));
5495 AsmNodeOperands.push_back(InOperandVal);
5499 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5500 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5501 "Unknown constraint type!");
5502 assert(!OpInfo.isIndirect &&
5503 "Don't know how to handle indirect register inputs yet!");
5505 // Copy the input into the appropriate registers.
5506 if (OpInfo.AssignedRegs.Regs.empty()) {
5507 llvm_report_error("Couldn't allocate input reg for"
5508 " constraint '"+ OpInfo.ConstraintCode +"'!");
5511 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5512 SDNodeOrder, Chain, &Flag);
5514 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5519 case InlineAsm::isClobber: {
5520 // Add the clobbered value to the operand list, so that the register
5521 // allocator is aware that the physreg got clobbered.
5522 if (!OpInfo.AssignedRegs.Regs.empty())
5523 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5524 false, 0, DAG, SDNodeOrder,
5531 // Finish up input operands.
5532 AsmNodeOperands[0] = Chain;
5533 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5535 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5536 DAG.getVTList(MVT::Other, MVT::Flag),
5537 &AsmNodeOperands[0], AsmNodeOperands.size());
5538 Flag = Chain.getValue(1);
5540 // If this asm returns a register value, copy the result from that register
5541 // and set it as the value of the call.
5542 if (!RetValRegs.Regs.empty()) {
5543 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5544 SDNodeOrder, Chain, &Flag);
5546 // FIXME: Why don't we do this for inline asms with MRVs?
5547 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5548 EVT ResultType = TLI.getValueType(CS.getType());
5550 // If any of the results of the inline asm is a vector, it may have the
5551 // wrong width/num elts. This can happen for register classes that can
5552 // contain multiple different value types. The preg or vreg allocated may
5553 // not have the same VT as was expected. Convert it to the right type
5554 // with bit_convert.
5555 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5556 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5559 } else if (ResultType != Val.getValueType() &&
5560 ResultType.isInteger() && Val.getValueType().isInteger()) {
5561 // If a result value was tied to an input value, the computed result may
5562 // have a wider width than the expected result. Extract the relevant
5564 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5567 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5570 setValue(CS.getInstruction(), Val);
5571 // Don't need to use this as a chain in this case.
5572 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5576 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5578 // Process indirect outputs, first output all of the flagged copies out of
5580 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5581 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5582 Value *Ptr = IndirectStoresToEmit[i].second;
5583 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5584 SDNodeOrder, Chain, &Flag);
5585 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5589 // Emit the non-flagged stores from the physregs.
5590 SmallVector<SDValue, 8> OutChains;
5591 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5592 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5593 StoresToEmit[i].first,
5594 getValue(StoresToEmit[i].second),
5595 StoresToEmit[i].second, 0);
5596 OutChains.push_back(Val);
5599 if (!OutChains.empty())
5600 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5601 &OutChains[0], OutChains.size());
5606 void SelectionDAGBuilder::visitVAStart(CallInst &I) {
5607 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5608 MVT::Other, getRoot(),
5609 getValue(I.getOperand(1)),
5610 DAG.getSrcValue(I.getOperand(1))));
5613 void SelectionDAGBuilder::visitVAArg(VAArgInst &I) {
5614 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5615 getRoot(), getValue(I.getOperand(0)),
5616 DAG.getSrcValue(I.getOperand(0)));
5618 DAG.setRoot(V.getValue(1));
5621 void SelectionDAGBuilder::visitVAEnd(CallInst &I) {
5622 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5623 MVT::Other, getRoot(),
5624 getValue(I.getOperand(1)),
5625 DAG.getSrcValue(I.getOperand(1))));
5628 void SelectionDAGBuilder::visitVACopy(CallInst &I) {
5629 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5630 MVT::Other, getRoot(),
5631 getValue(I.getOperand(1)),
5632 getValue(I.getOperand(2)),
5633 DAG.getSrcValue(I.getOperand(1)),
5634 DAG.getSrcValue(I.getOperand(2))));
5637 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5638 /// implementation, which just calls LowerCall.
5639 /// FIXME: When all targets are
5640 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5641 std::pair<SDValue, SDValue>
5642 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5643 bool RetSExt, bool RetZExt, bool isVarArg,
5644 bool isInreg, unsigned NumFixedArgs,
5645 CallingConv::ID CallConv, bool isTailCall,
5646 bool isReturnValueUsed,
5648 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl,
5650 // Handle all of the outgoing arguments.
5651 SmallVector<ISD::OutputArg, 32> Outs;
5652 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5653 SmallVector<EVT, 4> ValueVTs;
5654 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5655 for (unsigned Value = 0, NumValues = ValueVTs.size();
5656 Value != NumValues; ++Value) {
5657 EVT VT = ValueVTs[Value];
5658 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5659 SDValue Op = SDValue(Args[i].Node.getNode(),
5660 Args[i].Node.getResNo() + Value);
5661 ISD::ArgFlagsTy Flags;
5662 unsigned OriginalAlignment =
5663 getTargetData()->getABITypeAlignment(ArgTy);
5669 if (Args[i].isInReg)
5673 if (Args[i].isByVal) {
5675 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5676 const Type *ElementTy = Ty->getElementType();
5677 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5678 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5679 // For ByVal, alignment should come from FE. BE will guess if this
5680 // info is not there but there are cases it cannot get right.
5681 if (Args[i].Alignment)
5682 FrameAlign = Args[i].Alignment;
5683 Flags.setByValAlign(FrameAlign);
5684 Flags.setByValSize(FrameSize);
5688 Flags.setOrigAlign(OriginalAlignment);
5690 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5691 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5692 SmallVector<SDValue, 4> Parts(NumParts);
5693 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5696 ExtendKind = ISD::SIGN_EXTEND;
5697 else if (Args[i].isZExt)
5698 ExtendKind = ISD::ZERO_EXTEND;
5700 getCopyToParts(DAG, dl, Order, Op, &Parts[0], NumParts,
5701 PartVT, ExtendKind);
5703 for (unsigned j = 0; j != NumParts; ++j) {
5704 // if it isn't first piece, alignment must be 1
5705 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5706 if (NumParts > 1 && j == 0)
5707 MyFlags.Flags.setSplit();
5709 MyFlags.Flags.setOrigAlign(1);
5711 Outs.push_back(MyFlags);
5716 // Handle the incoming return values from the call.
5717 SmallVector<ISD::InputArg, 32> Ins;
5718 SmallVector<EVT, 4> RetTys;
5719 ComputeValueVTs(*this, RetTy, RetTys);
5720 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5722 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5723 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5724 for (unsigned i = 0; i != NumRegs; ++i) {
5725 ISD::InputArg MyFlags;
5726 MyFlags.VT = RegisterVT;
5727 MyFlags.Used = isReturnValueUsed;
5729 MyFlags.Flags.setSExt();
5731 MyFlags.Flags.setZExt();
5733 MyFlags.Flags.setInReg();
5734 Ins.push_back(MyFlags);
5738 SmallVector<SDValue, 4> InVals;
5739 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5740 Outs, Ins, dl, DAG, InVals);
5742 // Verify that the target's LowerCall behaved as expected.
5743 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5744 "LowerCall didn't return a valid chain!");
5745 assert((!isTailCall || InVals.empty()) &&
5746 "LowerCall emitted a return value for a tail call!");
5747 assert((isTailCall || InVals.size() == Ins.size()) &&
5748 "LowerCall didn't emit the correct number of values!");
5749 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5750 assert(InVals[i].getNode() &&
5751 "LowerCall emitted a null value!");
5752 assert(Ins[i].VT == InVals[i].getValueType() &&
5753 "LowerCall emitted a value with the wrong type!");
5756 // For a tail call, the return value is merely live-out and there aren't
5757 // any nodes in the DAG representing it. Return a special value to
5758 // indicate that a tail call has been emitted and no more Instructions
5759 // should be processed in the current block.
5762 return std::make_pair(SDValue(), SDValue());
5765 // Collect the legal value parts into potentially illegal values
5766 // that correspond to the original function's return values.
5767 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5769 AssertOp = ISD::AssertSext;
5771 AssertOp = ISD::AssertZext;
5772 SmallVector<SDValue, 4> ReturnValues;
5773 unsigned CurReg = 0;
5774 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5776 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5777 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5779 ReturnValues.push_back(getCopyFromParts(DAG, dl, Order, &InVals[CurReg],
5780 NumRegs, RegisterVT, VT,
5785 // For a function returning void, there is no return value. We can't create
5786 // such a node, so we just return a null return value in that case. In
5787 // that case, nothing will actualy look at the value.
5788 if (ReturnValues.empty())
5789 return std::make_pair(SDValue(), Chain);
5791 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5792 DAG.getVTList(&RetTys[0], RetTys.size()),
5793 &ReturnValues[0], ReturnValues.size());
5794 return std::make_pair(Res, Chain);
5797 void TargetLowering::LowerOperationWrapper(SDNode *N,
5798 SmallVectorImpl<SDValue> &Results,
5799 SelectionDAG &DAG) {
5800 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5802 Results.push_back(Res);
5805 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5806 llvm_unreachable("LowerOperation not implemented for this target!");
5810 void SelectionDAGBuilder::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5811 SDValue Op = getValue(V);
5812 assert((Op.getOpcode() != ISD::CopyFromReg ||
5813 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5814 "Copy from a reg to the same reg!");
5815 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5817 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5818 SDValue Chain = DAG.getEntryNode();
5819 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), SDNodeOrder, Chain, 0);
5820 PendingExports.push_back(Chain);
5823 #include "llvm/CodeGen/SelectionDAGISel.h"
5825 void SelectionDAGISel::LowerArguments(BasicBlock *LLVMBB) {
5826 // If this is the entry block, emit arguments.
5827 Function &F = *LLVMBB->getParent();
5828 SelectionDAG &DAG = SDB->DAG;
5829 SDValue OldRoot = DAG.getRoot();
5830 DebugLoc dl = SDB->getCurDebugLoc();
5831 const TargetData *TD = TLI.getTargetData();
5832 SmallVector<ISD::InputArg, 16> Ins;
5834 // Check whether the function can return without sret-demotion.
5835 SmallVector<EVT, 4> OutVTs;
5836 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
5837 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5838 OutVTs, OutsFlags, TLI);
5839 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5841 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
5842 OutVTs, OutsFlags, DAG);
5843 if (!FLI.CanLowerReturn) {
5844 // Put in an sret pointer parameter before all the other parameters.
5845 SmallVector<EVT, 1> ValueVTs;
5846 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5848 // NOTE: Assuming that a pointer will never break down to more than one VT
5850 ISD::ArgFlagsTy Flags;
5852 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), ValueVTs[0]);
5853 ISD::InputArg RetArg(Flags, RegisterVT, true);
5854 Ins.push_back(RetArg);
5857 // Set up the incoming argument description vector.
5859 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5860 I != E; ++I, ++Idx) {
5861 SmallVector<EVT, 4> ValueVTs;
5862 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5863 bool isArgValueUsed = !I->use_empty();
5864 for (unsigned Value = 0, NumValues = ValueVTs.size();
5865 Value != NumValues; ++Value) {
5866 EVT VT = ValueVTs[Value];
5867 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5868 ISD::ArgFlagsTy Flags;
5869 unsigned OriginalAlignment =
5870 TD->getABITypeAlignment(ArgTy);
5872 if (F.paramHasAttr(Idx, Attribute::ZExt))
5874 if (F.paramHasAttr(Idx, Attribute::SExt))
5876 if (F.paramHasAttr(Idx, Attribute::InReg))
5878 if (F.paramHasAttr(Idx, Attribute::StructRet))
5880 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5882 const PointerType *Ty = cast<PointerType>(I->getType());
5883 const Type *ElementTy = Ty->getElementType();
5884 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5885 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5886 // For ByVal, alignment should be passed from FE. BE will guess if
5887 // this info is not there but there are cases it cannot get right.
5888 if (F.getParamAlignment(Idx))
5889 FrameAlign = F.getParamAlignment(Idx);
5890 Flags.setByValAlign(FrameAlign);
5891 Flags.setByValSize(FrameSize);
5893 if (F.paramHasAttr(Idx, Attribute::Nest))
5895 Flags.setOrigAlign(OriginalAlignment);
5897 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5898 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5899 for (unsigned i = 0; i != NumRegs; ++i) {
5900 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5901 if (NumRegs > 1 && i == 0)
5902 MyFlags.Flags.setSplit();
5903 // if it isn't first piece, alignment must be 1
5905 MyFlags.Flags.setOrigAlign(1);
5906 Ins.push_back(MyFlags);
5911 // Call the target to set up the argument values.
5912 SmallVector<SDValue, 8> InVals;
5913 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5917 // Verify that the target's LowerFormalArguments behaved as expected.
5918 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5919 "LowerFormalArguments didn't return a valid chain!");
5920 assert(InVals.size() == Ins.size() &&
5921 "LowerFormalArguments didn't emit the correct number of values!");
5923 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5924 assert(InVals[i].getNode() &&
5925 "LowerFormalArguments emitted a null value!");
5926 assert(Ins[i].VT == InVals[i].getValueType() &&
5927 "LowerFormalArguments emitted a value with the wrong type!");
5931 // Update the DAG with the new chain value resulting from argument lowering.
5932 DAG.setRoot(NewRoot);
5934 // Set up the argument values.
5937 if (!FLI.CanLowerReturn) {
5938 // Create a virtual register for the sret pointer, and put in a copy
5939 // from the sret argument into it.
5940 SmallVector<EVT, 1> ValueVTs;
5941 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5942 EVT VT = ValueVTs[0];
5943 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5944 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5945 SDValue ArgValue = getCopyFromParts(DAG, dl, 0, &InVals[0], 1,
5946 RegVT, VT, AssertOp);
5948 MachineFunction& MF = SDB->DAG.getMachineFunction();
5949 MachineRegisterInfo& RegInfo = MF.getRegInfo();
5950 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
5951 FLI.DemoteRegister = SRetReg;
5952 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
5954 DAG.setRoot(NewRoot);
5956 // i indexes lowered arguments. Bump it past the hidden sret argument.
5957 // Idx indexes LLVM arguments. Don't touch it.
5961 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5963 SmallVector<SDValue, 4> ArgValues;
5964 SmallVector<EVT, 4> ValueVTs;
5965 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5966 unsigned NumValues = ValueVTs.size();
5967 for (unsigned Value = 0; Value != NumValues; ++Value) {
5968 EVT VT = ValueVTs[Value];
5969 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5970 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5972 if (!I->use_empty()) {
5973 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5974 if (F.paramHasAttr(Idx, Attribute::SExt))
5975 AssertOp = ISD::AssertSext;
5976 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5977 AssertOp = ISD::AssertZext;
5979 ArgValues.push_back(getCopyFromParts(DAG, dl, 0, &InVals[i],
5980 NumParts, PartVT, VT,
5987 if (!I->use_empty()) {
5988 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
5989 SDB->getCurDebugLoc());
5990 SDB->setValue(I, Res);
5992 // If this argument is live outside of the entry block, insert a copy from
5993 // whereever we got it to the vreg that other BB's will reference it as.
5994 SDB->CopyToExportRegsIfNeeded(I);
5998 assert(i == InVals.size() && "Argument register count mismatch!");
6000 // Finally, if the target has anything special to do, allow it to do so.
6001 // FIXME: this should insert code into the DAG!
6002 EmitFunctionEntryCode(F, SDB->DAG.getMachineFunction());
6005 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6006 /// ensure constants are generated when needed. Remember the virtual registers
6007 /// that need to be added to the Machine PHI nodes as input. We cannot just
6008 /// directly add them, because expansion might result in multiple MBB's for one
6009 /// BB. As such, the start of the BB might correspond to a different MBB than
6013 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
6014 TerminatorInst *TI = LLVMBB->getTerminator();
6016 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6018 // Check successor nodes' PHI nodes that expect a constant to be available
6020 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6021 BasicBlock *SuccBB = TI->getSuccessor(succ);
6022 if (!isa<PHINode>(SuccBB->begin())) continue;
6023 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6025 // If this terminator has multiple identical successors (common for
6026 // switches), only handle each succ once.
6027 if (!SuccsHandled.insert(SuccMBB)) continue;
6029 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6032 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6033 // nodes and Machine PHI nodes, but the incoming operands have not been
6035 for (BasicBlock::iterator I = SuccBB->begin();
6036 (PN = dyn_cast<PHINode>(I)); ++I) {
6037 // Ignore dead phi's.
6038 if (PN->use_empty()) continue;
6041 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6043 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
6044 unsigned &RegOut = SDB->ConstantsOut[C];
6046 RegOut = FuncInfo->CreateRegForValue(C);
6047 SDB->CopyValueToVirtualRegister(C, RegOut);
6051 Reg = FuncInfo->ValueMap[PHIOp];
6053 assert(isa<AllocaInst>(PHIOp) &&
6054 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6055 "Didn't codegen value into a register!??");
6056 Reg = FuncInfo->CreateRegForValue(PHIOp);
6057 SDB->CopyValueToVirtualRegister(PHIOp, Reg);
6061 // Remember that this register needs to added to the machine PHI node as
6062 // the input for this MBB.
6063 SmallVector<EVT, 4> ValueVTs;
6064 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6065 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6066 EVT VT = ValueVTs[vti];
6067 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6068 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6069 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6070 Reg += NumRegisters;
6074 SDB->ConstantsOut.clear();
6077 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6078 /// supports legal types, and it emits MachineInstrs directly instead of
6079 /// creating SelectionDAG nodes.
6082 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6084 TerminatorInst *TI = LLVMBB->getTerminator();
6086 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6087 unsigned OrigNumPHINodesToUpdate = SDB->PHINodesToUpdate.size();
6089 // Check successor nodes' PHI nodes that expect a constant to be available
6091 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6092 BasicBlock *SuccBB = TI->getSuccessor(succ);
6093 if (!isa<PHINode>(SuccBB->begin())) continue;
6094 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6096 // If this terminator has multiple identical successors (common for
6097 // switches), only handle each succ once.
6098 if (!SuccsHandled.insert(SuccMBB)) continue;
6100 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6103 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6104 // nodes and Machine PHI nodes, but the incoming operands have not been
6106 for (BasicBlock::iterator I = SuccBB->begin();
6107 (PN = dyn_cast<PHINode>(I)); ++I) {
6108 // Ignore dead phi's.
6109 if (PN->use_empty()) continue;
6111 // Only handle legal types. Two interesting things to note here. First,
6112 // by bailing out early, we may leave behind some dead instructions,
6113 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6114 // own moves. Second, this check is necessary becuase FastISel doesn't
6115 // use CreateRegForValue to create registers, so it always creates
6116 // exactly one register for each non-void instruction.
6117 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6118 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6121 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6123 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6128 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6130 unsigned Reg = F->getRegForValue(PHIOp);
6132 SDB->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6135 SDB->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));