1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
82 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
83 cl::desc("Enable fast-math-flags for DAG nodes"));
85 // Limit the width of DAG chains. This is important in general to prevent
86 // DAG-based analysis from blowing up. For example, alias analysis and
87 // load clustering may not complete in reasonable time. It is difficult to
88 // recognize and avoid this situation within each individual analysis, and
89 // future analyses are likely to have the same behavior. Limiting DAG width is
90 // the safe approach and will be especially important with global DAGs.
92 // MaxParallelChains default is arbitrarily high to avoid affecting
93 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
94 // sequence over this should have been converted to llvm.memcpy by the
95 // frontend. It easy to induce this behavior with .ll code such as:
96 // %buffer = alloca [4096 x i8]
97 // %data = load [4096 x i8]* %argPtr
98 // store [4096 x i8] %data, [4096 x i8]* %buffer
99 static const unsigned MaxParallelChains = 64;
101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts, unsigned NumParts,
103 MVT PartVT, EVT ValueVT, const Value *V);
105 /// getCopyFromParts - Create a value that contains the specified legal parts
106 /// combined into the value they represent. If the parts combine to a type
107 /// larger then ValueVT then AssertOp can be used to specify whether the extra
108 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
109 /// (ISD::AssertSext).
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
111 const SDValue *Parts,
112 unsigned NumParts, MVT PartVT, EVT ValueVT,
114 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
115 if (ValueVT.isVector())
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
119 assert(NumParts > 0 && "No parts to assemble!");
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 SDValue Val = Parts[0];
124 // Assemble the value from multiple parts.
125 if (ValueVT.isInteger()) {
126 unsigned PartBits = PartVT.getSizeInBits();
127 unsigned ValueBits = ValueVT.getSizeInBits();
129 // Assemble the power of 2 part.
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 << Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
139 if (RoundParts > 2) {
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
143 RoundParts / 2, PartVT, HalfVT, V);
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
149 if (DAG.getDataLayout().isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
154 if (RoundParts < NumParts) {
155 // Assemble the trailing non-power-of-2 part.
156 unsigned OddParts = NumParts - RoundParts;
157 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
158 Hi = getCopyFromParts(DAG, DL,
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
161 // Combine the round and odd parts.
163 if (DAG.getDataLayout().isBigEndian())
165 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
168 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
169 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
170 TLI.getPointerTy(DAG.getDataLayout())));
171 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
172 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
174 } else if (PartVT.isFloatingPoint()) {
175 // FP split into multiple FP parts (for ppcf128)
176 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
179 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
180 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
181 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
183 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
185 // FP split into integer parts (soft fp)
186 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
187 !PartVT.isVector() && "Unexpected split");
188 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
189 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
193 // There is now one part, held in Val. Correct it to match ValueVT.
194 EVT PartEVT = Val.getValueType();
196 if (PartEVT == ValueVT)
199 if (PartEVT.isInteger() && ValueVT.isInteger()) {
200 if (ValueVT.bitsLT(PartEVT)) {
201 // For a truncate, see if we have any information to
202 // indicate whether the truncated bits will always be
203 // zero or sign-extension.
204 if (AssertOp != ISD::DELETED_NODE)
205 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
206 DAG.getValueType(ValueVT));
207 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
209 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
212 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
213 // FP_ROUND's are always exact here.
214 if (ValueVT.bitsLT(Val.getValueType()))
216 ISD::FP_ROUND, DL, ValueVT, Val,
217 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
219 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
223 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
225 llvm_unreachable("Unknown mismatch!");
228 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
229 const Twine &ErrMsg) {
230 const Instruction *I = dyn_cast_or_null<Instruction>(V);
232 return Ctx.emitError(ErrMsg);
234 const char *AsmError = ", possible invalid constraint for vector type";
235 if (const CallInst *CI = dyn_cast<CallInst>(I))
236 if (isa<InlineAsm>(CI->getCalledValue()))
237 return Ctx.emitError(I, ErrMsg + AsmError);
239 return Ctx.emitError(I, ErrMsg);
242 /// getCopyFromPartsVector - Create a value that contains the specified legal
243 /// parts combined into the value they represent. If the parts combine to a
244 /// type larger then ValueVT then AssertOp can be used to specify whether the
245 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
246 /// ValueVT (ISD::AssertSext).
247 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
248 const SDValue *Parts, unsigned NumParts,
249 MVT PartVT, EVT ValueVT, const Value *V) {
250 assert(ValueVT.isVector() && "Not a vector value");
251 assert(NumParts > 0 && "No parts to assemble!");
252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
253 SDValue Val = Parts[0];
255 // Handle a multi-element vector.
259 unsigned NumIntermediates;
261 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
262 NumIntermediates, RegisterVT);
263 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
264 NumParts = NumRegs; // Silence a compiler warning.
265 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
266 assert(RegisterVT.getSizeInBits() ==
267 Parts[0].getSimpleValueType().getSizeInBits() &&
268 "Part type sizes don't match!");
270 // Assemble the parts into intermediate operands.
271 SmallVector<SDValue, 8> Ops(NumIntermediates);
272 if (NumIntermediates == NumParts) {
273 // If the register was not expanded, truncate or copy the value,
275 for (unsigned i = 0; i != NumParts; ++i)
276 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
277 PartVT, IntermediateVT, V);
278 } else if (NumParts > 0) {
279 // If the intermediate type was expanded, build the intermediate
280 // operands from the parts.
281 assert(NumParts % NumIntermediates == 0 &&
282 "Must expand into a divisible number of parts!");
283 unsigned Factor = NumParts / NumIntermediates;
284 for (unsigned i = 0; i != NumIntermediates; ++i)
285 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
286 PartVT, IntermediateVT, V);
289 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
290 // intermediate operands.
291 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
296 // There is now one part, held in Val. Correct it to match ValueVT.
297 EVT PartEVT = Val.getValueType();
299 if (PartEVT == ValueVT)
302 if (PartEVT.isVector()) {
303 // If the element type of the source/dest vectors are the same, but the
304 // parts vector has more elements than the value vector, then we have a
305 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
307 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
308 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
309 "Cannot narrow, it would be a lossy transformation");
311 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
312 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
315 // Vector/Vector bitcast.
316 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
317 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
319 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
320 "Cannot handle this kind of promotion");
321 // Promoted vector extract
322 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
326 // Trivial bitcast if the types are the same size and the destination
327 // vector type is legal.
328 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
329 TLI.isTypeLegal(ValueVT))
330 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
332 // Handle cases such as i8 -> <1 x i1>
333 if (ValueVT.getVectorNumElements() != 1) {
334 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
335 "non-trivial scalar-to-vector conversion");
336 return DAG.getUNDEF(ValueVT);
339 if (ValueVT.getVectorNumElements() == 1 &&
340 ValueVT.getVectorElementType() != PartEVT)
341 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
343 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
346 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
347 SDValue Val, SDValue *Parts, unsigned NumParts,
348 MVT PartVT, const Value *V);
350 /// getCopyToParts - Create a series of nodes that contain the specified value
351 /// split into legal parts. If the parts contain more bits than Val, then, for
352 /// integers, ExtendKind can be used to specify how to generate the extra bits.
353 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
354 SDValue Val, SDValue *Parts, unsigned NumParts,
355 MVT PartVT, const Value *V,
356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
357 EVT ValueVT = Val.getValueType();
359 // Handle the vector case separately.
360 if (ValueVT.isVector())
361 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
363 unsigned PartBits = PartVT.getSizeInBits();
364 unsigned OrigNumParts = NumParts;
365 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
366 "Copying to an illegal type!");
371 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
372 EVT PartEVT = PartVT;
373 if (PartEVT == ValueVT) {
374 assert(NumParts == 1 && "No-op copy with multiple parts!");
379 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
380 // If the parts cover more bits than the value has, promote the value.
381 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
382 assert(NumParts == 1 && "Do not know what to promote to!");
383 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
386 ValueVT.isInteger() &&
387 "Unknown mismatch!");
388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
389 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
390 if (PartVT == MVT::x86mmx)
391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 } else if (PartBits == ValueVT.getSizeInBits()) {
394 // Different types of the same size.
395 assert(NumParts == 1 && PartEVT != ValueVT);
396 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
397 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
398 // If the parts cover less bits than value has, truncate the value.
399 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
400 ValueVT.isInteger() &&
401 "Unknown mismatch!");
402 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
403 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
404 if (PartVT == MVT::x86mmx)
405 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
408 // The value may have changed - recompute ValueVT.
409 ValueVT = Val.getValueType();
410 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
411 "Failed to tile the value with PartVT!");
414 if (PartEVT != ValueVT)
415 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
416 "scalar-to-vector conversion failed");
422 // Expand the value into multiple parts.
423 if (NumParts & (NumParts - 1)) {
424 // The number of parts is not a power of 2. Split off and copy the tail.
425 assert(PartVT.isInteger() && ValueVT.isInteger() &&
426 "Do not know what to expand to!");
427 unsigned RoundParts = 1 << Log2_32(NumParts);
428 unsigned RoundBits = RoundParts * PartBits;
429 unsigned OddParts = NumParts - RoundParts;
430 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
431 DAG.getIntPtrConstant(RoundBits, DL));
432 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
434 if (DAG.getDataLayout().isBigEndian())
435 // The odd parts were reversed by getCopyToParts - unreverse them.
436 std::reverse(Parts + RoundParts, Parts + NumParts);
438 NumParts = RoundParts;
439 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
440 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
443 // The number of parts is a power of 2. Repeatedly bisect the value using
445 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
446 EVT::getIntegerVT(*DAG.getContext(),
447 ValueVT.getSizeInBits()),
450 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
451 for (unsigned i = 0; i < NumParts; i += StepSize) {
452 unsigned ThisBits = StepSize * PartBits / 2;
453 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
454 SDValue &Part0 = Parts[i];
455 SDValue &Part1 = Parts[i+StepSize/2];
457 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
459 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
460 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
462 if (ThisBits == PartBits && ThisVT != PartVT) {
463 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
464 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
469 if (DAG.getDataLayout().isBigEndian())
470 std::reverse(Parts, Parts + OrigNumParts);
474 /// getCopyToPartsVector - Create a series of nodes that contain the specified
475 /// value split into legal parts.
476 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
477 SDValue Val, SDValue *Parts, unsigned NumParts,
478 MVT PartVT, const Value *V) {
479 EVT ValueVT = Val.getValueType();
480 assert(ValueVT.isVector() && "Not a vector");
481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
484 EVT PartEVT = PartVT;
485 if (PartEVT == ValueVT) {
487 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
488 // Bitconvert vector->vector case.
489 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
490 } else if (PartVT.isVector() &&
491 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
492 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
493 EVT ElementVT = PartVT.getVectorElementType();
494 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
496 SmallVector<SDValue, 16> Ops;
497 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getNode(
499 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
500 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
502 for (unsigned i = ValueVT.getVectorNumElements(),
503 e = PartVT.getVectorNumElements(); i != e; ++i)
504 Ops.push_back(DAG.getUNDEF(ElementVT));
506 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
508 // FIXME: Use CONCAT for 2x -> 4x.
510 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
511 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
512 } else if (PartVT.isVector() &&
513 PartEVT.getVectorElementType().bitsGE(
514 ValueVT.getVectorElementType()) &&
515 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
517 // Promoted vector extract
518 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
524 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
525 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
527 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
552 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
553 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
554 TLI.getVectorIdxTy(DAG.getDataLayout())));
556 Ops[i] = DAG.getNode(
557 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
558 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
579 RegsForValue::RegsForValue() {}
581 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
585 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
586 const DataLayout &DL, unsigned Reg, Type *Ty) {
587 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
589 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
590 EVT ValueVT = ValueVTs[Value];
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1163 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1164 auto &DL = DAG.getDataLayout();
1165 SDValue Chain = getControlRoot();
1166 SmallVector<ISD::OutputArg, 8> Outs;
1167 SmallVector<SDValue, 8> OutVals;
1169 if (!FuncInfo.CanLowerReturn) {
1170 unsigned DemoteReg = FuncInfo.DemoteRegister;
1171 const Function *F = I.getParent()->getParent();
1173 // Emit a store of the return value through the virtual register.
1174 // Leave Outs empty so that LowerReturn won't try to load return
1175 // registers the usual way.
1176 SmallVector<EVT, 1> PtrValueVTs;
1177 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1180 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1181 SDValue RetOp = getValue(I.getOperand(0));
1183 SmallVector<EVT, 4> ValueVTs;
1184 SmallVector<uint64_t, 4> Offsets;
1185 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1186 unsigned NumValues = ValueVTs.size();
1188 SmallVector<SDValue, 4> Chains(NumValues);
1189 for (unsigned i = 0; i != NumValues; ++i) {
1190 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1191 RetPtr.getValueType(), RetPtr,
1192 DAG.getIntPtrConstant(Offsets[i],
1195 DAG.getStore(Chain, getCurSDLoc(),
1196 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1197 // FIXME: better loc info would be nice.
1198 Add, MachinePointerInfo(), false, false, 0);
1201 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1202 MVT::Other, Chains);
1203 } else if (I.getNumOperands() != 0) {
1204 SmallVector<EVT, 4> ValueVTs;
1205 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1206 unsigned NumValues = ValueVTs.size();
1208 SDValue RetOp = getValue(I.getOperand(0));
1210 const Function *F = I.getParent()->getParent();
1212 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1213 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1215 ExtendKind = ISD::SIGN_EXTEND;
1216 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1218 ExtendKind = ISD::ZERO_EXTEND;
1220 LLVMContext &Context = F->getContext();
1221 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1224 for (unsigned j = 0; j != NumValues; ++j) {
1225 EVT VT = ValueVTs[j];
1227 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1228 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1230 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1231 MVT PartVT = TLI.getRegisterType(Context, VT);
1232 SmallVector<SDValue, 4> Parts(NumParts);
1233 getCopyToParts(DAG, getCurSDLoc(),
1234 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1235 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1237 // 'inreg' on function refers to return value
1238 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1242 // Propagate extension type if any
1243 if (ExtendKind == ISD::SIGN_EXTEND)
1245 else if (ExtendKind == ISD::ZERO_EXTEND)
1248 for (unsigned i = 0; i < NumParts; ++i) {
1249 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1250 VT, /*isfixed=*/true, 0, 0));
1251 OutVals.push_back(Parts[i]);
1257 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1258 CallingConv::ID CallConv =
1259 DAG.getMachineFunction().getFunction()->getCallingConv();
1260 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1261 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1263 // Verify that the target's LowerReturn behaved as expected.
1264 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1265 "LowerReturn didn't return a valid chain!");
1267 // Update the DAG with the new chain value resulting from return lowering.
1271 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1272 /// created for it, emit nodes to copy the value into the virtual
1274 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1276 if (V->getType()->isEmptyTy())
1279 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1280 if (VMI != FuncInfo.ValueMap.end()) {
1281 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1282 CopyValueToVirtualRegister(V, VMI->second);
1286 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1287 /// the current basic block, add it to ValueMap now so that we'll get a
1289 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1290 // No need to export constants.
1291 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1293 // Already exported?
1294 if (FuncInfo.isExportedInst(V)) return;
1296 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1297 CopyValueToVirtualRegister(V, Reg);
1300 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1301 const BasicBlock *FromBB) {
1302 // The operands of the setcc have to be in this block. We don't know
1303 // how to export them from some other block.
1304 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1305 // Can export from current BB.
1306 if (VI->getParent() == FromBB)
1309 // Is already exported, noop.
1310 return FuncInfo.isExportedInst(V);
1313 // If this is an argument, we can export it if the BB is the entry block or
1314 // if it is already exported.
1315 if (isa<Argument>(V)) {
1316 if (FromBB == &FromBB->getParent()->getEntryBlock())
1319 // Otherwise, can only export this if it is already exported.
1320 return FuncInfo.isExportedInst(V);
1323 // Otherwise, constants can always be exported.
1327 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1328 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1329 const MachineBasicBlock *Dst) const {
1330 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1333 const BasicBlock *SrcBB = Src->getBasicBlock();
1334 const BasicBlock *DstBB = Dst->getBasicBlock();
1335 return BPI->getEdgeWeight(SrcBB, DstBB);
1338 void SelectionDAGBuilder::
1339 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1340 uint32_t Weight /* = 0 */) {
1342 Weight = getEdgeWeight(Src, Dst);
1343 Src->addSuccessor(Dst, Weight);
1347 static bool InBlock(const Value *V, const BasicBlock *BB) {
1348 if (const Instruction *I = dyn_cast<Instruction>(V))
1349 return I->getParent() == BB;
1353 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1354 /// This function emits a branch and is used at the leaves of an OR or an
1355 /// AND operator tree.
1358 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1359 MachineBasicBlock *TBB,
1360 MachineBasicBlock *FBB,
1361 MachineBasicBlock *CurBB,
1362 MachineBasicBlock *SwitchBB,
1365 const BasicBlock *BB = CurBB->getBasicBlock();
1367 // If the leaf of the tree is a comparison, merge the condition into
1369 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1370 // The operands of the cmp have to be in this block. We don't know
1371 // how to export them from some other block. If this is the first block
1372 // of the sequence, no exporting is needed.
1373 if (CurBB == SwitchBB ||
1374 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1375 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1376 ISD::CondCode Condition;
1377 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1378 Condition = getICmpCondCode(IC->getPredicate());
1379 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1380 Condition = getFCmpCondCode(FC->getPredicate());
1381 if (TM.Options.NoNaNsFPMath)
1382 Condition = getFCmpCodeWithoutNaN(Condition);
1384 (void)Condition; // silence warning.
1385 llvm_unreachable("Unknown compare instruction");
1388 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1389 TBB, FBB, CurBB, TWeight, FWeight);
1390 SwitchCases.push_back(CB);
1395 // Create a CaseBlock record representing this branch.
1396 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1397 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1398 SwitchCases.push_back(CB);
1401 /// Scale down both weights to fit into uint32_t.
1402 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1403 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1404 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1405 NewTrue = NewTrue / Scale;
1406 NewFalse = NewFalse / Scale;
1409 /// FindMergedConditions - If Cond is an expression like
1410 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1411 MachineBasicBlock *TBB,
1412 MachineBasicBlock *FBB,
1413 MachineBasicBlock *CurBB,
1414 MachineBasicBlock *SwitchBB,
1415 unsigned Opc, uint32_t TWeight,
1417 // If this node is not part of the or/and tree, emit it as a branch.
1418 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1419 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1420 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1421 BOp->getParent() != CurBB->getBasicBlock() ||
1422 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1423 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1424 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1429 // Create TmpBB after CurBB.
1430 MachineFunction::iterator BBI = CurBB;
1431 MachineFunction &MF = DAG.getMachineFunction();
1432 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1433 CurBB->getParent()->insert(++BBI, TmpBB);
1435 if (Opc == Instruction::Or) {
1436 // Codegen X | Y as:
1445 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1446 // The requirement is that
1447 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1448 // = TrueProb for original BB.
1449 // Assuming the original weights are A and B, one choice is to set BB1's
1450 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1452 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1453 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1454 // TmpBB, but the math is more complicated.
1456 uint64_t NewTrueWeight = TWeight;
1457 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1458 ScaleWeights(NewTrueWeight, NewFalseWeight);
1459 // Emit the LHS condition.
1460 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1461 NewTrueWeight, NewFalseWeight);
1463 NewTrueWeight = TWeight;
1464 NewFalseWeight = 2 * (uint64_t)FWeight;
1465 ScaleWeights(NewTrueWeight, NewFalseWeight);
1466 // Emit the RHS condition into TmpBB.
1467 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1468 NewTrueWeight, NewFalseWeight);
1470 assert(Opc == Instruction::And && "Unknown merge op!");
1471 // Codegen X & Y as:
1479 // This requires creation of TmpBB after CurBB.
1481 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1482 // The requirement is that
1483 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1484 // = FalseProb for original BB.
1485 // Assuming the original weights are A and B, one choice is to set BB1's
1486 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1488 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1490 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1491 uint64_t NewFalseWeight = FWeight;
1492 ScaleWeights(NewTrueWeight, NewFalseWeight);
1493 // Emit the LHS condition.
1494 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1495 NewTrueWeight, NewFalseWeight);
1497 NewTrueWeight = 2 * (uint64_t)TWeight;
1498 NewFalseWeight = FWeight;
1499 ScaleWeights(NewTrueWeight, NewFalseWeight);
1500 // Emit the RHS condition into TmpBB.
1501 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1502 NewTrueWeight, NewFalseWeight);
1506 /// If the set of cases should be emitted as a series of branches, return true.
1507 /// If we should emit this as a bunch of and/or'd together conditions, return
1510 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1511 if (Cases.size() != 2) return true;
1513 // If this is two comparisons of the same values or'd or and'd together, they
1514 // will get folded into a single comparison, so don't emit two blocks.
1515 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1516 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1517 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1518 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1522 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1523 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1524 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1525 Cases[0].CC == Cases[1].CC &&
1526 isa<Constant>(Cases[0].CmpRHS) &&
1527 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1528 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1530 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1537 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1538 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1540 // Update machine-CFG edges.
1541 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1543 if (I.isUnconditional()) {
1544 // Update machine-CFG edges.
1545 BrMBB->addSuccessor(Succ0MBB);
1547 // If this is not a fall-through branch or optimizations are switched off,
1549 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1550 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1551 MVT::Other, getControlRoot(),
1552 DAG.getBasicBlock(Succ0MBB)));
1557 // If this condition is one of the special cases we handle, do special stuff
1559 const Value *CondVal = I.getCondition();
1560 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1562 // If this is a series of conditions that are or'd or and'd together, emit
1563 // this as a sequence of branches instead of setcc's with and/or operations.
1564 // As long as jumps are not expensive, this should improve performance.
1565 // For example, instead of something like:
1578 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1579 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1580 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1581 BOp->getOpcode() == Instruction::Or)) {
1582 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1583 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1584 getEdgeWeight(BrMBB, Succ1MBB));
1585 // If the compares in later blocks need to use values not currently
1586 // exported from this block, export them now. This block should always
1587 // be the first entry.
1588 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1590 // Allow some cases to be rejected.
1591 if (ShouldEmitAsBranches(SwitchCases)) {
1592 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1593 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1594 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1597 // Emit the branch for this block.
1598 visitSwitchCase(SwitchCases[0], BrMBB);
1599 SwitchCases.erase(SwitchCases.begin());
1603 // Okay, we decided not to do this, remove any inserted MBB's and clear
1605 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1606 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1608 SwitchCases.clear();
1612 // Create a CaseBlock record representing this branch.
1613 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1614 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1616 // Use visitSwitchCase to actually insert the fast branch sequence for this
1618 visitSwitchCase(CB, BrMBB);
1621 /// visitSwitchCase - Emits the necessary code to represent a single node in
1622 /// the binary search tree resulting from lowering a switch instruction.
1623 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1624 MachineBasicBlock *SwitchBB) {
1626 SDValue CondLHS = getValue(CB.CmpLHS);
1627 SDLoc dl = getCurSDLoc();
1629 // Build the setcc now.
1631 // Fold "(X == true)" to X and "(X == false)" to !X to
1632 // handle common cases produced by branch lowering.
1633 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1634 CB.CC == ISD::SETEQ)
1636 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1637 CB.CC == ISD::SETEQ) {
1638 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1639 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1641 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1643 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1645 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1646 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1648 SDValue CmpOp = getValue(CB.CmpMHS);
1649 EVT VT = CmpOp.getValueType();
1651 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1652 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1655 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1656 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1657 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1658 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1662 // Update successor info
1663 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1664 // TrueBB and FalseBB are always different unless the incoming IR is
1665 // degenerate. This only happens when running llc on weird IR.
1666 if (CB.TrueBB != CB.FalseBB)
1667 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1669 // If the lhs block is the next block, invert the condition so that we can
1670 // fall through to the lhs instead of the rhs block.
1671 if (CB.TrueBB == NextBlock(SwitchBB)) {
1672 std::swap(CB.TrueBB, CB.FalseBB);
1673 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1674 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1677 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1678 MVT::Other, getControlRoot(), Cond,
1679 DAG.getBasicBlock(CB.TrueBB));
1681 // Insert the false branch. Do this even if it's a fall through branch,
1682 // this makes it easier to do DAG optimizations which require inverting
1683 // the branch condition.
1684 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1685 DAG.getBasicBlock(CB.FalseBB));
1687 DAG.setRoot(BrCond);
1690 /// visitJumpTable - Emit JumpTable node in the current MBB
1691 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1692 // Emit the code for the jump table
1693 assert(JT.Reg != -1U && "Should lower JT Header first!");
1694 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1695 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1697 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1698 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1699 MVT::Other, Index.getValue(1),
1701 DAG.setRoot(BrJumpTable);
1704 /// visitJumpTableHeader - This function emits necessary code to produce index
1705 /// in the JumpTable from switch case.
1706 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1707 JumpTableHeader &JTH,
1708 MachineBasicBlock *SwitchBB) {
1709 SDLoc dl = getCurSDLoc();
1711 // Subtract the lowest switch case value from the value being switched on and
1712 // conditional branch to default mbb if the result is greater than the
1713 // difference between smallest and largest cases.
1714 SDValue SwitchOp = getValue(JTH.SValue);
1715 EVT VT = SwitchOp.getValueType();
1716 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1717 DAG.getConstant(JTH.First, dl, VT));
1719 // The SDNode we just created, which holds the value being switched on minus
1720 // the smallest case value, needs to be copied to a virtual register so it
1721 // can be used as an index into the jump table in a subsequent basic block.
1722 // This value may be smaller or larger than the target's pointer type, and
1723 // therefore require extension or truncating.
1724 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1725 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1727 unsigned JumpTableReg =
1728 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1729 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1730 JumpTableReg, SwitchOp);
1731 JT.Reg = JumpTableReg;
1733 // Emit the range check for the jump table, and branch to the default block
1734 // for the switch statement if the value being switched on exceeds the largest
1735 // case in the switch.
1736 SDValue CMP = DAG.getSetCC(
1737 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1738 Sub.getValueType()),
1739 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1741 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1742 MVT::Other, CopyTo, CMP,
1743 DAG.getBasicBlock(JT.Default));
1745 // Avoid emitting unnecessary branches to the next block.
1746 if (JT.MBB != NextBlock(SwitchBB))
1747 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1748 DAG.getBasicBlock(JT.MBB));
1750 DAG.setRoot(BrCond);
1753 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1754 /// tail spliced into a stack protector check success bb.
1756 /// For a high level explanation of how this fits into the stack protector
1757 /// generation see the comment on the declaration of class
1758 /// StackProtectorDescriptor.
1759 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1760 MachineBasicBlock *ParentBB) {
1762 // First create the loads to the guard/stack slot for the comparison.
1763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1764 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1766 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1767 int FI = MFI->getStackProtectorIndex();
1769 const Value *IRGuard = SPD.getGuard();
1770 SDValue GuardPtr = getValue(IRGuard);
1771 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1773 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1776 SDLoc dl = getCurSDLoc();
1778 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1779 // guard value from the virtual register holding the value. Otherwise, emit a
1780 // volatile load to retrieve the stack guard value.
1781 unsigned GuardReg = SPD.getGuardReg();
1783 if (GuardReg && TLI.useLoadStackGuardNode())
1784 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1787 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1788 GuardPtr, MachinePointerInfo(IRGuard, 0),
1789 true, false, false, Align);
1791 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1793 MachinePointerInfo::getFixedStack(FI),
1794 true, false, false, Align);
1796 // Perform the comparison via a subtract/getsetcc.
1797 EVT VT = Guard.getValueType();
1798 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1800 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1802 Sub.getValueType()),
1803 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1805 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1806 // branch to failure MBB.
1807 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1808 MVT::Other, StackSlot.getOperand(0),
1809 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1810 // Otherwise branch to success MBB.
1811 SDValue Br = DAG.getNode(ISD::BR, dl,
1813 DAG.getBasicBlock(SPD.getSuccessMBB()));
1818 /// Codegen the failure basic block for a stack protector check.
1820 /// A failure stack protector machine basic block consists simply of a call to
1821 /// __stack_chk_fail().
1823 /// For a high level explanation of how this fits into the stack protector
1824 /// generation see the comment on the declaration of class
1825 /// StackProtectorDescriptor.
1827 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1828 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1830 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1831 nullptr, 0, false, getCurSDLoc(), false, false).second;
1835 /// visitBitTestHeader - This function emits necessary code to produce value
1836 /// suitable for "bit tests"
1837 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1838 MachineBasicBlock *SwitchBB) {
1839 SDLoc dl = getCurSDLoc();
1841 // Subtract the minimum value
1842 SDValue SwitchOp = getValue(B.SValue);
1843 EVT VT = SwitchOp.getValueType();
1844 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1845 DAG.getConstant(B.First, dl, VT));
1848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1849 SDValue RangeCmp = DAG.getSetCC(
1850 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1851 Sub.getValueType()),
1852 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1854 // Determine the type of the test operands.
1855 bool UsePtrType = false;
1856 if (!TLI.isTypeLegal(VT))
1859 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1860 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1861 // Switch table case range are encoded into series of masks.
1862 // Just use pointer type, it's guaranteed to fit.
1868 VT = TLI.getPointerTy(DAG.getDataLayout());
1869 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1872 B.RegVT = VT.getSimpleVT();
1873 B.Reg = FuncInfo.CreateReg(B.RegVT);
1874 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1876 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1878 addSuccessorWithWeight(SwitchBB, B.Default);
1879 addSuccessorWithWeight(SwitchBB, MBB);
1881 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1882 MVT::Other, CopyTo, RangeCmp,
1883 DAG.getBasicBlock(B.Default));
1885 // Avoid emitting unnecessary branches to the next block.
1886 if (MBB != NextBlock(SwitchBB))
1887 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1888 DAG.getBasicBlock(MBB));
1890 DAG.setRoot(BrRange);
1893 /// visitBitTestCase - this function produces one "bit test"
1894 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1895 MachineBasicBlock* NextMBB,
1896 uint32_t BranchWeightToNext,
1899 MachineBasicBlock *SwitchBB) {
1900 SDLoc dl = getCurSDLoc();
1902 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1904 unsigned PopCount = countPopulation(B.Mask);
1905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1906 if (PopCount == 1) {
1907 // Testing for a single bit; just compare the shift count with what it
1908 // would need to be to shift a 1 bit in that position.
1910 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1911 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1913 } else if (PopCount == BB.Range) {
1914 // There is only one zero bit in the range, test for it directly.
1916 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1917 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1920 // Make desired shift
1921 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1922 DAG.getConstant(1, dl, VT), ShiftOp);
1924 // Emit bit tests and jumps
1925 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1926 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1928 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1929 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1932 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1933 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1934 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1935 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1937 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1938 MVT::Other, getControlRoot(),
1939 Cmp, DAG.getBasicBlock(B.TargetBB));
1941 // Avoid emitting unnecessary branches to the next block.
1942 if (NextMBB != NextBlock(SwitchBB))
1943 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1944 DAG.getBasicBlock(NextMBB));
1949 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1950 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1952 // Retrieve successors.
1953 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1954 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1956 const Value *Callee(I.getCalledValue());
1957 const Function *Fn = dyn_cast<Function>(Callee);
1958 if (isa<InlineAsm>(Callee))
1960 else if (Fn && Fn->isIntrinsic()) {
1961 switch (Fn->getIntrinsicID()) {
1963 llvm_unreachable("Cannot invoke this intrinsic");
1964 case Intrinsic::donothing:
1965 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1967 case Intrinsic::experimental_patchpoint_void:
1968 case Intrinsic::experimental_patchpoint_i64:
1969 visitPatchpoint(&I, LandingPad);
1971 case Intrinsic::experimental_gc_statepoint:
1972 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1976 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1978 // If the value of the invoke is used outside of its defining block, make it
1979 // available as a virtual register.
1980 // We already took care of the exported value for the statepoint instruction
1981 // during call to the LowerStatepoint.
1982 if (!isStatepoint(I)) {
1983 CopyToExportRegsIfNeeded(&I);
1986 // Update successor info
1987 addSuccessorWithWeight(InvokeMBB, Return);
1988 addSuccessorWithWeight(InvokeMBB, LandingPad);
1990 // Drop into normal successor.
1991 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1992 MVT::Other, getControlRoot(),
1993 DAG.getBasicBlock(Return)));
1996 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1997 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2000 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2001 assert(FuncInfo.MBB->isLandingPad() &&
2002 "Call to landingpad not in landing pad!");
2004 MachineBasicBlock *MBB = FuncInfo.MBB;
2005 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2006 AddLandingPadInfo(LP, MMI, MBB);
2008 // If there aren't registers to copy the values into (e.g., during SjLj
2009 // exceptions), then don't bother to create these DAG nodes.
2010 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2011 if (TLI.getExceptionPointerRegister() == 0 &&
2012 TLI.getExceptionSelectorRegister() == 0)
2015 SmallVector<EVT, 2> ValueVTs;
2016 SDLoc dl = getCurSDLoc();
2017 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2018 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2020 // Get the two live-in registers as SDValues. The physregs have already been
2021 // copied into virtual registers.
2023 if (FuncInfo.ExceptionPointerVirtReg) {
2024 Ops[0] = DAG.getZExtOrTrunc(
2025 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2026 FuncInfo.ExceptionPointerVirtReg,
2027 TLI.getPointerTy(DAG.getDataLayout())),
2030 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2032 Ops[1] = DAG.getZExtOrTrunc(
2033 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2034 FuncInfo.ExceptionSelectorVirtReg,
2035 TLI.getPointerTy(DAG.getDataLayout())),
2039 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2040 DAG.getVTList(ValueVTs), Ops);
2044 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2046 for (const CaseCluster &CC : Clusters)
2047 assert(CC.Low == CC.High && "Input clusters must be single-case");
2050 std::sort(Clusters.begin(), Clusters.end(),
2051 [](const CaseCluster &a, const CaseCluster &b) {
2052 return a.Low->getValue().slt(b.Low->getValue());
2055 // Merge adjacent clusters with the same destination.
2056 const unsigned N = Clusters.size();
2057 unsigned DstIndex = 0;
2058 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2059 CaseCluster &CC = Clusters[SrcIndex];
2060 const ConstantInt *CaseVal = CC.Low;
2061 MachineBasicBlock *Succ = CC.MBB;
2063 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2064 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2065 // If this case has the same successor and is a neighbour, merge it into
2066 // the previous cluster.
2067 Clusters[DstIndex - 1].High = CaseVal;
2068 Clusters[DstIndex - 1].Weight += CC.Weight;
2069 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2071 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2072 sizeof(Clusters[SrcIndex]));
2075 Clusters.resize(DstIndex);
2078 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2079 MachineBasicBlock *Last) {
2081 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2082 if (JTCases[i].first.HeaderBB == First)
2083 JTCases[i].first.HeaderBB = Last;
2085 // Update BitTestCases.
2086 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2087 if (BitTestCases[i].Parent == First)
2088 BitTestCases[i].Parent = Last;
2091 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2092 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2094 // Update machine-CFG edges with unique successors.
2095 SmallSet<BasicBlock*, 32> Done;
2096 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2097 BasicBlock *BB = I.getSuccessor(i);
2098 bool Inserted = Done.insert(BB).second;
2102 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2103 addSuccessorWithWeight(IndirectBrMBB, Succ);
2106 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2107 MVT::Other, getControlRoot(),
2108 getValue(I.getAddress())));
2111 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2112 if (DAG.getTarget().Options.TrapUnreachable)
2113 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2116 void SelectionDAGBuilder::visitFSub(const User &I) {
2117 // -0.0 - X --> fneg
2118 Type *Ty = I.getType();
2119 if (isa<Constant>(I.getOperand(0)) &&
2120 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2121 SDValue Op2 = getValue(I.getOperand(1));
2122 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2123 Op2.getValueType(), Op2));
2127 visitBinary(I, ISD::FSUB);
2130 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2131 SDValue Op1 = getValue(I.getOperand(0));
2132 SDValue Op2 = getValue(I.getOperand(1));
2139 if (const OverflowingBinaryOperator *OFBinOp =
2140 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2141 nuw = OFBinOp->hasNoUnsignedWrap();
2142 nsw = OFBinOp->hasNoSignedWrap();
2144 if (const PossiblyExactOperator *ExactOp =
2145 dyn_cast<const PossiblyExactOperator>(&I))
2146 exact = ExactOp->isExact();
2147 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2148 FMF = FPOp->getFastMathFlags();
2151 Flags.setExact(exact);
2152 Flags.setNoSignedWrap(nsw);
2153 Flags.setNoUnsignedWrap(nuw);
2154 if (EnableFMFInDAG) {
2155 Flags.setAllowReciprocal(FMF.allowReciprocal());
2156 Flags.setNoInfs(FMF.noInfs());
2157 Flags.setNoNaNs(FMF.noNaNs());
2158 Flags.setNoSignedZeros(FMF.noSignedZeros());
2159 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2161 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2163 setValue(&I, BinNodeValue);
2166 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2167 SDValue Op1 = getValue(I.getOperand(0));
2168 SDValue Op2 = getValue(I.getOperand(1));
2170 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2171 Op2.getValueType(), DAG.getDataLayout());
2173 // Coerce the shift amount to the right type if we can.
2174 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2175 unsigned ShiftSize = ShiftTy.getSizeInBits();
2176 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2177 SDLoc DL = getCurSDLoc();
2179 // If the operand is smaller than the shift count type, promote it.
2180 if (ShiftSize > Op2Size)
2181 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2183 // If the operand is larger than the shift count type but the shift
2184 // count type has enough bits to represent any shift value, truncate
2185 // it now. This is a common case and it exposes the truncate to
2186 // optimization early.
2187 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2188 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2189 // Otherwise we'll need to temporarily settle for some other convenient
2190 // type. Type legalization will make adjustments once the shiftee is split.
2192 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2199 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2201 if (const OverflowingBinaryOperator *OFBinOp =
2202 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2203 nuw = OFBinOp->hasNoUnsignedWrap();
2204 nsw = OFBinOp->hasNoSignedWrap();
2206 if (const PossiblyExactOperator *ExactOp =
2207 dyn_cast<const PossiblyExactOperator>(&I))
2208 exact = ExactOp->isExact();
2211 Flags.setExact(exact);
2212 Flags.setNoSignedWrap(nsw);
2213 Flags.setNoUnsignedWrap(nuw);
2214 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2219 void SelectionDAGBuilder::visitSDiv(const User &I) {
2220 SDValue Op1 = getValue(I.getOperand(0));
2221 SDValue Op2 = getValue(I.getOperand(1));
2224 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2225 cast<PossiblyExactOperator>(&I)->isExact());
2226 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2230 void SelectionDAGBuilder::visitICmp(const User &I) {
2231 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2232 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2233 predicate = IC->getPredicate();
2234 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2235 predicate = ICmpInst::Predicate(IC->getPredicate());
2236 SDValue Op1 = getValue(I.getOperand(0));
2237 SDValue Op2 = getValue(I.getOperand(1));
2238 ISD::CondCode Opcode = getICmpCondCode(predicate);
2240 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2242 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2245 void SelectionDAGBuilder::visitFCmp(const User &I) {
2246 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2247 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2248 predicate = FC->getPredicate();
2249 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2250 predicate = FCmpInst::Predicate(FC->getPredicate());
2251 SDValue Op1 = getValue(I.getOperand(0));
2252 SDValue Op2 = getValue(I.getOperand(1));
2253 ISD::CondCode Condition = getFCmpCondCode(predicate);
2254 if (TM.Options.NoNaNsFPMath)
2255 Condition = getFCmpCodeWithoutNaN(Condition);
2256 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2258 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2261 void SelectionDAGBuilder::visitSelect(const User &I) {
2262 SmallVector<EVT, 4> ValueVTs;
2263 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2265 unsigned NumValues = ValueVTs.size();
2266 if (NumValues == 0) return;
2268 SmallVector<SDValue, 4> Values(NumValues);
2269 SDValue Cond = getValue(I.getOperand(0));
2270 SDValue LHSVal = getValue(I.getOperand(1));
2271 SDValue RHSVal = getValue(I.getOperand(2));
2272 auto BaseOps = {Cond};
2273 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2274 ISD::VSELECT : ISD::SELECT;
2276 // Min/max matching is only viable if all output VTs are the same.
2277 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2279 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2280 ISD::NodeType Opc = ISD::DELETED_NODE;
2282 case SPF_UMAX: Opc = ISD::UMAX; break;
2283 case SPF_UMIN: Opc = ISD::UMIN; break;
2284 case SPF_SMAX: Opc = ISD::SMAX; break;
2285 case SPF_SMIN: Opc = ISD::SMIN; break;
2289 EVT VT = ValueVTs[0];
2290 LLVMContext &Ctx = *DAG.getContext();
2291 auto &TLI = DAG.getTargetLoweringInfo();
2292 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2293 VT = TLI.getTypeToTransformTo(Ctx, VT);
2295 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2296 // If the underlying comparison instruction is used by any other instruction,
2297 // the consumed instructions won't be destroyed, so it is not profitable
2298 // to convert to a min/max.
2299 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2301 LHSVal = getValue(LHS);
2302 RHSVal = getValue(RHS);
2307 for (unsigned i = 0; i != NumValues; ++i) {
2308 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2309 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2310 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2311 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2312 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2316 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2317 DAG.getVTList(ValueVTs), Values));
2320 void SelectionDAGBuilder::visitTrunc(const User &I) {
2321 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2322 SDValue N = getValue(I.getOperand(0));
2323 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2325 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2328 void SelectionDAGBuilder::visitZExt(const User &I) {
2329 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2330 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2331 SDValue N = getValue(I.getOperand(0));
2332 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2334 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2337 void SelectionDAGBuilder::visitSExt(const User &I) {
2338 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2339 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2340 SDValue N = getValue(I.getOperand(0));
2341 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2343 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2346 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2347 // FPTrunc is never a no-op cast, no need to check
2348 SDValue N = getValue(I.getOperand(0));
2349 SDLoc dl = getCurSDLoc();
2350 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2351 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2352 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2353 DAG.getTargetConstant(
2354 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2357 void SelectionDAGBuilder::visitFPExt(const User &I) {
2358 // FPExt is never a no-op cast, no need to check
2359 SDValue N = getValue(I.getOperand(0));
2360 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2362 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2365 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2366 // FPToUI is never a no-op cast, no need to check
2367 SDValue N = getValue(I.getOperand(0));
2368 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2370 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2373 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2374 // FPToSI is never a no-op cast, no need to check
2375 SDValue N = getValue(I.getOperand(0));
2376 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2378 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2381 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2382 // UIToFP is never a no-op cast, no need to check
2383 SDValue N = getValue(I.getOperand(0));
2384 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2386 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2389 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2390 // SIToFP is never a no-op cast, no need to check
2391 SDValue N = getValue(I.getOperand(0));
2392 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2394 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2397 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2398 // What to do depends on the size of the integer and the size of the pointer.
2399 // We can either truncate, zero extend, or no-op, accordingly.
2400 SDValue N = getValue(I.getOperand(0));
2401 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2403 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2406 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2407 // What to do depends on the size of the integer and the size of the pointer.
2408 // We can either truncate, zero extend, or no-op, accordingly.
2409 SDValue N = getValue(I.getOperand(0));
2410 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2412 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2415 void SelectionDAGBuilder::visitBitCast(const User &I) {
2416 SDValue N = getValue(I.getOperand(0));
2417 SDLoc dl = getCurSDLoc();
2418 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2421 // BitCast assures us that source and destination are the same size so this is
2422 // either a BITCAST or a no-op.
2423 if (DestVT != N.getValueType())
2424 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2425 DestVT, N)); // convert types.
2426 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2427 // might fold any kind of constant expression to an integer constant and that
2428 // is not what we are looking for. Only regcognize a bitcast of a genuine
2429 // constant integer as an opaque constant.
2430 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2431 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2434 setValue(&I, N); // noop cast.
2437 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2439 const Value *SV = I.getOperand(0);
2440 SDValue N = getValue(SV);
2441 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2443 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2444 unsigned DestAS = I.getType()->getPointerAddressSpace();
2446 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2447 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2452 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2454 SDValue InVec = getValue(I.getOperand(0));
2455 SDValue InVal = getValue(I.getOperand(1));
2456 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2457 TLI.getVectorIdxTy(DAG.getDataLayout()));
2458 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2459 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2460 InVec, InVal, InIdx));
2463 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2465 SDValue InVec = getValue(I.getOperand(0));
2466 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2467 TLI.getVectorIdxTy(DAG.getDataLayout()));
2468 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2469 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2473 // Utility for visitShuffleVector - Return true if every element in Mask,
2474 // beginning from position Pos and ending in Pos+Size, falls within the
2475 // specified sequential range [L, L+Pos). or is undef.
2476 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2477 unsigned Pos, unsigned Size, int Low) {
2478 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2479 if (Mask[i] >= 0 && Mask[i] != Low)
2484 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2485 SDValue Src1 = getValue(I.getOperand(0));
2486 SDValue Src2 = getValue(I.getOperand(1));
2488 SmallVector<int, 8> Mask;
2489 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2490 unsigned MaskNumElts = Mask.size();
2492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2493 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2494 EVT SrcVT = Src1.getValueType();
2495 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2497 if (SrcNumElts == MaskNumElts) {
2498 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2503 // Normalize the shuffle vector since mask and vector length don't match.
2504 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2505 // Mask is longer than the source vectors and is a multiple of the source
2506 // vectors. We can use concatenate vector to make the mask and vectors
2508 if (SrcNumElts*2 == MaskNumElts) {
2509 // First check for Src1 in low and Src2 in high
2510 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2511 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2512 // The shuffle is concatenating two vectors together.
2513 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2517 // Then check for Src2 in low and Src1 in high
2518 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2519 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2520 // The shuffle is concatenating two vectors together.
2521 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2527 // Pad both vectors with undefs to make them the same length as the mask.
2528 unsigned NumConcat = MaskNumElts / SrcNumElts;
2529 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2530 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2531 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2533 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2534 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2538 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2539 getCurSDLoc(), VT, MOps1);
2540 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2541 getCurSDLoc(), VT, MOps2);
2543 // Readjust mask for new input vector length.
2544 SmallVector<int, 8> MappedOps;
2545 for (unsigned i = 0; i != MaskNumElts; ++i) {
2547 if (Idx >= (int)SrcNumElts)
2548 Idx -= SrcNumElts - MaskNumElts;
2549 MappedOps.push_back(Idx);
2552 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2557 if (SrcNumElts > MaskNumElts) {
2558 // Analyze the access pattern of the vector to see if we can extract
2559 // two subvectors and do the shuffle. The analysis is done by calculating
2560 // the range of elements the mask access on both vectors.
2561 int MinRange[2] = { static_cast<int>(SrcNumElts),
2562 static_cast<int>(SrcNumElts)};
2563 int MaxRange[2] = {-1, -1};
2565 for (unsigned i = 0; i != MaskNumElts; ++i) {
2571 if (Idx >= (int)SrcNumElts) {
2575 if (Idx > MaxRange[Input])
2576 MaxRange[Input] = Idx;
2577 if (Idx < MinRange[Input])
2578 MinRange[Input] = Idx;
2581 // Check if the access is smaller than the vector size and can we find
2582 // a reasonable extract index.
2583 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2585 int StartIdx[2]; // StartIdx to extract from
2586 for (unsigned Input = 0; Input < 2; ++Input) {
2587 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2588 RangeUse[Input] = 0; // Unused
2589 StartIdx[Input] = 0;
2593 // Find a good start index that is a multiple of the mask length. Then
2594 // see if the rest of the elements are in range.
2595 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2596 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2597 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2598 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2601 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2602 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2605 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2606 // Extract appropriate subvector and generate a vector shuffle
2607 for (unsigned Input = 0; Input < 2; ++Input) {
2608 SDValue &Src = Input == 0 ? Src1 : Src2;
2609 if (RangeUse[Input] == 0)
2610 Src = DAG.getUNDEF(VT);
2612 SDLoc dl = getCurSDLoc();
2614 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2615 DAG.getConstant(StartIdx[Input], dl,
2616 TLI.getVectorIdxTy(DAG.getDataLayout())));
2620 // Calculate new mask.
2621 SmallVector<int, 8> MappedOps;
2622 for (unsigned i = 0; i != MaskNumElts; ++i) {
2625 if (Idx < (int)SrcNumElts)
2628 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2630 MappedOps.push_back(Idx);
2633 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2639 // We can't use either concat vectors or extract subvectors so fall back to
2640 // replacing the shuffle with extract and build vector.
2641 // to insert and build vector.
2642 EVT EltVT = VT.getVectorElementType();
2643 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2644 SDLoc dl = getCurSDLoc();
2645 SmallVector<SDValue,8> Ops;
2646 for (unsigned i = 0; i != MaskNumElts; ++i) {
2651 Res = DAG.getUNDEF(EltVT);
2653 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2654 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2656 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2657 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2663 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2666 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2667 const Value *Op0 = I.getOperand(0);
2668 const Value *Op1 = I.getOperand(1);
2669 Type *AggTy = I.getType();
2670 Type *ValTy = Op1->getType();
2671 bool IntoUndef = isa<UndefValue>(Op0);
2672 bool FromUndef = isa<UndefValue>(Op1);
2674 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2677 SmallVector<EVT, 4> AggValueVTs;
2678 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2679 SmallVector<EVT, 4> ValValueVTs;
2680 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2682 unsigned NumAggValues = AggValueVTs.size();
2683 unsigned NumValValues = ValValueVTs.size();
2684 SmallVector<SDValue, 4> Values(NumAggValues);
2686 // Ignore an insertvalue that produces an empty object
2687 if (!NumAggValues) {
2688 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2692 SDValue Agg = getValue(Op0);
2694 // Copy the beginning value(s) from the original aggregate.
2695 for (; i != LinearIndex; ++i)
2696 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2697 SDValue(Agg.getNode(), Agg.getResNo() + i);
2698 // Copy values from the inserted value(s).
2700 SDValue Val = getValue(Op1);
2701 for (; i != LinearIndex + NumValValues; ++i)
2702 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2703 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2705 // Copy remaining value(s) from the original aggregate.
2706 for (; i != NumAggValues; ++i)
2707 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2708 SDValue(Agg.getNode(), Agg.getResNo() + i);
2710 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2711 DAG.getVTList(AggValueVTs), Values));
2714 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2715 const Value *Op0 = I.getOperand(0);
2716 Type *AggTy = Op0->getType();
2717 Type *ValTy = I.getType();
2718 bool OutOfUndef = isa<UndefValue>(Op0);
2720 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2723 SmallVector<EVT, 4> ValValueVTs;
2724 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2726 unsigned NumValValues = ValValueVTs.size();
2728 // Ignore a extractvalue that produces an empty object
2729 if (!NumValValues) {
2730 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2734 SmallVector<SDValue, 4> Values(NumValValues);
2736 SDValue Agg = getValue(Op0);
2737 // Copy out the selected value(s).
2738 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2739 Values[i - LinearIndex] =
2741 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2742 SDValue(Agg.getNode(), Agg.getResNo() + i);
2744 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2745 DAG.getVTList(ValValueVTs), Values));
2748 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2749 Value *Op0 = I.getOperand(0);
2750 // Note that the pointer operand may be a vector of pointers. Take the scalar
2751 // element which holds a pointer.
2752 Type *Ty = Op0->getType()->getScalarType();
2753 unsigned AS = Ty->getPointerAddressSpace();
2754 SDValue N = getValue(Op0);
2755 SDLoc dl = getCurSDLoc();
2757 // Normalize Vector GEP - all scalar operands should be converted to the
2759 unsigned VectorWidth = I.getType()->isVectorTy() ?
2760 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2762 if (VectorWidth && !N.getValueType().isVector()) {
2763 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2764 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2765 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2767 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2769 const Value *Idx = *OI;
2770 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2771 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2774 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2775 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2776 DAG.getConstant(Offset, dl, N.getValueType()));
2779 Ty = StTy->getElementType(Field);
2781 Ty = cast<SequentialType>(Ty)->getElementType();
2783 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2784 unsigned PtrSize = PtrTy.getSizeInBits();
2785 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2787 // If this is a scalar constant or a splat vector of constants,
2788 // handle it quickly.
2789 const auto *CI = dyn_cast<ConstantInt>(Idx);
2790 if (!CI && isa<ConstantDataVector>(Idx) &&
2791 cast<ConstantDataVector>(Idx)->getSplatValue())
2792 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2797 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2798 SDValue OffsVal = VectorWidth ?
2799 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2800 DAG.getConstant(Offs, dl, PtrTy);
2801 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2805 // N = N + Idx * ElementSize;
2806 SDValue IdxN = getValue(Idx);
2808 if (!IdxN.getValueType().isVector() && VectorWidth) {
2809 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2810 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2811 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2813 // If the index is smaller or larger than intptr_t, truncate or extend
2815 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2817 // If this is a multiply by a power of two, turn it into a shl
2818 // immediately. This is a very common case.
2819 if (ElementSize != 1) {
2820 if (ElementSize.isPowerOf2()) {
2821 unsigned Amt = ElementSize.logBase2();
2822 IdxN = DAG.getNode(ISD::SHL, dl,
2823 N.getValueType(), IdxN,
2824 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2826 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2827 IdxN = DAG.getNode(ISD::MUL, dl,
2828 N.getValueType(), IdxN, Scale);
2832 N = DAG.getNode(ISD::ADD, dl,
2833 N.getValueType(), N, IdxN);
2840 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2841 // If this is a fixed sized alloca in the entry block of the function,
2842 // allocate it statically on the stack.
2843 if (FuncInfo.StaticAllocaMap.count(&I))
2844 return; // getValue will auto-populate this.
2846 SDLoc dl = getCurSDLoc();
2847 Type *Ty = I.getAllocatedType();
2848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2849 auto &DL = DAG.getDataLayout();
2850 uint64_t TySize = DL.getTypeAllocSize(Ty);
2852 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2854 SDValue AllocSize = getValue(I.getArraySize());
2856 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2857 if (AllocSize.getValueType() != IntPtr)
2858 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2860 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2862 DAG.getConstant(TySize, dl, IntPtr));
2864 // Handle alignment. If the requested alignment is less than or equal to
2865 // the stack alignment, ignore it. If the size is greater than or equal to
2866 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2867 unsigned StackAlign =
2868 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2869 if (Align <= StackAlign)
2872 // Round the size of the allocation up to the stack alignment size
2873 // by add SA-1 to the size.
2874 AllocSize = DAG.getNode(ISD::ADD, dl,
2875 AllocSize.getValueType(), AllocSize,
2876 DAG.getIntPtrConstant(StackAlign - 1, dl));
2878 // Mask out the low bits for alignment purposes.
2879 AllocSize = DAG.getNode(ISD::AND, dl,
2880 AllocSize.getValueType(), AllocSize,
2881 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2884 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2885 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2886 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2888 DAG.setRoot(DSA.getValue(1));
2890 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2893 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2895 return visitAtomicLoad(I);
2897 const Value *SV = I.getOperand(0);
2898 SDValue Ptr = getValue(SV);
2900 Type *Ty = I.getType();
2902 bool isVolatile = I.isVolatile();
2903 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2905 // The IR notion of invariant_load only guarantees that all *non-faulting*
2906 // invariant loads result in the same value. The MI notion of invariant load
2907 // guarantees that the load can be legally moved to any location within its
2908 // containing function. The MI notion of invariant_load is stronger than the
2909 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2910 // with a guarantee that the location being loaded from is dereferenceable
2911 // throughout the function's lifetime.
2913 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2914 isDereferenceablePointer(SV, *DAG.getTarget().getDataLayout());
2915 unsigned Alignment = I.getAlignment();
2918 I.getAAMetadata(AAInfo);
2919 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2921 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2922 SmallVector<EVT, 4> ValueVTs;
2923 SmallVector<uint64_t, 4> Offsets;
2924 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2925 unsigned NumValues = ValueVTs.size();
2930 bool ConstantMemory = false;
2931 if (isVolatile || NumValues > MaxParallelChains)
2932 // Serialize volatile loads with other side effects.
2934 else if (AA->pointsToConstantMemory(
2935 MemoryLocation(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2936 // Do not serialize (non-volatile) loads of constant memory with anything.
2937 Root = DAG.getEntryNode();
2938 ConstantMemory = true;
2940 // Do not serialize non-volatile loads against each other.
2941 Root = DAG.getRoot();
2944 SDLoc dl = getCurSDLoc();
2947 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2949 SmallVector<SDValue, 4> Values(NumValues);
2950 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
2951 EVT PtrVT = Ptr.getValueType();
2952 unsigned ChainI = 0;
2953 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2954 // Serializing loads here may result in excessive register pressure, and
2955 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2956 // could recover a bit by hoisting nodes upward in the chain by recognizing
2957 // they are side-effect free or do not alias. The optimizer should really
2958 // avoid this case by converting large object/array copies to llvm.memcpy
2959 // (MaxParallelChains should always remain as failsafe).
2960 if (ChainI == MaxParallelChains) {
2961 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2962 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2963 makeArrayRef(Chains.data(), ChainI));
2967 SDValue A = DAG.getNode(ISD::ADD, dl,
2969 DAG.getConstant(Offsets[i], dl, PtrVT));
2970 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2971 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2972 isNonTemporal, isInvariant, Alignment, AAInfo,
2976 Chains[ChainI] = L.getValue(1);
2979 if (!ConstantMemory) {
2980 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2981 makeArrayRef(Chains.data(), ChainI));
2985 PendingLoads.push_back(Chain);
2988 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2989 DAG.getVTList(ValueVTs), Values));
2992 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2994 return visitAtomicStore(I);
2996 const Value *SrcV = I.getOperand(0);
2997 const Value *PtrV = I.getOperand(1);
2999 SmallVector<EVT, 4> ValueVTs;
3000 SmallVector<uint64_t, 4> Offsets;
3001 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3002 SrcV->getType(), ValueVTs, &Offsets);
3003 unsigned NumValues = ValueVTs.size();
3007 // Get the lowered operands. Note that we do this after
3008 // checking if NumResults is zero, because with zero results
3009 // the operands won't have values in the map.
3010 SDValue Src = getValue(SrcV);
3011 SDValue Ptr = getValue(PtrV);
3013 SDValue Root = getRoot();
3014 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3015 EVT PtrVT = Ptr.getValueType();
3016 bool isVolatile = I.isVolatile();
3017 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3018 unsigned Alignment = I.getAlignment();
3019 SDLoc dl = getCurSDLoc();
3022 I.getAAMetadata(AAInfo);
3024 unsigned ChainI = 0;
3025 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3026 // See visitLoad comments.
3027 if (ChainI == MaxParallelChains) {
3028 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3029 makeArrayRef(Chains.data(), ChainI));
3033 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3034 DAG.getConstant(Offsets[i], dl, PtrVT));
3035 SDValue St = DAG.getStore(Root, dl,
3036 SDValue(Src.getNode(), Src.getResNo() + i),
3037 Add, MachinePointerInfo(PtrV, Offsets[i]),
3038 isVolatile, isNonTemporal, Alignment, AAInfo);
3039 Chains[ChainI] = St;
3042 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3043 makeArrayRef(Chains.data(), ChainI));
3044 DAG.setRoot(StoreNode);
3047 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3048 SDLoc sdl = getCurSDLoc();
3050 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3051 Value *PtrOperand = I.getArgOperand(1);
3052 SDValue Ptr = getValue(PtrOperand);
3053 SDValue Src0 = getValue(I.getArgOperand(0));
3054 SDValue Mask = getValue(I.getArgOperand(3));
3055 EVT VT = Src0.getValueType();
3056 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3058 Alignment = DAG.getEVTAlignment(VT);
3061 I.getAAMetadata(AAInfo);
3063 MachineMemOperand *MMO =
3064 DAG.getMachineFunction().
3065 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3066 MachineMemOperand::MOStore, VT.getStoreSize(),
3068 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3070 DAG.setRoot(StoreNode);
3071 setValue(&I, StoreNode);
3074 // Gather/scatter receive a vector of pointers.
3075 // This vector of pointers may be represented as a base pointer + vector of
3076 // indices, it depends on GEP and instruction preceeding GEP
3077 // that calculates indices
3078 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3079 SelectionDAGBuilder* SDB) {
3081 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3082 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3083 if (!Gep || Gep->getNumOperands() > 2)
3085 ShuffleVectorInst *ShuffleInst =
3086 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3087 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3088 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3089 Instruction::InsertElement)
3092 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3094 SelectionDAG& DAG = SDB->DAG;
3095 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3096 // Check is the Ptr is inside current basic block
3097 // If not, look for the shuffle instruction
3098 if (SDB->findValue(Ptr))
3099 Base = SDB->getValue(Ptr);
3100 else if (SDB->findValue(ShuffleInst)) {
3101 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3102 SDLoc sdl = ShuffleNode;
3104 ISD::EXTRACT_VECTOR_ELT, sdl,
3105 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3106 DAG.getConstant(0, sdl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3107 SDB->setValue(Ptr, Base);
3112 Value *IndexVal = Gep->getOperand(1);
3113 if (SDB->findValue(IndexVal)) {
3114 Index = SDB->getValue(IndexVal);
3116 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3117 IndexVal = Sext->getOperand(0);
3118 if (SDB->findValue(IndexVal))
3119 Index = SDB->getValue(IndexVal);
3126 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3127 SDLoc sdl = getCurSDLoc();
3129 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3130 Value *Ptr = I.getArgOperand(1);
3131 SDValue Src0 = getValue(I.getArgOperand(0));
3132 SDValue Mask = getValue(I.getArgOperand(3));
3133 EVT VT = Src0.getValueType();
3134 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3136 Alignment = DAG.getEVTAlignment(VT);
3137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3140 I.getAAMetadata(AAInfo);
3144 Value *BasePtr = Ptr;
3145 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3147 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3148 MachineMemOperand *MMO = DAG.getMachineFunction().
3149 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3150 MachineMemOperand::MOStore, VT.getStoreSize(),
3153 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3154 Index = getValue(Ptr);
3156 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3157 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3159 DAG.setRoot(Scatter);
3160 setValue(&I, Scatter);
3163 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3164 SDLoc sdl = getCurSDLoc();
3166 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3167 Value *PtrOperand = I.getArgOperand(0);
3168 SDValue Ptr = getValue(PtrOperand);
3169 SDValue Src0 = getValue(I.getArgOperand(3));
3170 SDValue Mask = getValue(I.getArgOperand(2));
3172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3173 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3174 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3176 Alignment = DAG.getEVTAlignment(VT);
3179 I.getAAMetadata(AAInfo);
3180 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3182 SDValue InChain = DAG.getRoot();
3183 if (AA->pointsToConstantMemory(MemoryLocation(
3184 PtrOperand, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3185 // Do not serialize (non-volatile) loads of constant memory with anything.
3186 InChain = DAG.getEntryNode();
3189 MachineMemOperand *MMO =
3190 DAG.getMachineFunction().
3191 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3192 MachineMemOperand::MOLoad, VT.getStoreSize(),
3193 Alignment, AAInfo, Ranges);
3195 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3197 SDValue OutChain = Load.getValue(1);
3198 DAG.setRoot(OutChain);
3202 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3203 SDLoc sdl = getCurSDLoc();
3205 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3206 Value *Ptr = I.getArgOperand(0);
3207 SDValue Src0 = getValue(I.getArgOperand(3));
3208 SDValue Mask = getValue(I.getArgOperand(2));
3210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3211 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3212 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3214 Alignment = DAG.getEVTAlignment(VT);
3217 I.getAAMetadata(AAInfo);
3218 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3220 SDValue Root = DAG.getRoot();
3223 Value *BasePtr = Ptr;
3224 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3225 bool ConstantMemory = false;
3227 AA->pointsToConstantMemory(
3228 MemoryLocation(BasePtr, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3229 // Do not serialize (non-volatile) loads of constant memory with anything.
3230 Root = DAG.getEntryNode();
3231 ConstantMemory = true;
3234 MachineMemOperand *MMO =
3235 DAG.getMachineFunction().
3236 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3237 MachineMemOperand::MOLoad, VT.getStoreSize(),
3238 Alignment, AAInfo, Ranges);
3241 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3242 Index = getValue(Ptr);
3244 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3245 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3248 SDValue OutChain = Gather.getValue(1);
3249 if (!ConstantMemory)
3250 PendingLoads.push_back(OutChain);
3251 setValue(&I, Gather);
3254 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3255 SDLoc dl = getCurSDLoc();
3256 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3257 AtomicOrdering FailureOrder = I.getFailureOrdering();
3258 SynchronizationScope Scope = I.getSynchScope();
3260 SDValue InChain = getRoot();
3262 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3263 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3264 SDValue L = DAG.getAtomicCmpSwap(
3265 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3266 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3267 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3268 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3270 SDValue OutChain = L.getValue(2);
3273 DAG.setRoot(OutChain);
3276 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3277 SDLoc dl = getCurSDLoc();
3279 switch (I.getOperation()) {
3280 default: llvm_unreachable("Unknown atomicrmw operation");
3281 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3282 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3283 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3284 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3285 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3286 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3287 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3288 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3289 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3290 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3291 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3293 AtomicOrdering Order = I.getOrdering();
3294 SynchronizationScope Scope = I.getSynchScope();
3296 SDValue InChain = getRoot();
3299 DAG.getAtomic(NT, dl,
3300 getValue(I.getValOperand()).getSimpleValueType(),
3302 getValue(I.getPointerOperand()),
3303 getValue(I.getValOperand()),
3304 I.getPointerOperand(),
3305 /* Alignment=*/ 0, Order, Scope);
3307 SDValue OutChain = L.getValue(1);
3310 DAG.setRoot(OutChain);
3313 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3314 SDLoc dl = getCurSDLoc();
3315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3318 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3319 TLI.getPointerTy(DAG.getDataLayout()));
3320 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3321 TLI.getPointerTy(DAG.getDataLayout()));
3322 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3325 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3326 SDLoc dl = getCurSDLoc();
3327 AtomicOrdering Order = I.getOrdering();
3328 SynchronizationScope Scope = I.getSynchScope();
3330 SDValue InChain = getRoot();
3332 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3333 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3335 if (I.getAlignment() < VT.getSizeInBits() / 8)
3336 report_fatal_error("Cannot generate unaligned atomic load");
3338 MachineMemOperand *MMO =
3339 DAG.getMachineFunction().
3340 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3341 MachineMemOperand::MOVolatile |
3342 MachineMemOperand::MOLoad,
3344 I.getAlignment() ? I.getAlignment() :
3345 DAG.getEVTAlignment(VT));
3347 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3349 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3350 getValue(I.getPointerOperand()), MMO,
3353 SDValue OutChain = L.getValue(1);
3356 DAG.setRoot(OutChain);
3359 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3360 SDLoc dl = getCurSDLoc();
3362 AtomicOrdering Order = I.getOrdering();
3363 SynchronizationScope Scope = I.getSynchScope();
3365 SDValue InChain = getRoot();
3367 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3369 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3371 if (I.getAlignment() < VT.getSizeInBits() / 8)
3372 report_fatal_error("Cannot generate unaligned atomic store");
3375 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3377 getValue(I.getPointerOperand()),
3378 getValue(I.getValueOperand()),
3379 I.getPointerOperand(), I.getAlignment(),
3382 DAG.setRoot(OutChain);
3385 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3387 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3388 unsigned Intrinsic) {
3389 bool HasChain = !I.doesNotAccessMemory();
3390 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3392 // Build the operand list.
3393 SmallVector<SDValue, 8> Ops;
3394 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3396 // We don't need to serialize loads against other loads.
3397 Ops.push_back(DAG.getRoot());
3399 Ops.push_back(getRoot());
3403 // Info is set by getTgtMemInstrinsic
3404 TargetLowering::IntrinsicInfo Info;
3405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3406 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3408 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3409 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3410 Info.opc == ISD::INTRINSIC_W_CHAIN)
3411 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3412 TLI.getPointerTy(DAG.getDataLayout())));
3414 // Add all operands of the call to the operand list.
3415 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3416 SDValue Op = getValue(I.getArgOperand(i));
3420 SmallVector<EVT, 4> ValueVTs;
3421 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3424 ValueVTs.push_back(MVT::Other);
3426 SDVTList VTs = DAG.getVTList(ValueVTs);
3430 if (IsTgtIntrinsic) {
3431 // This is target intrinsic that touches memory
3432 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3433 VTs, Ops, Info.memVT,
3434 MachinePointerInfo(Info.ptrVal, Info.offset),
3435 Info.align, Info.vol,
3436 Info.readMem, Info.writeMem, Info.size);
3437 } else if (!HasChain) {
3438 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3439 } else if (!I.getType()->isVoidTy()) {
3440 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3442 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3446 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3448 PendingLoads.push_back(Chain);
3453 if (!I.getType()->isVoidTy()) {
3454 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3455 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3456 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3459 setValue(&I, Result);
3463 /// GetSignificand - Get the significand and build it into a floating-point
3464 /// number with exponent of 1:
3466 /// Op = (Op & 0x007fffff) | 0x3f800000;
3468 /// where Op is the hexadecimal representation of floating point value.
3470 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3471 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3472 DAG.getConstant(0x007fffff, dl, MVT::i32));
3473 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3474 DAG.getConstant(0x3f800000, dl, MVT::i32));
3475 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3478 /// GetExponent - Get the exponent:
3480 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3482 /// where Op is the hexadecimal representation of floating point value.
3484 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3486 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3487 DAG.getConstant(0x7f800000, dl, MVT::i32));
3488 SDValue t1 = DAG.getNode(
3489 ISD::SRL, dl, MVT::i32, t0,
3490 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3491 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3492 DAG.getConstant(127, dl, MVT::i32));
3493 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3496 /// getF32Constant - Get 32-bit floating point constant.
3498 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3499 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3503 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3504 SelectionDAG &DAG) {
3505 // IntegerPartOfX = ((int32_t)(t0);
3506 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3508 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3509 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3510 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3512 // IntegerPartOfX <<= 23;
3513 IntegerPartOfX = DAG.getNode(
3514 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3515 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3516 DAG.getDataLayout())));
3518 SDValue TwoToFractionalPartOfX;
3519 if (LimitFloatPrecision <= 6) {
3520 // For floating-point precision of 6:
3522 // TwoToFractionalPartOfX =
3524 // (0.735607626f + 0.252464424f * x) * x;
3526 // error 0.0144103317, which is 6 bits
3527 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3528 getF32Constant(DAG, 0x3e814304, dl));
3529 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3530 getF32Constant(DAG, 0x3f3c50c8, dl));
3531 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3532 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3533 getF32Constant(DAG, 0x3f7f5e7e, dl));
3534 } else if (LimitFloatPrecision <= 12) {
3535 // For floating-point precision of 12:
3537 // TwoToFractionalPartOfX =
3540 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3542 // error 0.000107046256, which is 13 to 14 bits
3543 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3544 getF32Constant(DAG, 0x3da235e3, dl));
3545 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3546 getF32Constant(DAG, 0x3e65b8f3, dl));
3547 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3548 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3549 getF32Constant(DAG, 0x3f324b07, dl));
3550 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3551 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3552 getF32Constant(DAG, 0x3f7ff8fd, dl));
3553 } else { // LimitFloatPrecision <= 18
3554 // For floating-point precision of 18:
3556 // TwoToFractionalPartOfX =
3560 // (0.554906021e-1f +
3561 // (0.961591928e-2f +
3562 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3563 // error 2.47208000*10^(-7), which is better than 18 bits
3564 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3565 getF32Constant(DAG, 0x3924b03e, dl));
3566 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3567 getF32Constant(DAG, 0x3ab24b87, dl));
3568 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3569 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3570 getF32Constant(DAG, 0x3c1d8c17, dl));
3571 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3572 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3573 getF32Constant(DAG, 0x3d634a1d, dl));
3574 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3575 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3576 getF32Constant(DAG, 0x3e75fe14, dl));
3577 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3578 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3579 getF32Constant(DAG, 0x3f317234, dl));
3580 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3581 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3582 getF32Constant(DAG, 0x3f800000, dl));
3585 // Add the exponent into the result in integer domain.
3586 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3587 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3588 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3591 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3592 /// limited-precision mode.
3593 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3594 const TargetLowering &TLI) {
3595 if (Op.getValueType() == MVT::f32 &&
3596 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3598 // Put the exponent in the right bit position for later addition to the
3601 // #define LOG2OFe 1.4426950f
3602 // t0 = Op * LOG2OFe
3603 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3604 getF32Constant(DAG, 0x3fb8aa3b, dl));
3605 return getLimitedPrecisionExp2(t0, dl, DAG);
3608 // No special expansion.
3609 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3612 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3613 /// limited-precision mode.
3614 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3615 const TargetLowering &TLI) {
3616 if (Op.getValueType() == MVT::f32 &&
3617 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3618 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3620 // Scale the exponent by log(2) [0.69314718f].
3621 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3622 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3623 getF32Constant(DAG, 0x3f317218, dl));
3625 // Get the significand and build it into a floating-point number with
3627 SDValue X = GetSignificand(DAG, Op1, dl);
3629 SDValue LogOfMantissa;
3630 if (LimitFloatPrecision <= 6) {
3631 // For floating-point precision of 6:
3635 // (1.4034025f - 0.23903021f * x) * x;
3637 // error 0.0034276066, which is better than 8 bits
3638 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3639 getF32Constant(DAG, 0xbe74c456, dl));
3640 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3641 getF32Constant(DAG, 0x3fb3a2b1, dl));
3642 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3643 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3644 getF32Constant(DAG, 0x3f949a29, dl));
3645 } else if (LimitFloatPrecision <= 12) {
3646 // For floating-point precision of 12:
3652 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3654 // error 0.000061011436, which is 14 bits
3655 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3656 getF32Constant(DAG, 0xbd67b6d6, dl));
3657 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3658 getF32Constant(DAG, 0x3ee4f4b8, dl));
3659 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3660 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3661 getF32Constant(DAG, 0x3fbc278b, dl));
3662 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3663 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3664 getF32Constant(DAG, 0x40348e95, dl));
3665 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3666 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3667 getF32Constant(DAG, 0x3fdef31a, dl));
3668 } else { // LimitFloatPrecision <= 18
3669 // For floating-point precision of 18:
3677 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3679 // error 0.0000023660568, which is better than 18 bits
3680 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3681 getF32Constant(DAG, 0xbc91e5ac, dl));
3682 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3683 getF32Constant(DAG, 0x3e4350aa, dl));
3684 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3685 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3686 getF32Constant(DAG, 0x3f60d3e3, dl));
3687 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3688 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3689 getF32Constant(DAG, 0x4011cdf0, dl));
3690 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3691 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3692 getF32Constant(DAG, 0x406cfd1c, dl));
3693 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3694 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3695 getF32Constant(DAG, 0x408797cb, dl));
3696 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3697 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3698 getF32Constant(DAG, 0x4006dcab, dl));
3701 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3704 // No special expansion.
3705 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3708 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3709 /// limited-precision mode.
3710 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3711 const TargetLowering &TLI) {
3712 if (Op.getValueType() == MVT::f32 &&
3713 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3714 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3716 // Get the exponent.
3717 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3719 // Get the significand and build it into a floating-point number with
3721 SDValue X = GetSignificand(DAG, Op1, dl);
3723 // Different possible minimax approximations of significand in
3724 // floating-point for various degrees of accuracy over [1,2].
3725 SDValue Log2ofMantissa;
3726 if (LimitFloatPrecision <= 6) {
3727 // For floating-point precision of 6:
3729 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3731 // error 0.0049451742, which is more than 7 bits
3732 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3733 getF32Constant(DAG, 0xbeb08fe0, dl));
3734 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3735 getF32Constant(DAG, 0x40019463, dl));
3736 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3737 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3738 getF32Constant(DAG, 0x3fd6633d, dl));
3739 } else if (LimitFloatPrecision <= 12) {
3740 // For floating-point precision of 12:
3746 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3748 // error 0.0000876136000, which is better than 13 bits
3749 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3750 getF32Constant(DAG, 0xbda7262e, dl));
3751 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3752 getF32Constant(DAG, 0x3f25280b, dl));
3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3754 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x4007b923, dl));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x40823e2f, dl));
3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3760 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3761 getF32Constant(DAG, 0x4020d29c, dl));
3762 } else { // LimitFloatPrecision <= 18
3763 // For floating-point precision of 18:
3772 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3774 // error 0.0000018516, which is better than 18 bits
3775 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3776 getF32Constant(DAG, 0xbcd2769e, dl));
3777 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3778 getF32Constant(DAG, 0x3e8ce0b9, dl));
3779 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3780 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3781 getF32Constant(DAG, 0x3fa22ae7, dl));
3782 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3783 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3784 getF32Constant(DAG, 0x40525723, dl));
3785 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3786 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3787 getF32Constant(DAG, 0x40aaf200, dl));
3788 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3789 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3790 getF32Constant(DAG, 0x40c39dad, dl));
3791 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3792 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3793 getF32Constant(DAG, 0x4042902c, dl));
3796 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3799 // No special expansion.
3800 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3803 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3804 /// limited-precision mode.
3805 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3806 const TargetLowering &TLI) {
3807 if (Op.getValueType() == MVT::f32 &&
3808 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3809 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3811 // Scale the exponent by log10(2) [0.30102999f].
3812 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3813 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3814 getF32Constant(DAG, 0x3e9a209a, dl));
3816 // Get the significand and build it into a floating-point number with
3818 SDValue X = GetSignificand(DAG, Op1, dl);
3820 SDValue Log10ofMantissa;
3821 if (LimitFloatPrecision <= 6) {
3822 // For floating-point precision of 6:
3824 // Log10ofMantissa =
3826 // (0.60948995f - 0.10380950f * x) * x;
3828 // error 0.0014886165, which is 6 bits
3829 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3830 getF32Constant(DAG, 0xbdd49a13, dl));
3831 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3832 getF32Constant(DAG, 0x3f1c0789, dl));
3833 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3834 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3835 getF32Constant(DAG, 0x3f011300, dl));
3836 } else if (LimitFloatPrecision <= 12) {
3837 // For floating-point precision of 12:
3839 // Log10ofMantissa =
3842 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3844 // error 0.00019228036, which is better than 12 bits
3845 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3846 getF32Constant(DAG, 0x3d431f31, dl));
3847 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3848 getF32Constant(DAG, 0x3ea21fb2, dl));
3849 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3850 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3851 getF32Constant(DAG, 0x3f6ae232, dl));
3852 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3853 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3854 getF32Constant(DAG, 0x3f25f7c3, dl));
3855 } else { // LimitFloatPrecision <= 18
3856 // For floating-point precision of 18:
3858 // Log10ofMantissa =
3863 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3865 // error 0.0000037995730, which is better than 18 bits
3866 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3867 getF32Constant(DAG, 0x3c5d51ce, dl));
3868 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3869 getF32Constant(DAG, 0x3e00685a, dl));
3870 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3871 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3872 getF32Constant(DAG, 0x3efb6798, dl));
3873 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3874 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3875 getF32Constant(DAG, 0x3f88d192, dl));
3876 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3877 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3878 getF32Constant(DAG, 0x3fc4316c, dl));
3879 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3880 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3881 getF32Constant(DAG, 0x3f57ce70, dl));
3884 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3887 // No special expansion.
3888 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3891 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3892 /// limited-precision mode.
3893 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3894 const TargetLowering &TLI) {
3895 if (Op.getValueType() == MVT::f32 &&
3896 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3897 return getLimitedPrecisionExp2(Op, dl, DAG);
3899 // No special expansion.
3900 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3903 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3904 /// limited-precision mode with x == 10.0f.
3905 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3906 SelectionDAG &DAG, const TargetLowering &TLI) {
3907 bool IsExp10 = false;
3908 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3909 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3910 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3912 IsExp10 = LHSC->isExactlyValue(Ten);
3917 // Put the exponent in the right bit position for later addition to the
3920 // #define LOG2OF10 3.3219281f
3921 // t0 = Op * LOG2OF10;
3922 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3923 getF32Constant(DAG, 0x40549a78, dl));
3924 return getLimitedPrecisionExp2(t0, dl, DAG);
3927 // No special expansion.
3928 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3932 /// ExpandPowI - Expand a llvm.powi intrinsic.
3933 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3934 SelectionDAG &DAG) {
3935 // If RHS is a constant, we can expand this out to a multiplication tree,
3936 // otherwise we end up lowering to a call to __powidf2 (for example). When
3937 // optimizing for size, we only want to do this if the expansion would produce
3938 // a small number of multiplies, otherwise we do the full expansion.
3939 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3940 // Get the exponent as a positive value.
3941 unsigned Val = RHSC->getSExtValue();
3942 if ((int)Val < 0) Val = -Val;
3944 // powi(x, 0) -> 1.0
3946 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3948 const Function *F = DAG.getMachineFunction().getFunction();
3949 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3950 // If optimizing for size, don't insert too many multiplies. This
3951 // inserts up to 5 multiplies.
3952 countPopulation(Val) + Log2_32(Val) < 7) {
3953 // We use the simple binary decomposition method to generate the multiply
3954 // sequence. There are more optimal ways to do this (for example,
3955 // powi(x,15) generates one more multiply than it should), but this has
3956 // the benefit of being both really simple and much better than a libcall.
3957 SDValue Res; // Logically starts equal to 1.0
3958 SDValue CurSquare = LHS;
3962 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3964 Res = CurSquare; // 1.0*CurSquare.
3967 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3968 CurSquare, CurSquare);
3972 // If the original was negative, invert the result, producing 1/(x*x*x).
3973 if (RHSC->getSExtValue() < 0)
3974 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3975 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3980 // Otherwise, expand to a libcall.
3981 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3984 // getTruncatedArgReg - Find underlying register used for an truncated
3986 static unsigned getTruncatedArgReg(const SDValue &N) {
3987 if (N.getOpcode() != ISD::TRUNCATE)
3990 const SDValue &Ext = N.getOperand(0);
3991 if (Ext.getOpcode() == ISD::AssertZext ||
3992 Ext.getOpcode() == ISD::AssertSext) {
3993 const SDValue &CFR = Ext.getOperand(0);
3994 if (CFR.getOpcode() == ISD::CopyFromReg)
3995 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3996 if (CFR.getOpcode() == ISD::TRUNCATE)
3997 return getTruncatedArgReg(CFR);
4002 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4003 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4004 /// At the end of instruction selection, they will be inserted to the entry BB.
4005 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4006 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4007 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4008 const Argument *Arg = dyn_cast<Argument>(V);
4012 MachineFunction &MF = DAG.getMachineFunction();
4013 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4015 // Ignore inlined function arguments here.
4017 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4018 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4021 Optional<MachineOperand> Op;
4022 // Some arguments' frame index is recorded during argument lowering.
4023 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4024 Op = MachineOperand::CreateFI(FI);
4026 if (!Op && N.getNode()) {
4028 if (N.getOpcode() == ISD::CopyFromReg)
4029 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4031 Reg = getTruncatedArgReg(N);
4032 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4033 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4034 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4039 Op = MachineOperand::CreateReg(Reg, false);
4043 // Check if ValueMap has reg number.
4044 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4045 if (VMI != FuncInfo.ValueMap.end())
4046 Op = MachineOperand::CreateReg(VMI->second, false);
4049 if (!Op && N.getNode())
4050 // Check if frame index is available.
4051 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4052 if (FrameIndexSDNode *FINode =
4053 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4054 Op = MachineOperand::CreateFI(FINode->getIndex());
4059 assert(Variable->isValidLocationForIntrinsic(DL) &&
4060 "Expected inlined-at fields to agree");
4062 FuncInfo.ArgDbgValues.push_back(
4063 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4064 Op->getReg(), Offset, Variable, Expr));
4066 FuncInfo.ArgDbgValues.push_back(
4067 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4070 .addMetadata(Variable)
4071 .addMetadata(Expr));
4076 // VisualStudio defines setjmp as _setjmp
4077 #if defined(_MSC_VER) && defined(setjmp) && \
4078 !defined(setjmp_undefined_for_msvc)
4079 # pragma push_macro("setjmp")
4081 # define setjmp_undefined_for_msvc
4084 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4085 /// we want to emit this as a call to a named external function, return the name
4086 /// otherwise lower it and return null.
4088 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4090 SDLoc sdl = getCurSDLoc();
4091 DebugLoc dl = getCurDebugLoc();
4094 switch (Intrinsic) {
4096 // By default, turn this into a target intrinsic node.
4097 visitTargetIntrinsic(I, Intrinsic);
4099 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4100 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4101 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4102 case Intrinsic::returnaddress:
4103 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4104 TLI.getPointerTy(DAG.getDataLayout()),
4105 getValue(I.getArgOperand(0))));
4107 case Intrinsic::frameaddress:
4108 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4109 TLI.getPointerTy(DAG.getDataLayout()),
4110 getValue(I.getArgOperand(0))));
4112 case Intrinsic::read_register: {
4113 Value *Reg = I.getArgOperand(0);
4114 SDValue Chain = getRoot();
4116 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4117 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4118 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4119 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4121 DAG.setRoot(Res.getValue(1));
4124 case Intrinsic::write_register: {
4125 Value *Reg = I.getArgOperand(0);
4126 Value *RegValue = I.getArgOperand(1);
4127 SDValue Chain = getRoot();
4129 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4130 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4131 RegName, getValue(RegValue)));
4134 case Intrinsic::setjmp:
4135 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4136 case Intrinsic::longjmp:
4137 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4138 case Intrinsic::memcpy: {
4139 // FIXME: this definition of "user defined address space" is x86-specific
4140 // Assert for address < 256 since we support only user defined address
4142 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4144 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4146 "Unknown address space");
4147 SDValue Op1 = getValue(I.getArgOperand(0));
4148 SDValue Op2 = getValue(I.getArgOperand(1));
4149 SDValue Op3 = getValue(I.getArgOperand(2));
4150 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4152 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4153 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4154 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4155 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4157 MachinePointerInfo(I.getArgOperand(0)),
4158 MachinePointerInfo(I.getArgOperand(1)));
4159 updateDAGForMaybeTailCall(MC);
4162 case Intrinsic::memset: {
4163 // FIXME: this definition of "user defined address space" is x86-specific
4164 // Assert for address < 256 since we support only user defined address
4166 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4168 "Unknown address space");
4169 SDValue Op1 = getValue(I.getArgOperand(0));
4170 SDValue Op2 = getValue(I.getArgOperand(1));
4171 SDValue Op3 = getValue(I.getArgOperand(2));
4172 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4174 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4175 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4176 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4177 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4178 isTC, MachinePointerInfo(I.getArgOperand(0)));
4179 updateDAGForMaybeTailCall(MS);
4182 case Intrinsic::memmove: {
4183 // FIXME: this definition of "user defined address space" is x86-specific
4184 // Assert for address < 256 since we support only user defined address
4186 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4188 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4190 "Unknown address space");
4191 SDValue Op1 = getValue(I.getArgOperand(0));
4192 SDValue Op2 = getValue(I.getArgOperand(1));
4193 SDValue Op3 = getValue(I.getArgOperand(2));
4194 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4196 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4197 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4198 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4199 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4200 isTC, MachinePointerInfo(I.getArgOperand(0)),
4201 MachinePointerInfo(I.getArgOperand(1)));
4202 updateDAGForMaybeTailCall(MM);
4205 case Intrinsic::dbg_declare: {
4206 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4207 DILocalVariable *Variable = DI.getVariable();
4208 DIExpression *Expression = DI.getExpression();
4209 const Value *Address = DI.getAddress();
4210 assert(Variable && "Missing variable");
4212 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4216 // Check if address has undef value.
4217 if (isa<UndefValue>(Address) ||
4218 (Address->use_empty() && !isa<Argument>(Address))) {
4219 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4223 SDValue &N = NodeMap[Address];
4224 if (!N.getNode() && isa<Argument>(Address))
4225 // Check unused arguments map.
4226 N = UnusedArgNodeMap[Address];
4229 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4230 Address = BCI->getOperand(0);
4231 // Parameters are handled specially.
4232 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4233 isa<Argument>(Address);
4235 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4237 if (isParameter && !AI) {
4238 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4240 // Byval parameter. We have a frame index at this point.
4241 SDV = DAG.getFrameIndexDbgValue(
4242 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4244 // Address is an argument, so try to emit its dbg value using
4245 // virtual register info from the FuncInfo.ValueMap.
4246 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4251 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4252 true, 0, dl, SDNodeOrder);
4254 // Can't do anything with other non-AI cases yet.
4255 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4256 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4257 DEBUG(Address->dump());
4260 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4262 // If Address is an argument then try to emit its dbg value using
4263 // virtual register info from the FuncInfo.ValueMap.
4264 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4266 // If variable is pinned by a alloca in dominating bb then
4267 // use StaticAllocaMap.
4268 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4269 if (AI->getParent() != DI.getParent()) {
4270 DenseMap<const AllocaInst*, int>::iterator SI =
4271 FuncInfo.StaticAllocaMap.find(AI);
4272 if (SI != FuncInfo.StaticAllocaMap.end()) {
4273 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4274 0, dl, SDNodeOrder);
4275 DAG.AddDbgValue(SDV, nullptr, false);
4280 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4285 case Intrinsic::dbg_value: {
4286 const DbgValueInst &DI = cast<DbgValueInst>(I);
4287 assert(DI.getVariable() && "Missing variable");
4289 DILocalVariable *Variable = DI.getVariable();
4290 DIExpression *Expression = DI.getExpression();
4291 uint64_t Offset = DI.getOffset();
4292 const Value *V = DI.getValue();
4297 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4298 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4300 DAG.AddDbgValue(SDV, nullptr, false);
4302 // Do not use getValue() in here; we don't want to generate code at
4303 // this point if it hasn't been done yet.
4304 SDValue N = NodeMap[V];
4305 if (!N.getNode() && isa<Argument>(V))
4306 // Check unused arguments map.
4307 N = UnusedArgNodeMap[V];
4309 // A dbg.value for an alloca is always indirect.
4310 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4311 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4313 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4314 IsIndirect, Offset, dl, SDNodeOrder);
4315 DAG.AddDbgValue(SDV, N.getNode(), false);
4317 } else if (!V->use_empty() ) {
4318 // Do not call getValue(V) yet, as we don't want to generate code.
4319 // Remember it for later.
4320 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4321 DanglingDebugInfoMap[V] = DDI;
4323 // We may expand this to cover more cases. One case where we have no
4324 // data available is an unreferenced parameter.
4325 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4329 // Build a debug info table entry.
4330 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4331 V = BCI->getOperand(0);
4332 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4333 // Don't handle byval struct arguments or VLAs, for example.
4335 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4336 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4339 DenseMap<const AllocaInst*, int>::iterator SI =
4340 FuncInfo.StaticAllocaMap.find(AI);
4341 if (SI == FuncInfo.StaticAllocaMap.end())
4342 return nullptr; // VLAs.
4346 case Intrinsic::eh_typeid_for: {
4347 // Find the type id for the given typeinfo.
4348 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4349 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4350 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4355 case Intrinsic::eh_return_i32:
4356 case Intrinsic::eh_return_i64:
4357 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4358 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4361 getValue(I.getArgOperand(0)),
4362 getValue(I.getArgOperand(1))));
4364 case Intrinsic::eh_unwind_init:
4365 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4367 case Intrinsic::eh_dwarf_cfa: {
4368 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4369 TLI.getPointerTy(DAG.getDataLayout()));
4370 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4371 CfaArg.getValueType(),
4372 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4373 CfaArg.getValueType()),
4375 SDValue FA = DAG.getNode(
4376 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4377 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4378 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4382 case Intrinsic::eh_sjlj_callsite: {
4383 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4384 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4385 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4386 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4388 MMI.setCurrentCallSite(CI->getZExtValue());
4391 case Intrinsic::eh_sjlj_functioncontext: {
4392 // Get and store the index of the function context.
4393 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4395 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4396 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4397 MFI->setFunctionContextIndex(FI);
4400 case Intrinsic::eh_sjlj_setjmp: {
4403 Ops[1] = getValue(I.getArgOperand(0));
4404 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4405 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4406 setValue(&I, Op.getValue(0));
4407 DAG.setRoot(Op.getValue(1));
4410 case Intrinsic::eh_sjlj_longjmp: {
4411 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4412 getRoot(), getValue(I.getArgOperand(0))));
4416 case Intrinsic::masked_gather:
4417 visitMaskedGather(I);
4419 case Intrinsic::masked_load:
4422 case Intrinsic::masked_scatter:
4423 visitMaskedScatter(I);
4425 case Intrinsic::masked_store:
4426 visitMaskedStore(I);
4428 case Intrinsic::x86_mmx_pslli_w:
4429 case Intrinsic::x86_mmx_pslli_d:
4430 case Intrinsic::x86_mmx_pslli_q:
4431 case Intrinsic::x86_mmx_psrli_w:
4432 case Intrinsic::x86_mmx_psrli_d:
4433 case Intrinsic::x86_mmx_psrli_q:
4434 case Intrinsic::x86_mmx_psrai_w:
4435 case Intrinsic::x86_mmx_psrai_d: {
4436 SDValue ShAmt = getValue(I.getArgOperand(1));
4437 if (isa<ConstantSDNode>(ShAmt)) {
4438 visitTargetIntrinsic(I, Intrinsic);
4441 unsigned NewIntrinsic = 0;
4442 EVT ShAmtVT = MVT::v2i32;
4443 switch (Intrinsic) {
4444 case Intrinsic::x86_mmx_pslli_w:
4445 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4447 case Intrinsic::x86_mmx_pslli_d:
4448 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4450 case Intrinsic::x86_mmx_pslli_q:
4451 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4453 case Intrinsic::x86_mmx_psrli_w:
4454 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4456 case Intrinsic::x86_mmx_psrli_d:
4457 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4459 case Intrinsic::x86_mmx_psrli_q:
4460 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4462 case Intrinsic::x86_mmx_psrai_w:
4463 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4465 case Intrinsic::x86_mmx_psrai_d:
4466 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4468 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4471 // The vector shift intrinsics with scalars uses 32b shift amounts but
4472 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4474 // We must do this early because v2i32 is not a legal type.
4477 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4478 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4479 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4480 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4481 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4482 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4483 getValue(I.getArgOperand(0)), ShAmt);
4487 case Intrinsic::convertff:
4488 case Intrinsic::convertfsi:
4489 case Intrinsic::convertfui:
4490 case Intrinsic::convertsif:
4491 case Intrinsic::convertuif:
4492 case Intrinsic::convertss:
4493 case Intrinsic::convertsu:
4494 case Intrinsic::convertus:
4495 case Intrinsic::convertuu: {
4496 ISD::CvtCode Code = ISD::CVT_INVALID;
4497 switch (Intrinsic) {
4498 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4499 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4500 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4501 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4502 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4503 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4504 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4505 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4506 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4507 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4509 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4510 const Value *Op1 = I.getArgOperand(0);
4511 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4512 DAG.getValueType(DestVT),
4513 DAG.getValueType(getValue(Op1).getValueType()),
4514 getValue(I.getArgOperand(1)),
4515 getValue(I.getArgOperand(2)),
4520 case Intrinsic::powi:
4521 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4522 getValue(I.getArgOperand(1)), DAG));
4524 case Intrinsic::log:
4525 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4527 case Intrinsic::log2:
4528 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4530 case Intrinsic::log10:
4531 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4533 case Intrinsic::exp:
4534 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4536 case Intrinsic::exp2:
4537 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4539 case Intrinsic::pow:
4540 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4541 getValue(I.getArgOperand(1)), DAG, TLI));
4543 case Intrinsic::sqrt:
4544 case Intrinsic::fabs:
4545 case Intrinsic::sin:
4546 case Intrinsic::cos:
4547 case Intrinsic::floor:
4548 case Intrinsic::ceil:
4549 case Intrinsic::trunc:
4550 case Intrinsic::rint:
4551 case Intrinsic::nearbyint:
4552 case Intrinsic::round: {
4554 switch (Intrinsic) {
4555 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4556 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4557 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4558 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4559 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4560 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4561 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4562 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4563 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4564 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4565 case Intrinsic::round: Opcode = ISD::FROUND; break;
4568 setValue(&I, DAG.getNode(Opcode, sdl,
4569 getValue(I.getArgOperand(0)).getValueType(),
4570 getValue(I.getArgOperand(0))));
4573 case Intrinsic::minnum:
4574 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4575 getValue(I.getArgOperand(0)).getValueType(),
4576 getValue(I.getArgOperand(0)),
4577 getValue(I.getArgOperand(1))));
4579 case Intrinsic::maxnum:
4580 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4581 getValue(I.getArgOperand(0)).getValueType(),
4582 getValue(I.getArgOperand(0)),
4583 getValue(I.getArgOperand(1))));
4585 case Intrinsic::copysign:
4586 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4587 getValue(I.getArgOperand(0)).getValueType(),
4588 getValue(I.getArgOperand(0)),
4589 getValue(I.getArgOperand(1))));
4591 case Intrinsic::fma:
4592 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4593 getValue(I.getArgOperand(0)).getValueType(),
4594 getValue(I.getArgOperand(0)),
4595 getValue(I.getArgOperand(1)),
4596 getValue(I.getArgOperand(2))));
4598 case Intrinsic::fmuladd: {
4599 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4600 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4601 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4602 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4603 getValue(I.getArgOperand(0)).getValueType(),
4604 getValue(I.getArgOperand(0)),
4605 getValue(I.getArgOperand(1)),
4606 getValue(I.getArgOperand(2))));
4608 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4609 getValue(I.getArgOperand(0)).getValueType(),
4610 getValue(I.getArgOperand(0)),
4611 getValue(I.getArgOperand(1)));
4612 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4613 getValue(I.getArgOperand(0)).getValueType(),
4615 getValue(I.getArgOperand(2)));
4620 case Intrinsic::convert_to_fp16:
4621 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4622 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4623 getValue(I.getArgOperand(0)),
4624 DAG.getTargetConstant(0, sdl,
4627 case Intrinsic::convert_from_fp16:
4628 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4629 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4630 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4631 getValue(I.getArgOperand(0)))));
4633 case Intrinsic::pcmarker: {
4634 SDValue Tmp = getValue(I.getArgOperand(0));
4635 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4638 case Intrinsic::readcyclecounter: {
4639 SDValue Op = getRoot();
4640 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4641 DAG.getVTList(MVT::i64, MVT::Other), Op);
4643 DAG.setRoot(Res.getValue(1));
4646 case Intrinsic::bswap:
4647 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4648 getValue(I.getArgOperand(0)).getValueType(),
4649 getValue(I.getArgOperand(0))));
4651 case Intrinsic::cttz: {
4652 SDValue Arg = getValue(I.getArgOperand(0));
4653 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4654 EVT Ty = Arg.getValueType();
4655 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4659 case Intrinsic::ctlz: {
4660 SDValue Arg = getValue(I.getArgOperand(0));
4661 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4662 EVT Ty = Arg.getValueType();
4663 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4667 case Intrinsic::ctpop: {
4668 SDValue Arg = getValue(I.getArgOperand(0));
4669 EVT Ty = Arg.getValueType();
4670 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4673 case Intrinsic::stacksave: {
4674 SDValue Op = getRoot();
4676 ISD::STACKSAVE, sdl,
4677 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4679 DAG.setRoot(Res.getValue(1));
4682 case Intrinsic::stackrestore: {
4683 Res = getValue(I.getArgOperand(0));
4684 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4687 case Intrinsic::stackprotector: {
4688 // Emit code into the DAG to store the stack guard onto the stack.
4689 MachineFunction &MF = DAG.getMachineFunction();
4690 MachineFrameInfo *MFI = MF.getFrameInfo();
4691 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4692 SDValue Src, Chain = getRoot();
4693 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4694 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4696 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4697 // global variable __stack_chk_guard.
4699 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4700 if (BC->getOpcode() == Instruction::BitCast)
4701 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4703 if (GV && TLI.useLoadStackGuardNode()) {
4704 // Emit a LOAD_STACK_GUARD node.
4705 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4707 MachinePointerInfo MPInfo(GV);
4708 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4709 unsigned Flags = MachineMemOperand::MOLoad |
4710 MachineMemOperand::MOInvariant;
4711 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4712 PtrTy.getSizeInBits() / 8,
4713 DAG.getEVTAlignment(PtrTy));
4714 Node->setMemRefs(MemRefs, MemRefs + 1);
4716 // Copy the guard value to a virtual register so that it can be
4717 // retrieved in the epilogue.
4718 Src = SDValue(Node, 0);
4719 const TargetRegisterClass *RC =
4720 TLI.getRegClassFor(Src.getSimpleValueType());
4721 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4723 SPDescriptor.setGuardReg(Reg);
4724 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4726 Src = getValue(I.getArgOperand(0)); // The guard's value.
4729 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4731 int FI = FuncInfo.StaticAllocaMap[Slot];
4732 MFI->setStackProtectorIndex(FI);
4734 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4736 // Store the stack protector onto the stack.
4737 Res = DAG.getStore(Chain, sdl, Src, FIN,
4738 MachinePointerInfo::getFixedStack(FI),
4744 case Intrinsic::objectsize: {
4745 // If we don't know by now, we're never going to know.
4746 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4748 assert(CI && "Non-constant type in __builtin_object_size?");
4750 SDValue Arg = getValue(I.getCalledValue());
4751 EVT Ty = Arg.getValueType();
4754 Res = DAG.getConstant(-1ULL, sdl, Ty);
4756 Res = DAG.getConstant(0, sdl, Ty);
4761 case Intrinsic::annotation:
4762 case Intrinsic::ptr_annotation:
4763 // Drop the intrinsic, but forward the value
4764 setValue(&I, getValue(I.getOperand(0)));
4766 case Intrinsic::assume:
4767 case Intrinsic::var_annotation:
4768 // Discard annotate attributes and assumptions
4771 case Intrinsic::init_trampoline: {
4772 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4776 Ops[1] = getValue(I.getArgOperand(0));
4777 Ops[2] = getValue(I.getArgOperand(1));
4778 Ops[3] = getValue(I.getArgOperand(2));
4779 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4780 Ops[5] = DAG.getSrcValue(F);
4782 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4787 case Intrinsic::adjust_trampoline: {
4788 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4789 TLI.getPointerTy(DAG.getDataLayout()),
4790 getValue(I.getArgOperand(0))));
4793 case Intrinsic::gcroot:
4795 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4796 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4798 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4799 GFI->addStackRoot(FI->getIndex(), TypeMap);
4802 case Intrinsic::gcread:
4803 case Intrinsic::gcwrite:
4804 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4805 case Intrinsic::flt_rounds:
4806 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4809 case Intrinsic::expect: {
4810 // Just replace __builtin_expect(exp, c) with EXP.
4811 setValue(&I, getValue(I.getArgOperand(0)));
4815 case Intrinsic::debugtrap:
4816 case Intrinsic::trap: {
4817 StringRef TrapFuncName =
4819 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4820 .getValueAsString();
4821 if (TrapFuncName.empty()) {
4822 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4823 ISD::TRAP : ISD::DEBUGTRAP;
4824 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4827 TargetLowering::ArgListTy Args;
4829 TargetLowering::CallLoweringInfo CLI(DAG);
4830 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4831 CallingConv::C, I.getType(),
4832 DAG.getExternalSymbol(TrapFuncName.data(),
4833 TLI.getPointerTy(DAG.getDataLayout())),
4834 std::move(Args), 0);
4836 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4837 DAG.setRoot(Result.second);
4841 case Intrinsic::uadd_with_overflow:
4842 case Intrinsic::sadd_with_overflow:
4843 case Intrinsic::usub_with_overflow:
4844 case Intrinsic::ssub_with_overflow:
4845 case Intrinsic::umul_with_overflow:
4846 case Intrinsic::smul_with_overflow: {
4848 switch (Intrinsic) {
4849 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4850 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4851 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4852 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4853 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4854 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4855 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4857 SDValue Op1 = getValue(I.getArgOperand(0));
4858 SDValue Op2 = getValue(I.getArgOperand(1));
4860 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4861 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4864 case Intrinsic::prefetch: {
4866 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4868 Ops[1] = getValue(I.getArgOperand(0));
4869 Ops[2] = getValue(I.getArgOperand(1));
4870 Ops[3] = getValue(I.getArgOperand(2));
4871 Ops[4] = getValue(I.getArgOperand(3));
4872 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4873 DAG.getVTList(MVT::Other), Ops,
4874 EVT::getIntegerVT(*Context, 8),
4875 MachinePointerInfo(I.getArgOperand(0)),
4877 false, /* volatile */
4879 rw==1)); /* write */
4882 case Intrinsic::lifetime_start:
4883 case Intrinsic::lifetime_end: {
4884 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4885 // Stack coloring is not enabled in O0, discard region information.
4886 if (TM.getOptLevel() == CodeGenOpt::None)
4889 SmallVector<Value *, 4> Allocas;
4890 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4892 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4893 E = Allocas.end(); Object != E; ++Object) {
4894 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4896 // Could not find an Alloca.
4897 if (!LifetimeObject)
4900 // First check that the Alloca is static, otherwise it won't have a
4901 // valid frame index.
4902 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4903 if (SI == FuncInfo.StaticAllocaMap.end())
4906 int FI = SI->second;
4911 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
4912 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4914 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4919 case Intrinsic::invariant_start:
4920 // Discard region information.
4921 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4923 case Intrinsic::invariant_end:
4924 // Discard region information.
4926 case Intrinsic::stackprotectorcheck: {
4927 // Do not actually emit anything for this basic block. Instead we initialize
4928 // the stack protector descriptor and export the guard variable so we can
4929 // access it in FinishBasicBlock.
4930 const BasicBlock *BB = I.getParent();
4931 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4932 ExportFromCurrentBlock(SPDescriptor.getGuard());
4934 // Flush our exports since we are going to process a terminator.
4935 (void)getControlRoot();
4938 case Intrinsic::clear_cache:
4939 return TLI.getClearCacheBuiltinName();
4940 case Intrinsic::eh_actions:
4941 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4943 case Intrinsic::donothing:
4946 case Intrinsic::experimental_stackmap: {
4950 case Intrinsic::experimental_patchpoint_void:
4951 case Intrinsic::experimental_patchpoint_i64: {
4952 visitPatchpoint(&I);
4955 case Intrinsic::experimental_gc_statepoint: {
4959 case Intrinsic::experimental_gc_result_int:
4960 case Intrinsic::experimental_gc_result_float:
4961 case Intrinsic::experimental_gc_result_ptr:
4962 case Intrinsic::experimental_gc_result: {
4966 case Intrinsic::experimental_gc_relocate: {
4970 case Intrinsic::instrprof_increment:
4971 llvm_unreachable("instrprof failed to lower an increment");
4973 case Intrinsic::localescape: {
4974 MachineFunction &MF = DAG.getMachineFunction();
4975 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4977 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
4978 // is the same on all targets.
4979 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4980 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4981 if (isa<ConstantPointerNull>(Arg))
4982 continue; // Skip null pointers. They represent a hole in index space.
4983 AllocaInst *Slot = cast<AllocaInst>(Arg);
4984 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4985 "can only escape static allocas");
4986 int FI = FuncInfo.StaticAllocaMap[Slot];
4987 MCSymbol *FrameAllocSym =
4988 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4989 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4991 TII->get(TargetOpcode::LOCAL_ESCAPE))
4992 .addSym(FrameAllocSym)
4999 case Intrinsic::localrecover: {
5000 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5001 MachineFunction &MF = DAG.getMachineFunction();
5002 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5004 // Get the symbol that defines the frame offset.
5005 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5006 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5007 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5008 MCSymbol *FrameAllocSym =
5009 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5010 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5012 // Create a MCSymbol for the label to avoid any target lowering
5013 // that would make this PC relative.
5014 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5016 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5018 // Add the offset to the FP.
5019 Value *FP = I.getArgOperand(1);
5020 SDValue FPVal = getValue(FP);
5021 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5026 case Intrinsic::eh_begincatch:
5027 case Intrinsic::eh_endcatch:
5028 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5029 case Intrinsic::eh_exceptioncode: {
5030 unsigned Reg = TLI.getExceptionPointerRegister();
5031 assert(Reg && "cannot get exception code on this platform");
5032 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5033 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5034 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
5035 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5037 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5038 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5045 std::pair<SDValue, SDValue>
5046 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5047 MachineBasicBlock *LandingPad) {
5048 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5049 MCSymbol *BeginLabel = nullptr;
5052 // Insert a label before the invoke call to mark the try range. This can be
5053 // used to detect deletion of the invoke via the MachineModuleInfo.
5054 BeginLabel = MMI.getContext().createTempSymbol();
5056 // For SjLj, keep track of which landing pads go with which invokes
5057 // so as to maintain the ordering of pads in the LSDA.
5058 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5059 if (CallSiteIndex) {
5060 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5061 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5063 // Now that the call site is handled, stop tracking it.
5064 MMI.setCurrentCallSite(0);
5067 // Both PendingLoads and PendingExports must be flushed here;
5068 // this call might not return.
5070 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5072 CLI.setChain(getRoot());
5074 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5075 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5077 assert((CLI.IsTailCall || Result.second.getNode()) &&
5078 "Non-null chain expected with non-tail call!");
5079 assert((Result.second.getNode() || !Result.first.getNode()) &&
5080 "Null value expected with tail call!");
5082 if (!Result.second.getNode()) {
5083 // As a special case, a null chain means that a tail call has been emitted
5084 // and the DAG root is already updated.
5087 // Since there's no actual continuation from this block, nothing can be
5088 // relying on us setting vregs for them.
5089 PendingExports.clear();
5091 DAG.setRoot(Result.second);
5095 // Insert a label at the end of the invoke call to mark the try range. This
5096 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5097 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5098 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5100 // Inform MachineModuleInfo of range.
5101 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5107 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5109 MachineBasicBlock *LandingPad) {
5110 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5111 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5112 Type *RetTy = FTy->getReturnType();
5114 TargetLowering::ArgListTy Args;
5115 TargetLowering::ArgListEntry Entry;
5116 Args.reserve(CS.arg_size());
5118 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5120 const Value *V = *i;
5123 if (V->getType()->isEmptyTy())
5126 SDValue ArgNode = getValue(V);
5127 Entry.Node = ArgNode; Entry.Ty = V->getType();
5129 // Skip the first return-type Attribute to get to params.
5130 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5131 Args.push_back(Entry);
5133 // If we have an explicit sret argument that is an Instruction, (i.e., it
5134 // might point to function-local memory), we can't meaningfully tail-call.
5135 if (Entry.isSRet && isa<Instruction>(V))
5139 // Check if target-independent constraints permit a tail call here.
5140 // Target-dependent constraints are checked within TLI->LowerCallTo.
5141 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5144 TargetLowering::CallLoweringInfo CLI(DAG);
5145 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5146 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5147 .setTailCall(isTailCall);
5148 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5150 if (Result.first.getNode())
5151 setValue(CS.getInstruction(), Result.first);
5154 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5155 /// value is equal or not-equal to zero.
5156 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5157 for (const User *U : V->users()) {
5158 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5159 if (IC->isEquality())
5160 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5161 if (C->isNullValue())
5163 // Unknown instruction.
5169 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5171 SelectionDAGBuilder &Builder) {
5173 // Check to see if this load can be trivially constant folded, e.g. if the
5174 // input is from a string literal.
5175 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5176 // Cast pointer to the type we really want to load.
5177 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5178 PointerType::getUnqual(LoadTy));
5180 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5181 const_cast<Constant *>(LoadInput), *Builder.DL))
5182 return Builder.getValue(LoadCst);
5185 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5186 // still constant memory, the input chain can be the entry node.
5188 bool ConstantMemory = false;
5190 // Do not serialize (non-volatile) loads of constant memory with anything.
5191 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5192 Root = Builder.DAG.getEntryNode();
5193 ConstantMemory = true;
5195 // Do not serialize non-volatile loads against each other.
5196 Root = Builder.DAG.getRoot();
5199 SDValue Ptr = Builder.getValue(PtrVal);
5200 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5201 Ptr, MachinePointerInfo(PtrVal),
5203 false /*nontemporal*/,
5204 false /*isinvariant*/, 1 /* align=1 */);
5206 if (!ConstantMemory)
5207 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5211 /// processIntegerCallValue - Record the value for an instruction that
5212 /// produces an integer result, converting the type where necessary.
5213 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5216 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5219 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5221 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5222 setValue(&I, Value);
5225 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5226 /// If so, return true and lower it, otherwise return false and it will be
5227 /// lowered like a normal call.
5228 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5229 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5230 if (I.getNumArgOperands() != 3)
5233 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5234 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5235 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5236 !I.getType()->isIntegerTy())
5239 const Value *Size = I.getArgOperand(2);
5240 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5241 if (CSize && CSize->getZExtValue() == 0) {
5242 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5244 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5248 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5249 std::pair<SDValue, SDValue> Res =
5250 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5251 getValue(LHS), getValue(RHS), getValue(Size),
5252 MachinePointerInfo(LHS),
5253 MachinePointerInfo(RHS));
5254 if (Res.first.getNode()) {
5255 processIntegerCallValue(I, Res.first, true);
5256 PendingLoads.push_back(Res.second);
5260 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5261 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5262 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5263 bool ActuallyDoIt = true;
5266 switch (CSize->getZExtValue()) {
5268 LoadVT = MVT::Other;
5270 ActuallyDoIt = false;
5274 LoadTy = Type::getInt16Ty(CSize->getContext());
5278 LoadTy = Type::getInt32Ty(CSize->getContext());
5282 LoadTy = Type::getInt64Ty(CSize->getContext());
5286 LoadVT = MVT::v4i32;
5287 LoadTy = Type::getInt32Ty(CSize->getContext());
5288 LoadTy = VectorType::get(LoadTy, 4);
5293 // This turns into unaligned loads. We only do this if the target natively
5294 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5295 // we'll only produce a small number of byte loads.
5297 // Require that we can find a legal MVT, and only do this if the target
5298 // supports unaligned loads of that type. Expanding into byte loads would
5300 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5301 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5302 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5303 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5304 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5305 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5306 // TODO: Check alignment of src and dest ptrs.
5307 if (!TLI.isTypeLegal(LoadVT) ||
5308 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5309 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5310 ActuallyDoIt = false;
5314 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5315 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5317 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5319 processIntegerCallValue(I, Res, false);
5328 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5329 /// form. If so, return true and lower it, otherwise return false and it
5330 /// will be lowered like a normal call.
5331 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5332 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5333 if (I.getNumArgOperands() != 3)
5336 const Value *Src = I.getArgOperand(0);
5337 const Value *Char = I.getArgOperand(1);
5338 const Value *Length = I.getArgOperand(2);
5339 if (!Src->getType()->isPointerTy() ||
5340 !Char->getType()->isIntegerTy() ||
5341 !Length->getType()->isIntegerTy() ||
5342 !I.getType()->isPointerTy())
5345 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5346 std::pair<SDValue, SDValue> Res =
5347 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5348 getValue(Src), getValue(Char), getValue(Length),
5349 MachinePointerInfo(Src));
5350 if (Res.first.getNode()) {
5351 setValue(&I, Res.first);
5352 PendingLoads.push_back(Res.second);
5359 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5360 /// optimized form. If so, return true and lower it, otherwise return false
5361 /// and it will be lowered like a normal call.
5362 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5363 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5364 if (I.getNumArgOperands() != 2)
5367 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5368 if (!Arg0->getType()->isPointerTy() ||
5369 !Arg1->getType()->isPointerTy() ||
5370 !I.getType()->isPointerTy())
5373 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5374 std::pair<SDValue, SDValue> Res =
5375 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5376 getValue(Arg0), getValue(Arg1),
5377 MachinePointerInfo(Arg0),
5378 MachinePointerInfo(Arg1), isStpcpy);
5379 if (Res.first.getNode()) {
5380 setValue(&I, Res.first);
5381 DAG.setRoot(Res.second);
5388 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5389 /// If so, return true and lower it, otherwise return false and it will be
5390 /// lowered like a normal call.
5391 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5392 // Verify that the prototype makes sense. int strcmp(void*,void*)
5393 if (I.getNumArgOperands() != 2)
5396 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5397 if (!Arg0->getType()->isPointerTy() ||
5398 !Arg1->getType()->isPointerTy() ||
5399 !I.getType()->isIntegerTy())
5402 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5403 std::pair<SDValue, SDValue> Res =
5404 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5405 getValue(Arg0), getValue(Arg1),
5406 MachinePointerInfo(Arg0),
5407 MachinePointerInfo(Arg1));
5408 if (Res.first.getNode()) {
5409 processIntegerCallValue(I, Res.first, true);
5410 PendingLoads.push_back(Res.second);
5417 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5418 /// form. If so, return true and lower it, otherwise return false and it
5419 /// will be lowered like a normal call.
5420 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5421 // Verify that the prototype makes sense. size_t strlen(char *)
5422 if (I.getNumArgOperands() != 1)
5425 const Value *Arg0 = I.getArgOperand(0);
5426 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5429 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5430 std::pair<SDValue, SDValue> Res =
5431 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5432 getValue(Arg0), MachinePointerInfo(Arg0));
5433 if (Res.first.getNode()) {
5434 processIntegerCallValue(I, Res.first, false);
5435 PendingLoads.push_back(Res.second);
5442 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5443 /// form. If so, return true and lower it, otherwise return false and it
5444 /// will be lowered like a normal call.
5445 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5446 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5447 if (I.getNumArgOperands() != 2)
5450 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5451 if (!Arg0->getType()->isPointerTy() ||
5452 !Arg1->getType()->isIntegerTy() ||
5453 !I.getType()->isIntegerTy())
5456 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5457 std::pair<SDValue, SDValue> Res =
5458 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5459 getValue(Arg0), getValue(Arg1),
5460 MachinePointerInfo(Arg0));
5461 if (Res.first.getNode()) {
5462 processIntegerCallValue(I, Res.first, false);
5463 PendingLoads.push_back(Res.second);
5470 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5471 /// operation (as expected), translate it to an SDNode with the specified opcode
5472 /// and return true.
5473 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5475 // Sanity check that it really is a unary floating-point call.
5476 if (I.getNumArgOperands() != 1 ||
5477 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5478 I.getType() != I.getArgOperand(0)->getType() ||
5479 !I.onlyReadsMemory())
5482 SDValue Tmp = getValue(I.getArgOperand(0));
5483 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5487 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5488 /// operation (as expected), translate it to an SDNode with the specified opcode
5489 /// and return true.
5490 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5492 // Sanity check that it really is a binary floating-point call.
5493 if (I.getNumArgOperands() != 2 ||
5494 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5495 I.getType() != I.getArgOperand(0)->getType() ||
5496 I.getType() != I.getArgOperand(1)->getType() ||
5497 !I.onlyReadsMemory())
5500 SDValue Tmp0 = getValue(I.getArgOperand(0));
5501 SDValue Tmp1 = getValue(I.getArgOperand(1));
5502 EVT VT = Tmp0.getValueType();
5503 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5507 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5508 // Handle inline assembly differently.
5509 if (isa<InlineAsm>(I.getCalledValue())) {
5514 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5515 ComputeUsesVAFloatArgument(I, &MMI);
5517 const char *RenameFn = nullptr;
5518 if (Function *F = I.getCalledFunction()) {
5519 if (F->isDeclaration()) {
5520 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5521 if (unsigned IID = II->getIntrinsicID(F)) {
5522 RenameFn = visitIntrinsicCall(I, IID);
5527 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5528 RenameFn = visitIntrinsicCall(I, IID);
5534 // Check for well-known libc/libm calls. If the function is internal, it
5535 // can't be a library call.
5537 if (!F->hasLocalLinkage() && F->hasName() &&
5538 LibInfo->getLibFunc(F->getName(), Func) &&
5539 LibInfo->hasOptimizedCodeGen(Func)) {
5542 case LibFunc::copysign:
5543 case LibFunc::copysignf:
5544 case LibFunc::copysignl:
5545 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5546 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5547 I.getType() == I.getArgOperand(0)->getType() &&
5548 I.getType() == I.getArgOperand(1)->getType() &&
5549 I.onlyReadsMemory()) {
5550 SDValue LHS = getValue(I.getArgOperand(0));
5551 SDValue RHS = getValue(I.getArgOperand(1));
5552 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5553 LHS.getValueType(), LHS, RHS));
5558 case LibFunc::fabsf:
5559 case LibFunc::fabsl:
5560 if (visitUnaryFloatCall(I, ISD::FABS))
5564 case LibFunc::fminf:
5565 case LibFunc::fminl:
5566 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5570 case LibFunc::fmaxf:
5571 case LibFunc::fmaxl:
5572 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5578 if (visitUnaryFloatCall(I, ISD::FSIN))
5584 if (visitUnaryFloatCall(I, ISD::FCOS))
5588 case LibFunc::sqrtf:
5589 case LibFunc::sqrtl:
5590 case LibFunc::sqrt_finite:
5591 case LibFunc::sqrtf_finite:
5592 case LibFunc::sqrtl_finite:
5593 if (visitUnaryFloatCall(I, ISD::FSQRT))
5596 case LibFunc::floor:
5597 case LibFunc::floorf:
5598 case LibFunc::floorl:
5599 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5602 case LibFunc::nearbyint:
5603 case LibFunc::nearbyintf:
5604 case LibFunc::nearbyintl:
5605 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5609 case LibFunc::ceilf:
5610 case LibFunc::ceill:
5611 if (visitUnaryFloatCall(I, ISD::FCEIL))
5615 case LibFunc::rintf:
5616 case LibFunc::rintl:
5617 if (visitUnaryFloatCall(I, ISD::FRINT))
5620 case LibFunc::round:
5621 case LibFunc::roundf:
5622 case LibFunc::roundl:
5623 if (visitUnaryFloatCall(I, ISD::FROUND))
5626 case LibFunc::trunc:
5627 case LibFunc::truncf:
5628 case LibFunc::truncl:
5629 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5633 case LibFunc::log2f:
5634 case LibFunc::log2l:
5635 if (visitUnaryFloatCall(I, ISD::FLOG2))
5639 case LibFunc::exp2f:
5640 case LibFunc::exp2l:
5641 if (visitUnaryFloatCall(I, ISD::FEXP2))
5644 case LibFunc::memcmp:
5645 if (visitMemCmpCall(I))
5648 case LibFunc::memchr:
5649 if (visitMemChrCall(I))
5652 case LibFunc::strcpy:
5653 if (visitStrCpyCall(I, false))
5656 case LibFunc::stpcpy:
5657 if (visitStrCpyCall(I, true))
5660 case LibFunc::strcmp:
5661 if (visitStrCmpCall(I))
5664 case LibFunc::strlen:
5665 if (visitStrLenCall(I))
5668 case LibFunc::strnlen:
5669 if (visitStrNLenCall(I))
5678 Callee = getValue(I.getCalledValue());
5680 Callee = DAG.getExternalSymbol(
5682 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5684 // Check if we can potentially perform a tail call. More detailed checking is
5685 // be done within LowerCallTo, after more information about the call is known.
5686 LowerCallTo(&I, Callee, I.isTailCall());
5691 /// AsmOperandInfo - This contains information for each constraint that we are
5693 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5695 /// CallOperand - If this is the result output operand or a clobber
5696 /// this is null, otherwise it is the incoming operand to the CallInst.
5697 /// This gets modified as the asm is processed.
5698 SDValue CallOperand;
5700 /// AssignedRegs - If this is a register or register class operand, this
5701 /// contains the set of register corresponding to the operand.
5702 RegsForValue AssignedRegs;
5704 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5705 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5708 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5709 /// corresponds to. If there is no Value* for this operand, it returns
5711 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5712 const DataLayout &DL) const {
5713 if (!CallOperandVal) return MVT::Other;
5715 if (isa<BasicBlock>(CallOperandVal))
5716 return TLI.getPointerTy(DL);
5718 llvm::Type *OpTy = CallOperandVal->getType();
5720 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5721 // If this is an indirect operand, the operand is a pointer to the
5724 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5726 report_fatal_error("Indirect operand for inline asm not a pointer!");
5727 OpTy = PtrTy->getElementType();
5730 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5731 if (StructType *STy = dyn_cast<StructType>(OpTy))
5732 if (STy->getNumElements() == 1)
5733 OpTy = STy->getElementType(0);
5735 // If OpTy is not a single value, it may be a struct/union that we
5736 // can tile with integers.
5737 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5738 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5747 OpTy = IntegerType::get(Context, BitSize);
5752 return TLI.getValueType(DL, OpTy, true);
5756 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5758 } // end anonymous namespace
5760 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5761 /// specified operand. We prefer to assign virtual registers, to allow the
5762 /// register allocator to handle the assignment process. However, if the asm
5763 /// uses features that we can't model on machineinstrs, we have SDISel do the
5764 /// allocation. This produces generally horrible, but correct, code.
5766 /// OpInfo describes the operand.
5768 static void GetRegistersForValue(SelectionDAG &DAG,
5769 const TargetLowering &TLI,
5771 SDISelAsmOperandInfo &OpInfo) {
5772 LLVMContext &Context = *DAG.getContext();
5774 MachineFunction &MF = DAG.getMachineFunction();
5775 SmallVector<unsigned, 4> Regs;
5777 // If this is a constraint for a single physreg, or a constraint for a
5778 // register class, find it.
5779 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5780 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5781 OpInfo.ConstraintCode,
5782 OpInfo.ConstraintVT);
5784 unsigned NumRegs = 1;
5785 if (OpInfo.ConstraintVT != MVT::Other) {
5786 // If this is a FP input in an integer register (or visa versa) insert a bit
5787 // cast of the input value. More generally, handle any case where the input
5788 // value disagrees with the register class we plan to stick this in.
5789 if (OpInfo.Type == InlineAsm::isInput &&
5790 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5791 // Try to convert to the first EVT that the reg class contains. If the
5792 // types are identical size, use a bitcast to convert (e.g. two differing
5794 MVT RegVT = *PhysReg.second->vt_begin();
5795 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5796 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5797 RegVT, OpInfo.CallOperand);
5798 OpInfo.ConstraintVT = RegVT;
5799 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5800 // If the input is a FP value and we want it in FP registers, do a
5801 // bitcast to the corresponding integer type. This turns an f64 value
5802 // into i64, which can be passed with two i32 values on a 32-bit
5804 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5805 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5806 RegVT, OpInfo.CallOperand);
5807 OpInfo.ConstraintVT = RegVT;
5811 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5815 EVT ValueVT = OpInfo.ConstraintVT;
5817 // If this is a constraint for a specific physical register, like {r17},
5819 if (unsigned AssignedReg = PhysReg.first) {
5820 const TargetRegisterClass *RC = PhysReg.second;
5821 if (OpInfo.ConstraintVT == MVT::Other)
5822 ValueVT = *RC->vt_begin();
5824 // Get the actual register value type. This is important, because the user
5825 // may have asked for (e.g.) the AX register in i32 type. We need to
5826 // remember that AX is actually i16 to get the right extension.
5827 RegVT = *RC->vt_begin();
5829 // This is a explicit reference to a physical register.
5830 Regs.push_back(AssignedReg);
5832 // If this is an expanded reference, add the rest of the regs to Regs.
5834 TargetRegisterClass::iterator I = RC->begin();
5835 for (; *I != AssignedReg; ++I)
5836 assert(I != RC->end() && "Didn't find reg!");
5838 // Already added the first reg.
5840 for (; NumRegs; --NumRegs, ++I) {
5841 assert(I != RC->end() && "Ran out of registers to allocate!");
5846 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5850 // Otherwise, if this was a reference to an LLVM register class, create vregs
5851 // for this reference.
5852 if (const TargetRegisterClass *RC = PhysReg.second) {
5853 RegVT = *RC->vt_begin();
5854 if (OpInfo.ConstraintVT == MVT::Other)
5857 // Create the appropriate number of virtual registers.
5858 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5859 for (; NumRegs; --NumRegs)
5860 Regs.push_back(RegInfo.createVirtualRegister(RC));
5862 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5866 // Otherwise, we couldn't allocate enough registers for this.
5869 /// visitInlineAsm - Handle a call to an InlineAsm object.
5871 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5872 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5874 /// ConstraintOperands - Information about all of the constraints.
5875 SDISelAsmOperandInfoVector ConstraintOperands;
5877 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5878 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5879 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5881 bool hasMemory = false;
5883 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5884 unsigned ResNo = 0; // ResNo - The result number of the next output.
5885 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5886 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5887 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5889 MVT OpVT = MVT::Other;
5891 // Compute the value type for each operand.
5892 switch (OpInfo.Type) {
5893 case InlineAsm::isOutput:
5894 // Indirect outputs just consume an argument.
5895 if (OpInfo.isIndirect) {
5896 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5900 // The return value of the call is this value. As such, there is no
5901 // corresponding argument.
5902 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5903 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5904 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
5905 STy->getElementType(ResNo));
5907 assert(ResNo == 0 && "Asm only has one result!");
5908 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
5912 case InlineAsm::isInput:
5913 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5915 case InlineAsm::isClobber:
5920 // If this is an input or an indirect output, process the call argument.
5921 // BasicBlocks are labels, currently appearing only in asm's.
5922 if (OpInfo.CallOperandVal) {
5923 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5924 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5926 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5929 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
5930 DAG.getDataLayout()).getSimpleVT();
5933 OpInfo.ConstraintVT = OpVT;
5935 // Indirect operand accesses access memory.
5936 if (OpInfo.isIndirect)
5939 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5940 TargetLowering::ConstraintType
5941 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5942 if (CType == TargetLowering::C_Memory) {
5950 SDValue Chain, Flag;
5952 // We won't need to flush pending loads if this asm doesn't touch
5953 // memory and is nonvolatile.
5954 if (hasMemory || IA->hasSideEffects())
5957 Chain = DAG.getRoot();
5959 // Second pass over the constraints: compute which constraint option to use
5960 // and assign registers to constraints that want a specific physreg.
5961 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5962 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5964 // If this is an output operand with a matching input operand, look up the
5965 // matching input. If their types mismatch, e.g. one is an integer, the
5966 // other is floating point, or their sizes are different, flag it as an
5968 if (OpInfo.hasMatchingInput()) {
5969 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5971 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5972 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5973 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5974 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5975 OpInfo.ConstraintVT);
5976 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5977 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5978 Input.ConstraintVT);
5979 if ((OpInfo.ConstraintVT.isInteger() !=
5980 Input.ConstraintVT.isInteger()) ||
5981 (MatchRC.second != InputRC.second)) {
5982 report_fatal_error("Unsupported asm: input constraint"
5983 " with a matching output constraint of"
5984 " incompatible type!");
5986 Input.ConstraintVT = OpInfo.ConstraintVT;
5990 // Compute the constraint code and ConstraintType to use.
5991 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5993 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5994 OpInfo.Type == InlineAsm::isClobber)
5997 // If this is a memory input, and if the operand is not indirect, do what we
5998 // need to to provide an address for the memory input.
5999 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6000 !OpInfo.isIndirect) {
6001 assert((OpInfo.isMultipleAlternative ||
6002 (OpInfo.Type == InlineAsm::isInput)) &&
6003 "Can only indirectify direct input operands!");
6005 // Memory operands really want the address of the value. If we don't have
6006 // an indirect input, put it in the constpool if we can, otherwise spill
6007 // it to a stack slot.
6008 // TODO: This isn't quite right. We need to handle these according to
6009 // the addressing mode that the constraint wants. Also, this may take
6010 // an additional register for the computation and we don't want that
6013 // If the operand is a float, integer, or vector constant, spill to a
6014 // constant pool entry to get its address.
6015 const Value *OpVal = OpInfo.CallOperandVal;
6016 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6017 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6018 OpInfo.CallOperand = DAG.getConstantPool(
6019 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6021 // Otherwise, create a stack slot and emit a store to it before the
6023 Type *Ty = OpVal->getType();
6024 auto &DL = DAG.getDataLayout();
6025 uint64_t TySize = DL.getTypeAllocSize(Ty);
6026 unsigned Align = DL.getPrefTypeAlignment(Ty);
6027 MachineFunction &MF = DAG.getMachineFunction();
6028 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6030 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6031 Chain = DAG.getStore(Chain, getCurSDLoc(),
6032 OpInfo.CallOperand, StackSlot,
6033 MachinePointerInfo::getFixedStack(SSFI),
6035 OpInfo.CallOperand = StackSlot;
6038 // There is no longer a Value* corresponding to this operand.
6039 OpInfo.CallOperandVal = nullptr;
6041 // It is now an indirect operand.
6042 OpInfo.isIndirect = true;
6045 // If this constraint is for a specific register, allocate it before
6047 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6048 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6051 // Second pass - Loop over all of the operands, assigning virtual or physregs
6052 // to register class operands.
6053 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6054 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6056 // C_Register operands have already been allocated, Other/Memory don't need
6058 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6059 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6062 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6063 std::vector<SDValue> AsmNodeOperands;
6064 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6065 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6066 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6068 // If we have a !srcloc metadata node associated with it, we want to attach
6069 // this to the ultimately generated inline asm machineinstr. To do this, we
6070 // pass in the third operand as this (potentially null) inline asm MDNode.
6071 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6072 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6074 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6075 // bits as operand 3.
6076 unsigned ExtraInfo = 0;
6077 if (IA->hasSideEffects())
6078 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6079 if (IA->isAlignStack())
6080 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6081 // Set the asm dialect.
6082 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6084 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6085 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6086 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6088 // Compute the constraint code and ConstraintType to use.
6089 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6091 // Ideally, we would only check against memory constraints. However, the
6092 // meaning of an other constraint can be target-specific and we can't easily
6093 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6094 // for other constriants as well.
6095 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6096 OpInfo.ConstraintType == TargetLowering::C_Other) {
6097 if (OpInfo.Type == InlineAsm::isInput)
6098 ExtraInfo |= InlineAsm::Extra_MayLoad;
6099 else if (OpInfo.Type == InlineAsm::isOutput)
6100 ExtraInfo |= InlineAsm::Extra_MayStore;
6101 else if (OpInfo.Type == InlineAsm::isClobber)
6102 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6106 AsmNodeOperands.push_back(DAG.getTargetConstant(
6107 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6109 // Loop over all of the inputs, copying the operand values into the
6110 // appropriate registers and processing the output regs.
6111 RegsForValue RetValRegs;
6113 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6114 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6116 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6117 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6119 switch (OpInfo.Type) {
6120 case InlineAsm::isOutput: {
6121 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6122 OpInfo.ConstraintType != TargetLowering::C_Register) {
6123 // Memory output, or 'other' output (e.g. 'X' constraint).
6124 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6126 unsigned ConstraintID =
6127 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6128 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6129 "Failed to convert memory constraint code to constraint id.");
6131 // Add information to the INLINEASM node to know about this output.
6132 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6133 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6134 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6136 AsmNodeOperands.push_back(OpInfo.CallOperand);
6140 // Otherwise, this is a register or register class output.
6142 // Copy the output from the appropriate register. Find a register that
6144 if (OpInfo.AssignedRegs.Regs.empty()) {
6145 LLVMContext &Ctx = *DAG.getContext();
6146 Ctx.emitError(CS.getInstruction(),
6147 "couldn't allocate output register for constraint '" +
6148 Twine(OpInfo.ConstraintCode) + "'");
6152 // If this is an indirect operand, store through the pointer after the
6154 if (OpInfo.isIndirect) {
6155 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6156 OpInfo.CallOperandVal));
6158 // This is the result value of the call.
6159 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6160 // Concatenate this output onto the outputs list.
6161 RetValRegs.append(OpInfo.AssignedRegs);
6164 // Add information to the INLINEASM node to know that this register is
6167 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6168 ? InlineAsm::Kind_RegDefEarlyClobber
6169 : InlineAsm::Kind_RegDef,
6170 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6173 case InlineAsm::isInput: {
6174 SDValue InOperandVal = OpInfo.CallOperand;
6176 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6177 // If this is required to match an output register we have already set,
6178 // just use its register.
6179 unsigned OperandNo = OpInfo.getMatchedOperand();
6181 // Scan until we find the definition we already emitted of this operand.
6182 // When we find it, create a RegsForValue operand.
6183 unsigned CurOp = InlineAsm::Op_FirstOperand;
6184 for (; OperandNo; --OperandNo) {
6185 // Advance to the next operand.
6187 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6188 assert((InlineAsm::isRegDefKind(OpFlag) ||
6189 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6190 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6191 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6195 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6196 if (InlineAsm::isRegDefKind(OpFlag) ||
6197 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6198 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6199 if (OpInfo.isIndirect) {
6200 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6201 LLVMContext &Ctx = *DAG.getContext();
6202 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6203 " don't know how to handle tied "
6204 "indirect register inputs");
6208 RegsForValue MatchedRegs;
6209 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6210 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6211 MatchedRegs.RegVTs.push_back(RegVT);
6212 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6213 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6215 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6216 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6218 LLVMContext &Ctx = *DAG.getContext();
6219 Ctx.emitError(CS.getInstruction(),
6220 "inline asm error: This value"
6221 " type register class is not natively supported!");
6225 SDLoc dl = getCurSDLoc();
6226 // Use the produced MatchedRegs object to
6227 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6228 Chain, &Flag, CS.getInstruction());
6229 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6230 true, OpInfo.getMatchedOperand(), dl,
6231 DAG, AsmNodeOperands);
6235 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6236 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6237 "Unexpected number of operands");
6238 // Add information to the INLINEASM node to know about this input.
6239 // See InlineAsm.h isUseOperandTiedToDef.
6240 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6241 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6242 OpInfo.getMatchedOperand());
6243 AsmNodeOperands.push_back(DAG.getTargetConstant(
6244 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6245 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6249 // Treat indirect 'X' constraint as memory.
6250 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6252 OpInfo.ConstraintType = TargetLowering::C_Memory;
6254 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6255 std::vector<SDValue> Ops;
6256 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6259 LLVMContext &Ctx = *DAG.getContext();
6260 Ctx.emitError(CS.getInstruction(),
6261 "invalid operand for inline asm constraint '" +
6262 Twine(OpInfo.ConstraintCode) + "'");
6266 // Add information to the INLINEASM node to know about this input.
6267 unsigned ResOpType =
6268 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6269 AsmNodeOperands.push_back(DAG.getTargetConstant(
6270 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6271 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6275 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6276 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6277 assert(InOperandVal.getValueType() ==
6278 TLI.getPointerTy(DAG.getDataLayout()) &&
6279 "Memory operands expect pointer values");
6281 unsigned ConstraintID =
6282 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6283 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6284 "Failed to convert memory constraint code to constraint id.");
6286 // Add information to the INLINEASM node to know about this input.
6287 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6288 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6289 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6292 AsmNodeOperands.push_back(InOperandVal);
6296 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6297 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6298 "Unknown constraint type!");
6300 // TODO: Support this.
6301 if (OpInfo.isIndirect) {
6302 LLVMContext &Ctx = *DAG.getContext();
6303 Ctx.emitError(CS.getInstruction(),
6304 "Don't know how to handle indirect register inputs yet "
6305 "for constraint '" +
6306 Twine(OpInfo.ConstraintCode) + "'");
6310 // Copy the input into the appropriate registers.
6311 if (OpInfo.AssignedRegs.Regs.empty()) {
6312 LLVMContext &Ctx = *DAG.getContext();
6313 Ctx.emitError(CS.getInstruction(),
6314 "couldn't allocate input reg for constraint '" +
6315 Twine(OpInfo.ConstraintCode) + "'");
6319 SDLoc dl = getCurSDLoc();
6321 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6322 Chain, &Flag, CS.getInstruction());
6324 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6325 dl, DAG, AsmNodeOperands);
6328 case InlineAsm::isClobber: {
6329 // Add the clobbered value to the operand list, so that the register
6330 // allocator is aware that the physreg got clobbered.
6331 if (!OpInfo.AssignedRegs.Regs.empty())
6332 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6333 false, 0, getCurSDLoc(), DAG,
6340 // Finish up input operands. Set the input chain and add the flag last.
6341 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6342 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6344 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6345 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6346 Flag = Chain.getValue(1);
6348 // If this asm returns a register value, copy the result from that register
6349 // and set it as the value of the call.
6350 if (!RetValRegs.Regs.empty()) {
6351 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6352 Chain, &Flag, CS.getInstruction());
6354 // FIXME: Why don't we do this for inline asms with MRVs?
6355 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6356 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6358 // If any of the results of the inline asm is a vector, it may have the
6359 // wrong width/num elts. This can happen for register classes that can
6360 // contain multiple different value types. The preg or vreg allocated may
6361 // not have the same VT as was expected. Convert it to the right type
6362 // with bit_convert.
6363 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6364 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6367 } else if (ResultType != Val.getValueType() &&
6368 ResultType.isInteger() && Val.getValueType().isInteger()) {
6369 // If a result value was tied to an input value, the computed result may
6370 // have a wider width than the expected result. Extract the relevant
6372 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6375 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6378 setValue(CS.getInstruction(), Val);
6379 // Don't need to use this as a chain in this case.
6380 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6384 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6386 // Process indirect outputs, first output all of the flagged copies out of
6388 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6389 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6390 const Value *Ptr = IndirectStoresToEmit[i].second;
6391 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6393 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6396 // Emit the non-flagged stores from the physregs.
6397 SmallVector<SDValue, 8> OutChains;
6398 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6399 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6400 StoresToEmit[i].first,
6401 getValue(StoresToEmit[i].second),
6402 MachinePointerInfo(StoresToEmit[i].second),
6404 OutChains.push_back(Val);
6407 if (!OutChains.empty())
6408 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6413 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6414 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6415 MVT::Other, getRoot(),
6416 getValue(I.getArgOperand(0)),
6417 DAG.getSrcValue(I.getArgOperand(0))));
6420 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6422 const DataLayout &DL = DAG.getDataLayout();
6423 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6424 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6425 DAG.getSrcValue(I.getOperand(0)),
6426 DL.getABITypeAlignment(I.getType()));
6428 DAG.setRoot(V.getValue(1));
6431 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6432 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6433 MVT::Other, getRoot(),
6434 getValue(I.getArgOperand(0)),
6435 DAG.getSrcValue(I.getArgOperand(0))));
6438 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6439 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6440 MVT::Other, getRoot(),
6441 getValue(I.getArgOperand(0)),
6442 getValue(I.getArgOperand(1)),
6443 DAG.getSrcValue(I.getArgOperand(0)),
6444 DAG.getSrcValue(I.getArgOperand(1))));
6447 /// \brief Lower an argument list according to the target calling convention.
6449 /// \return A tuple of <return-value, token-chain>
6451 /// This is a helper for lowering intrinsics that follow a target calling
6452 /// convention or require stack pointer adjustment. Only a subset of the
6453 /// intrinsic's operands need to participate in the calling convention.
6454 std::pair<SDValue, SDValue>
6455 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6456 unsigned NumArgs, SDValue Callee,
6458 MachineBasicBlock *LandingPad,
6459 bool IsPatchPoint) {
6460 TargetLowering::ArgListTy Args;
6461 Args.reserve(NumArgs);
6463 // Populate the argument list.
6464 // Attributes for args start at offset 1, after the return attribute.
6465 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6466 ArgI != ArgE; ++ArgI) {
6467 const Value *V = CS->getOperand(ArgI);
6469 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6471 TargetLowering::ArgListEntry Entry;
6472 Entry.Node = getValue(V);
6473 Entry.Ty = V->getType();
6474 Entry.setAttributes(&CS, AttrI);
6475 Args.push_back(Entry);
6478 TargetLowering::CallLoweringInfo CLI(DAG);
6479 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6480 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6481 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6483 return lowerInvokable(CLI, LandingPad);
6486 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6487 /// or patchpoint target node's operand list.
6489 /// Constants are converted to TargetConstants purely as an optimization to
6490 /// avoid constant materialization and register allocation.
6492 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6493 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6494 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6495 /// address materialization and register allocation, but may also be required
6496 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6497 /// alloca in the entry block, then the runtime may assume that the alloca's
6498 /// StackMap location can be read immediately after compilation and that the
6499 /// location is valid at any point during execution (this is similar to the
6500 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6501 /// only available in a register, then the runtime would need to trap when
6502 /// execution reaches the StackMap in order to read the alloca's location.
6503 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6504 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6505 SelectionDAGBuilder &Builder) {
6506 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6507 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6510 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6512 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6513 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6514 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6515 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6516 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6518 Ops.push_back(OpVal);
6522 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6523 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6524 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6525 // [live variables...])
6527 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6529 SDValue Chain, InFlag, Callee, NullPtr;
6530 SmallVector<SDValue, 32> Ops;
6532 SDLoc DL = getCurSDLoc();
6533 Callee = getValue(CI.getCalledValue());
6534 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6536 // The stackmap intrinsic only records the live variables (the arguemnts
6537 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6538 // intrinsic, this won't be lowered to a function call. This means we don't
6539 // have to worry about calling conventions and target specific lowering code.
6540 // Instead we perform the call lowering right here.
6542 // chain, flag = CALLSEQ_START(chain, 0)
6543 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6544 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6546 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6547 InFlag = Chain.getValue(1);
6549 // Add the <id> and <numBytes> constants.
6550 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6551 Ops.push_back(DAG.getTargetConstant(
6552 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6553 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6554 Ops.push_back(DAG.getTargetConstant(
6555 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6558 // Push live variables for the stack map.
6559 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6561 // We are not pushing any register mask info here on the operands list,
6562 // because the stackmap doesn't clobber anything.
6564 // Push the chain and the glue flag.
6565 Ops.push_back(Chain);
6566 Ops.push_back(InFlag);
6568 // Create the STACKMAP node.
6569 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6570 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6571 Chain = SDValue(SM, 0);
6572 InFlag = Chain.getValue(1);
6574 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6576 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6578 // Set the root to the target-lowered call chain.
6581 // Inform the Frame Information that we have a stackmap in this function.
6582 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6585 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6586 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6587 MachineBasicBlock *LandingPad) {
6588 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6593 // [live variables...])
6595 CallingConv::ID CC = CS.getCallingConv();
6596 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6597 bool HasDef = !CS->getType()->isVoidTy();
6598 SDLoc dl = getCurSDLoc();
6599 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6601 // Handle immediate and symbolic callees.
6602 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6603 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6605 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6606 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6607 SDLoc(SymbolicCallee),
6608 SymbolicCallee->getValueType(0));
6610 // Get the real number of arguments participating in the call <numArgs>
6611 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6612 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6614 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6615 // Intrinsics include all meta-operands up to but not including CC.
6616 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6617 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6618 "Not enough arguments provided to the patchpoint intrinsic");
6620 // For AnyRegCC the arguments are lowered later on manually.
6621 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6623 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6624 std::pair<SDValue, SDValue> Result =
6625 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6628 SDNode *CallEnd = Result.second.getNode();
6629 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6630 CallEnd = CallEnd->getOperand(0).getNode();
6632 /// Get a call instruction from the call sequence chain.
6633 /// Tail calls are not allowed.
6634 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6635 "Expected a callseq node.");
6636 SDNode *Call = CallEnd->getOperand(0).getNode();
6637 bool HasGlue = Call->getGluedNode();
6639 // Replace the target specific call node with the patchable intrinsic.
6640 SmallVector<SDValue, 8> Ops;
6642 // Add the <id> and <numBytes> constants.
6643 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6644 Ops.push_back(DAG.getTargetConstant(
6645 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6646 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6647 Ops.push_back(DAG.getTargetConstant(
6648 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6652 Ops.push_back(Callee);
6654 // Adjust <numArgs> to account for any arguments that have been passed on the
6656 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6657 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6658 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6659 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6661 // Add the calling convention
6662 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6664 // Add the arguments we omitted previously. The register allocator should
6665 // place these in any free register.
6667 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6668 Ops.push_back(getValue(CS.getArgument(i)));
6670 // Push the arguments from the call instruction up to the register mask.
6671 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6672 Ops.append(Call->op_begin() + 2, e);
6674 // Push live variables for the stack map.
6675 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6677 // Push the register mask info.
6679 Ops.push_back(*(Call->op_end()-2));
6681 Ops.push_back(*(Call->op_end()-1));
6683 // Push the chain (this is originally the first operand of the call, but
6684 // becomes now the last or second to last operand).
6685 Ops.push_back(*(Call->op_begin()));
6687 // Push the glue flag (last operand).
6689 Ops.push_back(*(Call->op_end()-1));
6692 if (IsAnyRegCC && HasDef) {
6693 // Create the return types based on the intrinsic definition
6694 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6695 SmallVector<EVT, 3> ValueVTs;
6696 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6697 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6699 // There is always a chain and a glue type at the end
6700 ValueVTs.push_back(MVT::Other);
6701 ValueVTs.push_back(MVT::Glue);
6702 NodeTys = DAG.getVTList(ValueVTs);
6704 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6706 // Replace the target specific call node with a PATCHPOINT node.
6707 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6710 // Update the NodeMap.
6713 setValue(CS.getInstruction(), SDValue(MN, 0));
6715 setValue(CS.getInstruction(), Result.first);
6718 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6719 // call sequence. Furthermore the location of the chain and glue can change
6720 // when the AnyReg calling convention is used and the intrinsic returns a
6722 if (IsAnyRegCC && HasDef) {
6723 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6724 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6725 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6727 DAG.ReplaceAllUsesWith(Call, MN);
6728 DAG.DeleteNode(Call);
6730 // Inform the Frame Information that we have a patchpoint in this function.
6731 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6734 /// Returns an AttributeSet representing the attributes applied to the return
6735 /// value of the given call.
6736 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6737 SmallVector<Attribute::AttrKind, 2> Attrs;
6739 Attrs.push_back(Attribute::SExt);
6741 Attrs.push_back(Attribute::ZExt);
6743 Attrs.push_back(Attribute::InReg);
6745 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6749 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6750 /// implementation, which just calls LowerCall.
6751 /// FIXME: When all targets are
6752 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6753 std::pair<SDValue, SDValue>
6754 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6755 // Handle the incoming return values from the call.
6757 Type *OrigRetTy = CLI.RetTy;
6758 SmallVector<EVT, 4> RetTys;
6759 SmallVector<uint64_t, 4> Offsets;
6760 auto &DL = CLI.DAG.getDataLayout();
6761 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6763 SmallVector<ISD::OutputArg, 4> Outs;
6764 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6766 bool CanLowerReturn =
6767 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6768 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6770 SDValue DemoteStackSlot;
6771 int DemoteStackIdx = -100;
6772 if (!CanLowerReturn) {
6773 // FIXME: equivalent assert?
6774 // assert(!CS.hasInAllocaArgument() &&
6775 // "sret demotion is incompatible with inalloca");
6776 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6777 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6778 MachineFunction &MF = CLI.DAG.getMachineFunction();
6779 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6780 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6782 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6784 Entry.Node = DemoteStackSlot;
6785 Entry.Ty = StackSlotPtrType;
6786 Entry.isSExt = false;
6787 Entry.isZExt = false;
6788 Entry.isInReg = false;
6789 Entry.isSRet = true;
6790 Entry.isNest = false;
6791 Entry.isByVal = false;
6792 Entry.isReturned = false;
6793 Entry.Alignment = Align;
6794 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6795 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6797 // sret demotion isn't compatible with tail-calls, since the sret argument
6798 // points into the callers stack frame.
6799 CLI.IsTailCall = false;
6801 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6803 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6804 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6805 for (unsigned i = 0; i != NumRegs; ++i) {
6806 ISD::InputArg MyFlags;
6807 MyFlags.VT = RegisterVT;
6809 MyFlags.Used = CLI.IsReturnValueUsed;
6811 MyFlags.Flags.setSExt();
6813 MyFlags.Flags.setZExt();
6815 MyFlags.Flags.setInReg();
6816 CLI.Ins.push_back(MyFlags);
6821 // Handle all of the outgoing arguments.
6823 CLI.OutVals.clear();
6824 ArgListTy &Args = CLI.getArgs();
6825 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6826 SmallVector<EVT, 4> ValueVTs;
6827 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6828 Type *FinalType = Args[i].Ty;
6829 if (Args[i].isByVal)
6830 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6831 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6832 FinalType, CLI.CallConv, CLI.IsVarArg);
6833 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6835 EVT VT = ValueVTs[Value];
6836 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6837 SDValue Op = SDValue(Args[i].Node.getNode(),
6838 Args[i].Node.getResNo() + Value);
6839 ISD::ArgFlagsTy Flags;
6840 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6846 if (Args[i].isInReg)
6850 if (Args[i].isByVal)
6852 if (Args[i].isInAlloca) {
6853 Flags.setInAlloca();
6854 // Set the byval flag for CCAssignFn callbacks that don't know about
6855 // inalloca. This way we can know how many bytes we should've allocated
6856 // and how many bytes a callee cleanup function will pop. If we port
6857 // inalloca to more targets, we'll have to add custom inalloca handling
6858 // in the various CC lowering callbacks.
6861 if (Args[i].isByVal || Args[i].isInAlloca) {
6862 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6863 Type *ElementTy = Ty->getElementType();
6864 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6865 // For ByVal, alignment should come from FE. BE will guess if this
6866 // info is not there but there are cases it cannot get right.
6867 unsigned FrameAlign;
6868 if (Args[i].Alignment)
6869 FrameAlign = Args[i].Alignment;
6871 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6872 Flags.setByValAlign(FrameAlign);
6877 Flags.setInConsecutiveRegs();
6878 Flags.setOrigAlign(OriginalAlignment);
6880 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6881 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6882 SmallVector<SDValue, 4> Parts(NumParts);
6883 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6886 ExtendKind = ISD::SIGN_EXTEND;
6887 else if (Args[i].isZExt)
6888 ExtendKind = ISD::ZERO_EXTEND;
6890 // Conservatively only handle 'returned' on non-vectors for now
6891 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6892 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6893 "unexpected use of 'returned'");
6894 // Before passing 'returned' to the target lowering code, ensure that
6895 // either the register MVT and the actual EVT are the same size or that
6896 // the return value and argument are extended in the same way; in these
6897 // cases it's safe to pass the argument register value unchanged as the
6898 // return register value (although it's at the target's option whether
6900 // TODO: allow code generation to take advantage of partially preserved
6901 // registers rather than clobbering the entire register when the
6902 // parameter extension method is not compatible with the return
6904 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6905 (ExtendKind != ISD::ANY_EXTEND &&
6906 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6907 Flags.setReturned();
6910 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6911 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6913 for (unsigned j = 0; j != NumParts; ++j) {
6914 // if it isn't first piece, alignment must be 1
6915 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6916 i < CLI.NumFixedArgs,
6917 i, j*Parts[j].getValueType().getStoreSize());
6918 if (NumParts > 1 && j == 0)
6919 MyFlags.Flags.setSplit();
6921 MyFlags.Flags.setOrigAlign(1);
6923 CLI.Outs.push_back(MyFlags);
6924 CLI.OutVals.push_back(Parts[j]);
6927 if (NeedsRegBlock && Value == NumValues - 1)
6928 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6932 SmallVector<SDValue, 4> InVals;
6933 CLI.Chain = LowerCall(CLI, InVals);
6935 // Verify that the target's LowerCall behaved as expected.
6936 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6937 "LowerCall didn't return a valid chain!");
6938 assert((!CLI.IsTailCall || InVals.empty()) &&
6939 "LowerCall emitted a return value for a tail call!");
6940 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6941 "LowerCall didn't emit the correct number of values!");
6943 // For a tail call, the return value is merely live-out and there aren't
6944 // any nodes in the DAG representing it. Return a special value to
6945 // indicate that a tail call has been emitted and no more Instructions
6946 // should be processed in the current block.
6947 if (CLI.IsTailCall) {
6948 CLI.DAG.setRoot(CLI.Chain);
6949 return std::make_pair(SDValue(), SDValue());
6952 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6953 assert(InVals[i].getNode() &&
6954 "LowerCall emitted a null value!");
6955 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6956 "LowerCall emitted a value with the wrong type!");
6959 SmallVector<SDValue, 4> ReturnValues;
6960 if (!CanLowerReturn) {
6961 // The instruction result is the result of loading from the
6962 // hidden sret parameter.
6963 SmallVector<EVT, 1> PVTs;
6964 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6966 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
6967 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6968 EVT PtrVT = PVTs[0];
6970 unsigned NumValues = RetTys.size();
6971 ReturnValues.resize(NumValues);
6972 SmallVector<SDValue, 4> Chains(NumValues);
6974 for (unsigned i = 0; i < NumValues; ++i) {
6975 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6976 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6978 SDValue L = CLI.DAG.getLoad(
6979 RetTys[i], CLI.DL, CLI.Chain, Add,
6980 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6982 ReturnValues[i] = L;
6983 Chains[i] = L.getValue(1);
6986 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6988 // Collect the legal value parts into potentially illegal values
6989 // that correspond to the original function's return values.
6990 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6992 AssertOp = ISD::AssertSext;
6993 else if (CLI.RetZExt)
6994 AssertOp = ISD::AssertZext;
6995 unsigned CurReg = 0;
6996 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6998 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6999 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7001 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7002 NumRegs, RegisterVT, VT, nullptr,
7007 // For a function returning void, there is no return value. We can't create
7008 // such a node, so we just return a null return value in that case. In
7009 // that case, nothing will actually look at the value.
7010 if (ReturnValues.empty())
7011 return std::make_pair(SDValue(), CLI.Chain);
7014 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7015 CLI.DAG.getVTList(RetTys), ReturnValues);
7016 return std::make_pair(Res, CLI.Chain);
7019 void TargetLowering::LowerOperationWrapper(SDNode *N,
7020 SmallVectorImpl<SDValue> &Results,
7021 SelectionDAG &DAG) const {
7022 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7024 Results.push_back(Res);
7027 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7028 llvm_unreachable("LowerOperation not implemented for this target!");
7032 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7033 SDValue Op = getNonRegisterValue(V);
7034 assert((Op.getOpcode() != ISD::CopyFromReg ||
7035 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7036 "Copy from a reg to the same reg!");
7037 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7040 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7042 SDValue Chain = DAG.getEntryNode();
7044 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7045 FuncInfo.PreferredExtendType.end())
7047 : FuncInfo.PreferredExtendType[V];
7048 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7049 PendingExports.push_back(Chain);
7052 #include "llvm/CodeGen/SelectionDAGISel.h"
7054 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7055 /// entry block, return true. This includes arguments used by switches, since
7056 /// the switch may expand into multiple basic blocks.
7057 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7058 // With FastISel active, we may be splitting blocks, so force creation
7059 // of virtual registers for all non-dead arguments.
7061 return A->use_empty();
7063 const BasicBlock *Entry = A->getParent()->begin();
7064 for (const User *U : A->users())
7065 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7066 return false; // Use not in entry block.
7071 void SelectionDAGISel::LowerArguments(const Function &F) {
7072 SelectionDAG &DAG = SDB->DAG;
7073 SDLoc dl = SDB->getCurSDLoc();
7074 const DataLayout &DL = DAG.getDataLayout();
7075 SmallVector<ISD::InputArg, 16> Ins;
7077 if (!FuncInfo->CanLowerReturn) {
7078 // Put in an sret pointer parameter before all the other parameters.
7079 SmallVector<EVT, 1> ValueVTs;
7080 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7081 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7083 // NOTE: Assuming that a pointer will never break down to more than one VT
7085 ISD::ArgFlagsTy Flags;
7087 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7088 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7089 ISD::InputArg::NoArgIndex, 0);
7090 Ins.push_back(RetArg);
7093 // Set up the incoming argument description vector.
7095 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7096 I != E; ++I, ++Idx) {
7097 SmallVector<EVT, 4> ValueVTs;
7098 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7099 bool isArgValueUsed = !I->use_empty();
7100 unsigned PartBase = 0;
7101 Type *FinalType = I->getType();
7102 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7103 FinalType = cast<PointerType>(FinalType)->getElementType();
7104 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7105 FinalType, F.getCallingConv(), F.isVarArg());
7106 for (unsigned Value = 0, NumValues = ValueVTs.size();
7107 Value != NumValues; ++Value) {
7108 EVT VT = ValueVTs[Value];
7109 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7110 ISD::ArgFlagsTy Flags;
7111 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7113 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7115 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7117 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7119 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7121 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7123 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7124 Flags.setInAlloca();
7125 // Set the byval flag for CCAssignFn callbacks that don't know about
7126 // inalloca. This way we can know how many bytes we should've allocated
7127 // and how many bytes a callee cleanup function will pop. If we port
7128 // inalloca to more targets, we'll have to add custom inalloca handling
7129 // in the various CC lowering callbacks.
7132 if (Flags.isByVal() || Flags.isInAlloca()) {
7133 PointerType *Ty = cast<PointerType>(I->getType());
7134 Type *ElementTy = Ty->getElementType();
7135 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7136 // For ByVal, alignment should be passed from FE. BE will guess if
7137 // this info is not there but there are cases it cannot get right.
7138 unsigned FrameAlign;
7139 if (F.getParamAlignment(Idx))
7140 FrameAlign = F.getParamAlignment(Idx);
7142 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7143 Flags.setByValAlign(FrameAlign);
7145 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7148 Flags.setInConsecutiveRegs();
7149 Flags.setOrigAlign(OriginalAlignment);
7151 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7152 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7153 for (unsigned i = 0; i != NumRegs; ++i) {
7154 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7155 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7156 if (NumRegs > 1 && i == 0)
7157 MyFlags.Flags.setSplit();
7158 // if it isn't first piece, alignment must be 1
7160 MyFlags.Flags.setOrigAlign(1);
7161 Ins.push_back(MyFlags);
7163 if (NeedsRegBlock && Value == NumValues - 1)
7164 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7165 PartBase += VT.getStoreSize();
7169 // Call the target to set up the argument values.
7170 SmallVector<SDValue, 8> InVals;
7171 SDValue NewRoot = TLI->LowerFormalArguments(
7172 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7174 // Verify that the target's LowerFormalArguments behaved as expected.
7175 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7176 "LowerFormalArguments didn't return a valid chain!");
7177 assert(InVals.size() == Ins.size() &&
7178 "LowerFormalArguments didn't emit the correct number of values!");
7180 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7181 assert(InVals[i].getNode() &&
7182 "LowerFormalArguments emitted a null value!");
7183 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7184 "LowerFormalArguments emitted a value with the wrong type!");
7188 // Update the DAG with the new chain value resulting from argument lowering.
7189 DAG.setRoot(NewRoot);
7191 // Set up the argument values.
7194 if (!FuncInfo->CanLowerReturn) {
7195 // Create a virtual register for the sret pointer, and put in a copy
7196 // from the sret argument into it.
7197 SmallVector<EVT, 1> ValueVTs;
7198 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7199 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7200 MVT VT = ValueVTs[0].getSimpleVT();
7201 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7202 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7203 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7204 RegVT, VT, nullptr, AssertOp);
7206 MachineFunction& MF = SDB->DAG.getMachineFunction();
7207 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7208 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7209 FuncInfo->DemoteRegister = SRetReg;
7211 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7212 DAG.setRoot(NewRoot);
7214 // i indexes lowered arguments. Bump it past the hidden sret argument.
7215 // Idx indexes LLVM arguments. Don't touch it.
7219 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7221 SmallVector<SDValue, 4> ArgValues;
7222 SmallVector<EVT, 4> ValueVTs;
7223 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7224 unsigned NumValues = ValueVTs.size();
7226 // If this argument is unused then remember its value. It is used to generate
7227 // debugging information.
7228 if (I->use_empty() && NumValues) {
7229 SDB->setUnusedArgValue(I, InVals[i]);
7231 // Also remember any frame index for use in FastISel.
7232 if (FrameIndexSDNode *FI =
7233 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7234 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7237 for (unsigned Val = 0; Val != NumValues; ++Val) {
7238 EVT VT = ValueVTs[Val];
7239 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7240 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7242 if (!I->use_empty()) {
7243 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7244 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7245 AssertOp = ISD::AssertSext;
7246 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7247 AssertOp = ISD::AssertZext;
7249 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7250 NumParts, PartVT, VT,
7251 nullptr, AssertOp));
7257 // We don't need to do anything else for unused arguments.
7258 if (ArgValues.empty())
7261 // Note down frame index.
7262 if (FrameIndexSDNode *FI =
7263 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7264 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7266 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7267 SDB->getCurSDLoc());
7269 SDB->setValue(I, Res);
7270 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7271 if (LoadSDNode *LNode =
7272 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7273 if (FrameIndexSDNode *FI =
7274 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7275 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7278 // If this argument is live outside of the entry block, insert a copy from
7279 // wherever we got it to the vreg that other BB's will reference it as.
7280 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7281 // If we can, though, try to skip creating an unnecessary vreg.
7282 // FIXME: This isn't very clean... it would be nice to make this more
7283 // general. It's also subtly incompatible with the hacks FastISel
7285 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7286 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7287 FuncInfo->ValueMap[I] = Reg;
7291 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7292 FuncInfo->InitializeRegForValue(I);
7293 SDB->CopyToExportRegsIfNeeded(I);
7297 assert(i == InVals.size() && "Argument register count mismatch!");
7299 // Finally, if the target has anything special to do, allow it to do so.
7300 EmitFunctionEntryCode();
7303 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7304 /// ensure constants are generated when needed. Remember the virtual registers
7305 /// that need to be added to the Machine PHI nodes as input. We cannot just
7306 /// directly add them, because expansion might result in multiple MBB's for one
7307 /// BB. As such, the start of the BB might correspond to a different MBB than
7311 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7312 const TerminatorInst *TI = LLVMBB->getTerminator();
7314 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7316 // Check PHI nodes in successors that expect a value to be available from this
7318 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7319 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7320 if (!isa<PHINode>(SuccBB->begin())) continue;
7321 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7323 // If this terminator has multiple identical successors (common for
7324 // switches), only handle each succ once.
7325 if (!SuccsHandled.insert(SuccMBB).second)
7328 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7330 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7331 // nodes and Machine PHI nodes, but the incoming operands have not been
7333 for (BasicBlock::const_iterator I = SuccBB->begin();
7334 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7335 // Ignore dead phi's.
7336 if (PN->use_empty()) continue;
7339 if (PN->getType()->isEmptyTy())
7343 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7345 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7346 unsigned &RegOut = ConstantsOut[C];
7348 RegOut = FuncInfo.CreateRegs(C->getType());
7349 CopyValueToVirtualRegister(C, RegOut);
7353 DenseMap<const Value *, unsigned>::iterator I =
7354 FuncInfo.ValueMap.find(PHIOp);
7355 if (I != FuncInfo.ValueMap.end())
7358 assert(isa<AllocaInst>(PHIOp) &&
7359 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7360 "Didn't codegen value into a register!??");
7361 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7362 CopyValueToVirtualRegister(PHIOp, Reg);
7366 // Remember that this register needs to added to the machine PHI node as
7367 // the input for this MBB.
7368 SmallVector<EVT, 4> ValueVTs;
7369 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7370 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7371 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7372 EVT VT = ValueVTs[vti];
7373 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7374 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7375 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7376 Reg += NumRegisters;
7381 ConstantsOut.clear();
7384 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7387 SelectionDAGBuilder::StackProtectorDescriptor::
7388 AddSuccessorMBB(const BasicBlock *BB,
7389 MachineBasicBlock *ParentMBB,
7391 MachineBasicBlock *SuccMBB) {
7392 // If SuccBB has not been created yet, create it.
7394 MachineFunction *MF = ParentMBB->getParent();
7395 MachineFunction::iterator BBI = ParentMBB;
7396 SuccMBB = MF->CreateMachineBasicBlock(BB);
7397 MF->insert(++BBI, SuccMBB);
7399 // Add it as a successor of ParentMBB.
7400 ParentMBB->addSuccessor(
7401 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7405 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7406 MachineFunction::iterator I = MBB;
7407 if (++I == FuncInfo.MF->end())
7412 /// During lowering new call nodes can be created (such as memset, etc.).
7413 /// Those will become new roots of the current DAG, but complications arise
7414 /// when they are tail calls. In such cases, the call lowering will update
7415 /// the root, but the builder still needs to know that a tail call has been
7416 /// lowered in order to avoid generating an additional return.
7417 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7418 // If the node is null, we do have a tail call.
7419 if (MaybeTC.getNode() != nullptr)
7420 DAG.setRoot(MaybeTC);
7425 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7426 unsigned *TotalCases, unsigned First,
7428 assert(Last >= First);
7429 assert(TotalCases[Last] >= TotalCases[First]);
7431 APInt LowCase = Clusters[First].Low->getValue();
7432 APInt HighCase = Clusters[Last].High->getValue();
7433 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7435 // FIXME: A range of consecutive cases has 100% density, but only requires one
7436 // comparison to lower. We should discriminate against such consecutive ranges
7439 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7440 uint64_t Range = Diff + 1;
7443 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7445 assert(NumCases < UINT64_MAX / 100);
7446 assert(Range >= NumCases);
7448 return NumCases * 100 >= Range * MinJumpTableDensity;
7451 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7452 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7453 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7456 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7457 unsigned First, unsigned Last,
7458 const SwitchInst *SI,
7459 MachineBasicBlock *DefaultMBB,
7460 CaseCluster &JTCluster) {
7461 assert(First <= Last);
7463 uint32_t Weight = 0;
7464 unsigned NumCmps = 0;
7465 std::vector<MachineBasicBlock*> Table;
7466 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7467 for (unsigned I = First; I <= Last; ++I) {
7468 assert(Clusters[I].Kind == CC_Range);
7469 Weight += Clusters[I].Weight;
7470 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7471 APInt Low = Clusters[I].Low->getValue();
7472 APInt High = Clusters[I].High->getValue();
7473 NumCmps += (Low == High) ? 1 : 2;
7475 // Fill the gap between this and the previous cluster.
7476 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7477 assert(PreviousHigh.slt(Low));
7478 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7479 for (uint64_t J = 0; J < Gap; J++)
7480 Table.push_back(DefaultMBB);
7482 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7483 for (uint64_t J = 0; J < ClusterSize; ++J)
7484 Table.push_back(Clusters[I].MBB);
7485 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7488 unsigned NumDests = JTWeights.size();
7489 if (isSuitableForBitTests(NumDests, NumCmps,
7490 Clusters[First].Low->getValue(),
7491 Clusters[Last].High->getValue())) {
7492 // Clusters[First..Last] should be lowered as bit tests instead.
7496 // Create the MBB that will load from and jump through the table.
7497 // Note: We create it here, but it's not inserted into the function yet.
7498 MachineFunction *CurMF = FuncInfo.MF;
7499 MachineBasicBlock *JumpTableMBB =
7500 CurMF->CreateMachineBasicBlock(SI->getParent());
7502 // Add successors. Note: use table order for determinism.
7503 SmallPtrSet<MachineBasicBlock *, 8> Done;
7504 for (MachineBasicBlock *Succ : Table) {
7505 if (Done.count(Succ))
7507 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7511 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7512 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7513 ->createJumpTableIndex(Table);
7515 // Set up the jump table info.
7516 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7517 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7518 Clusters[Last].High->getValue(), SI->getCondition(),
7520 JTCases.emplace_back(std::move(JTH), std::move(JT));
7522 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7523 JTCases.size() - 1, Weight);
7527 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7528 const SwitchInst *SI,
7529 MachineBasicBlock *DefaultMBB) {
7531 // Clusters must be non-empty, sorted, and only contain Range clusters.
7532 assert(!Clusters.empty());
7533 for (CaseCluster &C : Clusters)
7534 assert(C.Kind == CC_Range);
7535 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7536 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7540 if (!areJTsAllowed(TLI))
7543 const int64_t N = Clusters.size();
7544 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7546 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7547 SmallVector<unsigned, 8> TotalCases(N);
7549 for (unsigned i = 0; i < N; ++i) {
7550 APInt Hi = Clusters[i].High->getValue();
7551 APInt Lo = Clusters[i].Low->getValue();
7552 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7554 TotalCases[i] += TotalCases[i - 1];
7557 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7558 // Cheap case: the whole range might be suitable for jump table.
7559 CaseCluster JTCluster;
7560 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7561 Clusters[0] = JTCluster;
7567 // The algorithm below is not suitable for -O0.
7568 if (TM.getOptLevel() == CodeGenOpt::None)
7571 // Split Clusters into minimum number of dense partitions. The algorithm uses
7572 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7573 // for the Case Statement'" (1994), but builds the MinPartitions array in
7574 // reverse order to make it easier to reconstruct the partitions in ascending
7575 // order. In the choice between two optimal partitionings, it picks the one
7576 // which yields more jump tables.
7578 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7579 SmallVector<unsigned, 8> MinPartitions(N);
7580 // LastElement[i] is the last element of the partition starting at i.
7581 SmallVector<unsigned, 8> LastElement(N);
7582 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7583 SmallVector<unsigned, 8> NumTables(N);
7585 // Base case: There is only one way to partition Clusters[N-1].
7586 MinPartitions[N - 1] = 1;
7587 LastElement[N - 1] = N - 1;
7588 assert(MinJumpTableSize > 1);
7589 NumTables[N - 1] = 0;
7591 // Note: loop indexes are signed to avoid underflow.
7592 for (int64_t i = N - 2; i >= 0; i--) {
7593 // Find optimal partitioning of Clusters[i..N-1].
7594 // Baseline: Put Clusters[i] into a partition on its own.
7595 MinPartitions[i] = MinPartitions[i + 1] + 1;
7597 NumTables[i] = NumTables[i + 1];
7599 // Search for a solution that results in fewer partitions.
7600 for (int64_t j = N - 1; j > i; j--) {
7601 // Try building a partition from Clusters[i..j].
7602 if (isDense(Clusters, &TotalCases[0], i, j)) {
7603 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7604 bool IsTable = j - i + 1 >= MinJumpTableSize;
7605 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7607 // If this j leads to fewer partitions, or same number of partitions
7608 // with more lookup tables, it is a better partitioning.
7609 if (NumPartitions < MinPartitions[i] ||
7610 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7611 MinPartitions[i] = NumPartitions;
7613 NumTables[i] = Tables;
7619 // Iterate over the partitions, replacing some with jump tables in-place.
7620 unsigned DstIndex = 0;
7621 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7622 Last = LastElement[First];
7623 assert(Last >= First);
7624 assert(DstIndex <= First);
7625 unsigned NumClusters = Last - First + 1;
7627 CaseCluster JTCluster;
7628 if (NumClusters >= MinJumpTableSize &&
7629 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7630 Clusters[DstIndex++] = JTCluster;
7632 for (unsigned I = First; I <= Last; ++I)
7633 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7636 Clusters.resize(DstIndex);
7639 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7640 // FIXME: Using the pointer type doesn't seem ideal.
7641 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7642 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7646 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7649 const APInt &High) {
7650 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7651 // range of cases both require only one branch to lower. Just looking at the
7652 // number of clusters and destinations should be enough to decide whether to
7655 // To lower a range with bit tests, the range must fit the bitwidth of a
7657 if (!rangeFitsInWord(Low, High))
7660 // Decide whether it's profitable to lower this range with bit tests. Each
7661 // destination requires a bit test and branch, and there is an overall range
7662 // check branch. For a small number of clusters, separate comparisons might be
7663 // cheaper, and for many destinations, splitting the range might be better.
7664 return (NumDests == 1 && NumCmps >= 3) ||
7665 (NumDests == 2 && NumCmps >= 5) ||
7666 (NumDests == 3 && NumCmps >= 6);
7669 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7670 unsigned First, unsigned Last,
7671 const SwitchInst *SI,
7672 CaseCluster &BTCluster) {
7673 assert(First <= Last);
7677 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7678 unsigned NumCmps = 0;
7679 for (int64_t I = First; I <= Last; ++I) {
7680 assert(Clusters[I].Kind == CC_Range);
7681 Dests.set(Clusters[I].MBB->getNumber());
7682 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7684 unsigned NumDests = Dests.count();
7686 APInt Low = Clusters[First].Low->getValue();
7687 APInt High = Clusters[Last].High->getValue();
7688 assert(Low.slt(High));
7690 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7696 const int BitWidth = DAG.getTargetLoweringInfo()
7697 .getPointerTy(DAG.getDataLayout())
7699 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7701 if (Low.isNonNegative() && High.slt(BitWidth)) {
7702 // Optimize the case where all the case values fit in a
7703 // word without having to subtract minValue. In this case,
7704 // we can optimize away the subtraction.
7705 LowBound = APInt::getNullValue(Low.getBitWidth());
7709 CmpRange = High - Low;
7713 uint32_t TotalWeight = 0;
7714 for (unsigned i = First; i <= Last; ++i) {
7715 // Find the CaseBits for this destination.
7717 for (j = 0; j < CBV.size(); ++j)
7718 if (CBV[j].BB == Clusters[i].MBB)
7720 if (j == CBV.size())
7721 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7722 CaseBits *CB = &CBV[j];
7724 // Update Mask, Bits and ExtraWeight.
7725 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7726 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7727 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7728 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7729 CB->Bits += Hi - Lo + 1;
7730 CB->ExtraWeight += Clusters[i].Weight;
7731 TotalWeight += Clusters[i].Weight;
7732 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7736 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7737 // Sort by weight first, number of bits second.
7738 if (a.ExtraWeight != b.ExtraWeight)
7739 return a.ExtraWeight > b.ExtraWeight;
7740 return a.Bits > b.Bits;
7743 for (auto &CB : CBV) {
7744 MachineBasicBlock *BitTestBB =
7745 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7746 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7748 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7749 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7750 nullptr, std::move(BTI));
7752 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7753 BitTestCases.size() - 1, TotalWeight);
7757 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7758 const SwitchInst *SI) {
7759 // Partition Clusters into as few subsets as possible, where each subset has a
7760 // range that fits in a machine word and has <= 3 unique destinations.
7763 // Clusters must be sorted and contain Range or JumpTable clusters.
7764 assert(!Clusters.empty());
7765 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7766 for (const CaseCluster &C : Clusters)
7767 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7768 for (unsigned i = 1; i < Clusters.size(); ++i)
7769 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7772 // The algorithm below is not suitable for -O0.
7773 if (TM.getOptLevel() == CodeGenOpt::None)
7776 // If target does not have legal shift left, do not emit bit tests at all.
7777 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7778 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7779 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7782 int BitWidth = PTy.getSizeInBits();
7783 const int64_t N = Clusters.size();
7785 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7786 SmallVector<unsigned, 8> MinPartitions(N);
7787 // LastElement[i] is the last element of the partition starting at i.
7788 SmallVector<unsigned, 8> LastElement(N);
7790 // FIXME: This might not be the best algorithm for finding bit test clusters.
7792 // Base case: There is only one way to partition Clusters[N-1].
7793 MinPartitions[N - 1] = 1;
7794 LastElement[N - 1] = N - 1;
7796 // Note: loop indexes are signed to avoid underflow.
7797 for (int64_t i = N - 2; i >= 0; --i) {
7798 // Find optimal partitioning of Clusters[i..N-1].
7799 // Baseline: Put Clusters[i] into a partition on its own.
7800 MinPartitions[i] = MinPartitions[i + 1] + 1;
7803 // Search for a solution that results in fewer partitions.
7804 // Note: the search is limited by BitWidth, reducing time complexity.
7805 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7806 // Try building a partition from Clusters[i..j].
7809 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7810 Clusters[j].High->getValue()))
7813 // Check nbr of destinations and cluster types.
7814 // FIXME: This works, but doesn't seem very efficient.
7815 bool RangesOnly = true;
7816 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7817 for (int64_t k = i; k <= j; k++) {
7818 if (Clusters[k].Kind != CC_Range) {
7822 Dests.set(Clusters[k].MBB->getNumber());
7824 if (!RangesOnly || Dests.count() > 3)
7827 // Check if it's a better partition.
7828 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7829 if (NumPartitions < MinPartitions[i]) {
7830 // Found a better partition.
7831 MinPartitions[i] = NumPartitions;
7837 // Iterate over the partitions, replacing with bit-test clusters in-place.
7838 unsigned DstIndex = 0;
7839 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7840 Last = LastElement[First];
7841 assert(First <= Last);
7842 assert(DstIndex <= First);
7844 CaseCluster BitTestCluster;
7845 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7846 Clusters[DstIndex++] = BitTestCluster;
7848 size_t NumClusters = Last - First + 1;
7849 std::memmove(&Clusters[DstIndex], &Clusters[First],
7850 sizeof(Clusters[0]) * NumClusters);
7851 DstIndex += NumClusters;
7854 Clusters.resize(DstIndex);
7857 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7858 MachineBasicBlock *SwitchMBB,
7859 MachineBasicBlock *DefaultMBB) {
7860 MachineFunction *CurMF = FuncInfo.MF;
7861 MachineBasicBlock *NextMBB = nullptr;
7862 MachineFunction::iterator BBI = W.MBB;
7863 if (++BBI != FuncInfo.MF->end())
7866 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7868 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7870 if (Size == 2 && W.MBB == SwitchMBB) {
7871 // If any two of the cases has the same destination, and if one value
7872 // is the same as the other, but has one bit unset that the other has set,
7873 // use bit manipulation to do two compares at once. For example:
7874 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7875 // TODO: This could be extended to merge any 2 cases in switches with 3
7877 // TODO: Handle cases where W.CaseBB != SwitchBB.
7878 CaseCluster &Small = *W.FirstCluster;
7879 CaseCluster &Big = *W.LastCluster;
7881 if (Small.Low == Small.High && Big.Low == Big.High &&
7882 Small.MBB == Big.MBB) {
7883 const APInt &SmallValue = Small.Low->getValue();
7884 const APInt &BigValue = Big.Low->getValue();
7886 // Check that there is only one bit different.
7887 APInt CommonBit = BigValue ^ SmallValue;
7888 if (CommonBit.isPowerOf2()) {
7889 SDValue CondLHS = getValue(Cond);
7890 EVT VT = CondLHS.getValueType();
7891 SDLoc DL = getCurSDLoc();
7893 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7894 DAG.getConstant(CommonBit, DL, VT));
7895 SDValue Cond = DAG.getSetCC(
7896 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7899 // Update successor info.
7900 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7901 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7902 addSuccessorWithWeight(
7903 SwitchMBB, DefaultMBB,
7904 // The default destination is the first successor in IR.
7905 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7908 // Insert the true branch.
7910 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7911 DAG.getBasicBlock(Small.MBB));
7912 // Insert the false branch.
7913 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7914 DAG.getBasicBlock(DefaultMBB));
7916 DAG.setRoot(BrCond);
7922 if (TM.getOptLevel() != CodeGenOpt::None) {
7923 // Order cases by weight so the most likely case will be checked first.
7924 std::sort(W.FirstCluster, W.LastCluster + 1,
7925 [](const CaseCluster &a, const CaseCluster &b) {
7926 return a.Weight > b.Weight;
7929 // Rearrange the case blocks so that the last one falls through if possible
7930 // without without changing the order of weights.
7931 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7933 if (I->Weight > W.LastCluster->Weight)
7935 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7936 std::swap(*I, *W.LastCluster);
7942 // Compute total weight.
7943 uint32_t UnhandledWeights = 0;
7944 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7945 UnhandledWeights += I->Weight;
7946 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7949 MachineBasicBlock *CurMBB = W.MBB;
7950 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7951 MachineBasicBlock *Fallthrough;
7952 if (I == W.LastCluster) {
7953 // For the last cluster, fall through to the default destination.
7954 Fallthrough = DefaultMBB;
7956 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7957 CurMF->insert(BBI, Fallthrough);
7958 // Put Cond in a virtual register to make it available from the new blocks.
7959 ExportFromCurrentBlock(Cond);
7963 case CC_JumpTable: {
7964 // FIXME: Optimize away range check based on pivot comparisons.
7965 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7966 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7968 // The jump block hasn't been inserted yet; insert it here.
7969 MachineBasicBlock *JumpMBB = JT->MBB;
7970 CurMF->insert(BBI, JumpMBB);
7971 addSuccessorWithWeight(CurMBB, Fallthrough);
7972 addSuccessorWithWeight(CurMBB, JumpMBB);
7974 // The jump table header will be inserted in our current block, do the
7975 // range check, and fall through to our fallthrough block.
7976 JTH->HeaderBB = CurMBB;
7977 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7979 // If we're in the right place, emit the jump table header right now.
7980 if (CurMBB == SwitchMBB) {
7981 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7982 JTH->Emitted = true;
7987 // FIXME: Optimize away range check based on pivot comparisons.
7988 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7990 // The bit test blocks haven't been inserted yet; insert them here.
7991 for (BitTestCase &BTC : BTB->Cases)
7992 CurMF->insert(BBI, BTC.ThisBB);
7994 // Fill in fields of the BitTestBlock.
7995 BTB->Parent = CurMBB;
7996 BTB->Default = Fallthrough;
7998 // If we're in the right place, emit the bit test header header right now.
7999 if (CurMBB ==SwitchMBB) {
8000 visitBitTestHeader(*BTB, SwitchMBB);
8001 BTB->Emitted = true;
8006 const Value *RHS, *LHS, *MHS;
8008 if (I->Low == I->High) {
8009 // Check Cond == I->Low.
8015 // Check I->Low <= Cond <= I->High.
8022 // The false weight is the sum of all unhandled cases.
8023 UnhandledWeights -= I->Weight;
8024 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8027 if (CurMBB == SwitchMBB)
8028 visitSwitchCase(CB, SwitchMBB);
8030 SwitchCases.push_back(CB);
8035 CurMBB = Fallthrough;
8039 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8040 CaseClusterIt First,
8041 CaseClusterIt Last) {
8042 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8043 if (X.Weight != CC.Weight)
8044 return X.Weight > CC.Weight;
8046 // Ties are broken by comparing the case value.
8047 return X.Low->getValue().slt(CC.Low->getValue());
8051 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8052 const SwitchWorkListItem &W,
8054 MachineBasicBlock *SwitchMBB) {
8055 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8056 "Clusters not sorted?");
8058 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8060 // Balance the tree based on branch weights to create a near-optimal (in terms
8061 // of search time given key frequency) binary search tree. See e.g. Kurt
8062 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8063 CaseClusterIt LastLeft = W.FirstCluster;
8064 CaseClusterIt FirstRight = W.LastCluster;
8065 uint32_t LeftWeight = LastLeft->Weight;
8066 uint32_t RightWeight = FirstRight->Weight;
8068 // Move LastLeft and FirstRight towards each other from opposite directions to
8069 // find a partitioning of the clusters which balances the weight on both
8070 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8071 // taken to ensure 0-weight nodes are distributed evenly.
8073 while (LastLeft + 1 < FirstRight) {
8074 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8075 LeftWeight += (++LastLeft)->Weight;
8077 RightWeight += (--FirstRight)->Weight;
8082 // Our binary search tree differs from a typical BST in that ours can have up
8083 // to three values in each leaf. The pivot selection above doesn't take that
8084 // into account, which means the tree might require more nodes and be less
8085 // efficient. We compensate for this here.
8087 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8088 unsigned NumRight = W.LastCluster - FirstRight + 1;
8090 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8091 // If one side has less than 3 clusters, and the other has more than 3,
8092 // consider taking a cluster from the other side.
8094 if (NumLeft < NumRight) {
8095 // Consider moving the first cluster on the right to the left side.
8096 CaseCluster &CC = *FirstRight;
8097 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8098 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8099 if (LeftSideRank <= RightSideRank) {
8100 // Moving the cluster to the left does not demote it.
8106 assert(NumRight < NumLeft);
8107 // Consider moving the last element on the left to the right side.
8108 CaseCluster &CC = *LastLeft;
8109 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8110 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8111 if (RightSideRank <= LeftSideRank) {
8112 // Moving the cluster to the right does not demot it.
8122 assert(LastLeft + 1 == FirstRight);
8123 assert(LastLeft >= W.FirstCluster);
8124 assert(FirstRight <= W.LastCluster);
8126 // Use the first element on the right as pivot since we will make less-than
8127 // comparisons against it.
8128 CaseClusterIt PivotCluster = FirstRight;
8129 assert(PivotCluster > W.FirstCluster);
8130 assert(PivotCluster <= W.LastCluster);
8132 CaseClusterIt FirstLeft = W.FirstCluster;
8133 CaseClusterIt LastRight = W.LastCluster;
8135 const ConstantInt *Pivot = PivotCluster->Low;
8137 // New blocks will be inserted immediately after the current one.
8138 MachineFunction::iterator BBI = W.MBB;
8141 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8142 // we can branch to its destination directly if it's squeezed exactly in
8143 // between the known lower bound and Pivot - 1.
8144 MachineBasicBlock *LeftMBB;
8145 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8146 FirstLeft->Low == W.GE &&
8147 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8148 LeftMBB = FirstLeft->MBB;
8150 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8151 FuncInfo.MF->insert(BBI, LeftMBB);
8152 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8153 // Put Cond in a virtual register to make it available from the new blocks.
8154 ExportFromCurrentBlock(Cond);
8157 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8158 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8159 // directly if RHS.High equals the current upper bound.
8160 MachineBasicBlock *RightMBB;
8161 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8162 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8163 RightMBB = FirstRight->MBB;
8165 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8166 FuncInfo.MF->insert(BBI, RightMBB);
8167 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8168 // Put Cond in a virtual register to make it available from the new blocks.
8169 ExportFromCurrentBlock(Cond);
8172 // Create the CaseBlock record that will be used to lower the branch.
8173 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8174 LeftWeight, RightWeight);
8176 if (W.MBB == SwitchMBB)
8177 visitSwitchCase(CB, SwitchMBB);
8179 SwitchCases.push_back(CB);
8182 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8183 // Extract cases from the switch.
8184 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8185 CaseClusterVector Clusters;
8186 Clusters.reserve(SI.getNumCases());
8187 for (auto I : SI.cases()) {
8188 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8189 const ConstantInt *CaseVal = I.getCaseValue();
8191 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8192 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8195 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8197 // Cluster adjacent cases with the same destination. We do this at all
8198 // optimization levels because it's cheap to do and will make codegen faster
8199 // if there are many clusters.
8200 sortAndRangeify(Clusters);
8202 if (TM.getOptLevel() != CodeGenOpt::None) {
8203 // Replace an unreachable default with the most popular destination.
8204 // FIXME: Exploit unreachable default more aggressively.
8205 bool UnreachableDefault =
8206 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8207 if (UnreachableDefault && !Clusters.empty()) {
8208 DenseMap<const BasicBlock *, unsigned> Popularity;
8209 unsigned MaxPop = 0;
8210 const BasicBlock *MaxBB = nullptr;
8211 for (auto I : SI.cases()) {
8212 const BasicBlock *BB = I.getCaseSuccessor();
8213 if (++Popularity[BB] > MaxPop) {
8214 MaxPop = Popularity[BB];
8219 assert(MaxPop > 0 && MaxBB);
8220 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8222 // Remove cases that were pointing to the destination that is now the
8224 CaseClusterVector New;
8225 New.reserve(Clusters.size());
8226 for (CaseCluster &CC : Clusters) {
8227 if (CC.MBB != DefaultMBB)
8230 Clusters = std::move(New);
8234 // If there is only the default destination, jump there directly.
8235 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8236 if (Clusters.empty()) {
8237 SwitchMBB->addSuccessor(DefaultMBB);
8238 if (DefaultMBB != NextBlock(SwitchMBB)) {
8239 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8240 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8245 findJumpTables(Clusters, &SI, DefaultMBB);
8246 findBitTestClusters(Clusters, &SI);
8249 dbgs() << "Case clusters: ";
8250 for (const CaseCluster &C : Clusters) {
8251 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8252 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8254 C.Low->getValue().print(dbgs(), true);
8255 if (C.Low != C.High) {
8257 C.High->getValue().print(dbgs(), true);
8264 assert(!Clusters.empty());
8265 SwitchWorkList WorkList;
8266 CaseClusterIt First = Clusters.begin();
8267 CaseClusterIt Last = Clusters.end() - 1;
8268 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8270 while (!WorkList.empty()) {
8271 SwitchWorkListItem W = WorkList.back();
8272 WorkList.pop_back();
8273 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8275 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8276 // For optimized builds, lower large range as a balanced binary tree.
8277 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8281 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);