1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
82 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
83 cl::desc("Enable fast-math-flags for DAG nodes"));
85 // Limit the width of DAG chains. This is important in general to prevent
86 // DAG-based analysis from blowing up. For example, alias analysis and
87 // load clustering may not complete in reasonable time. It is difficult to
88 // recognize and avoid this situation within each individual analysis, and
89 // future analyses are likely to have the same behavior. Limiting DAG width is
90 // the safe approach and will be especially important with global DAGs.
92 // MaxParallelChains default is arbitrarily high to avoid affecting
93 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
94 // sequence over this should have been converted to llvm.memcpy by the
95 // frontend. It easy to induce this behavior with .ll code such as:
96 // %buffer = alloca [4096 x i8]
97 // %data = load [4096 x i8]* %argPtr
98 // store [4096 x i8] %data, [4096 x i8]* %buffer
99 static const unsigned MaxParallelChains = 64;
101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts, unsigned NumParts,
103 MVT PartVT, EVT ValueVT, const Value *V);
105 /// getCopyFromParts - Create a value that contains the specified legal parts
106 /// combined into the value they represent. If the parts combine to a type
107 /// larger then ValueVT then AssertOp can be used to specify whether the extra
108 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
109 /// (ISD::AssertSext).
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
111 const SDValue *Parts,
112 unsigned NumParts, MVT PartVT, EVT ValueVT,
114 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
115 if (ValueVT.isVector())
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
119 assert(NumParts > 0 && "No parts to assemble!");
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 SDValue Val = Parts[0];
124 // Assemble the value from multiple parts.
125 if (ValueVT.isInteger()) {
126 unsigned PartBits = PartVT.getSizeInBits();
127 unsigned ValueBits = ValueVT.getSizeInBits();
129 // Assemble the power of 2 part.
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 << Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
139 if (RoundParts > 2) {
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
143 RoundParts / 2, PartVT, HalfVT, V);
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
149 if (DAG.getDataLayout().isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
154 if (RoundParts < NumParts) {
155 // Assemble the trailing non-power-of-2 part.
156 unsigned OddParts = NumParts - RoundParts;
157 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
158 Hi = getCopyFromParts(DAG, DL,
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
161 // Combine the round and odd parts.
163 if (DAG.getDataLayout().isBigEndian())
165 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
168 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
169 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
170 TLI.getPointerTy(DAG.getDataLayout())));
171 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
172 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
174 } else if (PartVT.isFloatingPoint()) {
175 // FP split into multiple FP parts (for ppcf128)
176 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
179 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
180 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
181 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
183 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
185 // FP split into integer parts (soft fp)
186 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
187 !PartVT.isVector() && "Unexpected split");
188 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
189 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
193 // There is now one part, held in Val. Correct it to match ValueVT.
194 EVT PartEVT = Val.getValueType();
196 if (PartEVT == ValueVT)
199 if (PartEVT.isInteger() && ValueVT.isInteger()) {
200 if (ValueVT.bitsLT(PartEVT)) {
201 // For a truncate, see if we have any information to
202 // indicate whether the truncated bits will always be
203 // zero or sign-extension.
204 if (AssertOp != ISD::DELETED_NODE)
205 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
206 DAG.getValueType(ValueVT));
207 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
209 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
212 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
213 // FP_ROUND's are always exact here.
214 if (ValueVT.bitsLT(Val.getValueType()))
216 ISD::FP_ROUND, DL, ValueVT, Val,
217 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
219 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
223 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
225 llvm_unreachable("Unknown mismatch!");
228 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
229 const Twine &ErrMsg) {
230 const Instruction *I = dyn_cast_or_null<Instruction>(V);
232 return Ctx.emitError(ErrMsg);
234 const char *AsmError = ", possible invalid constraint for vector type";
235 if (const CallInst *CI = dyn_cast<CallInst>(I))
236 if (isa<InlineAsm>(CI->getCalledValue()))
237 return Ctx.emitError(I, ErrMsg + AsmError);
239 return Ctx.emitError(I, ErrMsg);
242 /// getCopyFromPartsVector - Create a value that contains the specified legal
243 /// parts combined into the value they represent. If the parts combine to a
244 /// type larger then ValueVT then AssertOp can be used to specify whether the
245 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
246 /// ValueVT (ISD::AssertSext).
247 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
248 const SDValue *Parts, unsigned NumParts,
249 MVT PartVT, EVT ValueVT, const Value *V) {
250 assert(ValueVT.isVector() && "Not a vector value");
251 assert(NumParts > 0 && "No parts to assemble!");
252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
253 SDValue Val = Parts[0];
255 // Handle a multi-element vector.
259 unsigned NumIntermediates;
261 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
262 NumIntermediates, RegisterVT);
263 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
264 NumParts = NumRegs; // Silence a compiler warning.
265 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
266 assert(RegisterVT.getSizeInBits() ==
267 Parts[0].getSimpleValueType().getSizeInBits() &&
268 "Part type sizes don't match!");
270 // Assemble the parts into intermediate operands.
271 SmallVector<SDValue, 8> Ops(NumIntermediates);
272 if (NumIntermediates == NumParts) {
273 // If the register was not expanded, truncate or copy the value,
275 for (unsigned i = 0; i != NumParts; ++i)
276 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
277 PartVT, IntermediateVT, V);
278 } else if (NumParts > 0) {
279 // If the intermediate type was expanded, build the intermediate
280 // operands from the parts.
281 assert(NumParts % NumIntermediates == 0 &&
282 "Must expand into a divisible number of parts!");
283 unsigned Factor = NumParts / NumIntermediates;
284 for (unsigned i = 0; i != NumIntermediates; ++i)
285 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
286 PartVT, IntermediateVT, V);
289 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
290 // intermediate operands.
291 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
296 // There is now one part, held in Val. Correct it to match ValueVT.
297 EVT PartEVT = Val.getValueType();
299 if (PartEVT == ValueVT)
302 if (PartEVT.isVector()) {
303 // If the element type of the source/dest vectors are the same, but the
304 // parts vector has more elements than the value vector, then we have a
305 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
307 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
308 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
309 "Cannot narrow, it would be a lossy transformation");
311 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
312 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
315 // Vector/Vector bitcast.
316 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
317 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
319 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
320 "Cannot handle this kind of promotion");
321 // Promoted vector extract
322 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
326 // Trivial bitcast if the types are the same size and the destination
327 // vector type is legal.
328 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
329 TLI.isTypeLegal(ValueVT))
330 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
332 // Handle cases such as i8 -> <1 x i1>
333 if (ValueVT.getVectorNumElements() != 1) {
334 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
335 "non-trivial scalar-to-vector conversion");
336 return DAG.getUNDEF(ValueVT);
339 if (ValueVT.getVectorNumElements() == 1 &&
340 ValueVT.getVectorElementType() != PartEVT)
341 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
343 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
346 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
347 SDValue Val, SDValue *Parts, unsigned NumParts,
348 MVT PartVT, const Value *V);
350 /// getCopyToParts - Create a series of nodes that contain the specified value
351 /// split into legal parts. If the parts contain more bits than Val, then, for
352 /// integers, ExtendKind can be used to specify how to generate the extra bits.
353 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
354 SDValue Val, SDValue *Parts, unsigned NumParts,
355 MVT PartVT, const Value *V,
356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
357 EVT ValueVT = Val.getValueType();
359 // Handle the vector case separately.
360 if (ValueVT.isVector())
361 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
363 unsigned PartBits = PartVT.getSizeInBits();
364 unsigned OrigNumParts = NumParts;
365 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
366 "Copying to an illegal type!");
371 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
372 EVT PartEVT = PartVT;
373 if (PartEVT == ValueVT) {
374 assert(NumParts == 1 && "No-op copy with multiple parts!");
379 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
380 // If the parts cover more bits than the value has, promote the value.
381 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
382 assert(NumParts == 1 && "Do not know what to promote to!");
383 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
386 ValueVT.isInteger() &&
387 "Unknown mismatch!");
388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
389 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
390 if (PartVT == MVT::x86mmx)
391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 } else if (PartBits == ValueVT.getSizeInBits()) {
394 // Different types of the same size.
395 assert(NumParts == 1 && PartEVT != ValueVT);
396 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
397 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
398 // If the parts cover less bits than value has, truncate the value.
399 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
400 ValueVT.isInteger() &&
401 "Unknown mismatch!");
402 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
403 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
404 if (PartVT == MVT::x86mmx)
405 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
408 // The value may have changed - recompute ValueVT.
409 ValueVT = Val.getValueType();
410 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
411 "Failed to tile the value with PartVT!");
414 if (PartEVT != ValueVT)
415 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
416 "scalar-to-vector conversion failed");
422 // Expand the value into multiple parts.
423 if (NumParts & (NumParts - 1)) {
424 // The number of parts is not a power of 2. Split off and copy the tail.
425 assert(PartVT.isInteger() && ValueVT.isInteger() &&
426 "Do not know what to expand to!");
427 unsigned RoundParts = 1 << Log2_32(NumParts);
428 unsigned RoundBits = RoundParts * PartBits;
429 unsigned OddParts = NumParts - RoundParts;
430 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
431 DAG.getIntPtrConstant(RoundBits, DL));
432 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
434 if (DAG.getDataLayout().isBigEndian())
435 // The odd parts were reversed by getCopyToParts - unreverse them.
436 std::reverse(Parts + RoundParts, Parts + NumParts);
438 NumParts = RoundParts;
439 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
440 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
443 // The number of parts is a power of 2. Repeatedly bisect the value using
445 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
446 EVT::getIntegerVT(*DAG.getContext(),
447 ValueVT.getSizeInBits()),
450 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
451 for (unsigned i = 0; i < NumParts; i += StepSize) {
452 unsigned ThisBits = StepSize * PartBits / 2;
453 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
454 SDValue &Part0 = Parts[i];
455 SDValue &Part1 = Parts[i+StepSize/2];
457 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
459 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
460 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
462 if (ThisBits == PartBits && ThisVT != PartVT) {
463 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
464 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
469 if (DAG.getDataLayout().isBigEndian())
470 std::reverse(Parts, Parts + OrigNumParts);
474 /// getCopyToPartsVector - Create a series of nodes that contain the specified
475 /// value split into legal parts.
476 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
477 SDValue Val, SDValue *Parts, unsigned NumParts,
478 MVT PartVT, const Value *V) {
479 EVT ValueVT = Val.getValueType();
480 assert(ValueVT.isVector() && "Not a vector");
481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
484 EVT PartEVT = PartVT;
485 if (PartEVT == ValueVT) {
487 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
488 // Bitconvert vector->vector case.
489 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
490 } else if (PartVT.isVector() &&
491 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
492 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
493 EVT ElementVT = PartVT.getVectorElementType();
494 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
496 SmallVector<SDValue, 16> Ops;
497 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getNode(
499 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
500 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
502 for (unsigned i = ValueVT.getVectorNumElements(),
503 e = PartVT.getVectorNumElements(); i != e; ++i)
504 Ops.push_back(DAG.getUNDEF(ElementVT));
506 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
508 // FIXME: Use CONCAT for 2x -> 4x.
510 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
511 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
512 } else if (PartVT.isVector() &&
513 PartEVT.getVectorElementType().bitsGE(
514 ValueVT.getVectorElementType()) &&
515 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
517 // Promoted vector extract
518 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
524 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
525 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
527 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
552 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
553 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
554 TLI.getVectorIdxTy(DAG.getDataLayout())));
556 Ops[i] = DAG.getNode(
557 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
558 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
579 RegsForValue::RegsForValue() {}
581 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
585 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
586 const DataLayout &DL, unsigned Reg, Type *Ty) {
587 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
589 for (EVT ValueVT : ValueVTs) {
590 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
591 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
592 for (unsigned i = 0; i != NumRegs; ++i)
593 Regs.push_back(Reg + i);
594 RegVTs.push_back(RegisterVT);
599 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
600 /// this value and returns the result as a ValueVT value. This uses
601 /// Chain/Flag as the input and updates them for the output Chain/Flag.
602 /// If the Flag pointer is NULL, no flag is used.
603 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
604 FunctionLoweringInfo &FuncInfo,
606 SDValue &Chain, SDValue *Flag,
607 const Value *V) const {
608 // A Value with type {} or [0 x %t] needs no registers.
609 if (ValueVTs.empty())
612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
614 // Assemble the legal parts into the final values.
615 SmallVector<SDValue, 4> Values(ValueVTs.size());
616 SmallVector<SDValue, 8> Parts;
617 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
618 // Copy the legal parts from the registers.
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
621 MVT RegisterVT = RegVTs[Value];
623 Parts.resize(NumRegs);
624 for (unsigned i = 0; i != NumRegs; ++i) {
627 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
630 *Flag = P.getValue(2);
633 Chain = P.getValue(1);
636 // If the source register was virtual and if we know something about it,
637 // add an assert node.
638 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
639 !RegisterVT.isInteger() || RegisterVT.isVector())
642 const FunctionLoweringInfo::LiveOutInfo *LOI =
643 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
647 unsigned RegSize = RegisterVT.getSizeInBits();
648 unsigned NumSignBits = LOI->NumSignBits;
649 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
651 if (NumZeroBits == RegSize) {
652 // The current value is a zero.
653 // Explicitly express that as it would be easier for
654 // optimizations to kick in.
655 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
659 // FIXME: We capture more information than the dag can represent. For
660 // now, just use the tightest assertzext/assertsext possible.
662 EVT FromVT(MVT::Other);
663 if (NumSignBits == RegSize)
664 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
665 else if (NumZeroBits >= RegSize-1)
666 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
667 else if (NumSignBits > RegSize-8)
668 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
669 else if (NumZeroBits >= RegSize-8)
670 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
671 else if (NumSignBits > RegSize-16)
672 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
673 else if (NumZeroBits >= RegSize-16)
674 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
675 else if (NumSignBits > RegSize-32)
676 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
677 else if (NumZeroBits >= RegSize-32)
678 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
682 // Add an assertion node.
683 assert(FromVT != MVT::Other);
684 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
685 RegisterVT, P, DAG.getValueType(FromVT));
688 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
689 NumRegs, RegisterVT, ValueVT, V);
694 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
697 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
698 /// specified value into the registers specified by this object. This uses
699 /// Chain/Flag as the input and updates them for the output Chain/Flag.
700 /// If the Flag pointer is NULL, no flag is used.
701 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
702 SDValue &Chain, SDValue *Flag, const Value *V,
703 ISD::NodeType PreferredExtendType) const {
704 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
705 ISD::NodeType ExtendKind = PreferredExtendType;
707 // Get the list of the values's legal parts.
708 unsigned NumRegs = Regs.size();
709 SmallVector<SDValue, 8> Parts(NumRegs);
710 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
711 EVT ValueVT = ValueVTs[Value];
712 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
713 MVT RegisterVT = RegVTs[Value];
715 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
716 ExtendKind = ISD::ZERO_EXTEND;
718 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
719 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
723 // Copy the parts into the registers.
724 SmallVector<SDValue, 8> Chains(NumRegs);
725 for (unsigned i = 0; i != NumRegs; ++i) {
728 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
731 *Flag = Part.getValue(1);
734 Chains[i] = Part.getValue(0);
737 if (NumRegs == 1 || Flag)
738 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
739 // flagged to it. That is the CopyToReg nodes and the user are considered
740 // a single scheduling unit. If we create a TokenFactor and return it as
741 // chain, then the TokenFactor is both a predecessor (operand) of the
742 // user as well as a successor (the TF operands are flagged to the user).
743 // c1, f1 = CopyToReg
744 // c2, f2 = CopyToReg
745 // c3 = TokenFactor c1, c2
748 Chain = Chains[NumRegs-1];
750 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
753 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
754 /// operand list. This adds the code marker and includes the number of
755 /// values added into it.
756 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
757 unsigned MatchingIdx, SDLoc dl,
759 std::vector<SDValue> &Ops) const {
760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
762 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
764 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
765 else if (!Regs.empty() &&
766 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
767 // Put the register class of the virtual registers in the flag word. That
768 // way, later passes can recompute register class constraints for inline
769 // assembly as well as normal instructions.
770 // Don't do this for tied operands that can use the regclass information
772 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
773 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
774 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
777 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
780 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
781 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
782 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
783 MVT RegisterVT = RegVTs[Value];
784 for (unsigned i = 0; i != NumRegs; ++i) {
785 assert(Reg < Regs.size() && "Mismatch in # registers expected");
786 unsigned TheReg = Regs[Reg++];
787 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
789 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
790 // If we clobbered the stack pointer, MFI should know about it.
791 assert(DAG.getMachineFunction().getFrameInfo()->
792 hasOpaqueSPAdjustment());
798 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
799 const TargetLibraryInfo *li) {
803 DL = &DAG.getDataLayout();
804 Context = DAG.getContext();
805 LPadToCallSiteMap.clear();
808 /// clear - Clear out the current SelectionDAG and the associated
809 /// state and prepare this SelectionDAGBuilder object to be used
810 /// for a new block. This doesn't clear out information about
811 /// additional blocks that are needed to complete switch lowering
812 /// or PHI node updating; that information is cleared out as it is
814 void SelectionDAGBuilder::clear() {
816 UnusedArgNodeMap.clear();
817 PendingLoads.clear();
818 PendingExports.clear();
821 SDNodeOrder = LowestSDNodeOrder;
822 StatepointLowering.clear();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is separated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
884 PendingExports.clear();
889 void SelectionDAGBuilder::visit(const Instruction &I) {
890 // Set up outgoing PHI node register values before emitting the terminator.
891 if (isa<TerminatorInst>(&I))
892 HandlePHINodesInSuccessorBlocks(I.getParent());
898 visit(I.getOpcode(), I);
900 if (!isa<TerminatorInst>(&I) && !HasTailCall)
901 CopyToExportRegsIfNeeded(&I);
906 void SelectionDAGBuilder::visitPHI(const PHINode &) {
907 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
910 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
911 // Note: this doesn't use InstVisitor, because it has to work with
912 // ConstantExpr's in addition to instructions.
914 default: llvm_unreachable("Unknown instruction type encountered!");
915 // Build the switch statement using the Instruction.def file.
916 #define HANDLE_INST(NUM, OPCODE, CLASS) \
917 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
918 #include "llvm/IR/Instruction.def"
922 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
923 // generate the debug data structures now that we've seen its definition.
924 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
926 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
928 const DbgValueInst *DI = DDI.getDI();
929 DebugLoc dl = DDI.getdl();
930 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
931 DILocalVariable *Variable = DI->getVariable();
932 DIExpression *Expr = DI->getExpression();
933 assert(Variable->isValidLocationForIntrinsic(dl) &&
934 "Expected inlined-at fields to agree");
935 uint64_t Offset = DI->getOffset();
936 // A dbg.value for an alloca is always indirect.
937 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
940 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
942 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
943 IsIndirect, Offset, dl, DbgSDNodeOrder);
944 DAG.AddDbgValue(SDV, Val.getNode(), false);
947 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
948 DanglingDebugInfoMap[V] = DanglingDebugInfo();
952 /// getCopyFromRegs - If there was virtual register allocated for the value V
953 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
954 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
955 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
958 if (It != FuncInfo.ValueMap.end()) {
959 unsigned InReg = It->second;
960 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
961 DAG.getDataLayout(), InReg, Ty);
962 SDValue Chain = DAG.getEntryNode();
963 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
964 resolveDanglingDebugInfo(V, Result);
970 /// getValue - Return an SDValue for the given Value.
971 SDValue SelectionDAGBuilder::getValue(const Value *V) {
972 // If we already have an SDValue for this value, use it. It's important
973 // to do this first, so that we don't create a CopyFromReg if we already
974 // have a regular SDValue.
975 SDValue &N = NodeMap[V];
976 if (N.getNode()) return N;
978 // If there's a virtual register allocated and initialized for this
980 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
981 if (copyFromReg.getNode()) {
985 // Otherwise create a new SDValue and remember it.
986 SDValue Val = getValueImpl(V);
988 resolveDanglingDebugInfo(V, Val);
992 // Return true if SDValue exists for the given Value
993 bool SelectionDAGBuilder::findValue(const Value *V) const {
994 return (NodeMap.find(V) != NodeMap.end()) ||
995 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
998 /// getNonRegisterValue - Return an SDValue for the given Value, but
999 /// don't look in FuncInfo.ValueMap for a virtual register.
1000 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1001 // If we already have an SDValue for this value, use it.
1002 SDValue &N = NodeMap[V];
1004 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1005 // Remove the debug location from the node as the node is about to be used
1006 // in a location which may differ from the original debug location. This
1007 // is relevant to Constant and ConstantFP nodes because they can appear
1008 // as constant expressions inside PHI nodes.
1009 N->setDebugLoc(DebugLoc());
1014 // Otherwise create a new SDValue and remember it.
1015 SDValue Val = getValueImpl(V);
1017 resolveDanglingDebugInfo(V, Val);
1021 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1022 /// Create an SDValue for the given value.
1023 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1026 if (const Constant *C = dyn_cast<Constant>(V)) {
1027 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1029 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1030 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1032 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1033 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1035 if (isa<ConstantPointerNull>(C)) {
1036 unsigned AS = V->getType()->getPointerAddressSpace();
1037 return DAG.getConstant(0, getCurSDLoc(),
1038 TLI.getPointerTy(DAG.getDataLayout(), AS));
1041 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1042 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1044 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1045 return DAG.getUNDEF(VT);
1047 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1048 visit(CE->getOpcode(), *CE);
1049 SDValue N1 = NodeMap[V];
1050 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1054 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1055 SmallVector<SDValue, 4> Constants;
1056 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1058 SDNode *Val = getValue(*OI).getNode();
1059 // If the operand is an empty aggregate, there are no values.
1061 // Add each leaf value from the operand to the Constants list
1062 // to form a flattened list of all the values.
1063 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1064 Constants.push_back(SDValue(Val, i));
1067 return DAG.getMergeValues(Constants, getCurSDLoc());
1070 if (const ConstantDataSequential *CDS =
1071 dyn_cast<ConstantDataSequential>(C)) {
1072 SmallVector<SDValue, 4> Ops;
1073 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1074 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1075 // Add each leaf value from the operand to the Constants list
1076 // to form a flattened list of all the values.
1077 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1078 Ops.push_back(SDValue(Val, i));
1081 if (isa<ArrayType>(CDS->getType()))
1082 return DAG.getMergeValues(Ops, getCurSDLoc());
1083 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1087 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1088 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1089 "Unknown struct or array constant!");
1091 SmallVector<EVT, 4> ValueVTs;
1092 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1093 unsigned NumElts = ValueVTs.size();
1095 return SDValue(); // empty struct
1096 SmallVector<SDValue, 4> Constants(NumElts);
1097 for (unsigned i = 0; i != NumElts; ++i) {
1098 EVT EltVT = ValueVTs[i];
1099 if (isa<UndefValue>(C))
1100 Constants[i] = DAG.getUNDEF(EltVT);
1101 else if (EltVT.isFloatingPoint())
1102 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1104 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1107 return DAG.getMergeValues(Constants, getCurSDLoc());
1110 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1111 return DAG.getBlockAddress(BA, VT);
1113 VectorType *VecTy = cast<VectorType>(V->getType());
1114 unsigned NumElements = VecTy->getNumElements();
1116 // Now that we know the number and type of the elements, get that number of
1117 // elements into the Ops array based on what kind of constant it is.
1118 SmallVector<SDValue, 16> Ops;
1119 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1120 for (unsigned i = 0; i != NumElements; ++i)
1121 Ops.push_back(getValue(CV->getOperand(i)));
1123 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1125 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1128 if (EltVT.isFloatingPoint())
1129 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1131 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1132 Ops.assign(NumElements, Op);
1135 // Create a BUILD_VECTOR node.
1136 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1139 // If this is a static alloca, generate it as the frameindex instead of
1141 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1142 DenseMap<const AllocaInst*, int>::iterator SI =
1143 FuncInfo.StaticAllocaMap.find(AI);
1144 if (SI != FuncInfo.StaticAllocaMap.end())
1145 return DAG.getFrameIndex(SI->second,
1146 TLI.getPointerTy(DAG.getDataLayout()));
1149 // If this is an instruction which fast-isel has deferred, select it now.
1150 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1151 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1152 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1154 SDValue Chain = DAG.getEntryNode();
1155 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1158 llvm_unreachable("Can't get register for value!");
1161 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1162 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1163 auto &DL = DAG.getDataLayout();
1164 SDValue Chain = getControlRoot();
1165 SmallVector<ISD::OutputArg, 8> Outs;
1166 SmallVector<SDValue, 8> OutVals;
1168 if (!FuncInfo.CanLowerReturn) {
1169 unsigned DemoteReg = FuncInfo.DemoteRegister;
1170 const Function *F = I.getParent()->getParent();
1172 // Emit a store of the return value through the virtual register.
1173 // Leave Outs empty so that LowerReturn won't try to load return
1174 // registers the usual way.
1175 SmallVector<EVT, 1> PtrValueVTs;
1176 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1179 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1180 SDValue RetOp = getValue(I.getOperand(0));
1182 SmallVector<EVT, 4> ValueVTs;
1183 SmallVector<uint64_t, 4> Offsets;
1184 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1185 unsigned NumValues = ValueVTs.size();
1187 SmallVector<SDValue, 4> Chains(NumValues);
1188 for (unsigned i = 0; i != NumValues; ++i) {
1189 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1190 RetPtr.getValueType(), RetPtr,
1191 DAG.getIntPtrConstant(Offsets[i],
1194 DAG.getStore(Chain, getCurSDLoc(),
1195 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1196 // FIXME: better loc info would be nice.
1197 Add, MachinePointerInfo(), false, false, 0);
1200 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1201 MVT::Other, Chains);
1202 } else if (I.getNumOperands() != 0) {
1203 SmallVector<EVT, 4> ValueVTs;
1204 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1205 unsigned NumValues = ValueVTs.size();
1207 SDValue RetOp = getValue(I.getOperand(0));
1209 const Function *F = I.getParent()->getParent();
1211 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1212 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1214 ExtendKind = ISD::SIGN_EXTEND;
1215 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1217 ExtendKind = ISD::ZERO_EXTEND;
1219 LLVMContext &Context = F->getContext();
1220 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1223 for (unsigned j = 0; j != NumValues; ++j) {
1224 EVT VT = ValueVTs[j];
1226 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1227 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1229 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1230 MVT PartVT = TLI.getRegisterType(Context, VT);
1231 SmallVector<SDValue, 4> Parts(NumParts);
1232 getCopyToParts(DAG, getCurSDLoc(),
1233 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1234 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1236 // 'inreg' on function refers to return value
1237 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1241 // Propagate extension type if any
1242 if (ExtendKind == ISD::SIGN_EXTEND)
1244 else if (ExtendKind == ISD::ZERO_EXTEND)
1247 for (unsigned i = 0; i < NumParts; ++i) {
1248 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1249 VT, /*isfixed=*/true, 0, 0));
1250 OutVals.push_back(Parts[i]);
1256 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1257 CallingConv::ID CallConv =
1258 DAG.getMachineFunction().getFunction()->getCallingConv();
1259 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1260 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1262 // Verify that the target's LowerReturn behaved as expected.
1263 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1264 "LowerReturn didn't return a valid chain!");
1266 // Update the DAG with the new chain value resulting from return lowering.
1270 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1271 /// created for it, emit nodes to copy the value into the virtual
1273 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1275 if (V->getType()->isEmptyTy())
1278 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1279 if (VMI != FuncInfo.ValueMap.end()) {
1280 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1281 CopyValueToVirtualRegister(V, VMI->second);
1285 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1286 /// the current basic block, add it to ValueMap now so that we'll get a
1288 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1289 // No need to export constants.
1290 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1292 // Already exported?
1293 if (FuncInfo.isExportedInst(V)) return;
1295 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1296 CopyValueToVirtualRegister(V, Reg);
1299 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1300 const BasicBlock *FromBB) {
1301 // The operands of the setcc have to be in this block. We don't know
1302 // how to export them from some other block.
1303 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1304 // Can export from current BB.
1305 if (VI->getParent() == FromBB)
1308 // Is already exported, noop.
1309 return FuncInfo.isExportedInst(V);
1312 // If this is an argument, we can export it if the BB is the entry block or
1313 // if it is already exported.
1314 if (isa<Argument>(V)) {
1315 if (FromBB == &FromBB->getParent()->getEntryBlock())
1318 // Otherwise, can only export this if it is already exported.
1319 return FuncInfo.isExportedInst(V);
1322 // Otherwise, constants can always be exported.
1326 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1327 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1328 const MachineBasicBlock *Dst) const {
1329 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1332 const BasicBlock *SrcBB = Src->getBasicBlock();
1333 const BasicBlock *DstBB = Dst->getBasicBlock();
1334 return BPI->getEdgeWeight(SrcBB, DstBB);
1337 void SelectionDAGBuilder::
1338 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1339 uint32_t Weight /* = 0 */) {
1341 Weight = getEdgeWeight(Src, Dst);
1342 Src->addSuccessor(Dst, Weight);
1346 static bool InBlock(const Value *V, const BasicBlock *BB) {
1347 if (const Instruction *I = dyn_cast<Instruction>(V))
1348 return I->getParent() == BB;
1352 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1353 /// This function emits a branch and is used at the leaves of an OR or an
1354 /// AND operator tree.
1357 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1358 MachineBasicBlock *TBB,
1359 MachineBasicBlock *FBB,
1360 MachineBasicBlock *CurBB,
1361 MachineBasicBlock *SwitchBB,
1364 const BasicBlock *BB = CurBB->getBasicBlock();
1366 // If the leaf of the tree is a comparison, merge the condition into
1368 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1369 // The operands of the cmp have to be in this block. We don't know
1370 // how to export them from some other block. If this is the first block
1371 // of the sequence, no exporting is needed.
1372 if (CurBB == SwitchBB ||
1373 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1374 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1375 ISD::CondCode Condition;
1376 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1377 Condition = getICmpCondCode(IC->getPredicate());
1379 const FCmpInst *FC = cast<FCmpInst>(Cond);
1380 Condition = getFCmpCondCode(FC->getPredicate());
1381 if (TM.Options.NoNaNsFPMath)
1382 Condition = getFCmpCodeWithoutNaN(Condition);
1385 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1386 TBB, FBB, CurBB, TWeight, FWeight);
1387 SwitchCases.push_back(CB);
1392 // Create a CaseBlock record representing this branch.
1393 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1394 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1395 SwitchCases.push_back(CB);
1398 /// Scale down both weights to fit into uint32_t.
1399 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1400 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1401 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1402 NewTrue = NewTrue / Scale;
1403 NewFalse = NewFalse / Scale;
1406 /// FindMergedConditions - If Cond is an expression like
1407 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1408 MachineBasicBlock *TBB,
1409 MachineBasicBlock *FBB,
1410 MachineBasicBlock *CurBB,
1411 MachineBasicBlock *SwitchBB,
1412 Instruction::BinaryOps Opc,
1415 // If this node is not part of the or/and tree, emit it as a branch.
1416 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1417 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1418 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1419 BOp->getParent() != CurBB->getBasicBlock() ||
1420 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1421 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1422 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1427 // Create TmpBB after CurBB.
1428 MachineFunction::iterator BBI = CurBB;
1429 MachineFunction &MF = DAG.getMachineFunction();
1430 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1431 CurBB->getParent()->insert(++BBI, TmpBB);
1433 if (Opc == Instruction::Or) {
1434 // Codegen X | Y as:
1443 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1444 // The requirement is that
1445 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1446 // = TrueProb for original BB.
1447 // Assuming the original weights are A and B, one choice is to set BB1's
1448 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1450 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1451 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1452 // TmpBB, but the math is more complicated.
1454 uint64_t NewTrueWeight = TWeight;
1455 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1456 ScaleWeights(NewTrueWeight, NewFalseWeight);
1457 // Emit the LHS condition.
1458 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1459 NewTrueWeight, NewFalseWeight);
1461 NewTrueWeight = TWeight;
1462 NewFalseWeight = 2 * (uint64_t)FWeight;
1463 ScaleWeights(NewTrueWeight, NewFalseWeight);
1464 // Emit the RHS condition into TmpBB.
1465 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1466 NewTrueWeight, NewFalseWeight);
1468 assert(Opc == Instruction::And && "Unknown merge op!");
1469 // Codegen X & Y as:
1477 // This requires creation of TmpBB after CurBB.
1479 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1480 // The requirement is that
1481 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1482 // = FalseProb for original BB.
1483 // Assuming the original weights are A and B, one choice is to set BB1's
1484 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1486 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1488 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1489 uint64_t NewFalseWeight = FWeight;
1490 ScaleWeights(NewTrueWeight, NewFalseWeight);
1491 // Emit the LHS condition.
1492 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1493 NewTrueWeight, NewFalseWeight);
1495 NewTrueWeight = 2 * (uint64_t)TWeight;
1496 NewFalseWeight = FWeight;
1497 ScaleWeights(NewTrueWeight, NewFalseWeight);
1498 // Emit the RHS condition into TmpBB.
1499 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1500 NewTrueWeight, NewFalseWeight);
1504 /// If the set of cases should be emitted as a series of branches, return true.
1505 /// If we should emit this as a bunch of and/or'd together conditions, return
1508 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1509 if (Cases.size() != 2) return true;
1511 // If this is two comparisons of the same values or'd or and'd together, they
1512 // will get folded into a single comparison, so don't emit two blocks.
1513 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1514 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1515 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1516 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1520 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1521 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1522 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1523 Cases[0].CC == Cases[1].CC &&
1524 isa<Constant>(Cases[0].CmpRHS) &&
1525 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1526 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1528 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1535 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1536 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1538 // Update machine-CFG edges.
1539 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1541 if (I.isUnconditional()) {
1542 // Update machine-CFG edges.
1543 BrMBB->addSuccessor(Succ0MBB);
1545 // If this is not a fall-through branch or optimizations are switched off,
1547 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1548 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1549 MVT::Other, getControlRoot(),
1550 DAG.getBasicBlock(Succ0MBB)));
1555 // If this condition is one of the special cases we handle, do special stuff
1557 const Value *CondVal = I.getCondition();
1558 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1560 // If this is a series of conditions that are or'd or and'd together, emit
1561 // this as a sequence of branches instead of setcc's with and/or operations.
1562 // As long as jumps are not expensive, this should improve performance.
1563 // For example, instead of something like:
1576 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1577 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1578 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1579 BOp->getOpcode() == Instruction::Or)) {
1580 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1581 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1582 getEdgeWeight(BrMBB, Succ1MBB));
1583 // If the compares in later blocks need to use values not currently
1584 // exported from this block, export them now. This block should always
1585 // be the first entry.
1586 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1588 // Allow some cases to be rejected.
1589 if (ShouldEmitAsBranches(SwitchCases)) {
1590 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1591 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1592 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1595 // Emit the branch for this block.
1596 visitSwitchCase(SwitchCases[0], BrMBB);
1597 SwitchCases.erase(SwitchCases.begin());
1601 // Okay, we decided not to do this, remove any inserted MBB's and clear
1603 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1604 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1606 SwitchCases.clear();
1610 // Create a CaseBlock record representing this branch.
1611 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1612 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1614 // Use visitSwitchCase to actually insert the fast branch sequence for this
1616 visitSwitchCase(CB, BrMBB);
1619 /// visitSwitchCase - Emits the necessary code to represent a single node in
1620 /// the binary search tree resulting from lowering a switch instruction.
1621 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1622 MachineBasicBlock *SwitchBB) {
1624 SDValue CondLHS = getValue(CB.CmpLHS);
1625 SDLoc dl = getCurSDLoc();
1627 // Build the setcc now.
1629 // Fold "(X == true)" to X and "(X == false)" to !X to
1630 // handle common cases produced by branch lowering.
1631 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1632 CB.CC == ISD::SETEQ)
1634 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1635 CB.CC == ISD::SETEQ) {
1636 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1637 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1639 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1641 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1643 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1644 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1646 SDValue CmpOp = getValue(CB.CmpMHS);
1647 EVT VT = CmpOp.getValueType();
1649 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1650 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1653 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1654 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1655 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1656 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1660 // Update successor info
1661 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1662 // TrueBB and FalseBB are always different unless the incoming IR is
1663 // degenerate. This only happens when running llc on weird IR.
1664 if (CB.TrueBB != CB.FalseBB)
1665 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1667 // If the lhs block is the next block, invert the condition so that we can
1668 // fall through to the lhs instead of the rhs block.
1669 if (CB.TrueBB == NextBlock(SwitchBB)) {
1670 std::swap(CB.TrueBB, CB.FalseBB);
1671 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1672 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1675 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1676 MVT::Other, getControlRoot(), Cond,
1677 DAG.getBasicBlock(CB.TrueBB));
1679 // Insert the false branch. Do this even if it's a fall through branch,
1680 // this makes it easier to do DAG optimizations which require inverting
1681 // the branch condition.
1682 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1683 DAG.getBasicBlock(CB.FalseBB));
1685 DAG.setRoot(BrCond);
1688 /// visitJumpTable - Emit JumpTable node in the current MBB
1689 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1690 // Emit the code for the jump table
1691 assert(JT.Reg != -1U && "Should lower JT Header first!");
1692 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1693 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1695 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1696 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1697 MVT::Other, Index.getValue(1),
1699 DAG.setRoot(BrJumpTable);
1702 /// visitJumpTableHeader - This function emits necessary code to produce index
1703 /// in the JumpTable from switch case.
1704 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1705 JumpTableHeader &JTH,
1706 MachineBasicBlock *SwitchBB) {
1707 SDLoc dl = getCurSDLoc();
1709 // Subtract the lowest switch case value from the value being switched on and
1710 // conditional branch to default mbb if the result is greater than the
1711 // difference between smallest and largest cases.
1712 SDValue SwitchOp = getValue(JTH.SValue);
1713 EVT VT = SwitchOp.getValueType();
1714 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1715 DAG.getConstant(JTH.First, dl, VT));
1717 // The SDNode we just created, which holds the value being switched on minus
1718 // the smallest case value, needs to be copied to a virtual register so it
1719 // can be used as an index into the jump table in a subsequent basic block.
1720 // This value may be smaller or larger than the target's pointer type, and
1721 // therefore require extension or truncating.
1722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1723 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1725 unsigned JumpTableReg =
1726 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1727 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1728 JumpTableReg, SwitchOp);
1729 JT.Reg = JumpTableReg;
1731 // Emit the range check for the jump table, and branch to the default block
1732 // for the switch statement if the value being switched on exceeds the largest
1733 // case in the switch.
1734 SDValue CMP = DAG.getSetCC(
1735 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1736 Sub.getValueType()),
1737 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1739 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1740 MVT::Other, CopyTo, CMP,
1741 DAG.getBasicBlock(JT.Default));
1743 // Avoid emitting unnecessary branches to the next block.
1744 if (JT.MBB != NextBlock(SwitchBB))
1745 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1746 DAG.getBasicBlock(JT.MBB));
1748 DAG.setRoot(BrCond);
1751 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1752 /// tail spliced into a stack protector check success bb.
1754 /// For a high level explanation of how this fits into the stack protector
1755 /// generation see the comment on the declaration of class
1756 /// StackProtectorDescriptor.
1757 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1758 MachineBasicBlock *ParentBB) {
1760 // First create the loads to the guard/stack slot for the comparison.
1761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1762 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1764 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1765 int FI = MFI->getStackProtectorIndex();
1767 const Value *IRGuard = SPD.getGuard();
1768 SDValue GuardPtr = getValue(IRGuard);
1769 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1771 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1774 SDLoc dl = getCurSDLoc();
1776 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1777 // guard value from the virtual register holding the value. Otherwise, emit a
1778 // volatile load to retrieve the stack guard value.
1779 unsigned GuardReg = SPD.getGuardReg();
1781 if (GuardReg && TLI.useLoadStackGuardNode())
1782 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1785 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1786 GuardPtr, MachinePointerInfo(IRGuard, 0),
1787 true, false, false, Align);
1789 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1791 MachinePointerInfo::getFixedStack(FI),
1792 true, false, false, Align);
1794 // Perform the comparison via a subtract/getsetcc.
1795 EVT VT = Guard.getValueType();
1796 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1798 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1800 Sub.getValueType()),
1801 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1803 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1804 // branch to failure MBB.
1805 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1806 MVT::Other, StackSlot.getOperand(0),
1807 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1808 // Otherwise branch to success MBB.
1809 SDValue Br = DAG.getNode(ISD::BR, dl,
1811 DAG.getBasicBlock(SPD.getSuccessMBB()));
1816 /// Codegen the failure basic block for a stack protector check.
1818 /// A failure stack protector machine basic block consists simply of a call to
1819 /// __stack_chk_fail().
1821 /// For a high level explanation of how this fits into the stack protector
1822 /// generation see the comment on the declaration of class
1823 /// StackProtectorDescriptor.
1825 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1826 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1828 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1829 nullptr, 0, false, getCurSDLoc(), false, false).second;
1833 /// visitBitTestHeader - This function emits necessary code to produce value
1834 /// suitable for "bit tests"
1835 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1836 MachineBasicBlock *SwitchBB) {
1837 SDLoc dl = getCurSDLoc();
1839 // Subtract the minimum value
1840 SDValue SwitchOp = getValue(B.SValue);
1841 EVT VT = SwitchOp.getValueType();
1842 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1843 DAG.getConstant(B.First, dl, VT));
1846 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1847 SDValue RangeCmp = DAG.getSetCC(
1848 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1849 Sub.getValueType()),
1850 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1852 // Determine the type of the test operands.
1853 bool UsePtrType = false;
1854 if (!TLI.isTypeLegal(VT))
1857 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1858 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1859 // Switch table case range are encoded into series of masks.
1860 // Just use pointer type, it's guaranteed to fit.
1866 VT = TLI.getPointerTy(DAG.getDataLayout());
1867 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1870 B.RegVT = VT.getSimpleVT();
1871 B.Reg = FuncInfo.CreateReg(B.RegVT);
1872 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1874 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1876 addSuccessorWithWeight(SwitchBB, B.Default);
1877 addSuccessorWithWeight(SwitchBB, MBB);
1879 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1880 MVT::Other, CopyTo, RangeCmp,
1881 DAG.getBasicBlock(B.Default));
1883 // Avoid emitting unnecessary branches to the next block.
1884 if (MBB != NextBlock(SwitchBB))
1885 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1886 DAG.getBasicBlock(MBB));
1888 DAG.setRoot(BrRange);
1891 /// visitBitTestCase - this function produces one "bit test"
1892 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1893 MachineBasicBlock* NextMBB,
1894 uint32_t BranchWeightToNext,
1897 MachineBasicBlock *SwitchBB) {
1898 SDLoc dl = getCurSDLoc();
1900 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1902 unsigned PopCount = countPopulation(B.Mask);
1903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1904 if (PopCount == 1) {
1905 // Testing for a single bit; just compare the shift count with what it
1906 // would need to be to shift a 1 bit in that position.
1908 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1909 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1911 } else if (PopCount == BB.Range) {
1912 // There is only one zero bit in the range, test for it directly.
1914 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1915 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1918 // Make desired shift
1919 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1920 DAG.getConstant(1, dl, VT), ShiftOp);
1922 // Emit bit tests and jumps
1923 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1924 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1926 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1927 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1930 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1931 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1932 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1933 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1935 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1936 MVT::Other, getControlRoot(),
1937 Cmp, DAG.getBasicBlock(B.TargetBB));
1939 // Avoid emitting unnecessary branches to the next block.
1940 if (NextMBB != NextBlock(SwitchBB))
1941 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1942 DAG.getBasicBlock(NextMBB));
1947 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1948 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1950 // Retrieve successors.
1951 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1952 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1954 const Value *Callee(I.getCalledValue());
1955 const Function *Fn = dyn_cast<Function>(Callee);
1956 if (isa<InlineAsm>(Callee))
1958 else if (Fn && Fn->isIntrinsic()) {
1959 switch (Fn->getIntrinsicID()) {
1961 llvm_unreachable("Cannot invoke this intrinsic");
1962 case Intrinsic::donothing:
1963 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1965 case Intrinsic::experimental_patchpoint_void:
1966 case Intrinsic::experimental_patchpoint_i64:
1967 visitPatchpoint(&I, LandingPad);
1969 case Intrinsic::experimental_gc_statepoint:
1970 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1974 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1976 // If the value of the invoke is used outside of its defining block, make it
1977 // available as a virtual register.
1978 // We already took care of the exported value for the statepoint instruction
1979 // during call to the LowerStatepoint.
1980 if (!isStatepoint(I)) {
1981 CopyToExportRegsIfNeeded(&I);
1984 // Update successor info
1985 addSuccessorWithWeight(InvokeMBB, Return);
1986 addSuccessorWithWeight(InvokeMBB, LandingPad);
1988 // Drop into normal successor.
1989 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1990 MVT::Other, getControlRoot(),
1991 DAG.getBasicBlock(Return)));
1994 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1995 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1998 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1999 assert(FuncInfo.MBB->isLandingPad() &&
2000 "Call to landingpad not in landing pad!");
2002 MachineBasicBlock *MBB = FuncInfo.MBB;
2003 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2004 AddLandingPadInfo(LP, MMI, MBB);
2006 // If there aren't registers to copy the values into (e.g., during SjLj
2007 // exceptions), then don't bother to create these DAG nodes.
2008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2009 if (TLI.getExceptionPointerRegister() == 0 &&
2010 TLI.getExceptionSelectorRegister() == 0)
2013 SmallVector<EVT, 2> ValueVTs;
2014 SDLoc dl = getCurSDLoc();
2015 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2016 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2018 // Get the two live-in registers as SDValues. The physregs have already been
2019 // copied into virtual registers.
2021 if (FuncInfo.ExceptionPointerVirtReg) {
2022 Ops[0] = DAG.getZExtOrTrunc(
2023 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2024 FuncInfo.ExceptionPointerVirtReg,
2025 TLI.getPointerTy(DAG.getDataLayout())),
2028 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2030 Ops[1] = DAG.getZExtOrTrunc(
2031 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2032 FuncInfo.ExceptionSelectorVirtReg,
2033 TLI.getPointerTy(DAG.getDataLayout())),
2037 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2038 DAG.getVTList(ValueVTs), Ops);
2042 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2044 for (const CaseCluster &CC : Clusters)
2045 assert(CC.Low == CC.High && "Input clusters must be single-case");
2048 std::sort(Clusters.begin(), Clusters.end(),
2049 [](const CaseCluster &a, const CaseCluster &b) {
2050 return a.Low->getValue().slt(b.Low->getValue());
2053 // Merge adjacent clusters with the same destination.
2054 const unsigned N = Clusters.size();
2055 unsigned DstIndex = 0;
2056 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2057 CaseCluster &CC = Clusters[SrcIndex];
2058 const ConstantInt *CaseVal = CC.Low;
2059 MachineBasicBlock *Succ = CC.MBB;
2061 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2062 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2063 // If this case has the same successor and is a neighbour, merge it into
2064 // the previous cluster.
2065 Clusters[DstIndex - 1].High = CaseVal;
2066 Clusters[DstIndex - 1].Weight += CC.Weight;
2067 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2069 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2070 sizeof(Clusters[SrcIndex]));
2073 Clusters.resize(DstIndex);
2076 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2077 MachineBasicBlock *Last) {
2079 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2080 if (JTCases[i].first.HeaderBB == First)
2081 JTCases[i].first.HeaderBB = Last;
2083 // Update BitTestCases.
2084 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2085 if (BitTestCases[i].Parent == First)
2086 BitTestCases[i].Parent = Last;
2089 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2090 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2092 // Update machine-CFG edges with unique successors.
2093 SmallSet<BasicBlock*, 32> Done;
2094 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2095 BasicBlock *BB = I.getSuccessor(i);
2096 bool Inserted = Done.insert(BB).second;
2100 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2101 addSuccessorWithWeight(IndirectBrMBB, Succ);
2104 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2105 MVT::Other, getControlRoot(),
2106 getValue(I.getAddress())));
2109 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2110 if (DAG.getTarget().Options.TrapUnreachable)
2111 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2114 void SelectionDAGBuilder::visitFSub(const User &I) {
2115 // -0.0 - X --> fneg
2116 Type *Ty = I.getType();
2117 if (isa<Constant>(I.getOperand(0)) &&
2118 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2119 SDValue Op2 = getValue(I.getOperand(1));
2120 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2121 Op2.getValueType(), Op2));
2125 visitBinary(I, ISD::FSUB);
2128 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2129 SDValue Op1 = getValue(I.getOperand(0));
2130 SDValue Op2 = getValue(I.getOperand(1));
2137 if (const OverflowingBinaryOperator *OFBinOp =
2138 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2139 nuw = OFBinOp->hasNoUnsignedWrap();
2140 nsw = OFBinOp->hasNoSignedWrap();
2142 if (const PossiblyExactOperator *ExactOp =
2143 dyn_cast<const PossiblyExactOperator>(&I))
2144 exact = ExactOp->isExact();
2145 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2146 FMF = FPOp->getFastMathFlags();
2149 Flags.setExact(exact);
2150 Flags.setNoSignedWrap(nsw);
2151 Flags.setNoUnsignedWrap(nuw);
2152 if (EnableFMFInDAG) {
2153 Flags.setAllowReciprocal(FMF.allowReciprocal());
2154 Flags.setNoInfs(FMF.noInfs());
2155 Flags.setNoNaNs(FMF.noNaNs());
2156 Flags.setNoSignedZeros(FMF.noSignedZeros());
2157 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2159 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2161 setValue(&I, BinNodeValue);
2164 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2165 SDValue Op1 = getValue(I.getOperand(0));
2166 SDValue Op2 = getValue(I.getOperand(1));
2168 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2169 Op2.getValueType(), DAG.getDataLayout());
2171 // Coerce the shift amount to the right type if we can.
2172 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2173 unsigned ShiftSize = ShiftTy.getSizeInBits();
2174 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2175 SDLoc DL = getCurSDLoc();
2177 // If the operand is smaller than the shift count type, promote it.
2178 if (ShiftSize > Op2Size)
2179 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2181 // If the operand is larger than the shift count type but the shift
2182 // count type has enough bits to represent any shift value, truncate
2183 // it now. This is a common case and it exposes the truncate to
2184 // optimization early.
2185 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2186 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2187 // Otherwise we'll need to temporarily settle for some other convenient
2188 // type. Type legalization will make adjustments once the shiftee is split.
2190 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2197 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2199 if (const OverflowingBinaryOperator *OFBinOp =
2200 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2201 nuw = OFBinOp->hasNoUnsignedWrap();
2202 nsw = OFBinOp->hasNoSignedWrap();
2204 if (const PossiblyExactOperator *ExactOp =
2205 dyn_cast<const PossiblyExactOperator>(&I))
2206 exact = ExactOp->isExact();
2209 Flags.setExact(exact);
2210 Flags.setNoSignedWrap(nsw);
2211 Flags.setNoUnsignedWrap(nuw);
2212 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2217 void SelectionDAGBuilder::visitSDiv(const User &I) {
2218 SDValue Op1 = getValue(I.getOperand(0));
2219 SDValue Op2 = getValue(I.getOperand(1));
2222 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2223 cast<PossiblyExactOperator>(&I)->isExact());
2224 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2228 void SelectionDAGBuilder::visitICmp(const User &I) {
2229 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2230 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2231 predicate = IC->getPredicate();
2232 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2233 predicate = ICmpInst::Predicate(IC->getPredicate());
2234 SDValue Op1 = getValue(I.getOperand(0));
2235 SDValue Op2 = getValue(I.getOperand(1));
2236 ISD::CondCode Opcode = getICmpCondCode(predicate);
2238 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2240 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2243 void SelectionDAGBuilder::visitFCmp(const User &I) {
2244 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2245 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2246 predicate = FC->getPredicate();
2247 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2248 predicate = FCmpInst::Predicate(FC->getPredicate());
2249 SDValue Op1 = getValue(I.getOperand(0));
2250 SDValue Op2 = getValue(I.getOperand(1));
2251 ISD::CondCode Condition = getFCmpCondCode(predicate);
2252 if (TM.Options.NoNaNsFPMath)
2253 Condition = getFCmpCodeWithoutNaN(Condition);
2254 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2256 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2259 void SelectionDAGBuilder::visitSelect(const User &I) {
2260 SmallVector<EVT, 4> ValueVTs;
2261 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2263 unsigned NumValues = ValueVTs.size();
2264 if (NumValues == 0) return;
2266 SmallVector<SDValue, 4> Values(NumValues);
2267 SDValue Cond = getValue(I.getOperand(0));
2268 SDValue LHSVal = getValue(I.getOperand(1));
2269 SDValue RHSVal = getValue(I.getOperand(2));
2270 auto BaseOps = {Cond};
2271 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2272 ISD::VSELECT : ISD::SELECT;
2274 // Min/max matching is only viable if all output VTs are the same.
2275 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2277 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2278 ISD::NodeType Opc = ISD::DELETED_NODE;
2280 case SPF_UMAX: Opc = ISD::UMAX; break;
2281 case SPF_UMIN: Opc = ISD::UMIN; break;
2282 case SPF_SMAX: Opc = ISD::SMAX; break;
2283 case SPF_SMIN: Opc = ISD::SMIN; break;
2287 EVT VT = ValueVTs[0];
2288 LLVMContext &Ctx = *DAG.getContext();
2289 auto &TLI = DAG.getTargetLoweringInfo();
2290 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2291 VT = TLI.getTypeToTransformTo(Ctx, VT);
2293 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2294 // If the underlying comparison instruction is used by any other instruction,
2295 // the consumed instructions won't be destroyed, so it is not profitable
2296 // to convert to a min/max.
2297 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2299 LHSVal = getValue(LHS);
2300 RHSVal = getValue(RHS);
2305 for (unsigned i = 0; i != NumValues; ++i) {
2306 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2307 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2308 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2309 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2310 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2314 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2315 DAG.getVTList(ValueVTs), Values));
2318 void SelectionDAGBuilder::visitTrunc(const User &I) {
2319 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2320 SDValue N = getValue(I.getOperand(0));
2321 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2323 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2326 void SelectionDAGBuilder::visitZExt(const User &I) {
2327 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2328 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2329 SDValue N = getValue(I.getOperand(0));
2330 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2332 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2335 void SelectionDAGBuilder::visitSExt(const User &I) {
2336 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2337 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2338 SDValue N = getValue(I.getOperand(0));
2339 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2341 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2344 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2345 // FPTrunc is never a no-op cast, no need to check
2346 SDValue N = getValue(I.getOperand(0));
2347 SDLoc dl = getCurSDLoc();
2348 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2349 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2350 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2351 DAG.getTargetConstant(
2352 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2355 void SelectionDAGBuilder::visitFPExt(const User &I) {
2356 // FPExt is never a no-op cast, no need to check
2357 SDValue N = getValue(I.getOperand(0));
2358 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2360 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2363 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2364 // FPToUI is never a no-op cast, no need to check
2365 SDValue N = getValue(I.getOperand(0));
2366 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2368 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2371 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2372 // FPToSI is never a no-op cast, no need to check
2373 SDValue N = getValue(I.getOperand(0));
2374 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2376 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2379 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2380 // UIToFP is never a no-op cast, no need to check
2381 SDValue N = getValue(I.getOperand(0));
2382 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2384 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2387 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2388 // SIToFP is never a no-op cast, no need to check
2389 SDValue N = getValue(I.getOperand(0));
2390 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2392 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2395 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2396 // What to do depends on the size of the integer and the size of the pointer.
2397 // We can either truncate, zero extend, or no-op, accordingly.
2398 SDValue N = getValue(I.getOperand(0));
2399 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2401 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2404 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2405 // What to do depends on the size of the integer and the size of the pointer.
2406 // We can either truncate, zero extend, or no-op, accordingly.
2407 SDValue N = getValue(I.getOperand(0));
2408 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2410 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2413 void SelectionDAGBuilder::visitBitCast(const User &I) {
2414 SDValue N = getValue(I.getOperand(0));
2415 SDLoc dl = getCurSDLoc();
2416 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2419 // BitCast assures us that source and destination are the same size so this is
2420 // either a BITCAST or a no-op.
2421 if (DestVT != N.getValueType())
2422 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2423 DestVT, N)); // convert types.
2424 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2425 // might fold any kind of constant expression to an integer constant and that
2426 // is not what we are looking for. Only regcognize a bitcast of a genuine
2427 // constant integer as an opaque constant.
2428 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2429 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2432 setValue(&I, N); // noop cast.
2435 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2437 const Value *SV = I.getOperand(0);
2438 SDValue N = getValue(SV);
2439 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2441 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2442 unsigned DestAS = I.getType()->getPointerAddressSpace();
2444 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2445 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2450 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2452 SDValue InVec = getValue(I.getOperand(0));
2453 SDValue InVal = getValue(I.getOperand(1));
2454 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2455 TLI.getVectorIdxTy(DAG.getDataLayout()));
2456 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2457 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2458 InVec, InVal, InIdx));
2461 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2463 SDValue InVec = getValue(I.getOperand(0));
2464 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2465 TLI.getVectorIdxTy(DAG.getDataLayout()));
2466 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2467 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2471 // Utility for visitShuffleVector - Return true if every element in Mask,
2472 // beginning from position Pos and ending in Pos+Size, falls within the
2473 // specified sequential range [L, L+Pos). or is undef.
2474 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2475 unsigned Pos, unsigned Size, int Low) {
2476 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2477 if (Mask[i] >= 0 && Mask[i] != Low)
2482 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2483 SDValue Src1 = getValue(I.getOperand(0));
2484 SDValue Src2 = getValue(I.getOperand(1));
2486 SmallVector<int, 8> Mask;
2487 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2488 unsigned MaskNumElts = Mask.size();
2490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2491 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2492 EVT SrcVT = Src1.getValueType();
2493 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2495 if (SrcNumElts == MaskNumElts) {
2496 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2501 // Normalize the shuffle vector since mask and vector length don't match.
2502 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2503 // Mask is longer than the source vectors and is a multiple of the source
2504 // vectors. We can use concatenate vector to make the mask and vectors
2506 if (SrcNumElts*2 == MaskNumElts) {
2507 // First check for Src1 in low and Src2 in high
2508 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2509 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2510 // The shuffle is concatenating two vectors together.
2511 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2515 // Then check for Src2 in low and Src1 in high
2516 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2517 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2518 // The shuffle is concatenating two vectors together.
2519 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2525 // Pad both vectors with undefs to make them the same length as the mask.
2526 unsigned NumConcat = MaskNumElts / SrcNumElts;
2527 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2528 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2529 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2531 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2532 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2536 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2537 getCurSDLoc(), VT, MOps1);
2538 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2539 getCurSDLoc(), VT, MOps2);
2541 // Readjust mask for new input vector length.
2542 SmallVector<int, 8> MappedOps;
2543 for (unsigned i = 0; i != MaskNumElts; ++i) {
2545 if (Idx >= (int)SrcNumElts)
2546 Idx -= SrcNumElts - MaskNumElts;
2547 MappedOps.push_back(Idx);
2550 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2555 if (SrcNumElts > MaskNumElts) {
2556 // Analyze the access pattern of the vector to see if we can extract
2557 // two subvectors and do the shuffle. The analysis is done by calculating
2558 // the range of elements the mask access on both vectors.
2559 int MinRange[2] = { static_cast<int>(SrcNumElts),
2560 static_cast<int>(SrcNumElts)};
2561 int MaxRange[2] = {-1, -1};
2563 for (unsigned i = 0; i != MaskNumElts; ++i) {
2569 if (Idx >= (int)SrcNumElts) {
2573 if (Idx > MaxRange[Input])
2574 MaxRange[Input] = Idx;
2575 if (Idx < MinRange[Input])
2576 MinRange[Input] = Idx;
2579 // Check if the access is smaller than the vector size and can we find
2580 // a reasonable extract index.
2581 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2583 int StartIdx[2]; // StartIdx to extract from
2584 for (unsigned Input = 0; Input < 2; ++Input) {
2585 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2586 RangeUse[Input] = 0; // Unused
2587 StartIdx[Input] = 0;
2591 // Find a good start index that is a multiple of the mask length. Then
2592 // see if the rest of the elements are in range.
2593 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2594 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2595 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2596 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2599 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2600 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2603 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2604 // Extract appropriate subvector and generate a vector shuffle
2605 for (unsigned Input = 0; Input < 2; ++Input) {
2606 SDValue &Src = Input == 0 ? Src1 : Src2;
2607 if (RangeUse[Input] == 0)
2608 Src = DAG.getUNDEF(VT);
2610 SDLoc dl = getCurSDLoc();
2612 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2613 DAG.getConstant(StartIdx[Input], dl,
2614 TLI.getVectorIdxTy(DAG.getDataLayout())));
2618 // Calculate new mask.
2619 SmallVector<int, 8> MappedOps;
2620 for (unsigned i = 0; i != MaskNumElts; ++i) {
2623 if (Idx < (int)SrcNumElts)
2626 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2628 MappedOps.push_back(Idx);
2631 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2637 // We can't use either concat vectors or extract subvectors so fall back to
2638 // replacing the shuffle with extract and build vector.
2639 // to insert and build vector.
2640 EVT EltVT = VT.getVectorElementType();
2641 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2642 SDLoc dl = getCurSDLoc();
2643 SmallVector<SDValue,8> Ops;
2644 for (unsigned i = 0; i != MaskNumElts; ++i) {
2649 Res = DAG.getUNDEF(EltVT);
2651 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2652 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2654 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2655 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2661 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2664 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2665 const Value *Op0 = I.getOperand(0);
2666 const Value *Op1 = I.getOperand(1);
2667 Type *AggTy = I.getType();
2668 Type *ValTy = Op1->getType();
2669 bool IntoUndef = isa<UndefValue>(Op0);
2670 bool FromUndef = isa<UndefValue>(Op1);
2672 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2674 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2675 SmallVector<EVT, 4> AggValueVTs;
2676 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2677 SmallVector<EVT, 4> ValValueVTs;
2678 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2680 unsigned NumAggValues = AggValueVTs.size();
2681 unsigned NumValValues = ValValueVTs.size();
2682 SmallVector<SDValue, 4> Values(NumAggValues);
2684 // Ignore an insertvalue that produces an empty object
2685 if (!NumAggValues) {
2686 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2690 SDValue Agg = getValue(Op0);
2692 // Copy the beginning value(s) from the original aggregate.
2693 for (; i != LinearIndex; ++i)
2694 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2695 SDValue(Agg.getNode(), Agg.getResNo() + i);
2696 // Copy values from the inserted value(s).
2698 SDValue Val = getValue(Op1);
2699 for (; i != LinearIndex + NumValValues; ++i)
2700 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2701 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2703 // Copy remaining value(s) from the original aggregate.
2704 for (; i != NumAggValues; ++i)
2705 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2706 SDValue(Agg.getNode(), Agg.getResNo() + i);
2708 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2709 DAG.getVTList(AggValueVTs), Values));
2712 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2713 const Value *Op0 = I.getOperand(0);
2714 Type *AggTy = Op0->getType();
2715 Type *ValTy = I.getType();
2716 bool OutOfUndef = isa<UndefValue>(Op0);
2718 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2721 SmallVector<EVT, 4> ValValueVTs;
2722 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2724 unsigned NumValValues = ValValueVTs.size();
2726 // Ignore a extractvalue that produces an empty object
2727 if (!NumValValues) {
2728 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2732 SmallVector<SDValue, 4> Values(NumValValues);
2734 SDValue Agg = getValue(Op0);
2735 // Copy out the selected value(s).
2736 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2737 Values[i - LinearIndex] =
2739 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2740 SDValue(Agg.getNode(), Agg.getResNo() + i);
2742 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2743 DAG.getVTList(ValValueVTs), Values));
2746 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2747 Value *Op0 = I.getOperand(0);
2748 // Note that the pointer operand may be a vector of pointers. Take the scalar
2749 // element which holds a pointer.
2750 Type *Ty = Op0->getType()->getScalarType();
2751 unsigned AS = Ty->getPointerAddressSpace();
2752 SDValue N = getValue(Op0);
2753 SDLoc dl = getCurSDLoc();
2755 // Normalize Vector GEP - all scalar operands should be converted to the
2757 unsigned VectorWidth = I.getType()->isVectorTy() ?
2758 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2760 if (VectorWidth && !N.getValueType().isVector()) {
2761 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2762 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2763 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2765 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2767 const Value *Idx = *OI;
2768 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2769 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2772 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2773 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2774 DAG.getConstant(Offset, dl, N.getValueType()));
2777 Ty = StTy->getElementType(Field);
2779 Ty = cast<SequentialType>(Ty)->getElementType();
2781 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2782 unsigned PtrSize = PtrTy.getSizeInBits();
2783 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2785 // If this is a scalar constant or a splat vector of constants,
2786 // handle it quickly.
2787 const auto *CI = dyn_cast<ConstantInt>(Idx);
2788 if (!CI && isa<ConstantDataVector>(Idx) &&
2789 cast<ConstantDataVector>(Idx)->getSplatValue())
2790 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2795 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2796 SDValue OffsVal = VectorWidth ?
2797 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2798 DAG.getConstant(Offs, dl, PtrTy);
2799 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2803 // N = N + Idx * ElementSize;
2804 SDValue IdxN = getValue(Idx);
2806 if (!IdxN.getValueType().isVector() && VectorWidth) {
2807 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2808 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2809 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2811 // If the index is smaller or larger than intptr_t, truncate or extend
2813 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2815 // If this is a multiply by a power of two, turn it into a shl
2816 // immediately. This is a very common case.
2817 if (ElementSize != 1) {
2818 if (ElementSize.isPowerOf2()) {
2819 unsigned Amt = ElementSize.logBase2();
2820 IdxN = DAG.getNode(ISD::SHL, dl,
2821 N.getValueType(), IdxN,
2822 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2824 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2825 IdxN = DAG.getNode(ISD::MUL, dl,
2826 N.getValueType(), IdxN, Scale);
2830 N = DAG.getNode(ISD::ADD, dl,
2831 N.getValueType(), N, IdxN);
2838 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2839 // If this is a fixed sized alloca in the entry block of the function,
2840 // allocate it statically on the stack.
2841 if (FuncInfo.StaticAllocaMap.count(&I))
2842 return; // getValue will auto-populate this.
2844 SDLoc dl = getCurSDLoc();
2845 Type *Ty = I.getAllocatedType();
2846 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2847 auto &DL = DAG.getDataLayout();
2848 uint64_t TySize = DL.getTypeAllocSize(Ty);
2850 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2852 SDValue AllocSize = getValue(I.getArraySize());
2854 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2855 if (AllocSize.getValueType() != IntPtr)
2856 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2858 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2860 DAG.getConstant(TySize, dl, IntPtr));
2862 // Handle alignment. If the requested alignment is less than or equal to
2863 // the stack alignment, ignore it. If the size is greater than or equal to
2864 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2865 unsigned StackAlign =
2866 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2867 if (Align <= StackAlign)
2870 // Round the size of the allocation up to the stack alignment size
2871 // by add SA-1 to the size.
2872 AllocSize = DAG.getNode(ISD::ADD, dl,
2873 AllocSize.getValueType(), AllocSize,
2874 DAG.getIntPtrConstant(StackAlign - 1, dl));
2876 // Mask out the low bits for alignment purposes.
2877 AllocSize = DAG.getNode(ISD::AND, dl,
2878 AllocSize.getValueType(), AllocSize,
2879 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2882 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2883 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2884 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2886 DAG.setRoot(DSA.getValue(1));
2888 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2891 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2893 return visitAtomicLoad(I);
2895 const Value *SV = I.getOperand(0);
2896 SDValue Ptr = getValue(SV);
2898 Type *Ty = I.getType();
2900 bool isVolatile = I.isVolatile();
2901 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2903 // The IR notion of invariant_load only guarantees that all *non-faulting*
2904 // invariant loads result in the same value. The MI notion of invariant load
2905 // guarantees that the load can be legally moved to any location within its
2906 // containing function. The MI notion of invariant_load is stronger than the
2907 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2908 // with a guarantee that the location being loaded from is dereferenceable
2909 // throughout the function's lifetime.
2911 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2912 isDereferenceablePointer(SV, DAG.getDataLayout());
2913 unsigned Alignment = I.getAlignment();
2916 I.getAAMetadata(AAInfo);
2917 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2920 SmallVector<EVT, 4> ValueVTs;
2921 SmallVector<uint64_t, 4> Offsets;
2922 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2923 unsigned NumValues = ValueVTs.size();
2928 bool ConstantMemory = false;
2929 if (isVolatile || NumValues > MaxParallelChains)
2930 // Serialize volatile loads with other side effects.
2932 else if (AA->pointsToConstantMemory(
2933 MemoryLocation(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2934 // Do not serialize (non-volatile) loads of constant memory with anything.
2935 Root = DAG.getEntryNode();
2936 ConstantMemory = true;
2938 // Do not serialize non-volatile loads against each other.
2939 Root = DAG.getRoot();
2942 SDLoc dl = getCurSDLoc();
2945 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2947 SmallVector<SDValue, 4> Values(NumValues);
2948 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
2949 EVT PtrVT = Ptr.getValueType();
2950 unsigned ChainI = 0;
2951 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2952 // Serializing loads here may result in excessive register pressure, and
2953 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2954 // could recover a bit by hoisting nodes upward in the chain by recognizing
2955 // they are side-effect free or do not alias. The optimizer should really
2956 // avoid this case by converting large object/array copies to llvm.memcpy
2957 // (MaxParallelChains should always remain as failsafe).
2958 if (ChainI == MaxParallelChains) {
2959 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2960 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2961 makeArrayRef(Chains.data(), ChainI));
2965 SDValue A = DAG.getNode(ISD::ADD, dl,
2967 DAG.getConstant(Offsets[i], dl, PtrVT));
2968 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2969 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2970 isNonTemporal, isInvariant, Alignment, AAInfo,
2974 Chains[ChainI] = L.getValue(1);
2977 if (!ConstantMemory) {
2978 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2979 makeArrayRef(Chains.data(), ChainI));
2983 PendingLoads.push_back(Chain);
2986 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2987 DAG.getVTList(ValueVTs), Values));
2990 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2992 return visitAtomicStore(I);
2994 const Value *SrcV = I.getOperand(0);
2995 const Value *PtrV = I.getOperand(1);
2997 SmallVector<EVT, 4> ValueVTs;
2998 SmallVector<uint64_t, 4> Offsets;
2999 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3000 SrcV->getType(), ValueVTs, &Offsets);
3001 unsigned NumValues = ValueVTs.size();
3005 // Get the lowered operands. Note that we do this after
3006 // checking if NumResults is zero, because with zero results
3007 // the operands won't have values in the map.
3008 SDValue Src = getValue(SrcV);
3009 SDValue Ptr = getValue(PtrV);
3011 SDValue Root = getRoot();
3012 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3013 EVT PtrVT = Ptr.getValueType();
3014 bool isVolatile = I.isVolatile();
3015 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3016 unsigned Alignment = I.getAlignment();
3017 SDLoc dl = getCurSDLoc();
3020 I.getAAMetadata(AAInfo);
3022 unsigned ChainI = 0;
3023 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3024 // See visitLoad comments.
3025 if (ChainI == MaxParallelChains) {
3026 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3027 makeArrayRef(Chains.data(), ChainI));
3031 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3032 DAG.getConstant(Offsets[i], dl, PtrVT));
3033 SDValue St = DAG.getStore(Root, dl,
3034 SDValue(Src.getNode(), Src.getResNo() + i),
3035 Add, MachinePointerInfo(PtrV, Offsets[i]),
3036 isVolatile, isNonTemporal, Alignment, AAInfo);
3037 Chains[ChainI] = St;
3040 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3041 makeArrayRef(Chains.data(), ChainI));
3042 DAG.setRoot(StoreNode);
3045 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3046 SDLoc sdl = getCurSDLoc();
3048 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3049 Value *PtrOperand = I.getArgOperand(1);
3050 SDValue Ptr = getValue(PtrOperand);
3051 SDValue Src0 = getValue(I.getArgOperand(0));
3052 SDValue Mask = getValue(I.getArgOperand(3));
3053 EVT VT = Src0.getValueType();
3054 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3056 Alignment = DAG.getEVTAlignment(VT);
3059 I.getAAMetadata(AAInfo);
3061 MachineMemOperand *MMO =
3062 DAG.getMachineFunction().
3063 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3064 MachineMemOperand::MOStore, VT.getStoreSize(),
3066 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3068 DAG.setRoot(StoreNode);
3069 setValue(&I, StoreNode);
3072 // Gather/scatter receive a vector of pointers.
3073 // This vector of pointers may be represented as a base pointer + vector of
3074 // indices, it depends on GEP and instruction preceeding GEP
3075 // that calculates indices
3076 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3077 SelectionDAGBuilder* SDB) {
3079 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3080 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3081 if (!Gep || Gep->getNumOperands() > 2)
3083 ShuffleVectorInst *ShuffleInst =
3084 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3085 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3086 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3087 Instruction::InsertElement)
3090 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3092 SelectionDAG& DAG = SDB->DAG;
3093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3094 // Check is the Ptr is inside current basic block
3095 // If not, look for the shuffle instruction
3096 if (SDB->findValue(Ptr))
3097 Base = SDB->getValue(Ptr);
3098 else if (SDB->findValue(ShuffleInst)) {
3099 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3100 SDLoc sdl = ShuffleNode;
3102 ISD::EXTRACT_VECTOR_ELT, sdl,
3103 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3104 DAG.getConstant(0, sdl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3105 SDB->setValue(Ptr, Base);
3110 Value *IndexVal = Gep->getOperand(1);
3111 if (SDB->findValue(IndexVal)) {
3112 Index = SDB->getValue(IndexVal);
3114 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3115 IndexVal = Sext->getOperand(0);
3116 if (SDB->findValue(IndexVal))
3117 Index = SDB->getValue(IndexVal);
3124 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3125 SDLoc sdl = getCurSDLoc();
3127 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3128 Value *Ptr = I.getArgOperand(1);
3129 SDValue Src0 = getValue(I.getArgOperand(0));
3130 SDValue Mask = getValue(I.getArgOperand(3));
3131 EVT VT = Src0.getValueType();
3132 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3134 Alignment = DAG.getEVTAlignment(VT);
3135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3138 I.getAAMetadata(AAInfo);
3142 Value *BasePtr = Ptr;
3143 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3145 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3146 MachineMemOperand *MMO = DAG.getMachineFunction().
3147 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3148 MachineMemOperand::MOStore, VT.getStoreSize(),
3151 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3152 Index = getValue(Ptr);
3154 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3155 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3157 DAG.setRoot(Scatter);
3158 setValue(&I, Scatter);
3161 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3162 SDLoc sdl = getCurSDLoc();
3164 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3165 Value *PtrOperand = I.getArgOperand(0);
3166 SDValue Ptr = getValue(PtrOperand);
3167 SDValue Src0 = getValue(I.getArgOperand(3));
3168 SDValue Mask = getValue(I.getArgOperand(2));
3170 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3171 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3172 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3174 Alignment = DAG.getEVTAlignment(VT);
3177 I.getAAMetadata(AAInfo);
3178 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3180 SDValue InChain = DAG.getRoot();
3181 if (AA->pointsToConstantMemory(MemoryLocation(
3182 PtrOperand, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3183 // Do not serialize (non-volatile) loads of constant memory with anything.
3184 InChain = DAG.getEntryNode();
3187 MachineMemOperand *MMO =
3188 DAG.getMachineFunction().
3189 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3190 MachineMemOperand::MOLoad, VT.getStoreSize(),
3191 Alignment, AAInfo, Ranges);
3193 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3195 SDValue OutChain = Load.getValue(1);
3196 DAG.setRoot(OutChain);
3200 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3201 SDLoc sdl = getCurSDLoc();
3203 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3204 Value *Ptr = I.getArgOperand(0);
3205 SDValue Src0 = getValue(I.getArgOperand(3));
3206 SDValue Mask = getValue(I.getArgOperand(2));
3208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3209 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3210 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3212 Alignment = DAG.getEVTAlignment(VT);
3215 I.getAAMetadata(AAInfo);
3216 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3218 SDValue Root = DAG.getRoot();
3221 Value *BasePtr = Ptr;
3222 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3223 bool ConstantMemory = false;
3225 AA->pointsToConstantMemory(
3226 MemoryLocation(BasePtr, AA->getTypeStoreSize(I.getType()), AAInfo))) {
3227 // Do not serialize (non-volatile) loads of constant memory with anything.
3228 Root = DAG.getEntryNode();
3229 ConstantMemory = true;
3232 MachineMemOperand *MMO =
3233 DAG.getMachineFunction().
3234 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3235 MachineMemOperand::MOLoad, VT.getStoreSize(),
3236 Alignment, AAInfo, Ranges);
3239 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3240 Index = getValue(Ptr);
3242 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3243 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3246 SDValue OutChain = Gather.getValue(1);
3247 if (!ConstantMemory)
3248 PendingLoads.push_back(OutChain);
3249 setValue(&I, Gather);
3252 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3253 SDLoc dl = getCurSDLoc();
3254 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3255 AtomicOrdering FailureOrder = I.getFailureOrdering();
3256 SynchronizationScope Scope = I.getSynchScope();
3258 SDValue InChain = getRoot();
3260 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3261 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3262 SDValue L = DAG.getAtomicCmpSwap(
3263 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3264 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3265 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3266 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3268 SDValue OutChain = L.getValue(2);
3271 DAG.setRoot(OutChain);
3274 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3275 SDLoc dl = getCurSDLoc();
3277 switch (I.getOperation()) {
3278 default: llvm_unreachable("Unknown atomicrmw operation");
3279 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3280 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3281 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3282 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3283 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3284 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3285 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3286 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3287 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3288 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3289 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3291 AtomicOrdering Order = I.getOrdering();
3292 SynchronizationScope Scope = I.getSynchScope();
3294 SDValue InChain = getRoot();
3297 DAG.getAtomic(NT, dl,
3298 getValue(I.getValOperand()).getSimpleValueType(),
3300 getValue(I.getPointerOperand()),
3301 getValue(I.getValOperand()),
3302 I.getPointerOperand(),
3303 /* Alignment=*/ 0, Order, Scope);
3305 SDValue OutChain = L.getValue(1);
3308 DAG.setRoot(OutChain);
3311 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3312 SDLoc dl = getCurSDLoc();
3313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3316 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3317 TLI.getPointerTy(DAG.getDataLayout()));
3318 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3319 TLI.getPointerTy(DAG.getDataLayout()));
3320 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3323 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3324 SDLoc dl = getCurSDLoc();
3325 AtomicOrdering Order = I.getOrdering();
3326 SynchronizationScope Scope = I.getSynchScope();
3328 SDValue InChain = getRoot();
3330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3331 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3333 if (I.getAlignment() < VT.getSizeInBits() / 8)
3334 report_fatal_error("Cannot generate unaligned atomic load");
3336 MachineMemOperand *MMO =
3337 DAG.getMachineFunction().
3338 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3339 MachineMemOperand::MOVolatile |
3340 MachineMemOperand::MOLoad,
3342 I.getAlignment() ? I.getAlignment() :
3343 DAG.getEVTAlignment(VT));
3345 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3347 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3348 getValue(I.getPointerOperand()), MMO,
3351 SDValue OutChain = L.getValue(1);
3354 DAG.setRoot(OutChain);
3357 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3358 SDLoc dl = getCurSDLoc();
3360 AtomicOrdering Order = I.getOrdering();
3361 SynchronizationScope Scope = I.getSynchScope();
3363 SDValue InChain = getRoot();
3365 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3367 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3369 if (I.getAlignment() < VT.getSizeInBits() / 8)
3370 report_fatal_error("Cannot generate unaligned atomic store");
3373 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3375 getValue(I.getPointerOperand()),
3376 getValue(I.getValueOperand()),
3377 I.getPointerOperand(), I.getAlignment(),
3380 DAG.setRoot(OutChain);
3383 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3385 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3386 unsigned Intrinsic) {
3387 bool HasChain = !I.doesNotAccessMemory();
3388 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3390 // Build the operand list.
3391 SmallVector<SDValue, 8> Ops;
3392 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3394 // We don't need to serialize loads against other loads.
3395 Ops.push_back(DAG.getRoot());
3397 Ops.push_back(getRoot());
3401 // Info is set by getTgtMemInstrinsic
3402 TargetLowering::IntrinsicInfo Info;
3403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3404 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3406 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3407 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3408 Info.opc == ISD::INTRINSIC_W_CHAIN)
3409 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3410 TLI.getPointerTy(DAG.getDataLayout())));
3412 // Add all operands of the call to the operand list.
3413 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3414 SDValue Op = getValue(I.getArgOperand(i));
3418 SmallVector<EVT, 4> ValueVTs;
3419 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3422 ValueVTs.push_back(MVT::Other);
3424 SDVTList VTs = DAG.getVTList(ValueVTs);
3428 if (IsTgtIntrinsic) {
3429 // This is target intrinsic that touches memory
3430 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3431 VTs, Ops, Info.memVT,
3432 MachinePointerInfo(Info.ptrVal, Info.offset),
3433 Info.align, Info.vol,
3434 Info.readMem, Info.writeMem, Info.size);
3435 } else if (!HasChain) {
3436 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3437 } else if (!I.getType()->isVoidTy()) {
3438 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3440 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3444 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3446 PendingLoads.push_back(Chain);
3451 if (!I.getType()->isVoidTy()) {
3452 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3453 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3454 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3457 setValue(&I, Result);
3461 /// GetSignificand - Get the significand and build it into a floating-point
3462 /// number with exponent of 1:
3464 /// Op = (Op & 0x007fffff) | 0x3f800000;
3466 /// where Op is the hexadecimal representation of floating point value.
3468 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3469 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3470 DAG.getConstant(0x007fffff, dl, MVT::i32));
3471 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3472 DAG.getConstant(0x3f800000, dl, MVT::i32));
3473 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3476 /// GetExponent - Get the exponent:
3478 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3480 /// where Op is the hexadecimal representation of floating point value.
3482 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3484 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3485 DAG.getConstant(0x7f800000, dl, MVT::i32));
3486 SDValue t1 = DAG.getNode(
3487 ISD::SRL, dl, MVT::i32, t0,
3488 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3489 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3490 DAG.getConstant(127, dl, MVT::i32));
3491 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3494 /// getF32Constant - Get 32-bit floating point constant.
3496 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3497 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3501 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3502 SelectionDAG &DAG) {
3503 // IntegerPartOfX = ((int32_t)(t0);
3504 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3506 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3507 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3508 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3510 // IntegerPartOfX <<= 23;
3511 IntegerPartOfX = DAG.getNode(
3512 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3513 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3514 DAG.getDataLayout())));
3516 SDValue TwoToFractionalPartOfX;
3517 if (LimitFloatPrecision <= 6) {
3518 // For floating-point precision of 6:
3520 // TwoToFractionalPartOfX =
3522 // (0.735607626f + 0.252464424f * x) * x;
3524 // error 0.0144103317, which is 6 bits
3525 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3526 getF32Constant(DAG, 0x3e814304, dl));
3527 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3528 getF32Constant(DAG, 0x3f3c50c8, dl));
3529 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3530 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3531 getF32Constant(DAG, 0x3f7f5e7e, dl));
3532 } else if (LimitFloatPrecision <= 12) {
3533 // For floating-point precision of 12:
3535 // TwoToFractionalPartOfX =
3538 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3540 // error 0.000107046256, which is 13 to 14 bits
3541 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3542 getF32Constant(DAG, 0x3da235e3, dl));
3543 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3544 getF32Constant(DAG, 0x3e65b8f3, dl));
3545 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3546 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3547 getF32Constant(DAG, 0x3f324b07, dl));
3548 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3549 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3550 getF32Constant(DAG, 0x3f7ff8fd, dl));
3551 } else { // LimitFloatPrecision <= 18
3552 // For floating-point precision of 18:
3554 // TwoToFractionalPartOfX =
3558 // (0.554906021e-1f +
3559 // (0.961591928e-2f +
3560 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3561 // error 2.47208000*10^(-7), which is better than 18 bits
3562 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3563 getF32Constant(DAG, 0x3924b03e, dl));
3564 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3565 getF32Constant(DAG, 0x3ab24b87, dl));
3566 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3567 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3568 getF32Constant(DAG, 0x3c1d8c17, dl));
3569 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3570 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3571 getF32Constant(DAG, 0x3d634a1d, dl));
3572 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3573 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3574 getF32Constant(DAG, 0x3e75fe14, dl));
3575 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3576 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3577 getF32Constant(DAG, 0x3f317234, dl));
3578 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3579 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3580 getF32Constant(DAG, 0x3f800000, dl));
3583 // Add the exponent into the result in integer domain.
3584 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3585 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3586 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3589 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3590 /// limited-precision mode.
3591 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3592 const TargetLowering &TLI) {
3593 if (Op.getValueType() == MVT::f32 &&
3594 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3596 // Put the exponent in the right bit position for later addition to the
3599 // #define LOG2OFe 1.4426950f
3600 // t0 = Op * LOG2OFe
3601 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3602 getF32Constant(DAG, 0x3fb8aa3b, dl));
3603 return getLimitedPrecisionExp2(t0, dl, DAG);
3606 // No special expansion.
3607 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3610 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3611 /// limited-precision mode.
3612 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3613 const TargetLowering &TLI) {
3614 if (Op.getValueType() == MVT::f32 &&
3615 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3616 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3618 // Scale the exponent by log(2) [0.69314718f].
3619 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3620 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3621 getF32Constant(DAG, 0x3f317218, dl));
3623 // Get the significand and build it into a floating-point number with
3625 SDValue X = GetSignificand(DAG, Op1, dl);
3627 SDValue LogOfMantissa;
3628 if (LimitFloatPrecision <= 6) {
3629 // For floating-point precision of 6:
3633 // (1.4034025f - 0.23903021f * x) * x;
3635 // error 0.0034276066, which is better than 8 bits
3636 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3637 getF32Constant(DAG, 0xbe74c456, dl));
3638 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3639 getF32Constant(DAG, 0x3fb3a2b1, dl));
3640 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3641 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3642 getF32Constant(DAG, 0x3f949a29, dl));
3643 } else if (LimitFloatPrecision <= 12) {
3644 // For floating-point precision of 12:
3650 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3652 // error 0.000061011436, which is 14 bits
3653 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3654 getF32Constant(DAG, 0xbd67b6d6, dl));
3655 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3656 getF32Constant(DAG, 0x3ee4f4b8, dl));
3657 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3658 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3659 getF32Constant(DAG, 0x3fbc278b, dl));
3660 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3661 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3662 getF32Constant(DAG, 0x40348e95, dl));
3663 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3664 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3665 getF32Constant(DAG, 0x3fdef31a, dl));
3666 } else { // LimitFloatPrecision <= 18
3667 // For floating-point precision of 18:
3675 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3677 // error 0.0000023660568, which is better than 18 bits
3678 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3679 getF32Constant(DAG, 0xbc91e5ac, dl));
3680 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3681 getF32Constant(DAG, 0x3e4350aa, dl));
3682 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3683 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3684 getF32Constant(DAG, 0x3f60d3e3, dl));
3685 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3686 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3687 getF32Constant(DAG, 0x4011cdf0, dl));
3688 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3689 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3690 getF32Constant(DAG, 0x406cfd1c, dl));
3691 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3692 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3693 getF32Constant(DAG, 0x408797cb, dl));
3694 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3695 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3696 getF32Constant(DAG, 0x4006dcab, dl));
3699 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3702 // No special expansion.
3703 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3706 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3707 /// limited-precision mode.
3708 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3709 const TargetLowering &TLI) {
3710 if (Op.getValueType() == MVT::f32 &&
3711 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3712 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3714 // Get the exponent.
3715 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3717 // Get the significand and build it into a floating-point number with
3719 SDValue X = GetSignificand(DAG, Op1, dl);
3721 // Different possible minimax approximations of significand in
3722 // floating-point for various degrees of accuracy over [1,2].
3723 SDValue Log2ofMantissa;
3724 if (LimitFloatPrecision <= 6) {
3725 // For floating-point precision of 6:
3727 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3729 // error 0.0049451742, which is more than 7 bits
3730 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3731 getF32Constant(DAG, 0xbeb08fe0, dl));
3732 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3733 getF32Constant(DAG, 0x40019463, dl));
3734 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3735 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3736 getF32Constant(DAG, 0x3fd6633d, dl));
3737 } else if (LimitFloatPrecision <= 12) {
3738 // For floating-point precision of 12:
3744 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3746 // error 0.0000876136000, which is better than 13 bits
3747 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3748 getF32Constant(DAG, 0xbda7262e, dl));
3749 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3750 getF32Constant(DAG, 0x3f25280b, dl));
3751 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3752 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3753 getF32Constant(DAG, 0x4007b923, dl));
3754 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3755 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3756 getF32Constant(DAG, 0x40823e2f, dl));
3757 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3758 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3759 getF32Constant(DAG, 0x4020d29c, dl));
3760 } else { // LimitFloatPrecision <= 18
3761 // For floating-point precision of 18:
3770 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3772 // error 0.0000018516, which is better than 18 bits
3773 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3774 getF32Constant(DAG, 0xbcd2769e, dl));
3775 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3776 getF32Constant(DAG, 0x3e8ce0b9, dl));
3777 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3778 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3779 getF32Constant(DAG, 0x3fa22ae7, dl));
3780 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3781 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3782 getF32Constant(DAG, 0x40525723, dl));
3783 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3784 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3785 getF32Constant(DAG, 0x40aaf200, dl));
3786 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3787 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3788 getF32Constant(DAG, 0x40c39dad, dl));
3789 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3790 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3791 getF32Constant(DAG, 0x4042902c, dl));
3794 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3797 // No special expansion.
3798 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3801 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3802 /// limited-precision mode.
3803 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3804 const TargetLowering &TLI) {
3805 if (Op.getValueType() == MVT::f32 &&
3806 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3807 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3809 // Scale the exponent by log10(2) [0.30102999f].
3810 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3811 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3812 getF32Constant(DAG, 0x3e9a209a, dl));
3814 // Get the significand and build it into a floating-point number with
3816 SDValue X = GetSignificand(DAG, Op1, dl);
3818 SDValue Log10ofMantissa;
3819 if (LimitFloatPrecision <= 6) {
3820 // For floating-point precision of 6:
3822 // Log10ofMantissa =
3824 // (0.60948995f - 0.10380950f * x) * x;
3826 // error 0.0014886165, which is 6 bits
3827 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3828 getF32Constant(DAG, 0xbdd49a13, dl));
3829 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3830 getF32Constant(DAG, 0x3f1c0789, dl));
3831 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3832 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3833 getF32Constant(DAG, 0x3f011300, dl));
3834 } else if (LimitFloatPrecision <= 12) {
3835 // For floating-point precision of 12:
3837 // Log10ofMantissa =
3840 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3842 // error 0.00019228036, which is better than 12 bits
3843 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3844 getF32Constant(DAG, 0x3d431f31, dl));
3845 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3846 getF32Constant(DAG, 0x3ea21fb2, dl));
3847 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3848 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3849 getF32Constant(DAG, 0x3f6ae232, dl));
3850 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3851 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3852 getF32Constant(DAG, 0x3f25f7c3, dl));
3853 } else { // LimitFloatPrecision <= 18
3854 // For floating-point precision of 18:
3856 // Log10ofMantissa =
3861 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3863 // error 0.0000037995730, which is better than 18 bits
3864 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3865 getF32Constant(DAG, 0x3c5d51ce, dl));
3866 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3867 getF32Constant(DAG, 0x3e00685a, dl));
3868 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3869 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3870 getF32Constant(DAG, 0x3efb6798, dl));
3871 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3872 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3873 getF32Constant(DAG, 0x3f88d192, dl));
3874 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3875 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3876 getF32Constant(DAG, 0x3fc4316c, dl));
3877 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3878 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3879 getF32Constant(DAG, 0x3f57ce70, dl));
3882 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3885 // No special expansion.
3886 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3889 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3890 /// limited-precision mode.
3891 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3892 const TargetLowering &TLI) {
3893 if (Op.getValueType() == MVT::f32 &&
3894 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3895 return getLimitedPrecisionExp2(Op, dl, DAG);
3897 // No special expansion.
3898 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3901 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3902 /// limited-precision mode with x == 10.0f.
3903 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3904 SelectionDAG &DAG, const TargetLowering &TLI) {
3905 bool IsExp10 = false;
3906 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3907 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3908 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3910 IsExp10 = LHSC->isExactlyValue(Ten);
3915 // Put the exponent in the right bit position for later addition to the
3918 // #define LOG2OF10 3.3219281f
3919 // t0 = Op * LOG2OF10;
3920 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3921 getF32Constant(DAG, 0x40549a78, dl));
3922 return getLimitedPrecisionExp2(t0, dl, DAG);
3925 // No special expansion.
3926 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3930 /// ExpandPowI - Expand a llvm.powi intrinsic.
3931 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3932 SelectionDAG &DAG) {
3933 // If RHS is a constant, we can expand this out to a multiplication tree,
3934 // otherwise we end up lowering to a call to __powidf2 (for example). When
3935 // optimizing for size, we only want to do this if the expansion would produce
3936 // a small number of multiplies, otherwise we do the full expansion.
3937 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3938 // Get the exponent as a positive value.
3939 unsigned Val = RHSC->getSExtValue();
3940 if ((int)Val < 0) Val = -Val;
3942 // powi(x, 0) -> 1.0
3944 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3946 const Function *F = DAG.getMachineFunction().getFunction();
3947 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3948 // If optimizing for size, don't insert too many multiplies. This
3949 // inserts up to 5 multiplies.
3950 countPopulation(Val) + Log2_32(Val) < 7) {
3951 // We use the simple binary decomposition method to generate the multiply
3952 // sequence. There are more optimal ways to do this (for example,
3953 // powi(x,15) generates one more multiply than it should), but this has
3954 // the benefit of being both really simple and much better than a libcall.
3955 SDValue Res; // Logically starts equal to 1.0
3956 SDValue CurSquare = LHS;
3960 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3962 Res = CurSquare; // 1.0*CurSquare.
3965 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3966 CurSquare, CurSquare);
3970 // If the original was negative, invert the result, producing 1/(x*x*x).
3971 if (RHSC->getSExtValue() < 0)
3972 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3973 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3978 // Otherwise, expand to a libcall.
3979 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3982 // getTruncatedArgReg - Find underlying register used for an truncated
3984 static unsigned getTruncatedArgReg(const SDValue &N) {
3985 if (N.getOpcode() != ISD::TRUNCATE)
3988 const SDValue &Ext = N.getOperand(0);
3989 if (Ext.getOpcode() == ISD::AssertZext ||
3990 Ext.getOpcode() == ISD::AssertSext) {
3991 const SDValue &CFR = Ext.getOperand(0);
3992 if (CFR.getOpcode() == ISD::CopyFromReg)
3993 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3994 if (CFR.getOpcode() == ISD::TRUNCATE)
3995 return getTruncatedArgReg(CFR);
4000 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4001 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4002 /// At the end of instruction selection, they will be inserted to the entry BB.
4003 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4004 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4005 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4006 const Argument *Arg = dyn_cast<Argument>(V);
4010 MachineFunction &MF = DAG.getMachineFunction();
4011 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4013 // Ignore inlined function arguments here.
4015 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4016 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4019 Optional<MachineOperand> Op;
4020 // Some arguments' frame index is recorded during argument lowering.
4021 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4022 Op = MachineOperand::CreateFI(FI);
4024 if (!Op && N.getNode()) {
4026 if (N.getOpcode() == ISD::CopyFromReg)
4027 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4029 Reg = getTruncatedArgReg(N);
4030 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4031 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4032 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4037 Op = MachineOperand::CreateReg(Reg, false);
4041 // Check if ValueMap has reg number.
4042 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4043 if (VMI != FuncInfo.ValueMap.end())
4044 Op = MachineOperand::CreateReg(VMI->second, false);
4047 if (!Op && N.getNode())
4048 // Check if frame index is available.
4049 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4050 if (FrameIndexSDNode *FINode =
4051 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4052 Op = MachineOperand::CreateFI(FINode->getIndex());
4057 assert(Variable->isValidLocationForIntrinsic(DL) &&
4058 "Expected inlined-at fields to agree");
4060 FuncInfo.ArgDbgValues.push_back(
4061 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4062 Op->getReg(), Offset, Variable, Expr));
4064 FuncInfo.ArgDbgValues.push_back(
4065 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4068 .addMetadata(Variable)
4069 .addMetadata(Expr));
4074 // VisualStudio defines setjmp as _setjmp
4075 #if defined(_MSC_VER) && defined(setjmp) && \
4076 !defined(setjmp_undefined_for_msvc)
4077 # pragma push_macro("setjmp")
4079 # define setjmp_undefined_for_msvc
4082 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4083 /// we want to emit this as a call to a named external function, return the name
4084 /// otherwise lower it and return null.
4086 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4087 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4088 SDLoc sdl = getCurSDLoc();
4089 DebugLoc dl = getCurDebugLoc();
4092 switch (Intrinsic) {
4094 // By default, turn this into a target intrinsic node.
4095 visitTargetIntrinsic(I, Intrinsic);
4097 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4098 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4099 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4100 case Intrinsic::returnaddress:
4101 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4102 TLI.getPointerTy(DAG.getDataLayout()),
4103 getValue(I.getArgOperand(0))));
4105 case Intrinsic::frameaddress:
4106 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4107 TLI.getPointerTy(DAG.getDataLayout()),
4108 getValue(I.getArgOperand(0))));
4110 case Intrinsic::read_register: {
4111 Value *Reg = I.getArgOperand(0);
4112 SDValue Chain = getRoot();
4114 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4115 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4116 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4117 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4119 DAG.setRoot(Res.getValue(1));
4122 case Intrinsic::write_register: {
4123 Value *Reg = I.getArgOperand(0);
4124 Value *RegValue = I.getArgOperand(1);
4125 SDValue Chain = getRoot();
4127 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4128 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4129 RegName, getValue(RegValue)));
4132 case Intrinsic::setjmp:
4133 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4134 case Intrinsic::longjmp:
4135 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4136 case Intrinsic::memcpy: {
4137 // FIXME: this definition of "user defined address space" is x86-specific
4138 // Assert for address < 256 since we support only user defined address
4140 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4142 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4144 "Unknown address space");
4145 SDValue Op1 = getValue(I.getArgOperand(0));
4146 SDValue Op2 = getValue(I.getArgOperand(1));
4147 SDValue Op3 = getValue(I.getArgOperand(2));
4148 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4150 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4151 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4152 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4153 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4155 MachinePointerInfo(I.getArgOperand(0)),
4156 MachinePointerInfo(I.getArgOperand(1)));
4157 updateDAGForMaybeTailCall(MC);
4160 case Intrinsic::memset: {
4161 // FIXME: this definition of "user defined address space" is x86-specific
4162 // Assert for address < 256 since we support only user defined address
4164 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4166 "Unknown address space");
4167 SDValue Op1 = getValue(I.getArgOperand(0));
4168 SDValue Op2 = getValue(I.getArgOperand(1));
4169 SDValue Op3 = getValue(I.getArgOperand(2));
4170 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4172 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4173 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4174 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4175 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4176 isTC, MachinePointerInfo(I.getArgOperand(0)));
4177 updateDAGForMaybeTailCall(MS);
4180 case Intrinsic::memmove: {
4181 // FIXME: this definition of "user defined address space" is x86-specific
4182 // Assert for address < 256 since we support only user defined address
4184 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4186 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4188 "Unknown address space");
4189 SDValue Op1 = getValue(I.getArgOperand(0));
4190 SDValue Op2 = getValue(I.getArgOperand(1));
4191 SDValue Op3 = getValue(I.getArgOperand(2));
4192 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4194 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4195 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4196 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4197 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4198 isTC, MachinePointerInfo(I.getArgOperand(0)),
4199 MachinePointerInfo(I.getArgOperand(1)));
4200 updateDAGForMaybeTailCall(MM);
4203 case Intrinsic::dbg_declare: {
4204 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4205 DILocalVariable *Variable = DI.getVariable();
4206 DIExpression *Expression = DI.getExpression();
4207 const Value *Address = DI.getAddress();
4208 assert(Variable && "Missing variable");
4210 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4214 // Check if address has undef value.
4215 if (isa<UndefValue>(Address) ||
4216 (Address->use_empty() && !isa<Argument>(Address))) {
4217 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4221 SDValue &N = NodeMap[Address];
4222 if (!N.getNode() && isa<Argument>(Address))
4223 // Check unused arguments map.
4224 N = UnusedArgNodeMap[Address];
4227 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4228 Address = BCI->getOperand(0);
4229 // Parameters are handled specially.
4230 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4231 isa<Argument>(Address);
4233 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4235 if (isParameter && !AI) {
4236 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4238 // Byval parameter. We have a frame index at this point.
4239 SDV = DAG.getFrameIndexDbgValue(
4240 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4242 // Address is an argument, so try to emit its dbg value using
4243 // virtual register info from the FuncInfo.ValueMap.
4244 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4249 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4250 true, 0, dl, SDNodeOrder);
4252 // Can't do anything with other non-AI cases yet.
4253 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4254 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4255 DEBUG(Address->dump());
4258 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4260 // If Address is an argument then try to emit its dbg value using
4261 // virtual register info from the FuncInfo.ValueMap.
4262 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4264 // If variable is pinned by a alloca in dominating bb then
4265 // use StaticAllocaMap.
4266 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4267 if (AI->getParent() != DI.getParent()) {
4268 DenseMap<const AllocaInst*, int>::iterator SI =
4269 FuncInfo.StaticAllocaMap.find(AI);
4270 if (SI != FuncInfo.StaticAllocaMap.end()) {
4271 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4272 0, dl, SDNodeOrder);
4273 DAG.AddDbgValue(SDV, nullptr, false);
4278 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4283 case Intrinsic::dbg_value: {
4284 const DbgValueInst &DI = cast<DbgValueInst>(I);
4285 assert(DI.getVariable() && "Missing variable");
4287 DILocalVariable *Variable = DI.getVariable();
4288 DIExpression *Expression = DI.getExpression();
4289 uint64_t Offset = DI.getOffset();
4290 const Value *V = DI.getValue();
4295 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4296 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4298 DAG.AddDbgValue(SDV, nullptr, false);
4300 // Do not use getValue() in here; we don't want to generate code at
4301 // this point if it hasn't been done yet.
4302 SDValue N = NodeMap[V];
4303 if (!N.getNode() && isa<Argument>(V))
4304 // Check unused arguments map.
4305 N = UnusedArgNodeMap[V];
4307 // A dbg.value for an alloca is always indirect.
4308 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4309 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4311 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4312 IsIndirect, Offset, dl, SDNodeOrder);
4313 DAG.AddDbgValue(SDV, N.getNode(), false);
4315 } else if (!V->use_empty() ) {
4316 // Do not call getValue(V) yet, as we don't want to generate code.
4317 // Remember it for later.
4318 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4319 DanglingDebugInfoMap[V] = DDI;
4321 // We may expand this to cover more cases. One case where we have no
4322 // data available is an unreferenced parameter.
4323 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4327 // Build a debug info table entry.
4328 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4329 V = BCI->getOperand(0);
4330 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4331 // Don't handle byval struct arguments or VLAs, for example.
4333 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4334 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4337 DenseMap<const AllocaInst*, int>::iterator SI =
4338 FuncInfo.StaticAllocaMap.find(AI);
4339 if (SI == FuncInfo.StaticAllocaMap.end())
4340 return nullptr; // VLAs.
4344 case Intrinsic::eh_typeid_for: {
4345 // Find the type id for the given typeinfo.
4346 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4347 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4348 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4353 case Intrinsic::eh_return_i32:
4354 case Intrinsic::eh_return_i64:
4355 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4356 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4359 getValue(I.getArgOperand(0)),
4360 getValue(I.getArgOperand(1))));
4362 case Intrinsic::eh_unwind_init:
4363 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4365 case Intrinsic::eh_dwarf_cfa: {
4366 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4367 TLI.getPointerTy(DAG.getDataLayout()));
4368 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4369 CfaArg.getValueType(),
4370 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4371 CfaArg.getValueType()),
4373 SDValue FA = DAG.getNode(
4374 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4375 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4376 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4380 case Intrinsic::eh_sjlj_callsite: {
4381 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4382 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4383 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4384 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4386 MMI.setCurrentCallSite(CI->getZExtValue());
4389 case Intrinsic::eh_sjlj_functioncontext: {
4390 // Get and store the index of the function context.
4391 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4393 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4394 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4395 MFI->setFunctionContextIndex(FI);
4398 case Intrinsic::eh_sjlj_setjmp: {
4401 Ops[1] = getValue(I.getArgOperand(0));
4402 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4403 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4404 setValue(&I, Op.getValue(0));
4405 DAG.setRoot(Op.getValue(1));
4408 case Intrinsic::eh_sjlj_longjmp: {
4409 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4410 getRoot(), getValue(I.getArgOperand(0))));
4413 case Intrinsic::eh_sjlj_setup_dispatch: {
4414 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4419 case Intrinsic::masked_gather:
4420 visitMaskedGather(I);
4422 case Intrinsic::masked_load:
4425 case Intrinsic::masked_scatter:
4426 visitMaskedScatter(I);
4428 case Intrinsic::masked_store:
4429 visitMaskedStore(I);
4431 case Intrinsic::x86_mmx_pslli_w:
4432 case Intrinsic::x86_mmx_pslli_d:
4433 case Intrinsic::x86_mmx_pslli_q:
4434 case Intrinsic::x86_mmx_psrli_w:
4435 case Intrinsic::x86_mmx_psrli_d:
4436 case Intrinsic::x86_mmx_psrli_q:
4437 case Intrinsic::x86_mmx_psrai_w:
4438 case Intrinsic::x86_mmx_psrai_d: {
4439 SDValue ShAmt = getValue(I.getArgOperand(1));
4440 if (isa<ConstantSDNode>(ShAmt)) {
4441 visitTargetIntrinsic(I, Intrinsic);
4444 unsigned NewIntrinsic = 0;
4445 EVT ShAmtVT = MVT::v2i32;
4446 switch (Intrinsic) {
4447 case Intrinsic::x86_mmx_pslli_w:
4448 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4450 case Intrinsic::x86_mmx_pslli_d:
4451 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4453 case Intrinsic::x86_mmx_pslli_q:
4454 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4456 case Intrinsic::x86_mmx_psrli_w:
4457 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4459 case Intrinsic::x86_mmx_psrli_d:
4460 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4462 case Intrinsic::x86_mmx_psrli_q:
4463 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4465 case Intrinsic::x86_mmx_psrai_w:
4466 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4468 case Intrinsic::x86_mmx_psrai_d:
4469 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4471 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4474 // The vector shift intrinsics with scalars uses 32b shift amounts but
4475 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4477 // We must do this early because v2i32 is not a legal type.
4480 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4481 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4482 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4483 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4484 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4485 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4486 getValue(I.getArgOperand(0)), ShAmt);
4490 case Intrinsic::convertff:
4491 case Intrinsic::convertfsi:
4492 case Intrinsic::convertfui:
4493 case Intrinsic::convertsif:
4494 case Intrinsic::convertuif:
4495 case Intrinsic::convertss:
4496 case Intrinsic::convertsu:
4497 case Intrinsic::convertus:
4498 case Intrinsic::convertuu: {
4499 ISD::CvtCode Code = ISD::CVT_INVALID;
4500 switch (Intrinsic) {
4501 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4502 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4503 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4504 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4505 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4506 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4507 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4508 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4509 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4510 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4512 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4513 const Value *Op1 = I.getArgOperand(0);
4514 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4515 DAG.getValueType(DestVT),
4516 DAG.getValueType(getValue(Op1).getValueType()),
4517 getValue(I.getArgOperand(1)),
4518 getValue(I.getArgOperand(2)),
4523 case Intrinsic::powi:
4524 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4525 getValue(I.getArgOperand(1)), DAG));
4527 case Intrinsic::log:
4528 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4530 case Intrinsic::log2:
4531 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4533 case Intrinsic::log10:
4534 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4536 case Intrinsic::exp:
4537 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4539 case Intrinsic::exp2:
4540 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4542 case Intrinsic::pow:
4543 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4544 getValue(I.getArgOperand(1)), DAG, TLI));
4546 case Intrinsic::sqrt:
4547 case Intrinsic::fabs:
4548 case Intrinsic::sin:
4549 case Intrinsic::cos:
4550 case Intrinsic::floor:
4551 case Intrinsic::ceil:
4552 case Intrinsic::trunc:
4553 case Intrinsic::rint:
4554 case Intrinsic::nearbyint:
4555 case Intrinsic::round: {
4557 switch (Intrinsic) {
4558 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4559 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4560 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4561 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4562 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4563 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4564 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4565 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4566 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4567 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4568 case Intrinsic::round: Opcode = ISD::FROUND; break;
4571 setValue(&I, DAG.getNode(Opcode, sdl,
4572 getValue(I.getArgOperand(0)).getValueType(),
4573 getValue(I.getArgOperand(0))));
4576 case Intrinsic::minnum:
4577 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4578 getValue(I.getArgOperand(0)).getValueType(),
4579 getValue(I.getArgOperand(0)),
4580 getValue(I.getArgOperand(1))));
4582 case Intrinsic::maxnum:
4583 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4584 getValue(I.getArgOperand(0)).getValueType(),
4585 getValue(I.getArgOperand(0)),
4586 getValue(I.getArgOperand(1))));
4588 case Intrinsic::copysign:
4589 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4590 getValue(I.getArgOperand(0)).getValueType(),
4591 getValue(I.getArgOperand(0)),
4592 getValue(I.getArgOperand(1))));
4594 case Intrinsic::fma:
4595 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4596 getValue(I.getArgOperand(0)).getValueType(),
4597 getValue(I.getArgOperand(0)),
4598 getValue(I.getArgOperand(1)),
4599 getValue(I.getArgOperand(2))));
4601 case Intrinsic::fmuladd: {
4602 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4603 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4604 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4605 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4606 getValue(I.getArgOperand(0)).getValueType(),
4607 getValue(I.getArgOperand(0)),
4608 getValue(I.getArgOperand(1)),
4609 getValue(I.getArgOperand(2))));
4611 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4612 getValue(I.getArgOperand(0)).getValueType(),
4613 getValue(I.getArgOperand(0)),
4614 getValue(I.getArgOperand(1)));
4615 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4616 getValue(I.getArgOperand(0)).getValueType(),
4618 getValue(I.getArgOperand(2)));
4623 case Intrinsic::convert_to_fp16:
4624 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4625 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4626 getValue(I.getArgOperand(0)),
4627 DAG.getTargetConstant(0, sdl,
4630 case Intrinsic::convert_from_fp16:
4631 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4632 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4633 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4634 getValue(I.getArgOperand(0)))));
4636 case Intrinsic::pcmarker: {
4637 SDValue Tmp = getValue(I.getArgOperand(0));
4638 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4641 case Intrinsic::readcyclecounter: {
4642 SDValue Op = getRoot();
4643 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4644 DAG.getVTList(MVT::i64, MVT::Other), Op);
4646 DAG.setRoot(Res.getValue(1));
4649 case Intrinsic::bswap:
4650 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4651 getValue(I.getArgOperand(0)).getValueType(),
4652 getValue(I.getArgOperand(0))));
4654 case Intrinsic::uabsdiff:
4655 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4656 getValue(I.getArgOperand(0)).getValueType(),
4657 getValue(I.getArgOperand(0)),
4658 getValue(I.getArgOperand(1))));
4660 case Intrinsic::sabsdiff:
4661 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4662 getValue(I.getArgOperand(0)).getValueType(),
4663 getValue(I.getArgOperand(0)),
4664 getValue(I.getArgOperand(1))));
4666 case Intrinsic::cttz: {
4667 SDValue Arg = getValue(I.getArgOperand(0));
4668 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4669 EVT Ty = Arg.getValueType();
4670 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4674 case Intrinsic::ctlz: {
4675 SDValue Arg = getValue(I.getArgOperand(0));
4676 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4677 EVT Ty = Arg.getValueType();
4678 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4682 case Intrinsic::ctpop: {
4683 SDValue Arg = getValue(I.getArgOperand(0));
4684 EVT Ty = Arg.getValueType();
4685 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4688 case Intrinsic::stacksave: {
4689 SDValue Op = getRoot();
4691 ISD::STACKSAVE, sdl,
4692 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4694 DAG.setRoot(Res.getValue(1));
4697 case Intrinsic::stackrestore: {
4698 Res = getValue(I.getArgOperand(0));
4699 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4702 case Intrinsic::stackprotector: {
4703 // Emit code into the DAG to store the stack guard onto the stack.
4704 MachineFunction &MF = DAG.getMachineFunction();
4705 MachineFrameInfo *MFI = MF.getFrameInfo();
4706 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4707 SDValue Src, Chain = getRoot();
4708 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4709 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4711 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4712 // global variable __stack_chk_guard.
4714 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4715 if (BC->getOpcode() == Instruction::BitCast)
4716 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4718 if (GV && TLI.useLoadStackGuardNode()) {
4719 // Emit a LOAD_STACK_GUARD node.
4720 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4722 MachinePointerInfo MPInfo(GV);
4723 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4724 unsigned Flags = MachineMemOperand::MOLoad |
4725 MachineMemOperand::MOInvariant;
4726 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4727 PtrTy.getSizeInBits() / 8,
4728 DAG.getEVTAlignment(PtrTy));
4729 Node->setMemRefs(MemRefs, MemRefs + 1);
4731 // Copy the guard value to a virtual register so that it can be
4732 // retrieved in the epilogue.
4733 Src = SDValue(Node, 0);
4734 const TargetRegisterClass *RC =
4735 TLI.getRegClassFor(Src.getSimpleValueType());
4736 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4738 SPDescriptor.setGuardReg(Reg);
4739 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4741 Src = getValue(I.getArgOperand(0)); // The guard's value.
4744 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4746 int FI = FuncInfo.StaticAllocaMap[Slot];
4747 MFI->setStackProtectorIndex(FI);
4749 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4751 // Store the stack protector onto the stack.
4752 Res = DAG.getStore(Chain, sdl, Src, FIN,
4753 MachinePointerInfo::getFixedStack(FI),
4759 case Intrinsic::objectsize: {
4760 // If we don't know by now, we're never going to know.
4761 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4763 assert(CI && "Non-constant type in __builtin_object_size?");
4765 SDValue Arg = getValue(I.getCalledValue());
4766 EVT Ty = Arg.getValueType();
4769 Res = DAG.getConstant(-1ULL, sdl, Ty);
4771 Res = DAG.getConstant(0, sdl, Ty);
4776 case Intrinsic::annotation:
4777 case Intrinsic::ptr_annotation:
4778 // Drop the intrinsic, but forward the value
4779 setValue(&I, getValue(I.getOperand(0)));
4781 case Intrinsic::assume:
4782 case Intrinsic::var_annotation:
4783 // Discard annotate attributes and assumptions
4786 case Intrinsic::init_trampoline: {
4787 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4791 Ops[1] = getValue(I.getArgOperand(0));
4792 Ops[2] = getValue(I.getArgOperand(1));
4793 Ops[3] = getValue(I.getArgOperand(2));
4794 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4795 Ops[5] = DAG.getSrcValue(F);
4797 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4802 case Intrinsic::adjust_trampoline: {
4803 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4804 TLI.getPointerTy(DAG.getDataLayout()),
4805 getValue(I.getArgOperand(0))));
4808 case Intrinsic::gcroot:
4810 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4811 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4813 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4814 GFI->addStackRoot(FI->getIndex(), TypeMap);
4817 case Intrinsic::gcread:
4818 case Intrinsic::gcwrite:
4819 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4820 case Intrinsic::flt_rounds:
4821 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4824 case Intrinsic::expect: {
4825 // Just replace __builtin_expect(exp, c) with EXP.
4826 setValue(&I, getValue(I.getArgOperand(0)));
4830 case Intrinsic::debugtrap:
4831 case Intrinsic::trap: {
4832 StringRef TrapFuncName =
4834 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4835 .getValueAsString();
4836 if (TrapFuncName.empty()) {
4837 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4838 ISD::TRAP : ISD::DEBUGTRAP;
4839 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4842 TargetLowering::ArgListTy Args;
4844 TargetLowering::CallLoweringInfo CLI(DAG);
4845 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4846 CallingConv::C, I.getType(),
4847 DAG.getExternalSymbol(TrapFuncName.data(),
4848 TLI.getPointerTy(DAG.getDataLayout())),
4849 std::move(Args), 0);
4851 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4852 DAG.setRoot(Result.second);
4856 case Intrinsic::uadd_with_overflow:
4857 case Intrinsic::sadd_with_overflow:
4858 case Intrinsic::usub_with_overflow:
4859 case Intrinsic::ssub_with_overflow:
4860 case Intrinsic::umul_with_overflow:
4861 case Intrinsic::smul_with_overflow: {
4863 switch (Intrinsic) {
4864 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4865 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4866 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4867 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4868 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4869 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4870 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4872 SDValue Op1 = getValue(I.getArgOperand(0));
4873 SDValue Op2 = getValue(I.getArgOperand(1));
4875 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4876 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4879 case Intrinsic::prefetch: {
4881 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4883 Ops[1] = getValue(I.getArgOperand(0));
4884 Ops[2] = getValue(I.getArgOperand(1));
4885 Ops[3] = getValue(I.getArgOperand(2));
4886 Ops[4] = getValue(I.getArgOperand(3));
4887 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4888 DAG.getVTList(MVT::Other), Ops,
4889 EVT::getIntegerVT(*Context, 8),
4890 MachinePointerInfo(I.getArgOperand(0)),
4892 false, /* volatile */
4894 rw==1)); /* write */
4897 case Intrinsic::lifetime_start:
4898 case Intrinsic::lifetime_end: {
4899 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4900 // Stack coloring is not enabled in O0, discard region information.
4901 if (TM.getOptLevel() == CodeGenOpt::None)
4904 SmallVector<Value *, 4> Allocas;
4905 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4907 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4908 E = Allocas.end(); Object != E; ++Object) {
4909 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4911 // Could not find an Alloca.
4912 if (!LifetimeObject)
4915 // First check that the Alloca is static, otherwise it won't have a
4916 // valid frame index.
4917 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4918 if (SI == FuncInfo.StaticAllocaMap.end())
4921 int FI = SI->second;
4926 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
4927 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4929 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4934 case Intrinsic::invariant_start:
4935 // Discard region information.
4936 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4938 case Intrinsic::invariant_end:
4939 // Discard region information.
4941 case Intrinsic::stackprotectorcheck: {
4942 // Do not actually emit anything for this basic block. Instead we initialize
4943 // the stack protector descriptor and export the guard variable so we can
4944 // access it in FinishBasicBlock.
4945 const BasicBlock *BB = I.getParent();
4946 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4947 ExportFromCurrentBlock(SPDescriptor.getGuard());
4949 // Flush our exports since we are going to process a terminator.
4950 (void)getControlRoot();
4953 case Intrinsic::clear_cache:
4954 return TLI.getClearCacheBuiltinName();
4955 case Intrinsic::eh_actions:
4956 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4958 case Intrinsic::donothing:
4961 case Intrinsic::experimental_stackmap: {
4965 case Intrinsic::experimental_patchpoint_void:
4966 case Intrinsic::experimental_patchpoint_i64: {
4967 visitPatchpoint(&I);
4970 case Intrinsic::experimental_gc_statepoint: {
4974 case Intrinsic::experimental_gc_result_int:
4975 case Intrinsic::experimental_gc_result_float:
4976 case Intrinsic::experimental_gc_result_ptr:
4977 case Intrinsic::experimental_gc_result: {
4981 case Intrinsic::experimental_gc_relocate: {
4985 case Intrinsic::instrprof_increment:
4986 llvm_unreachable("instrprof failed to lower an increment");
4988 case Intrinsic::localescape: {
4989 MachineFunction &MF = DAG.getMachineFunction();
4990 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4992 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
4993 // is the same on all targets.
4994 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4995 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4996 if (isa<ConstantPointerNull>(Arg))
4997 continue; // Skip null pointers. They represent a hole in index space.
4998 AllocaInst *Slot = cast<AllocaInst>(Arg);
4999 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5000 "can only escape static allocas");
5001 int FI = FuncInfo.StaticAllocaMap[Slot];
5002 MCSymbol *FrameAllocSym =
5003 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5004 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5005 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5006 TII->get(TargetOpcode::LOCAL_ESCAPE))
5007 .addSym(FrameAllocSym)
5014 case Intrinsic::localrecover: {
5015 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5016 MachineFunction &MF = DAG.getMachineFunction();
5017 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5019 // Get the symbol that defines the frame offset.
5020 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5021 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5022 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5023 MCSymbol *FrameAllocSym =
5024 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5025 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5027 // Create a MCSymbol for the label to avoid any target lowering
5028 // that would make this PC relative.
5029 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5031 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5033 // Add the offset to the FP.
5034 Value *FP = I.getArgOperand(1);
5035 SDValue FPVal = getValue(FP);
5036 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5041 case Intrinsic::eh_begincatch:
5042 case Intrinsic::eh_endcatch:
5043 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5044 case Intrinsic::eh_exceptioncode: {
5045 unsigned Reg = TLI.getExceptionPointerRegister();
5046 assert(Reg && "cannot get exception code on this platform");
5047 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5048 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5049 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
5050 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5052 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5053 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5060 std::pair<SDValue, SDValue>
5061 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5062 MachineBasicBlock *LandingPad) {
5063 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5064 MCSymbol *BeginLabel = nullptr;
5067 // Insert a label before the invoke call to mark the try range. This can be
5068 // used to detect deletion of the invoke via the MachineModuleInfo.
5069 BeginLabel = MMI.getContext().createTempSymbol();
5071 // For SjLj, keep track of which landing pads go with which invokes
5072 // so as to maintain the ordering of pads in the LSDA.
5073 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5074 if (CallSiteIndex) {
5075 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5076 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5078 // Now that the call site is handled, stop tracking it.
5079 MMI.setCurrentCallSite(0);
5082 // Both PendingLoads and PendingExports must be flushed here;
5083 // this call might not return.
5085 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5087 CLI.setChain(getRoot());
5089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5090 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5092 assert((CLI.IsTailCall || Result.second.getNode()) &&
5093 "Non-null chain expected with non-tail call!");
5094 assert((Result.second.getNode() || !Result.first.getNode()) &&
5095 "Null value expected with tail call!");
5097 if (!Result.second.getNode()) {
5098 // As a special case, a null chain means that a tail call has been emitted
5099 // and the DAG root is already updated.
5102 // Since there's no actual continuation from this block, nothing can be
5103 // relying on us setting vregs for them.
5104 PendingExports.clear();
5106 DAG.setRoot(Result.second);
5110 // Insert a label at the end of the invoke call to mark the try range. This
5111 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5112 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5113 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5115 // Inform MachineModuleInfo of range.
5116 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5122 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5124 MachineBasicBlock *LandingPad) {
5125 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5126 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5127 Type *RetTy = FTy->getReturnType();
5129 TargetLowering::ArgListTy Args;
5130 TargetLowering::ArgListEntry Entry;
5131 Args.reserve(CS.arg_size());
5133 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5135 const Value *V = *i;
5138 if (V->getType()->isEmptyTy())
5141 SDValue ArgNode = getValue(V);
5142 Entry.Node = ArgNode; Entry.Ty = V->getType();
5144 // Skip the first return-type Attribute to get to params.
5145 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5146 Args.push_back(Entry);
5148 // If we have an explicit sret argument that is an Instruction, (i.e., it
5149 // might point to function-local memory), we can't meaningfully tail-call.
5150 if (Entry.isSRet && isa<Instruction>(V))
5154 // Check if target-independent constraints permit a tail call here.
5155 // Target-dependent constraints are checked within TLI->LowerCallTo.
5156 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5159 TargetLowering::CallLoweringInfo CLI(DAG);
5160 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5161 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5162 .setTailCall(isTailCall);
5163 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5165 if (Result.first.getNode())
5166 setValue(CS.getInstruction(), Result.first);
5169 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5170 /// value is equal or not-equal to zero.
5171 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5172 for (const User *U : V->users()) {
5173 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5174 if (IC->isEquality())
5175 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5176 if (C->isNullValue())
5178 // Unknown instruction.
5184 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5186 SelectionDAGBuilder &Builder) {
5188 // Check to see if this load can be trivially constant folded, e.g. if the
5189 // input is from a string literal.
5190 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5191 // Cast pointer to the type we really want to load.
5192 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5193 PointerType::getUnqual(LoadTy));
5195 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5196 const_cast<Constant *>(LoadInput), *Builder.DL))
5197 return Builder.getValue(LoadCst);
5200 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5201 // still constant memory, the input chain can be the entry node.
5203 bool ConstantMemory = false;
5205 // Do not serialize (non-volatile) loads of constant memory with anything.
5206 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5207 Root = Builder.DAG.getEntryNode();
5208 ConstantMemory = true;
5210 // Do not serialize non-volatile loads against each other.
5211 Root = Builder.DAG.getRoot();
5214 SDValue Ptr = Builder.getValue(PtrVal);
5215 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5216 Ptr, MachinePointerInfo(PtrVal),
5218 false /*nontemporal*/,
5219 false /*isinvariant*/, 1 /* align=1 */);
5221 if (!ConstantMemory)
5222 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5226 /// processIntegerCallValue - Record the value for an instruction that
5227 /// produces an integer result, converting the type where necessary.
5228 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5231 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5234 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5236 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5237 setValue(&I, Value);
5240 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5241 /// If so, return true and lower it, otherwise return false and it will be
5242 /// lowered like a normal call.
5243 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5244 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5245 if (I.getNumArgOperands() != 3)
5248 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5249 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5250 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5251 !I.getType()->isIntegerTy())
5254 const Value *Size = I.getArgOperand(2);
5255 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5256 if (CSize && CSize->getZExtValue() == 0) {
5257 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5259 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5263 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5264 std::pair<SDValue, SDValue> Res =
5265 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5266 getValue(LHS), getValue(RHS), getValue(Size),
5267 MachinePointerInfo(LHS),
5268 MachinePointerInfo(RHS));
5269 if (Res.first.getNode()) {
5270 processIntegerCallValue(I, Res.first, true);
5271 PendingLoads.push_back(Res.second);
5275 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5276 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5277 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5278 bool ActuallyDoIt = true;
5281 switch (CSize->getZExtValue()) {
5283 LoadVT = MVT::Other;
5285 ActuallyDoIt = false;
5289 LoadTy = Type::getInt16Ty(CSize->getContext());
5293 LoadTy = Type::getInt32Ty(CSize->getContext());
5297 LoadTy = Type::getInt64Ty(CSize->getContext());
5301 LoadVT = MVT::v4i32;
5302 LoadTy = Type::getInt32Ty(CSize->getContext());
5303 LoadTy = VectorType::get(LoadTy, 4);
5308 // This turns into unaligned loads. We only do this if the target natively
5309 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5310 // we'll only produce a small number of byte loads.
5312 // Require that we can find a legal MVT, and only do this if the target
5313 // supports unaligned loads of that type. Expanding into byte loads would
5315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5316 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5317 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5318 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5319 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5320 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5321 // TODO: Check alignment of src and dest ptrs.
5322 if (!TLI.isTypeLegal(LoadVT) ||
5323 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5324 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5325 ActuallyDoIt = false;
5329 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5330 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5332 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5334 processIntegerCallValue(I, Res, false);
5343 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5344 /// form. If so, return true and lower it, otherwise return false and it
5345 /// will be lowered like a normal call.
5346 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5347 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5348 if (I.getNumArgOperands() != 3)
5351 const Value *Src = I.getArgOperand(0);
5352 const Value *Char = I.getArgOperand(1);
5353 const Value *Length = I.getArgOperand(2);
5354 if (!Src->getType()->isPointerTy() ||
5355 !Char->getType()->isIntegerTy() ||
5356 !Length->getType()->isIntegerTy() ||
5357 !I.getType()->isPointerTy())
5360 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5361 std::pair<SDValue, SDValue> Res =
5362 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5363 getValue(Src), getValue(Char), getValue(Length),
5364 MachinePointerInfo(Src));
5365 if (Res.first.getNode()) {
5366 setValue(&I, Res.first);
5367 PendingLoads.push_back(Res.second);
5374 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5375 /// optimized form. If so, return true and lower it, otherwise return false
5376 /// and it will be lowered like a normal call.
5377 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5378 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5379 if (I.getNumArgOperands() != 2)
5382 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5383 if (!Arg0->getType()->isPointerTy() ||
5384 !Arg1->getType()->isPointerTy() ||
5385 !I.getType()->isPointerTy())
5388 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5389 std::pair<SDValue, SDValue> Res =
5390 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5391 getValue(Arg0), getValue(Arg1),
5392 MachinePointerInfo(Arg0),
5393 MachinePointerInfo(Arg1), isStpcpy);
5394 if (Res.first.getNode()) {
5395 setValue(&I, Res.first);
5396 DAG.setRoot(Res.second);
5403 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5404 /// If so, return true and lower it, otherwise return false and it will be
5405 /// lowered like a normal call.
5406 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5407 // Verify that the prototype makes sense. int strcmp(void*,void*)
5408 if (I.getNumArgOperands() != 2)
5411 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5412 if (!Arg0->getType()->isPointerTy() ||
5413 !Arg1->getType()->isPointerTy() ||
5414 !I.getType()->isIntegerTy())
5417 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5418 std::pair<SDValue, SDValue> Res =
5419 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5420 getValue(Arg0), getValue(Arg1),
5421 MachinePointerInfo(Arg0),
5422 MachinePointerInfo(Arg1));
5423 if (Res.first.getNode()) {
5424 processIntegerCallValue(I, Res.first, true);
5425 PendingLoads.push_back(Res.second);
5432 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5433 /// form. If so, return true and lower it, otherwise return false and it
5434 /// will be lowered like a normal call.
5435 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5436 // Verify that the prototype makes sense. size_t strlen(char *)
5437 if (I.getNumArgOperands() != 1)
5440 const Value *Arg0 = I.getArgOperand(0);
5441 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5444 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5445 std::pair<SDValue, SDValue> Res =
5446 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5447 getValue(Arg0), MachinePointerInfo(Arg0));
5448 if (Res.first.getNode()) {
5449 processIntegerCallValue(I, Res.first, false);
5450 PendingLoads.push_back(Res.second);
5457 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5458 /// form. If so, return true and lower it, otherwise return false and it
5459 /// will be lowered like a normal call.
5460 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5461 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5462 if (I.getNumArgOperands() != 2)
5465 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5466 if (!Arg0->getType()->isPointerTy() ||
5467 !Arg1->getType()->isIntegerTy() ||
5468 !I.getType()->isIntegerTy())
5471 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5472 std::pair<SDValue, SDValue> Res =
5473 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5474 getValue(Arg0), getValue(Arg1),
5475 MachinePointerInfo(Arg0));
5476 if (Res.first.getNode()) {
5477 processIntegerCallValue(I, Res.first, false);
5478 PendingLoads.push_back(Res.second);
5485 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5486 /// operation (as expected), translate it to an SDNode with the specified opcode
5487 /// and return true.
5488 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5490 // Sanity check that it really is a unary floating-point call.
5491 if (I.getNumArgOperands() != 1 ||
5492 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5493 I.getType() != I.getArgOperand(0)->getType() ||
5494 !I.onlyReadsMemory())
5497 SDValue Tmp = getValue(I.getArgOperand(0));
5498 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5502 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5503 /// operation (as expected), translate it to an SDNode with the specified opcode
5504 /// and return true.
5505 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5507 // Sanity check that it really is a binary floating-point call.
5508 if (I.getNumArgOperands() != 2 ||
5509 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5510 I.getType() != I.getArgOperand(0)->getType() ||
5511 I.getType() != I.getArgOperand(1)->getType() ||
5512 !I.onlyReadsMemory())
5515 SDValue Tmp0 = getValue(I.getArgOperand(0));
5516 SDValue Tmp1 = getValue(I.getArgOperand(1));
5517 EVT VT = Tmp0.getValueType();
5518 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5522 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5523 // Handle inline assembly differently.
5524 if (isa<InlineAsm>(I.getCalledValue())) {
5529 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5530 ComputeUsesVAFloatArgument(I, &MMI);
5532 const char *RenameFn = nullptr;
5533 if (Function *F = I.getCalledFunction()) {
5534 if (F->isDeclaration()) {
5535 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5536 if (unsigned IID = II->getIntrinsicID(F)) {
5537 RenameFn = visitIntrinsicCall(I, IID);
5542 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5543 RenameFn = visitIntrinsicCall(I, IID);
5549 // Check for well-known libc/libm calls. If the function is internal, it
5550 // can't be a library call.
5552 if (!F->hasLocalLinkage() && F->hasName() &&
5553 LibInfo->getLibFunc(F->getName(), Func) &&
5554 LibInfo->hasOptimizedCodeGen(Func)) {
5557 case LibFunc::copysign:
5558 case LibFunc::copysignf:
5559 case LibFunc::copysignl:
5560 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5561 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5562 I.getType() == I.getArgOperand(0)->getType() &&
5563 I.getType() == I.getArgOperand(1)->getType() &&
5564 I.onlyReadsMemory()) {
5565 SDValue LHS = getValue(I.getArgOperand(0));
5566 SDValue RHS = getValue(I.getArgOperand(1));
5567 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5568 LHS.getValueType(), LHS, RHS));
5573 case LibFunc::fabsf:
5574 case LibFunc::fabsl:
5575 if (visitUnaryFloatCall(I, ISD::FABS))
5579 case LibFunc::fminf:
5580 case LibFunc::fminl:
5581 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5585 case LibFunc::fmaxf:
5586 case LibFunc::fmaxl:
5587 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5593 if (visitUnaryFloatCall(I, ISD::FSIN))
5599 if (visitUnaryFloatCall(I, ISD::FCOS))
5603 case LibFunc::sqrtf:
5604 case LibFunc::sqrtl:
5605 case LibFunc::sqrt_finite:
5606 case LibFunc::sqrtf_finite:
5607 case LibFunc::sqrtl_finite:
5608 if (visitUnaryFloatCall(I, ISD::FSQRT))
5611 case LibFunc::floor:
5612 case LibFunc::floorf:
5613 case LibFunc::floorl:
5614 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5617 case LibFunc::nearbyint:
5618 case LibFunc::nearbyintf:
5619 case LibFunc::nearbyintl:
5620 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5624 case LibFunc::ceilf:
5625 case LibFunc::ceill:
5626 if (visitUnaryFloatCall(I, ISD::FCEIL))
5630 case LibFunc::rintf:
5631 case LibFunc::rintl:
5632 if (visitUnaryFloatCall(I, ISD::FRINT))
5635 case LibFunc::round:
5636 case LibFunc::roundf:
5637 case LibFunc::roundl:
5638 if (visitUnaryFloatCall(I, ISD::FROUND))
5641 case LibFunc::trunc:
5642 case LibFunc::truncf:
5643 case LibFunc::truncl:
5644 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5648 case LibFunc::log2f:
5649 case LibFunc::log2l:
5650 if (visitUnaryFloatCall(I, ISD::FLOG2))
5654 case LibFunc::exp2f:
5655 case LibFunc::exp2l:
5656 if (visitUnaryFloatCall(I, ISD::FEXP2))
5659 case LibFunc::memcmp:
5660 if (visitMemCmpCall(I))
5663 case LibFunc::memchr:
5664 if (visitMemChrCall(I))
5667 case LibFunc::strcpy:
5668 if (visitStrCpyCall(I, false))
5671 case LibFunc::stpcpy:
5672 if (visitStrCpyCall(I, true))
5675 case LibFunc::strcmp:
5676 if (visitStrCmpCall(I))
5679 case LibFunc::strlen:
5680 if (visitStrLenCall(I))
5683 case LibFunc::strnlen:
5684 if (visitStrNLenCall(I))
5693 Callee = getValue(I.getCalledValue());
5695 Callee = DAG.getExternalSymbol(
5697 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5699 // Check if we can potentially perform a tail call. More detailed checking is
5700 // be done within LowerCallTo, after more information about the call is known.
5701 LowerCallTo(&I, Callee, I.isTailCall());
5706 /// AsmOperandInfo - This contains information for each constraint that we are
5708 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5710 /// CallOperand - If this is the result output operand or a clobber
5711 /// this is null, otherwise it is the incoming operand to the CallInst.
5712 /// This gets modified as the asm is processed.
5713 SDValue CallOperand;
5715 /// AssignedRegs - If this is a register or register class operand, this
5716 /// contains the set of register corresponding to the operand.
5717 RegsForValue AssignedRegs;
5719 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5720 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5723 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5724 /// corresponds to. If there is no Value* for this operand, it returns
5726 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5727 const DataLayout &DL) const {
5728 if (!CallOperandVal) return MVT::Other;
5730 if (isa<BasicBlock>(CallOperandVal))
5731 return TLI.getPointerTy(DL);
5733 llvm::Type *OpTy = CallOperandVal->getType();
5735 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5736 // If this is an indirect operand, the operand is a pointer to the
5739 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5741 report_fatal_error("Indirect operand for inline asm not a pointer!");
5742 OpTy = PtrTy->getElementType();
5745 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5746 if (StructType *STy = dyn_cast<StructType>(OpTy))
5747 if (STy->getNumElements() == 1)
5748 OpTy = STy->getElementType(0);
5750 // If OpTy is not a single value, it may be a struct/union that we
5751 // can tile with integers.
5752 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5753 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5762 OpTy = IntegerType::get(Context, BitSize);
5767 return TLI.getValueType(DL, OpTy, true);
5771 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5773 } // end anonymous namespace
5775 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5776 /// specified operand. We prefer to assign virtual registers, to allow the
5777 /// register allocator to handle the assignment process. However, if the asm
5778 /// uses features that we can't model on machineinstrs, we have SDISel do the
5779 /// allocation. This produces generally horrible, but correct, code.
5781 /// OpInfo describes the operand.
5783 static void GetRegistersForValue(SelectionDAG &DAG,
5784 const TargetLowering &TLI,
5786 SDISelAsmOperandInfo &OpInfo) {
5787 LLVMContext &Context = *DAG.getContext();
5789 MachineFunction &MF = DAG.getMachineFunction();
5790 SmallVector<unsigned, 4> Regs;
5792 // If this is a constraint for a single physreg, or a constraint for a
5793 // register class, find it.
5794 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5795 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5796 OpInfo.ConstraintCode,
5797 OpInfo.ConstraintVT);
5799 unsigned NumRegs = 1;
5800 if (OpInfo.ConstraintVT != MVT::Other) {
5801 // If this is a FP input in an integer register (or visa versa) insert a bit
5802 // cast of the input value. More generally, handle any case where the input
5803 // value disagrees with the register class we plan to stick this in.
5804 if (OpInfo.Type == InlineAsm::isInput &&
5805 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5806 // Try to convert to the first EVT that the reg class contains. If the
5807 // types are identical size, use a bitcast to convert (e.g. two differing
5809 MVT RegVT = *PhysReg.second->vt_begin();
5810 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5811 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5812 RegVT, OpInfo.CallOperand);
5813 OpInfo.ConstraintVT = RegVT;
5814 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5815 // If the input is a FP value and we want it in FP registers, do a
5816 // bitcast to the corresponding integer type. This turns an f64 value
5817 // into i64, which can be passed with two i32 values on a 32-bit
5819 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5820 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5821 RegVT, OpInfo.CallOperand);
5822 OpInfo.ConstraintVT = RegVT;
5826 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5830 EVT ValueVT = OpInfo.ConstraintVT;
5832 // If this is a constraint for a specific physical register, like {r17},
5834 if (unsigned AssignedReg = PhysReg.first) {
5835 const TargetRegisterClass *RC = PhysReg.second;
5836 if (OpInfo.ConstraintVT == MVT::Other)
5837 ValueVT = *RC->vt_begin();
5839 // Get the actual register value type. This is important, because the user
5840 // may have asked for (e.g.) the AX register in i32 type. We need to
5841 // remember that AX is actually i16 to get the right extension.
5842 RegVT = *RC->vt_begin();
5844 // This is a explicit reference to a physical register.
5845 Regs.push_back(AssignedReg);
5847 // If this is an expanded reference, add the rest of the regs to Regs.
5849 TargetRegisterClass::iterator I = RC->begin();
5850 for (; *I != AssignedReg; ++I)
5851 assert(I != RC->end() && "Didn't find reg!");
5853 // Already added the first reg.
5855 for (; NumRegs; --NumRegs, ++I) {
5856 assert(I != RC->end() && "Ran out of registers to allocate!");
5861 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5865 // Otherwise, if this was a reference to an LLVM register class, create vregs
5866 // for this reference.
5867 if (const TargetRegisterClass *RC = PhysReg.second) {
5868 RegVT = *RC->vt_begin();
5869 if (OpInfo.ConstraintVT == MVT::Other)
5872 // Create the appropriate number of virtual registers.
5873 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5874 for (; NumRegs; --NumRegs)
5875 Regs.push_back(RegInfo.createVirtualRegister(RC));
5877 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5881 // Otherwise, we couldn't allocate enough registers for this.
5884 /// visitInlineAsm - Handle a call to an InlineAsm object.
5886 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5887 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5889 /// ConstraintOperands - Information about all of the constraints.
5890 SDISelAsmOperandInfoVector ConstraintOperands;
5892 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5893 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5894 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5896 bool hasMemory = false;
5898 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5899 unsigned ResNo = 0; // ResNo - The result number of the next output.
5900 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5901 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5902 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5904 MVT OpVT = MVT::Other;
5906 // Compute the value type for each operand.
5907 switch (OpInfo.Type) {
5908 case InlineAsm::isOutput:
5909 // Indirect outputs just consume an argument.
5910 if (OpInfo.isIndirect) {
5911 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5915 // The return value of the call is this value. As such, there is no
5916 // corresponding argument.
5917 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5918 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5919 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
5920 STy->getElementType(ResNo));
5922 assert(ResNo == 0 && "Asm only has one result!");
5923 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
5927 case InlineAsm::isInput:
5928 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5930 case InlineAsm::isClobber:
5935 // If this is an input or an indirect output, process the call argument.
5936 // BasicBlocks are labels, currently appearing only in asm's.
5937 if (OpInfo.CallOperandVal) {
5938 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5939 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5941 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5944 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
5945 DAG.getDataLayout()).getSimpleVT();
5948 OpInfo.ConstraintVT = OpVT;
5950 // Indirect operand accesses access memory.
5951 if (OpInfo.isIndirect)
5954 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5955 TargetLowering::ConstraintType
5956 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5957 if (CType == TargetLowering::C_Memory) {
5965 SDValue Chain, Flag;
5967 // We won't need to flush pending loads if this asm doesn't touch
5968 // memory and is nonvolatile.
5969 if (hasMemory || IA->hasSideEffects())
5972 Chain = DAG.getRoot();
5974 // Second pass over the constraints: compute which constraint option to use
5975 // and assign registers to constraints that want a specific physreg.
5976 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5977 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5979 // If this is an output operand with a matching input operand, look up the
5980 // matching input. If their types mismatch, e.g. one is an integer, the
5981 // other is floating point, or their sizes are different, flag it as an
5983 if (OpInfo.hasMatchingInput()) {
5984 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5986 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5987 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5988 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5989 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5990 OpInfo.ConstraintVT);
5991 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5992 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5993 Input.ConstraintVT);
5994 if ((OpInfo.ConstraintVT.isInteger() !=
5995 Input.ConstraintVT.isInteger()) ||
5996 (MatchRC.second != InputRC.second)) {
5997 report_fatal_error("Unsupported asm: input constraint"
5998 " with a matching output constraint of"
5999 " incompatible type!");
6001 Input.ConstraintVT = OpInfo.ConstraintVT;
6005 // Compute the constraint code and ConstraintType to use.
6006 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6008 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6009 OpInfo.Type == InlineAsm::isClobber)
6012 // If this is a memory input, and if the operand is not indirect, do what we
6013 // need to to provide an address for the memory input.
6014 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6015 !OpInfo.isIndirect) {
6016 assert((OpInfo.isMultipleAlternative ||
6017 (OpInfo.Type == InlineAsm::isInput)) &&
6018 "Can only indirectify direct input operands!");
6020 // Memory operands really want the address of the value. If we don't have
6021 // an indirect input, put it in the constpool if we can, otherwise spill
6022 // it to a stack slot.
6023 // TODO: This isn't quite right. We need to handle these according to
6024 // the addressing mode that the constraint wants. Also, this may take
6025 // an additional register for the computation and we don't want that
6028 // If the operand is a float, integer, or vector constant, spill to a
6029 // constant pool entry to get its address.
6030 const Value *OpVal = OpInfo.CallOperandVal;
6031 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6032 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6033 OpInfo.CallOperand = DAG.getConstantPool(
6034 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6036 // Otherwise, create a stack slot and emit a store to it before the
6038 Type *Ty = OpVal->getType();
6039 auto &DL = DAG.getDataLayout();
6040 uint64_t TySize = DL.getTypeAllocSize(Ty);
6041 unsigned Align = DL.getPrefTypeAlignment(Ty);
6042 MachineFunction &MF = DAG.getMachineFunction();
6043 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6045 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6046 Chain = DAG.getStore(Chain, getCurSDLoc(),
6047 OpInfo.CallOperand, StackSlot,
6048 MachinePointerInfo::getFixedStack(SSFI),
6050 OpInfo.CallOperand = StackSlot;
6053 // There is no longer a Value* corresponding to this operand.
6054 OpInfo.CallOperandVal = nullptr;
6056 // It is now an indirect operand.
6057 OpInfo.isIndirect = true;
6060 // If this constraint is for a specific register, allocate it before
6062 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6063 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6066 // Second pass - Loop over all of the operands, assigning virtual or physregs
6067 // to register class operands.
6068 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6069 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6071 // C_Register operands have already been allocated, Other/Memory don't need
6073 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6074 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6077 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6078 std::vector<SDValue> AsmNodeOperands;
6079 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6080 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6081 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6083 // If we have a !srcloc metadata node associated with it, we want to attach
6084 // this to the ultimately generated inline asm machineinstr. To do this, we
6085 // pass in the third operand as this (potentially null) inline asm MDNode.
6086 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6087 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6089 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6090 // bits as operand 3.
6091 unsigned ExtraInfo = 0;
6092 if (IA->hasSideEffects())
6093 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6094 if (IA->isAlignStack())
6095 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6096 // Set the asm dialect.
6097 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6099 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6100 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6101 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6103 // Compute the constraint code and ConstraintType to use.
6104 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6106 // Ideally, we would only check against memory constraints. However, the
6107 // meaning of an other constraint can be target-specific and we can't easily
6108 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6109 // for other constriants as well.
6110 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6111 OpInfo.ConstraintType == TargetLowering::C_Other) {
6112 if (OpInfo.Type == InlineAsm::isInput)
6113 ExtraInfo |= InlineAsm::Extra_MayLoad;
6114 else if (OpInfo.Type == InlineAsm::isOutput)
6115 ExtraInfo |= InlineAsm::Extra_MayStore;
6116 else if (OpInfo.Type == InlineAsm::isClobber)
6117 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6121 AsmNodeOperands.push_back(DAG.getTargetConstant(
6122 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6124 // Loop over all of the inputs, copying the operand values into the
6125 // appropriate registers and processing the output regs.
6126 RegsForValue RetValRegs;
6128 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6129 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6131 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6132 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6134 switch (OpInfo.Type) {
6135 case InlineAsm::isOutput: {
6136 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6137 OpInfo.ConstraintType != TargetLowering::C_Register) {
6138 // Memory output, or 'other' output (e.g. 'X' constraint).
6139 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6141 unsigned ConstraintID =
6142 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6143 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6144 "Failed to convert memory constraint code to constraint id.");
6146 // Add information to the INLINEASM node to know about this output.
6147 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6148 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6149 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6151 AsmNodeOperands.push_back(OpInfo.CallOperand);
6155 // Otherwise, this is a register or register class output.
6157 // Copy the output from the appropriate register. Find a register that
6159 if (OpInfo.AssignedRegs.Regs.empty()) {
6160 LLVMContext &Ctx = *DAG.getContext();
6161 Ctx.emitError(CS.getInstruction(),
6162 "couldn't allocate output register for constraint '" +
6163 Twine(OpInfo.ConstraintCode) + "'");
6167 // If this is an indirect operand, store through the pointer after the
6169 if (OpInfo.isIndirect) {
6170 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6171 OpInfo.CallOperandVal));
6173 // This is the result value of the call.
6174 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6175 // Concatenate this output onto the outputs list.
6176 RetValRegs.append(OpInfo.AssignedRegs);
6179 // Add information to the INLINEASM node to know that this register is
6182 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6183 ? InlineAsm::Kind_RegDefEarlyClobber
6184 : InlineAsm::Kind_RegDef,
6185 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6188 case InlineAsm::isInput: {
6189 SDValue InOperandVal = OpInfo.CallOperand;
6191 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6192 // If this is required to match an output register we have already set,
6193 // just use its register.
6194 unsigned OperandNo = OpInfo.getMatchedOperand();
6196 // Scan until we find the definition we already emitted of this operand.
6197 // When we find it, create a RegsForValue operand.
6198 unsigned CurOp = InlineAsm::Op_FirstOperand;
6199 for (; OperandNo; --OperandNo) {
6200 // Advance to the next operand.
6202 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6203 assert((InlineAsm::isRegDefKind(OpFlag) ||
6204 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6205 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6206 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6210 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6211 if (InlineAsm::isRegDefKind(OpFlag) ||
6212 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6213 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6214 if (OpInfo.isIndirect) {
6215 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6216 LLVMContext &Ctx = *DAG.getContext();
6217 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6218 " don't know how to handle tied "
6219 "indirect register inputs");
6223 RegsForValue MatchedRegs;
6224 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6225 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6226 MatchedRegs.RegVTs.push_back(RegVT);
6227 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6228 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6230 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6231 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6233 LLVMContext &Ctx = *DAG.getContext();
6234 Ctx.emitError(CS.getInstruction(),
6235 "inline asm error: This value"
6236 " type register class is not natively supported!");
6240 SDLoc dl = getCurSDLoc();
6241 // Use the produced MatchedRegs object to
6242 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6243 Chain, &Flag, CS.getInstruction());
6244 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6245 true, OpInfo.getMatchedOperand(), dl,
6246 DAG, AsmNodeOperands);
6250 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6251 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6252 "Unexpected number of operands");
6253 // Add information to the INLINEASM node to know about this input.
6254 // See InlineAsm.h isUseOperandTiedToDef.
6255 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6256 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6257 OpInfo.getMatchedOperand());
6258 AsmNodeOperands.push_back(DAG.getTargetConstant(
6259 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6260 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6264 // Treat indirect 'X' constraint as memory.
6265 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6267 OpInfo.ConstraintType = TargetLowering::C_Memory;
6269 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6270 std::vector<SDValue> Ops;
6271 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6274 LLVMContext &Ctx = *DAG.getContext();
6275 Ctx.emitError(CS.getInstruction(),
6276 "invalid operand for inline asm constraint '" +
6277 Twine(OpInfo.ConstraintCode) + "'");
6281 // Add information to the INLINEASM node to know about this input.
6282 unsigned ResOpType =
6283 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6284 AsmNodeOperands.push_back(DAG.getTargetConstant(
6285 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6286 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6290 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6291 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6292 assert(InOperandVal.getValueType() ==
6293 TLI.getPointerTy(DAG.getDataLayout()) &&
6294 "Memory operands expect pointer values");
6296 unsigned ConstraintID =
6297 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6298 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6299 "Failed to convert memory constraint code to constraint id.");
6301 // Add information to the INLINEASM node to know about this input.
6302 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6303 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6304 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6307 AsmNodeOperands.push_back(InOperandVal);
6311 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6312 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6313 "Unknown constraint type!");
6315 // TODO: Support this.
6316 if (OpInfo.isIndirect) {
6317 LLVMContext &Ctx = *DAG.getContext();
6318 Ctx.emitError(CS.getInstruction(),
6319 "Don't know how to handle indirect register inputs yet "
6320 "for constraint '" +
6321 Twine(OpInfo.ConstraintCode) + "'");
6325 // Copy the input into the appropriate registers.
6326 if (OpInfo.AssignedRegs.Regs.empty()) {
6327 LLVMContext &Ctx = *DAG.getContext();
6328 Ctx.emitError(CS.getInstruction(),
6329 "couldn't allocate input reg for constraint '" +
6330 Twine(OpInfo.ConstraintCode) + "'");
6334 SDLoc dl = getCurSDLoc();
6336 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6337 Chain, &Flag, CS.getInstruction());
6339 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6340 dl, DAG, AsmNodeOperands);
6343 case InlineAsm::isClobber: {
6344 // Add the clobbered value to the operand list, so that the register
6345 // allocator is aware that the physreg got clobbered.
6346 if (!OpInfo.AssignedRegs.Regs.empty())
6347 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6348 false, 0, getCurSDLoc(), DAG,
6355 // Finish up input operands. Set the input chain and add the flag last.
6356 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6357 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6359 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6360 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6361 Flag = Chain.getValue(1);
6363 // If this asm returns a register value, copy the result from that register
6364 // and set it as the value of the call.
6365 if (!RetValRegs.Regs.empty()) {
6366 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6367 Chain, &Flag, CS.getInstruction());
6369 // FIXME: Why don't we do this for inline asms with MRVs?
6370 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6371 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6373 // If any of the results of the inline asm is a vector, it may have the
6374 // wrong width/num elts. This can happen for register classes that can
6375 // contain multiple different value types. The preg or vreg allocated may
6376 // not have the same VT as was expected. Convert it to the right type
6377 // with bit_convert.
6378 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6379 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6382 } else if (ResultType != Val.getValueType() &&
6383 ResultType.isInteger() && Val.getValueType().isInteger()) {
6384 // If a result value was tied to an input value, the computed result may
6385 // have a wider width than the expected result. Extract the relevant
6387 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6390 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6393 setValue(CS.getInstruction(), Val);
6394 // Don't need to use this as a chain in this case.
6395 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6399 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6401 // Process indirect outputs, first output all of the flagged copies out of
6403 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6404 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6405 const Value *Ptr = IndirectStoresToEmit[i].second;
6406 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6408 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6411 // Emit the non-flagged stores from the physregs.
6412 SmallVector<SDValue, 8> OutChains;
6413 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6414 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6415 StoresToEmit[i].first,
6416 getValue(StoresToEmit[i].second),
6417 MachinePointerInfo(StoresToEmit[i].second),
6419 OutChains.push_back(Val);
6422 if (!OutChains.empty())
6423 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6428 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6429 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6430 MVT::Other, getRoot(),
6431 getValue(I.getArgOperand(0)),
6432 DAG.getSrcValue(I.getArgOperand(0))));
6435 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6437 const DataLayout &DL = DAG.getDataLayout();
6438 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6439 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6440 DAG.getSrcValue(I.getOperand(0)),
6441 DL.getABITypeAlignment(I.getType()));
6443 DAG.setRoot(V.getValue(1));
6446 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6447 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6448 MVT::Other, getRoot(),
6449 getValue(I.getArgOperand(0)),
6450 DAG.getSrcValue(I.getArgOperand(0))));
6453 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6454 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6455 MVT::Other, getRoot(),
6456 getValue(I.getArgOperand(0)),
6457 getValue(I.getArgOperand(1)),
6458 DAG.getSrcValue(I.getArgOperand(0)),
6459 DAG.getSrcValue(I.getArgOperand(1))));
6462 /// \brief Lower an argument list according to the target calling convention.
6464 /// \return A tuple of <return-value, token-chain>
6466 /// This is a helper for lowering intrinsics that follow a target calling
6467 /// convention or require stack pointer adjustment. Only a subset of the
6468 /// intrinsic's operands need to participate in the calling convention.
6469 std::pair<SDValue, SDValue>
6470 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6471 unsigned NumArgs, SDValue Callee,
6473 MachineBasicBlock *LandingPad,
6474 bool IsPatchPoint) {
6475 TargetLowering::ArgListTy Args;
6476 Args.reserve(NumArgs);
6478 // Populate the argument list.
6479 // Attributes for args start at offset 1, after the return attribute.
6480 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6481 ArgI != ArgE; ++ArgI) {
6482 const Value *V = CS->getOperand(ArgI);
6484 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6486 TargetLowering::ArgListEntry Entry;
6487 Entry.Node = getValue(V);
6488 Entry.Ty = V->getType();
6489 Entry.setAttributes(&CS, AttrI);
6490 Args.push_back(Entry);
6493 TargetLowering::CallLoweringInfo CLI(DAG);
6494 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6495 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6496 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6498 return lowerInvokable(CLI, LandingPad);
6501 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6502 /// or patchpoint target node's operand list.
6504 /// Constants are converted to TargetConstants purely as an optimization to
6505 /// avoid constant materialization and register allocation.
6507 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6508 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6509 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6510 /// address materialization and register allocation, but may also be required
6511 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6512 /// alloca in the entry block, then the runtime may assume that the alloca's
6513 /// StackMap location can be read immediately after compilation and that the
6514 /// location is valid at any point during execution (this is similar to the
6515 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6516 /// only available in a register, then the runtime would need to trap when
6517 /// execution reaches the StackMap in order to read the alloca's location.
6518 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6519 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6520 SelectionDAGBuilder &Builder) {
6521 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6522 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6523 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6525 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6527 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6528 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6529 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6530 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6531 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6533 Ops.push_back(OpVal);
6537 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6538 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6539 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6540 // [live variables...])
6542 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6544 SDValue Chain, InFlag, Callee, NullPtr;
6545 SmallVector<SDValue, 32> Ops;
6547 SDLoc DL = getCurSDLoc();
6548 Callee = getValue(CI.getCalledValue());
6549 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6551 // The stackmap intrinsic only records the live variables (the arguemnts
6552 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6553 // intrinsic, this won't be lowered to a function call. This means we don't
6554 // have to worry about calling conventions and target specific lowering code.
6555 // Instead we perform the call lowering right here.
6557 // chain, flag = CALLSEQ_START(chain, 0)
6558 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6559 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6561 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6562 InFlag = Chain.getValue(1);
6564 // Add the <id> and <numBytes> constants.
6565 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6566 Ops.push_back(DAG.getTargetConstant(
6567 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6568 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6569 Ops.push_back(DAG.getTargetConstant(
6570 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6573 // Push live variables for the stack map.
6574 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6576 // We are not pushing any register mask info here on the operands list,
6577 // because the stackmap doesn't clobber anything.
6579 // Push the chain and the glue flag.
6580 Ops.push_back(Chain);
6581 Ops.push_back(InFlag);
6583 // Create the STACKMAP node.
6584 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6585 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6586 Chain = SDValue(SM, 0);
6587 InFlag = Chain.getValue(1);
6589 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6591 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6593 // Set the root to the target-lowered call chain.
6596 // Inform the Frame Information that we have a stackmap in this function.
6597 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6600 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6601 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6602 MachineBasicBlock *LandingPad) {
6603 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6608 // [live variables...])
6610 CallingConv::ID CC = CS.getCallingConv();
6611 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6612 bool HasDef = !CS->getType()->isVoidTy();
6613 SDLoc dl = getCurSDLoc();
6614 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6616 // Handle immediate and symbolic callees.
6617 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6618 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6620 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6621 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6622 SDLoc(SymbolicCallee),
6623 SymbolicCallee->getValueType(0));
6625 // Get the real number of arguments participating in the call <numArgs>
6626 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6627 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6629 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6630 // Intrinsics include all meta-operands up to but not including CC.
6631 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6632 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6633 "Not enough arguments provided to the patchpoint intrinsic");
6635 // For AnyRegCC the arguments are lowered later on manually.
6636 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6638 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6639 std::pair<SDValue, SDValue> Result =
6640 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6643 SDNode *CallEnd = Result.second.getNode();
6644 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6645 CallEnd = CallEnd->getOperand(0).getNode();
6647 /// Get a call instruction from the call sequence chain.
6648 /// Tail calls are not allowed.
6649 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6650 "Expected a callseq node.");
6651 SDNode *Call = CallEnd->getOperand(0).getNode();
6652 bool HasGlue = Call->getGluedNode();
6654 // Replace the target specific call node with the patchable intrinsic.
6655 SmallVector<SDValue, 8> Ops;
6657 // Add the <id> and <numBytes> constants.
6658 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6659 Ops.push_back(DAG.getTargetConstant(
6660 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6661 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6662 Ops.push_back(DAG.getTargetConstant(
6663 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6667 Ops.push_back(Callee);
6669 // Adjust <numArgs> to account for any arguments that have been passed on the
6671 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6672 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6673 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6674 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6676 // Add the calling convention
6677 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6679 // Add the arguments we omitted previously. The register allocator should
6680 // place these in any free register.
6682 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6683 Ops.push_back(getValue(CS.getArgument(i)));
6685 // Push the arguments from the call instruction up to the register mask.
6686 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6687 Ops.append(Call->op_begin() + 2, e);
6689 // Push live variables for the stack map.
6690 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6692 // Push the register mask info.
6694 Ops.push_back(*(Call->op_end()-2));
6696 Ops.push_back(*(Call->op_end()-1));
6698 // Push the chain (this is originally the first operand of the call, but
6699 // becomes now the last or second to last operand).
6700 Ops.push_back(*(Call->op_begin()));
6702 // Push the glue flag (last operand).
6704 Ops.push_back(*(Call->op_end()-1));
6707 if (IsAnyRegCC && HasDef) {
6708 // Create the return types based on the intrinsic definition
6709 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6710 SmallVector<EVT, 3> ValueVTs;
6711 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6712 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6714 // There is always a chain and a glue type at the end
6715 ValueVTs.push_back(MVT::Other);
6716 ValueVTs.push_back(MVT::Glue);
6717 NodeTys = DAG.getVTList(ValueVTs);
6719 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6721 // Replace the target specific call node with a PATCHPOINT node.
6722 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6725 // Update the NodeMap.
6728 setValue(CS.getInstruction(), SDValue(MN, 0));
6730 setValue(CS.getInstruction(), Result.first);
6733 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6734 // call sequence. Furthermore the location of the chain and glue can change
6735 // when the AnyReg calling convention is used and the intrinsic returns a
6737 if (IsAnyRegCC && HasDef) {
6738 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6739 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6740 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6742 DAG.ReplaceAllUsesWith(Call, MN);
6743 DAG.DeleteNode(Call);
6745 // Inform the Frame Information that we have a patchpoint in this function.
6746 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6749 /// Returns an AttributeSet representing the attributes applied to the return
6750 /// value of the given call.
6751 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6752 SmallVector<Attribute::AttrKind, 2> Attrs;
6754 Attrs.push_back(Attribute::SExt);
6756 Attrs.push_back(Attribute::ZExt);
6758 Attrs.push_back(Attribute::InReg);
6760 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6764 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6765 /// implementation, which just calls LowerCall.
6766 /// FIXME: When all targets are
6767 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6768 std::pair<SDValue, SDValue>
6769 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6770 // Handle the incoming return values from the call.
6772 Type *OrigRetTy = CLI.RetTy;
6773 SmallVector<EVT, 4> RetTys;
6774 SmallVector<uint64_t, 4> Offsets;
6775 auto &DL = CLI.DAG.getDataLayout();
6776 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6778 SmallVector<ISD::OutputArg, 4> Outs;
6779 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6781 bool CanLowerReturn =
6782 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6783 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6785 SDValue DemoteStackSlot;
6786 int DemoteStackIdx = -100;
6787 if (!CanLowerReturn) {
6788 // FIXME: equivalent assert?
6789 // assert(!CS.hasInAllocaArgument() &&
6790 // "sret demotion is incompatible with inalloca");
6791 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6792 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6793 MachineFunction &MF = CLI.DAG.getMachineFunction();
6794 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6795 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6797 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6799 Entry.Node = DemoteStackSlot;
6800 Entry.Ty = StackSlotPtrType;
6801 Entry.isSExt = false;
6802 Entry.isZExt = false;
6803 Entry.isInReg = false;
6804 Entry.isSRet = true;
6805 Entry.isNest = false;
6806 Entry.isByVal = false;
6807 Entry.isReturned = false;
6808 Entry.Alignment = Align;
6809 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6810 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6812 // sret demotion isn't compatible with tail-calls, since the sret argument
6813 // points into the callers stack frame.
6814 CLI.IsTailCall = false;
6816 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6818 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6819 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6820 for (unsigned i = 0; i != NumRegs; ++i) {
6821 ISD::InputArg MyFlags;
6822 MyFlags.VT = RegisterVT;
6824 MyFlags.Used = CLI.IsReturnValueUsed;
6826 MyFlags.Flags.setSExt();
6828 MyFlags.Flags.setZExt();
6830 MyFlags.Flags.setInReg();
6831 CLI.Ins.push_back(MyFlags);
6836 // Handle all of the outgoing arguments.
6838 CLI.OutVals.clear();
6839 ArgListTy &Args = CLI.getArgs();
6840 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6841 SmallVector<EVT, 4> ValueVTs;
6842 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6843 Type *FinalType = Args[i].Ty;
6844 if (Args[i].isByVal)
6845 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6846 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6847 FinalType, CLI.CallConv, CLI.IsVarArg);
6848 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6850 EVT VT = ValueVTs[Value];
6851 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6852 SDValue Op = SDValue(Args[i].Node.getNode(),
6853 Args[i].Node.getResNo() + Value);
6854 ISD::ArgFlagsTy Flags;
6855 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6861 if (Args[i].isInReg)
6865 if (Args[i].isByVal)
6867 if (Args[i].isInAlloca) {
6868 Flags.setInAlloca();
6869 // Set the byval flag for CCAssignFn callbacks that don't know about
6870 // inalloca. This way we can know how many bytes we should've allocated
6871 // and how many bytes a callee cleanup function will pop. If we port
6872 // inalloca to more targets, we'll have to add custom inalloca handling
6873 // in the various CC lowering callbacks.
6876 if (Args[i].isByVal || Args[i].isInAlloca) {
6877 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6878 Type *ElementTy = Ty->getElementType();
6879 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6880 // For ByVal, alignment should come from FE. BE will guess if this
6881 // info is not there but there are cases it cannot get right.
6882 unsigned FrameAlign;
6883 if (Args[i].Alignment)
6884 FrameAlign = Args[i].Alignment;
6886 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6887 Flags.setByValAlign(FrameAlign);
6892 Flags.setInConsecutiveRegs();
6893 Flags.setOrigAlign(OriginalAlignment);
6895 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6896 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6897 SmallVector<SDValue, 4> Parts(NumParts);
6898 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6901 ExtendKind = ISD::SIGN_EXTEND;
6902 else if (Args[i].isZExt)
6903 ExtendKind = ISD::ZERO_EXTEND;
6905 // Conservatively only handle 'returned' on non-vectors for now
6906 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6907 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6908 "unexpected use of 'returned'");
6909 // Before passing 'returned' to the target lowering code, ensure that
6910 // either the register MVT and the actual EVT are the same size or that
6911 // the return value and argument are extended in the same way; in these
6912 // cases it's safe to pass the argument register value unchanged as the
6913 // return register value (although it's at the target's option whether
6915 // TODO: allow code generation to take advantage of partially preserved
6916 // registers rather than clobbering the entire register when the
6917 // parameter extension method is not compatible with the return
6919 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6920 (ExtendKind != ISD::ANY_EXTEND &&
6921 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6922 Flags.setReturned();
6925 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6926 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6928 for (unsigned j = 0; j != NumParts; ++j) {
6929 // if it isn't first piece, alignment must be 1
6930 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6931 i < CLI.NumFixedArgs,
6932 i, j*Parts[j].getValueType().getStoreSize());
6933 if (NumParts > 1 && j == 0)
6934 MyFlags.Flags.setSplit();
6936 MyFlags.Flags.setOrigAlign(1);
6938 CLI.Outs.push_back(MyFlags);
6939 CLI.OutVals.push_back(Parts[j]);
6942 if (NeedsRegBlock && Value == NumValues - 1)
6943 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6947 SmallVector<SDValue, 4> InVals;
6948 CLI.Chain = LowerCall(CLI, InVals);
6950 // Verify that the target's LowerCall behaved as expected.
6951 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6952 "LowerCall didn't return a valid chain!");
6953 assert((!CLI.IsTailCall || InVals.empty()) &&
6954 "LowerCall emitted a return value for a tail call!");
6955 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6956 "LowerCall didn't emit the correct number of values!");
6958 // For a tail call, the return value is merely live-out and there aren't
6959 // any nodes in the DAG representing it. Return a special value to
6960 // indicate that a tail call has been emitted and no more Instructions
6961 // should be processed in the current block.
6962 if (CLI.IsTailCall) {
6963 CLI.DAG.setRoot(CLI.Chain);
6964 return std::make_pair(SDValue(), SDValue());
6967 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6968 assert(InVals[i].getNode() &&
6969 "LowerCall emitted a null value!");
6970 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6971 "LowerCall emitted a value with the wrong type!");
6974 SmallVector<SDValue, 4> ReturnValues;
6975 if (!CanLowerReturn) {
6976 // The instruction result is the result of loading from the
6977 // hidden sret parameter.
6978 SmallVector<EVT, 1> PVTs;
6979 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6981 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
6982 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6983 EVT PtrVT = PVTs[0];
6985 unsigned NumValues = RetTys.size();
6986 ReturnValues.resize(NumValues);
6987 SmallVector<SDValue, 4> Chains(NumValues);
6989 for (unsigned i = 0; i < NumValues; ++i) {
6990 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6991 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6993 SDValue L = CLI.DAG.getLoad(
6994 RetTys[i], CLI.DL, CLI.Chain, Add,
6995 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6997 ReturnValues[i] = L;
6998 Chains[i] = L.getValue(1);
7001 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7003 // Collect the legal value parts into potentially illegal values
7004 // that correspond to the original function's return values.
7005 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7007 AssertOp = ISD::AssertSext;
7008 else if (CLI.RetZExt)
7009 AssertOp = ISD::AssertZext;
7010 unsigned CurReg = 0;
7011 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7013 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7014 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7016 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7017 NumRegs, RegisterVT, VT, nullptr,
7022 // For a function returning void, there is no return value. We can't create
7023 // such a node, so we just return a null return value in that case. In
7024 // that case, nothing will actually look at the value.
7025 if (ReturnValues.empty())
7026 return std::make_pair(SDValue(), CLI.Chain);
7029 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7030 CLI.DAG.getVTList(RetTys), ReturnValues);
7031 return std::make_pair(Res, CLI.Chain);
7034 void TargetLowering::LowerOperationWrapper(SDNode *N,
7035 SmallVectorImpl<SDValue> &Results,
7036 SelectionDAG &DAG) const {
7037 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7039 Results.push_back(Res);
7042 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7043 llvm_unreachable("LowerOperation not implemented for this target!");
7047 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7048 SDValue Op = getNonRegisterValue(V);
7049 assert((Op.getOpcode() != ISD::CopyFromReg ||
7050 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7051 "Copy from a reg to the same reg!");
7052 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7054 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7055 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7057 SDValue Chain = DAG.getEntryNode();
7059 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7060 FuncInfo.PreferredExtendType.end())
7062 : FuncInfo.PreferredExtendType[V];
7063 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7064 PendingExports.push_back(Chain);
7067 #include "llvm/CodeGen/SelectionDAGISel.h"
7069 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7070 /// entry block, return true. This includes arguments used by switches, since
7071 /// the switch may expand into multiple basic blocks.
7072 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7073 // With FastISel active, we may be splitting blocks, so force creation
7074 // of virtual registers for all non-dead arguments.
7076 return A->use_empty();
7078 const BasicBlock *Entry = A->getParent()->begin();
7079 for (const User *U : A->users())
7080 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7081 return false; // Use not in entry block.
7086 void SelectionDAGISel::LowerArguments(const Function &F) {
7087 SelectionDAG &DAG = SDB->DAG;
7088 SDLoc dl = SDB->getCurSDLoc();
7089 const DataLayout &DL = DAG.getDataLayout();
7090 SmallVector<ISD::InputArg, 16> Ins;
7092 if (!FuncInfo->CanLowerReturn) {
7093 // Put in an sret pointer parameter before all the other parameters.
7094 SmallVector<EVT, 1> ValueVTs;
7095 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7096 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7098 // NOTE: Assuming that a pointer will never break down to more than one VT
7100 ISD::ArgFlagsTy Flags;
7102 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7103 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7104 ISD::InputArg::NoArgIndex, 0);
7105 Ins.push_back(RetArg);
7108 // Set up the incoming argument description vector.
7110 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7111 I != E; ++I, ++Idx) {
7112 SmallVector<EVT, 4> ValueVTs;
7113 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7114 bool isArgValueUsed = !I->use_empty();
7115 unsigned PartBase = 0;
7116 Type *FinalType = I->getType();
7117 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7118 FinalType = cast<PointerType>(FinalType)->getElementType();
7119 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7120 FinalType, F.getCallingConv(), F.isVarArg());
7121 for (unsigned Value = 0, NumValues = ValueVTs.size();
7122 Value != NumValues; ++Value) {
7123 EVT VT = ValueVTs[Value];
7124 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7125 ISD::ArgFlagsTy Flags;
7126 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7128 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7130 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7132 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7134 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7136 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7138 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7139 Flags.setInAlloca();
7140 // Set the byval flag for CCAssignFn callbacks that don't know about
7141 // inalloca. This way we can know how many bytes we should've allocated
7142 // and how many bytes a callee cleanup function will pop. If we port
7143 // inalloca to more targets, we'll have to add custom inalloca handling
7144 // in the various CC lowering callbacks.
7147 if (Flags.isByVal() || Flags.isInAlloca()) {
7148 PointerType *Ty = cast<PointerType>(I->getType());
7149 Type *ElementTy = Ty->getElementType();
7150 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7151 // For ByVal, alignment should be passed from FE. BE will guess if
7152 // this info is not there but there are cases it cannot get right.
7153 unsigned FrameAlign;
7154 if (F.getParamAlignment(Idx))
7155 FrameAlign = F.getParamAlignment(Idx);
7157 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7158 Flags.setByValAlign(FrameAlign);
7160 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7163 Flags.setInConsecutiveRegs();
7164 Flags.setOrigAlign(OriginalAlignment);
7166 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7167 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7168 for (unsigned i = 0; i != NumRegs; ++i) {
7169 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7170 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7171 if (NumRegs > 1 && i == 0)
7172 MyFlags.Flags.setSplit();
7173 // if it isn't first piece, alignment must be 1
7175 MyFlags.Flags.setOrigAlign(1);
7176 Ins.push_back(MyFlags);
7178 if (NeedsRegBlock && Value == NumValues - 1)
7179 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7180 PartBase += VT.getStoreSize();
7184 // Call the target to set up the argument values.
7185 SmallVector<SDValue, 8> InVals;
7186 SDValue NewRoot = TLI->LowerFormalArguments(
7187 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7189 // Verify that the target's LowerFormalArguments behaved as expected.
7190 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7191 "LowerFormalArguments didn't return a valid chain!");
7192 assert(InVals.size() == Ins.size() &&
7193 "LowerFormalArguments didn't emit the correct number of values!");
7195 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7196 assert(InVals[i].getNode() &&
7197 "LowerFormalArguments emitted a null value!");
7198 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7199 "LowerFormalArguments emitted a value with the wrong type!");
7203 // Update the DAG with the new chain value resulting from argument lowering.
7204 DAG.setRoot(NewRoot);
7206 // Set up the argument values.
7209 if (!FuncInfo->CanLowerReturn) {
7210 // Create a virtual register for the sret pointer, and put in a copy
7211 // from the sret argument into it.
7212 SmallVector<EVT, 1> ValueVTs;
7213 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7214 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7215 MVT VT = ValueVTs[0].getSimpleVT();
7216 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7217 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7218 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7219 RegVT, VT, nullptr, AssertOp);
7221 MachineFunction& MF = SDB->DAG.getMachineFunction();
7222 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7223 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7224 FuncInfo->DemoteRegister = SRetReg;
7226 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7227 DAG.setRoot(NewRoot);
7229 // i indexes lowered arguments. Bump it past the hidden sret argument.
7230 // Idx indexes LLVM arguments. Don't touch it.
7234 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7236 SmallVector<SDValue, 4> ArgValues;
7237 SmallVector<EVT, 4> ValueVTs;
7238 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7239 unsigned NumValues = ValueVTs.size();
7241 // If this argument is unused then remember its value. It is used to generate
7242 // debugging information.
7243 if (I->use_empty() && NumValues) {
7244 SDB->setUnusedArgValue(I, InVals[i]);
7246 // Also remember any frame index for use in FastISel.
7247 if (FrameIndexSDNode *FI =
7248 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7249 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7252 for (unsigned Val = 0; Val != NumValues; ++Val) {
7253 EVT VT = ValueVTs[Val];
7254 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7255 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7257 if (!I->use_empty()) {
7258 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7259 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7260 AssertOp = ISD::AssertSext;
7261 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7262 AssertOp = ISD::AssertZext;
7264 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7265 NumParts, PartVT, VT,
7266 nullptr, AssertOp));
7272 // We don't need to do anything else for unused arguments.
7273 if (ArgValues.empty())
7276 // Note down frame index.
7277 if (FrameIndexSDNode *FI =
7278 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7279 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7281 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7282 SDB->getCurSDLoc());
7284 SDB->setValue(I, Res);
7285 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7286 if (LoadSDNode *LNode =
7287 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7288 if (FrameIndexSDNode *FI =
7289 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7290 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7293 // If this argument is live outside of the entry block, insert a copy from
7294 // wherever we got it to the vreg that other BB's will reference it as.
7295 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7296 // If we can, though, try to skip creating an unnecessary vreg.
7297 // FIXME: This isn't very clean... it would be nice to make this more
7298 // general. It's also subtly incompatible with the hacks FastISel
7300 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7301 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7302 FuncInfo->ValueMap[I] = Reg;
7306 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7307 FuncInfo->InitializeRegForValue(I);
7308 SDB->CopyToExportRegsIfNeeded(I);
7312 assert(i == InVals.size() && "Argument register count mismatch!");
7314 // Finally, if the target has anything special to do, allow it to do so.
7315 EmitFunctionEntryCode();
7318 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7319 /// ensure constants are generated when needed. Remember the virtual registers
7320 /// that need to be added to the Machine PHI nodes as input. We cannot just
7321 /// directly add them, because expansion might result in multiple MBB's for one
7322 /// BB. As such, the start of the BB might correspond to a different MBB than
7326 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7327 const TerminatorInst *TI = LLVMBB->getTerminator();
7329 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7331 // Check PHI nodes in successors that expect a value to be available from this
7333 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7334 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7335 if (!isa<PHINode>(SuccBB->begin())) continue;
7336 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7338 // If this terminator has multiple identical successors (common for
7339 // switches), only handle each succ once.
7340 if (!SuccsHandled.insert(SuccMBB).second)
7343 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7345 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7346 // nodes and Machine PHI nodes, but the incoming operands have not been
7348 for (BasicBlock::const_iterator I = SuccBB->begin();
7349 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7350 // Ignore dead phi's.
7351 if (PN->use_empty()) continue;
7354 if (PN->getType()->isEmptyTy())
7358 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7360 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7361 unsigned &RegOut = ConstantsOut[C];
7363 RegOut = FuncInfo.CreateRegs(C->getType());
7364 CopyValueToVirtualRegister(C, RegOut);
7368 DenseMap<const Value *, unsigned>::iterator I =
7369 FuncInfo.ValueMap.find(PHIOp);
7370 if (I != FuncInfo.ValueMap.end())
7373 assert(isa<AllocaInst>(PHIOp) &&
7374 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7375 "Didn't codegen value into a register!??");
7376 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7377 CopyValueToVirtualRegister(PHIOp, Reg);
7381 // Remember that this register needs to added to the machine PHI node as
7382 // the input for this MBB.
7383 SmallVector<EVT, 4> ValueVTs;
7384 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7385 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7386 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7387 EVT VT = ValueVTs[vti];
7388 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7389 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7390 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7391 Reg += NumRegisters;
7396 ConstantsOut.clear();
7399 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7402 SelectionDAGBuilder::StackProtectorDescriptor::
7403 AddSuccessorMBB(const BasicBlock *BB,
7404 MachineBasicBlock *ParentMBB,
7406 MachineBasicBlock *SuccMBB) {
7407 // If SuccBB has not been created yet, create it.
7409 MachineFunction *MF = ParentMBB->getParent();
7410 MachineFunction::iterator BBI = ParentMBB;
7411 SuccMBB = MF->CreateMachineBasicBlock(BB);
7412 MF->insert(++BBI, SuccMBB);
7414 // Add it as a successor of ParentMBB.
7415 ParentMBB->addSuccessor(
7416 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7420 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7421 MachineFunction::iterator I = MBB;
7422 if (++I == FuncInfo.MF->end())
7427 /// During lowering new call nodes can be created (such as memset, etc.).
7428 /// Those will become new roots of the current DAG, but complications arise
7429 /// when they are tail calls. In such cases, the call lowering will update
7430 /// the root, but the builder still needs to know that a tail call has been
7431 /// lowered in order to avoid generating an additional return.
7432 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7433 // If the node is null, we do have a tail call.
7434 if (MaybeTC.getNode() != nullptr)
7435 DAG.setRoot(MaybeTC);
7440 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7441 unsigned *TotalCases, unsigned First,
7443 assert(Last >= First);
7444 assert(TotalCases[Last] >= TotalCases[First]);
7446 APInt LowCase = Clusters[First].Low->getValue();
7447 APInt HighCase = Clusters[Last].High->getValue();
7448 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7450 // FIXME: A range of consecutive cases has 100% density, but only requires one
7451 // comparison to lower. We should discriminate against such consecutive ranges
7454 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7455 uint64_t Range = Diff + 1;
7458 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7460 assert(NumCases < UINT64_MAX / 100);
7461 assert(Range >= NumCases);
7463 return NumCases * 100 >= Range * MinJumpTableDensity;
7466 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7467 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7468 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7471 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7472 unsigned First, unsigned Last,
7473 const SwitchInst *SI,
7474 MachineBasicBlock *DefaultMBB,
7475 CaseCluster &JTCluster) {
7476 assert(First <= Last);
7478 uint32_t Weight = 0;
7479 unsigned NumCmps = 0;
7480 std::vector<MachineBasicBlock*> Table;
7481 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7482 for (unsigned I = First; I <= Last; ++I) {
7483 assert(Clusters[I].Kind == CC_Range);
7484 Weight += Clusters[I].Weight;
7485 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7486 APInt Low = Clusters[I].Low->getValue();
7487 APInt High = Clusters[I].High->getValue();
7488 NumCmps += (Low == High) ? 1 : 2;
7490 // Fill the gap between this and the previous cluster.
7491 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7492 assert(PreviousHigh.slt(Low));
7493 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7494 for (uint64_t J = 0; J < Gap; J++)
7495 Table.push_back(DefaultMBB);
7497 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7498 for (uint64_t J = 0; J < ClusterSize; ++J)
7499 Table.push_back(Clusters[I].MBB);
7500 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7503 unsigned NumDests = JTWeights.size();
7504 if (isSuitableForBitTests(NumDests, NumCmps,
7505 Clusters[First].Low->getValue(),
7506 Clusters[Last].High->getValue())) {
7507 // Clusters[First..Last] should be lowered as bit tests instead.
7511 // Create the MBB that will load from and jump through the table.
7512 // Note: We create it here, but it's not inserted into the function yet.
7513 MachineFunction *CurMF = FuncInfo.MF;
7514 MachineBasicBlock *JumpTableMBB =
7515 CurMF->CreateMachineBasicBlock(SI->getParent());
7517 // Add successors. Note: use table order for determinism.
7518 SmallPtrSet<MachineBasicBlock *, 8> Done;
7519 for (MachineBasicBlock *Succ : Table) {
7520 if (Done.count(Succ))
7522 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7526 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7527 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7528 ->createJumpTableIndex(Table);
7530 // Set up the jump table info.
7531 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7532 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7533 Clusters[Last].High->getValue(), SI->getCondition(),
7535 JTCases.emplace_back(std::move(JTH), std::move(JT));
7537 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7538 JTCases.size() - 1, Weight);
7542 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7543 const SwitchInst *SI,
7544 MachineBasicBlock *DefaultMBB) {
7546 // Clusters must be non-empty, sorted, and only contain Range clusters.
7547 assert(!Clusters.empty());
7548 for (CaseCluster &C : Clusters)
7549 assert(C.Kind == CC_Range);
7550 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7551 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7555 if (!areJTsAllowed(TLI))
7558 const int64_t N = Clusters.size();
7559 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7561 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7562 SmallVector<unsigned, 8> TotalCases(N);
7564 for (unsigned i = 0; i < N; ++i) {
7565 APInt Hi = Clusters[i].High->getValue();
7566 APInt Lo = Clusters[i].Low->getValue();
7567 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7569 TotalCases[i] += TotalCases[i - 1];
7572 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7573 // Cheap case: the whole range might be suitable for jump table.
7574 CaseCluster JTCluster;
7575 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7576 Clusters[0] = JTCluster;
7582 // The algorithm below is not suitable for -O0.
7583 if (TM.getOptLevel() == CodeGenOpt::None)
7586 // Split Clusters into minimum number of dense partitions. The algorithm uses
7587 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7588 // for the Case Statement'" (1994), but builds the MinPartitions array in
7589 // reverse order to make it easier to reconstruct the partitions in ascending
7590 // order. In the choice between two optimal partitionings, it picks the one
7591 // which yields more jump tables.
7593 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7594 SmallVector<unsigned, 8> MinPartitions(N);
7595 // LastElement[i] is the last element of the partition starting at i.
7596 SmallVector<unsigned, 8> LastElement(N);
7597 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7598 SmallVector<unsigned, 8> NumTables(N);
7600 // Base case: There is only one way to partition Clusters[N-1].
7601 MinPartitions[N - 1] = 1;
7602 LastElement[N - 1] = N - 1;
7603 assert(MinJumpTableSize > 1);
7604 NumTables[N - 1] = 0;
7606 // Note: loop indexes are signed to avoid underflow.
7607 for (int64_t i = N - 2; i >= 0; i--) {
7608 // Find optimal partitioning of Clusters[i..N-1].
7609 // Baseline: Put Clusters[i] into a partition on its own.
7610 MinPartitions[i] = MinPartitions[i + 1] + 1;
7612 NumTables[i] = NumTables[i + 1];
7614 // Search for a solution that results in fewer partitions.
7615 for (int64_t j = N - 1; j > i; j--) {
7616 // Try building a partition from Clusters[i..j].
7617 if (isDense(Clusters, &TotalCases[0], i, j)) {
7618 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7619 bool IsTable = j - i + 1 >= MinJumpTableSize;
7620 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7622 // If this j leads to fewer partitions, or same number of partitions
7623 // with more lookup tables, it is a better partitioning.
7624 if (NumPartitions < MinPartitions[i] ||
7625 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7626 MinPartitions[i] = NumPartitions;
7628 NumTables[i] = Tables;
7634 // Iterate over the partitions, replacing some with jump tables in-place.
7635 unsigned DstIndex = 0;
7636 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7637 Last = LastElement[First];
7638 assert(Last >= First);
7639 assert(DstIndex <= First);
7640 unsigned NumClusters = Last - First + 1;
7642 CaseCluster JTCluster;
7643 if (NumClusters >= MinJumpTableSize &&
7644 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7645 Clusters[DstIndex++] = JTCluster;
7647 for (unsigned I = First; I <= Last; ++I)
7648 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7651 Clusters.resize(DstIndex);
7654 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7655 // FIXME: Using the pointer type doesn't seem ideal.
7656 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7657 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7661 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7664 const APInt &High) {
7665 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7666 // range of cases both require only one branch to lower. Just looking at the
7667 // number of clusters and destinations should be enough to decide whether to
7670 // To lower a range with bit tests, the range must fit the bitwidth of a
7672 if (!rangeFitsInWord(Low, High))
7675 // Decide whether it's profitable to lower this range with bit tests. Each
7676 // destination requires a bit test and branch, and there is an overall range
7677 // check branch. For a small number of clusters, separate comparisons might be
7678 // cheaper, and for many destinations, splitting the range might be better.
7679 return (NumDests == 1 && NumCmps >= 3) ||
7680 (NumDests == 2 && NumCmps >= 5) ||
7681 (NumDests == 3 && NumCmps >= 6);
7684 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7685 unsigned First, unsigned Last,
7686 const SwitchInst *SI,
7687 CaseCluster &BTCluster) {
7688 assert(First <= Last);
7692 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7693 unsigned NumCmps = 0;
7694 for (int64_t I = First; I <= Last; ++I) {
7695 assert(Clusters[I].Kind == CC_Range);
7696 Dests.set(Clusters[I].MBB->getNumber());
7697 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7699 unsigned NumDests = Dests.count();
7701 APInt Low = Clusters[First].Low->getValue();
7702 APInt High = Clusters[Last].High->getValue();
7703 assert(Low.slt(High));
7705 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7711 const int BitWidth = DAG.getTargetLoweringInfo()
7712 .getPointerTy(DAG.getDataLayout())
7714 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7716 if (Low.isNonNegative() && High.slt(BitWidth)) {
7717 // Optimize the case where all the case values fit in a
7718 // word without having to subtract minValue. In this case,
7719 // we can optimize away the subtraction.
7720 LowBound = APInt::getNullValue(Low.getBitWidth());
7724 CmpRange = High - Low;
7728 uint32_t TotalWeight = 0;
7729 for (unsigned i = First; i <= Last; ++i) {
7730 // Find the CaseBits for this destination.
7732 for (j = 0; j < CBV.size(); ++j)
7733 if (CBV[j].BB == Clusters[i].MBB)
7735 if (j == CBV.size())
7736 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7737 CaseBits *CB = &CBV[j];
7739 // Update Mask, Bits and ExtraWeight.
7740 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7741 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7742 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7743 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7744 CB->Bits += Hi - Lo + 1;
7745 CB->ExtraWeight += Clusters[i].Weight;
7746 TotalWeight += Clusters[i].Weight;
7747 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7751 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7752 // Sort by weight first, number of bits second.
7753 if (a.ExtraWeight != b.ExtraWeight)
7754 return a.ExtraWeight > b.ExtraWeight;
7755 return a.Bits > b.Bits;
7758 for (auto &CB : CBV) {
7759 MachineBasicBlock *BitTestBB =
7760 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7761 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7763 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7764 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7765 nullptr, std::move(BTI));
7767 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7768 BitTestCases.size() - 1, TotalWeight);
7772 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7773 const SwitchInst *SI) {
7774 // Partition Clusters into as few subsets as possible, where each subset has a
7775 // range that fits in a machine word and has <= 3 unique destinations.
7778 // Clusters must be sorted and contain Range or JumpTable clusters.
7779 assert(!Clusters.empty());
7780 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7781 for (const CaseCluster &C : Clusters)
7782 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7783 for (unsigned i = 1; i < Clusters.size(); ++i)
7784 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7787 // The algorithm below is not suitable for -O0.
7788 if (TM.getOptLevel() == CodeGenOpt::None)
7791 // If target does not have legal shift left, do not emit bit tests at all.
7792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7793 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7794 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7797 int BitWidth = PTy.getSizeInBits();
7798 const int64_t N = Clusters.size();
7800 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7801 SmallVector<unsigned, 8> MinPartitions(N);
7802 // LastElement[i] is the last element of the partition starting at i.
7803 SmallVector<unsigned, 8> LastElement(N);
7805 // FIXME: This might not be the best algorithm for finding bit test clusters.
7807 // Base case: There is only one way to partition Clusters[N-1].
7808 MinPartitions[N - 1] = 1;
7809 LastElement[N - 1] = N - 1;
7811 // Note: loop indexes are signed to avoid underflow.
7812 for (int64_t i = N - 2; i >= 0; --i) {
7813 // Find optimal partitioning of Clusters[i..N-1].
7814 // Baseline: Put Clusters[i] into a partition on its own.
7815 MinPartitions[i] = MinPartitions[i + 1] + 1;
7818 // Search for a solution that results in fewer partitions.
7819 // Note: the search is limited by BitWidth, reducing time complexity.
7820 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7821 // Try building a partition from Clusters[i..j].
7824 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7825 Clusters[j].High->getValue()))
7828 // Check nbr of destinations and cluster types.
7829 // FIXME: This works, but doesn't seem very efficient.
7830 bool RangesOnly = true;
7831 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7832 for (int64_t k = i; k <= j; k++) {
7833 if (Clusters[k].Kind != CC_Range) {
7837 Dests.set(Clusters[k].MBB->getNumber());
7839 if (!RangesOnly || Dests.count() > 3)
7842 // Check if it's a better partition.
7843 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7844 if (NumPartitions < MinPartitions[i]) {
7845 // Found a better partition.
7846 MinPartitions[i] = NumPartitions;
7852 // Iterate over the partitions, replacing with bit-test clusters in-place.
7853 unsigned DstIndex = 0;
7854 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7855 Last = LastElement[First];
7856 assert(First <= Last);
7857 assert(DstIndex <= First);
7859 CaseCluster BitTestCluster;
7860 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7861 Clusters[DstIndex++] = BitTestCluster;
7863 size_t NumClusters = Last - First + 1;
7864 std::memmove(&Clusters[DstIndex], &Clusters[First],
7865 sizeof(Clusters[0]) * NumClusters);
7866 DstIndex += NumClusters;
7869 Clusters.resize(DstIndex);
7872 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7873 MachineBasicBlock *SwitchMBB,
7874 MachineBasicBlock *DefaultMBB) {
7875 MachineFunction *CurMF = FuncInfo.MF;
7876 MachineBasicBlock *NextMBB = nullptr;
7877 MachineFunction::iterator BBI = W.MBB;
7878 if (++BBI != FuncInfo.MF->end())
7881 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7883 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7885 if (Size == 2 && W.MBB == SwitchMBB) {
7886 // If any two of the cases has the same destination, and if one value
7887 // is the same as the other, but has one bit unset that the other has set,
7888 // use bit manipulation to do two compares at once. For example:
7889 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7890 // TODO: This could be extended to merge any 2 cases in switches with 3
7892 // TODO: Handle cases where W.CaseBB != SwitchBB.
7893 CaseCluster &Small = *W.FirstCluster;
7894 CaseCluster &Big = *W.LastCluster;
7896 if (Small.Low == Small.High && Big.Low == Big.High &&
7897 Small.MBB == Big.MBB) {
7898 const APInt &SmallValue = Small.Low->getValue();
7899 const APInt &BigValue = Big.Low->getValue();
7901 // Check that there is only one bit different.
7902 APInt CommonBit = BigValue ^ SmallValue;
7903 if (CommonBit.isPowerOf2()) {
7904 SDValue CondLHS = getValue(Cond);
7905 EVT VT = CondLHS.getValueType();
7906 SDLoc DL = getCurSDLoc();
7908 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7909 DAG.getConstant(CommonBit, DL, VT));
7910 SDValue Cond = DAG.getSetCC(
7911 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7914 // Update successor info.
7915 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7916 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7917 addSuccessorWithWeight(
7918 SwitchMBB, DefaultMBB,
7919 // The default destination is the first successor in IR.
7920 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7923 // Insert the true branch.
7925 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7926 DAG.getBasicBlock(Small.MBB));
7927 // Insert the false branch.
7928 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7929 DAG.getBasicBlock(DefaultMBB));
7931 DAG.setRoot(BrCond);
7937 if (TM.getOptLevel() != CodeGenOpt::None) {
7938 // Order cases by weight so the most likely case will be checked first.
7939 std::sort(W.FirstCluster, W.LastCluster + 1,
7940 [](const CaseCluster &a, const CaseCluster &b) {
7941 return a.Weight > b.Weight;
7944 // Rearrange the case blocks so that the last one falls through if possible
7945 // without without changing the order of weights.
7946 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7948 if (I->Weight > W.LastCluster->Weight)
7950 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7951 std::swap(*I, *W.LastCluster);
7957 // Compute total weight.
7958 uint32_t UnhandledWeights = 0;
7959 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7960 UnhandledWeights += I->Weight;
7961 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7964 MachineBasicBlock *CurMBB = W.MBB;
7965 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7966 MachineBasicBlock *Fallthrough;
7967 if (I == W.LastCluster) {
7968 // For the last cluster, fall through to the default destination.
7969 Fallthrough = DefaultMBB;
7971 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7972 CurMF->insert(BBI, Fallthrough);
7973 // Put Cond in a virtual register to make it available from the new blocks.
7974 ExportFromCurrentBlock(Cond);
7978 case CC_JumpTable: {
7979 // FIXME: Optimize away range check based on pivot comparisons.
7980 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7981 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7983 // The jump block hasn't been inserted yet; insert it here.
7984 MachineBasicBlock *JumpMBB = JT->MBB;
7985 CurMF->insert(BBI, JumpMBB);
7986 addSuccessorWithWeight(CurMBB, Fallthrough);
7987 addSuccessorWithWeight(CurMBB, JumpMBB);
7989 // The jump table header will be inserted in our current block, do the
7990 // range check, and fall through to our fallthrough block.
7991 JTH->HeaderBB = CurMBB;
7992 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7994 // If we're in the right place, emit the jump table header right now.
7995 if (CurMBB == SwitchMBB) {
7996 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7997 JTH->Emitted = true;
8002 // FIXME: Optimize away range check based on pivot comparisons.
8003 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8005 // The bit test blocks haven't been inserted yet; insert them here.
8006 for (BitTestCase &BTC : BTB->Cases)
8007 CurMF->insert(BBI, BTC.ThisBB);
8009 // Fill in fields of the BitTestBlock.
8010 BTB->Parent = CurMBB;
8011 BTB->Default = Fallthrough;
8013 // If we're in the right place, emit the bit test header header right now.
8014 if (CurMBB ==SwitchMBB) {
8015 visitBitTestHeader(*BTB, SwitchMBB);
8016 BTB->Emitted = true;
8021 const Value *RHS, *LHS, *MHS;
8023 if (I->Low == I->High) {
8024 // Check Cond == I->Low.
8030 // Check I->Low <= Cond <= I->High.
8037 // The false weight is the sum of all unhandled cases.
8038 UnhandledWeights -= I->Weight;
8039 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8042 if (CurMBB == SwitchMBB)
8043 visitSwitchCase(CB, SwitchMBB);
8045 SwitchCases.push_back(CB);
8050 CurMBB = Fallthrough;
8054 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8055 CaseClusterIt First,
8056 CaseClusterIt Last) {
8057 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8058 if (X.Weight != CC.Weight)
8059 return X.Weight > CC.Weight;
8061 // Ties are broken by comparing the case value.
8062 return X.Low->getValue().slt(CC.Low->getValue());
8066 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8067 const SwitchWorkListItem &W,
8069 MachineBasicBlock *SwitchMBB) {
8070 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8071 "Clusters not sorted?");
8073 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8075 // Balance the tree based on branch weights to create a near-optimal (in terms
8076 // of search time given key frequency) binary search tree. See e.g. Kurt
8077 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8078 CaseClusterIt LastLeft = W.FirstCluster;
8079 CaseClusterIt FirstRight = W.LastCluster;
8080 uint32_t LeftWeight = LastLeft->Weight;
8081 uint32_t RightWeight = FirstRight->Weight;
8083 // Move LastLeft and FirstRight towards each other from opposite directions to
8084 // find a partitioning of the clusters which balances the weight on both
8085 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8086 // taken to ensure 0-weight nodes are distributed evenly.
8088 while (LastLeft + 1 < FirstRight) {
8089 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8090 LeftWeight += (++LastLeft)->Weight;
8092 RightWeight += (--FirstRight)->Weight;
8097 // Our binary search tree differs from a typical BST in that ours can have up
8098 // to three values in each leaf. The pivot selection above doesn't take that
8099 // into account, which means the tree might require more nodes and be less
8100 // efficient. We compensate for this here.
8102 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8103 unsigned NumRight = W.LastCluster - FirstRight + 1;
8105 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8106 // If one side has less than 3 clusters, and the other has more than 3,
8107 // consider taking a cluster from the other side.
8109 if (NumLeft < NumRight) {
8110 // Consider moving the first cluster on the right to the left side.
8111 CaseCluster &CC = *FirstRight;
8112 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8113 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8114 if (LeftSideRank <= RightSideRank) {
8115 // Moving the cluster to the left does not demote it.
8121 assert(NumRight < NumLeft);
8122 // Consider moving the last element on the left to the right side.
8123 CaseCluster &CC = *LastLeft;
8124 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8125 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8126 if (RightSideRank <= LeftSideRank) {
8127 // Moving the cluster to the right does not demot it.
8137 assert(LastLeft + 1 == FirstRight);
8138 assert(LastLeft >= W.FirstCluster);
8139 assert(FirstRight <= W.LastCluster);
8141 // Use the first element on the right as pivot since we will make less-than
8142 // comparisons against it.
8143 CaseClusterIt PivotCluster = FirstRight;
8144 assert(PivotCluster > W.FirstCluster);
8145 assert(PivotCluster <= W.LastCluster);
8147 CaseClusterIt FirstLeft = W.FirstCluster;
8148 CaseClusterIt LastRight = W.LastCluster;
8150 const ConstantInt *Pivot = PivotCluster->Low;
8152 // New blocks will be inserted immediately after the current one.
8153 MachineFunction::iterator BBI = W.MBB;
8156 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8157 // we can branch to its destination directly if it's squeezed exactly in
8158 // between the known lower bound and Pivot - 1.
8159 MachineBasicBlock *LeftMBB;
8160 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8161 FirstLeft->Low == W.GE &&
8162 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8163 LeftMBB = FirstLeft->MBB;
8165 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8166 FuncInfo.MF->insert(BBI, LeftMBB);
8167 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8168 // Put Cond in a virtual register to make it available from the new blocks.
8169 ExportFromCurrentBlock(Cond);
8172 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8173 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8174 // directly if RHS.High equals the current upper bound.
8175 MachineBasicBlock *RightMBB;
8176 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8177 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8178 RightMBB = FirstRight->MBB;
8180 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8181 FuncInfo.MF->insert(BBI, RightMBB);
8182 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8183 // Put Cond in a virtual register to make it available from the new blocks.
8184 ExportFromCurrentBlock(Cond);
8187 // Create the CaseBlock record that will be used to lower the branch.
8188 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8189 LeftWeight, RightWeight);
8191 if (W.MBB == SwitchMBB)
8192 visitSwitchCase(CB, SwitchMBB);
8194 SwitchCases.push_back(CB);
8197 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8198 // Extract cases from the switch.
8199 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8200 CaseClusterVector Clusters;
8201 Clusters.reserve(SI.getNumCases());
8202 for (auto I : SI.cases()) {
8203 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8204 const ConstantInt *CaseVal = I.getCaseValue();
8206 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8207 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8210 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8212 // Cluster adjacent cases with the same destination. We do this at all
8213 // optimization levels because it's cheap to do and will make codegen faster
8214 // if there are many clusters.
8215 sortAndRangeify(Clusters);
8217 if (TM.getOptLevel() != CodeGenOpt::None) {
8218 // Replace an unreachable default with the most popular destination.
8219 // FIXME: Exploit unreachable default more aggressively.
8220 bool UnreachableDefault =
8221 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8222 if (UnreachableDefault && !Clusters.empty()) {
8223 DenseMap<const BasicBlock *, unsigned> Popularity;
8224 unsigned MaxPop = 0;
8225 const BasicBlock *MaxBB = nullptr;
8226 for (auto I : SI.cases()) {
8227 const BasicBlock *BB = I.getCaseSuccessor();
8228 if (++Popularity[BB] > MaxPop) {
8229 MaxPop = Popularity[BB];
8234 assert(MaxPop > 0 && MaxBB);
8235 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8237 // Remove cases that were pointing to the destination that is now the
8239 CaseClusterVector New;
8240 New.reserve(Clusters.size());
8241 for (CaseCluster &CC : Clusters) {
8242 if (CC.MBB != DefaultMBB)
8245 Clusters = std::move(New);
8249 // If there is only the default destination, jump there directly.
8250 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8251 if (Clusters.empty()) {
8252 SwitchMBB->addSuccessor(DefaultMBB);
8253 if (DefaultMBB != NextBlock(SwitchMBB)) {
8254 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8255 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8260 findJumpTables(Clusters, &SI, DefaultMBB);
8261 findBitTestClusters(Clusters, &SI);
8264 dbgs() << "Case clusters: ";
8265 for (const CaseCluster &C : Clusters) {
8266 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8267 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8269 C.Low->getValue().print(dbgs(), true);
8270 if (C.Low != C.High) {
8272 C.High->getValue().print(dbgs(), true);
8279 assert(!Clusters.empty());
8280 SwitchWorkList WorkList;
8281 CaseClusterIt First = Clusters.begin();
8282 CaseClusterIt Last = Clusters.end() - 1;
8283 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8285 while (!WorkList.empty()) {
8286 SwitchWorkListItem W = WorkList.back();
8287 WorkList.pop_back();
8288 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8290 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8291 // For optimized builds, lower large range as a balanced binary tree.
8292 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8296 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);