1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 llvm_unreachable("should never codegen catchpads");
1166 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1167 // Update machine-CFG edge.
1168 MachineBasicBlock *PadMBB = FuncInfo.MBB;
1169 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1170 PadMBB->addSuccessor(TargetMBB);
1172 // Create the terminator node.
1173 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1174 getControlRoot(), DAG.getBasicBlock(TargetMBB));
1178 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1179 llvm_unreachable("should never codegen catchendpads");
1182 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1183 report_fatal_error("visitCleanupPad not yet implemented!");
1186 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1187 report_fatal_error("visitCleanupRet not yet implemented!");
1190 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1191 report_fatal_error("visitCleanupEndPad not yet implemented!");
1194 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1195 report_fatal_error("visitTerminatePad not yet implemented!");
1198 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1200 auto &DL = DAG.getDataLayout();
1201 SDValue Chain = getControlRoot();
1202 SmallVector<ISD::OutputArg, 8> Outs;
1203 SmallVector<SDValue, 8> OutVals;
1205 if (!FuncInfo.CanLowerReturn) {
1206 unsigned DemoteReg = FuncInfo.DemoteRegister;
1207 const Function *F = I.getParent()->getParent();
1209 // Emit a store of the return value through the virtual register.
1210 // Leave Outs empty so that LowerReturn won't try to load return
1211 // registers the usual way.
1212 SmallVector<EVT, 1> PtrValueVTs;
1213 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1216 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1217 SDValue RetOp = getValue(I.getOperand(0));
1219 SmallVector<EVT, 4> ValueVTs;
1220 SmallVector<uint64_t, 4> Offsets;
1221 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1222 unsigned NumValues = ValueVTs.size();
1224 SmallVector<SDValue, 4> Chains(NumValues);
1225 for (unsigned i = 0; i != NumValues; ++i) {
1226 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1227 RetPtr.getValueType(), RetPtr,
1228 DAG.getIntPtrConstant(Offsets[i],
1231 DAG.getStore(Chain, getCurSDLoc(),
1232 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1233 // FIXME: better loc info would be nice.
1234 Add, MachinePointerInfo(), false, false, 0);
1237 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1238 MVT::Other, Chains);
1239 } else if (I.getNumOperands() != 0) {
1240 SmallVector<EVT, 4> ValueVTs;
1241 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1242 unsigned NumValues = ValueVTs.size();
1244 SDValue RetOp = getValue(I.getOperand(0));
1246 const Function *F = I.getParent()->getParent();
1248 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1249 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1251 ExtendKind = ISD::SIGN_EXTEND;
1252 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1254 ExtendKind = ISD::ZERO_EXTEND;
1256 LLVMContext &Context = F->getContext();
1257 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 for (unsigned j = 0; j != NumValues; ++j) {
1261 EVT VT = ValueVTs[j];
1263 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1264 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1266 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1267 MVT PartVT = TLI.getRegisterType(Context, VT);
1268 SmallVector<SDValue, 4> Parts(NumParts);
1269 getCopyToParts(DAG, getCurSDLoc(),
1270 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1271 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1273 // 'inreg' on function refers to return value
1274 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1278 // Propagate extension type if any
1279 if (ExtendKind == ISD::SIGN_EXTEND)
1281 else if (ExtendKind == ISD::ZERO_EXTEND)
1284 for (unsigned i = 0; i < NumParts; ++i) {
1285 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1286 VT, /*isfixed=*/true, 0, 0));
1287 OutVals.push_back(Parts[i]);
1293 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1294 CallingConv::ID CallConv =
1295 DAG.getMachineFunction().getFunction()->getCallingConv();
1296 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1297 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1299 // Verify that the target's LowerReturn behaved as expected.
1300 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1301 "LowerReturn didn't return a valid chain!");
1303 // Update the DAG with the new chain value resulting from return lowering.
1307 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1308 /// created for it, emit nodes to copy the value into the virtual
1310 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1312 if (V->getType()->isEmptyTy())
1315 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1316 if (VMI != FuncInfo.ValueMap.end()) {
1317 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1318 CopyValueToVirtualRegister(V, VMI->second);
1322 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1323 /// the current basic block, add it to ValueMap now so that we'll get a
1325 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1326 // No need to export constants.
1327 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1329 // Already exported?
1330 if (FuncInfo.isExportedInst(V)) return;
1332 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1333 CopyValueToVirtualRegister(V, Reg);
1336 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1337 const BasicBlock *FromBB) {
1338 // The operands of the setcc have to be in this block. We don't know
1339 // how to export them from some other block.
1340 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1341 // Can export from current BB.
1342 if (VI->getParent() == FromBB)
1345 // Is already exported, noop.
1346 return FuncInfo.isExportedInst(V);
1349 // If this is an argument, we can export it if the BB is the entry block or
1350 // if it is already exported.
1351 if (isa<Argument>(V)) {
1352 if (FromBB == &FromBB->getParent()->getEntryBlock())
1355 // Otherwise, can only export this if it is already exported.
1356 return FuncInfo.isExportedInst(V);
1359 // Otherwise, constants can always be exported.
1363 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1364 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1365 const MachineBasicBlock *Dst) const {
1366 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1369 const BasicBlock *SrcBB = Src->getBasicBlock();
1370 const BasicBlock *DstBB = Dst->getBasicBlock();
1371 return BPI->getEdgeWeight(SrcBB, DstBB);
1374 void SelectionDAGBuilder::
1375 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1376 uint32_t Weight /* = 0 */) {
1378 Weight = getEdgeWeight(Src, Dst);
1379 Src->addSuccessor(Dst, Weight);
1383 static bool InBlock(const Value *V, const BasicBlock *BB) {
1384 if (const Instruction *I = dyn_cast<Instruction>(V))
1385 return I->getParent() == BB;
1389 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1390 /// This function emits a branch and is used at the leaves of an OR or an
1391 /// AND operator tree.
1394 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1395 MachineBasicBlock *TBB,
1396 MachineBasicBlock *FBB,
1397 MachineBasicBlock *CurBB,
1398 MachineBasicBlock *SwitchBB,
1401 const BasicBlock *BB = CurBB->getBasicBlock();
1403 // If the leaf of the tree is a comparison, merge the condition into
1405 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1406 // The operands of the cmp have to be in this block. We don't know
1407 // how to export them from some other block. If this is the first block
1408 // of the sequence, no exporting is needed.
1409 if (CurBB == SwitchBB ||
1410 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1411 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1412 ISD::CondCode Condition;
1413 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1414 Condition = getICmpCondCode(IC->getPredicate());
1416 const FCmpInst *FC = cast<FCmpInst>(Cond);
1417 Condition = getFCmpCondCode(FC->getPredicate());
1418 if (TM.Options.NoNaNsFPMath)
1419 Condition = getFCmpCodeWithoutNaN(Condition);
1422 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1423 TBB, FBB, CurBB, TWeight, FWeight);
1424 SwitchCases.push_back(CB);
1429 // Create a CaseBlock record representing this branch.
1430 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1431 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1432 SwitchCases.push_back(CB);
1435 /// Scale down both weights to fit into uint32_t.
1436 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1437 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1438 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1439 NewTrue = NewTrue / Scale;
1440 NewFalse = NewFalse / Scale;
1443 /// FindMergedConditions - If Cond is an expression like
1444 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1445 MachineBasicBlock *TBB,
1446 MachineBasicBlock *FBB,
1447 MachineBasicBlock *CurBB,
1448 MachineBasicBlock *SwitchBB,
1449 Instruction::BinaryOps Opc,
1452 // If this node is not part of the or/and tree, emit it as a branch.
1453 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1454 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1455 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1456 BOp->getParent() != CurBB->getBasicBlock() ||
1457 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1458 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1459 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1464 // Create TmpBB after CurBB.
1465 MachineFunction::iterator BBI = CurBB;
1466 MachineFunction &MF = DAG.getMachineFunction();
1467 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1468 CurBB->getParent()->insert(++BBI, TmpBB);
1470 if (Opc == Instruction::Or) {
1471 // Codegen X | Y as:
1480 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1481 // The requirement is that
1482 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1483 // = TrueProb for original BB.
1484 // Assuming the original weights are A and B, one choice is to set BB1's
1485 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1487 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1488 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1489 // TmpBB, but the math is more complicated.
1491 uint64_t NewTrueWeight = TWeight;
1492 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1493 ScaleWeights(NewTrueWeight, NewFalseWeight);
1494 // Emit the LHS condition.
1495 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1496 NewTrueWeight, NewFalseWeight);
1498 NewTrueWeight = TWeight;
1499 NewFalseWeight = 2 * (uint64_t)FWeight;
1500 ScaleWeights(NewTrueWeight, NewFalseWeight);
1501 // Emit the RHS condition into TmpBB.
1502 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1503 NewTrueWeight, NewFalseWeight);
1505 assert(Opc == Instruction::And && "Unknown merge op!");
1506 // Codegen X & Y as:
1514 // This requires creation of TmpBB after CurBB.
1516 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1517 // The requirement is that
1518 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1519 // = FalseProb for original BB.
1520 // Assuming the original weights are A and B, one choice is to set BB1's
1521 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1523 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1525 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1526 uint64_t NewFalseWeight = FWeight;
1527 ScaleWeights(NewTrueWeight, NewFalseWeight);
1528 // Emit the LHS condition.
1529 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1530 NewTrueWeight, NewFalseWeight);
1532 NewTrueWeight = 2 * (uint64_t)TWeight;
1533 NewFalseWeight = FWeight;
1534 ScaleWeights(NewTrueWeight, NewFalseWeight);
1535 // Emit the RHS condition into TmpBB.
1536 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1537 NewTrueWeight, NewFalseWeight);
1541 /// If the set of cases should be emitted as a series of branches, return true.
1542 /// If we should emit this as a bunch of and/or'd together conditions, return
1545 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1546 if (Cases.size() != 2) return true;
1548 // If this is two comparisons of the same values or'd or and'd together, they
1549 // will get folded into a single comparison, so don't emit two blocks.
1550 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1551 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1552 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1553 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1557 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1558 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1559 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1560 Cases[0].CC == Cases[1].CC &&
1561 isa<Constant>(Cases[0].CmpRHS) &&
1562 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1563 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1565 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1572 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1573 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1575 // Update machine-CFG edges.
1576 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1578 if (I.isUnconditional()) {
1579 // Update machine-CFG edges.
1580 BrMBB->addSuccessor(Succ0MBB);
1582 // If this is not a fall-through branch or optimizations are switched off,
1584 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1585 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1586 MVT::Other, getControlRoot(),
1587 DAG.getBasicBlock(Succ0MBB)));
1592 // If this condition is one of the special cases we handle, do special stuff
1594 const Value *CondVal = I.getCondition();
1595 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1597 // If this is a series of conditions that are or'd or and'd together, emit
1598 // this as a sequence of branches instead of setcc's with and/or operations.
1599 // As long as jumps are not expensive, this should improve performance.
1600 // For example, instead of something like:
1613 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1614 Instruction::BinaryOps Opcode = BOp->getOpcode();
1615 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1616 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1617 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1618 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1619 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1620 getEdgeWeight(BrMBB, Succ1MBB));
1621 // If the compares in later blocks need to use values not currently
1622 // exported from this block, export them now. This block should always
1623 // be the first entry.
1624 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1626 // Allow some cases to be rejected.
1627 if (ShouldEmitAsBranches(SwitchCases)) {
1628 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1629 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1630 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1633 // Emit the branch for this block.
1634 visitSwitchCase(SwitchCases[0], BrMBB);
1635 SwitchCases.erase(SwitchCases.begin());
1639 // Okay, we decided not to do this, remove any inserted MBB's and clear
1641 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1642 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1644 SwitchCases.clear();
1648 // Create a CaseBlock record representing this branch.
1649 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1650 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1652 // Use visitSwitchCase to actually insert the fast branch sequence for this
1654 visitSwitchCase(CB, BrMBB);
1657 /// visitSwitchCase - Emits the necessary code to represent a single node in
1658 /// the binary search tree resulting from lowering a switch instruction.
1659 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1660 MachineBasicBlock *SwitchBB) {
1662 SDValue CondLHS = getValue(CB.CmpLHS);
1663 SDLoc dl = getCurSDLoc();
1665 // Build the setcc now.
1667 // Fold "(X == true)" to X and "(X == false)" to !X to
1668 // handle common cases produced by branch lowering.
1669 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1670 CB.CC == ISD::SETEQ)
1672 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1673 CB.CC == ISD::SETEQ) {
1674 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1675 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1677 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1679 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1681 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1682 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1684 SDValue CmpOp = getValue(CB.CmpMHS);
1685 EVT VT = CmpOp.getValueType();
1687 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1688 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1691 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1692 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1693 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1694 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1698 // Update successor info
1699 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1700 // TrueBB and FalseBB are always different unless the incoming IR is
1701 // degenerate. This only happens when running llc on weird IR.
1702 if (CB.TrueBB != CB.FalseBB)
1703 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1705 // If the lhs block is the next block, invert the condition so that we can
1706 // fall through to the lhs instead of the rhs block.
1707 if (CB.TrueBB == NextBlock(SwitchBB)) {
1708 std::swap(CB.TrueBB, CB.FalseBB);
1709 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1710 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1713 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1714 MVT::Other, getControlRoot(), Cond,
1715 DAG.getBasicBlock(CB.TrueBB));
1717 // Insert the false branch. Do this even if it's a fall through branch,
1718 // this makes it easier to do DAG optimizations which require inverting
1719 // the branch condition.
1720 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1721 DAG.getBasicBlock(CB.FalseBB));
1723 DAG.setRoot(BrCond);
1726 /// visitJumpTable - Emit JumpTable node in the current MBB
1727 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1728 // Emit the code for the jump table
1729 assert(JT.Reg != -1U && "Should lower JT Header first!");
1730 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1731 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1733 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1734 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1735 MVT::Other, Index.getValue(1),
1737 DAG.setRoot(BrJumpTable);
1740 /// visitJumpTableHeader - This function emits necessary code to produce index
1741 /// in the JumpTable from switch case.
1742 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1743 JumpTableHeader &JTH,
1744 MachineBasicBlock *SwitchBB) {
1745 SDLoc dl = getCurSDLoc();
1747 // Subtract the lowest switch case value from the value being switched on and
1748 // conditional branch to default mbb if the result is greater than the
1749 // difference between smallest and largest cases.
1750 SDValue SwitchOp = getValue(JTH.SValue);
1751 EVT VT = SwitchOp.getValueType();
1752 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1753 DAG.getConstant(JTH.First, dl, VT));
1755 // The SDNode we just created, which holds the value being switched on minus
1756 // the smallest case value, needs to be copied to a virtual register so it
1757 // can be used as an index into the jump table in a subsequent basic block.
1758 // This value may be smaller or larger than the target's pointer type, and
1759 // therefore require extension or truncating.
1760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1761 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1763 unsigned JumpTableReg =
1764 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1765 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1766 JumpTableReg, SwitchOp);
1767 JT.Reg = JumpTableReg;
1769 // Emit the range check for the jump table, and branch to the default block
1770 // for the switch statement if the value being switched on exceeds the largest
1771 // case in the switch.
1772 SDValue CMP = DAG.getSetCC(
1773 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1774 Sub.getValueType()),
1775 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1777 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1778 MVT::Other, CopyTo, CMP,
1779 DAG.getBasicBlock(JT.Default));
1781 // Avoid emitting unnecessary branches to the next block.
1782 if (JT.MBB != NextBlock(SwitchBB))
1783 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1784 DAG.getBasicBlock(JT.MBB));
1786 DAG.setRoot(BrCond);
1789 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1790 /// tail spliced into a stack protector check success bb.
1792 /// For a high level explanation of how this fits into the stack protector
1793 /// generation see the comment on the declaration of class
1794 /// StackProtectorDescriptor.
1795 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1796 MachineBasicBlock *ParentBB) {
1798 // First create the loads to the guard/stack slot for the comparison.
1799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1800 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1802 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1803 int FI = MFI->getStackProtectorIndex();
1805 const Value *IRGuard = SPD.getGuard();
1806 SDValue GuardPtr = getValue(IRGuard);
1807 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1809 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1812 SDLoc dl = getCurSDLoc();
1814 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1815 // guard value from the virtual register holding the value. Otherwise, emit a
1816 // volatile load to retrieve the stack guard value.
1817 unsigned GuardReg = SPD.getGuardReg();
1819 if (GuardReg && TLI.useLoadStackGuardNode())
1820 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1823 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1824 GuardPtr, MachinePointerInfo(IRGuard, 0),
1825 true, false, false, Align);
1827 SDValue StackSlot = DAG.getLoad(
1828 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1829 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1830 false, false, Align);
1832 // Perform the comparison via a subtract/getsetcc.
1833 EVT VT = Guard.getValueType();
1834 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1836 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1838 Sub.getValueType()),
1839 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1841 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1842 // branch to failure MBB.
1843 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1844 MVT::Other, StackSlot.getOperand(0),
1845 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1846 // Otherwise branch to success MBB.
1847 SDValue Br = DAG.getNode(ISD::BR, dl,
1849 DAG.getBasicBlock(SPD.getSuccessMBB()));
1854 /// Codegen the failure basic block for a stack protector check.
1856 /// A failure stack protector machine basic block consists simply of a call to
1857 /// __stack_chk_fail().
1859 /// For a high level explanation of how this fits into the stack protector
1860 /// generation see the comment on the declaration of class
1861 /// StackProtectorDescriptor.
1863 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1866 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1867 nullptr, 0, false, getCurSDLoc(), false, false).second;
1871 /// visitBitTestHeader - This function emits necessary code to produce value
1872 /// suitable for "bit tests"
1873 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1874 MachineBasicBlock *SwitchBB) {
1875 SDLoc dl = getCurSDLoc();
1877 // Subtract the minimum value
1878 SDValue SwitchOp = getValue(B.SValue);
1879 EVT VT = SwitchOp.getValueType();
1880 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1881 DAG.getConstant(B.First, dl, VT));
1884 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1885 SDValue RangeCmp = DAG.getSetCC(
1886 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1887 Sub.getValueType()),
1888 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1890 // Determine the type of the test operands.
1891 bool UsePtrType = false;
1892 if (!TLI.isTypeLegal(VT))
1895 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1896 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1897 // Switch table case range are encoded into series of masks.
1898 // Just use pointer type, it's guaranteed to fit.
1904 VT = TLI.getPointerTy(DAG.getDataLayout());
1905 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1908 B.RegVT = VT.getSimpleVT();
1909 B.Reg = FuncInfo.CreateReg(B.RegVT);
1910 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1912 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1914 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
1915 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1917 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1918 MVT::Other, CopyTo, RangeCmp,
1919 DAG.getBasicBlock(B.Default));
1921 // Avoid emitting unnecessary branches to the next block.
1922 if (MBB != NextBlock(SwitchBB))
1923 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1924 DAG.getBasicBlock(MBB));
1926 DAG.setRoot(BrRange);
1929 /// visitBitTestCase - this function produces one "bit test"
1930 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1931 MachineBasicBlock* NextMBB,
1932 uint32_t BranchWeightToNext,
1935 MachineBasicBlock *SwitchBB) {
1936 SDLoc dl = getCurSDLoc();
1938 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1940 unsigned PopCount = countPopulation(B.Mask);
1941 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1942 if (PopCount == 1) {
1943 // Testing for a single bit; just compare the shift count with what it
1944 // would need to be to shift a 1 bit in that position.
1946 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1947 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1949 } else if (PopCount == BB.Range) {
1950 // There is only one zero bit in the range, test for it directly.
1952 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1953 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1956 // Make desired shift
1957 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1958 DAG.getConstant(1, dl, VT), ShiftOp);
1960 // Emit bit tests and jumps
1961 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1962 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1964 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1965 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1968 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1969 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1970 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1971 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1973 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1974 MVT::Other, getControlRoot(),
1975 Cmp, DAG.getBasicBlock(B.TargetBB));
1977 // Avoid emitting unnecessary branches to the next block.
1978 if (NextMBB != NextBlock(SwitchBB))
1979 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1980 DAG.getBasicBlock(NextMBB));
1985 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1986 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1988 // Retrieve successors. Look through artificial IR level blocks like catchpads
1989 // and catchendpads for successors.
1990 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1991 const BasicBlock *EHPadBB = I.getSuccessor(1);
1992 bool IsLandingPad = EHPadBB->isLandingPad();
1994 const Value *Callee(I.getCalledValue());
1995 const Function *Fn = dyn_cast<Function>(Callee);
1996 if (isa<InlineAsm>(Callee))
1998 else if (Fn && Fn->isIntrinsic()) {
1999 switch (Fn->getIntrinsicID()) {
2001 llvm_unreachable("Cannot invoke this intrinsic");
2002 case Intrinsic::donothing:
2003 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2005 case Intrinsic::experimental_patchpoint_void:
2006 case Intrinsic::experimental_patchpoint_i64:
2007 visitPatchpoint(&I, EHPadBB);
2009 case Intrinsic::experimental_gc_statepoint:
2010 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2014 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2016 // If the value of the invoke is used outside of its defining block, make it
2017 // available as a virtual register.
2018 // We already took care of the exported value for the statepoint instruction
2019 // during call to the LowerStatepoint.
2020 if (!isStatepoint(I)) {
2021 CopyToExportRegsIfNeeded(&I);
2024 // Stop when we hit a pad that generates real code or we unwind to caller.
2025 // Catchpads are conditional branches that add real MBB destinations and
2026 // continue the loop. EH "end" pads are not real BBs and simply continue.
2027 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2029 const Instruction *Pad = EHPadBB->getFirstNonPHI();
2030 if (isa<CleanupPadInst>(Pad) || isa<LandingPadInst>(Pad)) {
2031 assert(FuncInfo.MBBMap[EHPadBB]);
2032 // Stop on cleanup pads and landingpads.
2033 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
2035 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
2036 // Add the catchpad handler to the possible destinations.
2037 UnwindDests.push_back(FuncInfo.MBBMap[CPI->getNormalDest()]);
2038 EHPadBB = CPI->getUnwindDest();
2039 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
2040 EHPadBB = CEPI->getUnwindDest();
2041 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
2042 EHPadBB = CEPI->getUnwindDest();
2046 // Update successor info
2047 // FIXME: The weights for catchpads will be wrong.
2048 addSuccessorWithWeight(InvokeMBB, Return);
2049 for (auto *UnwindDest : UnwindDests) {
2050 UnwindDest->setIsEHPad();
2052 UnwindDest->setIsEHFuncletEntry();
2053 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2056 // Drop into normal successor.
2057 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2058 MVT::Other, getControlRoot(),
2059 DAG.getBasicBlock(Return)));
2062 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2063 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2066 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2067 assert(FuncInfo.MBB->isEHPad() &&
2068 "Call to landingpad not in landing pad!");
2070 MachineBasicBlock *MBB = FuncInfo.MBB;
2071 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2072 AddLandingPadInfo(LP, MMI, MBB);
2074 // If there aren't registers to copy the values into (e.g., during SjLj
2075 // exceptions), then don't bother to create these DAG nodes.
2076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2077 if (TLI.getExceptionPointerRegister() == 0 &&
2078 TLI.getExceptionSelectorRegister() == 0)
2081 SmallVector<EVT, 2> ValueVTs;
2082 SDLoc dl = getCurSDLoc();
2083 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2084 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2086 // Get the two live-in registers as SDValues. The physregs have already been
2087 // copied into virtual registers.
2089 if (FuncInfo.ExceptionPointerVirtReg) {
2090 Ops[0] = DAG.getZExtOrTrunc(
2091 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2092 FuncInfo.ExceptionPointerVirtReg,
2093 TLI.getPointerTy(DAG.getDataLayout())),
2096 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2098 Ops[1] = DAG.getZExtOrTrunc(
2099 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2100 FuncInfo.ExceptionSelectorVirtReg,
2101 TLI.getPointerTy(DAG.getDataLayout())),
2105 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2106 DAG.getVTList(ValueVTs), Ops);
2110 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2112 for (const CaseCluster &CC : Clusters)
2113 assert(CC.Low == CC.High && "Input clusters must be single-case");
2116 std::sort(Clusters.begin(), Clusters.end(),
2117 [](const CaseCluster &a, const CaseCluster &b) {
2118 return a.Low->getValue().slt(b.Low->getValue());
2121 // Merge adjacent clusters with the same destination.
2122 const unsigned N = Clusters.size();
2123 unsigned DstIndex = 0;
2124 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2125 CaseCluster &CC = Clusters[SrcIndex];
2126 const ConstantInt *CaseVal = CC.Low;
2127 MachineBasicBlock *Succ = CC.MBB;
2129 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2130 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2131 // If this case has the same successor and is a neighbour, merge it into
2132 // the previous cluster.
2133 Clusters[DstIndex - 1].High = CaseVal;
2134 Clusters[DstIndex - 1].Weight += CC.Weight;
2135 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2137 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2138 sizeof(Clusters[SrcIndex]));
2141 Clusters.resize(DstIndex);
2144 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2145 MachineBasicBlock *Last) {
2147 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2148 if (JTCases[i].first.HeaderBB == First)
2149 JTCases[i].first.HeaderBB = Last;
2151 // Update BitTestCases.
2152 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2153 if (BitTestCases[i].Parent == First)
2154 BitTestCases[i].Parent = Last;
2157 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2158 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2160 // Update machine-CFG edges with unique successors.
2161 SmallSet<BasicBlock*, 32> Done;
2162 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2163 BasicBlock *BB = I.getSuccessor(i);
2164 bool Inserted = Done.insert(BB).second;
2168 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2169 addSuccessorWithWeight(IndirectBrMBB, Succ);
2172 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2173 MVT::Other, getControlRoot(),
2174 getValue(I.getAddress())));
2177 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2178 if (DAG.getTarget().Options.TrapUnreachable)
2179 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2182 void SelectionDAGBuilder::visitFSub(const User &I) {
2183 // -0.0 - X --> fneg
2184 Type *Ty = I.getType();
2185 if (isa<Constant>(I.getOperand(0)) &&
2186 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2187 SDValue Op2 = getValue(I.getOperand(1));
2188 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2189 Op2.getValueType(), Op2));
2193 visitBinary(I, ISD::FSUB);
2196 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2197 SDValue Op1 = getValue(I.getOperand(0));
2198 SDValue Op2 = getValue(I.getOperand(1));
2205 if (const OverflowingBinaryOperator *OFBinOp =
2206 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2207 nuw = OFBinOp->hasNoUnsignedWrap();
2208 nsw = OFBinOp->hasNoSignedWrap();
2210 if (const PossiblyExactOperator *ExactOp =
2211 dyn_cast<const PossiblyExactOperator>(&I))
2212 exact = ExactOp->isExact();
2213 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2214 FMF = FPOp->getFastMathFlags();
2217 Flags.setExact(exact);
2218 Flags.setNoSignedWrap(nsw);
2219 Flags.setNoUnsignedWrap(nuw);
2220 if (EnableFMFInDAG) {
2221 Flags.setAllowReciprocal(FMF.allowReciprocal());
2222 Flags.setNoInfs(FMF.noInfs());
2223 Flags.setNoNaNs(FMF.noNaNs());
2224 Flags.setNoSignedZeros(FMF.noSignedZeros());
2225 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2227 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2229 setValue(&I, BinNodeValue);
2232 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2233 SDValue Op1 = getValue(I.getOperand(0));
2234 SDValue Op2 = getValue(I.getOperand(1));
2236 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2237 Op2.getValueType(), DAG.getDataLayout());
2239 // Coerce the shift amount to the right type if we can.
2240 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2241 unsigned ShiftSize = ShiftTy.getSizeInBits();
2242 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2243 SDLoc DL = getCurSDLoc();
2245 // If the operand is smaller than the shift count type, promote it.
2246 if (ShiftSize > Op2Size)
2247 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2249 // If the operand is larger than the shift count type but the shift
2250 // count type has enough bits to represent any shift value, truncate
2251 // it now. This is a common case and it exposes the truncate to
2252 // optimization early.
2253 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2254 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2255 // Otherwise we'll need to temporarily settle for some other convenient
2256 // type. Type legalization will make adjustments once the shiftee is split.
2258 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2265 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2267 if (const OverflowingBinaryOperator *OFBinOp =
2268 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2269 nuw = OFBinOp->hasNoUnsignedWrap();
2270 nsw = OFBinOp->hasNoSignedWrap();
2272 if (const PossiblyExactOperator *ExactOp =
2273 dyn_cast<const PossiblyExactOperator>(&I))
2274 exact = ExactOp->isExact();
2277 Flags.setExact(exact);
2278 Flags.setNoSignedWrap(nsw);
2279 Flags.setNoUnsignedWrap(nuw);
2280 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2285 void SelectionDAGBuilder::visitSDiv(const User &I) {
2286 SDValue Op1 = getValue(I.getOperand(0));
2287 SDValue Op2 = getValue(I.getOperand(1));
2290 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2291 cast<PossiblyExactOperator>(&I)->isExact());
2292 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2296 void SelectionDAGBuilder::visitICmp(const User &I) {
2297 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2298 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2299 predicate = IC->getPredicate();
2300 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2301 predicate = ICmpInst::Predicate(IC->getPredicate());
2302 SDValue Op1 = getValue(I.getOperand(0));
2303 SDValue Op2 = getValue(I.getOperand(1));
2304 ISD::CondCode Opcode = getICmpCondCode(predicate);
2306 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2308 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2311 void SelectionDAGBuilder::visitFCmp(const User &I) {
2312 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2313 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2314 predicate = FC->getPredicate();
2315 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2316 predicate = FCmpInst::Predicate(FC->getPredicate());
2317 SDValue Op1 = getValue(I.getOperand(0));
2318 SDValue Op2 = getValue(I.getOperand(1));
2319 ISD::CondCode Condition = getFCmpCondCode(predicate);
2320 if (TM.Options.NoNaNsFPMath)
2321 Condition = getFCmpCodeWithoutNaN(Condition);
2322 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2324 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2327 void SelectionDAGBuilder::visitSelect(const User &I) {
2328 SmallVector<EVT, 4> ValueVTs;
2329 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2331 unsigned NumValues = ValueVTs.size();
2332 if (NumValues == 0) return;
2334 SmallVector<SDValue, 4> Values(NumValues);
2335 SDValue Cond = getValue(I.getOperand(0));
2336 SDValue LHSVal = getValue(I.getOperand(1));
2337 SDValue RHSVal = getValue(I.getOperand(2));
2338 auto BaseOps = {Cond};
2339 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2340 ISD::VSELECT : ISD::SELECT;
2342 // Min/max matching is only viable if all output VTs are the same.
2343 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2344 EVT VT = ValueVTs[0];
2345 LLVMContext &Ctx = *DAG.getContext();
2346 auto &TLI = DAG.getTargetLoweringInfo();
2347 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2348 VT = TLI.getTypeToTransformTo(Ctx, VT);
2351 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2352 ISD::NodeType Opc = ISD::DELETED_NODE;
2353 switch (SPR.Flavor) {
2354 case SPF_UMAX: Opc = ISD::UMAX; break;
2355 case SPF_UMIN: Opc = ISD::UMIN; break;
2356 case SPF_SMAX: Opc = ISD::SMAX; break;
2357 case SPF_SMIN: Opc = ISD::SMIN; break;
2359 switch (SPR.NaNBehavior) {
2360 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2361 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2362 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2363 case SPNB_RETURNS_ANY:
2364 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2370 switch (SPR.NaNBehavior) {
2371 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2372 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2373 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2374 case SPNB_RETURNS_ANY:
2375 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2383 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2384 // If the underlying comparison instruction is used by any other instruction,
2385 // the consumed instructions won't be destroyed, so it is not profitable
2386 // to convert to a min/max.
2387 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2389 LHSVal = getValue(LHS);
2390 RHSVal = getValue(RHS);
2395 for (unsigned i = 0; i != NumValues; ++i) {
2396 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2397 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2398 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2399 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2400 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2404 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2405 DAG.getVTList(ValueVTs), Values));
2408 void SelectionDAGBuilder::visitTrunc(const User &I) {
2409 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2410 SDValue N = getValue(I.getOperand(0));
2411 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2413 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2416 void SelectionDAGBuilder::visitZExt(const User &I) {
2417 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2418 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2419 SDValue N = getValue(I.getOperand(0));
2420 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2422 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2425 void SelectionDAGBuilder::visitSExt(const User &I) {
2426 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2427 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2428 SDValue N = getValue(I.getOperand(0));
2429 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2431 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2434 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2435 // FPTrunc is never a no-op cast, no need to check
2436 SDValue N = getValue(I.getOperand(0));
2437 SDLoc dl = getCurSDLoc();
2438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2439 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2440 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2441 DAG.getTargetConstant(
2442 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2445 void SelectionDAGBuilder::visitFPExt(const User &I) {
2446 // FPExt is never a no-op cast, no need to check
2447 SDValue N = getValue(I.getOperand(0));
2448 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2450 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2453 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2454 // FPToUI is never a no-op cast, no need to check
2455 SDValue N = getValue(I.getOperand(0));
2456 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2458 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2461 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2462 // FPToSI is never a no-op cast, no need to check
2463 SDValue N = getValue(I.getOperand(0));
2464 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2466 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2469 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2470 // UIToFP is never a no-op cast, no need to check
2471 SDValue N = getValue(I.getOperand(0));
2472 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2474 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2477 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2478 // SIToFP is never a no-op cast, no need to check
2479 SDValue N = getValue(I.getOperand(0));
2480 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2482 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2485 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2486 // What to do depends on the size of the integer and the size of the pointer.
2487 // We can either truncate, zero extend, or no-op, accordingly.
2488 SDValue N = getValue(I.getOperand(0));
2489 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2491 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2494 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2495 // What to do depends on the size of the integer and the size of the pointer.
2496 // We can either truncate, zero extend, or no-op, accordingly.
2497 SDValue N = getValue(I.getOperand(0));
2498 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2500 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2503 void SelectionDAGBuilder::visitBitCast(const User &I) {
2504 SDValue N = getValue(I.getOperand(0));
2505 SDLoc dl = getCurSDLoc();
2506 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2509 // BitCast assures us that source and destination are the same size so this is
2510 // either a BITCAST or a no-op.
2511 if (DestVT != N.getValueType())
2512 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2513 DestVT, N)); // convert types.
2514 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2515 // might fold any kind of constant expression to an integer constant and that
2516 // is not what we are looking for. Only regcognize a bitcast of a genuine
2517 // constant integer as an opaque constant.
2518 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2519 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2522 setValue(&I, N); // noop cast.
2525 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2526 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2527 const Value *SV = I.getOperand(0);
2528 SDValue N = getValue(SV);
2529 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2531 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2532 unsigned DestAS = I.getType()->getPointerAddressSpace();
2534 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2535 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2540 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2542 SDValue InVec = getValue(I.getOperand(0));
2543 SDValue InVal = getValue(I.getOperand(1));
2544 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2545 TLI.getVectorIdxTy(DAG.getDataLayout()));
2546 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2547 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2548 InVec, InVal, InIdx));
2551 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2552 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2553 SDValue InVec = getValue(I.getOperand(0));
2554 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2555 TLI.getVectorIdxTy(DAG.getDataLayout()));
2556 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2557 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2561 // Utility for visitShuffleVector - Return true if every element in Mask,
2562 // beginning from position Pos and ending in Pos+Size, falls within the
2563 // specified sequential range [L, L+Pos). or is undef.
2564 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2565 unsigned Pos, unsigned Size, int Low) {
2566 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2567 if (Mask[i] >= 0 && Mask[i] != Low)
2572 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2573 SDValue Src1 = getValue(I.getOperand(0));
2574 SDValue Src2 = getValue(I.getOperand(1));
2576 SmallVector<int, 8> Mask;
2577 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2578 unsigned MaskNumElts = Mask.size();
2580 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2581 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2582 EVT SrcVT = Src1.getValueType();
2583 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2585 if (SrcNumElts == MaskNumElts) {
2586 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2591 // Normalize the shuffle vector since mask and vector length don't match.
2592 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2593 // Mask is longer than the source vectors and is a multiple of the source
2594 // vectors. We can use concatenate vector to make the mask and vectors
2596 if (SrcNumElts*2 == MaskNumElts) {
2597 // First check for Src1 in low and Src2 in high
2598 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2599 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2600 // The shuffle is concatenating two vectors together.
2601 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2605 // Then check for Src2 in low and Src1 in high
2606 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2607 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2608 // The shuffle is concatenating two vectors together.
2609 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2615 // Pad both vectors with undefs to make them the same length as the mask.
2616 unsigned NumConcat = MaskNumElts / SrcNumElts;
2617 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2618 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2619 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2621 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2622 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2626 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2627 getCurSDLoc(), VT, MOps1);
2628 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2629 getCurSDLoc(), VT, MOps2);
2631 // Readjust mask for new input vector length.
2632 SmallVector<int, 8> MappedOps;
2633 for (unsigned i = 0; i != MaskNumElts; ++i) {
2635 if (Idx >= (int)SrcNumElts)
2636 Idx -= SrcNumElts - MaskNumElts;
2637 MappedOps.push_back(Idx);
2640 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2645 if (SrcNumElts > MaskNumElts) {
2646 // Analyze the access pattern of the vector to see if we can extract
2647 // two subvectors and do the shuffle. The analysis is done by calculating
2648 // the range of elements the mask access on both vectors.
2649 int MinRange[2] = { static_cast<int>(SrcNumElts),
2650 static_cast<int>(SrcNumElts)};
2651 int MaxRange[2] = {-1, -1};
2653 for (unsigned i = 0; i != MaskNumElts; ++i) {
2659 if (Idx >= (int)SrcNumElts) {
2663 if (Idx > MaxRange[Input])
2664 MaxRange[Input] = Idx;
2665 if (Idx < MinRange[Input])
2666 MinRange[Input] = Idx;
2669 // Check if the access is smaller than the vector size and can we find
2670 // a reasonable extract index.
2671 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2673 int StartIdx[2]; // StartIdx to extract from
2674 for (unsigned Input = 0; Input < 2; ++Input) {
2675 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2676 RangeUse[Input] = 0; // Unused
2677 StartIdx[Input] = 0;
2681 // Find a good start index that is a multiple of the mask length. Then
2682 // see if the rest of the elements are in range.
2683 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2684 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2685 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2686 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2689 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2690 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2693 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2694 // Extract appropriate subvector and generate a vector shuffle
2695 for (unsigned Input = 0; Input < 2; ++Input) {
2696 SDValue &Src = Input == 0 ? Src1 : Src2;
2697 if (RangeUse[Input] == 0)
2698 Src = DAG.getUNDEF(VT);
2700 SDLoc dl = getCurSDLoc();
2702 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2703 DAG.getConstant(StartIdx[Input], dl,
2704 TLI.getVectorIdxTy(DAG.getDataLayout())));
2708 // Calculate new mask.
2709 SmallVector<int, 8> MappedOps;
2710 for (unsigned i = 0; i != MaskNumElts; ++i) {
2713 if (Idx < (int)SrcNumElts)
2716 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2718 MappedOps.push_back(Idx);
2721 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2727 // We can't use either concat vectors or extract subvectors so fall back to
2728 // replacing the shuffle with extract and build vector.
2729 // to insert and build vector.
2730 EVT EltVT = VT.getVectorElementType();
2731 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2732 SDLoc dl = getCurSDLoc();
2733 SmallVector<SDValue,8> Ops;
2734 for (unsigned i = 0; i != MaskNumElts; ++i) {
2739 Res = DAG.getUNDEF(EltVT);
2741 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2742 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2744 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2745 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2751 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2754 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2755 const Value *Op0 = I.getOperand(0);
2756 const Value *Op1 = I.getOperand(1);
2757 Type *AggTy = I.getType();
2758 Type *ValTy = Op1->getType();
2759 bool IntoUndef = isa<UndefValue>(Op0);
2760 bool FromUndef = isa<UndefValue>(Op1);
2762 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2764 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2765 SmallVector<EVT, 4> AggValueVTs;
2766 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2767 SmallVector<EVT, 4> ValValueVTs;
2768 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2770 unsigned NumAggValues = AggValueVTs.size();
2771 unsigned NumValValues = ValValueVTs.size();
2772 SmallVector<SDValue, 4> Values(NumAggValues);
2774 // Ignore an insertvalue that produces an empty object
2775 if (!NumAggValues) {
2776 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2780 SDValue Agg = getValue(Op0);
2782 // Copy the beginning value(s) from the original aggregate.
2783 for (; i != LinearIndex; ++i)
2784 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2785 SDValue(Agg.getNode(), Agg.getResNo() + i);
2786 // Copy values from the inserted value(s).
2788 SDValue Val = getValue(Op1);
2789 for (; i != LinearIndex + NumValValues; ++i)
2790 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2791 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2793 // Copy remaining value(s) from the original aggregate.
2794 for (; i != NumAggValues; ++i)
2795 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2796 SDValue(Agg.getNode(), Agg.getResNo() + i);
2798 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2799 DAG.getVTList(AggValueVTs), Values));
2802 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2803 const Value *Op0 = I.getOperand(0);
2804 Type *AggTy = Op0->getType();
2805 Type *ValTy = I.getType();
2806 bool OutOfUndef = isa<UndefValue>(Op0);
2808 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2810 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2811 SmallVector<EVT, 4> ValValueVTs;
2812 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2814 unsigned NumValValues = ValValueVTs.size();
2816 // Ignore a extractvalue that produces an empty object
2817 if (!NumValValues) {
2818 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2822 SmallVector<SDValue, 4> Values(NumValValues);
2824 SDValue Agg = getValue(Op0);
2825 // Copy out the selected value(s).
2826 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2827 Values[i - LinearIndex] =
2829 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2830 SDValue(Agg.getNode(), Agg.getResNo() + i);
2832 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2833 DAG.getVTList(ValValueVTs), Values));
2836 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2837 Value *Op0 = I.getOperand(0);
2838 // Note that the pointer operand may be a vector of pointers. Take the scalar
2839 // element which holds a pointer.
2840 Type *Ty = Op0->getType()->getScalarType();
2841 unsigned AS = Ty->getPointerAddressSpace();
2842 SDValue N = getValue(Op0);
2843 SDLoc dl = getCurSDLoc();
2845 // Normalize Vector GEP - all scalar operands should be converted to the
2847 unsigned VectorWidth = I.getType()->isVectorTy() ?
2848 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2850 if (VectorWidth && !N.getValueType().isVector()) {
2851 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2852 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2853 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2855 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2857 const Value *Idx = *OI;
2858 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2859 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2862 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2863 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2864 DAG.getConstant(Offset, dl, N.getValueType()));
2867 Ty = StTy->getElementType(Field);
2869 Ty = cast<SequentialType>(Ty)->getElementType();
2871 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2872 unsigned PtrSize = PtrTy.getSizeInBits();
2873 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2875 // If this is a scalar constant or a splat vector of constants,
2876 // handle it quickly.
2877 const auto *CI = dyn_cast<ConstantInt>(Idx);
2878 if (!CI && isa<ConstantDataVector>(Idx) &&
2879 cast<ConstantDataVector>(Idx)->getSplatValue())
2880 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2885 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2886 SDValue OffsVal = VectorWidth ?
2887 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2888 DAG.getConstant(Offs, dl, PtrTy);
2889 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2893 // N = N + Idx * ElementSize;
2894 SDValue IdxN = getValue(Idx);
2896 if (!IdxN.getValueType().isVector() && VectorWidth) {
2897 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2898 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2899 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2901 // If the index is smaller or larger than intptr_t, truncate or extend
2903 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2905 // If this is a multiply by a power of two, turn it into a shl
2906 // immediately. This is a very common case.
2907 if (ElementSize != 1) {
2908 if (ElementSize.isPowerOf2()) {
2909 unsigned Amt = ElementSize.logBase2();
2910 IdxN = DAG.getNode(ISD::SHL, dl,
2911 N.getValueType(), IdxN,
2912 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2914 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2915 IdxN = DAG.getNode(ISD::MUL, dl,
2916 N.getValueType(), IdxN, Scale);
2920 N = DAG.getNode(ISD::ADD, dl,
2921 N.getValueType(), N, IdxN);
2928 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2929 // If this is a fixed sized alloca in the entry block of the function,
2930 // allocate it statically on the stack.
2931 if (FuncInfo.StaticAllocaMap.count(&I))
2932 return; // getValue will auto-populate this.
2934 SDLoc dl = getCurSDLoc();
2935 Type *Ty = I.getAllocatedType();
2936 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2937 auto &DL = DAG.getDataLayout();
2938 uint64_t TySize = DL.getTypeAllocSize(Ty);
2940 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2942 SDValue AllocSize = getValue(I.getArraySize());
2944 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2945 if (AllocSize.getValueType() != IntPtr)
2946 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2948 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2950 DAG.getConstant(TySize, dl, IntPtr));
2952 // Handle alignment. If the requested alignment is less than or equal to
2953 // the stack alignment, ignore it. If the size is greater than or equal to
2954 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2955 unsigned StackAlign =
2956 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2957 if (Align <= StackAlign)
2960 // Round the size of the allocation up to the stack alignment size
2961 // by add SA-1 to the size.
2962 AllocSize = DAG.getNode(ISD::ADD, dl,
2963 AllocSize.getValueType(), AllocSize,
2964 DAG.getIntPtrConstant(StackAlign - 1, dl));
2966 // Mask out the low bits for alignment purposes.
2967 AllocSize = DAG.getNode(ISD::AND, dl,
2968 AllocSize.getValueType(), AllocSize,
2969 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2972 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2973 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2974 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2976 DAG.setRoot(DSA.getValue(1));
2978 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2981 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2983 return visitAtomicLoad(I);
2985 const Value *SV = I.getOperand(0);
2986 SDValue Ptr = getValue(SV);
2988 Type *Ty = I.getType();
2990 bool isVolatile = I.isVolatile();
2991 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2993 // The IR notion of invariant_load only guarantees that all *non-faulting*
2994 // invariant loads result in the same value. The MI notion of invariant load
2995 // guarantees that the load can be legally moved to any location within its
2996 // containing function. The MI notion of invariant_load is stronger than the
2997 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2998 // with a guarantee that the location being loaded from is dereferenceable
2999 // throughout the function's lifetime.
3001 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3002 isDereferenceablePointer(SV, DAG.getDataLayout());
3003 unsigned Alignment = I.getAlignment();
3006 I.getAAMetadata(AAInfo);
3007 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3009 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3010 SmallVector<EVT, 4> ValueVTs;
3011 SmallVector<uint64_t, 4> Offsets;
3012 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3013 unsigned NumValues = ValueVTs.size();
3018 bool ConstantMemory = false;
3019 if (isVolatile || NumValues > MaxParallelChains)
3020 // Serialize volatile loads with other side effects.
3022 else if (AA->pointsToConstantMemory(MemoryLocation(
3023 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3024 // Do not serialize (non-volatile) loads of constant memory with anything.
3025 Root = DAG.getEntryNode();
3026 ConstantMemory = true;
3028 // Do not serialize non-volatile loads against each other.
3029 Root = DAG.getRoot();
3032 SDLoc dl = getCurSDLoc();
3035 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3037 SmallVector<SDValue, 4> Values(NumValues);
3038 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3039 EVT PtrVT = Ptr.getValueType();
3040 unsigned ChainI = 0;
3041 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3042 // Serializing loads here may result in excessive register pressure, and
3043 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3044 // could recover a bit by hoisting nodes upward in the chain by recognizing
3045 // they are side-effect free or do not alias. The optimizer should really
3046 // avoid this case by converting large object/array copies to llvm.memcpy
3047 // (MaxParallelChains should always remain as failsafe).
3048 if (ChainI == MaxParallelChains) {
3049 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3050 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3051 makeArrayRef(Chains.data(), ChainI));
3055 SDValue A = DAG.getNode(ISD::ADD, dl,
3057 DAG.getConstant(Offsets[i], dl, PtrVT));
3058 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3059 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3060 isNonTemporal, isInvariant, Alignment, AAInfo,
3064 Chains[ChainI] = L.getValue(1);
3067 if (!ConstantMemory) {
3068 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3069 makeArrayRef(Chains.data(), ChainI));
3073 PendingLoads.push_back(Chain);
3076 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3077 DAG.getVTList(ValueVTs), Values));
3080 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3082 return visitAtomicStore(I);
3084 const Value *SrcV = I.getOperand(0);
3085 const Value *PtrV = I.getOperand(1);
3087 SmallVector<EVT, 4> ValueVTs;
3088 SmallVector<uint64_t, 4> Offsets;
3089 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3090 SrcV->getType(), ValueVTs, &Offsets);
3091 unsigned NumValues = ValueVTs.size();
3095 // Get the lowered operands. Note that we do this after
3096 // checking if NumResults is zero, because with zero results
3097 // the operands won't have values in the map.
3098 SDValue Src = getValue(SrcV);
3099 SDValue Ptr = getValue(PtrV);
3101 SDValue Root = getRoot();
3102 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3103 EVT PtrVT = Ptr.getValueType();
3104 bool isVolatile = I.isVolatile();
3105 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3106 unsigned Alignment = I.getAlignment();
3107 SDLoc dl = getCurSDLoc();
3110 I.getAAMetadata(AAInfo);
3112 unsigned ChainI = 0;
3113 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3114 // See visitLoad comments.
3115 if (ChainI == MaxParallelChains) {
3116 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3117 makeArrayRef(Chains.data(), ChainI));
3121 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3122 DAG.getConstant(Offsets[i], dl, PtrVT));
3123 SDValue St = DAG.getStore(Root, dl,
3124 SDValue(Src.getNode(), Src.getResNo() + i),
3125 Add, MachinePointerInfo(PtrV, Offsets[i]),
3126 isVolatile, isNonTemporal, Alignment, AAInfo);
3127 Chains[ChainI] = St;
3130 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3131 makeArrayRef(Chains.data(), ChainI));
3132 DAG.setRoot(StoreNode);
3135 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3136 SDLoc sdl = getCurSDLoc();
3138 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3139 Value *PtrOperand = I.getArgOperand(1);
3140 SDValue Ptr = getValue(PtrOperand);
3141 SDValue Src0 = getValue(I.getArgOperand(0));
3142 SDValue Mask = getValue(I.getArgOperand(3));
3143 EVT VT = Src0.getValueType();
3144 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3146 Alignment = DAG.getEVTAlignment(VT);
3149 I.getAAMetadata(AAInfo);
3151 MachineMemOperand *MMO =
3152 DAG.getMachineFunction().
3153 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3154 MachineMemOperand::MOStore, VT.getStoreSize(),
3156 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3158 DAG.setRoot(StoreNode);
3159 setValue(&I, StoreNode);
3162 // Get a uniform base for the Gather/Scatter intrinsic.
3163 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3164 // We try to represent it as a base pointer + vector of indices.
3165 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3166 // The first operand of the GEP may be a single pointer or a vector of pointers
3168 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3170 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3171 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3173 // When the first GEP operand is a single pointer - it is the uniform base we
3174 // are looking for. If first operand of the GEP is a splat vector - we
3175 // extract the spalt value and use it as a uniform base.
3176 // In all other cases the function returns 'false'.
3178 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3179 SelectionDAGBuilder* SDB) {
3181 SelectionDAG& DAG = SDB->DAG;
3182 LLVMContext &Context = *DAG.getContext();
3184 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3185 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3186 if (!GEP || GEP->getNumOperands() > 2)
3189 Value *GEPPtr = GEP->getPointerOperand();
3190 if (!GEPPtr->getType()->isVectorTy())
3192 else if (!(Ptr = getSplatValue(GEPPtr)))
3195 Value *IndexVal = GEP->getOperand(1);
3197 // The operands of the GEP may be defined in another basic block.
3198 // In this case we'll not find nodes for the operands.
3199 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3202 Base = SDB->getValue(Ptr);
3203 Index = SDB->getValue(IndexVal);
3205 // Suppress sign extension.
3206 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3207 if (SDB->findValue(Sext->getOperand(0))) {
3208 IndexVal = Sext->getOperand(0);
3209 Index = SDB->getValue(IndexVal);
3212 if (!Index.getValueType().isVector()) {
3213 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3214 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3215 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3216 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3221 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3222 SDLoc sdl = getCurSDLoc();
3224 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3225 Value *Ptr = I.getArgOperand(1);
3226 SDValue Src0 = getValue(I.getArgOperand(0));
3227 SDValue Mask = getValue(I.getArgOperand(3));
3228 EVT VT = Src0.getValueType();
3229 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3231 Alignment = DAG.getEVTAlignment(VT);
3232 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3235 I.getAAMetadata(AAInfo);
3239 Value *BasePtr = Ptr;
3240 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3242 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3243 MachineMemOperand *MMO = DAG.getMachineFunction().
3244 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3245 MachineMemOperand::MOStore, VT.getStoreSize(),
3248 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3249 Index = getValue(Ptr);
3251 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3252 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3254 DAG.setRoot(Scatter);
3255 setValue(&I, Scatter);
3258 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3259 SDLoc sdl = getCurSDLoc();
3261 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3262 Value *PtrOperand = I.getArgOperand(0);
3263 SDValue Ptr = getValue(PtrOperand);
3264 SDValue Src0 = getValue(I.getArgOperand(3));
3265 SDValue Mask = getValue(I.getArgOperand(2));
3267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3268 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3269 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3271 Alignment = DAG.getEVTAlignment(VT);
3274 I.getAAMetadata(AAInfo);
3275 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3277 SDValue InChain = DAG.getRoot();
3278 if (AA->pointsToConstantMemory(MemoryLocation(
3279 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3281 // Do not serialize (non-volatile) loads of constant memory with anything.
3282 InChain = DAG.getEntryNode();
3285 MachineMemOperand *MMO =
3286 DAG.getMachineFunction().
3287 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3288 MachineMemOperand::MOLoad, VT.getStoreSize(),
3289 Alignment, AAInfo, Ranges);
3291 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3293 SDValue OutChain = Load.getValue(1);
3294 DAG.setRoot(OutChain);
3298 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3299 SDLoc sdl = getCurSDLoc();
3301 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3302 Value *Ptr = I.getArgOperand(0);
3303 SDValue Src0 = getValue(I.getArgOperand(3));
3304 SDValue Mask = getValue(I.getArgOperand(2));
3306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3307 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3308 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3310 Alignment = DAG.getEVTAlignment(VT);
3313 I.getAAMetadata(AAInfo);
3314 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3316 SDValue Root = DAG.getRoot();
3319 Value *BasePtr = Ptr;
3320 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3321 bool ConstantMemory = false;
3323 AA->pointsToConstantMemory(MemoryLocation(
3324 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3326 // Do not serialize (non-volatile) loads of constant memory with anything.
3327 Root = DAG.getEntryNode();
3328 ConstantMemory = true;
3331 MachineMemOperand *MMO =
3332 DAG.getMachineFunction().
3333 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3334 MachineMemOperand::MOLoad, VT.getStoreSize(),
3335 Alignment, AAInfo, Ranges);
3338 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3339 Index = getValue(Ptr);
3341 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3342 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3345 SDValue OutChain = Gather.getValue(1);
3346 if (!ConstantMemory)
3347 PendingLoads.push_back(OutChain);
3348 setValue(&I, Gather);
3351 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3352 SDLoc dl = getCurSDLoc();
3353 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3354 AtomicOrdering FailureOrder = I.getFailureOrdering();
3355 SynchronizationScope Scope = I.getSynchScope();
3357 SDValue InChain = getRoot();
3359 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3360 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3361 SDValue L = DAG.getAtomicCmpSwap(
3362 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3363 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3364 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3365 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3367 SDValue OutChain = L.getValue(2);
3370 DAG.setRoot(OutChain);
3373 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3374 SDLoc dl = getCurSDLoc();
3376 switch (I.getOperation()) {
3377 default: llvm_unreachable("Unknown atomicrmw operation");
3378 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3379 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3380 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3381 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3382 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3383 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3384 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3385 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3386 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3387 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3388 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3390 AtomicOrdering Order = I.getOrdering();
3391 SynchronizationScope Scope = I.getSynchScope();
3393 SDValue InChain = getRoot();
3396 DAG.getAtomic(NT, dl,
3397 getValue(I.getValOperand()).getSimpleValueType(),
3399 getValue(I.getPointerOperand()),
3400 getValue(I.getValOperand()),
3401 I.getPointerOperand(),
3402 /* Alignment=*/ 0, Order, Scope);
3404 SDValue OutChain = L.getValue(1);
3407 DAG.setRoot(OutChain);
3410 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3411 SDLoc dl = getCurSDLoc();
3412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3415 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3416 TLI.getPointerTy(DAG.getDataLayout()));
3417 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3418 TLI.getPointerTy(DAG.getDataLayout()));
3419 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3422 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3423 SDLoc dl = getCurSDLoc();
3424 AtomicOrdering Order = I.getOrdering();
3425 SynchronizationScope Scope = I.getSynchScope();
3427 SDValue InChain = getRoot();
3429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3430 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3432 if (I.getAlignment() < VT.getSizeInBits() / 8)
3433 report_fatal_error("Cannot generate unaligned atomic load");
3435 MachineMemOperand *MMO =
3436 DAG.getMachineFunction().
3437 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3438 MachineMemOperand::MOVolatile |
3439 MachineMemOperand::MOLoad,
3441 I.getAlignment() ? I.getAlignment() :
3442 DAG.getEVTAlignment(VT));
3444 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3446 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3447 getValue(I.getPointerOperand()), MMO,
3450 SDValue OutChain = L.getValue(1);
3453 DAG.setRoot(OutChain);
3456 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3457 SDLoc dl = getCurSDLoc();
3459 AtomicOrdering Order = I.getOrdering();
3460 SynchronizationScope Scope = I.getSynchScope();
3462 SDValue InChain = getRoot();
3464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3466 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3468 if (I.getAlignment() < VT.getSizeInBits() / 8)
3469 report_fatal_error("Cannot generate unaligned atomic store");
3472 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3474 getValue(I.getPointerOperand()),
3475 getValue(I.getValueOperand()),
3476 I.getPointerOperand(), I.getAlignment(),
3479 DAG.setRoot(OutChain);
3482 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3484 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3485 unsigned Intrinsic) {
3486 bool HasChain = !I.doesNotAccessMemory();
3487 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3489 // Build the operand list.
3490 SmallVector<SDValue, 8> Ops;
3491 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3493 // We don't need to serialize loads against other loads.
3494 Ops.push_back(DAG.getRoot());
3496 Ops.push_back(getRoot());
3500 // Info is set by getTgtMemInstrinsic
3501 TargetLowering::IntrinsicInfo Info;
3502 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3503 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3505 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3506 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3507 Info.opc == ISD::INTRINSIC_W_CHAIN)
3508 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3509 TLI.getPointerTy(DAG.getDataLayout())));
3511 // Add all operands of the call to the operand list.
3512 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3513 SDValue Op = getValue(I.getArgOperand(i));
3517 SmallVector<EVT, 4> ValueVTs;
3518 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3521 ValueVTs.push_back(MVT::Other);
3523 SDVTList VTs = DAG.getVTList(ValueVTs);
3527 if (IsTgtIntrinsic) {
3528 // This is target intrinsic that touches memory
3529 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3530 VTs, Ops, Info.memVT,
3531 MachinePointerInfo(Info.ptrVal, Info.offset),
3532 Info.align, Info.vol,
3533 Info.readMem, Info.writeMem, Info.size);
3534 } else if (!HasChain) {
3535 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3536 } else if (!I.getType()->isVoidTy()) {
3537 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3539 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3543 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3545 PendingLoads.push_back(Chain);
3550 if (!I.getType()->isVoidTy()) {
3551 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3552 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3553 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3556 setValue(&I, Result);
3560 /// GetSignificand - Get the significand and build it into a floating-point
3561 /// number with exponent of 1:
3563 /// Op = (Op & 0x007fffff) | 0x3f800000;
3565 /// where Op is the hexadecimal representation of floating point value.
3567 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3568 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3569 DAG.getConstant(0x007fffff, dl, MVT::i32));
3570 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3571 DAG.getConstant(0x3f800000, dl, MVT::i32));
3572 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3575 /// GetExponent - Get the exponent:
3577 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3579 /// where Op is the hexadecimal representation of floating point value.
3581 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3583 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3584 DAG.getConstant(0x7f800000, dl, MVT::i32));
3585 SDValue t1 = DAG.getNode(
3586 ISD::SRL, dl, MVT::i32, t0,
3587 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3588 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3589 DAG.getConstant(127, dl, MVT::i32));
3590 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3593 /// getF32Constant - Get 32-bit floating point constant.
3595 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3596 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3600 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3601 SelectionDAG &DAG) {
3602 // IntegerPartOfX = ((int32_t)(t0);
3603 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3605 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3606 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3607 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3609 // IntegerPartOfX <<= 23;
3610 IntegerPartOfX = DAG.getNode(
3611 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3612 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3613 DAG.getDataLayout())));
3615 SDValue TwoToFractionalPartOfX;
3616 if (LimitFloatPrecision <= 6) {
3617 // For floating-point precision of 6:
3619 // TwoToFractionalPartOfX =
3621 // (0.735607626f + 0.252464424f * x) * x;
3623 // error 0.0144103317, which is 6 bits
3624 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3625 getF32Constant(DAG, 0x3e814304, dl));
3626 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3627 getF32Constant(DAG, 0x3f3c50c8, dl));
3628 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3629 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3630 getF32Constant(DAG, 0x3f7f5e7e, dl));
3631 } else if (LimitFloatPrecision <= 12) {
3632 // For floating-point precision of 12:
3634 // TwoToFractionalPartOfX =
3637 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3639 // error 0.000107046256, which is 13 to 14 bits
3640 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3641 getF32Constant(DAG, 0x3da235e3, dl));
3642 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3643 getF32Constant(DAG, 0x3e65b8f3, dl));
3644 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3645 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3646 getF32Constant(DAG, 0x3f324b07, dl));
3647 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3648 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3649 getF32Constant(DAG, 0x3f7ff8fd, dl));
3650 } else { // LimitFloatPrecision <= 18
3651 // For floating-point precision of 18:
3653 // TwoToFractionalPartOfX =
3657 // (0.554906021e-1f +
3658 // (0.961591928e-2f +
3659 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3660 // error 2.47208000*10^(-7), which is better than 18 bits
3661 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3662 getF32Constant(DAG, 0x3924b03e, dl));
3663 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3664 getF32Constant(DAG, 0x3ab24b87, dl));
3665 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3666 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3667 getF32Constant(DAG, 0x3c1d8c17, dl));
3668 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3669 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3670 getF32Constant(DAG, 0x3d634a1d, dl));
3671 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3672 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3673 getF32Constant(DAG, 0x3e75fe14, dl));
3674 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3675 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3676 getF32Constant(DAG, 0x3f317234, dl));
3677 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3678 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3679 getF32Constant(DAG, 0x3f800000, dl));
3682 // Add the exponent into the result in integer domain.
3683 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3684 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3685 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3688 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3689 /// limited-precision mode.
3690 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3691 const TargetLowering &TLI) {
3692 if (Op.getValueType() == MVT::f32 &&
3693 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3695 // Put the exponent in the right bit position for later addition to the
3698 // #define LOG2OFe 1.4426950f
3699 // t0 = Op * LOG2OFe
3700 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3701 getF32Constant(DAG, 0x3fb8aa3b, dl));
3702 return getLimitedPrecisionExp2(t0, dl, DAG);
3705 // No special expansion.
3706 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3709 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3710 /// limited-precision mode.
3711 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3712 const TargetLowering &TLI) {
3713 if (Op.getValueType() == MVT::f32 &&
3714 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3715 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3717 // Scale the exponent by log(2) [0.69314718f].
3718 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3719 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3720 getF32Constant(DAG, 0x3f317218, dl));
3722 // Get the significand and build it into a floating-point number with
3724 SDValue X = GetSignificand(DAG, Op1, dl);
3726 SDValue LogOfMantissa;
3727 if (LimitFloatPrecision <= 6) {
3728 // For floating-point precision of 6:
3732 // (1.4034025f - 0.23903021f * x) * x;
3734 // error 0.0034276066, which is better than 8 bits
3735 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3736 getF32Constant(DAG, 0xbe74c456, dl));
3737 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3738 getF32Constant(DAG, 0x3fb3a2b1, dl));
3739 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3740 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3741 getF32Constant(DAG, 0x3f949a29, dl));
3742 } else if (LimitFloatPrecision <= 12) {
3743 // For floating-point precision of 12:
3749 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3751 // error 0.000061011436, which is 14 bits
3752 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0xbd67b6d6, dl));
3754 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3755 getF32Constant(DAG, 0x3ee4f4b8, dl));
3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3757 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3758 getF32Constant(DAG, 0x3fbc278b, dl));
3759 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3760 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3761 getF32Constant(DAG, 0x40348e95, dl));
3762 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3763 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3764 getF32Constant(DAG, 0x3fdef31a, dl));
3765 } else { // LimitFloatPrecision <= 18
3766 // For floating-point precision of 18:
3774 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3776 // error 0.0000023660568, which is better than 18 bits
3777 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3778 getF32Constant(DAG, 0xbc91e5ac, dl));
3779 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3780 getF32Constant(DAG, 0x3e4350aa, dl));
3781 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3782 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3783 getF32Constant(DAG, 0x3f60d3e3, dl));
3784 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3785 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3786 getF32Constant(DAG, 0x4011cdf0, dl));
3787 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3788 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3789 getF32Constant(DAG, 0x406cfd1c, dl));
3790 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3791 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3792 getF32Constant(DAG, 0x408797cb, dl));
3793 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3794 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3795 getF32Constant(DAG, 0x4006dcab, dl));
3798 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3801 // No special expansion.
3802 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3805 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3806 /// limited-precision mode.
3807 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3808 const TargetLowering &TLI) {
3809 if (Op.getValueType() == MVT::f32 &&
3810 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3811 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3813 // Get the exponent.
3814 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3816 // Get the significand and build it into a floating-point number with
3818 SDValue X = GetSignificand(DAG, Op1, dl);
3820 // Different possible minimax approximations of significand in
3821 // floating-point for various degrees of accuracy over [1,2].
3822 SDValue Log2ofMantissa;
3823 if (LimitFloatPrecision <= 6) {
3824 // For floating-point precision of 6:
3826 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3828 // error 0.0049451742, which is more than 7 bits
3829 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3830 getF32Constant(DAG, 0xbeb08fe0, dl));
3831 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3832 getF32Constant(DAG, 0x40019463, dl));
3833 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3834 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3835 getF32Constant(DAG, 0x3fd6633d, dl));
3836 } else if (LimitFloatPrecision <= 12) {
3837 // For floating-point precision of 12:
3843 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3845 // error 0.0000876136000, which is better than 13 bits
3846 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3847 getF32Constant(DAG, 0xbda7262e, dl));
3848 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3849 getF32Constant(DAG, 0x3f25280b, dl));
3850 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3851 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3852 getF32Constant(DAG, 0x4007b923, dl));
3853 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3854 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3855 getF32Constant(DAG, 0x40823e2f, dl));
3856 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3857 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3858 getF32Constant(DAG, 0x4020d29c, dl));
3859 } else { // LimitFloatPrecision <= 18
3860 // For floating-point precision of 18:
3869 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3871 // error 0.0000018516, which is better than 18 bits
3872 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3873 getF32Constant(DAG, 0xbcd2769e, dl));
3874 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3875 getF32Constant(DAG, 0x3e8ce0b9, dl));
3876 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3877 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3878 getF32Constant(DAG, 0x3fa22ae7, dl));
3879 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3880 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3881 getF32Constant(DAG, 0x40525723, dl));
3882 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3883 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3884 getF32Constant(DAG, 0x40aaf200, dl));
3885 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3886 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3887 getF32Constant(DAG, 0x40c39dad, dl));
3888 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3889 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3890 getF32Constant(DAG, 0x4042902c, dl));
3893 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3896 // No special expansion.
3897 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3900 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3901 /// limited-precision mode.
3902 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3903 const TargetLowering &TLI) {
3904 if (Op.getValueType() == MVT::f32 &&
3905 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3906 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3908 // Scale the exponent by log10(2) [0.30102999f].
3909 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3910 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3911 getF32Constant(DAG, 0x3e9a209a, dl));
3913 // Get the significand and build it into a floating-point number with
3915 SDValue X = GetSignificand(DAG, Op1, dl);
3917 SDValue Log10ofMantissa;
3918 if (LimitFloatPrecision <= 6) {
3919 // For floating-point precision of 6:
3921 // Log10ofMantissa =
3923 // (0.60948995f - 0.10380950f * x) * x;
3925 // error 0.0014886165, which is 6 bits
3926 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3927 getF32Constant(DAG, 0xbdd49a13, dl));
3928 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3929 getF32Constant(DAG, 0x3f1c0789, dl));
3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3931 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3932 getF32Constant(DAG, 0x3f011300, dl));
3933 } else if (LimitFloatPrecision <= 12) {
3934 // For floating-point precision of 12:
3936 // Log10ofMantissa =
3939 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3941 // error 0.00019228036, which is better than 12 bits
3942 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3943 getF32Constant(DAG, 0x3d431f31, dl));
3944 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3945 getF32Constant(DAG, 0x3ea21fb2, dl));
3946 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3947 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3948 getF32Constant(DAG, 0x3f6ae232, dl));
3949 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3950 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3951 getF32Constant(DAG, 0x3f25f7c3, dl));
3952 } else { // LimitFloatPrecision <= 18
3953 // For floating-point precision of 18:
3955 // Log10ofMantissa =
3960 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3962 // error 0.0000037995730, which is better than 18 bits
3963 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3964 getF32Constant(DAG, 0x3c5d51ce, dl));
3965 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3966 getF32Constant(DAG, 0x3e00685a, dl));
3967 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3968 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3969 getF32Constant(DAG, 0x3efb6798, dl));
3970 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3971 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3972 getF32Constant(DAG, 0x3f88d192, dl));
3973 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3974 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3975 getF32Constant(DAG, 0x3fc4316c, dl));
3976 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3977 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3978 getF32Constant(DAG, 0x3f57ce70, dl));
3981 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3984 // No special expansion.
3985 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3988 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3989 /// limited-precision mode.
3990 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3991 const TargetLowering &TLI) {
3992 if (Op.getValueType() == MVT::f32 &&
3993 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3994 return getLimitedPrecisionExp2(Op, dl, DAG);
3996 // No special expansion.
3997 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4000 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4001 /// limited-precision mode with x == 10.0f.
4002 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4003 SelectionDAG &DAG, const TargetLowering &TLI) {
4004 bool IsExp10 = false;
4005 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4006 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4007 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4009 IsExp10 = LHSC->isExactlyValue(Ten);
4014 // Put the exponent in the right bit position for later addition to the
4017 // #define LOG2OF10 3.3219281f
4018 // t0 = Op * LOG2OF10;
4019 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4020 getF32Constant(DAG, 0x40549a78, dl));
4021 return getLimitedPrecisionExp2(t0, dl, DAG);
4024 // No special expansion.
4025 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4029 /// ExpandPowI - Expand a llvm.powi intrinsic.
4030 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4031 SelectionDAG &DAG) {
4032 // If RHS is a constant, we can expand this out to a multiplication tree,
4033 // otherwise we end up lowering to a call to __powidf2 (for example). When
4034 // optimizing for size, we only want to do this if the expansion would produce
4035 // a small number of multiplies, otherwise we do the full expansion.
4036 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4037 // Get the exponent as a positive value.
4038 unsigned Val = RHSC->getSExtValue();
4039 if ((int)Val < 0) Val = -Val;
4041 // powi(x, 0) -> 1.0
4043 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4045 const Function *F = DAG.getMachineFunction().getFunction();
4046 if (!F->optForSize() ||
4047 // If optimizing for size, don't insert too many multiplies.
4048 // This inserts up to 5 multiplies.
4049 countPopulation(Val) + Log2_32(Val) < 7) {
4050 // We use the simple binary decomposition method to generate the multiply
4051 // sequence. There are more optimal ways to do this (for example,
4052 // powi(x,15) generates one more multiply than it should), but this has
4053 // the benefit of being both really simple and much better than a libcall.
4054 SDValue Res; // Logically starts equal to 1.0
4055 SDValue CurSquare = LHS;
4059 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4061 Res = CurSquare; // 1.0*CurSquare.
4064 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4065 CurSquare, CurSquare);
4069 // If the original was negative, invert the result, producing 1/(x*x*x).
4070 if (RHSC->getSExtValue() < 0)
4071 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4072 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4077 // Otherwise, expand to a libcall.
4078 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4081 // getTruncatedArgReg - Find underlying register used for an truncated
4083 static unsigned getTruncatedArgReg(const SDValue &N) {
4084 if (N.getOpcode() != ISD::TRUNCATE)
4087 const SDValue &Ext = N.getOperand(0);
4088 if (Ext.getOpcode() == ISD::AssertZext ||
4089 Ext.getOpcode() == ISD::AssertSext) {
4090 const SDValue &CFR = Ext.getOperand(0);
4091 if (CFR.getOpcode() == ISD::CopyFromReg)
4092 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4093 if (CFR.getOpcode() == ISD::TRUNCATE)
4094 return getTruncatedArgReg(CFR);
4099 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4100 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4101 /// At the end of instruction selection, they will be inserted to the entry BB.
4102 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4103 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4104 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4105 const Argument *Arg = dyn_cast<Argument>(V);
4109 MachineFunction &MF = DAG.getMachineFunction();
4110 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4112 // Ignore inlined function arguments here.
4114 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4115 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4118 Optional<MachineOperand> Op;
4119 // Some arguments' frame index is recorded during argument lowering.
4120 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4121 Op = MachineOperand::CreateFI(FI);
4123 if (!Op && N.getNode()) {
4125 if (N.getOpcode() == ISD::CopyFromReg)
4126 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4128 Reg = getTruncatedArgReg(N);
4129 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4130 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4131 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4136 Op = MachineOperand::CreateReg(Reg, false);
4140 // Check if ValueMap has reg number.
4141 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4142 if (VMI != FuncInfo.ValueMap.end())
4143 Op = MachineOperand::CreateReg(VMI->second, false);
4146 if (!Op && N.getNode())
4147 // Check if frame index is available.
4148 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4149 if (FrameIndexSDNode *FINode =
4150 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4151 Op = MachineOperand::CreateFI(FINode->getIndex());
4156 assert(Variable->isValidLocationForIntrinsic(DL) &&
4157 "Expected inlined-at fields to agree");
4159 FuncInfo.ArgDbgValues.push_back(
4160 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4161 Op->getReg(), Offset, Variable, Expr));
4163 FuncInfo.ArgDbgValues.push_back(
4164 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4167 .addMetadata(Variable)
4168 .addMetadata(Expr));
4173 // VisualStudio defines setjmp as _setjmp
4174 #if defined(_MSC_VER) && defined(setjmp) && \
4175 !defined(setjmp_undefined_for_msvc)
4176 # pragma push_macro("setjmp")
4178 # define setjmp_undefined_for_msvc
4181 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4182 /// we want to emit this as a call to a named external function, return the name
4183 /// otherwise lower it and return null.
4185 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4187 SDLoc sdl = getCurSDLoc();
4188 DebugLoc dl = getCurDebugLoc();
4191 switch (Intrinsic) {
4193 // By default, turn this into a target intrinsic node.
4194 visitTargetIntrinsic(I, Intrinsic);
4196 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4197 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4198 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4199 case Intrinsic::returnaddress:
4200 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4201 TLI.getPointerTy(DAG.getDataLayout()),
4202 getValue(I.getArgOperand(0))));
4204 case Intrinsic::frameaddress:
4205 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4206 TLI.getPointerTy(DAG.getDataLayout()),
4207 getValue(I.getArgOperand(0))));
4209 case Intrinsic::read_register: {
4210 Value *Reg = I.getArgOperand(0);
4211 SDValue Chain = getRoot();
4213 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4214 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4215 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4216 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4218 DAG.setRoot(Res.getValue(1));
4221 case Intrinsic::write_register: {
4222 Value *Reg = I.getArgOperand(0);
4223 Value *RegValue = I.getArgOperand(1);
4224 SDValue Chain = getRoot();
4226 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4227 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4228 RegName, getValue(RegValue)));
4231 case Intrinsic::setjmp:
4232 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4233 case Intrinsic::longjmp:
4234 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4235 case Intrinsic::memcpy: {
4236 // FIXME: this definition of "user defined address space" is x86-specific
4237 // Assert for address < 256 since we support only user defined address
4239 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4241 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4243 "Unknown address space");
4244 SDValue Op1 = getValue(I.getArgOperand(0));
4245 SDValue Op2 = getValue(I.getArgOperand(1));
4246 SDValue Op3 = getValue(I.getArgOperand(2));
4247 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4249 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4250 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4251 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4252 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4254 MachinePointerInfo(I.getArgOperand(0)),
4255 MachinePointerInfo(I.getArgOperand(1)));
4256 updateDAGForMaybeTailCall(MC);
4259 case Intrinsic::memset: {
4260 // FIXME: this definition of "user defined address space" is x86-specific
4261 // Assert for address < 256 since we support only user defined address
4263 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4265 "Unknown address space");
4266 SDValue Op1 = getValue(I.getArgOperand(0));
4267 SDValue Op2 = getValue(I.getArgOperand(1));
4268 SDValue Op3 = getValue(I.getArgOperand(2));
4269 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4271 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4272 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4273 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4274 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4275 isTC, MachinePointerInfo(I.getArgOperand(0)));
4276 updateDAGForMaybeTailCall(MS);
4279 case Intrinsic::memmove: {
4280 // FIXME: this definition of "user defined address space" is x86-specific
4281 // Assert for address < 256 since we support only user defined address
4283 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4285 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4287 "Unknown address space");
4288 SDValue Op1 = getValue(I.getArgOperand(0));
4289 SDValue Op2 = getValue(I.getArgOperand(1));
4290 SDValue Op3 = getValue(I.getArgOperand(2));
4291 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4293 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4294 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4295 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4296 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4297 isTC, MachinePointerInfo(I.getArgOperand(0)),
4298 MachinePointerInfo(I.getArgOperand(1)));
4299 updateDAGForMaybeTailCall(MM);
4302 case Intrinsic::dbg_declare: {
4303 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4304 DILocalVariable *Variable = DI.getVariable();
4305 DIExpression *Expression = DI.getExpression();
4306 const Value *Address = DI.getAddress();
4307 assert(Variable && "Missing variable");
4309 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4313 // Check if address has undef value.
4314 if (isa<UndefValue>(Address) ||
4315 (Address->use_empty() && !isa<Argument>(Address))) {
4316 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4320 SDValue &N = NodeMap[Address];
4321 if (!N.getNode() && isa<Argument>(Address))
4322 // Check unused arguments map.
4323 N = UnusedArgNodeMap[Address];
4326 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4327 Address = BCI->getOperand(0);
4328 // Parameters are handled specially.
4329 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4331 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4333 if (isParameter && !AI) {
4334 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4336 // Byval parameter. We have a frame index at this point.
4337 SDV = DAG.getFrameIndexDbgValue(
4338 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4340 // Address is an argument, so try to emit its dbg value using
4341 // virtual register info from the FuncInfo.ValueMap.
4342 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4347 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4348 true, 0, dl, SDNodeOrder);
4350 // Can't do anything with other non-AI cases yet.
4351 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4352 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4353 DEBUG(Address->dump());
4356 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4358 // If Address is an argument then try to emit its dbg value using
4359 // virtual register info from the FuncInfo.ValueMap.
4360 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4362 // If variable is pinned by a alloca in dominating bb then
4363 // use StaticAllocaMap.
4364 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4365 if (AI->getParent() != DI.getParent()) {
4366 DenseMap<const AllocaInst*, int>::iterator SI =
4367 FuncInfo.StaticAllocaMap.find(AI);
4368 if (SI != FuncInfo.StaticAllocaMap.end()) {
4369 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4370 0, dl, SDNodeOrder);
4371 DAG.AddDbgValue(SDV, nullptr, false);
4376 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4381 case Intrinsic::dbg_value: {
4382 const DbgValueInst &DI = cast<DbgValueInst>(I);
4383 assert(DI.getVariable() && "Missing variable");
4385 DILocalVariable *Variable = DI.getVariable();
4386 DIExpression *Expression = DI.getExpression();
4387 uint64_t Offset = DI.getOffset();
4388 const Value *V = DI.getValue();
4393 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4394 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4396 DAG.AddDbgValue(SDV, nullptr, false);
4398 // Do not use getValue() in here; we don't want to generate code at
4399 // this point if it hasn't been done yet.
4400 SDValue N = NodeMap[V];
4401 if (!N.getNode() && isa<Argument>(V))
4402 // Check unused arguments map.
4403 N = UnusedArgNodeMap[V];
4405 // A dbg.value for an alloca is always indirect.
4406 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4407 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4409 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4410 IsIndirect, Offset, dl, SDNodeOrder);
4411 DAG.AddDbgValue(SDV, N.getNode(), false);
4413 } else if (!V->use_empty() ) {
4414 // Do not call getValue(V) yet, as we don't want to generate code.
4415 // Remember it for later.
4416 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4417 DanglingDebugInfoMap[V] = DDI;
4419 // We may expand this to cover more cases. One case where we have no
4420 // data available is an unreferenced parameter.
4421 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4425 // Build a debug info table entry.
4426 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4427 V = BCI->getOperand(0);
4428 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4429 // Don't handle byval struct arguments or VLAs, for example.
4431 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4432 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4435 DenseMap<const AllocaInst*, int>::iterator SI =
4436 FuncInfo.StaticAllocaMap.find(AI);
4437 if (SI == FuncInfo.StaticAllocaMap.end())
4438 return nullptr; // VLAs.
4442 case Intrinsic::eh_typeid_for: {
4443 // Find the type id for the given typeinfo.
4444 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4445 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4446 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4451 case Intrinsic::eh_return_i32:
4452 case Intrinsic::eh_return_i64:
4453 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4454 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4457 getValue(I.getArgOperand(0)),
4458 getValue(I.getArgOperand(1))));
4460 case Intrinsic::eh_unwind_init:
4461 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4463 case Intrinsic::eh_dwarf_cfa: {
4464 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4465 TLI.getPointerTy(DAG.getDataLayout()));
4466 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4467 CfaArg.getValueType(),
4468 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4469 CfaArg.getValueType()),
4471 SDValue FA = DAG.getNode(
4472 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4473 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4474 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4478 case Intrinsic::eh_sjlj_callsite: {
4479 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4480 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4481 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4482 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4484 MMI.setCurrentCallSite(CI->getZExtValue());
4487 case Intrinsic::eh_sjlj_functioncontext: {
4488 // Get and store the index of the function context.
4489 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4491 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4492 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4493 MFI->setFunctionContextIndex(FI);
4496 case Intrinsic::eh_sjlj_setjmp: {
4499 Ops[1] = getValue(I.getArgOperand(0));
4500 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4501 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4502 setValue(&I, Op.getValue(0));
4503 DAG.setRoot(Op.getValue(1));
4506 case Intrinsic::eh_sjlj_longjmp: {
4507 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4508 getRoot(), getValue(I.getArgOperand(0))));
4511 case Intrinsic::eh_sjlj_setup_dispatch: {
4512 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4517 case Intrinsic::masked_gather:
4518 visitMaskedGather(I);
4520 case Intrinsic::masked_load:
4523 case Intrinsic::masked_scatter:
4524 visitMaskedScatter(I);
4526 case Intrinsic::masked_store:
4527 visitMaskedStore(I);
4529 case Intrinsic::x86_mmx_pslli_w:
4530 case Intrinsic::x86_mmx_pslli_d:
4531 case Intrinsic::x86_mmx_pslli_q:
4532 case Intrinsic::x86_mmx_psrli_w:
4533 case Intrinsic::x86_mmx_psrli_d:
4534 case Intrinsic::x86_mmx_psrli_q:
4535 case Intrinsic::x86_mmx_psrai_w:
4536 case Intrinsic::x86_mmx_psrai_d: {
4537 SDValue ShAmt = getValue(I.getArgOperand(1));
4538 if (isa<ConstantSDNode>(ShAmt)) {
4539 visitTargetIntrinsic(I, Intrinsic);
4542 unsigned NewIntrinsic = 0;
4543 EVT ShAmtVT = MVT::v2i32;
4544 switch (Intrinsic) {
4545 case Intrinsic::x86_mmx_pslli_w:
4546 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4548 case Intrinsic::x86_mmx_pslli_d:
4549 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4551 case Intrinsic::x86_mmx_pslli_q:
4552 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4554 case Intrinsic::x86_mmx_psrli_w:
4555 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4557 case Intrinsic::x86_mmx_psrli_d:
4558 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4560 case Intrinsic::x86_mmx_psrli_q:
4561 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4563 case Intrinsic::x86_mmx_psrai_w:
4564 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4566 case Intrinsic::x86_mmx_psrai_d:
4567 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4569 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4572 // The vector shift intrinsics with scalars uses 32b shift amounts but
4573 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4575 // We must do this early because v2i32 is not a legal type.
4578 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4579 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4580 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4581 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4582 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4583 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4584 getValue(I.getArgOperand(0)), ShAmt);
4588 case Intrinsic::convertff:
4589 case Intrinsic::convertfsi:
4590 case Intrinsic::convertfui:
4591 case Intrinsic::convertsif:
4592 case Intrinsic::convertuif:
4593 case Intrinsic::convertss:
4594 case Intrinsic::convertsu:
4595 case Intrinsic::convertus:
4596 case Intrinsic::convertuu: {
4597 ISD::CvtCode Code = ISD::CVT_INVALID;
4598 switch (Intrinsic) {
4599 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4600 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4601 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4602 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4603 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4604 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4605 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4606 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4607 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4608 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4610 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4611 const Value *Op1 = I.getArgOperand(0);
4612 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4613 DAG.getValueType(DestVT),
4614 DAG.getValueType(getValue(Op1).getValueType()),
4615 getValue(I.getArgOperand(1)),
4616 getValue(I.getArgOperand(2)),
4621 case Intrinsic::powi:
4622 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4623 getValue(I.getArgOperand(1)), DAG));
4625 case Intrinsic::log:
4626 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4628 case Intrinsic::log2:
4629 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4631 case Intrinsic::log10:
4632 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4634 case Intrinsic::exp:
4635 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4637 case Intrinsic::exp2:
4638 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4640 case Intrinsic::pow:
4641 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4642 getValue(I.getArgOperand(1)), DAG, TLI));
4644 case Intrinsic::sqrt:
4645 case Intrinsic::fabs:
4646 case Intrinsic::sin:
4647 case Intrinsic::cos:
4648 case Intrinsic::floor:
4649 case Intrinsic::ceil:
4650 case Intrinsic::trunc:
4651 case Intrinsic::rint:
4652 case Intrinsic::nearbyint:
4653 case Intrinsic::round: {
4655 switch (Intrinsic) {
4656 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4657 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4658 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4659 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4660 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4661 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4662 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4663 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4664 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4665 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4666 case Intrinsic::round: Opcode = ISD::FROUND; break;
4669 setValue(&I, DAG.getNode(Opcode, sdl,
4670 getValue(I.getArgOperand(0)).getValueType(),
4671 getValue(I.getArgOperand(0))));
4674 case Intrinsic::minnum:
4675 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4676 getValue(I.getArgOperand(0)).getValueType(),
4677 getValue(I.getArgOperand(0)),
4678 getValue(I.getArgOperand(1))));
4680 case Intrinsic::maxnum:
4681 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4682 getValue(I.getArgOperand(0)).getValueType(),
4683 getValue(I.getArgOperand(0)),
4684 getValue(I.getArgOperand(1))));
4686 case Intrinsic::copysign:
4687 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4688 getValue(I.getArgOperand(0)).getValueType(),
4689 getValue(I.getArgOperand(0)),
4690 getValue(I.getArgOperand(1))));
4692 case Intrinsic::fma:
4693 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4694 getValue(I.getArgOperand(0)).getValueType(),
4695 getValue(I.getArgOperand(0)),
4696 getValue(I.getArgOperand(1)),
4697 getValue(I.getArgOperand(2))));
4699 case Intrinsic::fmuladd: {
4700 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4701 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4702 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4703 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4704 getValue(I.getArgOperand(0)).getValueType(),
4705 getValue(I.getArgOperand(0)),
4706 getValue(I.getArgOperand(1)),
4707 getValue(I.getArgOperand(2))));
4709 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4710 getValue(I.getArgOperand(0)).getValueType(),
4711 getValue(I.getArgOperand(0)),
4712 getValue(I.getArgOperand(1)));
4713 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4714 getValue(I.getArgOperand(0)).getValueType(),
4716 getValue(I.getArgOperand(2)));
4721 case Intrinsic::convert_to_fp16:
4722 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4723 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4724 getValue(I.getArgOperand(0)),
4725 DAG.getTargetConstant(0, sdl,
4728 case Intrinsic::convert_from_fp16:
4729 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4730 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4731 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4732 getValue(I.getArgOperand(0)))));
4734 case Intrinsic::pcmarker: {
4735 SDValue Tmp = getValue(I.getArgOperand(0));
4736 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4739 case Intrinsic::readcyclecounter: {
4740 SDValue Op = getRoot();
4741 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4742 DAG.getVTList(MVT::i64, MVT::Other), Op);
4744 DAG.setRoot(Res.getValue(1));
4747 case Intrinsic::bswap:
4748 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4749 getValue(I.getArgOperand(0)).getValueType(),
4750 getValue(I.getArgOperand(0))));
4752 case Intrinsic::uabsdiff:
4753 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4754 getValue(I.getArgOperand(0)).getValueType(),
4755 getValue(I.getArgOperand(0)),
4756 getValue(I.getArgOperand(1))));
4758 case Intrinsic::sabsdiff:
4759 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4760 getValue(I.getArgOperand(0)).getValueType(),
4761 getValue(I.getArgOperand(0)),
4762 getValue(I.getArgOperand(1))));
4764 case Intrinsic::cttz: {
4765 SDValue Arg = getValue(I.getArgOperand(0));
4766 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4767 EVT Ty = Arg.getValueType();
4768 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4772 case Intrinsic::ctlz: {
4773 SDValue Arg = getValue(I.getArgOperand(0));
4774 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4775 EVT Ty = Arg.getValueType();
4776 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4780 case Intrinsic::ctpop: {
4781 SDValue Arg = getValue(I.getArgOperand(0));
4782 EVT Ty = Arg.getValueType();
4783 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4786 case Intrinsic::stacksave: {
4787 SDValue Op = getRoot();
4789 ISD::STACKSAVE, sdl,
4790 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4792 DAG.setRoot(Res.getValue(1));
4795 case Intrinsic::stackrestore: {
4796 Res = getValue(I.getArgOperand(0));
4797 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4800 case Intrinsic::stackprotector: {
4801 // Emit code into the DAG to store the stack guard onto the stack.
4802 MachineFunction &MF = DAG.getMachineFunction();
4803 MachineFrameInfo *MFI = MF.getFrameInfo();
4804 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4805 SDValue Src, Chain = getRoot();
4806 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4807 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4809 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4810 // global variable __stack_chk_guard.
4812 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4813 if (BC->getOpcode() == Instruction::BitCast)
4814 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4816 if (GV && TLI.useLoadStackGuardNode()) {
4817 // Emit a LOAD_STACK_GUARD node.
4818 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4820 MachinePointerInfo MPInfo(GV);
4821 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4822 unsigned Flags = MachineMemOperand::MOLoad |
4823 MachineMemOperand::MOInvariant;
4824 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4825 PtrTy.getSizeInBits() / 8,
4826 DAG.getEVTAlignment(PtrTy));
4827 Node->setMemRefs(MemRefs, MemRefs + 1);
4829 // Copy the guard value to a virtual register so that it can be
4830 // retrieved in the epilogue.
4831 Src = SDValue(Node, 0);
4832 const TargetRegisterClass *RC =
4833 TLI.getRegClassFor(Src.getSimpleValueType());
4834 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4836 SPDescriptor.setGuardReg(Reg);
4837 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4839 Src = getValue(I.getArgOperand(0)); // The guard's value.
4842 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4844 int FI = FuncInfo.StaticAllocaMap[Slot];
4845 MFI->setStackProtectorIndex(FI);
4847 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4849 // Store the stack protector onto the stack.
4850 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4851 DAG.getMachineFunction(), FI),
4857 case Intrinsic::objectsize: {
4858 // If we don't know by now, we're never going to know.
4859 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4861 assert(CI && "Non-constant type in __builtin_object_size?");
4863 SDValue Arg = getValue(I.getCalledValue());
4864 EVT Ty = Arg.getValueType();
4867 Res = DAG.getConstant(-1ULL, sdl, Ty);
4869 Res = DAG.getConstant(0, sdl, Ty);
4874 case Intrinsic::annotation:
4875 case Intrinsic::ptr_annotation:
4876 // Drop the intrinsic, but forward the value
4877 setValue(&I, getValue(I.getOperand(0)));
4879 case Intrinsic::assume:
4880 case Intrinsic::var_annotation:
4881 // Discard annotate attributes and assumptions
4884 case Intrinsic::init_trampoline: {
4885 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4889 Ops[1] = getValue(I.getArgOperand(0));
4890 Ops[2] = getValue(I.getArgOperand(1));
4891 Ops[3] = getValue(I.getArgOperand(2));
4892 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4893 Ops[5] = DAG.getSrcValue(F);
4895 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4900 case Intrinsic::adjust_trampoline: {
4901 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4902 TLI.getPointerTy(DAG.getDataLayout()),
4903 getValue(I.getArgOperand(0))));
4906 case Intrinsic::gcroot:
4908 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4909 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4911 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4912 GFI->addStackRoot(FI->getIndex(), TypeMap);
4915 case Intrinsic::gcread:
4916 case Intrinsic::gcwrite:
4917 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4918 case Intrinsic::flt_rounds:
4919 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4922 case Intrinsic::expect: {
4923 // Just replace __builtin_expect(exp, c) with EXP.
4924 setValue(&I, getValue(I.getArgOperand(0)));
4928 case Intrinsic::debugtrap:
4929 case Intrinsic::trap: {
4930 StringRef TrapFuncName =
4932 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4933 .getValueAsString();
4934 if (TrapFuncName.empty()) {
4935 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4936 ISD::TRAP : ISD::DEBUGTRAP;
4937 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4940 TargetLowering::ArgListTy Args;
4942 TargetLowering::CallLoweringInfo CLI(DAG);
4943 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4944 CallingConv::C, I.getType(),
4945 DAG.getExternalSymbol(TrapFuncName.data(),
4946 TLI.getPointerTy(DAG.getDataLayout())),
4947 std::move(Args), 0);
4949 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4950 DAG.setRoot(Result.second);
4954 case Intrinsic::uadd_with_overflow:
4955 case Intrinsic::sadd_with_overflow:
4956 case Intrinsic::usub_with_overflow:
4957 case Intrinsic::ssub_with_overflow:
4958 case Intrinsic::umul_with_overflow:
4959 case Intrinsic::smul_with_overflow: {
4961 switch (Intrinsic) {
4962 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4963 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4964 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4965 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4966 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4967 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4968 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4970 SDValue Op1 = getValue(I.getArgOperand(0));
4971 SDValue Op2 = getValue(I.getArgOperand(1));
4973 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4974 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4977 case Intrinsic::prefetch: {
4979 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4981 Ops[1] = getValue(I.getArgOperand(0));
4982 Ops[2] = getValue(I.getArgOperand(1));
4983 Ops[3] = getValue(I.getArgOperand(2));
4984 Ops[4] = getValue(I.getArgOperand(3));
4985 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4986 DAG.getVTList(MVT::Other), Ops,
4987 EVT::getIntegerVT(*Context, 8),
4988 MachinePointerInfo(I.getArgOperand(0)),
4990 false, /* volatile */
4992 rw==1)); /* write */
4995 case Intrinsic::lifetime_start:
4996 case Intrinsic::lifetime_end: {
4997 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4998 // Stack coloring is not enabled in O0, discard region information.
4999 if (TM.getOptLevel() == CodeGenOpt::None)
5002 SmallVector<Value *, 4> Allocas;
5003 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5005 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5006 E = Allocas.end(); Object != E; ++Object) {
5007 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5009 // Could not find an Alloca.
5010 if (!LifetimeObject)
5013 // First check that the Alloca is static, otherwise it won't have a
5014 // valid frame index.
5015 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5016 if (SI == FuncInfo.StaticAllocaMap.end())
5019 int FI = SI->second;
5024 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5025 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5027 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5032 case Intrinsic::invariant_start:
5033 // Discard region information.
5034 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5036 case Intrinsic::invariant_end:
5037 // Discard region information.
5039 case Intrinsic::stackprotectorcheck: {
5040 // Do not actually emit anything for this basic block. Instead we initialize
5041 // the stack protector descriptor and export the guard variable so we can
5042 // access it in FinishBasicBlock.
5043 const BasicBlock *BB = I.getParent();
5044 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5045 ExportFromCurrentBlock(SPDescriptor.getGuard());
5047 // Flush our exports since we are going to process a terminator.
5048 (void)getControlRoot();
5051 case Intrinsic::clear_cache:
5052 return TLI.getClearCacheBuiltinName();
5053 case Intrinsic::eh_actions:
5054 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5056 case Intrinsic::donothing:
5059 case Intrinsic::experimental_stackmap: {
5063 case Intrinsic::experimental_patchpoint_void:
5064 case Intrinsic::experimental_patchpoint_i64: {
5065 visitPatchpoint(&I);
5068 case Intrinsic::experimental_gc_statepoint: {
5072 case Intrinsic::experimental_gc_result_int:
5073 case Intrinsic::experimental_gc_result_float:
5074 case Intrinsic::experimental_gc_result_ptr:
5075 case Intrinsic::experimental_gc_result: {
5079 case Intrinsic::experimental_gc_relocate: {
5083 case Intrinsic::instrprof_increment:
5084 llvm_unreachable("instrprof failed to lower an increment");
5086 case Intrinsic::localescape: {
5087 MachineFunction &MF = DAG.getMachineFunction();
5088 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5090 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5091 // is the same on all targets.
5092 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5093 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5094 if (isa<ConstantPointerNull>(Arg))
5095 continue; // Skip null pointers. They represent a hole in index space.
5096 AllocaInst *Slot = cast<AllocaInst>(Arg);
5097 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5098 "can only escape static allocas");
5099 int FI = FuncInfo.StaticAllocaMap[Slot];
5100 MCSymbol *FrameAllocSym =
5101 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5102 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5104 TII->get(TargetOpcode::LOCAL_ESCAPE))
5105 .addSym(FrameAllocSym)
5112 case Intrinsic::localrecover: {
5113 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5114 MachineFunction &MF = DAG.getMachineFunction();
5115 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5117 // Get the symbol that defines the frame offset.
5118 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5119 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5120 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5121 MCSymbol *FrameAllocSym =
5122 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5123 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5125 // Create a MCSymbol for the label to avoid any target lowering
5126 // that would make this PC relative.
5127 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5129 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5131 // Add the offset to the FP.
5132 Value *FP = I.getArgOperand(1);
5133 SDValue FPVal = getValue(FP);
5134 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5139 case Intrinsic::eh_begincatch:
5140 case Intrinsic::eh_endcatch:
5141 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5142 case Intrinsic::eh_exceptioncode: {
5143 unsigned Reg = TLI.getExceptionPointerRegister();
5144 assert(Reg && "cannot get exception code on this platform");
5145 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5146 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5147 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5148 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5150 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5151 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5158 std::pair<SDValue, SDValue>
5159 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5160 const BasicBlock *EHPadBB) {
5161 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5162 MCSymbol *BeginLabel = nullptr;
5165 // Insert a label before the invoke call to mark the try range. This can be
5166 // used to detect deletion of the invoke via the MachineModuleInfo.
5167 BeginLabel = MMI.getContext().createTempSymbol();
5169 // For SjLj, keep track of which landing pads go with which invokes
5170 // so as to maintain the ordering of pads in the LSDA.
5171 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5172 if (CallSiteIndex) {
5173 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5174 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5176 // Now that the call site is handled, stop tracking it.
5177 MMI.setCurrentCallSite(0);
5180 // Both PendingLoads and PendingExports must be flushed here;
5181 // this call might not return.
5183 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5185 CLI.setChain(getRoot());
5187 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5188 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5190 assert((CLI.IsTailCall || Result.second.getNode()) &&
5191 "Non-null chain expected with non-tail call!");
5192 assert((Result.second.getNode() || !Result.first.getNode()) &&
5193 "Null value expected with tail call!");
5195 if (!Result.second.getNode()) {
5196 // As a special case, a null chain means that a tail call has been emitted
5197 // and the DAG root is already updated.
5200 // Since there's no actual continuation from this block, nothing can be
5201 // relying on us setting vregs for them.
5202 PendingExports.clear();
5204 DAG.setRoot(Result.second);
5208 // Insert a label at the end of the invoke call to mark the try range. This
5209 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5210 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5211 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5213 // Inform MachineModuleInfo of range.
5214 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5220 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5222 const BasicBlock *EHPadBB) {
5223 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5224 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5225 Type *RetTy = FTy->getReturnType();
5227 TargetLowering::ArgListTy Args;
5228 TargetLowering::ArgListEntry Entry;
5229 Args.reserve(CS.arg_size());
5231 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5233 const Value *V = *i;
5236 if (V->getType()->isEmptyTy())
5239 SDValue ArgNode = getValue(V);
5240 Entry.Node = ArgNode; Entry.Ty = V->getType();
5242 // Skip the first return-type Attribute to get to params.
5243 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5244 Args.push_back(Entry);
5246 // If we have an explicit sret argument that is an Instruction, (i.e., it
5247 // might point to function-local memory), we can't meaningfully tail-call.
5248 if (Entry.isSRet && isa<Instruction>(V))
5252 // Check if target-independent constraints permit a tail call here.
5253 // Target-dependent constraints are checked within TLI->LowerCallTo.
5254 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5257 TargetLowering::CallLoweringInfo CLI(DAG);
5258 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5259 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5260 .setTailCall(isTailCall);
5261 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5263 if (Result.first.getNode())
5264 setValue(CS.getInstruction(), Result.first);
5267 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5268 /// value is equal or not-equal to zero.
5269 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5270 for (const User *U : V->users()) {
5271 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5272 if (IC->isEquality())
5273 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5274 if (C->isNullValue())
5276 // Unknown instruction.
5282 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5284 SelectionDAGBuilder &Builder) {
5286 // Check to see if this load can be trivially constant folded, e.g. if the
5287 // input is from a string literal.
5288 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5289 // Cast pointer to the type we really want to load.
5290 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5291 PointerType::getUnqual(LoadTy));
5293 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5294 const_cast<Constant *>(LoadInput), *Builder.DL))
5295 return Builder.getValue(LoadCst);
5298 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5299 // still constant memory, the input chain can be the entry node.
5301 bool ConstantMemory = false;
5303 // Do not serialize (non-volatile) loads of constant memory with anything.
5304 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5305 Root = Builder.DAG.getEntryNode();
5306 ConstantMemory = true;
5308 // Do not serialize non-volatile loads against each other.
5309 Root = Builder.DAG.getRoot();
5312 SDValue Ptr = Builder.getValue(PtrVal);
5313 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5314 Ptr, MachinePointerInfo(PtrVal),
5316 false /*nontemporal*/,
5317 false /*isinvariant*/, 1 /* align=1 */);
5319 if (!ConstantMemory)
5320 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5324 /// processIntegerCallValue - Record the value for an instruction that
5325 /// produces an integer result, converting the type where necessary.
5326 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5329 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5332 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5334 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5335 setValue(&I, Value);
5338 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5339 /// If so, return true and lower it, otherwise return false and it will be
5340 /// lowered like a normal call.
5341 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5342 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5343 if (I.getNumArgOperands() != 3)
5346 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5347 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5348 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5349 !I.getType()->isIntegerTy())
5352 const Value *Size = I.getArgOperand(2);
5353 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5354 if (CSize && CSize->getZExtValue() == 0) {
5355 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5357 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5361 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5362 std::pair<SDValue, SDValue> Res =
5363 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5364 getValue(LHS), getValue(RHS), getValue(Size),
5365 MachinePointerInfo(LHS),
5366 MachinePointerInfo(RHS));
5367 if (Res.first.getNode()) {
5368 processIntegerCallValue(I, Res.first, true);
5369 PendingLoads.push_back(Res.second);
5373 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5374 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5375 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5376 bool ActuallyDoIt = true;
5379 switch (CSize->getZExtValue()) {
5381 LoadVT = MVT::Other;
5383 ActuallyDoIt = false;
5387 LoadTy = Type::getInt16Ty(CSize->getContext());
5391 LoadTy = Type::getInt32Ty(CSize->getContext());
5395 LoadTy = Type::getInt64Ty(CSize->getContext());
5399 LoadVT = MVT::v4i32;
5400 LoadTy = Type::getInt32Ty(CSize->getContext());
5401 LoadTy = VectorType::get(LoadTy, 4);
5406 // This turns into unaligned loads. We only do this if the target natively
5407 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5408 // we'll only produce a small number of byte loads.
5410 // Require that we can find a legal MVT, and only do this if the target
5411 // supports unaligned loads of that type. Expanding into byte loads would
5413 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5414 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5415 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5416 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5417 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5418 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5419 // TODO: Check alignment of src and dest ptrs.
5420 if (!TLI.isTypeLegal(LoadVT) ||
5421 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5422 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5423 ActuallyDoIt = false;
5427 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5428 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5430 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5432 processIntegerCallValue(I, Res, false);
5441 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5442 /// form. If so, return true and lower it, otherwise return false and it
5443 /// will be lowered like a normal call.
5444 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5445 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5446 if (I.getNumArgOperands() != 3)
5449 const Value *Src = I.getArgOperand(0);
5450 const Value *Char = I.getArgOperand(1);
5451 const Value *Length = I.getArgOperand(2);
5452 if (!Src->getType()->isPointerTy() ||
5453 !Char->getType()->isIntegerTy() ||
5454 !Length->getType()->isIntegerTy() ||
5455 !I.getType()->isPointerTy())
5458 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5459 std::pair<SDValue, SDValue> Res =
5460 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5461 getValue(Src), getValue(Char), getValue(Length),
5462 MachinePointerInfo(Src));
5463 if (Res.first.getNode()) {
5464 setValue(&I, Res.first);
5465 PendingLoads.push_back(Res.second);
5472 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5473 /// optimized form. If so, return true and lower it, otherwise return false
5474 /// and it will be lowered like a normal call.
5475 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5476 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5477 if (I.getNumArgOperands() != 2)
5480 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5481 if (!Arg0->getType()->isPointerTy() ||
5482 !Arg1->getType()->isPointerTy() ||
5483 !I.getType()->isPointerTy())
5486 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5487 std::pair<SDValue, SDValue> Res =
5488 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5489 getValue(Arg0), getValue(Arg1),
5490 MachinePointerInfo(Arg0),
5491 MachinePointerInfo(Arg1), isStpcpy);
5492 if (Res.first.getNode()) {
5493 setValue(&I, Res.first);
5494 DAG.setRoot(Res.second);
5501 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5502 /// If so, return true and lower it, otherwise return false and it will be
5503 /// lowered like a normal call.
5504 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5505 // Verify that the prototype makes sense. int strcmp(void*,void*)
5506 if (I.getNumArgOperands() != 2)
5509 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5510 if (!Arg0->getType()->isPointerTy() ||
5511 !Arg1->getType()->isPointerTy() ||
5512 !I.getType()->isIntegerTy())
5515 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5516 std::pair<SDValue, SDValue> Res =
5517 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5518 getValue(Arg0), getValue(Arg1),
5519 MachinePointerInfo(Arg0),
5520 MachinePointerInfo(Arg1));
5521 if (Res.first.getNode()) {
5522 processIntegerCallValue(I, Res.first, true);
5523 PendingLoads.push_back(Res.second);
5530 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5531 /// form. If so, return true and lower it, otherwise return false and it
5532 /// will be lowered like a normal call.
5533 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5534 // Verify that the prototype makes sense. size_t strlen(char *)
5535 if (I.getNumArgOperands() != 1)
5538 const Value *Arg0 = I.getArgOperand(0);
5539 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5542 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5543 std::pair<SDValue, SDValue> Res =
5544 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5545 getValue(Arg0), MachinePointerInfo(Arg0));
5546 if (Res.first.getNode()) {
5547 processIntegerCallValue(I, Res.first, false);
5548 PendingLoads.push_back(Res.second);
5555 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5556 /// form. If so, return true and lower it, otherwise return false and it
5557 /// will be lowered like a normal call.
5558 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5559 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5560 if (I.getNumArgOperands() != 2)
5563 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5564 if (!Arg0->getType()->isPointerTy() ||
5565 !Arg1->getType()->isIntegerTy() ||
5566 !I.getType()->isIntegerTy())
5569 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5570 std::pair<SDValue, SDValue> Res =
5571 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5572 getValue(Arg0), getValue(Arg1),
5573 MachinePointerInfo(Arg0));
5574 if (Res.first.getNode()) {
5575 processIntegerCallValue(I, Res.first, false);
5576 PendingLoads.push_back(Res.second);
5583 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5584 /// operation (as expected), translate it to an SDNode with the specified opcode
5585 /// and return true.
5586 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5588 // Sanity check that it really is a unary floating-point call.
5589 if (I.getNumArgOperands() != 1 ||
5590 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5591 I.getType() != I.getArgOperand(0)->getType() ||
5592 !I.onlyReadsMemory())
5595 SDValue Tmp = getValue(I.getArgOperand(0));
5596 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5600 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5601 /// operation (as expected), translate it to an SDNode with the specified opcode
5602 /// and return true.
5603 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5605 // Sanity check that it really is a binary floating-point call.
5606 if (I.getNumArgOperands() != 2 ||
5607 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5608 I.getType() != I.getArgOperand(0)->getType() ||
5609 I.getType() != I.getArgOperand(1)->getType() ||
5610 !I.onlyReadsMemory())
5613 SDValue Tmp0 = getValue(I.getArgOperand(0));
5614 SDValue Tmp1 = getValue(I.getArgOperand(1));
5615 EVT VT = Tmp0.getValueType();
5616 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5620 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5621 // Handle inline assembly differently.
5622 if (isa<InlineAsm>(I.getCalledValue())) {
5627 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5628 ComputeUsesVAFloatArgument(I, &MMI);
5630 const char *RenameFn = nullptr;
5631 if (Function *F = I.getCalledFunction()) {
5632 if (F->isDeclaration()) {
5633 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5634 if (unsigned IID = II->getIntrinsicID(F)) {
5635 RenameFn = visitIntrinsicCall(I, IID);
5640 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5641 RenameFn = visitIntrinsicCall(I, IID);
5647 // Check for well-known libc/libm calls. If the function is internal, it
5648 // can't be a library call.
5650 if (!F->hasLocalLinkage() && F->hasName() &&
5651 LibInfo->getLibFunc(F->getName(), Func) &&
5652 LibInfo->hasOptimizedCodeGen(Func)) {
5655 case LibFunc::copysign:
5656 case LibFunc::copysignf:
5657 case LibFunc::copysignl:
5658 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5659 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5660 I.getType() == I.getArgOperand(0)->getType() &&
5661 I.getType() == I.getArgOperand(1)->getType() &&
5662 I.onlyReadsMemory()) {
5663 SDValue LHS = getValue(I.getArgOperand(0));
5664 SDValue RHS = getValue(I.getArgOperand(1));
5665 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5666 LHS.getValueType(), LHS, RHS));
5671 case LibFunc::fabsf:
5672 case LibFunc::fabsl:
5673 if (visitUnaryFloatCall(I, ISD::FABS))
5677 case LibFunc::fminf:
5678 case LibFunc::fminl:
5679 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5683 case LibFunc::fmaxf:
5684 case LibFunc::fmaxl:
5685 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5691 if (visitUnaryFloatCall(I, ISD::FSIN))
5697 if (visitUnaryFloatCall(I, ISD::FCOS))
5701 case LibFunc::sqrtf:
5702 case LibFunc::sqrtl:
5703 case LibFunc::sqrt_finite:
5704 case LibFunc::sqrtf_finite:
5705 case LibFunc::sqrtl_finite:
5706 if (visitUnaryFloatCall(I, ISD::FSQRT))
5709 case LibFunc::floor:
5710 case LibFunc::floorf:
5711 case LibFunc::floorl:
5712 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5715 case LibFunc::nearbyint:
5716 case LibFunc::nearbyintf:
5717 case LibFunc::nearbyintl:
5718 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5722 case LibFunc::ceilf:
5723 case LibFunc::ceill:
5724 if (visitUnaryFloatCall(I, ISD::FCEIL))
5728 case LibFunc::rintf:
5729 case LibFunc::rintl:
5730 if (visitUnaryFloatCall(I, ISD::FRINT))
5733 case LibFunc::round:
5734 case LibFunc::roundf:
5735 case LibFunc::roundl:
5736 if (visitUnaryFloatCall(I, ISD::FROUND))
5739 case LibFunc::trunc:
5740 case LibFunc::truncf:
5741 case LibFunc::truncl:
5742 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5746 case LibFunc::log2f:
5747 case LibFunc::log2l:
5748 if (visitUnaryFloatCall(I, ISD::FLOG2))
5752 case LibFunc::exp2f:
5753 case LibFunc::exp2l:
5754 if (visitUnaryFloatCall(I, ISD::FEXP2))
5757 case LibFunc::memcmp:
5758 if (visitMemCmpCall(I))
5761 case LibFunc::memchr:
5762 if (visitMemChrCall(I))
5765 case LibFunc::strcpy:
5766 if (visitStrCpyCall(I, false))
5769 case LibFunc::stpcpy:
5770 if (visitStrCpyCall(I, true))
5773 case LibFunc::strcmp:
5774 if (visitStrCmpCall(I))
5777 case LibFunc::strlen:
5778 if (visitStrLenCall(I))
5781 case LibFunc::strnlen:
5782 if (visitStrNLenCall(I))
5791 Callee = getValue(I.getCalledValue());
5793 Callee = DAG.getExternalSymbol(
5795 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5797 // Check if we can potentially perform a tail call. More detailed checking is
5798 // be done within LowerCallTo, after more information about the call is known.
5799 LowerCallTo(&I, Callee, I.isTailCall());
5804 /// AsmOperandInfo - This contains information for each constraint that we are
5806 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5808 /// CallOperand - If this is the result output operand or a clobber
5809 /// this is null, otherwise it is the incoming operand to the CallInst.
5810 /// This gets modified as the asm is processed.
5811 SDValue CallOperand;
5813 /// AssignedRegs - If this is a register or register class operand, this
5814 /// contains the set of register corresponding to the operand.
5815 RegsForValue AssignedRegs;
5817 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5818 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5821 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5822 /// corresponds to. If there is no Value* for this operand, it returns
5824 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5825 const DataLayout &DL) const {
5826 if (!CallOperandVal) return MVT::Other;
5828 if (isa<BasicBlock>(CallOperandVal))
5829 return TLI.getPointerTy(DL);
5831 llvm::Type *OpTy = CallOperandVal->getType();
5833 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5834 // If this is an indirect operand, the operand is a pointer to the
5837 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5839 report_fatal_error("Indirect operand for inline asm not a pointer!");
5840 OpTy = PtrTy->getElementType();
5843 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5844 if (StructType *STy = dyn_cast<StructType>(OpTy))
5845 if (STy->getNumElements() == 1)
5846 OpTy = STy->getElementType(0);
5848 // If OpTy is not a single value, it may be a struct/union that we
5849 // can tile with integers.
5850 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5851 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5860 OpTy = IntegerType::get(Context, BitSize);
5865 return TLI.getValueType(DL, OpTy, true);
5869 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5871 } // end anonymous namespace
5873 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5874 /// specified operand. We prefer to assign virtual registers, to allow the
5875 /// register allocator to handle the assignment process. However, if the asm
5876 /// uses features that we can't model on machineinstrs, we have SDISel do the
5877 /// allocation. This produces generally horrible, but correct, code.
5879 /// OpInfo describes the operand.
5881 static void GetRegistersForValue(SelectionDAG &DAG,
5882 const TargetLowering &TLI,
5884 SDISelAsmOperandInfo &OpInfo) {
5885 LLVMContext &Context = *DAG.getContext();
5887 MachineFunction &MF = DAG.getMachineFunction();
5888 SmallVector<unsigned, 4> Regs;
5890 // If this is a constraint for a single physreg, or a constraint for a
5891 // register class, find it.
5892 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5893 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5894 OpInfo.ConstraintCode,
5895 OpInfo.ConstraintVT);
5897 unsigned NumRegs = 1;
5898 if (OpInfo.ConstraintVT != MVT::Other) {
5899 // If this is a FP input in an integer register (or visa versa) insert a bit
5900 // cast of the input value. More generally, handle any case where the input
5901 // value disagrees with the register class we plan to stick this in.
5902 if (OpInfo.Type == InlineAsm::isInput &&
5903 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5904 // Try to convert to the first EVT that the reg class contains. If the
5905 // types are identical size, use a bitcast to convert (e.g. two differing
5907 MVT RegVT = *PhysReg.second->vt_begin();
5908 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5909 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5910 RegVT, OpInfo.CallOperand);
5911 OpInfo.ConstraintVT = RegVT;
5912 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5913 // If the input is a FP value and we want it in FP registers, do a
5914 // bitcast to the corresponding integer type. This turns an f64 value
5915 // into i64, which can be passed with two i32 values on a 32-bit
5917 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5918 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5919 RegVT, OpInfo.CallOperand);
5920 OpInfo.ConstraintVT = RegVT;
5924 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5928 EVT ValueVT = OpInfo.ConstraintVT;
5930 // If this is a constraint for a specific physical register, like {r17},
5932 if (unsigned AssignedReg = PhysReg.first) {
5933 const TargetRegisterClass *RC = PhysReg.second;
5934 if (OpInfo.ConstraintVT == MVT::Other)
5935 ValueVT = *RC->vt_begin();
5937 // Get the actual register value type. This is important, because the user
5938 // may have asked for (e.g.) the AX register in i32 type. We need to
5939 // remember that AX is actually i16 to get the right extension.
5940 RegVT = *RC->vt_begin();
5942 // This is a explicit reference to a physical register.
5943 Regs.push_back(AssignedReg);
5945 // If this is an expanded reference, add the rest of the regs to Regs.
5947 TargetRegisterClass::iterator I = RC->begin();
5948 for (; *I != AssignedReg; ++I)
5949 assert(I != RC->end() && "Didn't find reg!");
5951 // Already added the first reg.
5953 for (; NumRegs; --NumRegs, ++I) {
5954 assert(I != RC->end() && "Ran out of registers to allocate!");
5959 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5963 // Otherwise, if this was a reference to an LLVM register class, create vregs
5964 // for this reference.
5965 if (const TargetRegisterClass *RC = PhysReg.second) {
5966 RegVT = *RC->vt_begin();
5967 if (OpInfo.ConstraintVT == MVT::Other)
5970 // Create the appropriate number of virtual registers.
5971 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5972 for (; NumRegs; --NumRegs)
5973 Regs.push_back(RegInfo.createVirtualRegister(RC));
5975 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5979 // Otherwise, we couldn't allocate enough registers for this.
5982 /// visitInlineAsm - Handle a call to an InlineAsm object.
5984 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5985 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5987 /// ConstraintOperands - Information about all of the constraints.
5988 SDISelAsmOperandInfoVector ConstraintOperands;
5990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5991 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5992 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5994 bool hasMemory = false;
5996 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5997 unsigned ResNo = 0; // ResNo - The result number of the next output.
5998 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5999 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6000 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6002 MVT OpVT = MVT::Other;
6004 // Compute the value type for each operand.
6005 switch (OpInfo.Type) {
6006 case InlineAsm::isOutput:
6007 // Indirect outputs just consume an argument.
6008 if (OpInfo.isIndirect) {
6009 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6013 // The return value of the call is this value. As such, there is no
6014 // corresponding argument.
6015 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6016 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6017 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6018 STy->getElementType(ResNo));
6020 assert(ResNo == 0 && "Asm only has one result!");
6021 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6025 case InlineAsm::isInput:
6026 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6028 case InlineAsm::isClobber:
6033 // If this is an input or an indirect output, process the call argument.
6034 // BasicBlocks are labels, currently appearing only in asm's.
6035 if (OpInfo.CallOperandVal) {
6036 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6037 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6039 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6042 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6043 DAG.getDataLayout()).getSimpleVT();
6046 OpInfo.ConstraintVT = OpVT;
6048 // Indirect operand accesses access memory.
6049 if (OpInfo.isIndirect)
6052 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6053 TargetLowering::ConstraintType
6054 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6055 if (CType == TargetLowering::C_Memory) {
6063 SDValue Chain, Flag;
6065 // We won't need to flush pending loads if this asm doesn't touch
6066 // memory and is nonvolatile.
6067 if (hasMemory || IA->hasSideEffects())
6070 Chain = DAG.getRoot();
6072 // Second pass over the constraints: compute which constraint option to use
6073 // and assign registers to constraints that want a specific physreg.
6074 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6075 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6077 // If this is an output operand with a matching input operand, look up the
6078 // matching input. If their types mismatch, e.g. one is an integer, the
6079 // other is floating point, or their sizes are different, flag it as an
6081 if (OpInfo.hasMatchingInput()) {
6082 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6084 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6085 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6086 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6087 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6088 OpInfo.ConstraintVT);
6089 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6090 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6091 Input.ConstraintVT);
6092 if ((OpInfo.ConstraintVT.isInteger() !=
6093 Input.ConstraintVT.isInteger()) ||
6094 (MatchRC.second != InputRC.second)) {
6095 report_fatal_error("Unsupported asm: input constraint"
6096 " with a matching output constraint of"
6097 " incompatible type!");
6099 Input.ConstraintVT = OpInfo.ConstraintVT;
6103 // Compute the constraint code and ConstraintType to use.
6104 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6106 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6107 OpInfo.Type == InlineAsm::isClobber)
6110 // If this is a memory input, and if the operand is not indirect, do what we
6111 // need to to provide an address for the memory input.
6112 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6113 !OpInfo.isIndirect) {
6114 assert((OpInfo.isMultipleAlternative ||
6115 (OpInfo.Type == InlineAsm::isInput)) &&
6116 "Can only indirectify direct input operands!");
6118 // Memory operands really want the address of the value. If we don't have
6119 // an indirect input, put it in the constpool if we can, otherwise spill
6120 // it to a stack slot.
6121 // TODO: This isn't quite right. We need to handle these according to
6122 // the addressing mode that the constraint wants. Also, this may take
6123 // an additional register for the computation and we don't want that
6126 // If the operand is a float, integer, or vector constant, spill to a
6127 // constant pool entry to get its address.
6128 const Value *OpVal = OpInfo.CallOperandVal;
6129 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6130 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6131 OpInfo.CallOperand = DAG.getConstantPool(
6132 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6134 // Otherwise, create a stack slot and emit a store to it before the
6136 Type *Ty = OpVal->getType();
6137 auto &DL = DAG.getDataLayout();
6138 uint64_t TySize = DL.getTypeAllocSize(Ty);
6139 unsigned Align = DL.getPrefTypeAlignment(Ty);
6140 MachineFunction &MF = DAG.getMachineFunction();
6141 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6143 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6144 Chain = DAG.getStore(
6145 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6146 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6148 OpInfo.CallOperand = StackSlot;
6151 // There is no longer a Value* corresponding to this operand.
6152 OpInfo.CallOperandVal = nullptr;
6154 // It is now an indirect operand.
6155 OpInfo.isIndirect = true;
6158 // If this constraint is for a specific register, allocate it before
6160 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6161 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6164 // Second pass - Loop over all of the operands, assigning virtual or physregs
6165 // to register class operands.
6166 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6167 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6169 // C_Register operands have already been allocated, Other/Memory don't need
6171 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6172 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6175 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6176 std::vector<SDValue> AsmNodeOperands;
6177 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6178 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6179 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6181 // If we have a !srcloc metadata node associated with it, we want to attach
6182 // this to the ultimately generated inline asm machineinstr. To do this, we
6183 // pass in the third operand as this (potentially null) inline asm MDNode.
6184 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6185 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6187 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6188 // bits as operand 3.
6189 unsigned ExtraInfo = 0;
6190 if (IA->hasSideEffects())
6191 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6192 if (IA->isAlignStack())
6193 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6194 // Set the asm dialect.
6195 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6197 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6198 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6199 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6201 // Compute the constraint code and ConstraintType to use.
6202 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6204 // Ideally, we would only check against memory constraints. However, the
6205 // meaning of an other constraint can be target-specific and we can't easily
6206 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6207 // for other constriants as well.
6208 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6209 OpInfo.ConstraintType == TargetLowering::C_Other) {
6210 if (OpInfo.Type == InlineAsm::isInput)
6211 ExtraInfo |= InlineAsm::Extra_MayLoad;
6212 else if (OpInfo.Type == InlineAsm::isOutput)
6213 ExtraInfo |= InlineAsm::Extra_MayStore;
6214 else if (OpInfo.Type == InlineAsm::isClobber)
6215 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6219 AsmNodeOperands.push_back(DAG.getTargetConstant(
6220 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6222 // Loop over all of the inputs, copying the operand values into the
6223 // appropriate registers and processing the output regs.
6224 RegsForValue RetValRegs;
6226 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6227 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6229 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6230 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6232 switch (OpInfo.Type) {
6233 case InlineAsm::isOutput: {
6234 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6235 OpInfo.ConstraintType != TargetLowering::C_Register) {
6236 // Memory output, or 'other' output (e.g. 'X' constraint).
6237 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6239 unsigned ConstraintID =
6240 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6241 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6242 "Failed to convert memory constraint code to constraint id.");
6244 // Add information to the INLINEASM node to know about this output.
6245 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6246 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6247 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6249 AsmNodeOperands.push_back(OpInfo.CallOperand);
6253 // Otherwise, this is a register or register class output.
6255 // Copy the output from the appropriate register. Find a register that
6257 if (OpInfo.AssignedRegs.Regs.empty()) {
6258 LLVMContext &Ctx = *DAG.getContext();
6259 Ctx.emitError(CS.getInstruction(),
6260 "couldn't allocate output register for constraint '" +
6261 Twine(OpInfo.ConstraintCode) + "'");
6265 // If this is an indirect operand, store through the pointer after the
6267 if (OpInfo.isIndirect) {
6268 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6269 OpInfo.CallOperandVal));
6271 // This is the result value of the call.
6272 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6273 // Concatenate this output onto the outputs list.
6274 RetValRegs.append(OpInfo.AssignedRegs);
6277 // Add information to the INLINEASM node to know that this register is
6280 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6281 ? InlineAsm::Kind_RegDefEarlyClobber
6282 : InlineAsm::Kind_RegDef,
6283 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6286 case InlineAsm::isInput: {
6287 SDValue InOperandVal = OpInfo.CallOperand;
6289 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6290 // If this is required to match an output register we have already set,
6291 // just use its register.
6292 unsigned OperandNo = OpInfo.getMatchedOperand();
6294 // Scan until we find the definition we already emitted of this operand.
6295 // When we find it, create a RegsForValue operand.
6296 unsigned CurOp = InlineAsm::Op_FirstOperand;
6297 for (; OperandNo; --OperandNo) {
6298 // Advance to the next operand.
6300 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6301 assert((InlineAsm::isRegDefKind(OpFlag) ||
6302 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6303 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6304 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6308 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6309 if (InlineAsm::isRegDefKind(OpFlag) ||
6310 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6311 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6312 if (OpInfo.isIndirect) {
6313 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6314 LLVMContext &Ctx = *DAG.getContext();
6315 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6316 " don't know how to handle tied "
6317 "indirect register inputs");
6321 RegsForValue MatchedRegs;
6322 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6323 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6324 MatchedRegs.RegVTs.push_back(RegVT);
6325 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6326 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6328 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6329 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6331 LLVMContext &Ctx = *DAG.getContext();
6332 Ctx.emitError(CS.getInstruction(),
6333 "inline asm error: This value"
6334 " type register class is not natively supported!");
6338 SDLoc dl = getCurSDLoc();
6339 // Use the produced MatchedRegs object to
6340 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6341 Chain, &Flag, CS.getInstruction());
6342 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6343 true, OpInfo.getMatchedOperand(), dl,
6344 DAG, AsmNodeOperands);
6348 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6349 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6350 "Unexpected number of operands");
6351 // Add information to the INLINEASM node to know about this input.
6352 // See InlineAsm.h isUseOperandTiedToDef.
6353 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6354 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6355 OpInfo.getMatchedOperand());
6356 AsmNodeOperands.push_back(DAG.getTargetConstant(
6357 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6358 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6362 // Treat indirect 'X' constraint as memory.
6363 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6365 OpInfo.ConstraintType = TargetLowering::C_Memory;
6367 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6368 std::vector<SDValue> Ops;
6369 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6372 LLVMContext &Ctx = *DAG.getContext();
6373 Ctx.emitError(CS.getInstruction(),
6374 "invalid operand for inline asm constraint '" +
6375 Twine(OpInfo.ConstraintCode) + "'");
6379 // Add information to the INLINEASM node to know about this input.
6380 unsigned ResOpType =
6381 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6382 AsmNodeOperands.push_back(DAG.getTargetConstant(
6383 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6384 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6388 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6389 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6390 assert(InOperandVal.getValueType() ==
6391 TLI.getPointerTy(DAG.getDataLayout()) &&
6392 "Memory operands expect pointer values");
6394 unsigned ConstraintID =
6395 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6396 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6397 "Failed to convert memory constraint code to constraint id.");
6399 // Add information to the INLINEASM node to know about this input.
6400 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6401 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6402 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6405 AsmNodeOperands.push_back(InOperandVal);
6409 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6410 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6411 "Unknown constraint type!");
6413 // TODO: Support this.
6414 if (OpInfo.isIndirect) {
6415 LLVMContext &Ctx = *DAG.getContext();
6416 Ctx.emitError(CS.getInstruction(),
6417 "Don't know how to handle indirect register inputs yet "
6418 "for constraint '" +
6419 Twine(OpInfo.ConstraintCode) + "'");
6423 // Copy the input into the appropriate registers.
6424 if (OpInfo.AssignedRegs.Regs.empty()) {
6425 LLVMContext &Ctx = *DAG.getContext();
6426 Ctx.emitError(CS.getInstruction(),
6427 "couldn't allocate input reg for constraint '" +
6428 Twine(OpInfo.ConstraintCode) + "'");
6432 SDLoc dl = getCurSDLoc();
6434 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6435 Chain, &Flag, CS.getInstruction());
6437 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6438 dl, DAG, AsmNodeOperands);
6441 case InlineAsm::isClobber: {
6442 // Add the clobbered value to the operand list, so that the register
6443 // allocator is aware that the physreg got clobbered.
6444 if (!OpInfo.AssignedRegs.Regs.empty())
6445 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6446 false, 0, getCurSDLoc(), DAG,
6453 // Finish up input operands. Set the input chain and add the flag last.
6454 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6455 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6457 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6458 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6459 Flag = Chain.getValue(1);
6461 // If this asm returns a register value, copy the result from that register
6462 // and set it as the value of the call.
6463 if (!RetValRegs.Regs.empty()) {
6464 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6465 Chain, &Flag, CS.getInstruction());
6467 // FIXME: Why don't we do this for inline asms with MRVs?
6468 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6469 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6471 // If any of the results of the inline asm is a vector, it may have the
6472 // wrong width/num elts. This can happen for register classes that can
6473 // contain multiple different value types. The preg or vreg allocated may
6474 // not have the same VT as was expected. Convert it to the right type
6475 // with bit_convert.
6476 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6477 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6480 } else if (ResultType != Val.getValueType() &&
6481 ResultType.isInteger() && Val.getValueType().isInteger()) {
6482 // If a result value was tied to an input value, the computed result may
6483 // have a wider width than the expected result. Extract the relevant
6485 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6488 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6491 setValue(CS.getInstruction(), Val);
6492 // Don't need to use this as a chain in this case.
6493 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6497 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6499 // Process indirect outputs, first output all of the flagged copies out of
6501 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6502 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6503 const Value *Ptr = IndirectStoresToEmit[i].second;
6504 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6506 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6509 // Emit the non-flagged stores from the physregs.
6510 SmallVector<SDValue, 8> OutChains;
6511 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6512 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6513 StoresToEmit[i].first,
6514 getValue(StoresToEmit[i].second),
6515 MachinePointerInfo(StoresToEmit[i].second),
6517 OutChains.push_back(Val);
6520 if (!OutChains.empty())
6521 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6526 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6527 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6528 MVT::Other, getRoot(),
6529 getValue(I.getArgOperand(0)),
6530 DAG.getSrcValue(I.getArgOperand(0))));
6533 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6534 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6535 const DataLayout &DL = DAG.getDataLayout();
6536 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6537 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6538 DAG.getSrcValue(I.getOperand(0)),
6539 DL.getABITypeAlignment(I.getType()));
6541 DAG.setRoot(V.getValue(1));
6544 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6545 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6546 MVT::Other, getRoot(),
6547 getValue(I.getArgOperand(0)),
6548 DAG.getSrcValue(I.getArgOperand(0))));
6551 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6552 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6553 MVT::Other, getRoot(),
6554 getValue(I.getArgOperand(0)),
6555 getValue(I.getArgOperand(1)),
6556 DAG.getSrcValue(I.getArgOperand(0)),
6557 DAG.getSrcValue(I.getArgOperand(1))));
6560 /// \brief Lower an argument list according to the target calling convention.
6562 /// \return A tuple of <return-value, token-chain>
6564 /// This is a helper for lowering intrinsics that follow a target calling
6565 /// convention or require stack pointer adjustment. Only a subset of the
6566 /// intrinsic's operands need to participate in the calling convention.
6567 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6568 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6569 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6570 TargetLowering::ArgListTy Args;
6571 Args.reserve(NumArgs);
6573 // Populate the argument list.
6574 // Attributes for args start at offset 1, after the return attribute.
6575 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6576 ArgI != ArgE; ++ArgI) {
6577 const Value *V = CS->getOperand(ArgI);
6579 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6581 TargetLowering::ArgListEntry Entry;
6582 Entry.Node = getValue(V);
6583 Entry.Ty = V->getType();
6584 Entry.setAttributes(&CS, AttrI);
6585 Args.push_back(Entry);
6588 TargetLowering::CallLoweringInfo CLI(DAG);
6589 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6590 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6591 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6593 return lowerInvokable(CLI, EHPadBB);
6596 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6597 /// or patchpoint target node's operand list.
6599 /// Constants are converted to TargetConstants purely as an optimization to
6600 /// avoid constant materialization and register allocation.
6602 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6603 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6604 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6605 /// address materialization and register allocation, but may also be required
6606 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6607 /// alloca in the entry block, then the runtime may assume that the alloca's
6608 /// StackMap location can be read immediately after compilation and that the
6609 /// location is valid at any point during execution (this is similar to the
6610 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6611 /// only available in a register, then the runtime would need to trap when
6612 /// execution reaches the StackMap in order to read the alloca's location.
6613 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6614 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6615 SelectionDAGBuilder &Builder) {
6616 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6617 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6620 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6622 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6623 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6624 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6625 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6626 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6628 Ops.push_back(OpVal);
6632 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6633 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6634 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6635 // [live variables...])
6637 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6639 SDValue Chain, InFlag, Callee, NullPtr;
6640 SmallVector<SDValue, 32> Ops;
6642 SDLoc DL = getCurSDLoc();
6643 Callee = getValue(CI.getCalledValue());
6644 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6646 // The stackmap intrinsic only records the live variables (the arguemnts
6647 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6648 // intrinsic, this won't be lowered to a function call. This means we don't
6649 // have to worry about calling conventions and target specific lowering code.
6650 // Instead we perform the call lowering right here.
6652 // chain, flag = CALLSEQ_START(chain, 0)
6653 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6654 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6656 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6657 InFlag = Chain.getValue(1);
6659 // Add the <id> and <numBytes> constants.
6660 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6661 Ops.push_back(DAG.getTargetConstant(
6662 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6663 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6664 Ops.push_back(DAG.getTargetConstant(
6665 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6668 // Push live variables for the stack map.
6669 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6671 // We are not pushing any register mask info here on the operands list,
6672 // because the stackmap doesn't clobber anything.
6674 // Push the chain and the glue flag.
6675 Ops.push_back(Chain);
6676 Ops.push_back(InFlag);
6678 // Create the STACKMAP node.
6679 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6680 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6681 Chain = SDValue(SM, 0);
6682 InFlag = Chain.getValue(1);
6684 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6686 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6688 // Set the root to the target-lowered call chain.
6691 // Inform the Frame Information that we have a stackmap in this function.
6692 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6695 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6696 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6697 const BasicBlock *EHPadBB) {
6698 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6703 // [live variables...])
6705 CallingConv::ID CC = CS.getCallingConv();
6706 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6707 bool HasDef = !CS->getType()->isVoidTy();
6708 SDLoc dl = getCurSDLoc();
6709 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6711 // Handle immediate and symbolic callees.
6712 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6713 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6715 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6716 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6717 SDLoc(SymbolicCallee),
6718 SymbolicCallee->getValueType(0));
6720 // Get the real number of arguments participating in the call <numArgs>
6721 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6722 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6724 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6725 // Intrinsics include all meta-operands up to but not including CC.
6726 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6727 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6728 "Not enough arguments provided to the patchpoint intrinsic");
6730 // For AnyRegCC the arguments are lowered later on manually.
6731 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6733 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6734 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6735 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6737 SDNode *CallEnd = Result.second.getNode();
6738 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6739 CallEnd = CallEnd->getOperand(0).getNode();
6741 /// Get a call instruction from the call sequence chain.
6742 /// Tail calls are not allowed.
6743 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6744 "Expected a callseq node.");
6745 SDNode *Call = CallEnd->getOperand(0).getNode();
6746 bool HasGlue = Call->getGluedNode();
6748 // Replace the target specific call node with the patchable intrinsic.
6749 SmallVector<SDValue, 8> Ops;
6751 // Add the <id> and <numBytes> constants.
6752 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6753 Ops.push_back(DAG.getTargetConstant(
6754 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6755 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6756 Ops.push_back(DAG.getTargetConstant(
6757 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6761 Ops.push_back(Callee);
6763 // Adjust <numArgs> to account for any arguments that have been passed on the
6765 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6766 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6767 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6768 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6770 // Add the calling convention
6771 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6773 // Add the arguments we omitted previously. The register allocator should
6774 // place these in any free register.
6776 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6777 Ops.push_back(getValue(CS.getArgument(i)));
6779 // Push the arguments from the call instruction up to the register mask.
6780 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6781 Ops.append(Call->op_begin() + 2, e);
6783 // Push live variables for the stack map.
6784 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6786 // Push the register mask info.
6788 Ops.push_back(*(Call->op_end()-2));
6790 Ops.push_back(*(Call->op_end()-1));
6792 // Push the chain (this is originally the first operand of the call, but
6793 // becomes now the last or second to last operand).
6794 Ops.push_back(*(Call->op_begin()));
6796 // Push the glue flag (last operand).
6798 Ops.push_back(*(Call->op_end()-1));
6801 if (IsAnyRegCC && HasDef) {
6802 // Create the return types based on the intrinsic definition
6803 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6804 SmallVector<EVT, 3> ValueVTs;
6805 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6806 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6808 // There is always a chain and a glue type at the end
6809 ValueVTs.push_back(MVT::Other);
6810 ValueVTs.push_back(MVT::Glue);
6811 NodeTys = DAG.getVTList(ValueVTs);
6813 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6815 // Replace the target specific call node with a PATCHPOINT node.
6816 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6819 // Update the NodeMap.
6822 setValue(CS.getInstruction(), SDValue(MN, 0));
6824 setValue(CS.getInstruction(), Result.first);
6827 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6828 // call sequence. Furthermore the location of the chain and glue can change
6829 // when the AnyReg calling convention is used and the intrinsic returns a
6831 if (IsAnyRegCC && HasDef) {
6832 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6833 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6834 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6836 DAG.ReplaceAllUsesWith(Call, MN);
6837 DAG.DeleteNode(Call);
6839 // Inform the Frame Information that we have a patchpoint in this function.
6840 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6843 /// Returns an AttributeSet representing the attributes applied to the return
6844 /// value of the given call.
6845 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6846 SmallVector<Attribute::AttrKind, 2> Attrs;
6848 Attrs.push_back(Attribute::SExt);
6850 Attrs.push_back(Attribute::ZExt);
6852 Attrs.push_back(Attribute::InReg);
6854 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6858 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6859 /// implementation, which just calls LowerCall.
6860 /// FIXME: When all targets are
6861 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6862 std::pair<SDValue, SDValue>
6863 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6864 // Handle the incoming return values from the call.
6866 Type *OrigRetTy = CLI.RetTy;
6867 SmallVector<EVT, 4> RetTys;
6868 SmallVector<uint64_t, 4> Offsets;
6869 auto &DL = CLI.DAG.getDataLayout();
6870 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6872 SmallVector<ISD::OutputArg, 4> Outs;
6873 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6875 bool CanLowerReturn =
6876 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6877 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6879 SDValue DemoteStackSlot;
6880 int DemoteStackIdx = -100;
6881 if (!CanLowerReturn) {
6882 // FIXME: equivalent assert?
6883 // assert(!CS.hasInAllocaArgument() &&
6884 // "sret demotion is incompatible with inalloca");
6885 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6886 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6887 MachineFunction &MF = CLI.DAG.getMachineFunction();
6888 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6889 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6891 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6893 Entry.Node = DemoteStackSlot;
6894 Entry.Ty = StackSlotPtrType;
6895 Entry.isSExt = false;
6896 Entry.isZExt = false;
6897 Entry.isInReg = false;
6898 Entry.isSRet = true;
6899 Entry.isNest = false;
6900 Entry.isByVal = false;
6901 Entry.isReturned = false;
6902 Entry.Alignment = Align;
6903 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6904 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6906 // sret demotion isn't compatible with tail-calls, since the sret argument
6907 // points into the callers stack frame.
6908 CLI.IsTailCall = false;
6910 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6912 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6913 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6914 for (unsigned i = 0; i != NumRegs; ++i) {
6915 ISD::InputArg MyFlags;
6916 MyFlags.VT = RegisterVT;
6918 MyFlags.Used = CLI.IsReturnValueUsed;
6920 MyFlags.Flags.setSExt();
6922 MyFlags.Flags.setZExt();
6924 MyFlags.Flags.setInReg();
6925 CLI.Ins.push_back(MyFlags);
6930 // Handle all of the outgoing arguments.
6932 CLI.OutVals.clear();
6933 ArgListTy &Args = CLI.getArgs();
6934 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6935 SmallVector<EVT, 4> ValueVTs;
6936 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6937 Type *FinalType = Args[i].Ty;
6938 if (Args[i].isByVal)
6939 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6940 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6941 FinalType, CLI.CallConv, CLI.IsVarArg);
6942 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6944 EVT VT = ValueVTs[Value];
6945 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6946 SDValue Op = SDValue(Args[i].Node.getNode(),
6947 Args[i].Node.getResNo() + Value);
6948 ISD::ArgFlagsTy Flags;
6949 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6955 if (Args[i].isInReg)
6959 if (Args[i].isByVal)
6961 if (Args[i].isInAlloca) {
6962 Flags.setInAlloca();
6963 // Set the byval flag for CCAssignFn callbacks that don't know about
6964 // inalloca. This way we can know how many bytes we should've allocated
6965 // and how many bytes a callee cleanup function will pop. If we port
6966 // inalloca to more targets, we'll have to add custom inalloca handling
6967 // in the various CC lowering callbacks.
6970 if (Args[i].isByVal || Args[i].isInAlloca) {
6971 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6972 Type *ElementTy = Ty->getElementType();
6973 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6974 // For ByVal, alignment should come from FE. BE will guess if this
6975 // info is not there but there are cases it cannot get right.
6976 unsigned FrameAlign;
6977 if (Args[i].Alignment)
6978 FrameAlign = Args[i].Alignment;
6980 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6981 Flags.setByValAlign(FrameAlign);
6986 Flags.setInConsecutiveRegs();
6987 Flags.setOrigAlign(OriginalAlignment);
6989 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6990 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6991 SmallVector<SDValue, 4> Parts(NumParts);
6992 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6995 ExtendKind = ISD::SIGN_EXTEND;
6996 else if (Args[i].isZExt)
6997 ExtendKind = ISD::ZERO_EXTEND;
6999 // Conservatively only handle 'returned' on non-vectors for now
7000 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7001 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7002 "unexpected use of 'returned'");
7003 // Before passing 'returned' to the target lowering code, ensure that
7004 // either the register MVT and the actual EVT are the same size or that
7005 // the return value and argument are extended in the same way; in these
7006 // cases it's safe to pass the argument register value unchanged as the
7007 // return register value (although it's at the target's option whether
7009 // TODO: allow code generation to take advantage of partially preserved
7010 // registers rather than clobbering the entire register when the
7011 // parameter extension method is not compatible with the return
7013 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7014 (ExtendKind != ISD::ANY_EXTEND &&
7015 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7016 Flags.setReturned();
7019 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7020 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7022 for (unsigned j = 0; j != NumParts; ++j) {
7023 // if it isn't first piece, alignment must be 1
7024 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7025 i < CLI.NumFixedArgs,
7026 i, j*Parts[j].getValueType().getStoreSize());
7027 if (NumParts > 1 && j == 0)
7028 MyFlags.Flags.setSplit();
7030 MyFlags.Flags.setOrigAlign(1);
7032 CLI.Outs.push_back(MyFlags);
7033 CLI.OutVals.push_back(Parts[j]);
7036 if (NeedsRegBlock && Value == NumValues - 1)
7037 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7041 SmallVector<SDValue, 4> InVals;
7042 CLI.Chain = LowerCall(CLI, InVals);
7044 // Verify that the target's LowerCall behaved as expected.
7045 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7046 "LowerCall didn't return a valid chain!");
7047 assert((!CLI.IsTailCall || InVals.empty()) &&
7048 "LowerCall emitted a return value for a tail call!");
7049 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7050 "LowerCall didn't emit the correct number of values!");
7052 // For a tail call, the return value is merely live-out and there aren't
7053 // any nodes in the DAG representing it. Return a special value to
7054 // indicate that a tail call has been emitted and no more Instructions
7055 // should be processed in the current block.
7056 if (CLI.IsTailCall) {
7057 CLI.DAG.setRoot(CLI.Chain);
7058 return std::make_pair(SDValue(), SDValue());
7061 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7062 assert(InVals[i].getNode() &&
7063 "LowerCall emitted a null value!");
7064 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7065 "LowerCall emitted a value with the wrong type!");
7068 SmallVector<SDValue, 4> ReturnValues;
7069 if (!CanLowerReturn) {
7070 // The instruction result is the result of loading from the
7071 // hidden sret parameter.
7072 SmallVector<EVT, 1> PVTs;
7073 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7075 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7076 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7077 EVT PtrVT = PVTs[0];
7079 unsigned NumValues = RetTys.size();
7080 ReturnValues.resize(NumValues);
7081 SmallVector<SDValue, 4> Chains(NumValues);
7083 for (unsigned i = 0; i < NumValues; ++i) {
7084 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7085 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7087 SDValue L = CLI.DAG.getLoad(
7088 RetTys[i], CLI.DL, CLI.Chain, Add,
7089 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7090 DemoteStackIdx, Offsets[i]),
7091 false, false, false, 1);
7092 ReturnValues[i] = L;
7093 Chains[i] = L.getValue(1);
7096 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7098 // Collect the legal value parts into potentially illegal values
7099 // that correspond to the original function's return values.
7100 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7102 AssertOp = ISD::AssertSext;
7103 else if (CLI.RetZExt)
7104 AssertOp = ISD::AssertZext;
7105 unsigned CurReg = 0;
7106 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7108 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7109 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7111 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7112 NumRegs, RegisterVT, VT, nullptr,
7117 // For a function returning void, there is no return value. We can't create
7118 // such a node, so we just return a null return value in that case. In
7119 // that case, nothing will actually look at the value.
7120 if (ReturnValues.empty())
7121 return std::make_pair(SDValue(), CLI.Chain);
7124 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7125 CLI.DAG.getVTList(RetTys), ReturnValues);
7126 return std::make_pair(Res, CLI.Chain);
7129 void TargetLowering::LowerOperationWrapper(SDNode *N,
7130 SmallVectorImpl<SDValue> &Results,
7131 SelectionDAG &DAG) const {
7132 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7134 Results.push_back(Res);
7137 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7138 llvm_unreachable("LowerOperation not implemented for this target!");
7142 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7143 SDValue Op = getNonRegisterValue(V);
7144 assert((Op.getOpcode() != ISD::CopyFromReg ||
7145 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7146 "Copy from a reg to the same reg!");
7147 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7149 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7150 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7152 SDValue Chain = DAG.getEntryNode();
7154 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7155 FuncInfo.PreferredExtendType.end())
7157 : FuncInfo.PreferredExtendType[V];
7158 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7159 PendingExports.push_back(Chain);
7162 #include "llvm/CodeGen/SelectionDAGISel.h"
7164 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7165 /// entry block, return true. This includes arguments used by switches, since
7166 /// the switch may expand into multiple basic blocks.
7167 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7168 // With FastISel active, we may be splitting blocks, so force creation
7169 // of virtual registers for all non-dead arguments.
7171 return A->use_empty();
7173 const BasicBlock *Entry = A->getParent()->begin();
7174 for (const User *U : A->users())
7175 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7176 return false; // Use not in entry block.
7181 void SelectionDAGISel::LowerArguments(const Function &F) {
7182 SelectionDAG &DAG = SDB->DAG;
7183 SDLoc dl = SDB->getCurSDLoc();
7184 const DataLayout &DL = DAG.getDataLayout();
7185 SmallVector<ISD::InputArg, 16> Ins;
7187 if (!FuncInfo->CanLowerReturn) {
7188 // Put in an sret pointer parameter before all the other parameters.
7189 SmallVector<EVT, 1> ValueVTs;
7190 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7191 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7193 // NOTE: Assuming that a pointer will never break down to more than one VT
7195 ISD::ArgFlagsTy Flags;
7197 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7198 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7199 ISD::InputArg::NoArgIndex, 0);
7200 Ins.push_back(RetArg);
7203 // Set up the incoming argument description vector.
7205 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7206 I != E; ++I, ++Idx) {
7207 SmallVector<EVT, 4> ValueVTs;
7208 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7209 bool isArgValueUsed = !I->use_empty();
7210 unsigned PartBase = 0;
7211 Type *FinalType = I->getType();
7212 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7213 FinalType = cast<PointerType>(FinalType)->getElementType();
7214 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7215 FinalType, F.getCallingConv(), F.isVarArg());
7216 for (unsigned Value = 0, NumValues = ValueVTs.size();
7217 Value != NumValues; ++Value) {
7218 EVT VT = ValueVTs[Value];
7219 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7220 ISD::ArgFlagsTy Flags;
7221 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7223 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7225 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7227 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7229 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7231 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7233 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7234 Flags.setInAlloca();
7235 // Set the byval flag for CCAssignFn callbacks that don't know about
7236 // inalloca. This way we can know how many bytes we should've allocated
7237 // and how many bytes a callee cleanup function will pop. If we port
7238 // inalloca to more targets, we'll have to add custom inalloca handling
7239 // in the various CC lowering callbacks.
7242 if (Flags.isByVal() || Flags.isInAlloca()) {
7243 PointerType *Ty = cast<PointerType>(I->getType());
7244 Type *ElementTy = Ty->getElementType();
7245 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7246 // For ByVal, alignment should be passed from FE. BE will guess if
7247 // this info is not there but there are cases it cannot get right.
7248 unsigned FrameAlign;
7249 if (F.getParamAlignment(Idx))
7250 FrameAlign = F.getParamAlignment(Idx);
7252 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7253 Flags.setByValAlign(FrameAlign);
7255 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7258 Flags.setInConsecutiveRegs();
7259 Flags.setOrigAlign(OriginalAlignment);
7261 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7262 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7263 for (unsigned i = 0; i != NumRegs; ++i) {
7264 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7265 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7266 if (NumRegs > 1 && i == 0)
7267 MyFlags.Flags.setSplit();
7268 // if it isn't first piece, alignment must be 1
7270 MyFlags.Flags.setOrigAlign(1);
7271 Ins.push_back(MyFlags);
7273 if (NeedsRegBlock && Value == NumValues - 1)
7274 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7275 PartBase += VT.getStoreSize();
7279 // Call the target to set up the argument values.
7280 SmallVector<SDValue, 8> InVals;
7281 SDValue NewRoot = TLI->LowerFormalArguments(
7282 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7284 // Verify that the target's LowerFormalArguments behaved as expected.
7285 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7286 "LowerFormalArguments didn't return a valid chain!");
7287 assert(InVals.size() == Ins.size() &&
7288 "LowerFormalArguments didn't emit the correct number of values!");
7290 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7291 assert(InVals[i].getNode() &&
7292 "LowerFormalArguments emitted a null value!");
7293 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7294 "LowerFormalArguments emitted a value with the wrong type!");
7298 // Update the DAG with the new chain value resulting from argument lowering.
7299 DAG.setRoot(NewRoot);
7301 // Set up the argument values.
7304 if (!FuncInfo->CanLowerReturn) {
7305 // Create a virtual register for the sret pointer, and put in a copy
7306 // from the sret argument into it.
7307 SmallVector<EVT, 1> ValueVTs;
7308 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7309 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7310 MVT VT = ValueVTs[0].getSimpleVT();
7311 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7312 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7313 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7314 RegVT, VT, nullptr, AssertOp);
7316 MachineFunction& MF = SDB->DAG.getMachineFunction();
7317 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7318 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7319 FuncInfo->DemoteRegister = SRetReg;
7321 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7322 DAG.setRoot(NewRoot);
7324 // i indexes lowered arguments. Bump it past the hidden sret argument.
7325 // Idx indexes LLVM arguments. Don't touch it.
7329 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7331 SmallVector<SDValue, 4> ArgValues;
7332 SmallVector<EVT, 4> ValueVTs;
7333 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7334 unsigned NumValues = ValueVTs.size();
7336 // If this argument is unused then remember its value. It is used to generate
7337 // debugging information.
7338 if (I->use_empty() && NumValues) {
7339 SDB->setUnusedArgValue(I, InVals[i]);
7341 // Also remember any frame index for use in FastISel.
7342 if (FrameIndexSDNode *FI =
7343 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7344 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7347 for (unsigned Val = 0; Val != NumValues; ++Val) {
7348 EVT VT = ValueVTs[Val];
7349 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7350 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7352 if (!I->use_empty()) {
7353 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7354 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7355 AssertOp = ISD::AssertSext;
7356 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7357 AssertOp = ISD::AssertZext;
7359 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7360 NumParts, PartVT, VT,
7361 nullptr, AssertOp));
7367 // We don't need to do anything else for unused arguments.
7368 if (ArgValues.empty())
7371 // Note down frame index.
7372 if (FrameIndexSDNode *FI =
7373 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7374 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7376 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7377 SDB->getCurSDLoc());
7379 SDB->setValue(I, Res);
7380 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7381 if (LoadSDNode *LNode =
7382 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7383 if (FrameIndexSDNode *FI =
7384 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7385 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7388 // If this argument is live outside of the entry block, insert a copy from
7389 // wherever we got it to the vreg that other BB's will reference it as.
7390 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7391 // If we can, though, try to skip creating an unnecessary vreg.
7392 // FIXME: This isn't very clean... it would be nice to make this more
7393 // general. It's also subtly incompatible with the hacks FastISel
7395 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7396 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7397 FuncInfo->ValueMap[I] = Reg;
7401 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7402 FuncInfo->InitializeRegForValue(I);
7403 SDB->CopyToExportRegsIfNeeded(I);
7407 assert(i == InVals.size() && "Argument register count mismatch!");
7409 // Finally, if the target has anything special to do, allow it to do so.
7410 EmitFunctionEntryCode();
7413 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7414 /// ensure constants are generated when needed. Remember the virtual registers
7415 /// that need to be added to the Machine PHI nodes as input. We cannot just
7416 /// directly add them, because expansion might result in multiple MBB's for one
7417 /// BB. As such, the start of the BB might correspond to a different MBB than
7421 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7422 const TerminatorInst *TI = LLVMBB->getTerminator();
7424 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7426 // Check PHI nodes in successors that expect a value to be available from this
7428 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7429 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7430 if (!isa<PHINode>(SuccBB->begin())) continue;
7431 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7433 // If this terminator has multiple identical successors (common for
7434 // switches), only handle each succ once.
7435 if (!SuccsHandled.insert(SuccMBB).second)
7438 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7440 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7441 // nodes and Machine PHI nodes, but the incoming operands have not been
7443 for (BasicBlock::const_iterator I = SuccBB->begin();
7444 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7445 // Ignore dead phi's.
7446 if (PN->use_empty()) continue;
7449 if (PN->getType()->isEmptyTy())
7453 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7455 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7456 unsigned &RegOut = ConstantsOut[C];
7458 RegOut = FuncInfo.CreateRegs(C->getType());
7459 CopyValueToVirtualRegister(C, RegOut);
7463 DenseMap<const Value *, unsigned>::iterator I =
7464 FuncInfo.ValueMap.find(PHIOp);
7465 if (I != FuncInfo.ValueMap.end())
7468 assert(isa<AllocaInst>(PHIOp) &&
7469 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7470 "Didn't codegen value into a register!??");
7471 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7472 CopyValueToVirtualRegister(PHIOp, Reg);
7476 // Remember that this register needs to added to the machine PHI node as
7477 // the input for this MBB.
7478 SmallVector<EVT, 4> ValueVTs;
7479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7480 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7481 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7482 EVT VT = ValueVTs[vti];
7483 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7484 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7485 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7486 Reg += NumRegisters;
7491 ConstantsOut.clear();
7494 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7497 SelectionDAGBuilder::StackProtectorDescriptor::
7498 AddSuccessorMBB(const BasicBlock *BB,
7499 MachineBasicBlock *ParentMBB,
7501 MachineBasicBlock *SuccMBB) {
7502 // If SuccBB has not been created yet, create it.
7504 MachineFunction *MF = ParentMBB->getParent();
7505 MachineFunction::iterator BBI = ParentMBB;
7506 SuccMBB = MF->CreateMachineBasicBlock(BB);
7507 MF->insert(++BBI, SuccMBB);
7509 // Add it as a successor of ParentMBB.
7510 ParentMBB->addSuccessor(
7511 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7515 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7516 MachineFunction::iterator I = MBB;
7517 if (++I == FuncInfo.MF->end())
7522 /// During lowering new call nodes can be created (such as memset, etc.).
7523 /// Those will become new roots of the current DAG, but complications arise
7524 /// when they are tail calls. In such cases, the call lowering will update
7525 /// the root, but the builder still needs to know that a tail call has been
7526 /// lowered in order to avoid generating an additional return.
7527 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7528 // If the node is null, we do have a tail call.
7529 if (MaybeTC.getNode() != nullptr)
7530 DAG.setRoot(MaybeTC);
7535 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7536 unsigned *TotalCases, unsigned First,
7538 assert(Last >= First);
7539 assert(TotalCases[Last] >= TotalCases[First]);
7541 APInt LowCase = Clusters[First].Low->getValue();
7542 APInt HighCase = Clusters[Last].High->getValue();
7543 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7545 // FIXME: A range of consecutive cases has 100% density, but only requires one
7546 // comparison to lower. We should discriminate against such consecutive ranges
7549 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7550 uint64_t Range = Diff + 1;
7553 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7555 assert(NumCases < UINT64_MAX / 100);
7556 assert(Range >= NumCases);
7558 return NumCases * 100 >= Range * MinJumpTableDensity;
7561 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7562 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7563 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7566 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7567 unsigned First, unsigned Last,
7568 const SwitchInst *SI,
7569 MachineBasicBlock *DefaultMBB,
7570 CaseCluster &JTCluster) {
7571 assert(First <= Last);
7573 uint32_t Weight = 0;
7574 unsigned NumCmps = 0;
7575 std::vector<MachineBasicBlock*> Table;
7576 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7577 for (unsigned I = First; I <= Last; ++I) {
7578 assert(Clusters[I].Kind == CC_Range);
7579 Weight += Clusters[I].Weight;
7580 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7581 APInt Low = Clusters[I].Low->getValue();
7582 APInt High = Clusters[I].High->getValue();
7583 NumCmps += (Low == High) ? 1 : 2;
7585 // Fill the gap between this and the previous cluster.
7586 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7587 assert(PreviousHigh.slt(Low));
7588 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7589 for (uint64_t J = 0; J < Gap; J++)
7590 Table.push_back(DefaultMBB);
7592 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7593 for (uint64_t J = 0; J < ClusterSize; ++J)
7594 Table.push_back(Clusters[I].MBB);
7595 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7598 unsigned NumDests = JTWeights.size();
7599 if (isSuitableForBitTests(NumDests, NumCmps,
7600 Clusters[First].Low->getValue(),
7601 Clusters[Last].High->getValue())) {
7602 // Clusters[First..Last] should be lowered as bit tests instead.
7606 // Create the MBB that will load from and jump through the table.
7607 // Note: We create it here, but it's not inserted into the function yet.
7608 MachineFunction *CurMF = FuncInfo.MF;
7609 MachineBasicBlock *JumpTableMBB =
7610 CurMF->CreateMachineBasicBlock(SI->getParent());
7612 // Add successors. Note: use table order for determinism.
7613 SmallPtrSet<MachineBasicBlock *, 8> Done;
7614 for (MachineBasicBlock *Succ : Table) {
7615 if (Done.count(Succ))
7617 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7621 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7622 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7623 ->createJumpTableIndex(Table);
7625 // Set up the jump table info.
7626 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7627 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7628 Clusters[Last].High->getValue(), SI->getCondition(),
7630 JTCases.emplace_back(std::move(JTH), std::move(JT));
7632 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7633 JTCases.size() - 1, Weight);
7637 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7638 const SwitchInst *SI,
7639 MachineBasicBlock *DefaultMBB) {
7641 // Clusters must be non-empty, sorted, and only contain Range clusters.
7642 assert(!Clusters.empty());
7643 for (CaseCluster &C : Clusters)
7644 assert(C.Kind == CC_Range);
7645 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7646 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7650 if (!areJTsAllowed(TLI))
7653 const int64_t N = Clusters.size();
7654 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7656 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7657 SmallVector<unsigned, 8> TotalCases(N);
7659 for (unsigned i = 0; i < N; ++i) {
7660 APInt Hi = Clusters[i].High->getValue();
7661 APInt Lo = Clusters[i].Low->getValue();
7662 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7664 TotalCases[i] += TotalCases[i - 1];
7667 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7668 // Cheap case: the whole range might be suitable for jump table.
7669 CaseCluster JTCluster;
7670 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7671 Clusters[0] = JTCluster;
7677 // The algorithm below is not suitable for -O0.
7678 if (TM.getOptLevel() == CodeGenOpt::None)
7681 // Split Clusters into minimum number of dense partitions. The algorithm uses
7682 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7683 // for the Case Statement'" (1994), but builds the MinPartitions array in
7684 // reverse order to make it easier to reconstruct the partitions in ascending
7685 // order. In the choice between two optimal partitionings, it picks the one
7686 // which yields more jump tables.
7688 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7689 SmallVector<unsigned, 8> MinPartitions(N);
7690 // LastElement[i] is the last element of the partition starting at i.
7691 SmallVector<unsigned, 8> LastElement(N);
7692 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7693 SmallVector<unsigned, 8> NumTables(N);
7695 // Base case: There is only one way to partition Clusters[N-1].
7696 MinPartitions[N - 1] = 1;
7697 LastElement[N - 1] = N - 1;
7698 assert(MinJumpTableSize > 1);
7699 NumTables[N - 1] = 0;
7701 // Note: loop indexes are signed to avoid underflow.
7702 for (int64_t i = N - 2; i >= 0; i--) {
7703 // Find optimal partitioning of Clusters[i..N-1].
7704 // Baseline: Put Clusters[i] into a partition on its own.
7705 MinPartitions[i] = MinPartitions[i + 1] + 1;
7707 NumTables[i] = NumTables[i + 1];
7709 // Search for a solution that results in fewer partitions.
7710 for (int64_t j = N - 1; j > i; j--) {
7711 // Try building a partition from Clusters[i..j].
7712 if (isDense(Clusters, &TotalCases[0], i, j)) {
7713 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7714 bool IsTable = j - i + 1 >= MinJumpTableSize;
7715 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7717 // If this j leads to fewer partitions, or same number of partitions
7718 // with more lookup tables, it is a better partitioning.
7719 if (NumPartitions < MinPartitions[i] ||
7720 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7721 MinPartitions[i] = NumPartitions;
7723 NumTables[i] = Tables;
7729 // Iterate over the partitions, replacing some with jump tables in-place.
7730 unsigned DstIndex = 0;
7731 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7732 Last = LastElement[First];
7733 assert(Last >= First);
7734 assert(DstIndex <= First);
7735 unsigned NumClusters = Last - First + 1;
7737 CaseCluster JTCluster;
7738 if (NumClusters >= MinJumpTableSize &&
7739 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7740 Clusters[DstIndex++] = JTCluster;
7742 for (unsigned I = First; I <= Last; ++I)
7743 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7746 Clusters.resize(DstIndex);
7749 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7750 // FIXME: Using the pointer type doesn't seem ideal.
7751 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7752 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7756 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7759 const APInt &High) {
7760 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7761 // range of cases both require only one branch to lower. Just looking at the
7762 // number of clusters and destinations should be enough to decide whether to
7765 // To lower a range with bit tests, the range must fit the bitwidth of a
7767 if (!rangeFitsInWord(Low, High))
7770 // Decide whether it's profitable to lower this range with bit tests. Each
7771 // destination requires a bit test and branch, and there is an overall range
7772 // check branch. For a small number of clusters, separate comparisons might be
7773 // cheaper, and for many destinations, splitting the range might be better.
7774 return (NumDests == 1 && NumCmps >= 3) ||
7775 (NumDests == 2 && NumCmps >= 5) ||
7776 (NumDests == 3 && NumCmps >= 6);
7779 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7780 unsigned First, unsigned Last,
7781 const SwitchInst *SI,
7782 CaseCluster &BTCluster) {
7783 assert(First <= Last);
7787 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7788 unsigned NumCmps = 0;
7789 for (int64_t I = First; I <= Last; ++I) {
7790 assert(Clusters[I].Kind == CC_Range);
7791 Dests.set(Clusters[I].MBB->getNumber());
7792 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7794 unsigned NumDests = Dests.count();
7796 APInt Low = Clusters[First].Low->getValue();
7797 APInt High = Clusters[Last].High->getValue();
7798 assert(Low.slt(High));
7800 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7806 const int BitWidth = DAG.getTargetLoweringInfo()
7807 .getPointerTy(DAG.getDataLayout())
7809 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7811 // Check if the clusters cover a contiguous range such that no value in the
7812 // range will jump to the default statement.
7813 bool ContiguousRange = true;
7814 for (int64_t I = First + 1; I <= Last; ++I) {
7815 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7816 ContiguousRange = false;
7821 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7822 // Optimize the case where all the case values fit in a word without having
7823 // to subtract minValue. In this case, we can optimize away the subtraction.
7824 LowBound = APInt::getNullValue(Low.getBitWidth());
7826 ContiguousRange = false;
7829 CmpRange = High - Low;
7833 uint32_t TotalWeight = 0;
7834 for (unsigned i = First; i <= Last; ++i) {
7835 // Find the CaseBits for this destination.
7837 for (j = 0; j < CBV.size(); ++j)
7838 if (CBV[j].BB == Clusters[i].MBB)
7840 if (j == CBV.size())
7841 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7842 CaseBits *CB = &CBV[j];
7844 // Update Mask, Bits and ExtraWeight.
7845 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7846 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7847 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7848 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7849 CB->Bits += Hi - Lo + 1;
7850 CB->ExtraWeight += Clusters[i].Weight;
7851 TotalWeight += Clusters[i].Weight;
7852 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7856 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7857 // Sort by weight first, number of bits second.
7858 if (a.ExtraWeight != b.ExtraWeight)
7859 return a.ExtraWeight > b.ExtraWeight;
7860 return a.Bits > b.Bits;
7863 for (auto &CB : CBV) {
7864 MachineBasicBlock *BitTestBB =
7865 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7866 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7868 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7869 SI->getCondition(), -1U, MVT::Other, false,
7870 ContiguousRange, nullptr, nullptr, std::move(BTI),
7873 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7874 BitTestCases.size() - 1, TotalWeight);
7878 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7879 const SwitchInst *SI) {
7880 // Partition Clusters into as few subsets as possible, where each subset has a
7881 // range that fits in a machine word and has <= 3 unique destinations.
7884 // Clusters must be sorted and contain Range or JumpTable clusters.
7885 assert(!Clusters.empty());
7886 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7887 for (const CaseCluster &C : Clusters)
7888 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7889 for (unsigned i = 1; i < Clusters.size(); ++i)
7890 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7893 // The algorithm below is not suitable for -O0.
7894 if (TM.getOptLevel() == CodeGenOpt::None)
7897 // If target does not have legal shift left, do not emit bit tests at all.
7898 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7899 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7900 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7903 int BitWidth = PTy.getSizeInBits();
7904 const int64_t N = Clusters.size();
7906 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7907 SmallVector<unsigned, 8> MinPartitions(N);
7908 // LastElement[i] is the last element of the partition starting at i.
7909 SmallVector<unsigned, 8> LastElement(N);
7911 // FIXME: This might not be the best algorithm for finding bit test clusters.
7913 // Base case: There is only one way to partition Clusters[N-1].
7914 MinPartitions[N - 1] = 1;
7915 LastElement[N - 1] = N - 1;
7917 // Note: loop indexes are signed to avoid underflow.
7918 for (int64_t i = N - 2; i >= 0; --i) {
7919 // Find optimal partitioning of Clusters[i..N-1].
7920 // Baseline: Put Clusters[i] into a partition on its own.
7921 MinPartitions[i] = MinPartitions[i + 1] + 1;
7924 // Search for a solution that results in fewer partitions.
7925 // Note: the search is limited by BitWidth, reducing time complexity.
7926 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7927 // Try building a partition from Clusters[i..j].
7930 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7931 Clusters[j].High->getValue()))
7934 // Check nbr of destinations and cluster types.
7935 // FIXME: This works, but doesn't seem very efficient.
7936 bool RangesOnly = true;
7937 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7938 for (int64_t k = i; k <= j; k++) {
7939 if (Clusters[k].Kind != CC_Range) {
7943 Dests.set(Clusters[k].MBB->getNumber());
7945 if (!RangesOnly || Dests.count() > 3)
7948 // Check if it's a better partition.
7949 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7950 if (NumPartitions < MinPartitions[i]) {
7951 // Found a better partition.
7952 MinPartitions[i] = NumPartitions;
7958 // Iterate over the partitions, replacing with bit-test clusters in-place.
7959 unsigned DstIndex = 0;
7960 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7961 Last = LastElement[First];
7962 assert(First <= Last);
7963 assert(DstIndex <= First);
7965 CaseCluster BitTestCluster;
7966 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7967 Clusters[DstIndex++] = BitTestCluster;
7969 size_t NumClusters = Last - First + 1;
7970 std::memmove(&Clusters[DstIndex], &Clusters[First],
7971 sizeof(Clusters[0]) * NumClusters);
7972 DstIndex += NumClusters;
7975 Clusters.resize(DstIndex);
7978 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7979 MachineBasicBlock *SwitchMBB,
7980 MachineBasicBlock *DefaultMBB) {
7981 MachineFunction *CurMF = FuncInfo.MF;
7982 MachineBasicBlock *NextMBB = nullptr;
7983 MachineFunction::iterator BBI = W.MBB;
7984 if (++BBI != FuncInfo.MF->end())
7987 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7989 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7991 if (Size == 2 && W.MBB == SwitchMBB) {
7992 // If any two of the cases has the same destination, and if one value
7993 // is the same as the other, but has one bit unset that the other has set,
7994 // use bit manipulation to do two compares at once. For example:
7995 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7996 // TODO: This could be extended to merge any 2 cases in switches with 3
7998 // TODO: Handle cases where W.CaseBB != SwitchBB.
7999 CaseCluster &Small = *W.FirstCluster;
8000 CaseCluster &Big = *W.LastCluster;
8002 if (Small.Low == Small.High && Big.Low == Big.High &&
8003 Small.MBB == Big.MBB) {
8004 const APInt &SmallValue = Small.Low->getValue();
8005 const APInt &BigValue = Big.Low->getValue();
8007 // Check that there is only one bit different.
8008 APInt CommonBit = BigValue ^ SmallValue;
8009 if (CommonBit.isPowerOf2()) {
8010 SDValue CondLHS = getValue(Cond);
8011 EVT VT = CondLHS.getValueType();
8012 SDLoc DL = getCurSDLoc();
8014 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8015 DAG.getConstant(CommonBit, DL, VT));
8016 SDValue Cond = DAG.getSetCC(
8017 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8020 // Update successor info.
8021 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8022 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8023 addSuccessorWithWeight(
8024 SwitchMBB, DefaultMBB,
8025 // The default destination is the first successor in IR.
8026 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8029 // Insert the true branch.
8031 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8032 DAG.getBasicBlock(Small.MBB));
8033 // Insert the false branch.
8034 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8035 DAG.getBasicBlock(DefaultMBB));
8037 DAG.setRoot(BrCond);
8043 if (TM.getOptLevel() != CodeGenOpt::None) {
8044 // Order cases by weight so the most likely case will be checked first.
8045 std::sort(W.FirstCluster, W.LastCluster + 1,
8046 [](const CaseCluster &a, const CaseCluster &b) {
8047 return a.Weight > b.Weight;
8050 // Rearrange the case blocks so that the last one falls through if possible
8051 // without without changing the order of weights.
8052 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8054 if (I->Weight > W.LastCluster->Weight)
8056 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8057 std::swap(*I, *W.LastCluster);
8063 // Compute total weight.
8064 uint32_t DefaultWeight = W.DefaultWeight;
8065 uint32_t UnhandledWeights = DefaultWeight;
8066 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8067 UnhandledWeights += I->Weight;
8068 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8071 MachineBasicBlock *CurMBB = W.MBB;
8072 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8073 MachineBasicBlock *Fallthrough;
8074 if (I == W.LastCluster) {
8075 // For the last cluster, fall through to the default destination.
8076 Fallthrough = DefaultMBB;
8078 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8079 CurMF->insert(BBI, Fallthrough);
8080 // Put Cond in a virtual register to make it available from the new blocks.
8081 ExportFromCurrentBlock(Cond);
8083 UnhandledWeights -= I->Weight;
8086 case CC_JumpTable: {
8087 // FIXME: Optimize away range check based on pivot comparisons.
8088 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8089 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8091 // The jump block hasn't been inserted yet; insert it here.
8092 MachineBasicBlock *JumpMBB = JT->MBB;
8093 CurMF->insert(BBI, JumpMBB);
8095 uint32_t JumpWeight = I->Weight;
8096 uint32_t FallthroughWeight = UnhandledWeights;
8098 // If Fallthrough is a target of the jump table, we evenly distribute
8099 // the weight on the edge to Fallthrough to successors of CurMBB.
8100 // Also update the weight on the edge from JumpMBB to Fallthrough.
8101 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8102 SE = JumpMBB->succ_end();
8104 if (*SI == Fallthrough) {
8105 JumpWeight += DefaultWeight / 2;
8106 FallthroughWeight -= DefaultWeight / 2;
8107 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8112 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8113 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8115 // The jump table header will be inserted in our current block, do the
8116 // range check, and fall through to our fallthrough block.
8117 JTH->HeaderBB = CurMBB;
8118 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8120 // If we're in the right place, emit the jump table header right now.
8121 if (CurMBB == SwitchMBB) {
8122 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8123 JTH->Emitted = true;
8128 // FIXME: Optimize away range check based on pivot comparisons.
8129 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8131 // The bit test blocks haven't been inserted yet; insert them here.
8132 for (BitTestCase &BTC : BTB->Cases)
8133 CurMF->insert(BBI, BTC.ThisBB);
8135 // Fill in fields of the BitTestBlock.
8136 BTB->Parent = CurMBB;
8137 BTB->Default = Fallthrough;
8139 BTB->DefaultWeight = UnhandledWeights;
8140 // If the cases in bit test don't form a contiguous range, we evenly
8141 // distribute the weight on the edge to Fallthrough to two successors
8143 if (!BTB->ContiguousRange) {
8144 BTB->Weight += DefaultWeight / 2;
8145 BTB->DefaultWeight -= DefaultWeight / 2;
8148 // If we're in the right place, emit the bit test header right now.
8149 if (CurMBB == SwitchMBB) {
8150 visitBitTestHeader(*BTB, SwitchMBB);
8151 BTB->Emitted = true;
8156 const Value *RHS, *LHS, *MHS;
8158 if (I->Low == I->High) {
8159 // Check Cond == I->Low.
8165 // Check I->Low <= Cond <= I->High.
8172 // The false weight is the sum of all unhandled cases.
8173 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8176 if (CurMBB == SwitchMBB)
8177 visitSwitchCase(CB, SwitchMBB);
8179 SwitchCases.push_back(CB);
8184 CurMBB = Fallthrough;
8188 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8189 CaseClusterIt First,
8190 CaseClusterIt Last) {
8191 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8192 if (X.Weight != CC.Weight)
8193 return X.Weight > CC.Weight;
8195 // Ties are broken by comparing the case value.
8196 return X.Low->getValue().slt(CC.Low->getValue());
8200 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8201 const SwitchWorkListItem &W,
8203 MachineBasicBlock *SwitchMBB) {
8204 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8205 "Clusters not sorted?");
8207 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8209 // Balance the tree based on branch weights to create a near-optimal (in terms
8210 // of search time given key frequency) binary search tree. See e.g. Kurt
8211 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8212 CaseClusterIt LastLeft = W.FirstCluster;
8213 CaseClusterIt FirstRight = W.LastCluster;
8214 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8215 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8217 // Move LastLeft and FirstRight towards each other from opposite directions to
8218 // find a partitioning of the clusters which balances the weight on both
8219 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8220 // taken to ensure 0-weight nodes are distributed evenly.
8222 while (LastLeft + 1 < FirstRight) {
8223 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8224 LeftWeight += (++LastLeft)->Weight;
8226 RightWeight += (--FirstRight)->Weight;
8231 // Our binary search tree differs from a typical BST in that ours can have up
8232 // to three values in each leaf. The pivot selection above doesn't take that
8233 // into account, which means the tree might require more nodes and be less
8234 // efficient. We compensate for this here.
8236 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8237 unsigned NumRight = W.LastCluster - FirstRight + 1;
8239 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8240 // If one side has less than 3 clusters, and the other has more than 3,
8241 // consider taking a cluster from the other side.
8243 if (NumLeft < NumRight) {
8244 // Consider moving the first cluster on the right to the left side.
8245 CaseCluster &CC = *FirstRight;
8246 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8247 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8248 if (LeftSideRank <= RightSideRank) {
8249 // Moving the cluster to the left does not demote it.
8255 assert(NumRight < NumLeft);
8256 // Consider moving the last element on the left to the right side.
8257 CaseCluster &CC = *LastLeft;
8258 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8259 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8260 if (RightSideRank <= LeftSideRank) {
8261 // Moving the cluster to the right does not demot it.
8271 assert(LastLeft + 1 == FirstRight);
8272 assert(LastLeft >= W.FirstCluster);
8273 assert(FirstRight <= W.LastCluster);
8275 // Use the first element on the right as pivot since we will make less-than
8276 // comparisons against it.
8277 CaseClusterIt PivotCluster = FirstRight;
8278 assert(PivotCluster > W.FirstCluster);
8279 assert(PivotCluster <= W.LastCluster);
8281 CaseClusterIt FirstLeft = W.FirstCluster;
8282 CaseClusterIt LastRight = W.LastCluster;
8284 const ConstantInt *Pivot = PivotCluster->Low;
8286 // New blocks will be inserted immediately after the current one.
8287 MachineFunction::iterator BBI = W.MBB;
8290 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8291 // we can branch to its destination directly if it's squeezed exactly in
8292 // between the known lower bound and Pivot - 1.
8293 MachineBasicBlock *LeftMBB;
8294 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8295 FirstLeft->Low == W.GE &&
8296 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8297 LeftMBB = FirstLeft->MBB;
8299 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8300 FuncInfo.MF->insert(BBI, LeftMBB);
8302 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8303 // Put Cond in a virtual register to make it available from the new blocks.
8304 ExportFromCurrentBlock(Cond);
8307 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8308 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8309 // directly if RHS.High equals the current upper bound.
8310 MachineBasicBlock *RightMBB;
8311 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8312 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8313 RightMBB = FirstRight->MBB;
8315 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8316 FuncInfo.MF->insert(BBI, RightMBB);
8318 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8319 // Put Cond in a virtual register to make it available from the new blocks.
8320 ExportFromCurrentBlock(Cond);
8323 // Create the CaseBlock record that will be used to lower the branch.
8324 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8325 LeftWeight, RightWeight);
8327 if (W.MBB == SwitchMBB)
8328 visitSwitchCase(CB, SwitchMBB);
8330 SwitchCases.push_back(CB);
8333 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8334 // Extract cases from the switch.
8335 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8336 CaseClusterVector Clusters;
8337 Clusters.reserve(SI.getNumCases());
8338 for (auto I : SI.cases()) {
8339 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8340 const ConstantInt *CaseVal = I.getCaseValue();
8342 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8343 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8346 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8348 // Cluster adjacent cases with the same destination. We do this at all
8349 // optimization levels because it's cheap to do and will make codegen faster
8350 // if there are many clusters.
8351 sortAndRangeify(Clusters);
8353 if (TM.getOptLevel() != CodeGenOpt::None) {
8354 // Replace an unreachable default with the most popular destination.
8355 // FIXME: Exploit unreachable default more aggressively.
8356 bool UnreachableDefault =
8357 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8358 if (UnreachableDefault && !Clusters.empty()) {
8359 DenseMap<const BasicBlock *, unsigned> Popularity;
8360 unsigned MaxPop = 0;
8361 const BasicBlock *MaxBB = nullptr;
8362 for (auto I : SI.cases()) {
8363 const BasicBlock *BB = I.getCaseSuccessor();
8364 if (++Popularity[BB] > MaxPop) {
8365 MaxPop = Popularity[BB];
8370 assert(MaxPop > 0 && MaxBB);
8371 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8373 // Remove cases that were pointing to the destination that is now the
8375 CaseClusterVector New;
8376 New.reserve(Clusters.size());
8377 for (CaseCluster &CC : Clusters) {
8378 if (CC.MBB != DefaultMBB)
8381 Clusters = std::move(New);
8385 // If there is only the default destination, jump there directly.
8386 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8387 if (Clusters.empty()) {
8388 SwitchMBB->addSuccessor(DefaultMBB);
8389 if (DefaultMBB != NextBlock(SwitchMBB)) {
8390 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8391 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8396 findJumpTables(Clusters, &SI, DefaultMBB);
8397 findBitTestClusters(Clusters, &SI);
8400 dbgs() << "Case clusters: ";
8401 for (const CaseCluster &C : Clusters) {
8402 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8403 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8405 C.Low->getValue().print(dbgs(), true);
8406 if (C.Low != C.High) {
8408 C.High->getValue().print(dbgs(), true);
8415 assert(!Clusters.empty());
8416 SwitchWorkList WorkList;
8417 CaseClusterIt First = Clusters.begin();
8418 CaseClusterIt Last = Clusters.end() - 1;
8419 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8420 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8422 while (!WorkList.empty()) {
8423 SwitchWorkListItem W = WorkList.back();
8424 WorkList.pop_back();
8425 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8427 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8428 // For optimized builds, lower large range as a balanced binary tree.
8429 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8433 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);