1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuilder.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/Optional.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/ValueTracking.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/DebugInfo.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/InlineAsm.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/IntrinsicInst.h"
47 #include "llvm/IR/Intrinsics.h"
48 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/IR/Module.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetFrameLowering.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetIntrinsicInfo.h"
58 #include "llvm/Target/TargetLibraryInfo.h"
59 #include "llvm/Target/TargetLowering.h"
60 #include "llvm/Target/TargetOptions.h"
61 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 /// LimitFloatPrecision - Generate low-precision inline sequences for
66 /// some float libcalls (6, 8 or 12 bits).
67 static unsigned LimitFloatPrecision;
69 static cl::opt<unsigned, true>
70 LimitFPPrecision("limit-float-precision",
71 cl::desc("Generate low-precision inline sequences "
72 "for some float libcalls"),
73 cl::location(LimitFloatPrecision),
76 // Limit the width of DAG chains. This is important in general to prevent
77 // prevent DAG-based analysis from blowing up. For example, alias analysis and
78 // load clustering may not complete in reasonable time. It is difficult to
79 // recognize and avoid this situation within each individual analysis, and
80 // future analyses are likely to have the same behavior. Limiting DAG width is
81 // the safe approach, and will be especially important with global DAGs.
83 // MaxParallelChains default is arbitrarily high to avoid affecting
84 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
85 // sequence over this should have been converted to llvm.memcpy by the
86 // frontend. It easy to induce this behavior with .ll code such as:
87 // %buffer = alloca [4096 x i8]
88 // %data = load [4096 x i8]* %argPtr
89 // store [4096 x i8] %data, [4096 x i8]* %buffer
90 static const unsigned MaxParallelChains = 64;
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
93 const SDValue *Parts, unsigned NumParts,
94 MVT PartVT, EVT ValueVT, const Value *V);
96 /// getCopyFromParts - Create a value that contains the specified legal parts
97 /// combined into the value they represent. If the parts combine to a type
98 /// larger then ValueVT then AssertOp can be used to specify whether the extra
99 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
100 /// (ISD::AssertSext).
101 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts,
103 unsigned NumParts, MVT PartVT, EVT ValueVT,
105 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
106 if (ValueVT.isVector())
107 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
110 assert(NumParts > 0 && "No parts to assemble!");
111 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
112 SDValue Val = Parts[0];
115 // Assemble the value from multiple parts.
116 if (ValueVT.isInteger()) {
117 unsigned PartBits = PartVT.getSizeInBits();
118 unsigned ValueBits = ValueVT.getSizeInBits();
120 // Assemble the power of 2 part.
121 unsigned RoundParts = NumParts & (NumParts - 1) ?
122 1 << Log2_32(NumParts) : NumParts;
123 unsigned RoundBits = PartBits * RoundParts;
124 EVT RoundVT = RoundBits == ValueBits ?
125 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
128 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
130 if (RoundParts > 2) {
131 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
133 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
134 RoundParts / 2, PartVT, HalfVT, V);
136 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
137 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
140 if (TLI.isBigEndian())
143 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
145 if (RoundParts < NumParts) {
146 // Assemble the trailing non-power-of-2 part.
147 unsigned OddParts = NumParts - RoundParts;
148 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
149 Hi = getCopyFromParts(DAG, DL,
150 Parts + RoundParts, OddParts, PartVT, OddVT, V);
152 // Combine the round and odd parts.
154 if (TLI.isBigEndian())
156 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
157 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
158 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
159 DAG.getConstant(Lo.getValueType().getSizeInBits(),
160 TLI.getPointerTy()));
161 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
162 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
164 } else if (PartVT.isFloatingPoint()) {
165 // FP split into multiple FP parts (for ppcf128)
166 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
171 if (TLI.isBigEndian())
173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
175 // FP split into integer parts (soft fp)
176 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
177 !PartVT.isVector() && "Unexpected split");
178 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
179 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
183 // There is now one part, held in Val. Correct it to match ValueVT.
184 EVT PartEVT = Val.getValueType();
186 if (PartEVT == ValueVT)
189 if (PartEVT.isInteger() && ValueVT.isInteger()) {
190 if (ValueVT.bitsLT(PartEVT)) {
191 // For a truncate, see if we have any information to
192 // indicate whether the truncated bits will always be
193 // zero or sign-extension.
194 if (AssertOp != ISD::DELETED_NODE)
195 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
196 DAG.getValueType(ValueVT));
197 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
199 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
202 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
203 // FP_ROUND's are always exact here.
204 if (ValueVT.bitsLT(Val.getValueType()))
205 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
206 DAG.getTargetConstant(1, TLI.getPointerTy()));
208 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
211 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
212 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
214 llvm_unreachable("Unknown mismatch!");
217 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
218 const Twine &ErrMsg) {
219 const Instruction *I = dyn_cast_or_null<Instruction>(V);
221 return Ctx.emitError(ErrMsg);
223 const char *AsmError = ", possible invalid constraint for vector type";
224 if (const CallInst *CI = dyn_cast<CallInst>(I))
225 if (isa<InlineAsm>(CI->getCalledValue()))
226 return Ctx.emitError(I, ErrMsg + AsmError);
228 return Ctx.emitError(I, ErrMsg);
231 /// getCopyFromPartsVector - Create a value that contains the specified legal
232 /// parts combined into the value they represent. If the parts combine to a
233 /// type larger then ValueVT then AssertOp can be used to specify whether the
234 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
235 /// ValueVT (ISD::AssertSext).
236 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
237 const SDValue *Parts, unsigned NumParts,
238 MVT PartVT, EVT ValueVT, const Value *V) {
239 assert(ValueVT.isVector() && "Not a vector value");
240 assert(NumParts > 0 && "No parts to assemble!");
241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
242 SDValue Val = Parts[0];
244 // Handle a multi-element vector.
248 unsigned NumIntermediates;
250 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
251 NumIntermediates, RegisterVT);
252 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
253 NumParts = NumRegs; // Silence a compiler warning.
254 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
255 assert(RegisterVT == Parts[0].getSimpleValueType() &&
256 "Part type doesn't match part!");
258 // Assemble the parts into intermediate operands.
259 SmallVector<SDValue, 8> Ops(NumIntermediates);
260 if (NumIntermediates == NumParts) {
261 // If the register was not expanded, truncate or copy the value,
263 for (unsigned i = 0; i != NumParts; ++i)
264 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
265 PartVT, IntermediateVT, V);
266 } else if (NumParts > 0) {
267 // If the intermediate type was expanded, build the intermediate
268 // operands from the parts.
269 assert(NumParts % NumIntermediates == 0 &&
270 "Must expand into a divisible number of parts!");
271 unsigned Factor = NumParts / NumIntermediates;
272 for (unsigned i = 0; i != NumIntermediates; ++i)
273 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
274 PartVT, IntermediateVT, V);
277 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
278 // intermediate operands.
279 Val = DAG.getNode(IntermediateVT.isVector() ?
280 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
281 ValueVT, &Ops[0], NumIntermediates);
284 // There is now one part, held in Val. Correct it to match ValueVT.
285 EVT PartEVT = Val.getValueType();
287 if (PartEVT == ValueVT)
290 if (PartEVT.isVector()) {
291 // If the element type of the source/dest vectors are the same, but the
292 // parts vector has more elements than the value vector, then we have a
293 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
295 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
296 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
297 "Cannot narrow, it would be a lossy transformation");
298 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
299 DAG.getConstant(0, TLI.getVectorIdxTy()));
302 // Vector/Vector bitcast.
303 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
306 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
307 "Cannot handle this kind of promotion");
308 // Promoted vector extract
309 bool Smaller = ValueVT.bitsLE(PartEVT);
310 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
315 // Trivial bitcast if the types are the same size and the destination
316 // vector type is legal.
317 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
318 TLI.isTypeLegal(ValueVT))
319 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
321 // Handle cases such as i8 -> <1 x i1>
322 if (ValueVT.getVectorNumElements() != 1) {
323 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
324 "non-trivial scalar-to-vector conversion");
325 return DAG.getUNDEF(ValueVT);
328 if (ValueVT.getVectorNumElements() == 1 &&
329 ValueVT.getVectorElementType() != PartEVT) {
330 bool Smaller = ValueVT.bitsLE(PartEVT);
331 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
332 DL, ValueVT.getScalarType(), Val);
335 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
338 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
339 SDValue Val, SDValue *Parts, unsigned NumParts,
340 MVT PartVT, const Value *V);
342 /// getCopyToParts - Create a series of nodes that contain the specified value
343 /// split into legal parts. If the parts contain more bits than Val, then, for
344 /// integers, ExtendKind can be used to specify how to generate the extra bits.
345 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
346 SDValue Val, SDValue *Parts, unsigned NumParts,
347 MVT PartVT, const Value *V,
348 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
349 EVT ValueVT = Val.getValueType();
351 // Handle the vector case separately.
352 if (ValueVT.isVector())
353 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
356 unsigned PartBits = PartVT.getSizeInBits();
357 unsigned OrigNumParts = NumParts;
358 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
363 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
364 EVT PartEVT = PartVT;
365 if (PartEVT == ValueVT) {
366 assert(NumParts == 1 && "No-op copy with multiple parts!");
371 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
372 // If the parts cover more bits than the value has, promote the value.
373 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
374 assert(NumParts == 1 && "Do not know what to promote to!");
375 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
377 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
378 ValueVT.isInteger() &&
379 "Unknown mismatch!");
380 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
381 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
382 if (PartVT == MVT::x86mmx)
383 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
385 } else if (PartBits == ValueVT.getSizeInBits()) {
386 // Different types of the same size.
387 assert(NumParts == 1 && PartEVT != ValueVT);
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
389 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
390 // If the parts cover less bits than value has, truncate the value.
391 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
392 ValueVT.isInteger() &&
393 "Unknown mismatch!");
394 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
395 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
396 if (PartVT == MVT::x86mmx)
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
400 // The value may have changed - recompute ValueVT.
401 ValueVT = Val.getValueType();
402 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
403 "Failed to tile the value with PartVT!");
406 if (PartEVT != ValueVT)
407 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
408 "scalar-to-vector conversion failed");
414 // Expand the value into multiple parts.
415 if (NumParts & (NumParts - 1)) {
416 // The number of parts is not a power of 2. Split off and copy the tail.
417 assert(PartVT.isInteger() && ValueVT.isInteger() &&
418 "Do not know what to expand to!");
419 unsigned RoundParts = 1 << Log2_32(NumParts);
420 unsigned RoundBits = RoundParts * PartBits;
421 unsigned OddParts = NumParts - RoundParts;
422 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
423 DAG.getIntPtrConstant(RoundBits));
424 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
426 if (TLI.isBigEndian())
427 // The odd parts were reversed by getCopyToParts - unreverse them.
428 std::reverse(Parts + RoundParts, Parts + NumParts);
430 NumParts = RoundParts;
431 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
432 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
435 // The number of parts is a power of 2. Repeatedly bisect the value using
437 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
438 EVT::getIntegerVT(*DAG.getContext(),
439 ValueVT.getSizeInBits()),
442 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
443 for (unsigned i = 0; i < NumParts; i += StepSize) {
444 unsigned ThisBits = StepSize * PartBits / 2;
445 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
446 SDValue &Part0 = Parts[i];
447 SDValue &Part1 = Parts[i+StepSize/2];
449 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
450 ThisVT, Part0, DAG.getIntPtrConstant(1));
451 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(0));
454 if (ThisBits == PartBits && ThisVT != PartVT) {
455 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
456 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
461 if (TLI.isBigEndian())
462 std::reverse(Parts, Parts + OrigNumParts);
466 /// getCopyToPartsVector - Create a series of nodes that contain the specified
467 /// value split into legal parts.
468 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
469 SDValue Val, SDValue *Parts, unsigned NumParts,
470 MVT PartVT, const Value *V) {
471 EVT ValueVT = Val.getValueType();
472 assert(ValueVT.isVector() && "Not a vector");
473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
476 EVT PartEVT = PartVT;
477 if (PartEVT == ValueVT) {
479 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
480 // Bitconvert vector->vector case.
481 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
482 } else if (PartVT.isVector() &&
483 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
484 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
485 EVT ElementVT = PartVT.getVectorElementType();
486 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
488 SmallVector<SDValue, 16> Ops;
489 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
490 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
491 ElementVT, Val, DAG.getConstant(i,
492 TLI.getVectorIdxTy())));
494 for (unsigned i = ValueVT.getVectorNumElements(),
495 e = PartVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getUNDEF(ElementVT));
498 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
500 // FIXME: Use CONCAT for 2x -> 4x.
502 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
503 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
504 } else if (PartVT.isVector() &&
505 PartEVT.getVectorElementType().bitsGE(
506 ValueVT.getVectorElementType()) &&
507 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509 // Promoted vector extract
510 bool Smaller = PartEVT.bitsLE(ValueVT);
511 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
514 // Vector -> scalar conversion.
515 assert(ValueVT.getVectorNumElements() == 1 &&
516 "Only trivial vector-to-scalar conversions should get here!");
517 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
518 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
520 bool Smaller = ValueVT.bitsLE(PartVT);
521 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
529 // Handle a multi-element vector.
532 unsigned NumIntermediates;
533 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535 NumIntermediates, RegisterVT);
536 unsigned NumElements = ValueVT.getVectorNumElements();
538 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
539 NumParts = NumRegs; // Silence a compiler warning.
540 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542 // Split the vector into intermediate operands.
543 SmallVector<SDValue, 8> Ops(NumIntermediates);
544 for (unsigned i = 0; i != NumIntermediates; ++i) {
545 if (IntermediateVT.isVector())
546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548 DAG.getConstant(i * (NumElements / NumIntermediates),
549 TLI.getVectorIdxTy()));
551 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
553 DAG.getConstant(i, TLI.getVectorIdxTy()));
556 // Split the intermediate operands into legal parts.
557 if (NumParts == NumIntermediates) {
558 // If the register was not expanded, promote or copy the value,
560 for (unsigned i = 0; i != NumParts; ++i)
561 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
562 } else if (NumParts > 0) {
563 // If the intermediate type was expanded, split each the value into
565 assert(NumParts % NumIntermediates == 0 &&
566 "Must expand into a divisible number of parts!");
567 unsigned Factor = NumParts / NumIntermediates;
568 for (unsigned i = 0; i != NumIntermediates; ++i)
569 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
574 /// RegsForValue - This struct represents the registers (physical or virtual)
575 /// that a particular set of values is assigned, and the type information
576 /// about the value. The most common situation is to represent one value at a
577 /// time, but struct or array values are handled element-wise as multiple
578 /// values. The splitting of aggregates is performed recursively, so that we
579 /// never have aggregate-typed registers. The values at this point do not
580 /// necessarily have legal types, so each value may require one or more
581 /// registers of some legal type.
583 struct RegsForValue {
584 /// ValueVTs - The value types of the values, which may not be legal, and
585 /// may need be promoted or synthesized from one or more registers.
587 SmallVector<EVT, 4> ValueVTs;
589 /// RegVTs - The value types of the registers. This is the same size as
590 /// ValueVTs and it records, for each value, what the type of the assigned
591 /// register or registers are. (Individual values are never synthesized
592 /// from more than one type of register.)
594 /// With virtual registers, the contents of RegVTs is redundant with TLI's
595 /// getRegisterType member function, however when with physical registers
596 /// it is necessary to have a separate record of the types.
598 SmallVector<MVT, 4> RegVTs;
600 /// Regs - This list holds the registers assigned to the values.
601 /// Each legal or promoted value requires one register, and each
602 /// expanded value requires multiple registers.
604 SmallVector<unsigned, 4> Regs;
608 RegsForValue(const SmallVector<unsigned, 4> ®s,
609 MVT regvt, EVT valuevt)
610 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
612 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
613 unsigned Reg, Type *Ty) {
614 ComputeValueVTs(tli, Ty, ValueVTs);
616 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
617 EVT ValueVT = ValueVTs[Value];
618 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
619 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
620 for (unsigned i = 0; i != NumRegs; ++i)
621 Regs.push_back(Reg + i);
622 RegVTs.push_back(RegisterVT);
627 /// append - Add the specified values to this one.
628 void append(const RegsForValue &RHS) {
629 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
630 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
631 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
634 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
635 /// this value and returns the result as a ValueVTs value. This uses
636 /// Chain/Flag as the input and updates them for the output Chain/Flag.
637 /// If the Flag pointer is NULL, no flag is used.
638 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
640 SDValue &Chain, SDValue *Flag,
641 const Value *V = nullptr) const;
643 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
644 /// specified value into the registers specified by this object. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
648 SDValue &Chain, SDValue *Flag, const Value *V) const;
650 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
651 /// operand list. This adds the code marker, matching input operand index
652 /// (if applicable), and includes the number of values added into it.
653 void AddInlineAsmOperands(unsigned Kind,
654 bool HasMatching, unsigned MatchingIdx,
656 std::vector<SDValue> &Ops) const;
660 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
661 /// this value and returns the result as a ValueVT value. This uses
662 /// Chain/Flag as the input and updates them for the output Chain/Flag.
663 /// If the Flag pointer is NULL, no flag is used.
664 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
665 FunctionLoweringInfo &FuncInfo,
667 SDValue &Chain, SDValue *Flag,
668 const Value *V) const {
669 // A Value with type {} or [0 x %t] needs no registers.
670 if (ValueVTs.empty())
673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
675 // Assemble the legal parts into the final values.
676 SmallVector<SDValue, 4> Values(ValueVTs.size());
677 SmallVector<SDValue, 8> Parts;
678 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
679 // Copy the legal parts from the registers.
680 EVT ValueVT = ValueVTs[Value];
681 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
682 MVT RegisterVT = RegVTs[Value];
684 Parts.resize(NumRegs);
685 for (unsigned i = 0; i != NumRegs; ++i) {
688 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
690 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
691 *Flag = P.getValue(2);
694 Chain = P.getValue(1);
697 // If the source register was virtual and if we know something about it,
698 // add an assert node.
699 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
700 !RegisterVT.isInteger() || RegisterVT.isVector())
703 const FunctionLoweringInfo::LiveOutInfo *LOI =
704 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
708 unsigned RegSize = RegisterVT.getSizeInBits();
709 unsigned NumSignBits = LOI->NumSignBits;
710 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
712 if (NumZeroBits == RegSize) {
713 // The current value is a zero.
714 // Explicitly express that as it would be easier for
715 // optimizations to kick in.
716 Parts[i] = DAG.getConstant(0, RegisterVT);
720 // FIXME: We capture more information than the dag can represent. For
721 // now, just use the tightest assertzext/assertsext possible.
723 EVT FromVT(MVT::Other);
724 if (NumSignBits == RegSize)
725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
726 else if (NumZeroBits >= RegSize-1)
727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
728 else if (NumSignBits > RegSize-8)
729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
730 else if (NumZeroBits >= RegSize-8)
731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
732 else if (NumSignBits > RegSize-16)
733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
734 else if (NumZeroBits >= RegSize-16)
735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
736 else if (NumSignBits > RegSize-32)
737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
738 else if (NumZeroBits >= RegSize-32)
739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
743 // Add an assertion node.
744 assert(FromVT != MVT::Other);
745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
746 RegisterVT, P, DAG.getValueType(FromVT));
749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
750 NumRegs, RegisterVT, ValueVT, V);
755 return DAG.getNode(ISD::MERGE_VALUES, dl,
756 DAG.getVTList(ValueVTs),
757 &Values[0], ValueVTs.size());
760 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
761 /// specified value into the registers specified by this object. This uses
762 /// Chain/Flag as the input and updates them for the output Chain/Flag.
763 /// If the Flag pointer is NULL, no flag is used.
764 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
765 SDValue &Chain, SDValue *Flag,
766 const Value *V) const {
767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
769 // Get the list of the values's legal parts.
770 unsigned NumRegs = Regs.size();
771 SmallVector<SDValue, 8> Parts(NumRegs);
772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
773 EVT ValueVT = ValueVTs[Value];
774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
775 MVT RegisterVT = RegVTs[Value];
776 ISD::NodeType ExtendKind =
777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
784 // Copy the parts into the registers.
785 SmallVector<SDValue, 8> Chains(NumRegs);
786 for (unsigned i = 0; i != NumRegs; ++i) {
789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
792 *Flag = Part.getValue(1);
795 Chains[i] = Part.getValue(0);
798 if (NumRegs == 1 || Flag)
799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
800 // flagged to it. That is the CopyToReg nodes and the user are considered
801 // a single scheduling unit. If we create a TokenFactor and return it as
802 // chain, then the TokenFactor is both a predecessor (operand) of the
803 // user as well as a successor (the TF operands are flagged to the user).
804 // c1, f1 = CopyToReg
805 // c2, f2 = CopyToReg
806 // c3 = TokenFactor c1, c2
809 Chain = Chains[NumRegs-1];
811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
814 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
815 /// operand list. This adds the code marker and includes the number of
816 /// values added into it.
817 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
818 unsigned MatchingIdx,
820 std::vector<SDValue> &Ops) const {
821 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
826 else if (!Regs.empty() &&
827 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
828 // Put the register class of the virtual registers in the flag word. That
829 // way, later passes can recompute register class constraints for inline
830 // assembly as well as normal instructions.
831 // Don't do this for tied operands that can use the regclass information
833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
841 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
842 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
843 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
844 MVT RegisterVT = RegVTs[Value];
845 for (unsigned i = 0; i != NumRegs; ++i) {
846 assert(Reg < Regs.size() && "Mismatch in # registers expected");
847 unsigned TheReg = Regs[Reg++];
848 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
850 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
851 // If we clobbered the stack pointer, MFI should know about it.
852 assert(DAG.getMachineFunction().getFrameInfo()->
853 hasInlineAsmWithSPAdjust());
859 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
860 const TargetLibraryInfo *li) {
864 DL = DAG.getTarget().getDataLayout();
865 Context = DAG.getContext();
866 LPadToCallSiteMap.clear();
869 /// clear - Clear out the current SelectionDAG and the associated
870 /// state and prepare this SelectionDAGBuilder object to be used
871 /// for a new block. This doesn't clear out information about
872 /// additional blocks that are needed to complete switch lowering
873 /// or PHI node updating; that information is cleared out as it is
875 void SelectionDAGBuilder::clear() {
877 UnusedArgNodeMap.clear();
878 PendingLoads.clear();
879 PendingExports.clear();
882 SDNodeOrder = LowestSDNodeOrder;
885 /// clearDanglingDebugInfo - Clear the dangling debug information
886 /// map. This function is separated from the clear so that debug
887 /// information that is dangling in a basic block can be properly
888 /// resolved in a different basic block. This allows the
889 /// SelectionDAG to resolve dangling debug information attached
891 void SelectionDAGBuilder::clearDanglingDebugInfo() {
892 DanglingDebugInfoMap.clear();
895 /// getRoot - Return the current virtual root of the Selection DAG,
896 /// flushing any PendingLoad items. This must be done before emitting
897 /// a store or any other node that may need to be ordered after any
898 /// prior load instructions.
900 SDValue SelectionDAGBuilder::getRoot() {
901 if (PendingLoads.empty())
902 return DAG.getRoot();
904 if (PendingLoads.size() == 1) {
905 SDValue Root = PendingLoads[0];
907 PendingLoads.clear();
911 // Otherwise, we have to make a token factor node.
912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
913 &PendingLoads[0], PendingLoads.size());
914 PendingLoads.clear();
919 /// getControlRoot - Similar to getRoot, but instead of flushing all the
920 /// PendingLoad items, flush all the PendingExports items. It is necessary
921 /// to do this before emitting a terminator instruction.
923 SDValue SelectionDAGBuilder::getControlRoot() {
924 SDValue Root = DAG.getRoot();
926 if (PendingExports.empty())
929 // Turn all of the CopyToReg chains into one factored node.
930 if (Root.getOpcode() != ISD::EntryToken) {
931 unsigned i = 0, e = PendingExports.size();
932 for (; i != e; ++i) {
933 assert(PendingExports[i].getNode()->getNumOperands() > 1);
934 if (PendingExports[i].getNode()->getOperand(0) == Root)
935 break; // Don't add the root if we already indirectly depend on it.
939 PendingExports.push_back(Root);
942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
944 PendingExports.size());
945 PendingExports.clear();
950 void SelectionDAGBuilder::visit(const Instruction &I) {
951 // Set up outgoing PHI node register values before emitting the terminator.
952 if (isa<TerminatorInst>(&I))
953 HandlePHINodesInSuccessorBlocks(I.getParent());
959 visit(I.getOpcode(), I);
961 if (!isa<TerminatorInst>(&I) && !HasTailCall)
962 CopyToExportRegsIfNeeded(&I);
967 void SelectionDAGBuilder::visitPHI(const PHINode &) {
968 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
971 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
972 // Note: this doesn't use InstVisitor, because it has to work with
973 // ConstantExpr's in addition to instructions.
975 default: llvm_unreachable("Unknown instruction type encountered!");
976 // Build the switch statement using the Instruction.def file.
977 #define HANDLE_INST(NUM, OPCODE, CLASS) \
978 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
979 #include "llvm/IR/Instruction.def"
983 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
984 // generate the debug data structures now that we've seen its definition.
985 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
987 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
989 const DbgValueInst *DI = DDI.getDI();
990 DebugLoc dl = DDI.getdl();
991 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
992 MDNode *Variable = DI->getVariable();
993 uint64_t Offset = DI->getOffset();
996 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
997 SDV = DAG.getDbgValue(Variable, Val.getNode(),
998 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
999 DAG.AddDbgValue(SDV, Val.getNode(), false);
1002 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1003 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1007 /// getValue - Return an SDValue for the given Value.
1008 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1009 // If we already have an SDValue for this value, use it. It's important
1010 // to do this first, so that we don't create a CopyFromReg if we already
1011 // have a regular SDValue.
1012 SDValue &N = NodeMap[V];
1013 if (N.getNode()) return N;
1015 // If there's a virtual register allocated and initialized for this
1017 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1018 if (It != FuncInfo.ValueMap.end()) {
1019 unsigned InReg = It->second;
1020 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1021 InReg, V->getType());
1022 SDValue Chain = DAG.getEntryNode();
1023 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1024 resolveDanglingDebugInfo(V, N);
1028 // Otherwise create a new SDValue and remember it.
1029 SDValue Val = getValueImpl(V);
1031 resolveDanglingDebugInfo(V, Val);
1035 /// getNonRegisterValue - Return an SDValue for the given Value, but
1036 /// don't look in FuncInfo.ValueMap for a virtual register.
1037 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1038 // If we already have an SDValue for this value, use it.
1039 SDValue &N = NodeMap[V];
1040 if (N.getNode()) return N;
1042 // Otherwise create a new SDValue and remember it.
1043 SDValue Val = getValueImpl(V);
1045 resolveDanglingDebugInfo(V, Val);
1049 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1050 /// Create an SDValue for the given value.
1051 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1052 const TargetLowering *TLI = TM.getTargetLowering();
1054 if (const Constant *C = dyn_cast<Constant>(V)) {
1055 EVT VT = TLI->getValueType(V->getType(), true);
1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1058 return DAG.getConstant(*CI, VT);
1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1061 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1063 if (isa<ConstantPointerNull>(C)) {
1064 unsigned AS = V->getType()->getPointerAddressSpace();
1065 return DAG.getConstant(0, TLI->getPointerTy(AS));
1068 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1069 return DAG.getConstantFP(*CFP, VT);
1071 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1072 return DAG.getUNDEF(VT);
1074 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1075 visit(CE->getOpcode(), *CE);
1076 SDValue N1 = NodeMap[V];
1077 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1081 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1082 SmallVector<SDValue, 4> Constants;
1083 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1085 SDNode *Val = getValue(*OI).getNode();
1086 // If the operand is an empty aggregate, there are no values.
1088 // Add each leaf value from the operand to the Constants list
1089 // to form a flattened list of all the values.
1090 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1091 Constants.push_back(SDValue(Val, i));
1094 return DAG.getMergeValues(&Constants[0], Constants.size(),
1098 if (const ConstantDataSequential *CDS =
1099 dyn_cast<ConstantDataSequential>(C)) {
1100 SmallVector<SDValue, 4> Ops;
1101 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1102 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1103 // Add each leaf value from the operand to the Constants list
1104 // to form a flattened list of all the values.
1105 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1106 Ops.push_back(SDValue(Val, i));
1109 if (isa<ArrayType>(CDS->getType()))
1110 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1111 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1112 VT, &Ops[0], Ops.size());
1115 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1116 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1117 "Unknown struct or array constant!");
1119 SmallVector<EVT, 4> ValueVTs;
1120 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1121 unsigned NumElts = ValueVTs.size();
1123 return SDValue(); // empty struct
1124 SmallVector<SDValue, 4> Constants(NumElts);
1125 for (unsigned i = 0; i != NumElts; ++i) {
1126 EVT EltVT = ValueVTs[i];
1127 if (isa<UndefValue>(C))
1128 Constants[i] = DAG.getUNDEF(EltVT);
1129 else if (EltVT.isFloatingPoint())
1130 Constants[i] = DAG.getConstantFP(0, EltVT);
1132 Constants[i] = DAG.getConstant(0, EltVT);
1135 return DAG.getMergeValues(&Constants[0], NumElts,
1139 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1140 return DAG.getBlockAddress(BA, VT);
1142 VectorType *VecTy = cast<VectorType>(V->getType());
1143 unsigned NumElements = VecTy->getNumElements();
1145 // Now that we know the number and type of the elements, get that number of
1146 // elements into the Ops array based on what kind of constant it is.
1147 SmallVector<SDValue, 16> Ops;
1148 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1149 for (unsigned i = 0; i != NumElements; ++i)
1150 Ops.push_back(getValue(CV->getOperand(i)));
1152 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1153 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1156 if (EltVT.isFloatingPoint())
1157 Op = DAG.getConstantFP(0, EltVT);
1159 Op = DAG.getConstant(0, EltVT);
1160 Ops.assign(NumElements, Op);
1163 // Create a BUILD_VECTOR node.
1164 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1165 VT, &Ops[0], Ops.size());
1168 // If this is a static alloca, generate it as the frameindex instead of
1170 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1171 DenseMap<const AllocaInst*, int>::iterator SI =
1172 FuncInfo.StaticAllocaMap.find(AI);
1173 if (SI != FuncInfo.StaticAllocaMap.end())
1174 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1177 // If this is an instruction which fast-isel has deferred, select it now.
1178 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1179 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1180 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1181 SDValue Chain = DAG.getEntryNode();
1182 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1185 llvm_unreachable("Can't get register for value!");
1188 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1189 const TargetLowering *TLI = TM.getTargetLowering();
1190 SDValue Chain = getControlRoot();
1191 SmallVector<ISD::OutputArg, 8> Outs;
1192 SmallVector<SDValue, 8> OutVals;
1194 if (!FuncInfo.CanLowerReturn) {
1195 unsigned DemoteReg = FuncInfo.DemoteRegister;
1196 const Function *F = I.getParent()->getParent();
1198 // Emit a store of the return value through the virtual register.
1199 // Leave Outs empty so that LowerReturn won't try to load return
1200 // registers the usual way.
1201 SmallVector<EVT, 1> PtrValueVTs;
1202 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1205 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1206 SDValue RetOp = getValue(I.getOperand(0));
1208 SmallVector<EVT, 4> ValueVTs;
1209 SmallVector<uint64_t, 4> Offsets;
1210 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1211 unsigned NumValues = ValueVTs.size();
1213 SmallVector<SDValue, 4> Chains(NumValues);
1214 for (unsigned i = 0; i != NumValues; ++i) {
1215 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1216 RetPtr.getValueType(), RetPtr,
1217 DAG.getIntPtrConstant(Offsets[i]));
1219 DAG.getStore(Chain, getCurSDLoc(),
1220 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1221 // FIXME: better loc info would be nice.
1222 Add, MachinePointerInfo(), false, false, 0);
1225 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1226 MVT::Other, &Chains[0], NumValues);
1227 } else if (I.getNumOperands() != 0) {
1228 SmallVector<EVT, 4> ValueVTs;
1229 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1230 unsigned NumValues = ValueVTs.size();
1232 SDValue RetOp = getValue(I.getOperand(0));
1233 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1234 EVT VT = ValueVTs[j];
1236 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1238 const Function *F = I.getParent()->getParent();
1239 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::SIGN_EXTEND;
1242 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1244 ExtendKind = ISD::ZERO_EXTEND;
1246 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1247 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1249 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1250 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1251 SmallVector<SDValue, 4> Parts(NumParts);
1252 getCopyToParts(DAG, getCurSDLoc(),
1253 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1254 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1256 // 'inreg' on function refers to return value
1257 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1262 // Propagate extension type if any
1263 if (ExtendKind == ISD::SIGN_EXTEND)
1265 else if (ExtendKind == ISD::ZERO_EXTEND)
1268 for (unsigned i = 0; i < NumParts; ++i) {
1269 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1270 VT, /*isfixed=*/true, 0, 0));
1271 OutVals.push_back(Parts[i]);
1277 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1278 CallingConv::ID CallConv =
1279 DAG.getMachineFunction().getFunction()->getCallingConv();
1280 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1281 Outs, OutVals, getCurSDLoc(),
1284 // Verify that the target's LowerReturn behaved as expected.
1285 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1286 "LowerReturn didn't return a valid chain!");
1288 // Update the DAG with the new chain value resulting from return lowering.
1292 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1293 /// created for it, emit nodes to copy the value into the virtual
1295 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1297 if (V->getType()->isEmptyTy())
1300 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1301 if (VMI != FuncInfo.ValueMap.end()) {
1302 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1303 CopyValueToVirtualRegister(V, VMI->second);
1307 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1308 /// the current basic block, add it to ValueMap now so that we'll get a
1310 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1311 // No need to export constants.
1312 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1314 // Already exported?
1315 if (FuncInfo.isExportedInst(V)) return;
1317 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1318 CopyValueToVirtualRegister(V, Reg);
1321 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1322 const BasicBlock *FromBB) {
1323 // The operands of the setcc have to be in this block. We don't know
1324 // how to export them from some other block.
1325 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1326 // Can export from current BB.
1327 if (VI->getParent() == FromBB)
1330 // Is already exported, noop.
1331 return FuncInfo.isExportedInst(V);
1334 // If this is an argument, we can export it if the BB is the entry block or
1335 // if it is already exported.
1336 if (isa<Argument>(V)) {
1337 if (FromBB == &FromBB->getParent()->getEntryBlock())
1340 // Otherwise, can only export this if it is already exported.
1341 return FuncInfo.isExportedInst(V);
1344 // Otherwise, constants can always be exported.
1348 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1349 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1350 const MachineBasicBlock *Dst) const {
1351 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1354 const BasicBlock *SrcBB = Src->getBasicBlock();
1355 const BasicBlock *DstBB = Dst->getBasicBlock();
1356 return BPI->getEdgeWeight(SrcBB, DstBB);
1359 void SelectionDAGBuilder::
1360 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1361 uint32_t Weight /* = 0 */) {
1363 Weight = getEdgeWeight(Src, Dst);
1364 Src->addSuccessor(Dst, Weight);
1368 static bool InBlock(const Value *V, const BasicBlock *BB) {
1369 if (const Instruction *I = dyn_cast<Instruction>(V))
1370 return I->getParent() == BB;
1374 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1375 /// This function emits a branch and is used at the leaves of an OR or an
1376 /// AND operator tree.
1379 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1380 MachineBasicBlock *TBB,
1381 MachineBasicBlock *FBB,
1382 MachineBasicBlock *CurBB,
1383 MachineBasicBlock *SwitchBB,
1386 const BasicBlock *BB = CurBB->getBasicBlock();
1388 // If the leaf of the tree is a comparison, merge the condition into
1390 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1391 // The operands of the cmp have to be in this block. We don't know
1392 // how to export them from some other block. If this is the first block
1393 // of the sequence, no exporting is needed.
1394 if (CurBB == SwitchBB ||
1395 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1396 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1397 ISD::CondCode Condition;
1398 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1399 Condition = getICmpCondCode(IC->getPredicate());
1400 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1401 Condition = getFCmpCondCode(FC->getPredicate());
1402 if (TM.Options.NoNaNsFPMath)
1403 Condition = getFCmpCodeWithoutNaN(Condition);
1405 Condition = ISD::SETEQ; // silence warning.
1406 llvm_unreachable("Unknown compare instruction");
1409 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1410 TBB, FBB, CurBB, TWeight, FWeight);
1411 SwitchCases.push_back(CB);
1416 // Create a CaseBlock record representing this branch.
1417 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1418 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1419 SwitchCases.push_back(CB);
1422 /// Scale down both weights to fit into uint32_t.
1423 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1424 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1425 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1426 NewTrue = NewTrue / Scale;
1427 NewFalse = NewFalse / Scale;
1430 /// FindMergedConditions - If Cond is an expression like
1431 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1432 MachineBasicBlock *TBB,
1433 MachineBasicBlock *FBB,
1434 MachineBasicBlock *CurBB,
1435 MachineBasicBlock *SwitchBB,
1436 unsigned Opc, uint32_t TWeight,
1438 // If this node is not part of the or/and tree, emit it as a branch.
1439 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1440 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1441 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1442 BOp->getParent() != CurBB->getBasicBlock() ||
1443 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1444 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1445 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1450 // Create TmpBB after CurBB.
1451 MachineFunction::iterator BBI = CurBB;
1452 MachineFunction &MF = DAG.getMachineFunction();
1453 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1454 CurBB->getParent()->insert(++BBI, TmpBB);
1456 if (Opc == Instruction::Or) {
1457 // Codegen X | Y as:
1466 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1467 // The requirement is that
1468 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1469 // = TrueProb for orignal BB.
1470 // Assuming the orignal weights are A and B, one choice is to set BB1's
1471 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1473 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1474 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1475 // TmpBB, but the math is more complicated.
1477 uint64_t NewTrueWeight = TWeight;
1478 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1479 ScaleWeights(NewTrueWeight, NewFalseWeight);
1480 // Emit the LHS condition.
1481 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1482 NewTrueWeight, NewFalseWeight);
1484 NewTrueWeight = TWeight;
1485 NewFalseWeight = 2 * (uint64_t)FWeight;
1486 ScaleWeights(NewTrueWeight, NewFalseWeight);
1487 // Emit the RHS condition into TmpBB.
1488 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1489 NewTrueWeight, NewFalseWeight);
1491 assert(Opc == Instruction::And && "Unknown merge op!");
1492 // Codegen X & Y as:
1500 // This requires creation of TmpBB after CurBB.
1502 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1503 // The requirement is that
1504 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1505 // = FalseProb for orignal BB.
1506 // Assuming the orignal weights are A and B, one choice is to set BB1's
1507 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1509 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1511 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1512 uint64_t NewFalseWeight = FWeight;
1513 ScaleWeights(NewTrueWeight, NewFalseWeight);
1514 // Emit the LHS condition.
1515 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1516 NewTrueWeight, NewFalseWeight);
1518 NewTrueWeight = 2 * (uint64_t)TWeight;
1519 NewFalseWeight = FWeight;
1520 ScaleWeights(NewTrueWeight, NewFalseWeight);
1521 // Emit the RHS condition into TmpBB.
1522 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1523 NewTrueWeight, NewFalseWeight);
1527 /// If the set of cases should be emitted as a series of branches, return true.
1528 /// If we should emit this as a bunch of and/or'd together conditions, return
1531 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1532 if (Cases.size() != 2) return true;
1534 // If this is two comparisons of the same values or'd or and'd together, they
1535 // will get folded into a single comparison, so don't emit two blocks.
1536 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1537 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1538 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1539 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1543 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1544 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1545 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1546 Cases[0].CC == Cases[1].CC &&
1547 isa<Constant>(Cases[0].CmpRHS) &&
1548 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1549 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1551 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1558 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1559 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1561 // Update machine-CFG edges.
1562 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1564 // Figure out which block is immediately after the current one.
1565 MachineBasicBlock *NextBlock = nullptr;
1566 MachineFunction::iterator BBI = BrMBB;
1567 if (++BBI != FuncInfo.MF->end())
1570 if (I.isUnconditional()) {
1571 // Update machine-CFG edges.
1572 BrMBB->addSuccessor(Succ0MBB);
1574 // If this is not a fall-through branch or optimizations are switched off,
1576 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1577 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1578 MVT::Other, getControlRoot(),
1579 DAG.getBasicBlock(Succ0MBB)));
1584 // If this condition is one of the special cases we handle, do special stuff
1586 const Value *CondVal = I.getCondition();
1587 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1589 // If this is a series of conditions that are or'd or and'd together, emit
1590 // this as a sequence of branches instead of setcc's with and/or operations.
1591 // As long as jumps are not expensive, this should improve performance.
1592 // For example, instead of something like:
1605 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1606 if (!TM.getTargetLowering()->isJumpExpensive() &&
1608 (BOp->getOpcode() == Instruction::And ||
1609 BOp->getOpcode() == Instruction::Or)) {
1610 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1611 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1612 getEdgeWeight(BrMBB, Succ1MBB));
1613 // If the compares in later blocks need to use values not currently
1614 // exported from this block, export them now. This block should always
1615 // be the first entry.
1616 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1618 // Allow some cases to be rejected.
1619 if (ShouldEmitAsBranches(SwitchCases)) {
1620 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1621 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1622 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1625 // Emit the branch for this block.
1626 visitSwitchCase(SwitchCases[0], BrMBB);
1627 SwitchCases.erase(SwitchCases.begin());
1631 // Okay, we decided not to do this, remove any inserted MBB's and clear
1633 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1634 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1636 SwitchCases.clear();
1640 // Create a CaseBlock record representing this branch.
1641 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1642 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1644 // Use visitSwitchCase to actually insert the fast branch sequence for this
1646 visitSwitchCase(CB, BrMBB);
1649 /// visitSwitchCase - Emits the necessary code to represent a single node in
1650 /// the binary search tree resulting from lowering a switch instruction.
1651 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1652 MachineBasicBlock *SwitchBB) {
1654 SDValue CondLHS = getValue(CB.CmpLHS);
1655 SDLoc dl = getCurSDLoc();
1657 // Build the setcc now.
1659 // Fold "(X == true)" to X and "(X == false)" to !X to
1660 // handle common cases produced by branch lowering.
1661 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1662 CB.CC == ISD::SETEQ)
1664 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1665 CB.CC == ISD::SETEQ) {
1666 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1667 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1669 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1671 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1673 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1674 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1676 SDValue CmpOp = getValue(CB.CmpMHS);
1677 EVT VT = CmpOp.getValueType();
1679 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1680 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1683 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1684 VT, CmpOp, DAG.getConstant(Low, VT));
1685 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1686 DAG.getConstant(High-Low, VT), ISD::SETULE);
1690 // Update successor info
1691 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1692 // TrueBB and FalseBB are always different unless the incoming IR is
1693 // degenerate. This only happens when running llc on weird IR.
1694 if (CB.TrueBB != CB.FalseBB)
1695 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1697 // Set NextBlock to be the MBB immediately after the current one, if any.
1698 // This is used to avoid emitting unnecessary branches to the next block.
1699 MachineBasicBlock *NextBlock = nullptr;
1700 MachineFunction::iterator BBI = SwitchBB;
1701 if (++BBI != FuncInfo.MF->end())
1704 // If the lhs block is the next block, invert the condition so that we can
1705 // fall through to the lhs instead of the rhs block.
1706 if (CB.TrueBB == NextBlock) {
1707 std::swap(CB.TrueBB, CB.FalseBB);
1708 SDValue True = DAG.getConstant(1, Cond.getValueType());
1709 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1712 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1713 MVT::Other, getControlRoot(), Cond,
1714 DAG.getBasicBlock(CB.TrueBB));
1716 // Insert the false branch. Do this even if it's a fall through branch,
1717 // this makes it easier to do DAG optimizations which require inverting
1718 // the branch condition.
1719 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1720 DAG.getBasicBlock(CB.FalseBB));
1722 DAG.setRoot(BrCond);
1725 /// visitJumpTable - Emit JumpTable node in the current MBB
1726 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1727 // Emit the code for the jump table
1728 assert(JT.Reg != -1U && "Should lower JT Header first!");
1729 EVT PTy = TM.getTargetLowering()->getPointerTy();
1730 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1732 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1733 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1734 MVT::Other, Index.getValue(1),
1736 DAG.setRoot(BrJumpTable);
1739 /// visitJumpTableHeader - This function emits necessary code to produce index
1740 /// in the JumpTable from switch case.
1741 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1742 JumpTableHeader &JTH,
1743 MachineBasicBlock *SwitchBB) {
1744 // Subtract the lowest switch case value from the value being switched on and
1745 // conditional branch to default mbb if the result is greater than the
1746 // difference between smallest and largest cases.
1747 SDValue SwitchOp = getValue(JTH.SValue);
1748 EVT VT = SwitchOp.getValueType();
1749 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1750 DAG.getConstant(JTH.First, VT));
1752 // The SDNode we just created, which holds the value being switched on minus
1753 // the smallest case value, needs to be copied to a virtual register so it
1754 // can be used as an index into the jump table in a subsequent basic block.
1755 // This value may be smaller or larger than the target's pointer type, and
1756 // therefore require extension or truncating.
1757 const TargetLowering *TLI = TM.getTargetLowering();
1758 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1760 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1761 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1762 JumpTableReg, SwitchOp);
1763 JT.Reg = JumpTableReg;
1765 // Emit the range check for the jump table, and branch to the default block
1766 // for the switch statement if the value being switched on exceeds the largest
1767 // case in the switch.
1768 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1769 TLI->getSetCCResultType(*DAG.getContext(),
1770 Sub.getValueType()),
1772 DAG.getConstant(JTH.Last - JTH.First,VT),
1775 // Set NextBlock to be the MBB immediately after the current one, if any.
1776 // This is used to avoid emitting unnecessary branches to the next block.
1777 MachineBasicBlock *NextBlock = nullptr;
1778 MachineFunction::iterator BBI = SwitchBB;
1780 if (++BBI != FuncInfo.MF->end())
1783 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1784 MVT::Other, CopyTo, CMP,
1785 DAG.getBasicBlock(JT.Default));
1787 if (JT.MBB != NextBlock)
1788 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1789 DAG.getBasicBlock(JT.MBB));
1791 DAG.setRoot(BrCond);
1794 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1795 /// tail spliced into a stack protector check success bb.
1797 /// For a high level explanation of how this fits into the stack protector
1798 /// generation see the comment on the declaration of class
1799 /// StackProtectorDescriptor.
1800 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1801 MachineBasicBlock *ParentBB) {
1803 // First create the loads to the guard/stack slot for the comparison.
1804 const TargetLowering *TLI = TM.getTargetLowering();
1805 EVT PtrTy = TLI->getPointerTy();
1807 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1808 int FI = MFI->getStackProtectorIndex();
1810 const Value *IRGuard = SPD.getGuard();
1811 SDValue GuardPtr = getValue(IRGuard);
1812 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1815 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1816 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1817 GuardPtr, MachinePointerInfo(IRGuard, 0),
1818 true, false, false, Align);
1820 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1822 MachinePointerInfo::getFixedStack(FI),
1823 true, false, false, Align);
1825 // Perform the comparison via a subtract/getsetcc.
1826 EVT VT = Guard.getValueType();
1827 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1829 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1830 TLI->getSetCCResultType(*DAG.getContext(),
1831 Sub.getValueType()),
1832 Sub, DAG.getConstant(0, VT),
1835 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1836 // branch to failure MBB.
1837 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1838 MVT::Other, StackSlot.getOperand(0),
1839 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1840 // Otherwise branch to success MBB.
1841 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1843 DAG.getBasicBlock(SPD.getSuccessMBB()));
1848 /// Codegen the failure basic block for a stack protector check.
1850 /// A failure stack protector machine basic block consists simply of a call to
1851 /// __stack_chk_fail().
1853 /// For a high level explanation of how this fits into the stack protector
1854 /// generation see the comment on the declaration of class
1855 /// StackProtectorDescriptor.
1857 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1858 const TargetLowering *TLI = TM.getTargetLowering();
1859 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1860 MVT::isVoid, nullptr, 0, false,
1861 getCurSDLoc(), false, false).second;
1865 /// visitBitTestHeader - This function emits necessary code to produce value
1866 /// suitable for "bit tests"
1867 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1868 MachineBasicBlock *SwitchBB) {
1869 // Subtract the minimum value
1870 SDValue SwitchOp = getValue(B.SValue);
1871 EVT VT = SwitchOp.getValueType();
1872 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1873 DAG.getConstant(B.First, VT));
1876 const TargetLowering *TLI = TM.getTargetLowering();
1877 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1878 TLI->getSetCCResultType(*DAG.getContext(),
1879 Sub.getValueType()),
1880 Sub, DAG.getConstant(B.Range, VT),
1883 // Determine the type of the test operands.
1884 bool UsePtrType = false;
1885 if (!TLI->isTypeLegal(VT))
1888 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1889 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1890 // Switch table case range are encoded into series of masks.
1891 // Just use pointer type, it's guaranteed to fit.
1897 VT = TLI->getPointerTy();
1898 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1901 B.RegVT = VT.getSimpleVT();
1902 B.Reg = FuncInfo.CreateReg(B.RegVT);
1903 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1906 // Set NextBlock to be the MBB immediately after the current one, if any.
1907 // This is used to avoid emitting unnecessary branches to the next block.
1908 MachineBasicBlock *NextBlock = nullptr;
1909 MachineFunction::iterator BBI = SwitchBB;
1910 if (++BBI != FuncInfo.MF->end())
1913 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1915 addSuccessorWithWeight(SwitchBB, B.Default);
1916 addSuccessorWithWeight(SwitchBB, MBB);
1918 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1919 MVT::Other, CopyTo, RangeCmp,
1920 DAG.getBasicBlock(B.Default));
1922 if (MBB != NextBlock)
1923 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1924 DAG.getBasicBlock(MBB));
1926 DAG.setRoot(BrRange);
1929 /// visitBitTestCase - this function produces one "bit test"
1930 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1931 MachineBasicBlock* NextMBB,
1932 uint32_t BranchWeightToNext,
1935 MachineBasicBlock *SwitchBB) {
1937 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1940 unsigned PopCount = CountPopulation_64(B.Mask);
1941 const TargetLowering *TLI = TM.getTargetLowering();
1942 if (PopCount == 1) {
1943 // Testing for a single bit; just compare the shift count with what it
1944 // would need to be to shift a 1 bit in that position.
1945 Cmp = DAG.getSetCC(getCurSDLoc(),
1946 TLI->getSetCCResultType(*DAG.getContext(), VT),
1948 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1950 } else if (PopCount == BB.Range) {
1951 // There is only one zero bit in the range, test for it directly.
1952 Cmp = DAG.getSetCC(getCurSDLoc(),
1953 TLI->getSetCCResultType(*DAG.getContext(), VT),
1955 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1958 // Make desired shift
1959 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1960 DAG.getConstant(1, VT), ShiftOp);
1962 // Emit bit tests and jumps
1963 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1964 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1965 Cmp = DAG.getSetCC(getCurSDLoc(),
1966 TLI->getSetCCResultType(*DAG.getContext(), VT),
1967 AndOp, DAG.getConstant(0, VT),
1971 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1972 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1973 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1974 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1976 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1977 MVT::Other, getControlRoot(),
1978 Cmp, DAG.getBasicBlock(B.TargetBB));
1980 // Set NextBlock to be the MBB immediately after the current one, if any.
1981 // This is used to avoid emitting unnecessary branches to the next block.
1982 MachineBasicBlock *NextBlock = nullptr;
1983 MachineFunction::iterator BBI = SwitchBB;
1984 if (++BBI != FuncInfo.MF->end())
1987 if (NextMBB != NextBlock)
1988 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1989 DAG.getBasicBlock(NextMBB));
1994 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1995 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1997 // Retrieve successors.
1998 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1999 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2001 const Value *Callee(I.getCalledValue());
2002 const Function *Fn = dyn_cast<Function>(Callee);
2003 if (isa<InlineAsm>(Callee))
2005 else if (Fn && Fn->isIntrinsic()) {
2006 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2007 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2009 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2011 // If the value of the invoke is used outside of its defining block, make it
2012 // available as a virtual register.
2013 CopyToExportRegsIfNeeded(&I);
2015 // Update successor info
2016 addSuccessorWithWeight(InvokeMBB, Return);
2017 addSuccessorWithWeight(InvokeMBB, LandingPad);
2019 // Drop into normal successor.
2020 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2021 MVT::Other, getControlRoot(),
2022 DAG.getBasicBlock(Return)));
2025 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2026 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2029 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2030 assert(FuncInfo.MBB->isLandingPad() &&
2031 "Call to landingpad not in landing pad!");
2033 MachineBasicBlock *MBB = FuncInfo.MBB;
2034 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2035 AddLandingPadInfo(LP, MMI, MBB);
2037 // If there aren't registers to copy the values into (e.g., during SjLj
2038 // exceptions), then don't bother to create these DAG nodes.
2039 const TargetLowering *TLI = TM.getTargetLowering();
2040 if (TLI->getExceptionPointerRegister() == 0 &&
2041 TLI->getExceptionSelectorRegister() == 0)
2044 SmallVector<EVT, 2> ValueVTs;
2045 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2046 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2048 // Get the two live-in registers as SDValues. The physregs have already been
2049 // copied into virtual registers.
2051 Ops[0] = DAG.getZExtOrTrunc(
2052 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2053 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2054 getCurSDLoc(), ValueVTs[0]);
2055 Ops[1] = DAG.getZExtOrTrunc(
2056 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2057 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2058 getCurSDLoc(), ValueVTs[1]);
2061 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2062 DAG.getVTList(ValueVTs),
2067 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2068 /// small case ranges).
2069 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2070 CaseRecVector& WorkList,
2072 MachineBasicBlock *Default,
2073 MachineBasicBlock *SwitchBB) {
2074 // Size is the number of Cases represented by this range.
2075 size_t Size = CR.Range.second - CR.Range.first;
2079 // Get the MachineFunction which holds the current MBB. This is used when
2080 // inserting any additional MBBs necessary to represent the switch.
2081 MachineFunction *CurMF = FuncInfo.MF;
2083 // Figure out which block is immediately after the current one.
2084 MachineBasicBlock *NextBlock = nullptr;
2085 MachineFunction::iterator BBI = CR.CaseBB;
2087 if (++BBI != FuncInfo.MF->end())
2090 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2091 // If any two of the cases has the same destination, and if one value
2092 // is the same as the other, but has one bit unset that the other has set,
2093 // use bit manipulation to do two compares at once. For example:
2094 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2095 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2096 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2097 if (Size == 2 && CR.CaseBB == SwitchBB) {
2098 Case &Small = *CR.Range.first;
2099 Case &Big = *(CR.Range.second-1);
2101 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2102 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2103 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2105 // Check that there is only one bit different.
2106 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2107 (SmallValue | BigValue) == BigValue) {
2108 // Isolate the common bit.
2109 APInt CommonBit = BigValue & ~SmallValue;
2110 assert((SmallValue | CommonBit) == BigValue &&
2111 CommonBit.countPopulation() == 1 && "Not a common bit?");
2113 SDValue CondLHS = getValue(SV);
2114 EVT VT = CondLHS.getValueType();
2115 SDLoc DL = getCurSDLoc();
2117 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2118 DAG.getConstant(CommonBit, VT));
2119 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2120 Or, DAG.getConstant(BigValue, VT),
2123 // Update successor info.
2124 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2125 addSuccessorWithWeight(SwitchBB, Small.BB,
2126 Small.ExtraWeight + Big.ExtraWeight);
2127 addSuccessorWithWeight(SwitchBB, Default,
2128 // The default destination is the first successor in IR.
2129 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2131 // Insert the true branch.
2132 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2133 getControlRoot(), Cond,
2134 DAG.getBasicBlock(Small.BB));
2136 // Insert the false branch.
2137 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2138 DAG.getBasicBlock(Default));
2140 DAG.setRoot(BrCond);
2146 // Order cases by weight so the most likely case will be checked first.
2147 uint32_t UnhandledWeights = 0;
2149 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2150 uint32_t IWeight = I->ExtraWeight;
2151 UnhandledWeights += IWeight;
2152 for (CaseItr J = CR.Range.first; J < I; ++J) {
2153 uint32_t JWeight = J->ExtraWeight;
2154 if (IWeight > JWeight)
2159 // Rearrange the case blocks so that the last one falls through if possible.
2160 Case &BackCase = *(CR.Range.second-1);
2162 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2163 // The last case block won't fall through into 'NextBlock' if we emit the
2164 // branches in this order. See if rearranging a case value would help.
2165 // We start at the bottom as it's the case with the least weight.
2166 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2167 if (I->BB == NextBlock) {
2168 std::swap(*I, BackCase);
2173 // Create a CaseBlock record representing a conditional branch to
2174 // the Case's target mbb if the value being switched on SV is equal
2176 MachineBasicBlock *CurBlock = CR.CaseBB;
2177 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2178 MachineBasicBlock *FallThrough;
2180 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2181 CurMF->insert(BBI, FallThrough);
2183 // Put SV in a virtual register to make it available from the new blocks.
2184 ExportFromCurrentBlock(SV);
2186 // If the last case doesn't match, go to the default block.
2187 FallThrough = Default;
2190 const Value *RHS, *LHS, *MHS;
2192 if (I->High == I->Low) {
2193 // This is just small small case range :) containing exactly 1 case
2195 LHS = SV; RHS = I->High; MHS = nullptr;
2198 LHS = I->Low; MHS = SV; RHS = I->High;
2201 // The false weight should be sum of all un-handled cases.
2202 UnhandledWeights -= I->ExtraWeight;
2203 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2205 /* trueweight */ I->ExtraWeight,
2206 /* falseweight */ UnhandledWeights);
2208 // If emitting the first comparison, just call visitSwitchCase to emit the
2209 // code into the current block. Otherwise, push the CaseBlock onto the
2210 // vector to be later processed by SDISel, and insert the node's MBB
2211 // before the next MBB.
2212 if (CurBlock == SwitchBB)
2213 visitSwitchCase(CB, SwitchBB);
2215 SwitchCases.push_back(CB);
2217 CurBlock = FallThrough;
2223 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2224 return TLI.supportJumpTables() &&
2225 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2226 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2229 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2230 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2231 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2232 return (LastExt - FirstExt + 1ULL);
2235 /// handleJTSwitchCase - Emit jumptable for current switch case range
2236 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2237 CaseRecVector &WorkList,
2239 MachineBasicBlock *Default,
2240 MachineBasicBlock *SwitchBB) {
2241 Case& FrontCase = *CR.Range.first;
2242 Case& BackCase = *(CR.Range.second-1);
2244 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2245 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2247 APInt TSize(First.getBitWidth(), 0);
2248 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2251 const TargetLowering *TLI = TM.getTargetLowering();
2252 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2255 APInt Range = ComputeRange(First, Last);
2256 // The density is TSize / Range. Require at least 40%.
2257 // It should not be possible for IntTSize to saturate for sane code, but make
2258 // sure we handle Range saturation correctly.
2259 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2260 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2261 if (IntTSize * 10 < IntRange * 4)
2264 DEBUG(dbgs() << "Lowering jump table\n"
2265 << "First entry: " << First << ". Last entry: " << Last << '\n'
2266 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2268 // Get the MachineFunction which holds the current MBB. This is used when
2269 // inserting any additional MBBs necessary to represent the switch.
2270 MachineFunction *CurMF = FuncInfo.MF;
2272 // Figure out which block is immediately after the current one.
2273 MachineFunction::iterator BBI = CR.CaseBB;
2276 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2278 // Create a new basic block to hold the code for loading the address
2279 // of the jump table, and jumping to it. Update successor information;
2280 // we will either branch to the default case for the switch, or the jump
2282 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2283 CurMF->insert(BBI, JumpTableBB);
2285 addSuccessorWithWeight(CR.CaseBB, Default);
2286 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2288 // Build a vector of destination BBs, corresponding to each target
2289 // of the jump table. If the value of the jump table slot corresponds to
2290 // a case statement, push the case's BB onto the vector, otherwise, push
2292 std::vector<MachineBasicBlock*> DestBBs;
2294 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2295 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2296 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2298 if (Low.sle(TEI) && TEI.sle(High)) {
2299 DestBBs.push_back(I->BB);
2303 DestBBs.push_back(Default);
2307 // Calculate weight for each unique destination in CR.
2308 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2310 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2311 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2312 DestWeights.find(I->BB);
2313 if (Itr != DestWeights.end())
2314 Itr->second += I->ExtraWeight;
2316 DestWeights[I->BB] = I->ExtraWeight;
2319 // Update successor info. Add one edge to each unique successor.
2320 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2321 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2322 E = DestBBs.end(); I != E; ++I) {
2323 if (!SuccsHandled[(*I)->getNumber()]) {
2324 SuccsHandled[(*I)->getNumber()] = true;
2325 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2326 DestWeights.find(*I);
2327 addSuccessorWithWeight(JumpTableBB, *I,
2328 Itr != DestWeights.end() ? Itr->second : 0);
2332 // Create a jump table index for this jump table.
2333 unsigned JTEncoding = TLI->getJumpTableEncoding();
2334 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2335 ->createJumpTableIndex(DestBBs);
2337 // Set the jump table information so that we can codegen it as a second
2338 // MachineBasicBlock
2339 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2340 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2341 if (CR.CaseBB == SwitchBB)
2342 visitJumpTableHeader(JT, JTH, SwitchBB);
2344 JTCases.push_back(JumpTableBlock(JTH, JT));
2348 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2350 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2351 CaseRecVector& WorkList,
2353 MachineBasicBlock* Default,
2354 MachineBasicBlock* SwitchBB) {
2355 // Get the MachineFunction which holds the current MBB. This is used when
2356 // inserting any additional MBBs necessary to represent the switch.
2357 MachineFunction *CurMF = FuncInfo.MF;
2359 // Figure out which block is immediately after the current one.
2360 MachineFunction::iterator BBI = CR.CaseBB;
2363 Case& FrontCase = *CR.Range.first;
2364 Case& BackCase = *(CR.Range.second-1);
2365 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2367 // Size is the number of Cases represented by this range.
2368 unsigned Size = CR.Range.second - CR.Range.first;
2370 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2371 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2373 CaseItr Pivot = CR.Range.first + Size/2;
2375 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2376 // (heuristically) allow us to emit JumpTable's later.
2377 APInt TSize(First.getBitWidth(), 0);
2378 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2382 APInt LSize = FrontCase.size();
2383 APInt RSize = TSize-LSize;
2384 DEBUG(dbgs() << "Selecting best pivot: \n"
2385 << "First: " << First << ", Last: " << Last <<'\n'
2386 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2387 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2389 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2390 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2391 APInt Range = ComputeRange(LEnd, RBegin);
2392 assert((Range - 2ULL).isNonNegative() &&
2393 "Invalid case distance");
2394 // Use volatile double here to avoid excess precision issues on some hosts,
2395 // e.g. that use 80-bit X87 registers.
2396 volatile double LDensity =
2397 (double)LSize.roundToDouble() /
2398 (LEnd - First + 1ULL).roundToDouble();
2399 volatile double RDensity =
2400 (double)RSize.roundToDouble() /
2401 (Last - RBegin + 1ULL).roundToDouble();
2402 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2403 // Should always split in some non-trivial place
2404 DEBUG(dbgs() <<"=>Step\n"
2405 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2406 << "LDensity: " << LDensity
2407 << ", RDensity: " << RDensity << '\n'
2408 << "Metric: " << Metric << '\n');
2409 if (FMetric < Metric) {
2412 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2419 const TargetLowering *TLI = TM.getTargetLowering();
2420 if (areJTsAllowed(*TLI)) {
2421 // If our case is dense we *really* should handle it earlier!
2422 assert((FMetric > 0) && "Should handle dense range earlier!");
2424 Pivot = CR.Range.first + Size/2;
2427 CaseRange LHSR(CR.Range.first, Pivot);
2428 CaseRange RHSR(Pivot, CR.Range.second);
2429 const Constant *C = Pivot->Low;
2430 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2432 // We know that we branch to the LHS if the Value being switched on is
2433 // less than the Pivot value, C. We use this to optimize our binary
2434 // tree a bit, by recognizing that if SV is greater than or equal to the
2435 // LHS's Case Value, and that Case Value is exactly one less than the
2436 // Pivot's Value, then we can branch directly to the LHS's Target,
2437 // rather than creating a leaf node for it.
2438 if ((LHSR.second - LHSR.first) == 1 &&
2439 LHSR.first->High == CR.GE &&
2440 cast<ConstantInt>(C)->getValue() ==
2441 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2442 TrueBB = LHSR.first->BB;
2444 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2445 CurMF->insert(BBI, TrueBB);
2446 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2448 // Put SV in a virtual register to make it available from the new blocks.
2449 ExportFromCurrentBlock(SV);
2452 // Similar to the optimization above, if the Value being switched on is
2453 // known to be less than the Constant CR.LT, and the current Case Value
2454 // is CR.LT - 1, then we can branch directly to the target block for
2455 // the current Case Value, rather than emitting a RHS leaf node for it.
2456 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2457 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2458 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2459 FalseBB = RHSR.first->BB;
2461 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2462 CurMF->insert(BBI, FalseBB);
2463 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2465 // Put SV in a virtual register to make it available from the new blocks.
2466 ExportFromCurrentBlock(SV);
2469 // Create a CaseBlock record representing a conditional branch to
2470 // the LHS node if the value being switched on SV is less than C.
2471 // Otherwise, branch to LHS.
2472 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2474 if (CR.CaseBB == SwitchBB)
2475 visitSwitchCase(CB, SwitchBB);
2477 SwitchCases.push_back(CB);
2482 /// handleBitTestsSwitchCase - if current case range has few destination and
2483 /// range span less, than machine word bitwidth, encode case range into series
2484 /// of masks and emit bit tests with these masks.
2485 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2486 CaseRecVector& WorkList,
2488 MachineBasicBlock* Default,
2489 MachineBasicBlock* SwitchBB) {
2490 const TargetLowering *TLI = TM.getTargetLowering();
2491 EVT PTy = TLI->getPointerTy();
2492 unsigned IntPtrBits = PTy.getSizeInBits();
2494 Case& FrontCase = *CR.Range.first;
2495 Case& BackCase = *(CR.Range.second-1);
2497 // Get the MachineFunction which holds the current MBB. This is used when
2498 // inserting any additional MBBs necessary to represent the switch.
2499 MachineFunction *CurMF = FuncInfo.MF;
2501 // If target does not have legal shift left, do not emit bit tests at all.
2502 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2506 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2508 // Single case counts one, case range - two.
2509 numCmps += (I->Low == I->High ? 1 : 2);
2512 // Count unique destinations
2513 SmallSet<MachineBasicBlock*, 4> Dests;
2514 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2515 Dests.insert(I->BB);
2516 if (Dests.size() > 3)
2517 // Don't bother the code below, if there are too much unique destinations
2520 DEBUG(dbgs() << "Total number of unique destinations: "
2521 << Dests.size() << '\n'
2522 << "Total number of comparisons: " << numCmps << '\n');
2524 // Compute span of values.
2525 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2526 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2527 APInt cmpRange = maxValue - minValue;
2529 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2530 << "Low bound: " << minValue << '\n'
2531 << "High bound: " << maxValue << '\n');
2533 if (cmpRange.uge(IntPtrBits) ||
2534 (!(Dests.size() == 1 && numCmps >= 3) &&
2535 !(Dests.size() == 2 && numCmps >= 5) &&
2536 !(Dests.size() >= 3 && numCmps >= 6)))
2539 DEBUG(dbgs() << "Emitting bit tests\n");
2540 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2542 // Optimize the case where all the case values fit in a
2543 // word without having to subtract minValue. In this case,
2544 // we can optimize away the subtraction.
2545 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2546 cmpRange = maxValue;
2548 lowBound = minValue;
2551 CaseBitsVector CasesBits;
2552 unsigned i, count = 0;
2554 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2555 MachineBasicBlock* Dest = I->BB;
2556 for (i = 0; i < count; ++i)
2557 if (Dest == CasesBits[i].BB)
2561 assert((count < 3) && "Too much destinations to test!");
2562 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2566 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2567 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2569 uint64_t lo = (lowValue - lowBound).getZExtValue();
2570 uint64_t hi = (highValue - lowBound).getZExtValue();
2571 CasesBits[i].ExtraWeight += I->ExtraWeight;
2573 for (uint64_t j = lo; j <= hi; j++) {
2574 CasesBits[i].Mask |= 1ULL << j;
2575 CasesBits[i].Bits++;
2579 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2583 // Figure out which block is immediately after the current one.
2584 MachineFunction::iterator BBI = CR.CaseBB;
2587 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2589 DEBUG(dbgs() << "Cases:\n");
2590 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2591 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2592 << ", Bits: " << CasesBits[i].Bits
2593 << ", BB: " << CasesBits[i].BB << '\n');
2595 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2596 CurMF->insert(BBI, CaseBB);
2597 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2599 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2601 // Put SV in a virtual register to make it available from the new blocks.
2602 ExportFromCurrentBlock(SV);
2605 BitTestBlock BTB(lowBound, cmpRange, SV,
2606 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2607 CR.CaseBB, Default, BTC);
2609 if (CR.CaseBB == SwitchBB)
2610 visitBitTestHeader(BTB, SwitchBB);
2612 BitTestCases.push_back(BTB);
2617 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2618 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2619 const SwitchInst& SI) {
2622 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2623 // Start with "simple" cases
2624 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2626 const BasicBlock *SuccBB = i.getCaseSuccessor();
2627 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2629 uint32_t ExtraWeight =
2630 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2632 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2633 SMBB, ExtraWeight));
2635 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2637 // Merge case into clusters
2638 if (Cases.size() >= 2)
2639 // Must recompute end() each iteration because it may be
2640 // invalidated by erase if we hold on to it
2641 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2642 J != Cases.end(); ) {
2643 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2644 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2645 MachineBasicBlock* nextBB = J->BB;
2646 MachineBasicBlock* currentBB = I->BB;
2648 // If the two neighboring cases go to the same destination, merge them
2649 // into a single case.
2650 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2652 I->ExtraWeight += J->ExtraWeight;
2659 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2660 if (I->Low != I->High)
2661 // A range counts double, since it requires two compares.
2668 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2669 MachineBasicBlock *Last) {
2671 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2672 if (JTCases[i].first.HeaderBB == First)
2673 JTCases[i].first.HeaderBB = Last;
2675 // Update BitTestCases.
2676 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2677 if (BitTestCases[i].Parent == First)
2678 BitTestCases[i].Parent = Last;
2681 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2682 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2684 // Figure out which block is immediately after the current one.
2685 MachineBasicBlock *NextBlock = nullptr;
2686 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2688 // If there is only the default destination, branch to it if it is not the
2689 // next basic block. Otherwise, just fall through.
2690 if (!SI.getNumCases()) {
2691 // Update machine-CFG edges.
2693 // If this is not a fall-through branch, emit the branch.
2694 SwitchMBB->addSuccessor(Default);
2695 if (Default != NextBlock)
2696 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2697 MVT::Other, getControlRoot(),
2698 DAG.getBasicBlock(Default)));
2703 // If there are any non-default case statements, create a vector of Cases
2704 // representing each one, and sort the vector so that we can efficiently
2705 // create a binary search tree from them.
2707 size_t numCmps = Clusterify(Cases, SI);
2708 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2709 << ". Total compares: " << numCmps << '\n');
2712 // Get the Value to be switched on and default basic blocks, which will be
2713 // inserted into CaseBlock records, representing basic blocks in the binary
2715 const Value *SV = SI.getCondition();
2717 // Push the initial CaseRec onto the worklist
2718 CaseRecVector WorkList;
2719 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2720 CaseRange(Cases.begin(),Cases.end())));
2722 while (!WorkList.empty()) {
2723 // Grab a record representing a case range to process off the worklist
2724 CaseRec CR = WorkList.back();
2725 WorkList.pop_back();
2727 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2730 // If the range has few cases (two or less) emit a series of specific
2732 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2735 // If the switch has more than N blocks, and is at least 40% dense, and the
2736 // target supports indirect branches, then emit a jump table rather than
2737 // lowering the switch to a binary tree of conditional branches.
2738 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2739 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2742 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2743 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2744 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2748 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2749 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2751 // Update machine-CFG edges with unique successors.
2752 SmallSet<BasicBlock*, 32> Done;
2753 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2754 BasicBlock *BB = I.getSuccessor(i);
2755 bool Inserted = Done.insert(BB);
2759 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2760 addSuccessorWithWeight(IndirectBrMBB, Succ);
2763 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2764 MVT::Other, getControlRoot(),
2765 getValue(I.getAddress())));
2768 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2769 if (DAG.getTarget().Options.TrapUnreachable)
2770 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2773 void SelectionDAGBuilder::visitFSub(const User &I) {
2774 // -0.0 - X --> fneg
2775 Type *Ty = I.getType();
2776 if (isa<Constant>(I.getOperand(0)) &&
2777 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2778 SDValue Op2 = getValue(I.getOperand(1));
2779 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2780 Op2.getValueType(), Op2));
2784 visitBinary(I, ISD::FSUB);
2787 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2788 SDValue Op1 = getValue(I.getOperand(0));
2789 SDValue Op2 = getValue(I.getOperand(1));
2790 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2791 Op1.getValueType(), Op1, Op2));
2794 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2795 SDValue Op1 = getValue(I.getOperand(0));
2796 SDValue Op2 = getValue(I.getOperand(1));
2798 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2800 // Coerce the shift amount to the right type if we can.
2801 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2802 unsigned ShiftSize = ShiftTy.getSizeInBits();
2803 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2804 SDLoc DL = getCurSDLoc();
2806 // If the operand is smaller than the shift count type, promote it.
2807 if (ShiftSize > Op2Size)
2808 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2810 // If the operand is larger than the shift count type but the shift
2811 // count type has enough bits to represent any shift value, truncate
2812 // it now. This is a common case and it exposes the truncate to
2813 // optimization early.
2814 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2815 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2816 // Otherwise we'll need to temporarily settle for some other convenient
2817 // type. Type legalization will make adjustments once the shiftee is split.
2819 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2822 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2823 Op1.getValueType(), Op1, Op2));
2826 void SelectionDAGBuilder::visitSDiv(const User &I) {
2827 SDValue Op1 = getValue(I.getOperand(0));
2828 SDValue Op2 = getValue(I.getOperand(1));
2830 // Turn exact SDivs into multiplications.
2831 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2833 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2834 !isa<ConstantSDNode>(Op1) &&
2835 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2836 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2837 getCurSDLoc(), DAG));
2839 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2843 void SelectionDAGBuilder::visitICmp(const User &I) {
2844 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2845 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2846 predicate = IC->getPredicate();
2847 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2848 predicate = ICmpInst::Predicate(IC->getPredicate());
2849 SDValue Op1 = getValue(I.getOperand(0));
2850 SDValue Op2 = getValue(I.getOperand(1));
2851 ISD::CondCode Opcode = getICmpCondCode(predicate);
2853 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2854 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2857 void SelectionDAGBuilder::visitFCmp(const User &I) {
2858 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2859 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2860 predicate = FC->getPredicate();
2861 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2862 predicate = FCmpInst::Predicate(FC->getPredicate());
2863 SDValue Op1 = getValue(I.getOperand(0));
2864 SDValue Op2 = getValue(I.getOperand(1));
2865 ISD::CondCode Condition = getFCmpCondCode(predicate);
2866 if (TM.Options.NoNaNsFPMath)
2867 Condition = getFCmpCodeWithoutNaN(Condition);
2868 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2869 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2872 void SelectionDAGBuilder::visitSelect(const User &I) {
2873 SmallVector<EVT, 4> ValueVTs;
2874 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2875 unsigned NumValues = ValueVTs.size();
2876 if (NumValues == 0) return;
2878 SmallVector<SDValue, 4> Values(NumValues);
2879 SDValue Cond = getValue(I.getOperand(0));
2880 SDValue TrueVal = getValue(I.getOperand(1));
2881 SDValue FalseVal = getValue(I.getOperand(2));
2882 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2883 ISD::VSELECT : ISD::SELECT;
2885 for (unsigned i = 0; i != NumValues; ++i)
2886 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2887 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2889 SDValue(TrueVal.getNode(),
2890 TrueVal.getResNo() + i),
2891 SDValue(FalseVal.getNode(),
2892 FalseVal.getResNo() + i));
2894 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2895 DAG.getVTList(ValueVTs),
2896 &Values[0], NumValues));
2899 void SelectionDAGBuilder::visitTrunc(const User &I) {
2900 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2901 SDValue N = getValue(I.getOperand(0));
2902 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2903 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2906 void SelectionDAGBuilder::visitZExt(const User &I) {
2907 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2908 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2909 SDValue N = getValue(I.getOperand(0));
2910 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2911 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2914 void SelectionDAGBuilder::visitSExt(const User &I) {
2915 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2916 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2917 SDValue N = getValue(I.getOperand(0));
2918 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2919 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2922 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2923 // FPTrunc is never a no-op cast, no need to check
2924 SDValue N = getValue(I.getOperand(0));
2925 const TargetLowering *TLI = TM.getTargetLowering();
2926 EVT DestVT = TLI->getValueType(I.getType());
2927 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2929 DAG.getTargetConstant(0, TLI->getPointerTy())));
2932 void SelectionDAGBuilder::visitFPExt(const User &I) {
2933 // FPExt is never a no-op cast, no need to check
2934 SDValue N = getValue(I.getOperand(0));
2935 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2936 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2939 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2940 // FPToUI is never a no-op cast, no need to check
2941 SDValue N = getValue(I.getOperand(0));
2942 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2943 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2946 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2947 // FPToSI is never a no-op cast, no need to check
2948 SDValue N = getValue(I.getOperand(0));
2949 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2950 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2953 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2954 // UIToFP is never a no-op cast, no need to check
2955 SDValue N = getValue(I.getOperand(0));
2956 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2957 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2960 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2961 // SIToFP is never a no-op cast, no need to check
2962 SDValue N = getValue(I.getOperand(0));
2963 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2964 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2967 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2968 // What to do depends on the size of the integer and the size of the pointer.
2969 // We can either truncate, zero extend, or no-op, accordingly.
2970 SDValue N = getValue(I.getOperand(0));
2971 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2972 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2975 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2976 // What to do depends on the size of the integer and the size of the pointer.
2977 // We can either truncate, zero extend, or no-op, accordingly.
2978 SDValue N = getValue(I.getOperand(0));
2979 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2980 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2983 void SelectionDAGBuilder::visitBitCast(const User &I) {
2984 SDValue N = getValue(I.getOperand(0));
2985 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2987 // BitCast assures us that source and destination are the same size so this is
2988 // either a BITCAST or a no-op.
2989 if (DestVT != N.getValueType())
2990 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2991 DestVT, N)); // convert types.
2992 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2993 // might fold any kind of constant expression to an integer constant and that
2994 // is not what we are looking for. Only regcognize a bitcast of a genuine
2995 // constant integer as an opaque constant.
2996 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2997 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3000 setValue(&I, N); // noop cast.
3003 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3005 const Value *SV = I.getOperand(0);
3006 SDValue N = getValue(SV);
3007 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3009 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3010 unsigned DestAS = I.getType()->getPointerAddressSpace();
3012 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3013 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3018 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3020 SDValue InVec = getValue(I.getOperand(0));
3021 SDValue InVal = getValue(I.getOperand(1));
3022 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3023 getCurSDLoc(), TLI.getVectorIdxTy());
3024 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3025 TM.getTargetLowering()->getValueType(I.getType()),
3026 InVec, InVal, InIdx));
3029 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3030 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3031 SDValue InVec = getValue(I.getOperand(0));
3032 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3033 getCurSDLoc(), TLI.getVectorIdxTy());
3034 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3035 TM.getTargetLowering()->getValueType(I.getType()),
3039 // Utility for visitShuffleVector - Return true if every element in Mask,
3040 // beginning from position Pos and ending in Pos+Size, falls within the
3041 // specified sequential range [L, L+Pos). or is undef.
3042 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3043 unsigned Pos, unsigned Size, int Low) {
3044 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3045 if (Mask[i] >= 0 && Mask[i] != Low)
3050 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3051 SDValue Src1 = getValue(I.getOperand(0));
3052 SDValue Src2 = getValue(I.getOperand(1));
3054 SmallVector<int, 8> Mask;
3055 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3056 unsigned MaskNumElts = Mask.size();
3058 const TargetLowering *TLI = TM.getTargetLowering();
3059 EVT VT = TLI->getValueType(I.getType());
3060 EVT SrcVT = Src1.getValueType();
3061 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3063 if (SrcNumElts == MaskNumElts) {
3064 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3069 // Normalize the shuffle vector since mask and vector length don't match.
3070 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3071 // Mask is longer than the source vectors and is a multiple of the source
3072 // vectors. We can use concatenate vector to make the mask and vectors
3074 if (SrcNumElts*2 == MaskNumElts) {
3075 // First check for Src1 in low and Src2 in high
3076 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3077 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3078 // The shuffle is concatenating two vectors together.
3079 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3083 // Then check for Src2 in low and Src1 in high
3084 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3085 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3086 // The shuffle is concatenating two vectors together.
3087 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3093 // Pad both vectors with undefs to make them the same length as the mask.
3094 unsigned NumConcat = MaskNumElts / SrcNumElts;
3095 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3096 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3097 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3099 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3100 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3104 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3106 &MOps1[0], NumConcat);
3107 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3109 &MOps2[0], NumConcat);
3111 // Readjust mask for new input vector length.
3112 SmallVector<int, 8> MappedOps;
3113 for (unsigned i = 0; i != MaskNumElts; ++i) {
3115 if (Idx >= (int)SrcNumElts)
3116 Idx -= SrcNumElts - MaskNumElts;
3117 MappedOps.push_back(Idx);
3120 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3125 if (SrcNumElts > MaskNumElts) {
3126 // Analyze the access pattern of the vector to see if we can extract
3127 // two subvectors and do the shuffle. The analysis is done by calculating
3128 // the range of elements the mask access on both vectors.
3129 int MinRange[2] = { static_cast<int>(SrcNumElts),
3130 static_cast<int>(SrcNumElts)};
3131 int MaxRange[2] = {-1, -1};
3133 for (unsigned i = 0; i != MaskNumElts; ++i) {
3139 if (Idx >= (int)SrcNumElts) {
3143 if (Idx > MaxRange[Input])
3144 MaxRange[Input] = Idx;
3145 if (Idx < MinRange[Input])
3146 MinRange[Input] = Idx;
3149 // Check if the access is smaller than the vector size and can we find
3150 // a reasonable extract index.
3151 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3153 int StartIdx[2]; // StartIdx to extract from
3154 for (unsigned Input = 0; Input < 2; ++Input) {
3155 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3156 RangeUse[Input] = 0; // Unused
3157 StartIdx[Input] = 0;
3161 // Find a good start index that is a multiple of the mask length. Then
3162 // see if the rest of the elements are in range.
3163 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3164 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3165 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3166 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3169 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3170 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3173 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3174 // Extract appropriate subvector and generate a vector shuffle
3175 for (unsigned Input = 0; Input < 2; ++Input) {
3176 SDValue &Src = Input == 0 ? Src1 : Src2;
3177 if (RangeUse[Input] == 0)
3178 Src = DAG.getUNDEF(VT);
3180 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3181 Src, DAG.getConstant(StartIdx[Input],
3182 TLI->getVectorIdxTy()));
3185 // Calculate new mask.
3186 SmallVector<int, 8> MappedOps;
3187 for (unsigned i = 0; i != MaskNumElts; ++i) {
3190 if (Idx < (int)SrcNumElts)
3193 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3195 MappedOps.push_back(Idx);
3198 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3204 // We can't use either concat vectors or extract subvectors so fall back to
3205 // replacing the shuffle with extract and build vector.
3206 // to insert and build vector.
3207 EVT EltVT = VT.getVectorElementType();
3208 EVT IdxVT = TLI->getVectorIdxTy();
3209 SmallVector<SDValue,8> Ops;
3210 for (unsigned i = 0; i != MaskNumElts; ++i) {
3215 Res = DAG.getUNDEF(EltVT);
3217 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3218 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3220 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3221 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3227 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3228 VT, &Ops[0], Ops.size()));
3231 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3232 const Value *Op0 = I.getOperand(0);
3233 const Value *Op1 = I.getOperand(1);
3234 Type *AggTy = I.getType();
3235 Type *ValTy = Op1->getType();
3236 bool IntoUndef = isa<UndefValue>(Op0);
3237 bool FromUndef = isa<UndefValue>(Op1);
3239 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3241 const TargetLowering *TLI = TM.getTargetLowering();
3242 SmallVector<EVT, 4> AggValueVTs;
3243 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3244 SmallVector<EVT, 4> ValValueVTs;
3245 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3247 unsigned NumAggValues = AggValueVTs.size();
3248 unsigned NumValValues = ValValueVTs.size();
3249 SmallVector<SDValue, 4> Values(NumAggValues);
3251 SDValue Agg = getValue(Op0);
3253 // Copy the beginning value(s) from the original aggregate.
3254 for (; i != LinearIndex; ++i)
3255 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3256 SDValue(Agg.getNode(), Agg.getResNo() + i);
3257 // Copy values from the inserted value(s).
3259 SDValue Val = getValue(Op1);
3260 for (; i != LinearIndex + NumValValues; ++i)
3261 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3262 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3264 // Copy remaining value(s) from the original aggregate.
3265 for (; i != NumAggValues; ++i)
3266 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3267 SDValue(Agg.getNode(), Agg.getResNo() + i);
3269 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3270 DAG.getVTList(AggValueVTs),
3271 &Values[0], NumAggValues));
3274 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3275 const Value *Op0 = I.getOperand(0);
3276 Type *AggTy = Op0->getType();
3277 Type *ValTy = I.getType();
3278 bool OutOfUndef = isa<UndefValue>(Op0);
3280 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3282 const TargetLowering *TLI = TM.getTargetLowering();
3283 SmallVector<EVT, 4> ValValueVTs;
3284 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3286 unsigned NumValValues = ValValueVTs.size();
3288 // Ignore a extractvalue that produces an empty object
3289 if (!NumValValues) {
3290 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3294 SmallVector<SDValue, 4> Values(NumValValues);
3296 SDValue Agg = getValue(Op0);
3297 // Copy out the selected value(s).
3298 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3299 Values[i - LinearIndex] =
3301 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3302 SDValue(Agg.getNode(), Agg.getResNo() + i);
3304 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3305 DAG.getVTList(ValValueVTs),
3306 &Values[0], NumValValues));
3309 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3310 Value *Op0 = I.getOperand(0);
3311 // Note that the pointer operand may be a vector of pointers. Take the scalar
3312 // element which holds a pointer.
3313 Type *Ty = Op0->getType()->getScalarType();
3314 unsigned AS = Ty->getPointerAddressSpace();
3315 SDValue N = getValue(Op0);
3317 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3319 const Value *Idx = *OI;
3320 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3321 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3324 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3325 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3326 DAG.getConstant(Offset, N.getValueType()));
3329 Ty = StTy->getElementType(Field);
3331 Ty = cast<SequentialType>(Ty)->getElementType();
3333 // If this is a constant subscript, handle it quickly.
3334 const TargetLowering *TLI = TM.getTargetLowering();
3335 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3336 if (CI->isZero()) continue;
3338 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3340 EVT PTy = TLI->getPointerTy(AS);
3341 unsigned PtrBits = PTy.getSizeInBits();
3343 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3344 DAG.getConstant(Offs, MVT::i64));
3346 OffsVal = DAG.getConstant(Offs, PTy);
3348 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3353 // N = N + Idx * ElementSize;
3354 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3355 DL->getTypeAllocSize(Ty));
3356 SDValue IdxN = getValue(Idx);
3358 // If the index is smaller or larger than intptr_t, truncate or extend
3360 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3362 // If this is a multiply by a power of two, turn it into a shl
3363 // immediately. This is a very common case.
3364 if (ElementSize != 1) {
3365 if (ElementSize.isPowerOf2()) {
3366 unsigned Amt = ElementSize.logBase2();
3367 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3368 N.getValueType(), IdxN,
3369 DAG.getConstant(Amt, IdxN.getValueType()));
3371 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3372 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3373 N.getValueType(), IdxN, Scale);
3377 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3378 N.getValueType(), N, IdxN);
3385 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3386 // If this is a fixed sized alloca in the entry block of the function,
3387 // allocate it statically on the stack.
3388 if (FuncInfo.StaticAllocaMap.count(&I))
3389 return; // getValue will auto-populate this.
3391 Type *Ty = I.getAllocatedType();
3392 const TargetLowering *TLI = TM.getTargetLowering();
3393 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3395 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3398 SDValue AllocSize = getValue(I.getArraySize());
3400 EVT IntPtr = TLI->getPointerTy();
3401 if (AllocSize.getValueType() != IntPtr)
3402 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3404 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3406 DAG.getConstant(TySize, IntPtr));
3408 // Handle alignment. If the requested alignment is less than or equal to
3409 // the stack alignment, ignore it. If the size is greater than or equal to
3410 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3411 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3412 if (Align <= StackAlign)
3415 // Round the size of the allocation up to the stack alignment size
3416 // by add SA-1 to the size.
3417 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3418 AllocSize.getValueType(), AllocSize,
3419 DAG.getIntPtrConstant(StackAlign-1));
3421 // Mask out the low bits for alignment purposes.
3422 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3423 AllocSize.getValueType(), AllocSize,
3424 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3426 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3427 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3428 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3431 DAG.setRoot(DSA.getValue(1));
3433 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3436 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3438 return visitAtomicLoad(I);
3440 const Value *SV = I.getOperand(0);
3441 SDValue Ptr = getValue(SV);
3443 Type *Ty = I.getType();
3445 bool isVolatile = I.isVolatile();
3446 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3447 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3448 unsigned Alignment = I.getAlignment();
3449 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3450 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3452 SmallVector<EVT, 4> ValueVTs;
3453 SmallVector<uint64_t, 4> Offsets;
3454 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3455 unsigned NumValues = ValueVTs.size();
3460 bool ConstantMemory = false;
3461 if (isVolatile || NumValues > MaxParallelChains)
3462 // Serialize volatile loads with other side effects.
3464 else if (AA->pointsToConstantMemory(
3465 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3466 // Do not serialize (non-volatile) loads of constant memory with anything.
3467 Root = DAG.getEntryNode();
3468 ConstantMemory = true;
3470 // Do not serialize non-volatile loads against each other.
3471 Root = DAG.getRoot();
3474 const TargetLowering *TLI = TM.getTargetLowering();
3476 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3478 SmallVector<SDValue, 4> Values(NumValues);
3479 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3481 EVT PtrVT = Ptr.getValueType();
3482 unsigned ChainI = 0;
3483 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3484 // Serializing loads here may result in excessive register pressure, and
3485 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3486 // could recover a bit by hoisting nodes upward in the chain by recognizing
3487 // they are side-effect free or do not alias. The optimizer should really
3488 // avoid this case by converting large object/array copies to llvm.memcpy
3489 // (MaxParallelChains should always remain as failsafe).
3490 if (ChainI == MaxParallelChains) {
3491 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3492 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3493 MVT::Other, &Chains[0], ChainI);
3497 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3499 DAG.getConstant(Offsets[i], PtrVT));
3500 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3501 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3502 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3506 Chains[ChainI] = L.getValue(1);
3509 if (!ConstantMemory) {
3510 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3511 MVT::Other, &Chains[0], ChainI);
3515 PendingLoads.push_back(Chain);
3518 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3519 DAG.getVTList(ValueVTs),
3520 &Values[0], NumValues));
3523 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3525 return visitAtomicStore(I);
3527 const Value *SrcV = I.getOperand(0);
3528 const Value *PtrV = I.getOperand(1);
3530 SmallVector<EVT, 4> ValueVTs;
3531 SmallVector<uint64_t, 4> Offsets;
3532 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3533 unsigned NumValues = ValueVTs.size();
3537 // Get the lowered operands. Note that we do this after
3538 // checking if NumResults is zero, because with zero results
3539 // the operands won't have values in the map.
3540 SDValue Src = getValue(SrcV);
3541 SDValue Ptr = getValue(PtrV);
3543 SDValue Root = getRoot();
3544 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3546 EVT PtrVT = Ptr.getValueType();
3547 bool isVolatile = I.isVolatile();
3548 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3549 unsigned Alignment = I.getAlignment();
3550 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3552 unsigned ChainI = 0;
3553 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3554 // See visitLoad comments.
3555 if (ChainI == MaxParallelChains) {
3556 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3557 MVT::Other, &Chains[0], ChainI);
3561 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3562 DAG.getConstant(Offsets[i], PtrVT));
3563 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3564 SDValue(Src.getNode(), Src.getResNo() + i),
3565 Add, MachinePointerInfo(PtrV, Offsets[i]),
3566 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3567 Chains[ChainI] = St;
3570 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3571 MVT::Other, &Chains[0], ChainI);
3572 DAG.setRoot(StoreNode);
3575 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3576 SynchronizationScope Scope,
3577 bool Before, SDLoc dl,
3579 const TargetLowering &TLI) {
3580 // Fence, if necessary
3582 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3584 else if (Order == Acquire || Order == Monotonic)
3587 if (Order == AcquireRelease)
3589 else if (Order == Release || Order == Monotonic)
3594 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3595 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3596 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3599 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3600 SDLoc dl = getCurSDLoc();
3601 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3602 AtomicOrdering FailureOrder = I.getFailureOrdering();
3603 SynchronizationScope Scope = I.getSynchScope();
3605 SDValue InChain = getRoot();
3607 const TargetLowering *TLI = TM.getTargetLowering();
3608 if (TLI->getInsertFencesForAtomic())
3609 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3613 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3614 getValue(I.getCompareOperand()).getSimpleValueType(),
3616 getValue(I.getPointerOperand()),
3617 getValue(I.getCompareOperand()),
3618 getValue(I.getNewValOperand()),
3619 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3620 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3621 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder,
3624 SDValue OutChain = L.getValue(1);
3626 if (TLI->getInsertFencesForAtomic())
3627 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3631 DAG.setRoot(OutChain);
3634 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3635 SDLoc dl = getCurSDLoc();
3637 switch (I.getOperation()) {
3638 default: llvm_unreachable("Unknown atomicrmw operation");
3639 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3640 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3641 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3642 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3643 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3644 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3645 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3646 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3647 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3648 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3649 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3651 AtomicOrdering Order = I.getOrdering();
3652 SynchronizationScope Scope = I.getSynchScope();
3654 SDValue InChain = getRoot();
3656 const TargetLowering *TLI = TM.getTargetLowering();
3657 if (TLI->getInsertFencesForAtomic())
3658 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3662 DAG.getAtomic(NT, dl,
3663 getValue(I.getValOperand()).getSimpleValueType(),
3665 getValue(I.getPointerOperand()),
3666 getValue(I.getValOperand()),
3667 I.getPointerOperand(), 0 /* Alignment */,
3668 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3671 SDValue OutChain = L.getValue(1);
3673 if (TLI->getInsertFencesForAtomic())
3674 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3678 DAG.setRoot(OutChain);
3681 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3682 SDLoc dl = getCurSDLoc();
3683 const TargetLowering *TLI = TM.getTargetLowering();
3686 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3687 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3688 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3691 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3692 SDLoc dl = getCurSDLoc();
3693 AtomicOrdering Order = I.getOrdering();
3694 SynchronizationScope Scope = I.getSynchScope();
3696 SDValue InChain = getRoot();
3698 const TargetLowering *TLI = TM.getTargetLowering();
3699 EVT VT = TLI->getValueType(I.getType());
3701 if (I.getAlignment() < VT.getSizeInBits() / 8)
3702 report_fatal_error("Cannot generate unaligned atomic load");
3704 MachineMemOperand *MMO =
3705 DAG.getMachineFunction().
3706 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3707 MachineMemOperand::MOVolatile |
3708 MachineMemOperand::MOLoad,
3710 I.getAlignment() ? I.getAlignment() :
3711 DAG.getEVTAlignment(VT));
3713 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3715 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3716 getValue(I.getPointerOperand()), MMO,
3717 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3720 SDValue OutChain = L.getValue(1);
3722 if (TLI->getInsertFencesForAtomic())
3723 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3727 DAG.setRoot(OutChain);
3730 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3731 SDLoc dl = getCurSDLoc();
3733 AtomicOrdering Order = I.getOrdering();
3734 SynchronizationScope Scope = I.getSynchScope();
3736 SDValue InChain = getRoot();
3738 const TargetLowering *TLI = TM.getTargetLowering();
3739 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3741 if (I.getAlignment() < VT.getSizeInBits() / 8)
3742 report_fatal_error("Cannot generate unaligned atomic store");
3744 if (TLI->getInsertFencesForAtomic())
3745 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3749 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3751 getValue(I.getPointerOperand()),
3752 getValue(I.getValueOperand()),
3753 I.getPointerOperand(), I.getAlignment(),
3754 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3757 if (TLI->getInsertFencesForAtomic())
3758 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3761 DAG.setRoot(OutChain);
3764 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3766 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3767 unsigned Intrinsic) {
3768 bool HasChain = !I.doesNotAccessMemory();
3769 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3771 // Build the operand list.
3772 SmallVector<SDValue, 8> Ops;
3773 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3775 // We don't need to serialize loads against other loads.
3776 Ops.push_back(DAG.getRoot());
3778 Ops.push_back(getRoot());
3782 // Info is set by getTgtMemInstrinsic
3783 TargetLowering::IntrinsicInfo Info;
3784 const TargetLowering *TLI = TM.getTargetLowering();
3785 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3787 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3788 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3789 Info.opc == ISD::INTRINSIC_W_CHAIN)
3790 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3792 // Add all operands of the call to the operand list.
3793 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3794 SDValue Op = getValue(I.getArgOperand(i));
3798 SmallVector<EVT, 4> ValueVTs;
3799 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3802 ValueVTs.push_back(MVT::Other);
3804 SDVTList VTs = DAG.getVTList(ValueVTs);
3808 if (IsTgtIntrinsic) {
3809 // This is target intrinsic that touches memory
3810 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3811 VTs, &Ops[0], Ops.size(),
3813 MachinePointerInfo(Info.ptrVal, Info.offset),
3814 Info.align, Info.vol,
3815 Info.readMem, Info.writeMem);
3816 } else if (!HasChain) {
3817 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3818 VTs, &Ops[0], Ops.size());
3819 } else if (!I.getType()->isVoidTy()) {
3820 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3821 VTs, &Ops[0], Ops.size());
3823 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3824 VTs, &Ops[0], Ops.size());
3828 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3830 PendingLoads.push_back(Chain);
3835 if (!I.getType()->isVoidTy()) {
3836 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3837 EVT VT = TLI->getValueType(PTy);
3838 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3841 setValue(&I, Result);
3845 /// GetSignificand - Get the significand and build it into a floating-point
3846 /// number with exponent of 1:
3848 /// Op = (Op & 0x007fffff) | 0x3f800000;
3850 /// where Op is the hexadecimal representation of floating point value.
3852 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3853 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3854 DAG.getConstant(0x007fffff, MVT::i32));
3855 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3856 DAG.getConstant(0x3f800000, MVT::i32));
3857 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3860 /// GetExponent - Get the exponent:
3862 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3864 /// where Op is the hexadecimal representation of floating point value.
3866 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3868 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3869 DAG.getConstant(0x7f800000, MVT::i32));
3870 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3871 DAG.getConstant(23, TLI.getPointerTy()));
3872 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3873 DAG.getConstant(127, MVT::i32));
3874 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3877 /// getF32Constant - Get 32-bit floating point constant.
3879 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3880 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3884 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3885 /// limited-precision mode.
3886 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3887 const TargetLowering &TLI) {
3888 if (Op.getValueType() == MVT::f32 &&
3889 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3891 // Put the exponent in the right bit position for later addition to the
3894 // #define LOG2OFe 1.4426950f
3895 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3896 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3897 getF32Constant(DAG, 0x3fb8aa3b));
3898 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3900 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3901 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3902 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3904 // IntegerPartOfX <<= 23;
3905 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3906 DAG.getConstant(23, TLI.getPointerTy()));
3908 SDValue TwoToFracPartOfX;
3909 if (LimitFloatPrecision <= 6) {
3910 // For floating-point precision of 6:
3912 // TwoToFractionalPartOfX =
3914 // (0.735607626f + 0.252464424f * x) * x;
3916 // error 0.0144103317, which is 6 bits
3917 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3918 getF32Constant(DAG, 0x3e814304));
3919 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3920 getF32Constant(DAG, 0x3f3c50c8));
3921 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3922 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3923 getF32Constant(DAG, 0x3f7f5e7e));
3924 } else if (LimitFloatPrecision <= 12) {
3925 // For floating-point precision of 12:
3927 // TwoToFractionalPartOfX =
3930 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3932 // 0.000107046256 error, which is 13 to 14 bits
3933 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3934 getF32Constant(DAG, 0x3da235e3));
3935 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3936 getF32Constant(DAG, 0x3e65b8f3));
3937 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3938 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3939 getF32Constant(DAG, 0x3f324b07));
3940 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3941 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3942 getF32Constant(DAG, 0x3f7ff8fd));
3943 } else { // LimitFloatPrecision <= 18
3944 // For floating-point precision of 18:
3946 // TwoToFractionalPartOfX =
3950 // (0.554906021e-1f +
3951 // (0.961591928e-2f +
3952 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3954 // error 2.47208000*10^(-7), which is better than 18 bits
3955 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3956 getF32Constant(DAG, 0x3924b03e));
3957 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3958 getF32Constant(DAG, 0x3ab24b87));
3959 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3960 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3961 getF32Constant(DAG, 0x3c1d8c17));
3962 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3963 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3964 getF32Constant(DAG, 0x3d634a1d));
3965 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3966 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3967 getF32Constant(DAG, 0x3e75fe14));
3968 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3969 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3970 getF32Constant(DAG, 0x3f317234));
3971 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3972 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3973 getF32Constant(DAG, 0x3f800000));
3976 // Add the exponent into the result in integer domain.
3977 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3978 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3979 DAG.getNode(ISD::ADD, dl, MVT::i32,
3980 t13, IntegerPartOfX));
3983 // No special expansion.
3984 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3987 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3988 /// limited-precision mode.
3989 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3990 const TargetLowering &TLI) {
3991 if (Op.getValueType() == MVT::f32 &&
3992 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3993 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3995 // Scale the exponent by log(2) [0.69314718f].
3996 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3997 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3998 getF32Constant(DAG, 0x3f317218));
4000 // Get the significand and build it into a floating-point number with
4002 SDValue X = GetSignificand(DAG, Op1, dl);
4004 SDValue LogOfMantissa;
4005 if (LimitFloatPrecision <= 6) {
4006 // For floating-point precision of 6:
4010 // (1.4034025f - 0.23903021f * x) * x;
4012 // error 0.0034276066, which is better than 8 bits
4013 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4014 getF32Constant(DAG, 0xbe74c456));
4015 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4016 getF32Constant(DAG, 0x3fb3a2b1));
4017 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4018 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4019 getF32Constant(DAG, 0x3f949a29));
4020 } else if (LimitFloatPrecision <= 12) {
4021 // For floating-point precision of 12:
4027 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4029 // error 0.000061011436, which is 14 bits
4030 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4031 getF32Constant(DAG, 0xbd67b6d6));
4032 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4033 getF32Constant(DAG, 0x3ee4f4b8));
4034 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4035 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4036 getF32Constant(DAG, 0x3fbc278b));
4037 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4038 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4039 getF32Constant(DAG, 0x40348e95));
4040 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4041 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4042 getF32Constant(DAG, 0x3fdef31a));
4043 } else { // LimitFloatPrecision <= 18
4044 // For floating-point precision of 18:
4052 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4054 // error 0.0000023660568, which is better than 18 bits
4055 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4056 getF32Constant(DAG, 0xbc91e5ac));
4057 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4058 getF32Constant(DAG, 0x3e4350aa));
4059 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4060 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4061 getF32Constant(DAG, 0x3f60d3e3));
4062 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4063 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4064 getF32Constant(DAG, 0x4011cdf0));
4065 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4066 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4067 getF32Constant(DAG, 0x406cfd1c));
4068 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4069 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4070 getF32Constant(DAG, 0x408797cb));
4071 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4072 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4073 getF32Constant(DAG, 0x4006dcab));
4076 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4079 // No special expansion.
4080 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4083 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4084 /// limited-precision mode.
4085 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4086 const TargetLowering &TLI) {
4087 if (Op.getValueType() == MVT::f32 &&
4088 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4089 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4091 // Get the exponent.
4092 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4094 // Get the significand and build it into a floating-point number with
4096 SDValue X = GetSignificand(DAG, Op1, dl);
4098 // Different possible minimax approximations of significand in
4099 // floating-point for various degrees of accuracy over [1,2].
4100 SDValue Log2ofMantissa;
4101 if (LimitFloatPrecision <= 6) {
4102 // For floating-point precision of 6:
4104 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4106 // error 0.0049451742, which is more than 7 bits
4107 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4108 getF32Constant(DAG, 0xbeb08fe0));
4109 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4110 getF32Constant(DAG, 0x40019463));
4111 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4112 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4113 getF32Constant(DAG, 0x3fd6633d));
4114 } else if (LimitFloatPrecision <= 12) {
4115 // For floating-point precision of 12:
4121 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4123 // error 0.0000876136000, which is better than 13 bits
4124 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4125 getF32Constant(DAG, 0xbda7262e));
4126 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4127 getF32Constant(DAG, 0x3f25280b));
4128 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4129 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4130 getF32Constant(DAG, 0x4007b923));
4131 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4132 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4133 getF32Constant(DAG, 0x40823e2f));
4134 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4135 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4136 getF32Constant(DAG, 0x4020d29c));
4137 } else { // LimitFloatPrecision <= 18
4138 // For floating-point precision of 18:
4147 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4149 // error 0.0000018516, which is better than 18 bits
4150 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4151 getF32Constant(DAG, 0xbcd2769e));
4152 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4153 getF32Constant(DAG, 0x3e8ce0b9));
4154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4155 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4156 getF32Constant(DAG, 0x3fa22ae7));
4157 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4158 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4159 getF32Constant(DAG, 0x40525723));
4160 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4161 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4162 getF32Constant(DAG, 0x40aaf200));
4163 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4164 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4165 getF32Constant(DAG, 0x40c39dad));
4166 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4167 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4168 getF32Constant(DAG, 0x4042902c));
4171 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4174 // No special expansion.
4175 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4178 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4179 /// limited-precision mode.
4180 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4181 const TargetLowering &TLI) {
4182 if (Op.getValueType() == MVT::f32 &&
4183 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4184 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4186 // Scale the exponent by log10(2) [0.30102999f].
4187 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4188 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4189 getF32Constant(DAG, 0x3e9a209a));
4191 // Get the significand and build it into a floating-point number with
4193 SDValue X = GetSignificand(DAG, Op1, dl);
4195 SDValue Log10ofMantissa;
4196 if (LimitFloatPrecision <= 6) {
4197 // For floating-point precision of 6:
4199 // Log10ofMantissa =
4201 // (0.60948995f - 0.10380950f * x) * x;
4203 // error 0.0014886165, which is 6 bits
4204 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4205 getF32Constant(DAG, 0xbdd49a13));
4206 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4207 getF32Constant(DAG, 0x3f1c0789));
4208 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4209 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4210 getF32Constant(DAG, 0x3f011300));
4211 } else if (LimitFloatPrecision <= 12) {
4212 // For floating-point precision of 12:
4214 // Log10ofMantissa =
4217 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4219 // error 0.00019228036, which is better than 12 bits
4220 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4221 getF32Constant(DAG, 0x3d431f31));
4222 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4223 getF32Constant(DAG, 0x3ea21fb2));
4224 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4225 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4226 getF32Constant(DAG, 0x3f6ae232));
4227 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4228 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4229 getF32Constant(DAG, 0x3f25f7c3));
4230 } else { // LimitFloatPrecision <= 18
4231 // For floating-point precision of 18:
4233 // Log10ofMantissa =
4238 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4240 // error 0.0000037995730, which is better than 18 bits
4241 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4242 getF32Constant(DAG, 0x3c5d51ce));
4243 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4244 getF32Constant(DAG, 0x3e00685a));
4245 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4246 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4247 getF32Constant(DAG, 0x3efb6798));
4248 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4249 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4250 getF32Constant(DAG, 0x3f88d192));
4251 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4252 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4253 getF32Constant(DAG, 0x3fc4316c));
4254 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4255 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4256 getF32Constant(DAG, 0x3f57ce70));
4259 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4262 // No special expansion.
4263 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4266 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4267 /// limited-precision mode.
4268 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4269 const TargetLowering &TLI) {
4270 if (Op.getValueType() == MVT::f32 &&
4271 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4272 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4274 // FractionalPartOfX = x - (float)IntegerPartOfX;
4275 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4276 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4278 // IntegerPartOfX <<= 23;
4279 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4280 DAG.getConstant(23, TLI.getPointerTy()));
4282 SDValue TwoToFractionalPartOfX;
4283 if (LimitFloatPrecision <= 6) {
4284 // For floating-point precision of 6:
4286 // TwoToFractionalPartOfX =
4288 // (0.735607626f + 0.252464424f * x) * x;
4290 // error 0.0144103317, which is 6 bits
4291 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4292 getF32Constant(DAG, 0x3e814304));
4293 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4294 getF32Constant(DAG, 0x3f3c50c8));
4295 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4296 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4297 getF32Constant(DAG, 0x3f7f5e7e));
4298 } else if (LimitFloatPrecision <= 12) {
4299 // For floating-point precision of 12:
4301 // TwoToFractionalPartOfX =
4304 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4306 // error 0.000107046256, which is 13 to 14 bits
4307 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4308 getF32Constant(DAG, 0x3da235e3));
4309 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4310 getF32Constant(DAG, 0x3e65b8f3));
4311 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4312 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4313 getF32Constant(DAG, 0x3f324b07));
4314 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4315 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4316 getF32Constant(DAG, 0x3f7ff8fd));
4317 } else { // LimitFloatPrecision <= 18
4318 // For floating-point precision of 18:
4320 // TwoToFractionalPartOfX =
4324 // (0.554906021e-1f +
4325 // (0.961591928e-2f +
4326 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4327 // error 2.47208000*10^(-7), which is better than 18 bits
4328 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4329 getF32Constant(DAG, 0x3924b03e));
4330 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4331 getF32Constant(DAG, 0x3ab24b87));
4332 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4333 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4334 getF32Constant(DAG, 0x3c1d8c17));
4335 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4336 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4337 getF32Constant(DAG, 0x3d634a1d));
4338 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4339 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4340 getF32Constant(DAG, 0x3e75fe14));
4341 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4342 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4343 getF32Constant(DAG, 0x3f317234));
4344 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4345 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4346 getF32Constant(DAG, 0x3f800000));
4349 // Add the exponent into the result in integer domain.
4350 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4351 TwoToFractionalPartOfX);
4352 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4353 DAG.getNode(ISD::ADD, dl, MVT::i32,
4354 t13, IntegerPartOfX));
4357 // No special expansion.
4358 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4361 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4362 /// limited-precision mode with x == 10.0f.
4363 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4364 SelectionDAG &DAG, const TargetLowering &TLI) {
4365 bool IsExp10 = false;
4366 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4367 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4368 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4370 IsExp10 = LHSC->isExactlyValue(Ten);
4375 // Put the exponent in the right bit position for later addition to the
4378 // #define LOG2OF10 3.3219281f
4379 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4380 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4381 getF32Constant(DAG, 0x40549a78));
4382 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4384 // FractionalPartOfX = x - (float)IntegerPartOfX;
4385 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4386 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4388 // IntegerPartOfX <<= 23;
4389 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4390 DAG.getConstant(23, TLI.getPointerTy()));
4392 SDValue TwoToFractionalPartOfX;
4393 if (LimitFloatPrecision <= 6) {
4394 // For floating-point precision of 6:
4396 // twoToFractionalPartOfX =
4398 // (0.735607626f + 0.252464424f * x) * x;
4400 // error 0.0144103317, which is 6 bits
4401 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4402 getF32Constant(DAG, 0x3e814304));
4403 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4404 getF32Constant(DAG, 0x3f3c50c8));
4405 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4406 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4407 getF32Constant(DAG, 0x3f7f5e7e));
4408 } else if (LimitFloatPrecision <= 12) {
4409 // For floating-point precision of 12:
4411 // TwoToFractionalPartOfX =
4414 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4416 // error 0.000107046256, which is 13 to 14 bits
4417 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4418 getF32Constant(DAG, 0x3da235e3));
4419 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4420 getF32Constant(DAG, 0x3e65b8f3));
4421 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4422 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4423 getF32Constant(DAG, 0x3f324b07));
4424 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4425 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4426 getF32Constant(DAG, 0x3f7ff8fd));
4427 } else { // LimitFloatPrecision <= 18
4428 // For floating-point precision of 18:
4430 // TwoToFractionalPartOfX =
4434 // (0.554906021e-1f +
4435 // (0.961591928e-2f +
4436 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4437 // error 2.47208000*10^(-7), which is better than 18 bits
4438 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4439 getF32Constant(DAG, 0x3924b03e));
4440 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4441 getF32Constant(DAG, 0x3ab24b87));
4442 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4443 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4444 getF32Constant(DAG, 0x3c1d8c17));
4445 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4446 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4447 getF32Constant(DAG, 0x3d634a1d));
4448 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4449 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4450 getF32Constant(DAG, 0x3e75fe14));
4451 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4452 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4453 getF32Constant(DAG, 0x3f317234));
4454 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4455 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4456 getF32Constant(DAG, 0x3f800000));
4459 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4460 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4461 DAG.getNode(ISD::ADD, dl, MVT::i32,
4462 t13, IntegerPartOfX));
4465 // No special expansion.
4466 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4470 /// ExpandPowI - Expand a llvm.powi intrinsic.
4471 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4472 SelectionDAG &DAG) {
4473 // If RHS is a constant, we can expand this out to a multiplication tree,
4474 // otherwise we end up lowering to a call to __powidf2 (for example). When
4475 // optimizing for size, we only want to do this if the expansion would produce
4476 // a small number of multiplies, otherwise we do the full expansion.
4477 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4478 // Get the exponent as a positive value.
4479 unsigned Val = RHSC->getSExtValue();
4480 if ((int)Val < 0) Val = -Val;
4482 // powi(x, 0) -> 1.0
4484 return DAG.getConstantFP(1.0, LHS.getValueType());
4486 const Function *F = DAG.getMachineFunction().getFunction();
4487 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4488 Attribute::OptimizeForSize) ||
4489 // If optimizing for size, don't insert too many multiplies. This
4490 // inserts up to 5 multiplies.
4491 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4492 // We use the simple binary decomposition method to generate the multiply
4493 // sequence. There are more optimal ways to do this (for example,
4494 // powi(x,15) generates one more multiply than it should), but this has
4495 // the benefit of being both really simple and much better than a libcall.
4496 SDValue Res; // Logically starts equal to 1.0
4497 SDValue CurSquare = LHS;
4501 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4503 Res = CurSquare; // 1.0*CurSquare.
4506 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4507 CurSquare, CurSquare);
4511 // If the original was negative, invert the result, producing 1/(x*x*x).
4512 if (RHSC->getSExtValue() < 0)
4513 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4514 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4519 // Otherwise, expand to a libcall.
4520 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4523 // getTruncatedArgReg - Find underlying register used for an truncated
4525 static unsigned getTruncatedArgReg(const SDValue &N) {
4526 if (N.getOpcode() != ISD::TRUNCATE)
4529 const SDValue &Ext = N.getOperand(0);
4530 if (Ext.getOpcode() == ISD::AssertZext ||
4531 Ext.getOpcode() == ISD::AssertSext) {
4532 const SDValue &CFR = Ext.getOperand(0);
4533 if (CFR.getOpcode() == ISD::CopyFromReg)
4534 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4535 if (CFR.getOpcode() == ISD::TRUNCATE)
4536 return getTruncatedArgReg(CFR);
4541 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4542 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4543 /// At the end of instruction selection, they will be inserted to the entry BB.
4545 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4548 const Argument *Arg = dyn_cast<Argument>(V);
4552 MachineFunction &MF = DAG.getMachineFunction();
4553 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4555 // Ignore inlined function arguments here.
4556 DIVariable DV(Variable);
4557 if (DV.isInlinedFnArgument(MF.getFunction()))
4560 Optional<MachineOperand> Op;
4561 // Some arguments' frame index is recorded during argument lowering.
4562 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4563 Op = MachineOperand::CreateFI(FI);
4565 if (!Op && N.getNode()) {
4567 if (N.getOpcode() == ISD::CopyFromReg)
4568 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4570 Reg = getTruncatedArgReg(N);
4571 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4572 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4573 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4578 Op = MachineOperand::CreateReg(Reg, false);
4582 // Check if ValueMap has reg number.
4583 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4584 if (VMI != FuncInfo.ValueMap.end())
4585 Op = MachineOperand::CreateReg(VMI->second, false);
4588 if (!Op && N.getNode())
4589 // Check if frame index is available.
4590 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4591 if (FrameIndexSDNode *FINode =
4592 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4593 Op = MachineOperand::CreateFI(FINode->getIndex());
4598 // FIXME: This does not handle register-indirect values at offset 0.
4599 bool IsIndirect = Offset != 0;
4601 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4602 TII->get(TargetOpcode::DBG_VALUE),
4604 Op->getReg(), Offset, Variable));
4606 FuncInfo.ArgDbgValues.push_back(
4607 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4608 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4613 // VisualStudio defines setjmp as _setjmp
4614 #if defined(_MSC_VER) && defined(setjmp) && \
4615 !defined(setjmp_undefined_for_msvc)
4616 # pragma push_macro("setjmp")
4618 # define setjmp_undefined_for_msvc
4621 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4622 /// we want to emit this as a call to a named external function, return the name
4623 /// otherwise lower it and return null.
4625 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4626 const TargetLowering *TLI = TM.getTargetLowering();
4627 SDLoc sdl = getCurSDLoc();
4628 DebugLoc dl = getCurDebugLoc();
4631 switch (Intrinsic) {
4633 // By default, turn this into a target intrinsic node.
4634 visitTargetIntrinsic(I, Intrinsic);
4636 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4637 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4638 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4639 case Intrinsic::returnaddress:
4640 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4641 getValue(I.getArgOperand(0))));
4643 case Intrinsic::frameaddress:
4644 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4645 getValue(I.getArgOperand(0))));
4647 case Intrinsic::setjmp:
4648 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4649 case Intrinsic::longjmp:
4650 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4651 case Intrinsic::memcpy: {
4652 // Assert for address < 256 since we support only user defined address
4654 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4656 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4658 "Unknown address space");
4659 SDValue Op1 = getValue(I.getArgOperand(0));
4660 SDValue Op2 = getValue(I.getArgOperand(1));
4661 SDValue Op3 = getValue(I.getArgOperand(2));
4662 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4664 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4665 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4666 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4667 MachinePointerInfo(I.getArgOperand(0)),
4668 MachinePointerInfo(I.getArgOperand(1))));
4671 case Intrinsic::memset: {
4672 // Assert for address < 256 since we support only user defined address
4674 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4676 "Unknown address space");
4677 SDValue Op1 = getValue(I.getArgOperand(0));
4678 SDValue Op2 = getValue(I.getArgOperand(1));
4679 SDValue Op3 = getValue(I.getArgOperand(2));
4680 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4682 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4683 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4684 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4685 MachinePointerInfo(I.getArgOperand(0))));
4688 case Intrinsic::memmove: {
4689 // Assert for address < 256 since we support only user defined address
4691 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4693 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4695 "Unknown address space");
4696 SDValue Op1 = getValue(I.getArgOperand(0));
4697 SDValue Op2 = getValue(I.getArgOperand(1));
4698 SDValue Op3 = getValue(I.getArgOperand(2));
4699 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4701 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4702 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4703 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4704 MachinePointerInfo(I.getArgOperand(0)),
4705 MachinePointerInfo(I.getArgOperand(1))));
4708 case Intrinsic::dbg_declare: {
4709 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4710 MDNode *Variable = DI.getVariable();
4711 const Value *Address = DI.getAddress();
4712 DIVariable DIVar(Variable);
4713 assert((!DIVar || DIVar.isVariable()) &&
4714 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4715 if (!Address || !DIVar) {
4716 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4720 // Check if address has undef value.
4721 if (isa<UndefValue>(Address) ||
4722 (Address->use_empty() && !isa<Argument>(Address))) {
4723 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4727 SDValue &N = NodeMap[Address];
4728 if (!N.getNode() && isa<Argument>(Address))
4729 // Check unused arguments map.
4730 N = UnusedArgNodeMap[Address];
4733 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4734 Address = BCI->getOperand(0);
4735 // Parameters are handled specially.
4737 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4738 isa<Argument>(Address));
4740 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4742 if (isParameter && !AI) {
4743 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4745 // Byval parameter. We have a frame index at this point.
4746 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4747 0, dl, SDNodeOrder);
4749 // Address is an argument, so try to emit its dbg value using
4750 // virtual register info from the FuncInfo.ValueMap.
4751 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4755 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4756 0, dl, SDNodeOrder);
4758 // Can't do anything with other non-AI cases yet.
4759 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4760 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4761 DEBUG(Address->dump());
4764 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4766 // If Address is an argument then try to emit its dbg value using
4767 // virtual register info from the FuncInfo.ValueMap.
4768 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4769 // If variable is pinned by a alloca in dominating bb then
4770 // use StaticAllocaMap.
4771 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4772 if (AI->getParent() != DI.getParent()) {
4773 DenseMap<const AllocaInst*, int>::iterator SI =
4774 FuncInfo.StaticAllocaMap.find(AI);
4775 if (SI != FuncInfo.StaticAllocaMap.end()) {
4776 SDV = DAG.getDbgValue(Variable, SI->second,
4777 0, dl, SDNodeOrder);
4778 DAG.AddDbgValue(SDV, nullptr, false);
4783 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4788 case Intrinsic::dbg_value: {
4789 const DbgValueInst &DI = cast<DbgValueInst>(I);
4790 DIVariable DIVar(DI.getVariable());
4791 assert((!DIVar || DIVar.isVariable()) &&
4792 "Variable in DbgValueInst should be either null or a DIVariable.");
4796 MDNode *Variable = DI.getVariable();
4797 uint64_t Offset = DI.getOffset();
4798 const Value *V = DI.getValue();
4803 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4804 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4805 DAG.AddDbgValue(SDV, nullptr, false);
4807 // Do not use getValue() in here; we don't want to generate code at
4808 // this point if it hasn't been done yet.
4809 SDValue N = NodeMap[V];
4810 if (!N.getNode() && isa<Argument>(V))
4811 // Check unused arguments map.
4812 N = UnusedArgNodeMap[V];
4814 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4815 SDV = DAG.getDbgValue(Variable, N.getNode(),
4816 N.getResNo(), Offset, dl, SDNodeOrder);
4817 DAG.AddDbgValue(SDV, N.getNode(), false);
4819 } else if (!V->use_empty() ) {
4820 // Do not call getValue(V) yet, as we don't want to generate code.
4821 // Remember it for later.
4822 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4823 DanglingDebugInfoMap[V] = DDI;
4825 // We may expand this to cover more cases. One case where we have no
4826 // data available is an unreferenced parameter.
4827 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4831 // Build a debug info table entry.
4832 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4833 V = BCI->getOperand(0);
4834 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4835 // Don't handle byval struct arguments or VLAs, for example.
4837 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4838 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4841 DenseMap<const AllocaInst*, int>::iterator SI =
4842 FuncInfo.StaticAllocaMap.find(AI);
4843 if (SI == FuncInfo.StaticAllocaMap.end())
4844 return nullptr; // VLAs.
4845 int FI = SI->second;
4847 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4848 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4849 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4853 case Intrinsic::eh_typeid_for: {
4854 // Find the type id for the given typeinfo.
4855 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4856 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4857 Res = DAG.getConstant(TypeID, MVT::i32);
4862 case Intrinsic::eh_return_i32:
4863 case Intrinsic::eh_return_i64:
4864 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4865 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4868 getValue(I.getArgOperand(0)),
4869 getValue(I.getArgOperand(1))));
4871 case Intrinsic::eh_unwind_init:
4872 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4874 case Intrinsic::eh_dwarf_cfa: {
4875 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4876 TLI->getPointerTy());
4877 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4878 CfaArg.getValueType(),
4879 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4880 CfaArg.getValueType()),
4882 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4883 TLI->getPointerTy(),
4884 DAG.getConstant(0, TLI->getPointerTy()));
4885 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4889 case Intrinsic::eh_sjlj_callsite: {
4890 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4891 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4892 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4893 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4895 MMI.setCurrentCallSite(CI->getZExtValue());
4898 case Intrinsic::eh_sjlj_functioncontext: {
4899 // Get and store the index of the function context.
4900 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4902 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4903 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4904 MFI->setFunctionContextIndex(FI);
4907 case Intrinsic::eh_sjlj_setjmp: {
4910 Ops[1] = getValue(I.getArgOperand(0));
4911 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4912 DAG.getVTList(MVT::i32, MVT::Other),
4914 setValue(&I, Op.getValue(0));
4915 DAG.setRoot(Op.getValue(1));
4918 case Intrinsic::eh_sjlj_longjmp: {
4919 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4920 getRoot(), getValue(I.getArgOperand(0))));
4924 case Intrinsic::x86_mmx_pslli_w:
4925 case Intrinsic::x86_mmx_pslli_d:
4926 case Intrinsic::x86_mmx_pslli_q:
4927 case Intrinsic::x86_mmx_psrli_w:
4928 case Intrinsic::x86_mmx_psrli_d:
4929 case Intrinsic::x86_mmx_psrli_q:
4930 case Intrinsic::x86_mmx_psrai_w:
4931 case Intrinsic::x86_mmx_psrai_d: {
4932 SDValue ShAmt = getValue(I.getArgOperand(1));
4933 if (isa<ConstantSDNode>(ShAmt)) {
4934 visitTargetIntrinsic(I, Intrinsic);
4937 unsigned NewIntrinsic = 0;
4938 EVT ShAmtVT = MVT::v2i32;
4939 switch (Intrinsic) {
4940 case Intrinsic::x86_mmx_pslli_w:
4941 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4943 case Intrinsic::x86_mmx_pslli_d:
4944 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4946 case Intrinsic::x86_mmx_pslli_q:
4947 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4949 case Intrinsic::x86_mmx_psrli_w:
4950 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4952 case Intrinsic::x86_mmx_psrli_d:
4953 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4955 case Intrinsic::x86_mmx_psrli_q:
4956 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4958 case Intrinsic::x86_mmx_psrai_w:
4959 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4961 case Intrinsic::x86_mmx_psrai_d:
4962 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4964 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4967 // The vector shift intrinsics with scalars uses 32b shift amounts but
4968 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4970 // We must do this early because v2i32 is not a legal type.
4973 ShOps[1] = DAG.getConstant(0, MVT::i32);
4974 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4975 EVT DestVT = TLI->getValueType(I.getType());
4976 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4977 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4978 DAG.getConstant(NewIntrinsic, MVT::i32),
4979 getValue(I.getArgOperand(0)), ShAmt);
4983 case Intrinsic::x86_avx_vinsertf128_pd_256:
4984 case Intrinsic::x86_avx_vinsertf128_ps_256:
4985 case Intrinsic::x86_avx_vinsertf128_si_256:
4986 case Intrinsic::x86_avx2_vinserti128: {
4987 EVT DestVT = TLI->getValueType(I.getType());
4988 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4989 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4990 ElVT.getVectorNumElements();
4991 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4992 getValue(I.getArgOperand(0)),
4993 getValue(I.getArgOperand(1)),
4994 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4998 case Intrinsic::x86_avx_vextractf128_pd_256:
4999 case Intrinsic::x86_avx_vextractf128_ps_256:
5000 case Intrinsic::x86_avx_vextractf128_si_256:
5001 case Intrinsic::x86_avx2_vextracti128: {
5002 EVT DestVT = TLI->getValueType(I.getType());
5003 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5004 DestVT.getVectorNumElements();
5005 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5006 getValue(I.getArgOperand(0)),
5007 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5011 case Intrinsic::convertff:
5012 case Intrinsic::convertfsi:
5013 case Intrinsic::convertfui:
5014 case Intrinsic::convertsif:
5015 case Intrinsic::convertuif:
5016 case Intrinsic::convertss:
5017 case Intrinsic::convertsu:
5018 case Intrinsic::convertus:
5019 case Intrinsic::convertuu: {
5020 ISD::CvtCode Code = ISD::CVT_INVALID;
5021 switch (Intrinsic) {
5022 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5023 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5024 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5025 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5026 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5027 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5028 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5029 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5030 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5031 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5033 EVT DestVT = TLI->getValueType(I.getType());
5034 const Value *Op1 = I.getArgOperand(0);
5035 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5036 DAG.getValueType(DestVT),
5037 DAG.getValueType(getValue(Op1).getValueType()),
5038 getValue(I.getArgOperand(1)),
5039 getValue(I.getArgOperand(2)),
5044 case Intrinsic::powi:
5045 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5046 getValue(I.getArgOperand(1)), DAG));
5048 case Intrinsic::log:
5049 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5051 case Intrinsic::log2:
5052 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5054 case Intrinsic::log10:
5055 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5057 case Intrinsic::exp:
5058 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5060 case Intrinsic::exp2:
5061 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5063 case Intrinsic::pow:
5064 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5065 getValue(I.getArgOperand(1)), DAG, *TLI));
5067 case Intrinsic::sqrt:
5068 case Intrinsic::fabs:
5069 case Intrinsic::sin:
5070 case Intrinsic::cos:
5071 case Intrinsic::floor:
5072 case Intrinsic::ceil:
5073 case Intrinsic::trunc:
5074 case Intrinsic::rint:
5075 case Intrinsic::nearbyint:
5076 case Intrinsic::round: {
5078 switch (Intrinsic) {
5079 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5080 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5081 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5082 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5083 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5084 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5085 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5086 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5087 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5088 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5089 case Intrinsic::round: Opcode = ISD::FROUND; break;
5092 setValue(&I, DAG.getNode(Opcode, sdl,
5093 getValue(I.getArgOperand(0)).getValueType(),
5094 getValue(I.getArgOperand(0))));
5097 case Intrinsic::copysign:
5098 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5099 getValue(I.getArgOperand(0)).getValueType(),
5100 getValue(I.getArgOperand(0)),
5101 getValue(I.getArgOperand(1))));
5103 case Intrinsic::fma:
5104 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5105 getValue(I.getArgOperand(0)).getValueType(),
5106 getValue(I.getArgOperand(0)),
5107 getValue(I.getArgOperand(1)),
5108 getValue(I.getArgOperand(2))));
5110 case Intrinsic::fmuladd: {
5111 EVT VT = TLI->getValueType(I.getType());
5112 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5113 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5114 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5115 getValue(I.getArgOperand(0)).getValueType(),
5116 getValue(I.getArgOperand(0)),
5117 getValue(I.getArgOperand(1)),
5118 getValue(I.getArgOperand(2))));
5120 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5121 getValue(I.getArgOperand(0)).getValueType(),
5122 getValue(I.getArgOperand(0)),
5123 getValue(I.getArgOperand(1)));
5124 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5125 getValue(I.getArgOperand(0)).getValueType(),
5127 getValue(I.getArgOperand(2)));
5132 case Intrinsic::convert_to_fp16:
5133 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
5134 MVT::i16, getValue(I.getArgOperand(0))));
5136 case Intrinsic::convert_from_fp16:
5137 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
5138 MVT::f32, getValue(I.getArgOperand(0))));
5140 case Intrinsic::pcmarker: {
5141 SDValue Tmp = getValue(I.getArgOperand(0));
5142 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5145 case Intrinsic::readcyclecounter: {
5146 SDValue Op = getRoot();
5147 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5148 DAG.getVTList(MVT::i64, MVT::Other),
5151 DAG.setRoot(Res.getValue(1));
5154 case Intrinsic::bswap:
5155 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5156 getValue(I.getArgOperand(0)).getValueType(),
5157 getValue(I.getArgOperand(0))));
5159 case Intrinsic::cttz: {
5160 SDValue Arg = getValue(I.getArgOperand(0));
5161 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5162 EVT Ty = Arg.getValueType();
5163 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5167 case Intrinsic::ctlz: {
5168 SDValue Arg = getValue(I.getArgOperand(0));
5169 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5170 EVT Ty = Arg.getValueType();
5171 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5175 case Intrinsic::ctpop: {
5176 SDValue Arg = getValue(I.getArgOperand(0));
5177 EVT Ty = Arg.getValueType();
5178 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5181 case Intrinsic::stacksave: {
5182 SDValue Op = getRoot();
5183 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5184 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5186 DAG.setRoot(Res.getValue(1));
5189 case Intrinsic::stackrestore: {
5190 Res = getValue(I.getArgOperand(0));
5191 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5194 case Intrinsic::stackprotector: {
5195 // Emit code into the DAG to store the stack guard onto the stack.
5196 MachineFunction &MF = DAG.getMachineFunction();
5197 MachineFrameInfo *MFI = MF.getFrameInfo();
5198 EVT PtrTy = TLI->getPointerTy();
5200 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5201 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5203 int FI = FuncInfo.StaticAllocaMap[Slot];
5204 MFI->setStackProtectorIndex(FI);
5206 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5208 // Store the stack protector onto the stack.
5209 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5210 MachinePointerInfo::getFixedStack(FI),
5216 case Intrinsic::objectsize: {
5217 // If we don't know by now, we're never going to know.
5218 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5220 assert(CI && "Non-constant type in __builtin_object_size?");
5222 SDValue Arg = getValue(I.getCalledValue());
5223 EVT Ty = Arg.getValueType();
5226 Res = DAG.getConstant(-1ULL, Ty);
5228 Res = DAG.getConstant(0, Ty);
5233 case Intrinsic::annotation:
5234 case Intrinsic::ptr_annotation:
5235 // Drop the intrinsic, but forward the value
5236 setValue(&I, getValue(I.getOperand(0)));
5238 case Intrinsic::var_annotation:
5239 // Discard annotate attributes
5242 case Intrinsic::init_trampoline: {
5243 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5247 Ops[1] = getValue(I.getArgOperand(0));
5248 Ops[2] = getValue(I.getArgOperand(1));
5249 Ops[3] = getValue(I.getArgOperand(2));
5250 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5251 Ops[5] = DAG.getSrcValue(F);
5253 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5258 case Intrinsic::adjust_trampoline: {
5259 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5260 TLI->getPointerTy(),
5261 getValue(I.getArgOperand(0))));
5264 case Intrinsic::gcroot:
5266 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5267 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5269 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5270 GFI->addStackRoot(FI->getIndex(), TypeMap);
5273 case Intrinsic::gcread:
5274 case Intrinsic::gcwrite:
5275 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5276 case Intrinsic::flt_rounds:
5277 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5280 case Intrinsic::expect: {
5281 // Just replace __builtin_expect(exp, c) with EXP.
5282 setValue(&I, getValue(I.getArgOperand(0)));
5286 case Intrinsic::debugtrap:
5287 case Intrinsic::trap: {
5288 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5289 if (TrapFuncName.empty()) {
5290 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5291 ISD::TRAP : ISD::DEBUGTRAP;
5292 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5295 TargetLowering::ArgListTy Args;
5297 CallLoweringInfo CLI(getRoot(), I.getType(),
5298 false, false, false, false, 0, CallingConv::C,
5299 /*isTailCall=*/false,
5300 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5301 DAG.getExternalSymbol(TrapFuncName.data(),
5302 TLI->getPointerTy()),
5304 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5305 DAG.setRoot(Result.second);
5309 case Intrinsic::uadd_with_overflow:
5310 case Intrinsic::sadd_with_overflow:
5311 case Intrinsic::usub_with_overflow:
5312 case Intrinsic::ssub_with_overflow:
5313 case Intrinsic::umul_with_overflow:
5314 case Intrinsic::smul_with_overflow: {
5316 switch (Intrinsic) {
5317 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5318 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5319 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5320 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5321 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5322 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5323 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5325 SDValue Op1 = getValue(I.getArgOperand(0));
5326 SDValue Op2 = getValue(I.getArgOperand(1));
5328 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5329 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5332 case Intrinsic::prefetch: {
5334 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5336 Ops[1] = getValue(I.getArgOperand(0));
5337 Ops[2] = getValue(I.getArgOperand(1));
5338 Ops[3] = getValue(I.getArgOperand(2));
5339 Ops[4] = getValue(I.getArgOperand(3));
5340 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5341 DAG.getVTList(MVT::Other),
5343 EVT::getIntegerVT(*Context, 8),
5344 MachinePointerInfo(I.getArgOperand(0)),
5346 false, /* volatile */
5348 rw==1)); /* write */
5351 case Intrinsic::lifetime_start:
5352 case Intrinsic::lifetime_end: {
5353 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5354 // Stack coloring is not enabled in O0, discard region information.
5355 if (TM.getOptLevel() == CodeGenOpt::None)
5358 SmallVector<Value *, 4> Allocas;
5359 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5361 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5362 E = Allocas.end(); Object != E; ++Object) {
5363 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5365 // Could not find an Alloca.
5366 if (!LifetimeObject)
5369 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5373 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5374 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5376 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5381 case Intrinsic::invariant_start:
5382 // Discard region information.
5383 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5385 case Intrinsic::invariant_end:
5386 // Discard region information.
5388 case Intrinsic::stackprotectorcheck: {
5389 // Do not actually emit anything for this basic block. Instead we initialize
5390 // the stack protector descriptor and export the guard variable so we can
5391 // access it in FinishBasicBlock.
5392 const BasicBlock *BB = I.getParent();
5393 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5394 ExportFromCurrentBlock(SPDescriptor.getGuard());
5396 // Flush our exports since we are going to process a terminator.
5397 (void)getControlRoot();
5400 case Intrinsic::clear_cache:
5401 return TLI->getClearCacheBuiltinName();
5402 case Intrinsic::donothing:
5405 case Intrinsic::experimental_stackmap: {
5409 case Intrinsic::experimental_patchpoint_void:
5410 case Intrinsic::experimental_patchpoint_i64: {
5417 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5419 MachineBasicBlock *LandingPad) {
5420 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5421 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5422 Type *RetTy = FTy->getReturnType();
5423 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5424 MCSymbol *BeginLabel = nullptr;
5426 TargetLowering::ArgListTy Args;
5427 TargetLowering::ArgListEntry Entry;
5428 Args.reserve(CS.arg_size());
5430 // Check whether the function can return without sret-demotion.
5431 SmallVector<ISD::OutputArg, 4> Outs;
5432 const TargetLowering *TLI = TM.getTargetLowering();
5433 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5435 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5436 DAG.getMachineFunction(),
5437 FTy->isVarArg(), Outs,
5440 SDValue DemoteStackSlot;
5441 int DemoteStackIdx = -100;
5443 if (!CanLowerReturn) {
5444 assert(!CS.hasInAllocaArgument() &&
5445 "sret demotion is incompatible with inalloca");
5446 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5447 FTy->getReturnType());
5448 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5449 FTy->getReturnType());
5450 MachineFunction &MF = DAG.getMachineFunction();
5451 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5452 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5454 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5455 Entry.Node = DemoteStackSlot;
5456 Entry.Ty = StackSlotPtrType;
5457 Entry.isSExt = false;
5458 Entry.isZExt = false;
5459 Entry.isInReg = false;
5460 Entry.isSRet = true;
5461 Entry.isNest = false;
5462 Entry.isByVal = false;
5463 Entry.isReturned = false;
5464 Entry.Alignment = Align;
5465 Args.push_back(Entry);
5466 RetTy = Type::getVoidTy(FTy->getContext());
5469 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5471 const Value *V = *i;
5474 if (V->getType()->isEmptyTy())
5477 SDValue ArgNode = getValue(V);
5478 Entry.Node = ArgNode; Entry.Ty = V->getType();
5480 // Skip the first return-type Attribute to get to params.
5481 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5482 Args.push_back(Entry);
5486 // Insert a label before the invoke call to mark the try range. This can be
5487 // used to detect deletion of the invoke via the MachineModuleInfo.
5488 BeginLabel = MMI.getContext().CreateTempSymbol();
5490 // For SjLj, keep track of which landing pads go with which invokes
5491 // so as to maintain the ordering of pads in the LSDA.
5492 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5493 if (CallSiteIndex) {
5494 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5495 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5497 // Now that the call site is handled, stop tracking it.
5498 MMI.setCurrentCallSite(0);
5501 // Both PendingLoads and PendingExports must be flushed here;
5502 // this call might not return.
5504 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5507 // Check if target-independent constraints permit a tail call here.
5508 // Target-dependent constraints are checked within TLI->LowerCallTo.
5509 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5513 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5515 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5516 assert((isTailCall || Result.second.getNode()) &&
5517 "Non-null chain expected with non-tail call!");
5518 assert((Result.second.getNode() || !Result.first.getNode()) &&
5519 "Null value expected with tail call!");
5520 if (Result.first.getNode()) {
5521 setValue(CS.getInstruction(), Result.first);
5522 } else if (!CanLowerReturn && Result.second.getNode()) {
5523 // The instruction result is the result of loading from the
5524 // hidden sret parameter.
5525 SmallVector<EVT, 1> PVTs;
5526 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5528 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5529 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5530 EVT PtrVT = PVTs[0];
5532 SmallVector<EVT, 4> RetTys;
5533 SmallVector<uint64_t, 4> Offsets;
5534 RetTy = FTy->getReturnType();
5535 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5537 unsigned NumValues = RetTys.size();
5538 SmallVector<SDValue, 4> Values(NumValues);
5539 SmallVector<SDValue, 4> Chains(NumValues);
5541 for (unsigned i = 0; i < NumValues; ++i) {
5542 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5544 DAG.getConstant(Offsets[i], PtrVT));
5545 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5546 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5547 false, false, false, 1);
5549 Chains[i] = L.getValue(1);
5552 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5553 MVT::Other, &Chains[0], NumValues);
5554 PendingLoads.push_back(Chain);
5556 setValue(CS.getInstruction(),
5557 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5558 DAG.getVTList(RetTys),
5559 &Values[0], Values.size()));
5562 if (!Result.second.getNode()) {
5563 // As a special case, a null chain means that a tail call has been emitted
5564 // and the DAG root is already updated.
5567 // Since there's no actual continuation from this block, nothing can be
5568 // relying on us setting vregs for them.
5569 PendingExports.clear();
5571 DAG.setRoot(Result.second);
5575 // Insert a label at the end of the invoke call to mark the try range. This
5576 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5577 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5578 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5580 // Inform MachineModuleInfo of range.
5581 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5585 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5586 /// value is equal or not-equal to zero.
5587 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5588 for (const User *U : V->users()) {
5589 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5590 if (IC->isEquality())
5591 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5592 if (C->isNullValue())
5594 // Unknown instruction.
5600 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5602 SelectionDAGBuilder &Builder) {
5604 // Check to see if this load can be trivially constant folded, e.g. if the
5605 // input is from a string literal.
5606 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5607 // Cast pointer to the type we really want to load.
5608 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5609 PointerType::getUnqual(LoadTy));
5611 if (const Constant *LoadCst =
5612 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5614 return Builder.getValue(LoadCst);
5617 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5618 // still constant memory, the input chain can be the entry node.
5620 bool ConstantMemory = false;
5622 // Do not serialize (non-volatile) loads of constant memory with anything.
5623 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5624 Root = Builder.DAG.getEntryNode();
5625 ConstantMemory = true;
5627 // Do not serialize non-volatile loads against each other.
5628 Root = Builder.DAG.getRoot();
5631 SDValue Ptr = Builder.getValue(PtrVal);
5632 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5633 Ptr, MachinePointerInfo(PtrVal),
5635 false /*nontemporal*/,
5636 false /*isinvariant*/, 1 /* align=1 */);
5638 if (!ConstantMemory)
5639 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5643 /// processIntegerCallValue - Record the value for an instruction that
5644 /// produces an integer result, converting the type where necessary.
5645 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5648 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true);
5650 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5652 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5653 setValue(&I, Value);
5656 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5657 /// If so, return true and lower it, otherwise return false and it will be
5658 /// lowered like a normal call.
5659 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5660 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5661 if (I.getNumArgOperands() != 3)
5664 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5665 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5666 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5667 !I.getType()->isIntegerTy())
5670 const Value *Size = I.getArgOperand(2);
5671 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5672 if (CSize && CSize->getZExtValue() == 0) {
5673 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true);
5674 setValue(&I, DAG.getConstant(0, CallVT));
5678 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5679 std::pair<SDValue, SDValue> Res =
5680 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5681 getValue(LHS), getValue(RHS), getValue(Size),
5682 MachinePointerInfo(LHS),
5683 MachinePointerInfo(RHS));
5684 if (Res.first.getNode()) {
5685 processIntegerCallValue(I, Res.first, true);
5686 PendingLoads.push_back(Res.second);
5690 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5691 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5692 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5693 bool ActuallyDoIt = true;
5696 switch (CSize->getZExtValue()) {
5698 LoadVT = MVT::Other;
5700 ActuallyDoIt = false;
5704 LoadTy = Type::getInt16Ty(CSize->getContext());
5708 LoadTy = Type::getInt32Ty(CSize->getContext());
5712 LoadTy = Type::getInt64Ty(CSize->getContext());
5716 LoadVT = MVT::v4i32;
5717 LoadTy = Type::getInt32Ty(CSize->getContext());
5718 LoadTy = VectorType::get(LoadTy, 4);
5723 // This turns into unaligned loads. We only do this if the target natively
5724 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5725 // we'll only produce a small number of byte loads.
5727 // Require that we can find a legal MVT, and only do this if the target
5728 // supports unaligned loads of that type. Expanding into byte loads would
5730 const TargetLowering *TLI = TM.getTargetLowering();
5731 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5732 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5733 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5734 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5735 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5736 if (!TLI->isTypeLegal(LoadVT) ||
5737 !TLI->allowsUnalignedMemoryAccesses(LoadVT, SrcAS) ||
5738 !TLI->allowsUnalignedMemoryAccesses(LoadVT, DstAS))
5739 ActuallyDoIt = false;
5743 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5744 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5746 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5748 processIntegerCallValue(I, Res, false);
5757 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5758 /// form. If so, return true and lower it, otherwise return false and it
5759 /// will be lowered like a normal call.
5760 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5761 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5762 if (I.getNumArgOperands() != 3)
5765 const Value *Src = I.getArgOperand(0);
5766 const Value *Char = I.getArgOperand(1);
5767 const Value *Length = I.getArgOperand(2);
5768 if (!Src->getType()->isPointerTy() ||
5769 !Char->getType()->isIntegerTy() ||
5770 !Length->getType()->isIntegerTy() ||
5771 !I.getType()->isPointerTy())
5774 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5775 std::pair<SDValue, SDValue> Res =
5776 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5777 getValue(Src), getValue(Char), getValue(Length),
5778 MachinePointerInfo(Src));
5779 if (Res.first.getNode()) {
5780 setValue(&I, Res.first);
5781 PendingLoads.push_back(Res.second);
5788 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5789 /// optimized form. If so, return true and lower it, otherwise return false
5790 /// and it will be lowered like a normal call.
5791 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5792 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5793 if (I.getNumArgOperands() != 2)
5796 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5797 if (!Arg0->getType()->isPointerTy() ||
5798 !Arg1->getType()->isPointerTy() ||
5799 !I.getType()->isPointerTy())
5802 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5803 std::pair<SDValue, SDValue> Res =
5804 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5805 getValue(Arg0), getValue(Arg1),
5806 MachinePointerInfo(Arg0),
5807 MachinePointerInfo(Arg1), isStpcpy);
5808 if (Res.first.getNode()) {
5809 setValue(&I, Res.first);
5810 DAG.setRoot(Res.second);
5817 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5818 /// If so, return true and lower it, otherwise return false and it will be
5819 /// lowered like a normal call.
5820 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5821 // Verify that the prototype makes sense. int strcmp(void*,void*)
5822 if (I.getNumArgOperands() != 2)
5825 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5826 if (!Arg0->getType()->isPointerTy() ||
5827 !Arg1->getType()->isPointerTy() ||
5828 !I.getType()->isIntegerTy())
5831 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5832 std::pair<SDValue, SDValue> Res =
5833 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5834 getValue(Arg0), getValue(Arg1),
5835 MachinePointerInfo(Arg0),
5836 MachinePointerInfo(Arg1));
5837 if (Res.first.getNode()) {
5838 processIntegerCallValue(I, Res.first, true);
5839 PendingLoads.push_back(Res.second);
5846 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5847 /// form. If so, return true and lower it, otherwise return false and it
5848 /// will be lowered like a normal call.
5849 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5850 // Verify that the prototype makes sense. size_t strlen(char *)
5851 if (I.getNumArgOperands() != 1)
5854 const Value *Arg0 = I.getArgOperand(0);
5855 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5858 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5859 std::pair<SDValue, SDValue> Res =
5860 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5861 getValue(Arg0), MachinePointerInfo(Arg0));
5862 if (Res.first.getNode()) {
5863 processIntegerCallValue(I, Res.first, false);
5864 PendingLoads.push_back(Res.second);
5871 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5872 /// form. If so, return true and lower it, otherwise return false and it
5873 /// will be lowered like a normal call.
5874 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5875 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5876 if (I.getNumArgOperands() != 2)
5879 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5880 if (!Arg0->getType()->isPointerTy() ||
5881 !Arg1->getType()->isIntegerTy() ||
5882 !I.getType()->isIntegerTy())
5885 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5886 std::pair<SDValue, SDValue> Res =
5887 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5888 getValue(Arg0), getValue(Arg1),
5889 MachinePointerInfo(Arg0));
5890 if (Res.first.getNode()) {
5891 processIntegerCallValue(I, Res.first, false);
5892 PendingLoads.push_back(Res.second);
5899 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5900 /// operation (as expected), translate it to an SDNode with the specified opcode
5901 /// and return true.
5902 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5904 // Sanity check that it really is a unary floating-point call.
5905 if (I.getNumArgOperands() != 1 ||
5906 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5907 I.getType() != I.getArgOperand(0)->getType() ||
5908 !I.onlyReadsMemory())
5911 SDValue Tmp = getValue(I.getArgOperand(0));
5912 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5916 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5917 // Handle inline assembly differently.
5918 if (isa<InlineAsm>(I.getCalledValue())) {
5923 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5924 ComputeUsesVAFloatArgument(I, &MMI);
5926 const char *RenameFn = nullptr;
5927 if (Function *F = I.getCalledFunction()) {
5928 if (F->isDeclaration()) {
5929 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5930 if (unsigned IID = II->getIntrinsicID(F)) {
5931 RenameFn = visitIntrinsicCall(I, IID);
5936 if (unsigned IID = F->getIntrinsicID()) {
5937 RenameFn = visitIntrinsicCall(I, IID);
5943 // Check for well-known libc/libm calls. If the function is internal, it
5944 // can't be a library call.
5946 if (!F->hasLocalLinkage() && F->hasName() &&
5947 LibInfo->getLibFunc(F->getName(), Func) &&
5948 LibInfo->hasOptimizedCodeGen(Func)) {
5951 case LibFunc::copysign:
5952 case LibFunc::copysignf:
5953 case LibFunc::copysignl:
5954 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5955 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5956 I.getType() == I.getArgOperand(0)->getType() &&
5957 I.getType() == I.getArgOperand(1)->getType() &&
5958 I.onlyReadsMemory()) {
5959 SDValue LHS = getValue(I.getArgOperand(0));
5960 SDValue RHS = getValue(I.getArgOperand(1));
5961 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5962 LHS.getValueType(), LHS, RHS));
5967 case LibFunc::fabsf:
5968 case LibFunc::fabsl:
5969 if (visitUnaryFloatCall(I, ISD::FABS))
5975 if (visitUnaryFloatCall(I, ISD::FSIN))
5981 if (visitUnaryFloatCall(I, ISD::FCOS))
5985 case LibFunc::sqrtf:
5986 case LibFunc::sqrtl:
5987 case LibFunc::sqrt_finite:
5988 case LibFunc::sqrtf_finite:
5989 case LibFunc::sqrtl_finite:
5990 if (visitUnaryFloatCall(I, ISD::FSQRT))
5993 case LibFunc::floor:
5994 case LibFunc::floorf:
5995 case LibFunc::floorl:
5996 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5999 case LibFunc::nearbyint:
6000 case LibFunc::nearbyintf:
6001 case LibFunc::nearbyintl:
6002 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6006 case LibFunc::ceilf:
6007 case LibFunc::ceill:
6008 if (visitUnaryFloatCall(I, ISD::FCEIL))
6012 case LibFunc::rintf:
6013 case LibFunc::rintl:
6014 if (visitUnaryFloatCall(I, ISD::FRINT))
6017 case LibFunc::round:
6018 case LibFunc::roundf:
6019 case LibFunc::roundl:
6020 if (visitUnaryFloatCall(I, ISD::FROUND))
6023 case LibFunc::trunc:
6024 case LibFunc::truncf:
6025 case LibFunc::truncl:
6026 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6030 case LibFunc::log2f:
6031 case LibFunc::log2l:
6032 if (visitUnaryFloatCall(I, ISD::FLOG2))
6036 case LibFunc::exp2f:
6037 case LibFunc::exp2l:
6038 if (visitUnaryFloatCall(I, ISD::FEXP2))
6041 case LibFunc::memcmp:
6042 if (visitMemCmpCall(I))
6045 case LibFunc::memchr:
6046 if (visitMemChrCall(I))
6049 case LibFunc::strcpy:
6050 if (visitStrCpyCall(I, false))
6053 case LibFunc::stpcpy:
6054 if (visitStrCpyCall(I, true))
6057 case LibFunc::strcmp:
6058 if (visitStrCmpCall(I))
6061 case LibFunc::strlen:
6062 if (visitStrLenCall(I))
6065 case LibFunc::strnlen:
6066 if (visitStrNLenCall(I))
6075 Callee = getValue(I.getCalledValue());
6077 Callee = DAG.getExternalSymbol(RenameFn,
6078 TM.getTargetLowering()->getPointerTy());
6080 // Check if we can potentially perform a tail call. More detailed checking is
6081 // be done within LowerCallTo, after more information about the call is known.
6082 LowerCallTo(&I, Callee, I.isTailCall());
6087 /// AsmOperandInfo - This contains information for each constraint that we are
6089 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6091 /// CallOperand - If this is the result output operand or a clobber
6092 /// this is null, otherwise it is the incoming operand to the CallInst.
6093 /// This gets modified as the asm is processed.
6094 SDValue CallOperand;
6096 /// AssignedRegs - If this is a register or register class operand, this
6097 /// contains the set of register corresponding to the operand.
6098 RegsForValue AssignedRegs;
6100 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6101 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6104 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6105 /// corresponds to. If there is no Value* for this operand, it returns
6107 EVT getCallOperandValEVT(LLVMContext &Context,
6108 const TargetLowering &TLI,
6109 const DataLayout *DL) const {
6110 if (!CallOperandVal) return MVT::Other;
6112 if (isa<BasicBlock>(CallOperandVal))
6113 return TLI.getPointerTy();
6115 llvm::Type *OpTy = CallOperandVal->getType();
6117 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6118 // If this is an indirect operand, the operand is a pointer to the
6121 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6123 report_fatal_error("Indirect operand for inline asm not a pointer!");
6124 OpTy = PtrTy->getElementType();
6127 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6128 if (StructType *STy = dyn_cast<StructType>(OpTy))
6129 if (STy->getNumElements() == 1)
6130 OpTy = STy->getElementType(0);
6132 // If OpTy is not a single value, it may be a struct/union that we
6133 // can tile with integers.
6134 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6135 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6144 OpTy = IntegerType::get(Context, BitSize);
6149 return TLI.getValueType(OpTy, true);
6153 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6155 } // end anonymous namespace
6157 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6158 /// specified operand. We prefer to assign virtual registers, to allow the
6159 /// register allocator to handle the assignment process. However, if the asm
6160 /// uses features that we can't model on machineinstrs, we have SDISel do the
6161 /// allocation. This produces generally horrible, but correct, code.
6163 /// OpInfo describes the operand.
6165 static void GetRegistersForValue(SelectionDAG &DAG,
6166 const TargetLowering &TLI,
6168 SDISelAsmOperandInfo &OpInfo) {
6169 LLVMContext &Context = *DAG.getContext();
6171 MachineFunction &MF = DAG.getMachineFunction();
6172 SmallVector<unsigned, 4> Regs;
6174 // If this is a constraint for a single physreg, or a constraint for a
6175 // register class, find it.
6176 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6177 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6178 OpInfo.ConstraintVT);
6180 unsigned NumRegs = 1;
6181 if (OpInfo.ConstraintVT != MVT::Other) {
6182 // If this is a FP input in an integer register (or visa versa) insert a bit
6183 // cast of the input value. More generally, handle any case where the input
6184 // value disagrees with the register class we plan to stick this in.
6185 if (OpInfo.Type == InlineAsm::isInput &&
6186 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6187 // Try to convert to the first EVT that the reg class contains. If the
6188 // types are identical size, use a bitcast to convert (e.g. two differing
6190 MVT RegVT = *PhysReg.second->vt_begin();
6191 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6192 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6193 RegVT, OpInfo.CallOperand);
6194 OpInfo.ConstraintVT = RegVT;
6195 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6196 // If the input is a FP value and we want it in FP registers, do a
6197 // bitcast to the corresponding integer type. This turns an f64 value
6198 // into i64, which can be passed with two i32 values on a 32-bit
6200 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6201 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6202 RegVT, OpInfo.CallOperand);
6203 OpInfo.ConstraintVT = RegVT;
6207 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6211 EVT ValueVT = OpInfo.ConstraintVT;
6213 // If this is a constraint for a specific physical register, like {r17},
6215 if (unsigned AssignedReg = PhysReg.first) {
6216 const TargetRegisterClass *RC = PhysReg.second;
6217 if (OpInfo.ConstraintVT == MVT::Other)
6218 ValueVT = *RC->vt_begin();
6220 // Get the actual register value type. This is important, because the user
6221 // may have asked for (e.g.) the AX register in i32 type. We need to
6222 // remember that AX is actually i16 to get the right extension.
6223 RegVT = *RC->vt_begin();
6225 // This is a explicit reference to a physical register.
6226 Regs.push_back(AssignedReg);
6228 // If this is an expanded reference, add the rest of the regs to Regs.
6230 TargetRegisterClass::iterator I = RC->begin();
6231 for (; *I != AssignedReg; ++I)
6232 assert(I != RC->end() && "Didn't find reg!");
6234 // Already added the first reg.
6236 for (; NumRegs; --NumRegs, ++I) {
6237 assert(I != RC->end() && "Ran out of registers to allocate!");
6242 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6246 // Otherwise, if this was a reference to an LLVM register class, create vregs
6247 // for this reference.
6248 if (const TargetRegisterClass *RC = PhysReg.second) {
6249 RegVT = *RC->vt_begin();
6250 if (OpInfo.ConstraintVT == MVT::Other)
6253 // Create the appropriate number of virtual registers.
6254 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6255 for (; NumRegs; --NumRegs)
6256 Regs.push_back(RegInfo.createVirtualRegister(RC));
6258 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6262 // Otherwise, we couldn't allocate enough registers for this.
6265 /// visitInlineAsm - Handle a call to an InlineAsm object.
6267 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6268 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6270 /// ConstraintOperands - Information about all of the constraints.
6271 SDISelAsmOperandInfoVector ConstraintOperands;
6273 const TargetLowering *TLI = TM.getTargetLowering();
6274 TargetLowering::AsmOperandInfoVector
6275 TargetConstraints = TLI->ParseConstraints(CS);
6277 bool hasMemory = false;
6279 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6280 unsigned ResNo = 0; // ResNo - The result number of the next output.
6281 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6282 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6283 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6285 MVT OpVT = MVT::Other;
6287 // Compute the value type for each operand.
6288 switch (OpInfo.Type) {
6289 case InlineAsm::isOutput:
6290 // Indirect outputs just consume an argument.
6291 if (OpInfo.isIndirect) {
6292 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6296 // The return value of the call is this value. As such, there is no
6297 // corresponding argument.
6298 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6299 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6300 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6302 assert(ResNo == 0 && "Asm only has one result!");
6303 OpVT = TLI->getSimpleValueType(CS.getType());
6307 case InlineAsm::isInput:
6308 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6310 case InlineAsm::isClobber:
6315 // If this is an input or an indirect output, process the call argument.
6316 // BasicBlocks are labels, currently appearing only in asm's.
6317 if (OpInfo.CallOperandVal) {
6318 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6319 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6321 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6324 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6328 OpInfo.ConstraintVT = OpVT;
6330 // Indirect operand accesses access memory.
6331 if (OpInfo.isIndirect)
6334 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6335 TargetLowering::ConstraintType
6336 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6337 if (CType == TargetLowering::C_Memory) {
6345 SDValue Chain, Flag;
6347 // We won't need to flush pending loads if this asm doesn't touch
6348 // memory and is nonvolatile.
6349 if (hasMemory || IA->hasSideEffects())
6352 Chain = DAG.getRoot();
6354 // Second pass over the constraints: compute which constraint option to use
6355 // and assign registers to constraints that want a specific physreg.
6356 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6357 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6359 // If this is an output operand with a matching input operand, look up the
6360 // matching input. If their types mismatch, e.g. one is an integer, the
6361 // other is floating point, or their sizes are different, flag it as an
6363 if (OpInfo.hasMatchingInput()) {
6364 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6366 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6367 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6368 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6369 OpInfo.ConstraintVT);
6370 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6371 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6372 Input.ConstraintVT);
6373 if ((OpInfo.ConstraintVT.isInteger() !=
6374 Input.ConstraintVT.isInteger()) ||
6375 (MatchRC.second != InputRC.second)) {
6376 report_fatal_error("Unsupported asm: input constraint"
6377 " with a matching output constraint of"
6378 " incompatible type!");
6380 Input.ConstraintVT = OpInfo.ConstraintVT;
6384 // Compute the constraint code and ConstraintType to use.
6385 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6387 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6388 OpInfo.Type == InlineAsm::isClobber)
6391 // If this is a memory input, and if the operand is not indirect, do what we
6392 // need to to provide an address for the memory input.
6393 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6394 !OpInfo.isIndirect) {
6395 assert((OpInfo.isMultipleAlternative ||
6396 (OpInfo.Type == InlineAsm::isInput)) &&
6397 "Can only indirectify direct input operands!");
6399 // Memory operands really want the address of the value. If we don't have
6400 // an indirect input, put it in the constpool if we can, otherwise spill
6401 // it to a stack slot.
6402 // TODO: This isn't quite right. We need to handle these according to
6403 // the addressing mode that the constraint wants. Also, this may take
6404 // an additional register for the computation and we don't want that
6407 // If the operand is a float, integer, or vector constant, spill to a
6408 // constant pool entry to get its address.
6409 const Value *OpVal = OpInfo.CallOperandVal;
6410 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6411 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6412 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6413 TLI->getPointerTy());
6415 // Otherwise, create a stack slot and emit a store to it before the
6417 Type *Ty = OpVal->getType();
6418 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6419 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6420 MachineFunction &MF = DAG.getMachineFunction();
6421 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6422 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6423 Chain = DAG.getStore(Chain, getCurSDLoc(),
6424 OpInfo.CallOperand, StackSlot,
6425 MachinePointerInfo::getFixedStack(SSFI),
6427 OpInfo.CallOperand = StackSlot;
6430 // There is no longer a Value* corresponding to this operand.
6431 OpInfo.CallOperandVal = nullptr;
6433 // It is now an indirect operand.
6434 OpInfo.isIndirect = true;
6437 // If this constraint is for a specific register, allocate it before
6439 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6440 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6443 // Second pass - Loop over all of the operands, assigning virtual or physregs
6444 // to register class operands.
6445 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6446 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6448 // C_Register operands have already been allocated, Other/Memory don't need
6450 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6451 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6454 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6455 std::vector<SDValue> AsmNodeOperands;
6456 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6457 AsmNodeOperands.push_back(
6458 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6459 TLI->getPointerTy()));
6461 // If we have a !srcloc metadata node associated with it, we want to attach
6462 // this to the ultimately generated inline asm machineinstr. To do this, we
6463 // pass in the third operand as this (potentially null) inline asm MDNode.
6464 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6465 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6467 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6468 // bits as operand 3.
6469 unsigned ExtraInfo = 0;
6470 if (IA->hasSideEffects())
6471 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6472 if (IA->isAlignStack())
6473 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6474 // Set the asm dialect.
6475 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6477 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6478 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6479 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6481 // Compute the constraint code and ConstraintType to use.
6482 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6484 // Ideally, we would only check against memory constraints. However, the
6485 // meaning of an other constraint can be target-specific and we can't easily
6486 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6487 // for other constriants as well.
6488 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6489 OpInfo.ConstraintType == TargetLowering::C_Other) {
6490 if (OpInfo.Type == InlineAsm::isInput)
6491 ExtraInfo |= InlineAsm::Extra_MayLoad;
6492 else if (OpInfo.Type == InlineAsm::isOutput)
6493 ExtraInfo |= InlineAsm::Extra_MayStore;
6494 else if (OpInfo.Type == InlineAsm::isClobber)
6495 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6499 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6500 TLI->getPointerTy()));
6502 // Loop over all of the inputs, copying the operand values into the
6503 // appropriate registers and processing the output regs.
6504 RegsForValue RetValRegs;
6506 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6507 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6509 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6510 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6512 switch (OpInfo.Type) {
6513 case InlineAsm::isOutput: {
6514 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6515 OpInfo.ConstraintType != TargetLowering::C_Register) {
6516 // Memory output, or 'other' output (e.g. 'X' constraint).
6517 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6519 // Add information to the INLINEASM node to know about this output.
6520 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6521 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6522 TLI->getPointerTy()));
6523 AsmNodeOperands.push_back(OpInfo.CallOperand);
6527 // Otherwise, this is a register or register class output.
6529 // Copy the output from the appropriate register. Find a register that
6531 if (OpInfo.AssignedRegs.Regs.empty()) {
6532 LLVMContext &Ctx = *DAG.getContext();
6533 Ctx.emitError(CS.getInstruction(),
6534 "couldn't allocate output register for constraint '" +
6535 Twine(OpInfo.ConstraintCode) + "'");
6539 // If this is an indirect operand, store through the pointer after the
6541 if (OpInfo.isIndirect) {
6542 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6543 OpInfo.CallOperandVal));
6545 // This is the result value of the call.
6546 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6547 // Concatenate this output onto the outputs list.
6548 RetValRegs.append(OpInfo.AssignedRegs);
6551 // Add information to the INLINEASM node to know that this register is
6554 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6555 ? InlineAsm::Kind_RegDefEarlyClobber
6556 : InlineAsm::Kind_RegDef,
6557 false, 0, DAG, AsmNodeOperands);
6560 case InlineAsm::isInput: {
6561 SDValue InOperandVal = OpInfo.CallOperand;
6563 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6564 // If this is required to match an output register we have already set,
6565 // just use its register.
6566 unsigned OperandNo = OpInfo.getMatchedOperand();
6568 // Scan until we find the definition we already emitted of this operand.
6569 // When we find it, create a RegsForValue operand.
6570 unsigned CurOp = InlineAsm::Op_FirstOperand;
6571 for (; OperandNo; --OperandNo) {
6572 // Advance to the next operand.
6574 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6575 assert((InlineAsm::isRegDefKind(OpFlag) ||
6576 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6577 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6578 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6582 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6583 if (InlineAsm::isRegDefKind(OpFlag) ||
6584 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6585 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6586 if (OpInfo.isIndirect) {
6587 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6588 LLVMContext &Ctx = *DAG.getContext();
6589 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6590 " don't know how to handle tied "
6591 "indirect register inputs");
6595 RegsForValue MatchedRegs;
6596 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6597 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6598 MatchedRegs.RegVTs.push_back(RegVT);
6599 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6600 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6602 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6603 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6605 LLVMContext &Ctx = *DAG.getContext();
6606 Ctx.emitError(CS.getInstruction(),
6607 "inline asm error: This value"
6608 " type register class is not natively supported!");
6612 // Use the produced MatchedRegs object to
6613 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6614 Chain, &Flag, CS.getInstruction());
6615 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6616 true, OpInfo.getMatchedOperand(),
6617 DAG, AsmNodeOperands);
6621 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6622 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6623 "Unexpected number of operands");
6624 // Add information to the INLINEASM node to know about this input.
6625 // See InlineAsm.h isUseOperandTiedToDef.
6626 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6627 OpInfo.getMatchedOperand());
6628 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6629 TLI->getPointerTy()));
6630 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6634 // Treat indirect 'X' constraint as memory.
6635 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6637 OpInfo.ConstraintType = TargetLowering::C_Memory;
6639 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6640 std::vector<SDValue> Ops;
6641 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6644 LLVMContext &Ctx = *DAG.getContext();
6645 Ctx.emitError(CS.getInstruction(),
6646 "invalid operand for inline asm constraint '" +
6647 Twine(OpInfo.ConstraintCode) + "'");
6651 // Add information to the INLINEASM node to know about this input.
6652 unsigned ResOpType =
6653 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6654 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6655 TLI->getPointerTy()));
6656 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6660 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6661 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6662 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6663 "Memory operands expect pointer values");
6665 // Add information to the INLINEASM node to know about this input.
6666 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6667 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6668 TLI->getPointerTy()));
6669 AsmNodeOperands.push_back(InOperandVal);
6673 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6674 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6675 "Unknown constraint type!");
6677 // TODO: Support this.
6678 if (OpInfo.isIndirect) {
6679 LLVMContext &Ctx = *DAG.getContext();
6680 Ctx.emitError(CS.getInstruction(),
6681 "Don't know how to handle indirect register inputs yet "
6682 "for constraint '" +
6683 Twine(OpInfo.ConstraintCode) + "'");
6687 // Copy the input into the appropriate registers.
6688 if (OpInfo.AssignedRegs.Regs.empty()) {
6689 LLVMContext &Ctx = *DAG.getContext();
6690 Ctx.emitError(CS.getInstruction(),
6691 "couldn't allocate input reg for constraint '" +
6692 Twine(OpInfo.ConstraintCode) + "'");
6696 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6697 Chain, &Flag, CS.getInstruction());
6699 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6700 DAG, AsmNodeOperands);
6703 case InlineAsm::isClobber: {
6704 // Add the clobbered value to the operand list, so that the register
6705 // allocator is aware that the physreg got clobbered.
6706 if (!OpInfo.AssignedRegs.Regs.empty())
6707 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6715 // Finish up input operands. Set the input chain and add the flag last.
6716 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6717 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6719 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6720 DAG.getVTList(MVT::Other, MVT::Glue),
6721 &AsmNodeOperands[0], AsmNodeOperands.size());
6722 Flag = Chain.getValue(1);
6724 // If this asm returns a register value, copy the result from that register
6725 // and set it as the value of the call.
6726 if (!RetValRegs.Regs.empty()) {
6727 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6728 Chain, &Flag, CS.getInstruction());
6730 // FIXME: Why don't we do this for inline asms with MRVs?
6731 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6732 EVT ResultType = TLI->getValueType(CS.getType());
6734 // If any of the results of the inline asm is a vector, it may have the
6735 // wrong width/num elts. This can happen for register classes that can
6736 // contain multiple different value types. The preg or vreg allocated may
6737 // not have the same VT as was expected. Convert it to the right type
6738 // with bit_convert.
6739 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6740 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6743 } else if (ResultType != Val.getValueType() &&
6744 ResultType.isInteger() && Val.getValueType().isInteger()) {
6745 // If a result value was tied to an input value, the computed result may
6746 // have a wider width than the expected result. Extract the relevant
6748 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6751 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6754 setValue(CS.getInstruction(), Val);
6755 // Don't need to use this as a chain in this case.
6756 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6760 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6762 // Process indirect outputs, first output all of the flagged copies out of
6764 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6765 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6766 const Value *Ptr = IndirectStoresToEmit[i].second;
6767 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6769 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6772 // Emit the non-flagged stores from the physregs.
6773 SmallVector<SDValue, 8> OutChains;
6774 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6775 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6776 StoresToEmit[i].first,
6777 getValue(StoresToEmit[i].second),
6778 MachinePointerInfo(StoresToEmit[i].second),
6780 OutChains.push_back(Val);
6783 if (!OutChains.empty())
6784 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6785 &OutChains[0], OutChains.size());
6790 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6791 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6792 MVT::Other, getRoot(),
6793 getValue(I.getArgOperand(0)),
6794 DAG.getSrcValue(I.getArgOperand(0))));
6797 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6798 const TargetLowering *TLI = TM.getTargetLowering();
6799 const DataLayout &DL = *TLI->getDataLayout();
6800 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6801 getRoot(), getValue(I.getOperand(0)),
6802 DAG.getSrcValue(I.getOperand(0)),
6803 DL.getABITypeAlignment(I.getType()));
6805 DAG.setRoot(V.getValue(1));
6808 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6809 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6810 MVT::Other, getRoot(),
6811 getValue(I.getArgOperand(0)),
6812 DAG.getSrcValue(I.getArgOperand(0))));
6815 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6816 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6817 MVT::Other, getRoot(),
6818 getValue(I.getArgOperand(0)),
6819 getValue(I.getArgOperand(1)),
6820 DAG.getSrcValue(I.getArgOperand(0)),
6821 DAG.getSrcValue(I.getArgOperand(1))));
6824 /// \brief Lower an argument list according to the target calling convention.
6826 /// \return A tuple of <return-value, token-chain>
6828 /// This is a helper for lowering intrinsics that follow a target calling
6829 /// convention or require stack pointer adjustment. Only a subset of the
6830 /// intrinsic's operands need to participate in the calling convention.
6831 std::pair<SDValue, SDValue>
6832 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6833 unsigned NumArgs, SDValue Callee,
6835 TargetLowering::ArgListTy Args;
6836 Args.reserve(NumArgs);
6838 // Populate the argument list.
6839 // Attributes for args start at offset 1, after the return attribute.
6840 ImmutableCallSite CS(&CI);
6841 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6842 ArgI != ArgE; ++ArgI) {
6843 const Value *V = CI.getOperand(ArgI);
6845 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6847 TargetLowering::ArgListEntry Entry;
6848 Entry.Node = getValue(V);
6849 Entry.Ty = V->getType();
6850 Entry.setAttributes(&CS, AttrI);
6851 Args.push_back(Entry);
6854 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6855 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false,
6856 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs,
6857 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false,
6858 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc());
6860 const TargetLowering *TLI = TM.getTargetLowering();
6861 return TLI->LowerCallTo(CLI);
6864 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6865 /// or patchpoint target node's operand list.
6867 /// Constants are converted to TargetConstants purely as an optimization to
6868 /// avoid constant materialization and register allocation.
6870 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6871 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6872 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6873 /// address materialization and register allocation, but may also be required
6874 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6875 /// alloca in the entry block, then the runtime may assume that the alloca's
6876 /// StackMap location can be read immediately after compilation and that the
6877 /// location is valid at any point during execution (this is similar to the
6878 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6879 /// only available in a register, then the runtime would need to trap when
6880 /// execution reaches the StackMap in order to read the alloca's location.
6881 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6882 SmallVectorImpl<SDValue> &Ops,
6883 SelectionDAGBuilder &Builder) {
6884 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6885 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6888 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6890 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6891 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6892 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6894 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6896 Ops.push_back(OpVal);
6900 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6901 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6902 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6903 // [live variables...])
6905 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6907 SDValue Chain, InFlag, Callee, NullPtr;
6908 SmallVector<SDValue, 32> Ops;
6910 SDLoc DL = getCurSDLoc();
6911 Callee = getValue(CI.getCalledValue());
6912 NullPtr = DAG.getIntPtrConstant(0, true);
6914 // The stackmap intrinsic only records the live variables (the arguemnts
6915 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6916 // intrinsic, this won't be lowered to a function call. This means we don't
6917 // have to worry about calling conventions and target specific lowering code.
6918 // Instead we perform the call lowering right here.
6920 // chain, flag = CALLSEQ_START(chain, 0)
6921 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6922 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6924 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6925 InFlag = Chain.getValue(1);
6927 // Add the <id> and <numBytes> constants.
6928 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6929 Ops.push_back(DAG.getTargetConstant(
6930 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6931 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6932 Ops.push_back(DAG.getTargetConstant(
6933 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6935 // Push live variables for the stack map.
6936 addStackMapLiveVars(CI, 2, Ops, *this);
6938 // We are not pushing any register mask info here on the operands list,
6939 // because the stackmap doesn't clobber anything.
6941 // Push the chain and the glue flag.
6942 Ops.push_back(Chain);
6943 Ops.push_back(InFlag);
6945 // Create the STACKMAP node.
6946 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6947 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6948 Chain = SDValue(SM, 0);
6949 InFlag = Chain.getValue(1);
6951 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6953 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6955 // Set the root to the target-lowered call chain.
6958 // Inform the Frame Information that we have a stackmap in this function.
6959 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6962 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6963 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6964 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6969 // [live variables...])
6971 CallingConv::ID CC = CI.getCallingConv();
6972 bool isAnyRegCC = CC == CallingConv::AnyReg;
6973 bool hasDef = !CI.getType()->isVoidTy();
6974 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6976 // Get the real number of arguments participating in the call <numArgs>
6977 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6978 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6980 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6981 // Intrinsics include all meta-operands up to but not including CC.
6982 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6983 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6984 "Not enough arguments provided to the patchpoint intrinsic");
6986 // For AnyRegCC the arguments are lowered later on manually.
6987 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6988 std::pair<SDValue, SDValue> Result =
6989 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6991 // Set the root to the target-lowered call chain.
6992 SDValue Chain = Result.second;
6995 SDNode *CallEnd = Chain.getNode();
6996 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6997 CallEnd = CallEnd->getOperand(0).getNode();
6999 /// Get a call instruction from the call sequence chain.
7000 /// Tail calls are not allowed.
7001 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7002 "Expected a callseq node.");
7003 SDNode *Call = CallEnd->getOperand(0).getNode();
7004 bool hasGlue = Call->getGluedNode();
7006 // Replace the target specific call node with the patchable intrinsic.
7007 SmallVector<SDValue, 8> Ops;
7009 // Add the <id> and <numBytes> constants.
7010 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7011 Ops.push_back(DAG.getTargetConstant(
7012 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7013 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7014 Ops.push_back(DAG.getTargetConstant(
7015 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7017 // Assume that the Callee is a constant address.
7018 // FIXME: handle function symbols in the future.
7020 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7021 /*isTarget=*/true));
7023 // Adjust <numArgs> to account for any arguments that have been passed on the
7025 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7026 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7027 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7028 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7030 // Add the calling convention
7031 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7033 // Add the arguments we omitted previously. The register allocator should
7034 // place these in any free register.
7036 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7037 Ops.push_back(getValue(CI.getArgOperand(i)));
7039 // Push the arguments from the call instruction up to the register mask.
7040 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7041 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7044 // Push live variables for the stack map.
7045 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7047 // Push the register mask info.
7049 Ops.push_back(*(Call->op_end()-2));
7051 Ops.push_back(*(Call->op_end()-1));
7053 // Push the chain (this is originally the first operand of the call, but
7054 // becomes now the last or second to last operand).
7055 Ops.push_back(*(Call->op_begin()));
7057 // Push the glue flag (last operand).
7059 Ops.push_back(*(Call->op_end()-1));
7062 if (isAnyRegCC && hasDef) {
7063 // Create the return types based on the intrinsic definition
7064 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7065 SmallVector<EVT, 3> ValueVTs;
7066 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7067 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7069 // There is always a chain and a glue type at the end
7070 ValueVTs.push_back(MVT::Other);
7071 ValueVTs.push_back(MVT::Glue);
7072 NodeTys = DAG.getVTList(ValueVTs);
7074 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7076 // Replace the target specific call node with a PATCHPOINT node.
7077 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7078 getCurSDLoc(), NodeTys, Ops);
7080 // Update the NodeMap.
7083 setValue(&CI, SDValue(MN, 0));
7085 setValue(&CI, Result.first);
7088 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7089 // call sequence. Furthermore the location of the chain and glue can change
7090 // when the AnyReg calling convention is used and the intrinsic returns a
7092 if (isAnyRegCC && hasDef) {
7093 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7094 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7095 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7097 DAG.ReplaceAllUsesWith(Call, MN);
7098 DAG.DeleteNode(Call);
7100 // Inform the Frame Information that we have a patchpoint in this function.
7101 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7104 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7105 /// implementation, which just calls LowerCall.
7106 /// FIXME: When all targets are
7107 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7108 std::pair<SDValue, SDValue>
7109 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7110 // Handle the incoming return values from the call.
7112 SmallVector<EVT, 4> RetTys;
7113 ComputeValueVTs(*this, CLI.RetTy, RetTys);
7114 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7116 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7117 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118 for (unsigned i = 0; i != NumRegs; ++i) {
7119 ISD::InputArg MyFlags;
7120 MyFlags.VT = RegisterVT;
7122 MyFlags.Used = CLI.IsReturnValueUsed;
7124 MyFlags.Flags.setSExt();
7126 MyFlags.Flags.setZExt();
7128 MyFlags.Flags.setInReg();
7129 CLI.Ins.push_back(MyFlags);
7133 // Handle all of the outgoing arguments.
7135 CLI.OutVals.clear();
7136 ArgListTy &Args = CLI.Args;
7137 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7138 SmallVector<EVT, 4> ValueVTs;
7139 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7140 for (unsigned Value = 0, NumValues = ValueVTs.size();
7141 Value != NumValues; ++Value) {
7142 EVT VT = ValueVTs[Value];
7143 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7144 SDValue Op = SDValue(Args[i].Node.getNode(),
7145 Args[i].Node.getResNo() + Value);
7146 ISD::ArgFlagsTy Flags;
7147 unsigned OriginalAlignment =
7148 getDataLayout()->getABITypeAlignment(ArgTy);
7154 if (Args[i].isInReg)
7158 if (Args[i].isByVal)
7160 if (Args[i].isInAlloca) {
7161 Flags.setInAlloca();
7162 // Set the byval flag for CCAssignFn callbacks that don't know about
7163 // inalloca. This way we can know how many bytes we should've allocated
7164 // and how many bytes a callee cleanup function will pop. If we port
7165 // inalloca to more targets, we'll have to add custom inalloca handling
7166 // in the various CC lowering callbacks.
7169 if (Args[i].isByVal || Args[i].isInAlloca) {
7170 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7171 Type *ElementTy = Ty->getElementType();
7172 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7173 // For ByVal, alignment should come from FE. BE will guess if this
7174 // info is not there but there are cases it cannot get right.
7175 unsigned FrameAlign;
7176 if (Args[i].Alignment)
7177 FrameAlign = Args[i].Alignment;
7179 FrameAlign = getByValTypeAlignment(ElementTy);
7180 Flags.setByValAlign(FrameAlign);
7184 Flags.setOrigAlign(OriginalAlignment);
7186 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7187 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7188 SmallVector<SDValue, 4> Parts(NumParts);
7189 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7192 ExtendKind = ISD::SIGN_EXTEND;
7193 else if (Args[i].isZExt)
7194 ExtendKind = ISD::ZERO_EXTEND;
7196 // Conservatively only handle 'returned' on non-vectors for now
7197 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7198 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7199 "unexpected use of 'returned'");
7200 // Before passing 'returned' to the target lowering code, ensure that
7201 // either the register MVT and the actual EVT are the same size or that
7202 // the return value and argument are extended in the same way; in these
7203 // cases it's safe to pass the argument register value unchanged as the
7204 // return register value (although it's at the target's option whether
7206 // TODO: allow code generation to take advantage of partially preserved
7207 // registers rather than clobbering the entire register when the
7208 // parameter extension method is not compatible with the return
7210 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7211 (ExtendKind != ISD::ANY_EXTEND &&
7212 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7213 Flags.setReturned();
7216 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7217 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7219 for (unsigned j = 0; j != NumParts; ++j) {
7220 // if it isn't first piece, alignment must be 1
7221 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7222 i < CLI.NumFixedArgs,
7223 i, j*Parts[j].getValueType().getStoreSize());
7224 if (NumParts > 1 && j == 0)
7225 MyFlags.Flags.setSplit();
7227 MyFlags.Flags.setOrigAlign(1);
7229 CLI.Outs.push_back(MyFlags);
7230 CLI.OutVals.push_back(Parts[j]);
7235 SmallVector<SDValue, 4> InVals;
7236 CLI.Chain = LowerCall(CLI, InVals);
7238 // Verify that the target's LowerCall behaved as expected.
7239 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7240 "LowerCall didn't return a valid chain!");
7241 assert((!CLI.IsTailCall || InVals.empty()) &&
7242 "LowerCall emitted a return value for a tail call!");
7243 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7244 "LowerCall didn't emit the correct number of values!");
7246 // For a tail call, the return value is merely live-out and there aren't
7247 // any nodes in the DAG representing it. Return a special value to
7248 // indicate that a tail call has been emitted and no more Instructions
7249 // should be processed in the current block.
7250 if (CLI.IsTailCall) {
7251 CLI.DAG.setRoot(CLI.Chain);
7252 return std::make_pair(SDValue(), SDValue());
7255 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7256 assert(InVals[i].getNode() &&
7257 "LowerCall emitted a null value!");
7258 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7259 "LowerCall emitted a value with the wrong type!");
7262 // Collect the legal value parts into potentially illegal values
7263 // that correspond to the original function's return values.
7264 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7266 AssertOp = ISD::AssertSext;
7267 else if (CLI.RetZExt)
7268 AssertOp = ISD::AssertZext;
7269 SmallVector<SDValue, 4> ReturnValues;
7270 unsigned CurReg = 0;
7271 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7273 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7274 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7276 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7277 NumRegs, RegisterVT, VT, nullptr,
7282 // For a function returning void, there is no return value. We can't create
7283 // such a node, so we just return a null return value in that case. In
7284 // that case, nothing will actually look at the value.
7285 if (ReturnValues.empty())
7286 return std::make_pair(SDValue(), CLI.Chain);
7288 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7289 CLI.DAG.getVTList(RetTys),
7290 &ReturnValues[0], ReturnValues.size());
7291 return std::make_pair(Res, CLI.Chain);
7294 void TargetLowering::LowerOperationWrapper(SDNode *N,
7295 SmallVectorImpl<SDValue> &Results,
7296 SelectionDAG &DAG) const {
7297 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7299 Results.push_back(Res);
7302 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7303 llvm_unreachable("LowerOperation not implemented for this target!");
7307 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7308 SDValue Op = getNonRegisterValue(V);
7309 assert((Op.getOpcode() != ISD::CopyFromReg ||
7310 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7311 "Copy from a reg to the same reg!");
7312 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7314 const TargetLowering *TLI = TM.getTargetLowering();
7315 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7316 SDValue Chain = DAG.getEntryNode();
7317 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V);
7318 PendingExports.push_back(Chain);
7321 #include "llvm/CodeGen/SelectionDAGISel.h"
7323 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7324 /// entry block, return true. This includes arguments used by switches, since
7325 /// the switch may expand into multiple basic blocks.
7326 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7327 // With FastISel active, we may be splitting blocks, so force creation
7328 // of virtual registers for all non-dead arguments.
7330 return A->use_empty();
7332 const BasicBlock *Entry = A->getParent()->begin();
7333 for (const User *U : A->users())
7334 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7335 return false; // Use not in entry block.
7340 void SelectionDAGISel::LowerArguments(const Function &F) {
7341 SelectionDAG &DAG = SDB->DAG;
7342 SDLoc dl = SDB->getCurSDLoc();
7343 const TargetLowering *TLI = getTargetLowering();
7344 const DataLayout *DL = TLI->getDataLayout();
7345 SmallVector<ISD::InputArg, 16> Ins;
7347 if (!FuncInfo->CanLowerReturn) {
7348 // Put in an sret pointer parameter before all the other parameters.
7349 SmallVector<EVT, 1> ValueVTs;
7350 ComputeValueVTs(*getTargetLowering(),
7351 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7353 // NOTE: Assuming that a pointer will never break down to more than one VT
7355 ISD::ArgFlagsTy Flags;
7357 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7358 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7359 Ins.push_back(RetArg);
7362 // Set up the incoming argument description vector.
7364 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7365 I != E; ++I, ++Idx) {
7366 SmallVector<EVT, 4> ValueVTs;
7367 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7368 bool isArgValueUsed = !I->use_empty();
7369 unsigned PartBase = 0;
7370 for (unsigned Value = 0, NumValues = ValueVTs.size();
7371 Value != NumValues; ++Value) {
7372 EVT VT = ValueVTs[Value];
7373 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7374 ISD::ArgFlagsTy Flags;
7375 unsigned OriginalAlignment =
7376 DL->getABITypeAlignment(ArgTy);
7378 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7380 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7382 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7384 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7386 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7388 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7389 Flags.setInAlloca();
7390 // Set the byval flag for CCAssignFn callbacks that don't know about
7391 // inalloca. This way we can know how many bytes we should've allocated
7392 // and how many bytes a callee cleanup function will pop. If we port
7393 // inalloca to more targets, we'll have to add custom inalloca handling
7394 // in the various CC lowering callbacks.
7397 if (Flags.isByVal() || Flags.isInAlloca()) {
7398 PointerType *Ty = cast<PointerType>(I->getType());
7399 Type *ElementTy = Ty->getElementType();
7400 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7401 // For ByVal, alignment should be passed from FE. BE will guess if
7402 // this info is not there but there are cases it cannot get right.
7403 unsigned FrameAlign;
7404 if (F.getParamAlignment(Idx))
7405 FrameAlign = F.getParamAlignment(Idx);
7407 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7408 Flags.setByValAlign(FrameAlign);
7410 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7412 Flags.setOrigAlign(OriginalAlignment);
7414 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7415 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7416 for (unsigned i = 0; i != NumRegs; ++i) {
7417 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7418 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7419 if (NumRegs > 1 && i == 0)
7420 MyFlags.Flags.setSplit();
7421 // if it isn't first piece, alignment must be 1
7423 MyFlags.Flags.setOrigAlign(1);
7424 Ins.push_back(MyFlags);
7426 PartBase += VT.getStoreSize();
7430 // Call the target to set up the argument values.
7431 SmallVector<SDValue, 8> InVals;
7432 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7436 // Verify that the target's LowerFormalArguments behaved as expected.
7437 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7438 "LowerFormalArguments didn't return a valid chain!");
7439 assert(InVals.size() == Ins.size() &&
7440 "LowerFormalArguments didn't emit the correct number of values!");
7442 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7443 assert(InVals[i].getNode() &&
7444 "LowerFormalArguments emitted a null value!");
7445 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7446 "LowerFormalArguments emitted a value with the wrong type!");
7450 // Update the DAG with the new chain value resulting from argument lowering.
7451 DAG.setRoot(NewRoot);
7453 // Set up the argument values.
7456 if (!FuncInfo->CanLowerReturn) {
7457 // Create a virtual register for the sret pointer, and put in a copy
7458 // from the sret argument into it.
7459 SmallVector<EVT, 1> ValueVTs;
7460 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7461 MVT VT = ValueVTs[0].getSimpleVT();
7462 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7463 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7464 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7465 RegVT, VT, nullptr, AssertOp);
7467 MachineFunction& MF = SDB->DAG.getMachineFunction();
7468 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7469 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7470 FuncInfo->DemoteRegister = SRetReg;
7471 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7473 DAG.setRoot(NewRoot);
7475 // i indexes lowered arguments. Bump it past the hidden sret argument.
7476 // Idx indexes LLVM arguments. Don't touch it.
7480 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7482 SmallVector<SDValue, 4> ArgValues;
7483 SmallVector<EVT, 4> ValueVTs;
7484 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7485 unsigned NumValues = ValueVTs.size();
7487 // If this argument is unused then remember its value. It is used to generate
7488 // debugging information.
7489 if (I->use_empty() && NumValues) {
7490 SDB->setUnusedArgValue(I, InVals[i]);
7492 // Also remember any frame index for use in FastISel.
7493 if (FrameIndexSDNode *FI =
7494 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7495 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7498 for (unsigned Val = 0; Val != NumValues; ++Val) {
7499 EVT VT = ValueVTs[Val];
7500 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7501 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7503 if (!I->use_empty()) {
7504 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7505 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7506 AssertOp = ISD::AssertSext;
7507 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7508 AssertOp = ISD::AssertZext;
7510 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7511 NumParts, PartVT, VT,
7512 nullptr, AssertOp));
7518 // We don't need to do anything else for unused arguments.
7519 if (ArgValues.empty())
7522 // Note down frame index.
7523 if (FrameIndexSDNode *FI =
7524 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7525 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7527 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7528 SDB->getCurSDLoc());
7530 SDB->setValue(I, Res);
7531 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7532 if (LoadSDNode *LNode =
7533 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7534 if (FrameIndexSDNode *FI =
7535 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7536 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7539 // If this argument is live outside of the entry block, insert a copy from
7540 // wherever we got it to the vreg that other BB's will reference it as.
7541 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7542 // If we can, though, try to skip creating an unnecessary vreg.
7543 // FIXME: This isn't very clean... it would be nice to make this more
7544 // general. It's also subtly incompatible with the hacks FastISel
7546 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7547 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7548 FuncInfo->ValueMap[I] = Reg;
7552 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7553 FuncInfo->InitializeRegForValue(I);
7554 SDB->CopyToExportRegsIfNeeded(I);
7558 assert(i == InVals.size() && "Argument register count mismatch!");
7560 // Finally, if the target has anything special to do, allow it to do so.
7561 // FIXME: this should insert code into the DAG!
7562 EmitFunctionEntryCode();
7565 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7566 /// ensure constants are generated when needed. Remember the virtual registers
7567 /// that need to be added to the Machine PHI nodes as input. We cannot just
7568 /// directly add them, because expansion might result in multiple MBB's for one
7569 /// BB. As such, the start of the BB might correspond to a different MBB than
7573 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7574 const TerminatorInst *TI = LLVMBB->getTerminator();
7576 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7578 // Check successor nodes' PHI nodes that expect a constant to be available
7580 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7581 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7582 if (!isa<PHINode>(SuccBB->begin())) continue;
7583 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7585 // If this terminator has multiple identical successors (common for
7586 // switches), only handle each succ once.
7587 if (!SuccsHandled.insert(SuccMBB)) continue;
7589 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7591 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7592 // nodes and Machine PHI nodes, but the incoming operands have not been
7594 for (BasicBlock::const_iterator I = SuccBB->begin();
7595 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7596 // Ignore dead phi's.
7597 if (PN->use_empty()) continue;
7600 if (PN->getType()->isEmptyTy())
7604 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7606 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7607 unsigned &RegOut = ConstantsOut[C];
7609 RegOut = FuncInfo.CreateRegs(C->getType());
7610 CopyValueToVirtualRegister(C, RegOut);
7614 DenseMap<const Value *, unsigned>::iterator I =
7615 FuncInfo.ValueMap.find(PHIOp);
7616 if (I != FuncInfo.ValueMap.end())
7619 assert(isa<AllocaInst>(PHIOp) &&
7620 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7621 "Didn't codegen value into a register!??");
7622 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7623 CopyValueToVirtualRegister(PHIOp, Reg);
7627 // Remember that this register needs to added to the machine PHI node as
7628 // the input for this MBB.
7629 SmallVector<EVT, 4> ValueVTs;
7630 const TargetLowering *TLI = TM.getTargetLowering();
7631 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7632 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7633 EVT VT = ValueVTs[vti];
7634 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7635 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7636 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7637 Reg += NumRegisters;
7642 ConstantsOut.clear();
7645 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7648 SelectionDAGBuilder::StackProtectorDescriptor::
7649 AddSuccessorMBB(const BasicBlock *BB,
7650 MachineBasicBlock *ParentMBB,
7651 MachineBasicBlock *SuccMBB) {
7652 // If SuccBB has not been created yet, create it.
7654 MachineFunction *MF = ParentMBB->getParent();
7655 MachineFunction::iterator BBI = ParentMBB;
7656 SuccMBB = MF->CreateMachineBasicBlock(BB);
7657 MF->insert(++BBI, SuccMBB);
7659 // Add it as a successor of ParentMBB.
7660 ParentMBB->addSuccessor(SuccMBB);