1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Interpret void as zero return values.
139 if (Ty == Type::VoidTy)
141 // Base case: we can get an MVT for this LLVM IR type.
142 ValueVTs.push_back(TLI.getValueType(Ty));
144 Offsets->push_back(StartingOffset);
148 /// RegsForValue - This struct represents the registers (physical or virtual)
149 /// that a particular set of values is assigned, and the type information about
150 /// the value. The most common situation is to represent one value at a time,
151 /// but struct or array values are handled element-wise as multiple values.
152 /// The splitting of aggregates is performed recursively, so that we never
153 /// have aggregate-typed registers. The values at this point do not necessarily
154 /// have legal types, so each value may require one or more registers of some
157 struct VISIBILITY_HIDDEN RegsForValue {
158 /// TLI - The TargetLowering object.
160 const TargetLowering *TLI;
162 /// ValueVTs - The value types of the values, which may not be legal, and
163 /// may need be promoted or synthesized from one or more registers.
165 SmallVector<MVT, 4> ValueVTs;
167 /// RegVTs - The value types of the registers. This is the same size as
168 /// ValueVTs and it records, for each value, what the type of the assigned
169 /// register or registers are. (Individual values are never synthesized
170 /// from more than one type of register.)
172 /// With virtual registers, the contents of RegVTs is redundant with TLI's
173 /// getRegisterType member function, however when with physical registers
174 /// it is necessary to have a separate record of the types.
176 SmallVector<MVT, 4> RegVTs;
178 /// Regs - This list holds the registers assigned to the values.
179 /// Each legal or promoted value requires one register, and each
180 /// expanded value requires multiple registers.
182 SmallVector<unsigned, 4> Regs;
184 RegsForValue() : TLI(0) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 MVT regvt, MVT valuevt)
189 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
190 RegsForValue(const TargetLowering &tli,
191 const SmallVector<unsigned, 4> ®s,
192 const SmallVector<MVT, 4> ®vts,
193 const SmallVector<MVT, 4> &valuevts)
194 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
195 RegsForValue(const TargetLowering &tli,
196 unsigned Reg, const Type *Ty) : TLI(&tli) {
197 ComputeValueVTs(tli, Ty, ValueVTs);
199 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
200 MVT ValueVT = ValueVTs[Value];
201 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
202 MVT RegisterVT = TLI->getRegisterType(ValueVT);
203 for (unsigned i = 0; i != NumRegs; ++i)
204 Regs.push_back(Reg + i);
205 RegVTs.push_back(RegisterVT);
210 /// append - Add the specified values to this one.
211 void append(const RegsForValue &RHS) {
213 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
214 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
215 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
219 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
220 /// this value and returns the result as a ValueVTs value. This uses
221 /// Chain/Flag as the input and updates them for the output Chain/Flag.
222 /// If the Flag pointer is NULL, no flag is used.
223 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
224 SDValue &Chain, SDValue *Flag) const;
226 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
227 /// specified value into the registers specified by this object. This uses
228 /// Chain/Flag as the input and updates them for the output Chain/Flag.
229 /// If the Flag pointer is NULL, no flag is used.
230 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
231 SDValue &Chain, SDValue *Flag) const;
233 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
234 /// operand list. This adds the code marker, matching input operand index
235 /// (if applicable), and includes the number of values added into it.
236 void AddInlineAsmOperands(unsigned Code,
237 bool HasMatching, unsigned MatchingIdx,
238 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
242 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
243 /// PHI nodes or outside of the basic block that defines it, or used by a
244 /// switch or atomic instruction, which may expand to multiple basic blocks.
245 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
246 if (isa<PHINode>(I)) return true;
247 BasicBlock *BB = I->getParent();
248 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
249 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
254 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
255 /// entry block, return true. This includes arguments used by switches, since
256 /// the switch may expand into multiple basic blocks.
257 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
258 // With FastISel active, we may be splitting blocks, so force creation
259 // of virtual registers for all non-dead arguments.
260 // Don't force virtual registers for byval arguments though, because
261 // fast-isel can't handle those in all cases.
262 if (EnableFastISel && !A->hasByValAttr())
263 return A->use_empty();
265 BasicBlock *Entry = A->getParent()->begin();
266 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
267 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
268 return false; // Use not in entry block.
272 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
276 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 bool EnableFastISel) {
281 RegInfo = &MF->getRegInfo();
283 // Create a vreg for each argument register that is not dead and is used
284 // outside of the entry block for the function.
285 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
288 InitializeRegForValue(AI);
290 // Initialize the mapping of values to registers. This is only set up for
291 // instruction values that are used outside of the block that defines
293 Function::iterator BB = Fn->begin(), EB = Fn->end();
294 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
295 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
296 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
297 const Type *Ty = AI->getAllocatedType();
298 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
300 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
303 TySize *= CUI->getZExtValue(); // Get total allocated size.
304 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
305 StaticAllocaMap[AI] =
306 MF->getFrameInfo()->CreateStackObject(TySize, Align);
309 for (; BB != EB; ++BB)
310 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
311 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
312 if (!isa<AllocaInst>(I) ||
313 !StaticAllocaMap.count(cast<AllocaInst>(I)))
314 InitializeRegForValue(I);
316 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
317 // also creates the initial PHI MachineInstrs, though none of the input
318 // operands are populated.
319 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
320 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
324 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
328 for (BasicBlock::iterator
329 I = BB->begin(), E = BB->end(); I != E; ++I) {
330 if (CallInst *CI = dyn_cast<CallInst>(I)) {
331 if (Function *F = CI->getCalledFunction()) {
332 switch (F->getIntrinsicID()) {
334 case Intrinsic::dbg_stoppoint: {
335 DwarfWriter *DW = DAG.getDwarfWriter();
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
338 if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
339 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
341 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
343 unsigned idx = MF->getOrCreateDebugLocID(SrcFile,
346 DL = DebugLoc::get(idx);
351 case Intrinsic::dbg_func_start: {
352 DwarfWriter *DW = DAG.getDwarfWriter();
354 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
355 Value *SP = FSI->getSubprogram();
357 if (DW->ValidDebugInfo(SP, false)) {
358 DISubprogram Subprogram(cast<GlobalVariable>(SP));
359 DICompileUnit CU(Subprogram.getCompileUnit());
361 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
363 unsigned Line = Subprogram.getLineNumber();
364 DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0));
374 PN = dyn_cast<PHINode>(I);
375 if (!PN || PN->use_empty()) continue;
377 unsigned PHIReg = ValueMap[PN];
378 assert(PHIReg && "PHI node does not have an assigned virtual register!");
380 SmallVector<MVT, 4> ValueVTs;
381 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
382 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
383 MVT VT = ValueVTs[vti];
384 unsigned NumRegisters = TLI.getNumRegisters(VT);
385 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
386 for (unsigned i = 0; i != NumRegisters; ++i)
387 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
388 PHIReg += NumRegisters;
394 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
395 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
398 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
399 /// the correctly promoted or expanded types. Assign these registers
400 /// consecutive vreg numbers and return the first assigned number.
402 /// In the case that the given value has struct or array type, this function
403 /// will assign registers for each member or element.
405 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
406 SmallVector<MVT, 4> ValueVTs;
407 ComputeValueVTs(TLI, V->getType(), ValueVTs);
409 unsigned FirstReg = 0;
410 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
411 MVT ValueVT = ValueVTs[Value];
412 MVT RegisterVT = TLI.getRegisterType(ValueVT);
414 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
415 for (unsigned i = 0; i != NumRegs; ++i) {
416 unsigned R = MakeReg(RegisterVT);
417 if (!FirstReg) FirstReg = R;
423 /// getCopyFromParts - Create a value that contains the specified legal parts
424 /// combined into the value they represent. If the parts combine to a type
425 /// larger then ValueVT then AssertOp can be used to specify whether the extra
426 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
427 /// (ISD::AssertSext).
428 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
429 const SDValue *Parts,
430 unsigned NumParts, MVT PartVT, MVT ValueVT,
431 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
432 assert(NumParts > 0 && "No parts to assemble!");
433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
434 SDValue Val = Parts[0];
437 // Assemble the value from multiple parts.
438 if (!ValueVT.isVector()) {
439 unsigned PartBits = PartVT.getSizeInBits();
440 unsigned ValueBits = ValueVT.getSizeInBits();
442 // Assemble the power of 2 part.
443 unsigned RoundParts = NumParts & (NumParts - 1) ?
444 1 << Log2_32(NumParts) : NumParts;
445 unsigned RoundBits = PartBits * RoundParts;
446 MVT RoundVT = RoundBits == ValueBits ?
447 ValueVT : MVT::getIntegerVT(RoundBits);
450 MVT HalfVT = ValueVT.isInteger() ?
451 MVT::getIntegerVT(RoundBits/2) :
452 MVT::getFloatingPointVT(RoundBits/2);
454 if (RoundParts > 2) {
455 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
456 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
459 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
460 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
462 if (TLI.isBigEndian())
464 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
466 if (RoundParts < NumParts) {
467 // Assemble the trailing non-power-of-2 part.
468 unsigned OddParts = NumParts - RoundParts;
469 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
470 Hi = getCopyFromParts(DAG, dl,
471 Parts+RoundParts, OddParts, PartVT, OddVT);
473 // Combine the round and odd parts.
475 if (TLI.isBigEndian())
477 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
478 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
479 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
480 DAG.getConstant(Lo.getValueType().getSizeInBits(),
481 TLI.getPointerTy()));
482 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
483 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
486 // Handle a multi-element vector.
487 MVT IntermediateVT, RegisterVT;
488 unsigned NumIntermediates;
490 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
492 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
493 NumParts = NumRegs; // Silence a compiler warning.
494 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
495 assert(RegisterVT == Parts[0].getValueType() &&
496 "Part type doesn't match part!");
498 // Assemble the parts into intermediate operands.
499 SmallVector<SDValue, 8> Ops(NumIntermediates);
500 if (NumIntermediates == NumParts) {
501 // If the register was not expanded, truncate or copy the value,
503 for (unsigned i = 0; i != NumParts; ++i)
504 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
505 PartVT, IntermediateVT);
506 } else if (NumParts > 0) {
507 // If the intermediate type was expanded, build the intermediate operands
509 assert(NumParts % NumIntermediates == 0 &&
510 "Must expand into a divisible number of parts!");
511 unsigned Factor = NumParts / NumIntermediates;
512 for (unsigned i = 0; i != NumIntermediates; ++i)
513 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
514 PartVT, IntermediateVT);
517 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
519 Val = DAG.getNode(IntermediateVT.isVector() ?
520 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
521 ValueVT, &Ops[0], NumIntermediates);
525 // There is now one part, held in Val. Correct it to match ValueVT.
526 PartVT = Val.getValueType();
528 if (PartVT == ValueVT)
531 if (PartVT.isVector()) {
532 assert(ValueVT.isVector() && "Unknown vector conversion!");
533 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
536 if (ValueVT.isVector()) {
537 assert(ValueVT.getVectorElementType() == PartVT &&
538 ValueVT.getVectorNumElements() == 1 &&
539 "Only trivial scalar-to-vector conversions should get here!");
540 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
543 if (PartVT.isInteger() &&
544 ValueVT.isInteger()) {
545 if (ValueVT.bitsLT(PartVT)) {
546 // For a truncate, see if we have any information to
547 // indicate whether the truncated bits will always be
548 // zero or sign-extension.
549 if (AssertOp != ISD::DELETED_NODE)
550 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
551 DAG.getValueType(ValueVT));
552 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
554 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
558 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
559 if (ValueVT.bitsLT(Val.getValueType()))
560 // FP_ROUND's are always exact here.
561 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
562 DAG.getIntPtrConstant(1));
563 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
566 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
567 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
569 assert(0 && "Unknown mismatch!");
573 /// getCopyToParts - Create a series of nodes that contain the specified value
574 /// split into legal parts. If the parts contain more bits than Val, then, for
575 /// integers, ExtendKind can be used to specify how to generate the extra bits.
576 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
577 SDValue *Parts, unsigned NumParts, MVT PartVT,
578 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
579 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
580 MVT PtrVT = TLI.getPointerTy();
581 MVT ValueVT = Val.getValueType();
582 unsigned PartBits = PartVT.getSizeInBits();
583 unsigned OrigNumParts = NumParts;
584 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
589 if (!ValueVT.isVector()) {
590 if (PartVT == ValueVT) {
591 assert(NumParts == 1 && "No-op copy with multiple parts!");
596 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
597 // If the parts cover more bits than the value has, promote the value.
598 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
599 assert(NumParts == 1 && "Do not know what to promote to!");
600 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
601 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
602 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
603 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
605 assert(0 && "Unknown mismatch!");
607 } else if (PartBits == ValueVT.getSizeInBits()) {
608 // Different types of the same size.
609 assert(NumParts == 1 && PartVT != ValueVT);
610 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
611 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
612 // If the parts cover less bits than value has, truncate the value.
613 if (PartVT.isInteger() && ValueVT.isInteger()) {
614 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
615 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
617 assert(0 && "Unknown mismatch!");
621 // The value may have changed - recompute ValueVT.
622 ValueVT = Val.getValueType();
623 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
624 "Failed to tile the value with PartVT!");
627 assert(PartVT == ValueVT && "Type conversion failed!");
632 // Expand the value into multiple parts.
633 if (NumParts & (NumParts - 1)) {
634 // The number of parts is not a power of 2. Split off and copy the tail.
635 assert(PartVT.isInteger() && ValueVT.isInteger() &&
636 "Do not know what to expand to!");
637 unsigned RoundParts = 1 << Log2_32(NumParts);
638 unsigned RoundBits = RoundParts * PartBits;
639 unsigned OddParts = NumParts - RoundParts;
640 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
641 DAG.getConstant(RoundBits,
642 TLI.getPointerTy()));
643 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
644 if (TLI.isBigEndian())
645 // The odd parts were reversed by getCopyToParts - unreverse them.
646 std::reverse(Parts + RoundParts, Parts + NumParts);
647 NumParts = RoundParts;
648 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
649 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
652 // The number of parts is a power of 2. Repeatedly bisect the value using
654 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
655 MVT::getIntegerVT(ValueVT.getSizeInBits()),
657 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
658 for (unsigned i = 0; i < NumParts; i += StepSize) {
659 unsigned ThisBits = StepSize * PartBits / 2;
660 MVT ThisVT = MVT::getIntegerVT (ThisBits);
661 SDValue &Part0 = Parts[i];
662 SDValue &Part1 = Parts[i+StepSize/2];
664 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
666 DAG.getConstant(1, PtrVT));
667 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
669 DAG.getConstant(0, PtrVT));
671 if (ThisBits == PartBits && ThisVT != PartVT) {
672 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
674 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
680 if (TLI.isBigEndian())
681 std::reverse(Parts, Parts + OrigNumParts);
688 if (PartVT != ValueVT) {
689 if (PartVT.isVector()) {
690 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
692 assert(ValueVT.getVectorElementType() == PartVT &&
693 ValueVT.getVectorNumElements() == 1 &&
694 "Only trivial vector-to-scalar conversions should get here!");
695 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
697 DAG.getConstant(0, PtrVT));
705 // Handle a multi-element vector.
706 MVT IntermediateVT, RegisterVT;
707 unsigned NumIntermediates;
708 unsigned NumRegs = TLI
709 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
711 unsigned NumElements = ValueVT.getVectorNumElements();
713 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
714 NumParts = NumRegs; // Silence a compiler warning.
715 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
717 // Split the vector into intermediate operands.
718 SmallVector<SDValue, 8> Ops(NumIntermediates);
719 for (unsigned i = 0; i != NumIntermediates; ++i)
720 if (IntermediateVT.isVector())
721 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
723 DAG.getConstant(i * (NumElements / NumIntermediates),
726 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
728 DAG.getConstant(i, PtrVT));
730 // Split the intermediate operands into legal parts.
731 if (NumParts == NumIntermediates) {
732 // If the register was not expanded, promote or copy the value,
734 for (unsigned i = 0; i != NumParts; ++i)
735 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
736 } else if (NumParts > 0) {
737 // If the intermediate type was expanded, split each the value into
739 assert(NumParts % NumIntermediates == 0 &&
740 "Must expand into a divisible number of parts!");
741 unsigned Factor = NumParts / NumIntermediates;
742 for (unsigned i = 0; i != NumIntermediates; ++i)
743 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
748 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
751 TD = DAG.getTarget().getTargetData();
754 /// clear - Clear out the curret SelectionDAG and the associated
755 /// state and prepare this SelectionDAGLowering object to be used
756 /// for a new block. This doesn't clear out information about
757 /// additional blocks that are needed to complete switch lowering
758 /// or PHI node updating; that information is cleared out as it is
760 void SelectionDAGLowering::clear() {
762 PendingLoads.clear();
763 PendingExports.clear();
765 CurDebugLoc = DebugLoc::getUnknownLoc();
768 /// getRoot - Return the current virtual root of the Selection DAG,
769 /// flushing any PendingLoad items. This must be done before emitting
770 /// a store or any other node that may need to be ordered after any
771 /// prior load instructions.
773 SDValue SelectionDAGLowering::getRoot() {
774 if (PendingLoads.empty())
775 return DAG.getRoot();
777 if (PendingLoads.size() == 1) {
778 SDValue Root = PendingLoads[0];
780 PendingLoads.clear();
784 // Otherwise, we have to make a token factor node.
785 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
786 &PendingLoads[0], PendingLoads.size());
787 PendingLoads.clear();
792 /// getControlRoot - Similar to getRoot, but instead of flushing all the
793 /// PendingLoad items, flush all the PendingExports items. It is necessary
794 /// to do this before emitting a terminator instruction.
796 SDValue SelectionDAGLowering::getControlRoot() {
797 SDValue Root = DAG.getRoot();
799 if (PendingExports.empty())
802 // Turn all of the CopyToReg chains into one factored node.
803 if (Root.getOpcode() != ISD::EntryToken) {
804 unsigned i = 0, e = PendingExports.size();
805 for (; i != e; ++i) {
806 assert(PendingExports[i].getNode()->getNumOperands() > 1);
807 if (PendingExports[i].getNode()->getOperand(0) == Root)
808 break; // Don't add the root if we already indirectly depend on it.
812 PendingExports.push_back(Root);
815 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
817 PendingExports.size());
818 PendingExports.clear();
823 void SelectionDAGLowering::visit(Instruction &I) {
824 visit(I.getOpcode(), I);
827 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
828 // Note: this doesn't use InstVisitor, because it has to work with
829 // ConstantExpr's in addition to instructions.
831 default: assert(0 && "Unknown instruction type encountered!");
833 // Build the switch statement using the Instruction.def file.
834 #define HANDLE_INST(NUM, OPCODE, CLASS) \
835 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
836 #include "llvm/Instruction.def"
840 void SelectionDAGLowering::visitAdd(User &I) {
841 if (I.getType()->isFPOrFPVector())
842 visitBinary(I, ISD::FADD);
844 visitBinary(I, ISD::ADD);
847 void SelectionDAGLowering::visitMul(User &I) {
848 if (I.getType()->isFPOrFPVector())
849 visitBinary(I, ISD::FMUL);
851 visitBinary(I, ISD::MUL);
854 SDValue SelectionDAGLowering::getValue(const Value *V) {
855 SDValue &N = NodeMap[V];
856 if (N.getNode()) return N;
858 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
859 MVT VT = TLI.getValueType(V->getType(), true);
861 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
862 return N = DAG.getConstant(*CI, VT);
864 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
865 return N = DAG.getGlobalAddress(GV, VT);
867 if (isa<ConstantPointerNull>(C))
868 return N = DAG.getConstant(0, TLI.getPointerTy());
870 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
871 return N = DAG.getConstantFP(*CFP, VT);
873 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
874 return N = DAG.getUNDEF(VT);
876 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
877 visit(CE->getOpcode(), *CE);
878 SDValue N1 = NodeMap[V];
879 assert(N1.getNode() && "visit didn't populate the ValueMap!");
883 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
884 SmallVector<SDValue, 4> Constants;
885 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
887 SDNode *Val = getValue(*OI).getNode();
888 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
889 Constants.push_back(SDValue(Val, i));
891 return DAG.getMergeValues(&Constants[0], Constants.size(),
895 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
896 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
897 "Unknown struct or array constant!");
899 SmallVector<MVT, 4> ValueVTs;
900 ComputeValueVTs(TLI, C->getType(), ValueVTs);
901 unsigned NumElts = ValueVTs.size();
903 return SDValue(); // empty struct
904 SmallVector<SDValue, 4> Constants(NumElts);
905 for (unsigned i = 0; i != NumElts; ++i) {
906 MVT EltVT = ValueVTs[i];
907 if (isa<UndefValue>(C))
908 Constants[i] = DAG.getUNDEF(EltVT);
909 else if (EltVT.isFloatingPoint())
910 Constants[i] = DAG.getConstantFP(0, EltVT);
912 Constants[i] = DAG.getConstant(0, EltVT);
914 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
917 const VectorType *VecTy = cast<VectorType>(V->getType());
918 unsigned NumElements = VecTy->getNumElements();
920 // Now that we know the number and type of the elements, get that number of
921 // elements into the Ops array based on what kind of constant it is.
922 SmallVector<SDValue, 16> Ops;
923 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
924 for (unsigned i = 0; i != NumElements; ++i)
925 Ops.push_back(getValue(CP->getOperand(i)));
927 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
928 MVT EltVT = TLI.getValueType(VecTy->getElementType());
931 if (EltVT.isFloatingPoint())
932 Op = DAG.getConstantFP(0, EltVT);
934 Op = DAG.getConstant(0, EltVT);
935 Ops.assign(NumElements, Op);
938 // Create a BUILD_VECTOR node.
939 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
940 VT, &Ops[0], Ops.size());
943 // If this is a static alloca, generate it as the frameindex instead of
945 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
946 DenseMap<const AllocaInst*, int>::iterator SI =
947 FuncInfo.StaticAllocaMap.find(AI);
948 if (SI != FuncInfo.StaticAllocaMap.end())
949 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
952 unsigned InReg = FuncInfo.ValueMap[V];
953 assert(InReg && "Value not in map!");
955 RegsForValue RFV(TLI, InReg, V->getType());
956 SDValue Chain = DAG.getEntryNode();
957 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
961 void SelectionDAGLowering::visitRet(ReturnInst &I) {
962 if (I.getNumOperands() == 0) {
963 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
964 MVT::Other, getControlRoot()));
968 SmallVector<SDValue, 8> NewValues;
969 NewValues.push_back(getControlRoot());
970 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
971 SmallVector<MVT, 4> ValueVTs;
972 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
973 unsigned NumValues = ValueVTs.size();
974 if (NumValues == 0) continue;
976 SDValue RetOp = getValue(I.getOperand(i));
977 for (unsigned j = 0, f = NumValues; j != f; ++j) {
978 MVT VT = ValueVTs[j];
980 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
982 const Function *F = I.getParent()->getParent();
983 if (F->paramHasAttr(0, Attribute::SExt))
984 ExtendKind = ISD::SIGN_EXTEND;
985 else if (F->paramHasAttr(0, Attribute::ZExt))
986 ExtendKind = ISD::ZERO_EXTEND;
988 // FIXME: C calling convention requires the return type to be promoted to
989 // at least 32-bit. But this is not necessary for non-C calling
990 // conventions. The frontend should mark functions whose return values
991 // require promoting with signext or zeroext attributes.
992 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
993 MVT MinVT = TLI.getRegisterType(MVT::i32);
994 if (VT.bitsLT(MinVT))
998 unsigned NumParts = TLI.getNumRegisters(VT);
999 MVT PartVT = TLI.getRegisterType(VT);
1000 SmallVector<SDValue, 4> Parts(NumParts);
1001 getCopyToParts(DAG, getCurDebugLoc(),
1002 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1003 &Parts[0], NumParts, PartVT, ExtendKind);
1005 // 'inreg' on function refers to return value
1006 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1007 if (F->paramHasAttr(0, Attribute::InReg))
1009 for (unsigned i = 0; i < NumParts; ++i) {
1010 NewValues.push_back(Parts[i]);
1011 NewValues.push_back(DAG.getArgFlags(Flags));
1015 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
1016 &NewValues[0], NewValues.size()));
1019 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1020 /// created for it, emit nodes to copy the value into the virtual
1022 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1023 if (!V->use_empty()) {
1024 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1025 if (VMI != FuncInfo.ValueMap.end())
1026 CopyValueToVirtualRegister(V, VMI->second);
1030 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1031 /// the current basic block, add it to ValueMap now so that we'll get a
1033 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1034 // No need to export constants.
1035 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1037 // Already exported?
1038 if (FuncInfo.isExportedInst(V)) return;
1040 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1041 CopyValueToVirtualRegister(V, Reg);
1044 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1045 const BasicBlock *FromBB) {
1046 // The operands of the setcc have to be in this block. We don't know
1047 // how to export them from some other block.
1048 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1049 // Can export from current BB.
1050 if (VI->getParent() == FromBB)
1053 // Is already exported, noop.
1054 return FuncInfo.isExportedInst(V);
1057 // If this is an argument, we can export it if the BB is the entry block or
1058 // if it is already exported.
1059 if (isa<Argument>(V)) {
1060 if (FromBB == &FromBB->getParent()->getEntryBlock())
1063 // Otherwise, can only export this if it is already exported.
1064 return FuncInfo.isExportedInst(V);
1067 // Otherwise, constants can always be exported.
1071 static bool InBlock(const Value *V, const BasicBlock *BB) {
1072 if (const Instruction *I = dyn_cast<Instruction>(V))
1073 return I->getParent() == BB;
1077 /// getFCmpCondCode - Return the ISD condition code corresponding to
1078 /// the given LLVM IR floating-point condition code. This includes
1079 /// consideration of global floating-point math flags.
1081 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1082 ISD::CondCode FPC, FOC;
1084 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1085 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1086 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1087 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1088 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1089 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1090 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1091 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1092 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1093 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1094 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1095 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1096 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1097 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1098 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1099 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1101 assert(0 && "Invalid FCmp predicate opcode!");
1102 FOC = FPC = ISD::SETFALSE;
1105 if (FiniteOnlyFPMath())
1111 /// getICmpCondCode - Return the ISD condition code corresponding to
1112 /// the given LLVM IR integer condition code.
1114 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1116 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1117 case ICmpInst::ICMP_NE: return ISD::SETNE;
1118 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1119 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1120 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1121 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1122 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1123 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1124 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1125 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1127 assert(0 && "Invalid ICmp predicate opcode!");
1132 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1133 /// This function emits a branch and is used at the leaves of an OR or an
1134 /// AND operator tree.
1137 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1138 MachineBasicBlock *TBB,
1139 MachineBasicBlock *FBB,
1140 MachineBasicBlock *CurBB) {
1141 const BasicBlock *BB = CurBB->getBasicBlock();
1143 // If the leaf of the tree is a comparison, merge the condition into
1145 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1146 // The operands of the cmp have to be in this block. We don't know
1147 // how to export them from some other block. If this is the first block
1148 // of the sequence, no exporting is needed.
1149 if (CurBB == CurMBB ||
1150 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1151 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1152 ISD::CondCode Condition;
1153 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1154 Condition = getICmpCondCode(IC->getPredicate());
1155 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1156 Condition = getFCmpCondCode(FC->getPredicate());
1158 Condition = ISD::SETEQ; // silence warning.
1159 assert(0 && "Unknown compare instruction");
1162 CaseBlock CB(Condition, BOp->getOperand(0),
1163 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1164 SwitchCases.push_back(CB);
1169 // Create a CaseBlock record representing this branch.
1170 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1171 NULL, TBB, FBB, CurBB);
1172 SwitchCases.push_back(CB);
1175 /// FindMergedConditions - If Cond is an expression like
1176 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1177 MachineBasicBlock *TBB,
1178 MachineBasicBlock *FBB,
1179 MachineBasicBlock *CurBB,
1181 // If this node is not part of the or/and tree, emit it as a branch.
1182 Instruction *BOp = dyn_cast<Instruction>(Cond);
1183 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1184 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1185 BOp->getParent() != CurBB->getBasicBlock() ||
1186 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1187 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1188 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1192 // Create TmpBB after CurBB.
1193 MachineFunction::iterator BBI = CurBB;
1194 MachineFunction &MF = DAG.getMachineFunction();
1195 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1196 CurBB->getParent()->insert(++BBI, TmpBB);
1198 if (Opc == Instruction::Or) {
1199 // Codegen X | Y as:
1207 // Emit the LHS condition.
1208 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1210 // Emit the RHS condition into TmpBB.
1211 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1213 assert(Opc == Instruction::And && "Unknown merge op!");
1214 // Codegen X & Y as:
1221 // This requires creation of TmpBB after CurBB.
1223 // Emit the LHS condition.
1224 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1226 // Emit the RHS condition into TmpBB.
1227 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1231 /// If the set of cases should be emitted as a series of branches, return true.
1232 /// If we should emit this as a bunch of and/or'd together conditions, return
1235 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1236 if (Cases.size() != 2) return true;
1238 // If this is two comparisons of the same values or'd or and'd together, they
1239 // will get folded into a single comparison, so don't emit two blocks.
1240 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1241 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1242 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1243 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1250 void SelectionDAGLowering::visitBr(BranchInst &I) {
1251 // Update machine-CFG edges.
1252 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1254 // Figure out which block is immediately after the current one.
1255 MachineBasicBlock *NextBlock = 0;
1256 MachineFunction::iterator BBI = CurMBB;
1257 if (++BBI != CurMBB->getParent()->end())
1260 if (I.isUnconditional()) {
1261 // Update machine-CFG edges.
1262 CurMBB->addSuccessor(Succ0MBB);
1264 // If this is not a fall-through branch, emit the branch.
1265 if (Succ0MBB != NextBlock)
1266 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1267 MVT::Other, getControlRoot(),
1268 DAG.getBasicBlock(Succ0MBB)));
1272 // If this condition is one of the special cases we handle, do special stuff
1274 Value *CondVal = I.getCondition();
1275 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1277 // If this is a series of conditions that are or'd or and'd together, emit
1278 // this as a sequence of branches instead of setcc's with and/or operations.
1279 // For example, instead of something like:
1292 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1293 if (BOp->hasOneUse() &&
1294 (BOp->getOpcode() == Instruction::And ||
1295 BOp->getOpcode() == Instruction::Or)) {
1296 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1297 // If the compares in later blocks need to use values not currently
1298 // exported from this block, export them now. This block should always
1299 // be the first entry.
1300 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1302 // Allow some cases to be rejected.
1303 if (ShouldEmitAsBranches(SwitchCases)) {
1304 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1305 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1306 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1309 // Emit the branch for this block.
1310 visitSwitchCase(SwitchCases[0]);
1311 SwitchCases.erase(SwitchCases.begin());
1315 // Okay, we decided not to do this, remove any inserted MBB's and clear
1317 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1318 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1320 SwitchCases.clear();
1324 // Create a CaseBlock record representing this branch.
1325 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1326 NULL, Succ0MBB, Succ1MBB, CurMBB);
1327 // Use visitSwitchCase to actually insert the fast branch sequence for this
1329 visitSwitchCase(CB);
1332 /// visitSwitchCase - Emits the necessary code to represent a single node in
1333 /// the binary search tree resulting from lowering a switch instruction.
1334 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1336 SDValue CondLHS = getValue(CB.CmpLHS);
1337 DebugLoc dl = getCurDebugLoc();
1339 // Build the setcc now.
1340 if (CB.CmpMHS == NULL) {
1341 // Fold "(X == true)" to X and "(X == false)" to !X to
1342 // handle common cases produced by branch lowering.
1343 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1345 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1346 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1347 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1349 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1351 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1353 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1354 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1356 SDValue CmpOp = getValue(CB.CmpMHS);
1357 MVT VT = CmpOp.getValueType();
1359 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1360 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1363 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1364 VT, CmpOp, DAG.getConstant(Low, VT));
1365 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1366 DAG.getConstant(High-Low, VT), ISD::SETULE);
1370 // Update successor info
1371 CurMBB->addSuccessor(CB.TrueBB);
1372 CurMBB->addSuccessor(CB.FalseBB);
1374 // Set NextBlock to be the MBB immediately after the current one, if any.
1375 // This is used to avoid emitting unnecessary branches to the next block.
1376 MachineBasicBlock *NextBlock = 0;
1377 MachineFunction::iterator BBI = CurMBB;
1378 if (++BBI != CurMBB->getParent()->end())
1381 // If the lhs block is the next block, invert the condition so that we can
1382 // fall through to the lhs instead of the rhs block.
1383 if (CB.TrueBB == NextBlock) {
1384 std::swap(CB.TrueBB, CB.FalseBB);
1385 SDValue True = DAG.getConstant(1, Cond.getValueType());
1386 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1388 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1389 MVT::Other, getControlRoot(), Cond,
1390 DAG.getBasicBlock(CB.TrueBB));
1392 // If the branch was constant folded, fix up the CFG.
1393 if (BrCond.getOpcode() == ISD::BR) {
1394 CurMBB->removeSuccessor(CB.FalseBB);
1395 DAG.setRoot(BrCond);
1397 // Otherwise, go ahead and insert the false branch.
1398 if (BrCond == getControlRoot())
1399 CurMBB->removeSuccessor(CB.TrueBB);
1401 if (CB.FalseBB == NextBlock)
1402 DAG.setRoot(BrCond);
1404 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1405 DAG.getBasicBlock(CB.FalseBB)));
1409 /// visitJumpTable - Emit JumpTable node in the current MBB
1410 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1411 // Emit the code for the jump table
1412 assert(JT.Reg != -1U && "Should lower JT Header first!");
1413 MVT PTy = TLI.getPointerTy();
1414 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1416 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1417 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1418 MVT::Other, Index.getValue(1),
1422 /// visitJumpTableHeader - This function emits necessary code to produce index
1423 /// in the JumpTable from switch case.
1424 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1425 JumpTableHeader &JTH) {
1426 // Subtract the lowest switch case value from the value being switched on and
1427 // conditional branch to default mbb if the result is greater than the
1428 // difference between smallest and largest cases.
1429 SDValue SwitchOp = getValue(JTH.SValue);
1430 MVT VT = SwitchOp.getValueType();
1431 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1432 DAG.getConstant(JTH.First, VT));
1434 // The SDNode we just created, which holds the value being switched on minus
1435 // the the smallest case value, needs to be copied to a virtual register so it
1436 // can be used as an index into the jump table in a subsequent basic block.
1437 // This value may be smaller or larger than the target's pointer type, and
1438 // therefore require extension or truncating.
1439 if (VT.bitsGT(TLI.getPointerTy()))
1440 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1441 TLI.getPointerTy(), SUB);
1443 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1444 TLI.getPointerTy(), SUB);
1446 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1447 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1448 JumpTableReg, SwitchOp);
1449 JT.Reg = JumpTableReg;
1451 // Emit the range check for the jump table, and branch to the default block
1452 // for the switch statement if the value being switched on exceeds the largest
1453 // case in the switch.
1454 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1455 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1456 DAG.getConstant(JTH.Last-JTH.First,VT),
1459 // Set NextBlock to be the MBB immediately after the current one, if any.
1460 // This is used to avoid emitting unnecessary branches to the next block.
1461 MachineBasicBlock *NextBlock = 0;
1462 MachineFunction::iterator BBI = CurMBB;
1463 if (++BBI != CurMBB->getParent()->end())
1466 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1467 MVT::Other, CopyTo, CMP,
1468 DAG.getBasicBlock(JT.Default));
1470 if (JT.MBB == NextBlock)
1471 DAG.setRoot(BrCond);
1473 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1474 DAG.getBasicBlock(JT.MBB)));
1477 /// visitBitTestHeader - This function emits necessary code to produce value
1478 /// suitable for "bit tests"
1479 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1480 // Subtract the minimum value
1481 SDValue SwitchOp = getValue(B.SValue);
1482 MVT VT = SwitchOp.getValueType();
1483 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1484 DAG.getConstant(B.First, VT));
1487 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1488 TLI.getSetCCResultType(SUB.getValueType()),
1489 SUB, DAG.getConstant(B.Range, VT),
1493 if (VT.bitsGT(TLI.getPointerTy()))
1494 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1495 TLI.getPointerTy(), SUB);
1497 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1498 TLI.getPointerTy(), SUB);
1500 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1501 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1504 // Set NextBlock to be the MBB immediately after the current one, if any.
1505 // This is used to avoid emitting unnecessary branches to the next block.
1506 MachineBasicBlock *NextBlock = 0;
1507 MachineFunction::iterator BBI = CurMBB;
1508 if (++BBI != CurMBB->getParent()->end())
1511 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1513 CurMBB->addSuccessor(B.Default);
1514 CurMBB->addSuccessor(MBB);
1516 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1517 MVT::Other, CopyTo, RangeCmp,
1518 DAG.getBasicBlock(B.Default));
1520 if (MBB == NextBlock)
1521 DAG.setRoot(BrRange);
1523 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1524 DAG.getBasicBlock(MBB)));
1527 /// visitBitTestCase - this function produces one "bit test"
1528 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1531 // Make desired shift
1532 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1533 TLI.getPointerTy());
1534 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1536 DAG.getConstant(1, TLI.getPointerTy()),
1539 // Emit bit tests and jumps
1540 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1541 TLI.getPointerTy(), SwitchVal,
1542 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1543 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1544 TLI.getSetCCResultType(AndOp.getValueType()),
1545 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1548 CurMBB->addSuccessor(B.TargetBB);
1549 CurMBB->addSuccessor(NextMBB);
1551 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1552 MVT::Other, getControlRoot(),
1553 AndCmp, DAG.getBasicBlock(B.TargetBB));
1555 // Set NextBlock to be the MBB immediately after the current one, if any.
1556 // This is used to avoid emitting unnecessary branches to the next block.
1557 MachineBasicBlock *NextBlock = 0;
1558 MachineFunction::iterator BBI = CurMBB;
1559 if (++BBI != CurMBB->getParent()->end())
1562 if (NextMBB == NextBlock)
1565 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1566 DAG.getBasicBlock(NextMBB)));
1569 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1570 // Retrieve successors.
1571 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1572 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1574 const Value *Callee(I.getCalledValue());
1575 if (isa<InlineAsm>(Callee))
1578 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1580 // If the value of the invoke is used outside of its defining block, make it
1581 // available as a virtual register.
1582 CopyToExportRegsIfNeeded(&I);
1584 // Update successor info
1585 CurMBB->addSuccessor(Return);
1586 CurMBB->addSuccessor(LandingPad);
1588 // Drop into normal successor.
1589 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1590 MVT::Other, getControlRoot(),
1591 DAG.getBasicBlock(Return)));
1594 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1597 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1598 /// small case ranges).
1599 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1600 CaseRecVector& WorkList,
1602 MachineBasicBlock* Default) {
1603 Case& BackCase = *(CR.Range.second-1);
1605 // Size is the number of Cases represented by this range.
1606 size_t Size = CR.Range.second - CR.Range.first;
1610 // Get the MachineFunction which holds the current MBB. This is used when
1611 // inserting any additional MBBs necessary to represent the switch.
1612 MachineFunction *CurMF = CurMBB->getParent();
1614 // Figure out which block is immediately after the current one.
1615 MachineBasicBlock *NextBlock = 0;
1616 MachineFunction::iterator BBI = CR.CaseBB;
1618 if (++BBI != CurMBB->getParent()->end())
1621 // TODO: If any two of the cases has the same destination, and if one value
1622 // is the same as the other, but has one bit unset that the other has set,
1623 // use bit manipulation to do two compares at once. For example:
1624 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1626 // Rearrange the case blocks so that the last one falls through if possible.
1627 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1628 // The last case block won't fall through into 'NextBlock' if we emit the
1629 // branches in this order. See if rearranging a case value would help.
1630 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1631 if (I->BB == NextBlock) {
1632 std::swap(*I, BackCase);
1638 // Create a CaseBlock record representing a conditional branch to
1639 // the Case's target mbb if the value being switched on SV is equal
1641 MachineBasicBlock *CurBlock = CR.CaseBB;
1642 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1643 MachineBasicBlock *FallThrough;
1645 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1646 CurMF->insert(BBI, FallThrough);
1648 // Put SV in a virtual register to make it available from the new blocks.
1649 ExportFromCurrentBlock(SV);
1651 // If the last case doesn't match, go to the default block.
1652 FallThrough = Default;
1655 Value *RHS, *LHS, *MHS;
1657 if (I->High == I->Low) {
1658 // This is just small small case range :) containing exactly 1 case
1660 LHS = SV; RHS = I->High; MHS = NULL;
1663 LHS = I->Low; MHS = SV; RHS = I->High;
1665 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1667 // If emitting the first comparison, just call visitSwitchCase to emit the
1668 // code into the current block. Otherwise, push the CaseBlock onto the
1669 // vector to be later processed by SDISel, and insert the node's MBB
1670 // before the next MBB.
1671 if (CurBlock == CurMBB)
1672 visitSwitchCase(CB);
1674 SwitchCases.push_back(CB);
1676 CurBlock = FallThrough;
1682 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1683 return !DisableJumpTables &&
1684 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1685 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1688 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1689 APInt LastExt(Last), FirstExt(First);
1690 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1691 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1692 return (LastExt - FirstExt + 1ULL);
1695 /// handleJTSwitchCase - Emit jumptable for current switch case range
1696 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1697 CaseRecVector& WorkList,
1699 MachineBasicBlock* Default) {
1700 Case& FrontCase = *CR.Range.first;
1701 Case& BackCase = *(CR.Range.second-1);
1703 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1704 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1707 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1711 if (!areJTsAllowed(TLI) || TSize <= 3)
1714 APInt Range = ComputeRange(First, Last);
1715 double Density = (double)TSize / Range.roundToDouble();
1719 DEBUG(errs() << "Lowering jump table\n"
1720 << "First entry: " << First << ". Last entry: " << Last << '\n'
1721 << "Range: " << Range
1722 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1724 // Get the MachineFunction which holds the current MBB. This is used when
1725 // inserting any additional MBBs necessary to represent the switch.
1726 MachineFunction *CurMF = CurMBB->getParent();
1728 // Figure out which block is immediately after the current one.
1729 MachineBasicBlock *NextBlock = 0;
1730 MachineFunction::iterator BBI = CR.CaseBB;
1732 if (++BBI != CurMBB->getParent()->end())
1735 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1737 // Create a new basic block to hold the code for loading the address
1738 // of the jump table, and jumping to it. Update successor information;
1739 // we will either branch to the default case for the switch, or the jump
1741 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1742 CurMF->insert(BBI, JumpTableBB);
1743 CR.CaseBB->addSuccessor(Default);
1744 CR.CaseBB->addSuccessor(JumpTableBB);
1746 // Build a vector of destination BBs, corresponding to each target
1747 // of the jump table. If the value of the jump table slot corresponds to
1748 // a case statement, push the case's BB onto the vector, otherwise, push
1750 std::vector<MachineBasicBlock*> DestBBs;
1752 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1753 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1754 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1756 if (Low.sle(TEI) && TEI.sle(High)) {
1757 DestBBs.push_back(I->BB);
1761 DestBBs.push_back(Default);
1765 // Update successor info. Add one edge to each unique successor.
1766 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1767 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1768 E = DestBBs.end(); I != E; ++I) {
1769 if (!SuccsHandled[(*I)->getNumber()]) {
1770 SuccsHandled[(*I)->getNumber()] = true;
1771 JumpTableBB->addSuccessor(*I);
1775 // Create a jump table index for this jump table, or return an existing
1777 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1779 // Set the jump table information so that we can codegen it as a second
1780 // MachineBasicBlock
1781 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1782 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1783 if (CR.CaseBB == CurMBB)
1784 visitJumpTableHeader(JT, JTH);
1786 JTCases.push_back(JumpTableBlock(JTH, JT));
1791 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1793 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1794 CaseRecVector& WorkList,
1796 MachineBasicBlock* Default) {
1797 // Get the MachineFunction which holds the current MBB. This is used when
1798 // inserting any additional MBBs necessary to represent the switch.
1799 MachineFunction *CurMF = CurMBB->getParent();
1801 // Figure out which block is immediately after the current one.
1802 MachineBasicBlock *NextBlock = 0;
1803 MachineFunction::iterator BBI = CR.CaseBB;
1805 if (++BBI != CurMBB->getParent()->end())
1808 Case& FrontCase = *CR.Range.first;
1809 Case& BackCase = *(CR.Range.second-1);
1810 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1812 // Size is the number of Cases represented by this range.
1813 unsigned Size = CR.Range.second - CR.Range.first;
1815 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1816 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1818 CaseItr Pivot = CR.Range.first + Size/2;
1820 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1821 // (heuristically) allow us to emit JumpTable's later.
1823 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1827 size_t LSize = FrontCase.size();
1828 size_t RSize = TSize-LSize;
1829 DEBUG(errs() << "Selecting best pivot: \n"
1830 << "First: " << First << ", Last: " << Last <<'\n'
1831 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1832 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1834 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1835 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1836 APInt Range = ComputeRange(LEnd, RBegin);
1837 assert((Range - 2ULL).isNonNegative() &&
1838 "Invalid case distance");
1839 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1840 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1841 double Metric = Range.logBase2()*(LDensity+RDensity);
1842 // Should always split in some non-trivial place
1843 DEBUG(errs() <<"=>Step\n"
1844 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1845 << "LDensity: " << LDensity
1846 << ", RDensity: " << RDensity << '\n'
1847 << "Metric: " << Metric << '\n');
1848 if (FMetric < Metric) {
1851 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1857 if (areJTsAllowed(TLI)) {
1858 // If our case is dense we *really* should handle it earlier!
1859 assert((FMetric > 0) && "Should handle dense range earlier!");
1861 Pivot = CR.Range.first + Size/2;
1864 CaseRange LHSR(CR.Range.first, Pivot);
1865 CaseRange RHSR(Pivot, CR.Range.second);
1866 Constant *C = Pivot->Low;
1867 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1869 // We know that we branch to the LHS if the Value being switched on is
1870 // less than the Pivot value, C. We use this to optimize our binary
1871 // tree a bit, by recognizing that if SV is greater than or equal to the
1872 // LHS's Case Value, and that Case Value is exactly one less than the
1873 // Pivot's Value, then we can branch directly to the LHS's Target,
1874 // rather than creating a leaf node for it.
1875 if ((LHSR.second - LHSR.first) == 1 &&
1876 LHSR.first->High == CR.GE &&
1877 cast<ConstantInt>(C)->getValue() ==
1878 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1879 TrueBB = LHSR.first->BB;
1881 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1882 CurMF->insert(BBI, TrueBB);
1883 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1885 // Put SV in a virtual register to make it available from the new blocks.
1886 ExportFromCurrentBlock(SV);
1889 // Similar to the optimization above, if the Value being switched on is
1890 // known to be less than the Constant CR.LT, and the current Case Value
1891 // is CR.LT - 1, then we can branch directly to the target block for
1892 // the current Case Value, rather than emitting a RHS leaf node for it.
1893 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1894 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1895 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1896 FalseBB = RHSR.first->BB;
1898 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1899 CurMF->insert(BBI, FalseBB);
1900 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1902 // Put SV in a virtual register to make it available from the new blocks.
1903 ExportFromCurrentBlock(SV);
1906 // Create a CaseBlock record representing a conditional branch to
1907 // the LHS node if the value being switched on SV is less than C.
1908 // Otherwise, branch to LHS.
1909 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1911 if (CR.CaseBB == CurMBB)
1912 visitSwitchCase(CB);
1914 SwitchCases.push_back(CB);
1919 /// handleBitTestsSwitchCase - if current case range has few destination and
1920 /// range span less, than machine word bitwidth, encode case range into series
1921 /// of masks and emit bit tests with these masks.
1922 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1923 CaseRecVector& WorkList,
1925 MachineBasicBlock* Default){
1926 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1928 Case& FrontCase = *CR.Range.first;
1929 Case& BackCase = *(CR.Range.second-1);
1931 // Get the MachineFunction which holds the current MBB. This is used when
1932 // inserting any additional MBBs necessary to represent the switch.
1933 MachineFunction *CurMF = CurMBB->getParent();
1936 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1938 // Single case counts one, case range - two.
1939 numCmps += (I->Low == I->High ? 1 : 2);
1942 // Count unique destinations
1943 SmallSet<MachineBasicBlock*, 4> Dests;
1944 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1945 Dests.insert(I->BB);
1946 if (Dests.size() > 3)
1947 // Don't bother the code below, if there are too much unique destinations
1950 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1951 << "Total number of comparisons: " << numCmps << '\n');
1953 // Compute span of values.
1954 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1955 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1956 APInt cmpRange = maxValue - minValue;
1958 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1959 << "Low bound: " << minValue << '\n'
1960 << "High bound: " << maxValue << '\n');
1962 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1963 (!(Dests.size() == 1 && numCmps >= 3) &&
1964 !(Dests.size() == 2 && numCmps >= 5) &&
1965 !(Dests.size() >= 3 && numCmps >= 6)))
1968 DEBUG(errs() << "Emitting bit tests\n");
1969 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1971 // Optimize the case where all the case values fit in a
1972 // word without having to subtract minValue. In this case,
1973 // we can optimize away the subtraction.
1974 if (minValue.isNonNegative() &&
1975 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1976 cmpRange = maxValue;
1978 lowBound = minValue;
1981 CaseBitsVector CasesBits;
1982 unsigned i, count = 0;
1984 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1985 MachineBasicBlock* Dest = I->BB;
1986 for (i = 0; i < count; ++i)
1987 if (Dest == CasesBits[i].BB)
1991 assert((count < 3) && "Too much destinations to test!");
1992 CasesBits.push_back(CaseBits(0, Dest, 0));
1996 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1997 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1999 uint64_t lo = (lowValue - lowBound).getZExtValue();
2000 uint64_t hi = (highValue - lowBound).getZExtValue();
2002 for (uint64_t j = lo; j <= hi; j++) {
2003 CasesBits[i].Mask |= 1ULL << j;
2004 CasesBits[i].Bits++;
2008 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2012 // Figure out which block is immediately after the current one.
2013 MachineFunction::iterator BBI = CR.CaseBB;
2016 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2018 DEBUG(errs() << "Cases:\n");
2019 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2020 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2021 << ", Bits: " << CasesBits[i].Bits
2022 << ", BB: " << CasesBits[i].BB << '\n');
2024 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2025 CurMF->insert(BBI, CaseBB);
2026 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2030 // Put SV in a virtual register to make it available from the new blocks.
2031 ExportFromCurrentBlock(SV);
2034 BitTestBlock BTB(lowBound, cmpRange, SV,
2035 -1U, (CR.CaseBB == CurMBB),
2036 CR.CaseBB, Default, BTC);
2038 if (CR.CaseBB == CurMBB)
2039 visitBitTestHeader(BTB);
2041 BitTestCases.push_back(BTB);
2047 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2048 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2049 const SwitchInst& SI) {
2052 // Start with "simple" cases
2053 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2054 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2055 Cases.push_back(Case(SI.getSuccessorValue(i),
2056 SI.getSuccessorValue(i),
2059 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2061 // Merge case into clusters
2062 if (Cases.size() >= 2)
2063 // Must recompute end() each iteration because it may be
2064 // invalidated by erase if we hold on to it
2065 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2066 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2067 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2068 MachineBasicBlock* nextBB = J->BB;
2069 MachineBasicBlock* currentBB = I->BB;
2071 // If the two neighboring cases go to the same destination, merge them
2072 // into a single case.
2073 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2081 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2082 if (I->Low != I->High)
2083 // A range counts double, since it requires two compares.
2090 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2091 // Figure out which block is immediately after the current one.
2092 MachineBasicBlock *NextBlock = 0;
2093 MachineFunction::iterator BBI = CurMBB;
2095 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2097 // If there is only the default destination, branch to it if it is not the
2098 // next basic block. Otherwise, just fall through.
2099 if (SI.getNumOperands() == 2) {
2100 // Update machine-CFG edges.
2102 // If this is not a fall-through branch, emit the branch.
2103 CurMBB->addSuccessor(Default);
2104 if (Default != NextBlock)
2105 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2106 MVT::Other, getControlRoot(),
2107 DAG.getBasicBlock(Default)));
2111 // If there are any non-default case statements, create a vector of Cases
2112 // representing each one, and sort the vector so that we can efficiently
2113 // create a binary search tree from them.
2115 size_t numCmps = Clusterify(Cases, SI);
2116 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2117 << ". Total compares: " << numCmps << '\n');
2120 // Get the Value to be switched on and default basic blocks, which will be
2121 // inserted into CaseBlock records, representing basic blocks in the binary
2123 Value *SV = SI.getOperand(0);
2125 // Push the initial CaseRec onto the worklist
2126 CaseRecVector WorkList;
2127 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2129 while (!WorkList.empty()) {
2130 // Grab a record representing a case range to process off the worklist
2131 CaseRec CR = WorkList.back();
2132 WorkList.pop_back();
2134 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2137 // If the range has few cases (two or less) emit a series of specific
2139 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2142 // If the switch has more than 5 blocks, and at least 40% dense, and the
2143 // target supports indirect branches, then emit a jump table rather than
2144 // lowering the switch to a binary tree of conditional branches.
2145 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2148 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2149 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2150 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2155 void SelectionDAGLowering::visitSub(User &I) {
2156 // -0.0 - X --> fneg
2157 const Type *Ty = I.getType();
2158 if (isa<VectorType>(Ty)) {
2159 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2160 const VectorType *DestTy = cast<VectorType>(I.getType());
2161 const Type *ElTy = DestTy->getElementType();
2162 if (ElTy->isFloatingPoint()) {
2163 unsigned VL = DestTy->getNumElements();
2164 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2165 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2167 SDValue Op2 = getValue(I.getOperand(1));
2168 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2169 Op2.getValueType(), Op2));
2175 if (Ty->isFloatingPoint()) {
2176 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2177 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2178 SDValue Op2 = getValue(I.getOperand(1));
2179 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2180 Op2.getValueType(), Op2));
2185 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2188 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2189 SDValue Op1 = getValue(I.getOperand(0));
2190 SDValue Op2 = getValue(I.getOperand(1));
2192 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2193 Op1.getValueType(), Op1, Op2));
2196 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2197 SDValue Op1 = getValue(I.getOperand(0));
2198 SDValue Op2 = getValue(I.getOperand(1));
2199 if (!isa<VectorType>(I.getType()) &&
2200 Op2.getValueType() != TLI.getShiftAmountTy()) {
2201 // If the operand is smaller than the shift count type, promote it.
2202 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2203 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2204 TLI.getShiftAmountTy(), Op2);
2205 // If the operand is larger than the shift count type but the shift
2206 // count type has enough bits to represent any shift value, truncate
2207 // it now. This is a common case and it exposes the truncate to
2208 // optimization early.
2209 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2210 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2211 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2212 TLI.getShiftAmountTy(), Op2);
2213 // Otherwise we'll need to temporarily settle for some other
2214 // convenient type; type legalization will make adjustments as
2216 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2217 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2218 TLI.getPointerTy(), Op2);
2219 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2220 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2221 TLI.getPointerTy(), Op2);
2224 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2225 Op1.getValueType(), Op1, Op2));
2228 void SelectionDAGLowering::visitICmp(User &I) {
2229 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2230 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2231 predicate = IC->getPredicate();
2232 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2233 predicate = ICmpInst::Predicate(IC->getPredicate());
2234 SDValue Op1 = getValue(I.getOperand(0));
2235 SDValue Op2 = getValue(I.getOperand(1));
2236 ISD::CondCode Opcode = getICmpCondCode(predicate);
2237 setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode));
2240 void SelectionDAGLowering::visitFCmp(User &I) {
2241 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2242 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2243 predicate = FC->getPredicate();
2244 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2245 predicate = FCmpInst::Predicate(FC->getPredicate());
2246 SDValue Op1 = getValue(I.getOperand(0));
2247 SDValue Op2 = getValue(I.getOperand(1));
2248 ISD::CondCode Condition = getFCmpCondCode(predicate);
2249 setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition));
2252 void SelectionDAGLowering::visitVICmp(User &I) {
2253 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2254 if (VICmpInst *IC = dyn_cast<VICmpInst>(&I))
2255 predicate = IC->getPredicate();
2256 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2257 predicate = ICmpInst::Predicate(IC->getPredicate());
2258 SDValue Op1 = getValue(I.getOperand(0));
2259 SDValue Op2 = getValue(I.getOperand(1));
2260 ISD::CondCode Opcode = getICmpCondCode(predicate);
2261 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(),
2265 void SelectionDAGLowering::visitVFCmp(User &I) {
2266 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2267 if (VFCmpInst *FC = dyn_cast<VFCmpInst>(&I))
2268 predicate = FC->getPredicate();
2269 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2270 predicate = FCmpInst::Predicate(FC->getPredicate());
2271 SDValue Op1 = getValue(I.getOperand(0));
2272 SDValue Op2 = getValue(I.getOperand(1));
2273 ISD::CondCode Condition = getFCmpCondCode(predicate);
2274 MVT DestVT = TLI.getValueType(I.getType());
2276 setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2279 void SelectionDAGLowering::visitSelect(User &I) {
2280 SmallVector<MVT, 4> ValueVTs;
2281 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2282 unsigned NumValues = ValueVTs.size();
2283 if (NumValues != 0) {
2284 SmallVector<SDValue, 4> Values(NumValues);
2285 SDValue Cond = getValue(I.getOperand(0));
2286 SDValue TrueVal = getValue(I.getOperand(1));
2287 SDValue FalseVal = getValue(I.getOperand(2));
2289 for (unsigned i = 0; i != NumValues; ++i)
2290 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2291 TrueVal.getValueType(), Cond,
2292 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2293 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2295 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2296 DAG.getVTList(&ValueVTs[0], NumValues),
2297 &Values[0], NumValues));
2302 void SelectionDAGLowering::visitTrunc(User &I) {
2303 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2304 SDValue N = getValue(I.getOperand(0));
2305 MVT DestVT = TLI.getValueType(I.getType());
2306 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2309 void SelectionDAGLowering::visitZExt(User &I) {
2310 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2311 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2312 SDValue N = getValue(I.getOperand(0));
2313 MVT DestVT = TLI.getValueType(I.getType());
2314 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2317 void SelectionDAGLowering::visitSExt(User &I) {
2318 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2319 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2320 SDValue N = getValue(I.getOperand(0));
2321 MVT DestVT = TLI.getValueType(I.getType());
2322 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2325 void SelectionDAGLowering::visitFPTrunc(User &I) {
2326 // FPTrunc is never a no-op cast, no need to check
2327 SDValue N = getValue(I.getOperand(0));
2328 MVT DestVT = TLI.getValueType(I.getType());
2329 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2330 DestVT, N, DAG.getIntPtrConstant(0)));
2333 void SelectionDAGLowering::visitFPExt(User &I){
2334 // FPTrunc is never a no-op cast, no need to check
2335 SDValue N = getValue(I.getOperand(0));
2336 MVT DestVT = TLI.getValueType(I.getType());
2337 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2340 void SelectionDAGLowering::visitFPToUI(User &I) {
2341 // FPToUI is never a no-op cast, no need to check
2342 SDValue N = getValue(I.getOperand(0));
2343 MVT DestVT = TLI.getValueType(I.getType());
2344 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2347 void SelectionDAGLowering::visitFPToSI(User &I) {
2348 // FPToSI is never a no-op cast, no need to check
2349 SDValue N = getValue(I.getOperand(0));
2350 MVT DestVT = TLI.getValueType(I.getType());
2351 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2354 void SelectionDAGLowering::visitUIToFP(User &I) {
2355 // UIToFP is never a no-op cast, no need to check
2356 SDValue N = getValue(I.getOperand(0));
2357 MVT DestVT = TLI.getValueType(I.getType());
2358 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2361 void SelectionDAGLowering::visitSIToFP(User &I){
2362 // SIToFP is never a no-op cast, no need to check
2363 SDValue N = getValue(I.getOperand(0));
2364 MVT DestVT = TLI.getValueType(I.getType());
2365 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2368 void SelectionDAGLowering::visitPtrToInt(User &I) {
2369 // What to do depends on the size of the integer and the size of the pointer.
2370 // We can either truncate, zero extend, or no-op, accordingly.
2371 SDValue N = getValue(I.getOperand(0));
2372 MVT SrcVT = N.getValueType();
2373 MVT DestVT = TLI.getValueType(I.getType());
2375 if (DestVT.bitsLT(SrcVT))
2376 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2378 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2379 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2380 setValue(&I, Result);
2383 void SelectionDAGLowering::visitIntToPtr(User &I) {
2384 // What to do depends on the size of the integer and the size of the pointer.
2385 // We can either truncate, zero extend, or no-op, accordingly.
2386 SDValue N = getValue(I.getOperand(0));
2387 MVT SrcVT = N.getValueType();
2388 MVT DestVT = TLI.getValueType(I.getType());
2389 if (DestVT.bitsLT(SrcVT))
2390 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2392 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2393 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2397 void SelectionDAGLowering::visitBitCast(User &I) {
2398 SDValue N = getValue(I.getOperand(0));
2399 MVT DestVT = TLI.getValueType(I.getType());
2401 // BitCast assures us that source and destination are the same size so this
2402 // is either a BIT_CONVERT or a no-op.
2403 if (DestVT != N.getValueType())
2404 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2405 DestVT, N)); // convert types
2407 setValue(&I, N); // noop cast.
2410 void SelectionDAGLowering::visitInsertElement(User &I) {
2411 SDValue InVec = getValue(I.getOperand(0));
2412 SDValue InVal = getValue(I.getOperand(1));
2413 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2415 getValue(I.getOperand(2)));
2417 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2418 TLI.getValueType(I.getType()),
2419 InVec, InVal, InIdx));
2422 void SelectionDAGLowering::visitExtractElement(User &I) {
2423 SDValue InVec = getValue(I.getOperand(0));
2424 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2426 getValue(I.getOperand(1)));
2427 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2428 TLI.getValueType(I.getType()), InVec, InIdx));
2432 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2433 // from SIndx and increasing to the element length (undefs are allowed).
2434 static bool SequentialMask(SmallVectorImpl<int> &Mask, int SIndx) {
2435 int MaskNumElts = Mask.size();
2436 for (int i = 0; i != MaskNumElts; ++i)
2437 if ((Mask[i] >= 0) && (Mask[i] != i + SIndx))
2442 void SelectionDAGLowering::visitShuffleVector(User &I) {
2443 SmallVector<int, 8> Mask;
2444 SDValue Src1 = getValue(I.getOperand(0));
2445 SDValue Src2 = getValue(I.getOperand(1));
2447 // Convert the ConstantVector mask operand into an array of ints, with -1
2448 // representing undef values.
2449 SmallVector<Constant*, 8> MaskElts;
2450 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2451 int MaskNumElts = MaskElts.size();
2452 for (int i = 0; i != MaskNumElts; ++i) {
2453 if (isa<UndefValue>(MaskElts[i]))
2456 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2459 MVT VT = TLI.getValueType(I.getType());
2460 MVT SrcVT = Src1.getValueType();
2461 int SrcNumElts = SrcVT.getVectorNumElements();
2463 if (SrcNumElts == MaskNumElts) {
2464 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2469 // Normalize the shuffle vector since mask and vector length don't match.
2470 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2471 // Mask is longer than the source vectors and is a multiple of the source
2472 // vectors. We can use concatenate vector to make the mask and vectors
2474 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2475 // The shuffle is concatenating two vectors together.
2476 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2481 // Pad both vectors with undefs to make them the same length as the mask.
2482 unsigned NumConcat = MaskNumElts / SrcNumElts;
2483 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2484 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2485 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2487 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2488 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2492 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2493 getCurDebugLoc(), VT,
2494 &MOps1[0], NumConcat);
2495 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2496 getCurDebugLoc(), VT,
2497 &MOps2[0], NumConcat);
2499 // Readjust mask for new input vector length.
2500 SmallVector<int, 8> MappedOps;
2501 for (int i = 0; i != MaskNumElts; ++i) {
2503 if (Idx < SrcNumElts)
2504 MappedOps.push_back(Idx);
2506 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2508 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2513 if (SrcNumElts > MaskNumElts) {
2514 // Resulting vector is shorter than the incoming vector.
2515 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,0)) {
2516 // Shuffle extracts 1st vector.
2521 if (SrcNumElts == MaskNumElts && SequentialMask(Mask,MaskNumElts)) {
2522 // Shuffle extracts 2nd vector.
2527 // Analyze the access pattern of the vector to see if we can extract
2528 // two subvectors and do the shuffle. The analysis is done by calculating
2529 // the range of elements the mask access on both vectors.
2530 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2531 int MaxRange[2] = {-1, -1};
2533 for (int i = 0; i != MaskNumElts; ++i) {
2539 if (Idx >= SrcNumElts) {
2543 if (Idx > MaxRange[Input])
2544 MaxRange[Input] = Idx;
2545 if (Idx < MinRange[Input])
2546 MinRange[Input] = Idx;
2549 // Check if the access is smaller than the vector size and can we find
2550 // a reasonable extract index.
2551 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2552 int StartIdx[2]; // StartIdx to extract from
2553 for (int Input=0; Input < 2; ++Input) {
2554 if (MinRange[Input] == SrcNumElts+1 && MaxRange[Input] == -1) {
2555 RangeUse[Input] = 0; // Unused
2556 StartIdx[Input] = 0;
2557 } else if (MaxRange[Input] - MinRange[Input] < MaskNumElts) {
2558 // Fits within range but we should see if we can find a good
2559 // start index that is a multiple of the mask length.
2560 if (MaxRange[Input] < MaskNumElts) {
2561 RangeUse[Input] = 1; // Extract from beginning of the vector
2562 StartIdx[Input] = 0;
2564 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2565 if (MaxRange[Input] - StartIdx[Input] < MaskNumElts &&
2566 StartIdx[Input] + MaskNumElts < SrcNumElts)
2567 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2572 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2573 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2576 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2577 // Extract appropriate subvector and generate a vector shuffle
2578 for (int Input=0; Input < 2; ++Input) {
2579 SDValue& Src = Input == 0 ? Src1 : Src2;
2580 if (RangeUse[Input] == 0) {
2581 Src = DAG.getUNDEF(VT);
2583 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2584 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2587 // Calculate new mask.
2588 SmallVector<int, 8> MappedOps;
2589 for (int i = 0; i != MaskNumElts; ++i) {
2592 MappedOps.push_back(Idx);
2593 else if (Idx < SrcNumElts)
2594 MappedOps.push_back(Idx - StartIdx[0]);
2596 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2598 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2604 // We can't use either concat vectors or extract subvectors so fall back to
2605 // replacing the shuffle with extract and build vector.
2606 // to insert and build vector.
2607 MVT EltVT = VT.getVectorElementType();
2608 MVT PtrVT = TLI.getPointerTy();
2609 SmallVector<SDValue,8> Ops;
2610 for (int i = 0; i != MaskNumElts; ++i) {
2612 Ops.push_back(DAG.getUNDEF(EltVT));
2615 if (Idx < SrcNumElts)
2616 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2617 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2619 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2621 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2624 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2625 VT, &Ops[0], Ops.size()));
2628 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2629 const Value *Op0 = I.getOperand(0);
2630 const Value *Op1 = I.getOperand(1);
2631 const Type *AggTy = I.getType();
2632 const Type *ValTy = Op1->getType();
2633 bool IntoUndef = isa<UndefValue>(Op0);
2634 bool FromUndef = isa<UndefValue>(Op1);
2636 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2637 I.idx_begin(), I.idx_end());
2639 SmallVector<MVT, 4> AggValueVTs;
2640 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2641 SmallVector<MVT, 4> ValValueVTs;
2642 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2644 unsigned NumAggValues = AggValueVTs.size();
2645 unsigned NumValValues = ValValueVTs.size();
2646 SmallVector<SDValue, 4> Values(NumAggValues);
2648 SDValue Agg = getValue(Op0);
2649 SDValue Val = getValue(Op1);
2651 // Copy the beginning value(s) from the original aggregate.
2652 for (; i != LinearIndex; ++i)
2653 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2654 SDValue(Agg.getNode(), Agg.getResNo() + i);
2655 // Copy values from the inserted value(s).
2656 for (; i != LinearIndex + NumValValues; ++i)
2657 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2658 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2659 // Copy remaining value(s) from the original aggregate.
2660 for (; i != NumAggValues; ++i)
2661 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2662 SDValue(Agg.getNode(), Agg.getResNo() + i);
2664 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2665 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2666 &Values[0], NumAggValues));
2669 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2670 const Value *Op0 = I.getOperand(0);
2671 const Type *AggTy = Op0->getType();
2672 const Type *ValTy = I.getType();
2673 bool OutOfUndef = isa<UndefValue>(Op0);
2675 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2676 I.idx_begin(), I.idx_end());
2678 SmallVector<MVT, 4> ValValueVTs;
2679 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2681 unsigned NumValValues = ValValueVTs.size();
2682 SmallVector<SDValue, 4> Values(NumValValues);
2684 SDValue Agg = getValue(Op0);
2685 // Copy out the selected value(s).
2686 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2687 Values[i - LinearIndex] =
2689 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2690 SDValue(Agg.getNode(), Agg.getResNo() + i);
2692 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2693 DAG.getVTList(&ValValueVTs[0], NumValValues),
2694 &Values[0], NumValValues));
2698 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2699 SDValue N = getValue(I.getOperand(0));
2700 const Type *Ty = I.getOperand(0)->getType();
2702 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2705 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2706 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2709 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2710 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2711 DAG.getIntPtrConstant(Offset));
2713 Ty = StTy->getElementType(Field);
2715 Ty = cast<SequentialType>(Ty)->getElementType();
2717 // If this is a constant subscript, handle it quickly.
2718 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2719 if (CI->getZExtValue() == 0) continue;
2721 TD->getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2723 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2725 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2727 DAG.getConstant(Offs, MVT::i64));
2729 OffsVal = DAG.getIntPtrConstant(Offs);
2730 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2735 // N = N + Idx * ElementSize;
2736 uint64_t ElementSize = TD->getTypePaddedSize(Ty);
2737 SDValue IdxN = getValue(Idx);
2739 // If the index is smaller or larger than intptr_t, truncate or extend
2741 if (IdxN.getValueType().bitsLT(N.getValueType()))
2742 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2743 N.getValueType(), IdxN);
2744 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2745 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2746 N.getValueType(), IdxN);
2748 // If this is a multiply by a power of two, turn it into a shl
2749 // immediately. This is a very common case.
2750 if (ElementSize != 1) {
2751 if (isPowerOf2_64(ElementSize)) {
2752 unsigned Amt = Log2_64(ElementSize);
2753 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2754 N.getValueType(), IdxN,
2755 DAG.getConstant(Amt, TLI.getPointerTy()));
2757 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2758 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2759 N.getValueType(), IdxN, Scale);
2763 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2764 N.getValueType(), N, IdxN);
2770 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2771 // If this is a fixed sized alloca in the entry block of the function,
2772 // allocate it statically on the stack.
2773 if (FuncInfo.StaticAllocaMap.count(&I))
2774 return; // getValue will auto-populate this.
2776 const Type *Ty = I.getAllocatedType();
2777 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
2779 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2782 SDValue AllocSize = getValue(I.getArraySize());
2784 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2786 DAG.getConstant(TySize, AllocSize.getValueType()));
2790 MVT IntPtr = TLI.getPointerTy();
2791 if (IntPtr.bitsLT(AllocSize.getValueType()))
2792 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2794 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2795 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2798 // Handle alignment. If the requested alignment is less than or equal to
2799 // the stack alignment, ignore it. If the size is greater than or equal to
2800 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2801 unsigned StackAlign =
2802 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2803 if (Align <= StackAlign)
2806 // Round the size of the allocation up to the stack alignment size
2807 // by add SA-1 to the size.
2808 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2809 AllocSize.getValueType(), AllocSize,
2810 DAG.getIntPtrConstant(StackAlign-1));
2811 // Mask out the low bits for alignment purposes.
2812 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2813 AllocSize.getValueType(), AllocSize,
2814 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2816 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2817 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2818 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2821 DAG.setRoot(DSA.getValue(1));
2823 // Inform the Frame Information that we have just allocated a variable-sized
2825 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2828 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2829 const Value *SV = I.getOperand(0);
2830 SDValue Ptr = getValue(SV);
2832 const Type *Ty = I.getType();
2833 bool isVolatile = I.isVolatile();
2834 unsigned Alignment = I.getAlignment();
2836 SmallVector<MVT, 4> ValueVTs;
2837 SmallVector<uint64_t, 4> Offsets;
2838 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2839 unsigned NumValues = ValueVTs.size();
2844 bool ConstantMemory = false;
2846 // Serialize volatile loads with other side effects.
2848 else if (AA->pointsToConstantMemory(SV)) {
2849 // Do not serialize (non-volatile) loads of constant memory with anything.
2850 Root = DAG.getEntryNode();
2851 ConstantMemory = true;
2853 // Do not serialize non-volatile loads against each other.
2854 Root = DAG.getRoot();
2857 SmallVector<SDValue, 4> Values(NumValues);
2858 SmallVector<SDValue, 4> Chains(NumValues);
2859 MVT PtrVT = Ptr.getValueType();
2860 for (unsigned i = 0; i != NumValues; ++i) {
2861 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2862 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2864 DAG.getConstant(Offsets[i], PtrVT)),
2866 isVolatile, Alignment);
2868 Chains[i] = L.getValue(1);
2871 if (!ConstantMemory) {
2872 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2874 &Chains[0], NumValues);
2878 PendingLoads.push_back(Chain);
2881 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2882 DAG.getVTList(&ValueVTs[0], NumValues),
2883 &Values[0], NumValues));
2887 void SelectionDAGLowering::visitStore(StoreInst &I) {
2888 Value *SrcV = I.getOperand(0);
2889 Value *PtrV = I.getOperand(1);
2891 SmallVector<MVT, 4> ValueVTs;
2892 SmallVector<uint64_t, 4> Offsets;
2893 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2894 unsigned NumValues = ValueVTs.size();
2898 // Get the lowered operands. Note that we do this after
2899 // checking if NumResults is zero, because with zero results
2900 // the operands won't have values in the map.
2901 SDValue Src = getValue(SrcV);
2902 SDValue Ptr = getValue(PtrV);
2904 SDValue Root = getRoot();
2905 SmallVector<SDValue, 4> Chains(NumValues);
2906 MVT PtrVT = Ptr.getValueType();
2907 bool isVolatile = I.isVolatile();
2908 unsigned Alignment = I.getAlignment();
2909 for (unsigned i = 0; i != NumValues; ++i)
2910 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2911 SDValue(Src.getNode(), Src.getResNo() + i),
2912 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2914 DAG.getConstant(Offsets[i], PtrVT)),
2916 isVolatile, Alignment);
2918 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2919 MVT::Other, &Chains[0], NumValues));
2922 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2924 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2925 unsigned Intrinsic) {
2926 bool HasChain = !I.doesNotAccessMemory();
2927 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2929 // Build the operand list.
2930 SmallVector<SDValue, 8> Ops;
2931 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2933 // We don't need to serialize loads against other loads.
2934 Ops.push_back(DAG.getRoot());
2936 Ops.push_back(getRoot());
2940 // Info is set by getTgtMemInstrinsic
2941 TargetLowering::IntrinsicInfo Info;
2942 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2944 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2945 if (!IsTgtIntrinsic)
2946 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2948 // Add all operands of the call to the operand list.
2949 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2950 SDValue Op = getValue(I.getOperand(i));
2951 assert(TLI.isTypeLegal(Op.getValueType()) &&
2952 "Intrinsic uses a non-legal type?");
2956 std::vector<MVT> VTArray;
2957 if (I.getType() != Type::VoidTy) {
2958 MVT VT = TLI.getValueType(I.getType());
2959 if (VT.isVector()) {
2960 const VectorType *DestTy = cast<VectorType>(I.getType());
2961 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2963 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2964 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2967 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2968 VTArray.push_back(VT);
2971 VTArray.push_back(MVT::Other);
2973 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2977 if (IsTgtIntrinsic) {
2978 // This is target intrinsic that touches memory
2979 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2980 VTs, &Ops[0], Ops.size(),
2981 Info.memVT, Info.ptrVal, Info.offset,
2982 Info.align, Info.vol,
2983 Info.readMem, Info.writeMem);
2986 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2987 VTs, &Ops[0], Ops.size());
2988 else if (I.getType() != Type::VoidTy)
2989 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2990 VTs, &Ops[0], Ops.size());
2992 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2993 VTs, &Ops[0], Ops.size());
2996 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2998 PendingLoads.push_back(Chain);
3002 if (I.getType() != Type::VoidTy) {
3003 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3004 MVT VT = TLI.getValueType(PTy);
3005 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3007 setValue(&I, Result);
3011 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
3012 static GlobalVariable *ExtractTypeInfo(Value *V) {
3013 V = V->stripPointerCasts();
3014 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
3015 assert ((GV || isa<ConstantPointerNull>(V)) &&
3016 "TypeInfo must be a global variable or NULL");
3022 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
3023 /// call, and add them to the specified machine basic block.
3024 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
3025 MachineBasicBlock *MBB) {
3026 // Inform the MachineModuleInfo of the personality for this landing pad.
3027 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
3028 assert(CE->getOpcode() == Instruction::BitCast &&
3029 isa<Function>(CE->getOperand(0)) &&
3030 "Personality should be a function");
3031 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
3033 // Gather all the type infos for this landing pad and pass them along to
3034 // MachineModuleInfo.
3035 std::vector<GlobalVariable *> TyInfo;
3036 unsigned N = I.getNumOperands();
3038 for (unsigned i = N - 1; i > 2; --i) {
3039 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
3040 unsigned FilterLength = CI->getZExtValue();
3041 unsigned FirstCatch = i + FilterLength + !FilterLength;
3042 assert (FirstCatch <= N && "Invalid filter length");
3044 if (FirstCatch < N) {
3045 TyInfo.reserve(N - FirstCatch);
3046 for (unsigned j = FirstCatch; j < N; ++j)
3047 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3048 MMI->addCatchTypeInfo(MBB, TyInfo);
3052 if (!FilterLength) {
3054 MMI->addCleanup(MBB);
3057 TyInfo.reserve(FilterLength - 1);
3058 for (unsigned j = i + 1; j < FirstCatch; ++j)
3059 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3060 MMI->addFilterTypeInfo(MBB, TyInfo);
3069 TyInfo.reserve(N - 3);
3070 for (unsigned j = 3; j < N; ++j)
3071 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3072 MMI->addCatchTypeInfo(MBB, TyInfo);
3078 /// GetSignificand - Get the significand and build it into a floating-point
3079 /// number with exponent of 1:
3081 /// Op = (Op & 0x007fffff) | 0x3f800000;
3083 /// where Op is the hexidecimal representation of floating point value.
3085 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3086 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3087 DAG.getConstant(0x007fffff, MVT::i32));
3088 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3089 DAG.getConstant(0x3f800000, MVT::i32));
3090 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3093 /// GetExponent - Get the exponent:
3095 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3097 /// where Op is the hexidecimal representation of floating point value.
3099 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3101 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3102 DAG.getConstant(0x7f800000, MVT::i32));
3103 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3104 DAG.getConstant(23, TLI.getPointerTy()));
3105 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3106 DAG.getConstant(127, MVT::i32));
3107 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3110 /// getF32Constant - Get 32-bit floating point constant.
3112 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3113 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3116 /// Inlined utility function to implement binary input atomic intrinsics for
3117 /// visitIntrinsicCall: I is a call instruction
3118 /// Op is the associated NodeType for I
3120 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3121 SDValue Root = getRoot();
3123 DAG.getAtomic(Op, getCurDebugLoc(),
3124 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3126 getValue(I.getOperand(1)),
3127 getValue(I.getOperand(2)),
3130 DAG.setRoot(L.getValue(1));
3134 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3136 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3137 SDValue Op1 = getValue(I.getOperand(1));
3138 SDValue Op2 = getValue(I.getOperand(2));
3140 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3141 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3143 setValue(&I, Result);
3147 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3148 /// limited-precision mode.
3150 SelectionDAGLowering::visitExp(CallInst &I) {
3152 DebugLoc dl = getCurDebugLoc();
3154 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3155 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3156 SDValue Op = getValue(I.getOperand(1));
3158 // Put the exponent in the right bit position for later addition to the
3161 // #define LOG2OFe 1.4426950f
3162 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3163 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3164 getF32Constant(DAG, 0x3fb8aa3b));
3165 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3167 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3168 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3169 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3171 // IntegerPartOfX <<= 23;
3172 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3173 DAG.getConstant(23, TLI.getPointerTy()));
3175 if (LimitFloatPrecision <= 6) {
3176 // For floating-point precision of 6:
3178 // TwoToFractionalPartOfX =
3180 // (0.735607626f + 0.252464424f * x) * x;
3182 // error 0.0144103317, which is 6 bits
3183 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3184 getF32Constant(DAG, 0x3e814304));
3185 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3186 getF32Constant(DAG, 0x3f3c50c8));
3187 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3188 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3189 getF32Constant(DAG, 0x3f7f5e7e));
3190 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3192 // Add the exponent into the result in integer domain.
3193 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3194 TwoToFracPartOfX, IntegerPartOfX);
3196 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3197 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3198 // For floating-point precision of 12:
3200 // TwoToFractionalPartOfX =
3203 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3205 // 0.000107046256 error, which is 13 to 14 bits
3206 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3207 getF32Constant(DAG, 0x3da235e3));
3208 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3209 getF32Constant(DAG, 0x3e65b8f3));
3210 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3211 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3212 getF32Constant(DAG, 0x3f324b07));
3213 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3214 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3215 getF32Constant(DAG, 0x3f7ff8fd));
3216 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3218 // Add the exponent into the result in integer domain.
3219 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3220 TwoToFracPartOfX, IntegerPartOfX);
3222 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3223 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3224 // For floating-point precision of 18:
3226 // TwoToFractionalPartOfX =
3230 // (0.554906021e-1f +
3231 // (0.961591928e-2f +
3232 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3234 // error 2.47208000*10^(-7), which is better than 18 bits
3235 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3236 getF32Constant(DAG, 0x3924b03e));
3237 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3238 getF32Constant(DAG, 0x3ab24b87));
3239 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3240 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3241 getF32Constant(DAG, 0x3c1d8c17));
3242 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3243 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3244 getF32Constant(DAG, 0x3d634a1d));
3245 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3246 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3247 getF32Constant(DAG, 0x3e75fe14));
3248 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3249 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3250 getF32Constant(DAG, 0x3f317234));
3251 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3252 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3253 getF32Constant(DAG, 0x3f800000));
3254 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3257 // Add the exponent into the result in integer domain.
3258 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3259 TwoToFracPartOfX, IntegerPartOfX);
3261 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3264 // No special expansion.
3265 result = DAG.getNode(ISD::FEXP, dl,
3266 getValue(I.getOperand(1)).getValueType(),
3267 getValue(I.getOperand(1)));
3270 setValue(&I, result);
3273 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3274 /// limited-precision mode.
3276 SelectionDAGLowering::visitLog(CallInst &I) {
3278 DebugLoc dl = getCurDebugLoc();
3280 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3281 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3282 SDValue Op = getValue(I.getOperand(1));
3283 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3285 // Scale the exponent by log(2) [0.69314718f].
3286 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3287 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3288 getF32Constant(DAG, 0x3f317218));
3290 // Get the significand and build it into a floating-point number with
3292 SDValue X = GetSignificand(DAG, Op1, dl);
3294 if (LimitFloatPrecision <= 6) {
3295 // For floating-point precision of 6:
3299 // (1.4034025f - 0.23903021f * x) * x;
3301 // error 0.0034276066, which is better than 8 bits
3302 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3303 getF32Constant(DAG, 0xbe74c456));
3304 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3305 getF32Constant(DAG, 0x3fb3a2b1));
3306 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3307 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3308 getF32Constant(DAG, 0x3f949a29));
3310 result = DAG.getNode(ISD::FADD, dl,
3311 MVT::f32, LogOfExponent, LogOfMantissa);
3312 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3313 // For floating-point precision of 12:
3319 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3321 // error 0.000061011436, which is 14 bits
3322 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3323 getF32Constant(DAG, 0xbd67b6d6));
3324 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3325 getF32Constant(DAG, 0x3ee4f4b8));
3326 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3327 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3328 getF32Constant(DAG, 0x3fbc278b));
3329 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3330 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3331 getF32Constant(DAG, 0x40348e95));
3332 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3333 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3334 getF32Constant(DAG, 0x3fdef31a));
3336 result = DAG.getNode(ISD::FADD, dl,
3337 MVT::f32, LogOfExponent, LogOfMantissa);
3338 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3339 // For floating-point precision of 18:
3347 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3349 // error 0.0000023660568, which is better than 18 bits
3350 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3351 getF32Constant(DAG, 0xbc91e5ac));
3352 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3353 getF32Constant(DAG, 0x3e4350aa));
3354 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3355 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3356 getF32Constant(DAG, 0x3f60d3e3));
3357 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3358 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3359 getF32Constant(DAG, 0x4011cdf0));
3360 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3361 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3362 getF32Constant(DAG, 0x406cfd1c));
3363 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3364 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3365 getF32Constant(DAG, 0x408797cb));
3366 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3367 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3368 getF32Constant(DAG, 0x4006dcab));
3370 result = DAG.getNode(ISD::FADD, dl,
3371 MVT::f32, LogOfExponent, LogOfMantissa);
3374 // No special expansion.
3375 result = DAG.getNode(ISD::FLOG, dl,
3376 getValue(I.getOperand(1)).getValueType(),
3377 getValue(I.getOperand(1)));
3380 setValue(&I, result);
3383 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3384 /// limited-precision mode.
3386 SelectionDAGLowering::visitLog2(CallInst &I) {
3388 DebugLoc dl = getCurDebugLoc();
3390 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3391 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3392 SDValue Op = getValue(I.getOperand(1));
3393 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3395 // Get the exponent.
3396 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3398 // Get the significand and build it into a floating-point number with
3400 SDValue X = GetSignificand(DAG, Op1, dl);
3402 // Different possible minimax approximations of significand in
3403 // floating-point for various degrees of accuracy over [1,2].
3404 if (LimitFloatPrecision <= 6) {
3405 // For floating-point precision of 6:
3407 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3409 // error 0.0049451742, which is more than 7 bits
3410 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3411 getF32Constant(DAG, 0xbeb08fe0));
3412 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3413 getF32Constant(DAG, 0x40019463));
3414 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3415 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3416 getF32Constant(DAG, 0x3fd6633d));
3418 result = DAG.getNode(ISD::FADD, dl,
3419 MVT::f32, LogOfExponent, Log2ofMantissa);
3420 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3421 // For floating-point precision of 12:
3427 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3429 // error 0.0000876136000, which is better than 13 bits
3430 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3431 getF32Constant(DAG, 0xbda7262e));
3432 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3433 getF32Constant(DAG, 0x3f25280b));
3434 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3435 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3436 getF32Constant(DAG, 0x4007b923));
3437 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3438 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3439 getF32Constant(DAG, 0x40823e2f));
3440 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3441 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3442 getF32Constant(DAG, 0x4020d29c));
3444 result = DAG.getNode(ISD::FADD, dl,
3445 MVT::f32, LogOfExponent, Log2ofMantissa);
3446 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3447 // For floating-point precision of 18:
3456 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3458 // error 0.0000018516, which is better than 18 bits
3459 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3460 getF32Constant(DAG, 0xbcd2769e));
3461 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3462 getF32Constant(DAG, 0x3e8ce0b9));
3463 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3464 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3465 getF32Constant(DAG, 0x3fa22ae7));
3466 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3467 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3468 getF32Constant(DAG, 0x40525723));
3469 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3470 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3471 getF32Constant(DAG, 0x40aaf200));
3472 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3473 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3474 getF32Constant(DAG, 0x40c39dad));
3475 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3476 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3477 getF32Constant(DAG, 0x4042902c));
3479 result = DAG.getNode(ISD::FADD, dl,
3480 MVT::f32, LogOfExponent, Log2ofMantissa);
3483 // No special expansion.
3484 result = DAG.getNode(ISD::FLOG2, dl,
3485 getValue(I.getOperand(1)).getValueType(),
3486 getValue(I.getOperand(1)));
3489 setValue(&I, result);
3492 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3493 /// limited-precision mode.
3495 SelectionDAGLowering::visitLog10(CallInst &I) {
3497 DebugLoc dl = getCurDebugLoc();
3499 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3500 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3501 SDValue Op = getValue(I.getOperand(1));
3502 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3504 // Scale the exponent by log10(2) [0.30102999f].
3505 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3506 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3507 getF32Constant(DAG, 0x3e9a209a));
3509 // Get the significand and build it into a floating-point number with
3511 SDValue X = GetSignificand(DAG, Op1, dl);
3513 if (LimitFloatPrecision <= 6) {
3514 // For floating-point precision of 6:
3516 // Log10ofMantissa =
3518 // (0.60948995f - 0.10380950f * x) * x;
3520 // error 0.0014886165, which is 6 bits
3521 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3522 getF32Constant(DAG, 0xbdd49a13));
3523 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3524 getF32Constant(DAG, 0x3f1c0789));
3525 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3526 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3527 getF32Constant(DAG, 0x3f011300));
3529 result = DAG.getNode(ISD::FADD, dl,
3530 MVT::f32, LogOfExponent, Log10ofMantissa);
3531 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3532 // For floating-point precision of 12:
3534 // Log10ofMantissa =
3537 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3539 // error 0.00019228036, which is better than 12 bits
3540 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3541 getF32Constant(DAG, 0x3d431f31));
3542 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3543 getF32Constant(DAG, 0x3ea21fb2));
3544 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3545 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3546 getF32Constant(DAG, 0x3f6ae232));
3547 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3548 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3549 getF32Constant(DAG, 0x3f25f7c3));
3551 result = DAG.getNode(ISD::FADD, dl,
3552 MVT::f32, LogOfExponent, Log10ofMantissa);
3553 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3554 // For floating-point precision of 18:
3556 // Log10ofMantissa =
3561 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3563 // error 0.0000037995730, which is better than 18 bits
3564 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3565 getF32Constant(DAG, 0x3c5d51ce));
3566 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3567 getF32Constant(DAG, 0x3e00685a));
3568 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3569 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3570 getF32Constant(DAG, 0x3efb6798));
3571 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3572 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3573 getF32Constant(DAG, 0x3f88d192));
3574 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3575 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3576 getF32Constant(DAG, 0x3fc4316c));
3577 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3578 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3579 getF32Constant(DAG, 0x3f57ce70));
3581 result = DAG.getNode(ISD::FADD, dl,
3582 MVT::f32, LogOfExponent, Log10ofMantissa);
3585 // No special expansion.
3586 result = DAG.getNode(ISD::FLOG10, dl,
3587 getValue(I.getOperand(1)).getValueType(),
3588 getValue(I.getOperand(1)));
3591 setValue(&I, result);
3594 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3595 /// limited-precision mode.
3597 SelectionDAGLowering::visitExp2(CallInst &I) {
3599 DebugLoc dl = getCurDebugLoc();
3601 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3602 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3603 SDValue Op = getValue(I.getOperand(1));
3605 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3607 // FractionalPartOfX = x - (float)IntegerPartOfX;
3608 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3609 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3611 // IntegerPartOfX <<= 23;
3612 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3613 DAG.getConstant(23, TLI.getPointerTy()));
3615 if (LimitFloatPrecision <= 6) {
3616 // For floating-point precision of 6:
3618 // TwoToFractionalPartOfX =
3620 // (0.735607626f + 0.252464424f * x) * x;
3622 // error 0.0144103317, which is 6 bits
3623 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3624 getF32Constant(DAG, 0x3e814304));
3625 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3626 getF32Constant(DAG, 0x3f3c50c8));
3627 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3628 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3629 getF32Constant(DAG, 0x3f7f5e7e));
3630 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3631 SDValue TwoToFractionalPartOfX =
3632 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3634 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3635 MVT::f32, TwoToFractionalPartOfX);
3636 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3637 // For floating-point precision of 12:
3639 // TwoToFractionalPartOfX =
3642 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3644 // error 0.000107046256, which is 13 to 14 bits
3645 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3646 getF32Constant(DAG, 0x3da235e3));
3647 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3648 getF32Constant(DAG, 0x3e65b8f3));
3649 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3650 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3651 getF32Constant(DAG, 0x3f324b07));
3652 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3653 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3654 getF32Constant(DAG, 0x3f7ff8fd));
3655 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3656 SDValue TwoToFractionalPartOfX =
3657 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3659 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3660 MVT::f32, TwoToFractionalPartOfX);
3661 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3662 // For floating-point precision of 18:
3664 // TwoToFractionalPartOfX =
3668 // (0.554906021e-1f +
3669 // (0.961591928e-2f +
3670 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3671 // error 2.47208000*10^(-7), which is better than 18 bits
3672 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3673 getF32Constant(DAG, 0x3924b03e));
3674 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3675 getF32Constant(DAG, 0x3ab24b87));
3676 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3677 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3678 getF32Constant(DAG, 0x3c1d8c17));
3679 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3680 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3681 getF32Constant(DAG, 0x3d634a1d));
3682 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3683 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3684 getF32Constant(DAG, 0x3e75fe14));
3685 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3686 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3687 getF32Constant(DAG, 0x3f317234));
3688 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3689 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3690 getF32Constant(DAG, 0x3f800000));
3691 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3692 SDValue TwoToFractionalPartOfX =
3693 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3695 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3696 MVT::f32, TwoToFractionalPartOfX);
3699 // No special expansion.
3700 result = DAG.getNode(ISD::FEXP2, dl,
3701 getValue(I.getOperand(1)).getValueType(),
3702 getValue(I.getOperand(1)));
3705 setValue(&I, result);
3708 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3709 /// limited-precision mode with x == 10.0f.
3711 SelectionDAGLowering::visitPow(CallInst &I) {
3713 Value *Val = I.getOperand(1);
3714 DebugLoc dl = getCurDebugLoc();
3715 bool IsExp10 = false;
3717 if (getValue(Val).getValueType() == MVT::f32 &&
3718 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3719 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3720 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3721 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3723 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3728 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3729 SDValue Op = getValue(I.getOperand(2));
3731 // Put the exponent in the right bit position for later addition to the
3734 // #define LOG2OF10 3.3219281f
3735 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3736 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3737 getF32Constant(DAG, 0x40549a78));
3738 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3740 // FractionalPartOfX = x - (float)IntegerPartOfX;
3741 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3742 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3744 // IntegerPartOfX <<= 23;
3745 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3746 DAG.getConstant(23, TLI.getPointerTy()));
3748 if (LimitFloatPrecision <= 6) {
3749 // For floating-point precision of 6:
3751 // twoToFractionalPartOfX =
3753 // (0.735607626f + 0.252464424f * x) * x;
3755 // error 0.0144103317, which is 6 bits
3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3757 getF32Constant(DAG, 0x3e814304));
3758 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3f3c50c8));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x3f7f5e7e));
3763 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3764 SDValue TwoToFractionalPartOfX =
3765 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3767 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3768 MVT::f32, TwoToFractionalPartOfX);
3769 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3770 // For floating-point precision of 12:
3772 // TwoToFractionalPartOfX =
3775 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3777 // error 0.000107046256, which is 13 to 14 bits
3778 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3779 getF32Constant(DAG, 0x3da235e3));
3780 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3781 getF32Constant(DAG, 0x3e65b8f3));
3782 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3783 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3784 getF32Constant(DAG, 0x3f324b07));
3785 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3786 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3787 getF32Constant(DAG, 0x3f7ff8fd));
3788 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3789 SDValue TwoToFractionalPartOfX =
3790 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3792 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3793 MVT::f32, TwoToFractionalPartOfX);
3794 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3795 // For floating-point precision of 18:
3797 // TwoToFractionalPartOfX =
3801 // (0.554906021e-1f +
3802 // (0.961591928e-2f +
3803 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3804 // error 2.47208000*10^(-7), which is better than 18 bits
3805 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3806 getF32Constant(DAG, 0x3924b03e));
3807 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3808 getF32Constant(DAG, 0x3ab24b87));
3809 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3810 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3811 getF32Constant(DAG, 0x3c1d8c17));
3812 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3813 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3814 getF32Constant(DAG, 0x3d634a1d));
3815 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3816 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3817 getF32Constant(DAG, 0x3e75fe14));
3818 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3819 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3820 getF32Constant(DAG, 0x3f317234));
3821 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3822 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3823 getF32Constant(DAG, 0x3f800000));
3824 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3825 SDValue TwoToFractionalPartOfX =
3826 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3828 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3829 MVT::f32, TwoToFractionalPartOfX);
3832 // No special expansion.
3833 result = DAG.getNode(ISD::FPOW, dl,
3834 getValue(I.getOperand(1)).getValueType(),
3835 getValue(I.getOperand(1)),
3836 getValue(I.getOperand(2)));
3839 setValue(&I, result);
3842 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3843 /// we want to emit this as a call to a named external function, return the name
3844 /// otherwise lower it and return null.
3846 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3847 DebugLoc dl = getCurDebugLoc();
3848 switch (Intrinsic) {
3850 // By default, turn this into a target intrinsic node.
3851 visitTargetIntrinsic(I, Intrinsic);
3853 case Intrinsic::vastart: visitVAStart(I); return 0;
3854 case Intrinsic::vaend: visitVAEnd(I); return 0;
3855 case Intrinsic::vacopy: visitVACopy(I); return 0;
3856 case Intrinsic::returnaddress:
3857 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3858 getValue(I.getOperand(1))));
3860 case Intrinsic::frameaddress:
3861 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3862 getValue(I.getOperand(1))));
3864 case Intrinsic::setjmp:
3865 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3867 case Intrinsic::longjmp:
3868 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3870 case Intrinsic::memcpy: {
3871 SDValue Op1 = getValue(I.getOperand(1));
3872 SDValue Op2 = getValue(I.getOperand(2));
3873 SDValue Op3 = getValue(I.getOperand(3));
3874 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3875 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3876 I.getOperand(1), 0, I.getOperand(2), 0));
3879 case Intrinsic::memset: {
3880 SDValue Op1 = getValue(I.getOperand(1));
3881 SDValue Op2 = getValue(I.getOperand(2));
3882 SDValue Op3 = getValue(I.getOperand(3));
3883 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3884 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3885 I.getOperand(1), 0));
3888 case Intrinsic::memmove: {
3889 SDValue Op1 = getValue(I.getOperand(1));
3890 SDValue Op2 = getValue(I.getOperand(2));
3891 SDValue Op3 = getValue(I.getOperand(3));
3892 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3894 // If the source and destination are known to not be aliases, we can
3895 // lower memmove as memcpy.
3896 uint64_t Size = -1ULL;
3897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3898 Size = C->getZExtValue();
3899 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3900 AliasAnalysis::NoAlias) {
3901 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3902 I.getOperand(1), 0, I.getOperand(2), 0));
3906 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3907 I.getOperand(1), 0, I.getOperand(2), 0));
3910 case Intrinsic::dbg_stoppoint: {
3911 DwarfWriter *DW = DAG.getDwarfWriter();
3912 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3913 if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
3914 MachineFunction &MF = DAG.getMachineFunction();
3916 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
3920 DICompileUnit CU(cast<GlobalVariable>(SPI.getContext()));
3921 std::string Dir, FN;
3922 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
3923 CU.getFilename(FN));
3924 unsigned idx = MF.getOrCreateDebugLocID(SrcFile,
3925 SPI.getLine(), SPI.getColumn());
3926 setCurDebugLoc(DebugLoc::get(idx));
3930 case Intrinsic::dbg_region_start: {
3931 DwarfWriter *DW = DAG.getDwarfWriter();
3932 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3934 if (DW && DW->ValidDebugInfo(RSI.getContext(), OptLevel)) {
3936 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3937 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3938 getRoot(), LabelID));
3943 case Intrinsic::dbg_region_end: {
3944 DwarfWriter *DW = DAG.getDwarfWriter();
3945 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3947 if (DW && DW->ValidDebugInfo(REI.getContext(), OptLevel)) {
3948 MachineFunction &MF = DAG.getMachineFunction();
3949 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3951 Subprogram.getLinkageName(SPName);
3953 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
3954 // This is end of inlined function. Debugging information for
3955 // inlined function is not handled yet (only supported by FastISel).
3956 if (OptLevel == 0) {
3957 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3959 // Returned ID is 0 if this is unbalanced "end of inlined
3960 // scope". This could happen if optimizer eats dbg intrinsics
3961 // or "beginning of inlined scope" is not recoginized due to
3962 // missing location info. In such cases, do ignore this region.end.
3963 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3970 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3971 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3972 getRoot(), LabelID));
3977 case Intrinsic::dbg_func_start: {
3978 DwarfWriter *DW = DAG.getDwarfWriter();
3980 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3981 Value *SP = FSI.getSubprogram();
3982 if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
3983 MachineFunction &MF = DAG.getMachineFunction();
3984 if (OptLevel == 0) {
3985 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
3986 // (most?) gdb expects.
3987 DebugLoc PrevLoc = CurDebugLoc;
3988 DISubprogram Subprogram(cast<GlobalVariable>(SP));
3989 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
3990 std::string Dir, FN;
3991 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
3992 CompileUnit.getFilename(FN));
3994 if (!Subprogram.describes(MF.getFunction())) {
3995 // This is a beginning of an inlined function.
3997 // If llvm.dbg.func.start is seen in a new block before any
3998 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3999 // FIXME : Why DebugLoc is reset at the beginning of each block ?
4000 if (PrevLoc.isUnknown())
4003 // Record the source line.
4004 unsigned Line = Subprogram.getLineNumber();
4005 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
4006 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4008 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
4009 getRoot(), LabelID));
4010 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
4011 DW->RecordInlinedFnStart(&FSI, Subprogram, LabelID,
4016 // Record the source line.
4017 unsigned Line = Subprogram.getLineNumber();
4018 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4019 DW->RecordSourceLine(Line, 0, SrcFile);
4020 // llvm.dbg.func_start also defines beginning of function scope.
4021 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
4024 DISubprogram Subprogram(cast<GlobalVariable>(SP));
4027 Subprogram.getLinkageName(SPName);
4029 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
4030 // This is beginning of inlined function. Debugging information for
4031 // inlined function is not handled yet (only supported by FastISel).
4035 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
4036 // what (most?) gdb expects.
4037 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
4038 std::string Dir, FN;
4039 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
4040 CompileUnit.getFilename(FN));
4042 // Record the source line but does not create a label for the normal
4043 // function start. It will be emitted at asm emission time. However,
4044 // create a label if this is a beginning of inlined function.
4045 unsigned Line = Subprogram.getLineNumber();
4046 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
4047 // FIXME - Start new region because llvm.dbg.func_start also defines
4048 // beginning of function scope.
4054 case Intrinsic::dbg_declare: {
4055 if (OptLevel == 0) {
4056 DwarfWriter *DW = DAG.getDwarfWriter();
4057 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4058 Value *Variable = DI.getVariable();
4059 if (DW && DW->ValidDebugInfo(Variable, OptLevel))
4060 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
4061 getValue(DI.getAddress()), getValue(Variable)));
4063 // FIXME: Do something sensible here when we support debug declare.
4067 case Intrinsic::eh_exception: {
4068 if (!CurMBB->isLandingPad()) {
4069 // FIXME: Mark exception register as live in. Hack for PR1508.
4070 unsigned Reg = TLI.getExceptionAddressRegister();
4071 if (Reg) CurMBB->addLiveIn(Reg);
4073 // Insert the EXCEPTIONADDR instruction.
4074 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4076 Ops[0] = DAG.getRoot();
4077 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4079 DAG.setRoot(Op.getValue(1));
4083 case Intrinsic::eh_selector_i32:
4084 case Intrinsic::eh_selector_i64: {
4085 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4086 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
4087 MVT::i32 : MVT::i64);
4090 if (CurMBB->isLandingPad())
4091 AddCatchInfo(I, MMI, CurMBB);
4094 FuncInfo.CatchInfoLost.insert(&I);
4096 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4097 unsigned Reg = TLI.getExceptionSelectorRegister();
4098 if (Reg) CurMBB->addLiveIn(Reg);
4101 // Insert the EHSELECTION instruction.
4102 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4104 Ops[0] = getValue(I.getOperand(1));
4106 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4108 DAG.setRoot(Op.getValue(1));
4110 setValue(&I, DAG.getConstant(0, VT));
4116 case Intrinsic::eh_typeid_for_i32:
4117 case Intrinsic::eh_typeid_for_i64: {
4118 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4119 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4120 MVT::i32 : MVT::i64);
4123 // Find the type id for the given typeinfo.
4124 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4126 unsigned TypeID = MMI->getTypeIDFor(GV);
4127 setValue(&I, DAG.getConstant(TypeID, VT));
4129 // Return something different to eh_selector.
4130 setValue(&I, DAG.getConstant(1, VT));
4136 case Intrinsic::eh_return_i32:
4137 case Intrinsic::eh_return_i64:
4138 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4139 MMI->setCallsEHReturn(true);
4140 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4143 getValue(I.getOperand(1)),
4144 getValue(I.getOperand(2))));
4146 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4150 case Intrinsic::eh_unwind_init:
4151 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4152 MMI->setCallsUnwindInit(true);
4157 case Intrinsic::eh_dwarf_cfa: {
4158 MVT VT = getValue(I.getOperand(1)).getValueType();
4160 if (VT.bitsGT(TLI.getPointerTy()))
4161 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4162 TLI.getPointerTy(), getValue(I.getOperand(1)));
4164 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4165 TLI.getPointerTy(), getValue(I.getOperand(1)));
4167 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4169 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4170 TLI.getPointerTy()),
4172 setValue(&I, DAG.getNode(ISD::ADD, dl,
4174 DAG.getNode(ISD::FRAMEADDR, dl,
4177 TLI.getPointerTy())),
4182 case Intrinsic::convertff:
4183 case Intrinsic::convertfsi:
4184 case Intrinsic::convertfui:
4185 case Intrinsic::convertsif:
4186 case Intrinsic::convertuif:
4187 case Intrinsic::convertss:
4188 case Intrinsic::convertsu:
4189 case Intrinsic::convertus:
4190 case Intrinsic::convertuu: {
4191 ISD::CvtCode Code = ISD::CVT_INVALID;
4192 switch (Intrinsic) {
4193 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4194 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4195 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4196 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4197 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4198 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4199 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4200 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4201 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4203 MVT DestVT = TLI.getValueType(I.getType());
4204 Value* Op1 = I.getOperand(1);
4205 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4206 DAG.getValueType(DestVT),
4207 DAG.getValueType(getValue(Op1).getValueType()),
4208 getValue(I.getOperand(2)),
4209 getValue(I.getOperand(3)),
4214 case Intrinsic::sqrt:
4215 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4216 getValue(I.getOperand(1)).getValueType(),
4217 getValue(I.getOperand(1))));
4219 case Intrinsic::powi:
4220 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4221 getValue(I.getOperand(1)).getValueType(),
4222 getValue(I.getOperand(1)),
4223 getValue(I.getOperand(2))));
4225 case Intrinsic::sin:
4226 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4227 getValue(I.getOperand(1)).getValueType(),
4228 getValue(I.getOperand(1))));
4230 case Intrinsic::cos:
4231 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4232 getValue(I.getOperand(1)).getValueType(),
4233 getValue(I.getOperand(1))));
4235 case Intrinsic::log:
4238 case Intrinsic::log2:
4241 case Intrinsic::log10:
4244 case Intrinsic::exp:
4247 case Intrinsic::exp2:
4250 case Intrinsic::pow:
4253 case Intrinsic::pcmarker: {
4254 SDValue Tmp = getValue(I.getOperand(1));
4255 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4258 case Intrinsic::readcyclecounter: {
4259 SDValue Op = getRoot();
4260 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4261 DAG.getVTList(MVT::i64, MVT::Other),
4264 DAG.setRoot(Tmp.getValue(1));
4267 case Intrinsic::part_select: {
4268 // Currently not implemented: just abort
4269 assert(0 && "part_select intrinsic not implemented");
4272 case Intrinsic::part_set: {
4273 // Currently not implemented: just abort
4274 assert(0 && "part_set intrinsic not implemented");
4277 case Intrinsic::bswap:
4278 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4279 getValue(I.getOperand(1)).getValueType(),
4280 getValue(I.getOperand(1))));
4282 case Intrinsic::cttz: {
4283 SDValue Arg = getValue(I.getOperand(1));
4284 MVT Ty = Arg.getValueType();
4285 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4286 setValue(&I, result);
4289 case Intrinsic::ctlz: {
4290 SDValue Arg = getValue(I.getOperand(1));
4291 MVT Ty = Arg.getValueType();
4292 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4293 setValue(&I, result);
4296 case Intrinsic::ctpop: {
4297 SDValue Arg = getValue(I.getOperand(1));
4298 MVT Ty = Arg.getValueType();
4299 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4300 setValue(&I, result);
4303 case Intrinsic::stacksave: {
4304 SDValue Op = getRoot();
4305 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4306 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4308 DAG.setRoot(Tmp.getValue(1));
4311 case Intrinsic::stackrestore: {
4312 SDValue Tmp = getValue(I.getOperand(1));
4313 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4316 case Intrinsic::stackprotector: {
4317 // Emit code into the DAG to store the stack guard onto the stack.
4318 MachineFunction &MF = DAG.getMachineFunction();
4319 MachineFrameInfo *MFI = MF.getFrameInfo();
4320 MVT PtrTy = TLI.getPointerTy();
4322 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4323 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4325 int FI = FuncInfo.StaticAllocaMap[Slot];
4326 MFI->setStackProtectorIndex(FI);
4328 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4330 // Store the stack protector onto the stack.
4331 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4332 PseudoSourceValue::getFixedStack(FI),
4334 setValue(&I, Result);
4335 DAG.setRoot(Result);
4338 case Intrinsic::var_annotation:
4339 // Discard annotate attributes
4342 case Intrinsic::init_trampoline: {
4343 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4347 Ops[1] = getValue(I.getOperand(1));
4348 Ops[2] = getValue(I.getOperand(2));
4349 Ops[3] = getValue(I.getOperand(3));
4350 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4351 Ops[5] = DAG.getSrcValue(F);
4353 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4354 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4358 DAG.setRoot(Tmp.getValue(1));
4362 case Intrinsic::gcroot:
4364 Value *Alloca = I.getOperand(1);
4365 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4367 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4368 GFI->addStackRoot(FI->getIndex(), TypeMap);
4372 case Intrinsic::gcread:
4373 case Intrinsic::gcwrite:
4374 assert(0 && "GC failed to lower gcread/gcwrite intrinsics!");
4377 case Intrinsic::flt_rounds: {
4378 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4382 case Intrinsic::trap: {
4383 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4387 case Intrinsic::uadd_with_overflow:
4388 return implVisitAluOverflow(I, ISD::UADDO);
4389 case Intrinsic::sadd_with_overflow:
4390 return implVisitAluOverflow(I, ISD::SADDO);
4391 case Intrinsic::usub_with_overflow:
4392 return implVisitAluOverflow(I, ISD::USUBO);
4393 case Intrinsic::ssub_with_overflow:
4394 return implVisitAluOverflow(I, ISD::SSUBO);
4395 case Intrinsic::umul_with_overflow:
4396 return implVisitAluOverflow(I, ISD::UMULO);
4397 case Intrinsic::smul_with_overflow:
4398 return implVisitAluOverflow(I, ISD::SMULO);
4400 case Intrinsic::prefetch: {
4403 Ops[1] = getValue(I.getOperand(1));
4404 Ops[2] = getValue(I.getOperand(2));
4405 Ops[3] = getValue(I.getOperand(3));
4406 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4410 case Intrinsic::memory_barrier: {
4413 for (int x = 1; x < 6; ++x)
4414 Ops[x] = getValue(I.getOperand(x));
4416 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4419 case Intrinsic::atomic_cmp_swap: {
4420 SDValue Root = getRoot();
4422 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4423 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4425 getValue(I.getOperand(1)),
4426 getValue(I.getOperand(2)),
4427 getValue(I.getOperand(3)),
4430 DAG.setRoot(L.getValue(1));
4433 case Intrinsic::atomic_load_add:
4434 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4435 case Intrinsic::atomic_load_sub:
4436 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4437 case Intrinsic::atomic_load_or:
4438 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4439 case Intrinsic::atomic_load_xor:
4440 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4441 case Intrinsic::atomic_load_and:
4442 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4443 case Intrinsic::atomic_load_nand:
4444 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4445 case Intrinsic::atomic_load_max:
4446 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4447 case Intrinsic::atomic_load_min:
4448 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4449 case Intrinsic::atomic_load_umin:
4450 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4451 case Intrinsic::atomic_load_umax:
4452 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4453 case Intrinsic::atomic_swap:
4454 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4459 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4461 MachineBasicBlock *LandingPad) {
4462 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4463 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4464 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4465 unsigned BeginLabel = 0, EndLabel = 0;
4467 TargetLowering::ArgListTy Args;
4468 TargetLowering::ArgListEntry Entry;
4469 Args.reserve(CS.arg_size());
4470 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4472 SDValue ArgNode = getValue(*i);
4473 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4475 unsigned attrInd = i - CS.arg_begin() + 1;
4476 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4477 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4478 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4479 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4480 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4481 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4482 Entry.Alignment = CS.getParamAlignment(attrInd);
4483 Args.push_back(Entry);
4486 if (LandingPad && MMI) {
4487 // Insert a label before the invoke call to mark the try range. This can be
4488 // used to detect deletion of the invoke via the MachineModuleInfo.
4489 BeginLabel = MMI->NextLabelID();
4490 // Both PendingLoads and PendingExports must be flushed here;
4491 // this call might not return.
4493 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4494 getControlRoot(), BeginLabel));
4497 std::pair<SDValue,SDValue> Result =
4498 TLI.LowerCallTo(getRoot(), CS.getType(),
4499 CS.paramHasAttr(0, Attribute::SExt),
4500 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4501 CS.paramHasAttr(0, Attribute::InReg),
4502 CS.getCallingConv(),
4503 IsTailCall && PerformTailCallOpt,
4504 Callee, Args, DAG, getCurDebugLoc());
4505 if (CS.getType() != Type::VoidTy)
4506 setValue(CS.getInstruction(), Result.first);
4507 DAG.setRoot(Result.second);
4509 if (LandingPad && MMI) {
4510 // Insert a label at the end of the invoke call to mark the try range. This
4511 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4512 EndLabel = MMI->NextLabelID();
4513 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4514 getRoot(), EndLabel));
4516 // Inform MachineModuleInfo of range.
4517 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4522 void SelectionDAGLowering::visitCall(CallInst &I) {
4523 const char *RenameFn = 0;
4524 if (Function *F = I.getCalledFunction()) {
4525 if (F->isDeclaration()) {
4526 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4528 if (unsigned IID = II->getIntrinsicID(F)) {
4529 RenameFn = visitIntrinsicCall(I, IID);
4534 if (unsigned IID = F->getIntrinsicID()) {
4535 RenameFn = visitIntrinsicCall(I, IID);
4541 // Check for well-known libc/libm calls. If the function is internal, it
4542 // can't be a library call.
4543 unsigned NameLen = F->getNameLen();
4544 if (!F->hasLocalLinkage() && NameLen) {
4545 const char *NameStr = F->getNameStart();
4546 if (NameStr[0] == 'c' &&
4547 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4548 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4549 if (I.getNumOperands() == 3 && // Basic sanity checks.
4550 I.getOperand(1)->getType()->isFloatingPoint() &&
4551 I.getType() == I.getOperand(1)->getType() &&
4552 I.getType() == I.getOperand(2)->getType()) {
4553 SDValue LHS = getValue(I.getOperand(1));
4554 SDValue RHS = getValue(I.getOperand(2));
4555 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4556 LHS.getValueType(), LHS, RHS));
4559 } else if (NameStr[0] == 'f' &&
4560 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4561 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4562 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4563 if (I.getNumOperands() == 2 && // Basic sanity checks.
4564 I.getOperand(1)->getType()->isFloatingPoint() &&
4565 I.getType() == I.getOperand(1)->getType()) {
4566 SDValue Tmp = getValue(I.getOperand(1));
4567 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4568 Tmp.getValueType(), Tmp));
4571 } else if (NameStr[0] == 's' &&
4572 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4573 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4574 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4575 if (I.getNumOperands() == 2 && // Basic sanity checks.
4576 I.getOperand(1)->getType()->isFloatingPoint() &&
4577 I.getType() == I.getOperand(1)->getType()) {
4578 SDValue Tmp = getValue(I.getOperand(1));
4579 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4580 Tmp.getValueType(), Tmp));
4583 } else if (NameStr[0] == 'c' &&
4584 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4585 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4586 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4587 if (I.getNumOperands() == 2 && // Basic sanity checks.
4588 I.getOperand(1)->getType()->isFloatingPoint() &&
4589 I.getType() == I.getOperand(1)->getType()) {
4590 SDValue Tmp = getValue(I.getOperand(1));
4591 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4592 Tmp.getValueType(), Tmp));
4597 } else if (isa<InlineAsm>(I.getOperand(0))) {
4604 Callee = getValue(I.getOperand(0));
4606 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4608 LowerCallTo(&I, Callee, I.isTailCall());
4612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4613 /// this value and returns the result as a ValueVT value. This uses
4614 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4615 /// If the Flag pointer is NULL, no flag is used.
4616 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4618 SDValue *Flag) const {
4619 // Assemble the legal parts into the final values.
4620 SmallVector<SDValue, 4> Values(ValueVTs.size());
4621 SmallVector<SDValue, 8> Parts;
4622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4623 // Copy the legal parts from the registers.
4624 MVT ValueVT = ValueVTs[Value];
4625 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4626 MVT RegisterVT = RegVTs[Value];
4628 Parts.resize(NumRegs);
4629 for (unsigned i = 0; i != NumRegs; ++i) {
4632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4635 *Flag = P.getValue(2);
4637 Chain = P.getValue(1);
4639 // If the source register was virtual and if we know something about it,
4640 // add an assert node.
4641 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4642 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4643 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4644 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4645 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4646 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4648 unsigned RegSize = RegisterVT.getSizeInBits();
4649 unsigned NumSignBits = LOI.NumSignBits;
4650 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4652 // FIXME: We capture more information than the dag can represent. For
4653 // now, just use the tightest assertzext/assertsext possible.
4655 MVT FromVT(MVT::Other);
4656 if (NumSignBits == RegSize)
4657 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4658 else if (NumZeroBits >= RegSize-1)
4659 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4660 else if (NumSignBits > RegSize-8)
4661 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4662 else if (NumZeroBits >= RegSize-8)
4663 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4664 else if (NumSignBits > RegSize-16)
4665 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4666 else if (NumZeroBits >= RegSize-16)
4667 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4668 else if (NumSignBits > RegSize-32)
4669 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4670 else if (NumZeroBits >= RegSize-32)
4671 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4673 if (FromVT != MVT::Other) {
4674 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4675 RegisterVT, P, DAG.getValueType(FromVT));
4684 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4685 NumRegs, RegisterVT, ValueVT);
4690 return DAG.getNode(ISD::MERGE_VALUES, dl,
4691 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4692 &Values[0], ValueVTs.size());
4695 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4696 /// specified value into the registers specified by this object. This uses
4697 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4698 /// If the Flag pointer is NULL, no flag is used.
4699 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4700 SDValue &Chain, SDValue *Flag) const {
4701 // Get the list of the values's legal parts.
4702 unsigned NumRegs = Regs.size();
4703 SmallVector<SDValue, 8> Parts(NumRegs);
4704 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4705 MVT ValueVT = ValueVTs[Value];
4706 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4707 MVT RegisterVT = RegVTs[Value];
4709 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4710 &Parts[Part], NumParts, RegisterVT);
4714 // Copy the parts into the registers.
4715 SmallVector<SDValue, 8> Chains(NumRegs);
4716 for (unsigned i = 0; i != NumRegs; ++i) {
4719 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4722 *Flag = Part.getValue(1);
4724 Chains[i] = Part.getValue(0);
4727 if (NumRegs == 1 || Flag)
4728 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4729 // flagged to it. That is the CopyToReg nodes and the user are considered
4730 // a single scheduling unit. If we create a TokenFactor and return it as
4731 // chain, then the TokenFactor is both a predecessor (operand) of the
4732 // user as well as a successor (the TF operands are flagged to the user).
4733 // c1, f1 = CopyToReg
4734 // c2, f2 = CopyToReg
4735 // c3 = TokenFactor c1, c2
4738 Chain = Chains[NumRegs-1];
4740 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4743 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4744 /// operand list. This adds the code marker and includes the number of
4745 /// values added into it.
4746 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4747 bool HasMatching,unsigned MatchingIdx,
4749 std::vector<SDValue> &Ops) const {
4750 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4751 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4752 unsigned Flag = Code | (Regs.size() << 3);
4754 Flag |= 0x80000000 | (MatchingIdx << 16);
4755 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4756 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4757 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4758 MVT RegisterVT = RegVTs[Value];
4759 for (unsigned i = 0; i != NumRegs; ++i) {
4760 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4761 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4766 /// isAllocatableRegister - If the specified register is safe to allocate,
4767 /// i.e. it isn't a stack pointer or some other special register, return the
4768 /// register class for the register. Otherwise, return null.
4769 static const TargetRegisterClass *
4770 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4771 const TargetLowering &TLI,
4772 const TargetRegisterInfo *TRI) {
4773 MVT FoundVT = MVT::Other;
4774 const TargetRegisterClass *FoundRC = 0;
4775 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4776 E = TRI->regclass_end(); RCI != E; ++RCI) {
4777 MVT ThisVT = MVT::Other;
4779 const TargetRegisterClass *RC = *RCI;
4780 // If none of the the value types for this register class are valid, we
4781 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4782 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4784 if (TLI.isTypeLegal(*I)) {
4785 // If we have already found this register in a different register class,
4786 // choose the one with the largest VT specified. For example, on
4787 // PowerPC, we favor f64 register classes over f32.
4788 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4795 if (ThisVT == MVT::Other) continue;
4797 // NOTE: This isn't ideal. In particular, this might allocate the
4798 // frame pointer in functions that need it (due to them not being taken
4799 // out of allocation, because a variable sized allocation hasn't been seen
4800 // yet). This is a slight code pessimization, but should still work.
4801 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4802 E = RC->allocation_order_end(MF); I != E; ++I)
4804 // We found a matching register class. Keep looking at others in case
4805 // we find one with larger registers that this physreg is also in.
4816 /// AsmOperandInfo - This contains information for each constraint that we are
4818 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4819 public TargetLowering::AsmOperandInfo {
4821 /// CallOperand - If this is the result output operand or a clobber
4822 /// this is null, otherwise it is the incoming operand to the CallInst.
4823 /// This gets modified as the asm is processed.
4824 SDValue CallOperand;
4826 /// AssignedRegs - If this is a register or register class operand, this
4827 /// contains the set of register corresponding to the operand.
4828 RegsForValue AssignedRegs;
4830 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4831 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4834 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4835 /// busy in OutputRegs/InputRegs.
4836 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4837 std::set<unsigned> &OutputRegs,
4838 std::set<unsigned> &InputRegs,
4839 const TargetRegisterInfo &TRI) const {
4841 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4842 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4845 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4846 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4850 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4851 /// corresponds to. If there is no Value* for this operand, it returns
4853 MVT getCallOperandValMVT(const TargetLowering &TLI,
4854 const TargetData *TD) const {
4855 if (CallOperandVal == 0) return MVT::Other;
4857 if (isa<BasicBlock>(CallOperandVal))
4858 return TLI.getPointerTy();
4860 const llvm::Type *OpTy = CallOperandVal->getType();
4862 // If this is an indirect operand, the operand is a pointer to the
4865 OpTy = cast<PointerType>(OpTy)->getElementType();
4867 // If OpTy is not a single value, it may be a struct/union that we
4868 // can tile with integers.
4869 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4870 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4879 OpTy = IntegerType::get(BitSize);
4884 return TLI.getValueType(OpTy, true);
4888 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4890 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4891 const TargetRegisterInfo &TRI) {
4892 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4894 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4895 for (; *Aliases; ++Aliases)
4896 Regs.insert(*Aliases);
4899 } // end llvm namespace.
4902 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4903 /// specified operand. We prefer to assign virtual registers, to allow the
4904 /// register allocator handle the assignment process. However, if the asm uses
4905 /// features that we can't model on machineinstrs, we have SDISel do the
4906 /// allocation. This produces generally horrible, but correct, code.
4908 /// OpInfo describes the operand.
4909 /// Input and OutputRegs are the set of already allocated physical registers.
4911 void SelectionDAGLowering::
4912 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4913 std::set<unsigned> &OutputRegs,
4914 std::set<unsigned> &InputRegs) {
4915 // Compute whether this value requires an input register, an output register,
4917 bool isOutReg = false;
4918 bool isInReg = false;
4919 switch (OpInfo.Type) {
4920 case InlineAsm::isOutput:
4923 // If there is an input constraint that matches this, we need to reserve
4924 // the input register so no other inputs allocate to it.
4925 isInReg = OpInfo.hasMatchingInput();
4927 case InlineAsm::isInput:
4931 case InlineAsm::isClobber:
4938 MachineFunction &MF = DAG.getMachineFunction();
4939 SmallVector<unsigned, 4> Regs;
4941 // If this is a constraint for a single physreg, or a constraint for a
4942 // register class, find it.
4943 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4944 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4945 OpInfo.ConstraintVT);
4947 unsigned NumRegs = 1;
4948 if (OpInfo.ConstraintVT != MVT::Other) {
4949 // If this is a FP input in an integer register (or visa versa) insert a bit
4950 // cast of the input value. More generally, handle any case where the input
4951 // value disagrees with the register class we plan to stick this in.
4952 if (OpInfo.Type == InlineAsm::isInput &&
4953 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4954 // Try to convert to the first MVT that the reg class contains. If the
4955 // types are identical size, use a bitcast to convert (e.g. two differing
4957 MVT RegVT = *PhysReg.second->vt_begin();
4958 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4959 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4960 RegVT, OpInfo.CallOperand);
4961 OpInfo.ConstraintVT = RegVT;
4962 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4963 // If the input is a FP value and we want it in FP registers, do a
4964 // bitcast to the corresponding integer type. This turns an f64 value
4965 // into i64, which can be passed with two i32 values on a 32-bit
4967 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4968 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4969 RegVT, OpInfo.CallOperand);
4970 OpInfo.ConstraintVT = RegVT;
4974 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4978 MVT ValueVT = OpInfo.ConstraintVT;
4980 // If this is a constraint for a specific physical register, like {r17},
4982 if (unsigned AssignedReg = PhysReg.first) {
4983 const TargetRegisterClass *RC = PhysReg.second;
4984 if (OpInfo.ConstraintVT == MVT::Other)
4985 ValueVT = *RC->vt_begin();
4987 // Get the actual register value type. This is important, because the user
4988 // may have asked for (e.g.) the AX register in i32 type. We need to
4989 // remember that AX is actually i16 to get the right extension.
4990 RegVT = *RC->vt_begin();
4992 // This is a explicit reference to a physical register.
4993 Regs.push_back(AssignedReg);
4995 // If this is an expanded reference, add the rest of the regs to Regs.
4997 TargetRegisterClass::iterator I = RC->begin();
4998 for (; *I != AssignedReg; ++I)
4999 assert(I != RC->end() && "Didn't find reg!");
5001 // Already added the first reg.
5003 for (; NumRegs; --NumRegs, ++I) {
5004 assert(I != RC->end() && "Ran out of registers to allocate!");
5008 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5009 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5010 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5014 // Otherwise, if this was a reference to an LLVM register class, create vregs
5015 // for this reference.
5016 if (const TargetRegisterClass *RC = PhysReg.second) {
5017 RegVT = *RC->vt_begin();
5018 if (OpInfo.ConstraintVT == MVT::Other)
5021 // Create the appropriate number of virtual registers.
5022 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5023 for (; NumRegs; --NumRegs)
5024 Regs.push_back(RegInfo.createVirtualRegister(RC));
5026 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5030 // This is a reference to a register class that doesn't directly correspond
5031 // to an LLVM register class. Allocate NumRegs consecutive, available,
5032 // registers from the class.
5033 std::vector<unsigned> RegClassRegs
5034 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5035 OpInfo.ConstraintVT);
5037 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5038 unsigned NumAllocated = 0;
5039 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5040 unsigned Reg = RegClassRegs[i];
5041 // See if this register is available.
5042 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5043 (isInReg && InputRegs.count(Reg))) { // Already used.
5044 // Make sure we find consecutive registers.
5049 // Check to see if this register is allocatable (i.e. don't give out the
5051 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5052 if (!RC) { // Couldn't allocate this register.
5053 // Reset NumAllocated to make sure we return consecutive registers.
5058 // Okay, this register is good, we can use it.
5061 // If we allocated enough consecutive registers, succeed.
5062 if (NumAllocated == NumRegs) {
5063 unsigned RegStart = (i-NumAllocated)+1;
5064 unsigned RegEnd = i+1;
5065 // Mark all of the allocated registers used.
5066 for (unsigned i = RegStart; i != RegEnd; ++i)
5067 Regs.push_back(RegClassRegs[i]);
5069 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5070 OpInfo.ConstraintVT);
5071 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5076 // Otherwise, we couldn't allocate enough registers for this.
5079 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5080 /// processed uses a memory 'm' constraint.
5082 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5083 const TargetLowering &TLI) {
5084 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5085 InlineAsm::ConstraintInfo &CI = CInfos[i];
5086 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5087 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5088 if (CType == TargetLowering::C_Memory)
5096 /// visitInlineAsm - Handle a call to an InlineAsm object.
5098 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5099 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5101 /// ConstraintOperands - Information about all of the constraints.
5102 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5104 // We won't need to flush pending loads if this asm doesn't touch
5105 // memory and is nonvolatile.
5106 SDValue Chain = IA->hasSideEffects() ? getRoot() : DAG.getRoot();
5109 std::set<unsigned> OutputRegs, InputRegs;
5111 // Do a prepass over the constraints, canonicalizing them, and building up the
5112 // ConstraintOperands list.
5113 std::vector<InlineAsm::ConstraintInfo>
5114 ConstraintInfos = IA->ParseConstraints();
5116 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5117 // Flush pending loads if this touches memory (includes clobbering it).
5118 // It's possible this is overly conservative.
5122 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5123 unsigned ResNo = 0; // ResNo - The result number of the next output.
5124 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5125 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5126 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5128 MVT OpVT = MVT::Other;
5130 // Compute the value type for each operand.
5131 switch (OpInfo.Type) {
5132 case InlineAsm::isOutput:
5133 // Indirect outputs just consume an argument.
5134 if (OpInfo.isIndirect) {
5135 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5139 // The return value of the call is this value. As such, there is no
5140 // corresponding argument.
5141 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5142 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5143 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5145 assert(ResNo == 0 && "Asm only has one result!");
5146 OpVT = TLI.getValueType(CS.getType());
5150 case InlineAsm::isInput:
5151 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5153 case InlineAsm::isClobber:
5158 // If this is an input or an indirect output, process the call argument.
5159 // BasicBlocks are labels, currently appearing only in asm's.
5160 if (OpInfo.CallOperandVal) {
5161 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5162 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5164 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5167 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5170 OpInfo.ConstraintVT = OpVT;
5173 // Second pass over the constraints: compute which constraint option to use
5174 // and assign registers to constraints that want a specific physreg.
5175 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5176 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5178 // If this is an output operand with a matching input operand, look up the
5179 // matching input. If their types mismatch, e.g. one is an integer, the
5180 // other is floating point, or their sizes are different, flag it as an
5182 if (OpInfo.hasMatchingInput()) {
5183 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5184 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5185 if ((OpInfo.ConstraintVT.isInteger() !=
5186 Input.ConstraintVT.isInteger()) ||
5187 (OpInfo.ConstraintVT.getSizeInBits() !=
5188 Input.ConstraintVT.getSizeInBits())) {
5189 cerr << "llvm: error: Unsupported asm: input constraint with a "
5190 << "matching output constraint of incompatible type!\n";
5193 Input.ConstraintVT = OpInfo.ConstraintVT;
5197 // Compute the constraint code and ConstraintType to use.
5198 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5200 // If this is a memory input, and if the operand is not indirect, do what we
5201 // need to to provide an address for the memory input.
5202 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5203 !OpInfo.isIndirect) {
5204 assert(OpInfo.Type == InlineAsm::isInput &&
5205 "Can only indirectify direct input operands!");
5207 // Memory operands really want the address of the value. If we don't have
5208 // an indirect input, put it in the constpool if we can, otherwise spill
5209 // it to a stack slot.
5211 // If the operand is a float, integer, or vector constant, spill to a
5212 // constant pool entry to get its address.
5213 Value *OpVal = OpInfo.CallOperandVal;
5214 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5215 isa<ConstantVector>(OpVal)) {
5216 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5217 TLI.getPointerTy());
5219 // Otherwise, create a stack slot and emit a store to it before the
5221 const Type *Ty = OpVal->getType();
5222 uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty);
5223 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5224 MachineFunction &MF = DAG.getMachineFunction();
5225 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5226 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5227 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5228 OpInfo.CallOperand, StackSlot, NULL, 0);
5229 OpInfo.CallOperand = StackSlot;
5232 // There is no longer a Value* corresponding to this operand.
5233 OpInfo.CallOperandVal = 0;
5234 // It is now an indirect operand.
5235 OpInfo.isIndirect = true;
5238 // If this constraint is for a specific register, allocate it before
5240 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5241 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5243 ConstraintInfos.clear();
5246 // Second pass - Loop over all of the operands, assigning virtual or physregs
5247 // to register class operands.
5248 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5249 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5251 // C_Register operands have already been allocated, Other/Memory don't need
5253 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5254 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5257 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5258 std::vector<SDValue> AsmNodeOperands;
5259 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5260 AsmNodeOperands.push_back(
5261 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5264 // Loop over all of the inputs, copying the operand values into the
5265 // appropriate registers and processing the output regs.
5266 RegsForValue RetValRegs;
5268 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5269 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5271 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5272 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5274 switch (OpInfo.Type) {
5275 case InlineAsm::isOutput: {
5276 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5277 OpInfo.ConstraintType != TargetLowering::C_Register) {
5278 // Memory output, or 'other' output (e.g. 'X' constraint).
5279 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5281 // Add information to the INLINEASM node to know about this output.
5282 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5283 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5284 TLI.getPointerTy()));
5285 AsmNodeOperands.push_back(OpInfo.CallOperand);
5289 // Otherwise, this is a register or register class output.
5291 // Copy the output from the appropriate register. Find a register that
5293 if (OpInfo.AssignedRegs.Regs.empty()) {
5294 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5295 << OpInfo.ConstraintCode << "'!\n";
5299 // If this is an indirect operand, store through the pointer after the
5301 if (OpInfo.isIndirect) {
5302 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5303 OpInfo.CallOperandVal));
5305 // This is the result value of the call.
5306 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5307 // Concatenate this output onto the outputs list.
5308 RetValRegs.append(OpInfo.AssignedRegs);
5311 // Add information to the INLINEASM node to know that this register is
5313 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5314 6 /* EARLYCLOBBER REGDEF */ :
5318 DAG, AsmNodeOperands);
5321 case InlineAsm::isInput: {
5322 SDValue InOperandVal = OpInfo.CallOperand;
5324 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5325 // If this is required to match an output register we have already set,
5326 // just use its register.
5327 unsigned OperandNo = OpInfo.getMatchedOperand();
5329 // Scan until we find the definition we already emitted of this operand.
5330 // When we find it, create a RegsForValue operand.
5331 unsigned CurOp = 2; // The first operand.
5332 for (; OperandNo; --OperandNo) {
5333 // Advance to the next operand.
5335 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5336 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5337 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5338 (OpFlag & 7) == 4 /*MEM*/) &&
5339 "Skipped past definitions?");
5340 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5344 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5345 if ((OpFlag & 7) == 2 /*REGDEF*/
5346 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5347 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5348 RegsForValue MatchedRegs;
5349 MatchedRegs.TLI = &TLI;
5350 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5351 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5352 MatchedRegs.RegVTs.push_back(RegVT);
5353 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5354 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5357 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5359 // Use the produced MatchedRegs object to
5360 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5362 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5363 true, OpInfo.getMatchedOperand(),
5364 DAG, AsmNodeOperands);
5367 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5368 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5369 "Unexpected number of operands");
5370 // Add information to the INLINEASM node to know about this input.
5371 // See InlineAsm.h isUseOperandTiedToDef.
5372 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5373 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5374 TLI.getPointerTy()));
5375 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5380 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5381 assert(!OpInfo.isIndirect &&
5382 "Don't know how to handle indirect other inputs yet!");
5384 std::vector<SDValue> Ops;
5385 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5386 hasMemory, Ops, DAG);
5388 cerr << "llvm: error: Invalid operand for inline asm constraint '"
5389 << OpInfo.ConstraintCode << "'!\n";
5393 // Add information to the INLINEASM node to know about this input.
5394 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5395 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5396 TLI.getPointerTy()));
5397 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5399 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5400 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5401 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5402 "Memory operands expect pointer values");
5404 // Add information to the INLINEASM node to know about this input.
5405 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5406 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5407 TLI.getPointerTy()));
5408 AsmNodeOperands.push_back(InOperandVal);
5412 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5413 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5414 "Unknown constraint type!");
5415 assert(!OpInfo.isIndirect &&
5416 "Don't know how to handle indirect register inputs yet!");
5418 // Copy the input into the appropriate registers.
5419 if (OpInfo.AssignedRegs.Regs.empty()) {
5420 cerr << "llvm: error: Couldn't allocate output reg for constraint '"
5421 << OpInfo.ConstraintCode << "'!\n";
5425 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5428 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5429 DAG, AsmNodeOperands);
5432 case InlineAsm::isClobber: {
5433 // Add the clobbered value to the operand list, so that the register
5434 // allocator is aware that the physreg got clobbered.
5435 if (!OpInfo.AssignedRegs.Regs.empty())
5436 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5437 false, 0, DAG,AsmNodeOperands);
5443 // Finish up input operands.
5444 AsmNodeOperands[0] = Chain;
5445 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5447 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5448 DAG.getVTList(MVT::Other, MVT::Flag),
5449 &AsmNodeOperands[0], AsmNodeOperands.size());
5450 Flag = Chain.getValue(1);
5452 // If this asm returns a register value, copy the result from that register
5453 // and set it as the value of the call.
5454 if (!RetValRegs.Regs.empty()) {
5455 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5458 // FIXME: Why don't we do this for inline asms with MRVs?
5459 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5460 MVT ResultType = TLI.getValueType(CS.getType());
5462 // If any of the results of the inline asm is a vector, it may have the
5463 // wrong width/num elts. This can happen for register classes that can
5464 // contain multiple different value types. The preg or vreg allocated may
5465 // not have the same VT as was expected. Convert it to the right type
5466 // with bit_convert.
5467 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5468 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5471 } else if (ResultType != Val.getValueType() &&
5472 ResultType.isInteger() && Val.getValueType().isInteger()) {
5473 // If a result value was tied to an input value, the computed result may
5474 // have a wider width than the expected result. Extract the relevant
5476 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5479 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5482 setValue(CS.getInstruction(), Val);
5483 // Don't need to use this as a chain in this case.
5484 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5488 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5490 // Process indirect outputs, first output all of the flagged copies out of
5492 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5493 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5494 Value *Ptr = IndirectStoresToEmit[i].second;
5495 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5497 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5500 // Emit the non-flagged stores from the physregs.
5501 SmallVector<SDValue, 8> OutChains;
5502 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5503 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5504 StoresToEmit[i].first,
5505 getValue(StoresToEmit[i].second),
5506 StoresToEmit[i].second, 0));
5507 if (!OutChains.empty())
5508 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5509 &OutChains[0], OutChains.size());
5514 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5515 SDValue Src = getValue(I.getOperand(0));
5517 // Scale up by the type size in the original i32 type width. Various
5518 // mid-level optimizers may make assumptions about demanded bits etc from the
5519 // i32-ness of the optimizer: we do not want to promote to i64 and then
5520 // multiply on 64-bit targets.
5521 // FIXME: Malloc inst should go away: PR715.
5522 uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType());
5523 if (ElementSize != 1)
5524 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5525 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5527 MVT IntPtr = TLI.getPointerTy();
5529 if (IntPtr.bitsLT(Src.getValueType()))
5530 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5531 else if (IntPtr.bitsGT(Src.getValueType()))
5532 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5534 TargetLowering::ArgListTy Args;
5535 TargetLowering::ArgListEntry Entry;
5537 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5538 Args.push_back(Entry);
5540 std::pair<SDValue,SDValue> Result =
5541 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5542 CallingConv::C, PerformTailCallOpt,
5543 DAG.getExternalSymbol("malloc", IntPtr),
5544 Args, DAG, getCurDebugLoc());
5545 setValue(&I, Result.first); // Pointers always fit in registers
5546 DAG.setRoot(Result.second);
5549 void SelectionDAGLowering::visitFree(FreeInst &I) {
5550 TargetLowering::ArgListTy Args;
5551 TargetLowering::ArgListEntry Entry;
5552 Entry.Node = getValue(I.getOperand(0));
5553 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5554 Args.push_back(Entry);
5555 MVT IntPtr = TLI.getPointerTy();
5556 std::pair<SDValue,SDValue> Result =
5557 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5558 CallingConv::C, PerformTailCallOpt,
5559 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5561 DAG.setRoot(Result.second);
5564 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5565 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5566 MVT::Other, getRoot(),
5567 getValue(I.getOperand(1)),
5568 DAG.getSrcValue(I.getOperand(1))));
5571 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5572 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5573 getRoot(), getValue(I.getOperand(0)),
5574 DAG.getSrcValue(I.getOperand(0)));
5576 DAG.setRoot(V.getValue(1));
5579 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5580 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5581 MVT::Other, getRoot(),
5582 getValue(I.getOperand(1)),
5583 DAG.getSrcValue(I.getOperand(1))));
5586 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5587 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5588 MVT::Other, getRoot(),
5589 getValue(I.getOperand(1)),
5590 getValue(I.getOperand(2)),
5591 DAG.getSrcValue(I.getOperand(1)),
5592 DAG.getSrcValue(I.getOperand(2))));
5595 /// TargetLowering::LowerArguments - This is the default LowerArguments
5596 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5597 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5598 /// integrated into SDISel.
5599 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5600 SmallVectorImpl<SDValue> &ArgValues,
5602 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5603 SmallVector<SDValue, 3+16> Ops;
5604 Ops.push_back(DAG.getRoot());
5605 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5606 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5608 // Add one result value for each formal argument.
5609 SmallVector<MVT, 16> RetVals;
5611 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5613 SmallVector<MVT, 4> ValueVTs;
5614 ComputeValueVTs(*this, I->getType(), ValueVTs);
5615 for (unsigned Value = 0, NumValues = ValueVTs.size();
5616 Value != NumValues; ++Value) {
5617 MVT VT = ValueVTs[Value];
5618 const Type *ArgTy = VT.getTypeForMVT();
5619 ISD::ArgFlagsTy Flags;
5620 unsigned OriginalAlignment =
5621 getTargetData()->getABITypeAlignment(ArgTy);
5623 if (F.paramHasAttr(j, Attribute::ZExt))
5625 if (F.paramHasAttr(j, Attribute::SExt))
5627 if (F.paramHasAttr(j, Attribute::InReg))
5629 if (F.paramHasAttr(j, Attribute::StructRet))
5631 if (F.paramHasAttr(j, Attribute::ByVal)) {
5633 const PointerType *Ty = cast<PointerType>(I->getType());
5634 const Type *ElementTy = Ty->getElementType();
5635 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5636 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5637 // For ByVal, alignment should be passed from FE. BE will guess if
5638 // this info is not there but there are cases it cannot get right.
5639 if (F.getParamAlignment(j))
5640 FrameAlign = F.getParamAlignment(j);
5641 Flags.setByValAlign(FrameAlign);
5642 Flags.setByValSize(FrameSize);
5644 if (F.paramHasAttr(j, Attribute::Nest))
5646 Flags.setOrigAlign(OriginalAlignment);
5648 MVT RegisterVT = getRegisterType(VT);
5649 unsigned NumRegs = getNumRegisters(VT);
5650 for (unsigned i = 0; i != NumRegs; ++i) {
5651 RetVals.push_back(RegisterVT);
5652 ISD::ArgFlagsTy MyFlags = Flags;
5653 if (NumRegs > 1 && i == 0)
5655 // if it isn't first piece, alignment must be 1
5657 MyFlags.setOrigAlign(1);
5658 Ops.push_back(DAG.getArgFlags(MyFlags));
5663 RetVals.push_back(MVT::Other);
5666 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5667 DAG.getVTList(&RetVals[0], RetVals.size()),
5668 &Ops[0], Ops.size()).getNode();
5670 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5671 // allows exposing the loads that may be part of the argument access to the
5672 // first DAGCombiner pass.
5673 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5675 // The number of results should match up, except that the lowered one may have
5676 // an extra flag result.
5677 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5678 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5679 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5680 && "Lowering produced unexpected number of results!");
5682 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5683 if (Result != TmpRes.getNode() && Result->use_empty()) {
5684 HandleSDNode Dummy(DAG.getRoot());
5685 DAG.RemoveDeadNode(Result);
5688 Result = TmpRes.getNode();
5690 unsigned NumArgRegs = Result->getNumValues() - 1;
5691 DAG.setRoot(SDValue(Result, NumArgRegs));
5693 // Set up the return result vector.
5696 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5698 SmallVector<MVT, 4> ValueVTs;
5699 ComputeValueVTs(*this, I->getType(), ValueVTs);
5700 for (unsigned Value = 0, NumValues = ValueVTs.size();
5701 Value != NumValues; ++Value) {
5702 MVT VT = ValueVTs[Value];
5703 MVT PartVT = getRegisterType(VT);
5705 unsigned NumParts = getNumRegisters(VT);
5706 SmallVector<SDValue, 4> Parts(NumParts);
5707 for (unsigned j = 0; j != NumParts; ++j)
5708 Parts[j] = SDValue(Result, i++);
5710 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5711 if (F.paramHasAttr(Idx, Attribute::SExt))
5712 AssertOp = ISD::AssertSext;
5713 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5714 AssertOp = ISD::AssertZext;
5716 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5717 PartVT, VT, AssertOp));
5720 assert(i == NumArgRegs && "Argument register count mismatch!");
5724 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5725 /// implementation, which just inserts an ISD::CALL node, which is later custom
5726 /// lowered by the target to something concrete. FIXME: When all targets are
5727 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5728 std::pair<SDValue, SDValue>
5729 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5730 bool RetSExt, bool RetZExt, bool isVarArg,
5732 unsigned CallingConv, bool isTailCall,
5734 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5735 assert((!isTailCall || PerformTailCallOpt) &&
5736 "isTailCall set when tail-call optimizations are disabled!");
5738 SmallVector<SDValue, 32> Ops;
5739 Ops.push_back(Chain); // Op#0 - Chain
5740 Ops.push_back(Callee);
5742 // Handle all of the outgoing arguments.
5743 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5744 SmallVector<MVT, 4> ValueVTs;
5745 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5746 for (unsigned Value = 0, NumValues = ValueVTs.size();
5747 Value != NumValues; ++Value) {
5748 MVT VT = ValueVTs[Value];
5749 const Type *ArgTy = VT.getTypeForMVT();
5750 SDValue Op = SDValue(Args[i].Node.getNode(),
5751 Args[i].Node.getResNo() + Value);
5752 ISD::ArgFlagsTy Flags;
5753 unsigned OriginalAlignment =
5754 getTargetData()->getABITypeAlignment(ArgTy);
5760 if (Args[i].isInReg)
5764 if (Args[i].isByVal) {
5766 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5767 const Type *ElementTy = Ty->getElementType();
5768 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5769 unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy);
5770 // For ByVal, alignment should come from FE. BE will guess if this
5771 // info is not there but there are cases it cannot get right.
5772 if (Args[i].Alignment)
5773 FrameAlign = Args[i].Alignment;
5774 Flags.setByValAlign(FrameAlign);
5775 Flags.setByValSize(FrameSize);
5779 Flags.setOrigAlign(OriginalAlignment);
5781 MVT PartVT = getRegisterType(VT);
5782 unsigned NumParts = getNumRegisters(VT);
5783 SmallVector<SDValue, 4> Parts(NumParts);
5784 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5787 ExtendKind = ISD::SIGN_EXTEND;
5788 else if (Args[i].isZExt)
5789 ExtendKind = ISD::ZERO_EXTEND;
5791 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5793 for (unsigned i = 0; i != NumParts; ++i) {
5794 // if it isn't first piece, alignment must be 1
5795 ISD::ArgFlagsTy MyFlags = Flags;
5796 if (NumParts > 1 && i == 0)
5799 MyFlags.setOrigAlign(1);
5801 Ops.push_back(Parts[i]);
5802 Ops.push_back(DAG.getArgFlags(MyFlags));
5807 // Figure out the result value types. We start by making a list of
5808 // the potentially illegal return value types.
5809 SmallVector<MVT, 4> LoweredRetTys;
5810 SmallVector<MVT, 4> RetTys;
5811 ComputeValueVTs(*this, RetTy, RetTys);
5813 // Then we translate that to a list of legal types.
5814 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5816 MVT RegisterVT = getRegisterType(VT);
5817 unsigned NumRegs = getNumRegisters(VT);
5818 for (unsigned i = 0; i != NumRegs; ++i)
5819 LoweredRetTys.push_back(RegisterVT);
5822 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5824 // Create the CALL node.
5825 SDValue Res = DAG.getCall(CallingConv, dl,
5826 isVarArg, isTailCall, isInreg,
5827 DAG.getVTList(&LoweredRetTys[0],
5828 LoweredRetTys.size()),
5831 Chain = Res.getValue(LoweredRetTys.size() - 1);
5833 // Gather up the call result into a single value.
5834 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5835 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5838 AssertOp = ISD::AssertSext;
5840 AssertOp = ISD::AssertZext;
5842 SmallVector<SDValue, 4> ReturnValues;
5844 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5846 MVT RegisterVT = getRegisterType(VT);
5847 unsigned NumRegs = getNumRegisters(VT);
5848 unsigned RegNoEnd = NumRegs + RegNo;
5849 SmallVector<SDValue, 4> Results;
5850 for (; RegNo != RegNoEnd; ++RegNo)
5851 Results.push_back(Res.getValue(RegNo));
5852 SDValue ReturnValue =
5853 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5855 ReturnValues.push_back(ReturnValue);
5857 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5858 DAG.getVTList(&RetTys[0], RetTys.size()),
5859 &ReturnValues[0], ReturnValues.size());
5862 return std::make_pair(Res, Chain);
5865 void TargetLowering::LowerOperationWrapper(SDNode *N,
5866 SmallVectorImpl<SDValue> &Results,
5867 SelectionDAG &DAG) {
5868 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5870 Results.push_back(Res);
5873 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5874 assert(0 && "LowerOperation not implemented for this target!");
5880 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5881 SDValue Op = getValue(V);
5882 assert((Op.getOpcode() != ISD::CopyFromReg ||
5883 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5884 "Copy from a reg to the same reg!");
5885 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5887 RegsForValue RFV(TLI, Reg, V->getType());
5888 SDValue Chain = DAG.getEntryNode();
5889 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5890 PendingExports.push_back(Chain);
5893 #include "llvm/CodeGen/SelectionDAGISel.h"
5895 void SelectionDAGISel::
5896 LowerArguments(BasicBlock *LLVMBB) {
5897 // If this is the entry block, emit arguments.
5898 Function &F = *LLVMBB->getParent();
5899 SDValue OldRoot = SDL->DAG.getRoot();
5900 SmallVector<SDValue, 16> Args;
5901 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5904 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5906 SmallVector<MVT, 4> ValueVTs;
5907 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5908 unsigned NumValues = ValueVTs.size();
5909 if (!AI->use_empty()) {
5910 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5911 SDL->getCurDebugLoc()));
5912 // If this argument is live outside of the entry block, insert a copy from
5913 // whereever we got it to the vreg that other BB's will reference it as.
5914 SDL->CopyToExportRegsIfNeeded(AI);
5919 // Finally, if the target has anything special to do, allow it to do so.
5920 // FIXME: this should insert code into the DAG!
5921 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5924 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5925 /// ensure constants are generated when needed. Remember the virtual registers
5926 /// that need to be added to the Machine PHI nodes as input. We cannot just
5927 /// directly add them, because expansion might result in multiple MBB's for one
5928 /// BB. As such, the start of the BB might correspond to a different MBB than
5932 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5933 TerminatorInst *TI = LLVMBB->getTerminator();
5935 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5937 // Check successor nodes' PHI nodes that expect a constant to be available
5939 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5940 BasicBlock *SuccBB = TI->getSuccessor(succ);
5941 if (!isa<PHINode>(SuccBB->begin())) continue;
5942 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5944 // If this terminator has multiple identical successors (common for
5945 // switches), only handle each succ once.
5946 if (!SuccsHandled.insert(SuccMBB)) continue;
5948 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5951 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5952 // nodes and Machine PHI nodes, but the incoming operands have not been
5954 for (BasicBlock::iterator I = SuccBB->begin();
5955 (PN = dyn_cast<PHINode>(I)); ++I) {
5956 // Ignore dead phi's.
5957 if (PN->use_empty()) continue;
5960 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5962 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5963 unsigned &RegOut = SDL->ConstantsOut[C];
5965 RegOut = FuncInfo->CreateRegForValue(C);
5966 SDL->CopyValueToVirtualRegister(C, RegOut);
5970 Reg = FuncInfo->ValueMap[PHIOp];
5972 assert(isa<AllocaInst>(PHIOp) &&
5973 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5974 "Didn't codegen value into a register!??");
5975 Reg = FuncInfo->CreateRegForValue(PHIOp);
5976 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5980 // Remember that this register needs to added to the machine PHI node as
5981 // the input for this MBB.
5982 SmallVector<MVT, 4> ValueVTs;
5983 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5984 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5985 MVT VT = ValueVTs[vti];
5986 unsigned NumRegisters = TLI.getNumRegisters(VT);
5987 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5988 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5989 Reg += NumRegisters;
5993 SDL->ConstantsOut.clear();
5996 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5997 /// supports legal types, and it emits MachineInstrs directly instead of
5998 /// creating SelectionDAG nodes.
6001 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6003 TerminatorInst *TI = LLVMBB->getTerminator();
6005 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6006 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6008 // Check successor nodes' PHI nodes that expect a constant to be available
6010 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6011 BasicBlock *SuccBB = TI->getSuccessor(succ);
6012 if (!isa<PHINode>(SuccBB->begin())) continue;
6013 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6015 // If this terminator has multiple identical successors (common for
6016 // switches), only handle each succ once.
6017 if (!SuccsHandled.insert(SuccMBB)) continue;
6019 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6022 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6023 // nodes and Machine PHI nodes, but the incoming operands have not been
6025 for (BasicBlock::iterator I = SuccBB->begin();
6026 (PN = dyn_cast<PHINode>(I)); ++I) {
6027 // Ignore dead phi's.
6028 if (PN->use_empty()) continue;
6030 // Only handle legal types. Two interesting things to note here. First,
6031 // by bailing out early, we may leave behind some dead instructions,
6032 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6033 // own moves. Second, this check is necessary becuase FastISel doesn't
6034 // use CreateRegForValue to create registers, so it always creates
6035 // exactly one register for each non-void instruction.
6036 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6037 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6040 VT = TLI.getTypeToTransformTo(VT);
6042 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6047 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6049 unsigned Reg = F->getRegForValue(PHIOp);
6051 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6054 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));