1 //===-- ScheduleDAGSimple.cpp - Implement a trivial DAG scheduler ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
29 // Style of scheduling to use.
30 enum ScheduleChoices {
33 simpleNoItinScheduling
37 cl::opt<ScheduleChoices> ScheduleStyle("sched",
38 cl::desc("Choose scheduling style"),
39 cl::init(noScheduling),
41 clEnumValN(noScheduling, "none",
42 "Trivial emission with no analysis"),
43 clEnumValN(simpleScheduling, "simple",
44 "Minimize critical path and maximize processor utilization"),
45 clEnumValN(simpleNoItinScheduling, "simple-noitin",
46 "Same as simple except using generic latency"),
51 //===----------------------------------------------------------------------===//
53 /// BitsIterator - Provides iteration through individual bits in a bit vector.
58 T Bits; // Bits left to iterate through
62 BitsIterator(T Initial) : Bits(Initial) {}
64 /// Next - Returns the next bit set or zero if exhausted.
66 // Get the rightmost bit set
67 T Result = Bits & -Bits;
70 // Return single bit or zero
75 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 /// ResourceTally - Manages the use of resources over time intervals. Each
81 /// item (slot) in the tally vector represents the resources used at a given
82 /// moment. A bit set to 1 indicates that a resource is in use, otherwise
83 /// available. An assumption is made that the tally is large enough to schedule
84 /// all current instructions (asserts otherwise.)
89 std::vector<T> Tally; // Resources used per slot
90 typedef typename std::vector<T>::iterator Iter;
93 /// SlotsAvailable - Returns true if all units are available.
95 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
97 assert(N && "Must check availability with N != 0");
98 // Determine end of interval
100 assert(End <= Tally.end() && "Tally is not large enough for schedule");
102 // Iterate thru each resource
103 BitsIterator<T> Resources(ResourceSet & ~*Begin);
104 while (unsigned Res = Resources.Next()) {
105 // Check if resource is available for next N slots
109 if (*Interval & Res) break;
110 } while (Interval != Begin);
112 // If available for N
113 if (Interval == Begin) {
125 /// RetrySlot - Finds a good candidate slot to retry search.
126 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
127 assert(N && "Must check availability with N != 0");
128 // Determine end of interval
129 Iter End = Begin + N;
130 assert(End <= Tally.end() && "Tally is not large enough for schedule");
132 while (Begin != End--) {
133 // Clear units in use
134 ResourceSet &= ~*End;
135 // If no units left then we should go no further
136 if (!ResourceSet) return End + 1;
138 // Made it all the way through
142 /// FindAndReserveStages - Return true if the stages can be completed. If
144 bool FindAndReserveStages(Iter Begin,
145 InstrStage *Stage, InstrStage *StageEnd) {
146 // If at last stage then we're done
147 if (Stage == StageEnd) return true;
148 // Get number of cycles for current stage
149 unsigned N = Stage->Cycles;
150 // Check to see if N slots are available, if not fail
152 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
153 // Check to see if remaining stages are available, if not fail
154 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
156 Reserve(Begin, N, Resource);
161 /// Reserve - Mark busy (set) the specified N slots.
162 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
163 // Determine end of interval
164 Iter End = Begin + N;
165 assert(End <= Tally.end() && "Tally is not large enough for schedule");
167 // Set resource bit in each slot
168 for (; Begin < End; Begin++)
172 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
173 /// can be completed. Returns the address of first slot.
174 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
178 // Try all possible slots forward
180 // Try at cursor, if successful return position.
181 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
182 // Locate a better position
183 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
188 /// Initialize - Resize and zero the tally to the specified number of time
190 inline void Initialize(unsigned N) {
191 Tally.assign(N, 0); // Initialize tally to all zeros.
194 // FindAndReserve - Locate an ideal slot for the specified stages and mark
196 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
197 InstrStage *StageEnd) {
199 Iter Begin = Tally.begin() + Slot;
201 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
202 // Distance is slot number
203 unsigned Final = Where - Tally.begin();
209 //===----------------------------------------------------------------------===//
211 /// ScheduleDAGSimple - Simple two pass scheduler.
213 class ScheduleDAGSimple : public ScheduleDAG {
215 unsigned NodeCount; // Number of nodes in DAG
216 bool HasGroups; // True if there are any groups
217 NodeInfo *Info; // Info for nodes being scheduled
218 NIVector Ordering; // Emit ordering of nodes
219 ResourceTally<unsigned> Tally; // Resource usage tally
220 unsigned NSlots; // Total latency
221 static const unsigned NotFound = ~0U; // Search marker
226 ScheduleDAGSimple(SelectionDAG &dag, MachineBasicBlock *bb,
227 const TargetMachine &tm)
228 : ScheduleDAG(dag, bb, tm),
229 NodeCount(0), HasGroups(false), Info(NULL), Tally(), NSlots(0) {
230 assert(&TII && "Target doesn't provide instr info?");
231 assert(&MRI && "Target doesn't provide register info?");
234 virtual ~ScheduleDAGSimple() {};
237 static bool isFlagDefiner(SDNode *A);
238 static bool isFlagUser(SDNode *A);
239 static bool isDefiner(NodeInfo *A, NodeInfo *B);
240 static bool isPassiveNode(SDNode *Node);
241 void IncludeNode(NodeInfo *NI);
244 void IdentifyGroups();
245 void GatherSchedulingInfo();
246 void FakeGroupDominators();
247 void PrepareNodeInfo();
248 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
249 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
250 void ScheduleBackward();
251 void ScheduleForward();
254 void printChanges(unsigned Index);
255 void printSI(std::ostream &O, NodeInfo *NI) const;
256 void print(std::ostream &O) const;
260 //===----------------------------------------------------------------------===//
261 /// Special case itineraries.
264 CallLatency = 40, // To push calls back in time
266 RSInteger = 0xC0000000, // Two integer units
267 RSFloat = 0x30000000, // Two float units
268 RSLoadStore = 0x0C000000, // Two load store units
269 RSBranch = 0x02000000 // One branch unit
271 static InstrStage CallStage = { CallLatency, RSBranch };
272 static InstrStage LoadStage = { 5, RSLoadStore };
273 static InstrStage StoreStage = { 2, RSLoadStore };
274 static InstrStage IntStage = { 2, RSInteger };
275 static InstrStage FloatStage = { 3, RSFloat };
276 //===----------------------------------------------------------------------===//
279 //===----------------------------------------------------------------------===//
283 //===----------------------------------------------------------------------===//
286 //===----------------------------------------------------------------------===//
287 /// Add - Adds a definer and user pair to a node group.
289 void NodeGroup::Add(NodeInfo *D, NodeInfo *U) {
290 // Get current groups
291 NodeGroup *DGroup = D->Group;
292 NodeGroup *UGroup = U->Group;
293 // If both are members of groups
294 if (DGroup && UGroup) {
295 // There may have been another edge connecting
296 if (DGroup == UGroup) return;
297 // Add the pending users count
298 DGroup->addPending(UGroup->getPending());
299 // For each member of the users group
300 NodeGroupIterator UNGI(U);
301 while (NodeInfo *UNI = UNGI.next() ) {
304 // For each member of the definers group
305 NodeGroupIterator DNGI(D);
306 while (NodeInfo *DNI = DNGI.next() ) {
307 // Remove internal edges
308 DGroup->addPending(-CountInternalUses(DNI, UNI));
311 // Merge the two lists
312 DGroup->group_insert(DGroup->group_end(),
313 UGroup->group_begin(), UGroup->group_end());
315 // Make user member of definers group
317 // Add users uses to definers group pending
318 DGroup->addPending(U->Node->use_size());
319 // For each member of the definers group
320 NodeGroupIterator DNGI(D);
321 while (NodeInfo *DNI = DNGI.next() ) {
322 // Remove internal edges
323 DGroup->addPending(-CountInternalUses(DNI, U));
325 DGroup->group_push_back(U);
327 // Make definer member of users group
329 // Add definers uses to users group pending
330 UGroup->addPending(D->Node->use_size());
331 // For each member of the users group
332 NodeGroupIterator UNGI(U);
333 while (NodeInfo *UNI = UNGI.next() ) {
334 // Remove internal edges
335 UGroup->addPending(-CountInternalUses(D, UNI));
337 UGroup->group_insert(UGroup->group_begin(), D);
339 D->Group = U->Group = DGroup = new NodeGroup();
340 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
341 CountInternalUses(D, U));
342 DGroup->group_push_back(D);
343 DGroup->group_push_back(U);
347 /// CountInternalUses - Returns the number of edges between the two nodes.
349 unsigned NodeGroup::CountInternalUses(NodeInfo *D, NodeInfo *U) {
351 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
352 SDOperand Op = U->Node->getOperand(M);
353 if (Op.Val == D->Node) N++;
358 //===----------------------------------------------------------------------===//
361 //===----------------------------------------------------------------------===//
362 /// isFlagDefiner - Returns true if the node defines a flag result.
363 bool ScheduleDAGSimple::isFlagDefiner(SDNode *A) {
364 unsigned N = A->getNumValues();
365 return N && A->getValueType(N - 1) == MVT::Flag;
368 /// isFlagUser - Returns true if the node uses a flag result.
370 bool ScheduleDAGSimple::isFlagUser(SDNode *A) {
371 unsigned N = A->getNumOperands();
372 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
375 /// isDefiner - Return true if node A is a definer for B.
377 bool ScheduleDAGSimple::isDefiner(NodeInfo *A, NodeInfo *B) {
378 // While there are A nodes
379 NodeGroupIterator NII(A);
380 while (NodeInfo *NI = NII.next()) {
382 SDNode *Node = NI->Node;
383 // While there operands in nodes of B
384 NodeGroupOpIterator NGOI(B);
385 while (!NGOI.isEnd()) {
386 SDOperand Op = NGOI.next();
387 // If node from A defines a node in B
388 if (Node == Op.Val) return true;
394 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
396 bool ScheduleDAGSimple::isPassiveNode(SDNode *Node) {
397 if (isa<ConstantSDNode>(Node)) return true;
398 if (isa<RegisterSDNode>(Node)) return true;
399 if (isa<GlobalAddressSDNode>(Node)) return true;
400 if (isa<BasicBlockSDNode>(Node)) return true;
401 if (isa<FrameIndexSDNode>(Node)) return true;
402 if (isa<ConstantPoolSDNode>(Node)) return true;
403 if (isa<ExternalSymbolSDNode>(Node)) return true;
407 /// IncludeNode - Add node to NodeInfo vector.
409 void ScheduleDAGSimple::IncludeNode(NodeInfo *NI) {
411 SDNode *Node = NI->Node;
413 if (Node->getOpcode() == ISD::EntryToken) return;
414 // Check current count for node
415 int Count = NI->getPending();
416 // If the node is already in list
417 if (Count < 0) return;
418 // Decrement count to indicate a visit
420 // If count has gone to zero then add node to list
423 if (NI->isInGroup()) {
424 Ordering.push_back(NI->Group->getDominator());
426 Ordering.push_back(NI);
428 // indicate node has been added
431 // Mark as visited with new count
432 NI->setPending(Count);
435 /// VisitAll - Visit each node breadth-wise to produce an initial ordering.
436 /// Note that the ordering in the Nodes vector is reversed.
437 void ScheduleDAGSimple::VisitAll() {
438 // Add first element to list
439 NodeInfo *NI = getNI(DAG.getRoot().Val);
440 if (NI->isInGroup()) {
441 Ordering.push_back(NI->Group->getDominator());
443 Ordering.push_back(NI);
446 // Iterate through all nodes that have been added
447 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
448 // Visit all operands
449 NodeGroupOpIterator NGI(Ordering[i]);
450 while (!NGI.isEnd()) {
452 SDOperand Op = NGI.next();
454 SDNode *Node = Op.Val;
455 // Ignore passive nodes
456 if (isPassiveNode(Node)) continue;
458 IncludeNode(getNI(Node));
462 // Add entry node last (IncludeNode filters entry nodes)
463 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
464 Ordering.push_back(getNI(DAG.getEntryNode().Val));
467 std::reverse(Ordering.begin(), Ordering.end());
470 /// IdentifyGroups - Put flagged nodes into groups.
472 void ScheduleDAGSimple::IdentifyGroups() {
473 for (unsigned i = 0, N = NodeCount; i < N; i++) {
474 NodeInfo* NI = &Info[i];
475 SDNode *Node = NI->Node;
477 // For each operand (in reverse to only look at flags)
478 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
480 SDOperand Op = Node->getOperand(N);
481 // No more flags to walk
482 if (Op.getValueType() != MVT::Flag) break;
484 NodeGroup::Add(getNI(Op.Val), NI);
485 // Let evryone else know
491 /// GatherSchedulingInfo - Get latency and resource information about each node.
493 void ScheduleDAGSimple::GatherSchedulingInfo() {
494 // Get instruction itineraries for the target
495 const InstrItineraryData InstrItins = TM.getInstrItineraryData();
498 for (unsigned i = 0, N = NodeCount; i < N; i++) {
500 NodeInfo* NI = &Info[i];
501 SDNode *Node = NI->Node;
503 // If there are itineraries and it is a machine instruction
504 if (InstrItins.isEmpty() || ScheduleStyle == simpleNoItinScheduling) {
506 if (Node->isTargetOpcode()) {
507 // Get return type to guess which processing unit
508 MVT::ValueType VT = Node->getValueType(0);
509 // Get machine opcode
510 MachineOpCode TOpc = Node->getTargetOpcode();
511 NI->IsCall = TII->isCall(TOpc);
512 NI->IsLoad = TII->isLoad(TOpc);
513 NI->IsStore = TII->isStore(TOpc);
515 if (TII->isLoad(TOpc)) NI->StageBegin = &LoadStage;
516 else if (TII->isStore(TOpc)) NI->StageBegin = &StoreStage;
517 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
518 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
519 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
521 } else if (Node->isTargetOpcode()) {
522 // get machine opcode
523 MachineOpCode TOpc = Node->getTargetOpcode();
524 // Check to see if it is a call
525 NI->IsCall = TII->isCall(TOpc);
526 // Get itinerary stages for instruction
527 unsigned II = TII->getSchedClass(TOpc);
528 NI->StageBegin = InstrItins.begin(II);
529 NI->StageEnd = InstrItins.end(II);
532 // One slot for the instruction itself
535 // Add long latency for a call to push it back in time
536 if (NI->IsCall) NI->Latency += CallLatency;
538 // Sum up all the latencies
539 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
540 Stage != E; Stage++) {
541 NI->Latency += Stage->Cycles;
544 // Sum up all the latencies for max tally size
545 NSlots += NI->Latency;
548 // Unify metrics if in a group
550 for (unsigned i = 0, N = NodeCount; i < N; i++) {
551 NodeInfo* NI = &Info[i];
553 if (NI->isInGroup()) {
554 NodeGroup *Group = NI->Group;
556 if (!Group->getDominator()) {
557 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
558 NodeInfo *Dominator = *NGI;
559 unsigned Latency = 0;
561 for (NGI++; NGI != NGE; NGI++) {
562 NodeInfo* NGNI = *NGI;
563 Latency += NGNI->Latency;
564 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
567 Dominator->Latency = Latency;
568 Group->setDominator(Dominator);
575 /// FakeGroupDominators - Set dominators for non-scheduling.
577 void ScheduleDAGSimple::FakeGroupDominators() {
578 for (unsigned i = 0, N = NodeCount; i < N; i++) {
579 NodeInfo* NI = &Info[i];
581 if (NI->isInGroup()) {
582 NodeGroup *Group = NI->Group;
584 if (!Group->getDominator()) {
585 Group->setDominator(NI);
591 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
593 void ScheduleDAGSimple::PrepareNodeInfo() {
594 // Allocate node information
595 Info = new NodeInfo[NodeCount];
598 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
599 E = DAG.allnodes_end(); I != E; ++I, ++i) {
600 // Fast reference to node schedule info
601 NodeInfo* NI = &Info[i];
606 // Set pending visit count
607 NI->setPending(I->use_size());
611 /// isStrongDependency - Return true if node A has results used by node B.
612 /// I.E., B must wait for latency of A.
613 bool ScheduleDAGSimple::isStrongDependency(NodeInfo *A, NodeInfo *B) {
614 // If A defines for B then it's a strong dependency or
615 // if a load follows a store (may be dependent but why take a chance.)
616 return isDefiner(A, B) || (A->IsStore && B->IsLoad);
619 /// isWeakDependency Return true if node A produces a result that will
620 /// conflict with operands of B. It is assumed that we have called
621 /// isStrongDependency prior.
622 bool ScheduleDAGSimple::isWeakDependency(NodeInfo *A, NodeInfo *B) {
623 // TODO check for conflicting real registers and aliases
624 #if 0 // FIXME - Since we are in SSA form and not checking register aliasing
625 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
627 return A->Node->getOpcode() == ISD::EntryToken;
631 /// ScheduleBackward - Schedule instructions so that any long latency
632 /// instructions and the critical path get pushed back in time. Time is run in
633 /// reverse to allow code reuse of the Tally and eliminate the overhead of
634 /// biasing every slot indices against NSlots.
635 void ScheduleDAGSimple::ScheduleBackward() {
636 // Size and clear the resource tally
637 Tally.Initialize(NSlots);
638 // Get number of nodes to schedule
639 unsigned N = Ordering.size();
641 // For each node being scheduled
642 for (unsigned i = N; 0 < i--;) {
643 NodeInfo *NI = Ordering[i];
645 unsigned Slot = NotFound;
647 // Compare against those previously scheduled nodes
650 // Get following instruction
651 NodeInfo *Other = Ordering[j];
653 // Check dependency against previously inserted nodes
654 if (isStrongDependency(NI, Other)) {
655 Slot = Other->Slot + Other->Latency;
657 } else if (isWeakDependency(NI, Other)) {
663 // If independent of others (or first entry)
664 if (Slot == NotFound) Slot = 0;
666 #if 0 // FIXME - measure later
667 // Find a slot where the needed resources are available
668 if (NI->StageBegin != NI->StageEnd)
669 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
675 // Insert sort based on slot
678 // Get following instruction
679 NodeInfo *Other = Ordering[j];
680 // Should we look further (remember slots are in reverse time)
681 if (Slot >= Other->Slot) break;
682 // Shuffle other into ordering
683 Ordering[j - 1] = Other;
685 // Insert node in proper slot
686 if (j != i + 1) Ordering[j - 1] = NI;
690 /// ScheduleForward - Schedule instructions to maximize packing.
692 void ScheduleDAGSimple::ScheduleForward() {
693 // Size and clear the resource tally
694 Tally.Initialize(NSlots);
695 // Get number of nodes to schedule
696 unsigned N = Ordering.size();
698 // For each node being scheduled
699 for (unsigned i = 0; i < N; i++) {
700 NodeInfo *NI = Ordering[i];
702 unsigned Slot = NotFound;
704 // Compare against those previously scheduled nodes
707 // Get following instruction
708 NodeInfo *Other = Ordering[j];
710 // Check dependency against previously inserted nodes
711 if (isStrongDependency(Other, NI)) {
712 Slot = Other->Slot + Other->Latency;
714 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
720 // If independent of others (or first entry)
721 if (Slot == NotFound) Slot = 0;
723 // Find a slot where the needed resources are available
724 if (NI->StageBegin != NI->StageEnd)
725 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
730 // Insert sort based on slot
733 // Get prior instruction
734 NodeInfo *Other = Ordering[j];
735 // Should we look further
736 if (Slot >= Other->Slot) break;
737 // Shuffle other into ordering
738 Ordering[j + 1] = Other;
740 // Insert node in proper slot
741 if (j != i) Ordering[j + 1] = NI;
745 /// EmitAll - Emit all nodes in schedule sorted order.
747 void ScheduleDAGSimple::EmitAll() {
748 // For each node in the ordering
749 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
750 // Get the scheduling info
751 NodeInfo *NI = Ordering[i];
752 if (NI->isInGroup()) {
753 NodeGroupIterator NGI(Ordering[i]);
754 while (NodeInfo *NI = NGI.next()) EmitNode(NI);
761 /// Schedule - Order nodes according to selected style.
763 void ScheduleDAGSimple::Schedule() {
765 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
766 // Test to see if scheduling should occur
767 bool ShouldSchedule = NodeCount > 3 && ScheduleStyle != noScheduling;
768 // Set up minimum info for scheduling
770 // Construct node groups for flagged nodes
773 // Don't waste time if is only entry and return
774 if (ShouldSchedule) {
775 // Get latency and resource requirements
776 GatherSchedulingInfo();
777 } else if (HasGroups) {
778 // Make sure all the groups have dominators
779 FakeGroupDominators();
782 // Breadth first walk of DAG
786 static unsigned Count = 0;
788 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
789 NodeInfo *NI = Ordering[i];
794 // Don't waste time if is only entry and return
795 if (ShouldSchedule) {
796 // Push back long instructions and critical path
799 // Pack instructions to maximize resource utilization
803 DEBUG(printChanges(Count));
805 // Emit in scheduled order
809 /// printChanges - Hilight changes in order caused by scheduling.
811 void ScheduleDAGSimple::printChanges(unsigned Index) {
813 // Get the ordered node count
814 unsigned N = Ordering.size();
815 // Determine if any changes
818 NodeInfo *NI = Ordering[i];
819 if (NI->Preorder != i) break;
823 std::cerr << Index << ". New Ordering\n";
825 for (i = 0; i < N; i++) {
826 NodeInfo *NI = Ordering[i];
827 std::cerr << " " << NI->Preorder << ". ";
828 printSI(std::cerr, NI);
830 if (NI->isGroupDominator()) {
831 NodeGroup *Group = NI->Group;
832 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
835 printSI(std::cerr, *NII);
841 std::cerr << Index << ". No Changes\n";
846 /// printSI - Print schedule info.
848 void ScheduleDAGSimple::printSI(std::ostream &O, NodeInfo *NI) const {
850 SDNode *Node = NI->Node;
852 << std::hex << Node << std::dec
853 << ", Lat=" << NI->Latency
854 << ", Slot=" << NI->Slot
855 << ", ARITY=(" << Node->getNumOperands() << ","
856 << Node->getNumValues() << ")"
857 << " " << Node->getOperationName(&DAG);
858 if (isFlagDefiner(Node)) O << "<#";
859 if (isFlagUser(Node)) O << ">#";
863 /// print - Print ordering to specified output stream.
865 void ScheduleDAGSimple::print(std::ostream &O) const {
869 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
870 NodeInfo *NI = Ordering[i];
873 if (NI->isGroupDominator()) {
874 NodeGroup *Group = NI->Group;
875 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
886 /// createSimpleDAGScheduler - This creates a simple two pass instruction
888 llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAG &DAG,
889 MachineBasicBlock *BB) {
890 return new ScheduleDAGSimple(DAG, BB, DAG.getTarget());