1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGSDNodes class, which implements
11 // scheduling for an SDNode-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGSDNODES_H
16 #define SCHEDULEDAGSDNODES_H
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
22 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
24 /// Edges between SUnits are initially based on edges in the SelectionDAG,
25 /// and additional edges can be added by the schedulers as heuristics.
26 /// SDNodes such as Constants, Registers, and a few others that are not
27 /// interesting to schedulers are not allocated SUnits.
29 /// SDNodes with MVT::Glue operands are grouped along with the flagged
30 /// nodes into a single SUnit so that they are scheduled together.
32 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
33 /// edges. Physical register dependence information is not carried in
34 /// the DAG and must be handled explicitly by schedulers.
36 class ScheduleDAGSDNodes : public ScheduleDAG {
38 MachineBasicBlock *BB;
39 SelectionDAG *DAG; // DAG of the current basic block
40 const InstrItineraryData *InstrItins;
42 /// The schedule. Null SUnit*'s represent noop instructions.
43 std::vector<SUnit*> Sequence;
45 explicit ScheduleDAGSDNodes(MachineFunction &mf);
47 virtual ~ScheduleDAGSDNodes() {}
49 /// Run - perform scheduling.
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
53 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
55 static bool isPassiveNode(SDNode *Node) {
56 if (isa<ConstantSDNode>(Node)) return true;
57 if (isa<ConstantFPSDNode>(Node)) return true;
58 if (isa<RegisterSDNode>(Node)) return true;
59 if (isa<RegisterMaskSDNode>(Node)) return true;
60 if (isa<GlobalAddressSDNode>(Node)) return true;
61 if (isa<BasicBlockSDNode>(Node)) return true;
62 if (isa<FrameIndexSDNode>(Node)) return true;
63 if (isa<ConstantPoolSDNode>(Node)) return true;
64 if (isa<JumpTableSDNode>(Node)) return true;
65 if (isa<ExternalSymbolSDNode>(Node)) return true;
66 if (isa<BlockAddressSDNode>(Node)) return true;
67 if (Node->getOpcode() == ISD::EntryToken ||
68 isa<MDNodeSDNode>(Node)) return true;
72 /// NewSUnit - Creates a new SUnit and return a ptr to it.
74 SUnit *NewSUnit(SDNode *N);
76 /// Clone - Creates a clone of the specified SUnit. It does not copy the
77 /// predecessors / successors info nor the temporary scheduling states.
79 SUnit *Clone(SUnit *N);
81 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
82 /// are input. This SUnit graph is similar to the SelectionDAG, but
83 /// excludes nodes that aren't interesting to scheduling, and represents
84 /// flagged together nodes with a single SUnit.
85 void BuildSchedGraph(AliasAnalysis *AA);
87 /// InitVRegCycleFlag - Set isVRegCycle if this node's single use is
88 /// CopyToReg and its only active data operands are CopyFromReg within a
89 /// single block loop.
91 void InitVRegCycleFlag(SUnit *SU);
93 /// InitNumRegDefsLeft - Determine the # of regs defined by this node.
95 void InitNumRegDefsLeft(SUnit *SU);
97 /// ComputeLatency - Compute node latency.
99 virtual void ComputeLatency(SUnit *SU);
101 /// ComputeOperandLatency - Override dependence edge latency using
102 /// operand use/def information
104 virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
107 virtual void ComputeOperandLatency(SDNode *Def, SDNode *Use,
108 unsigned OpIdx, SDep& dep) const;
110 /// Schedule - Order nodes according to selected style, filling
111 /// in the Sequence member.
113 virtual void Schedule() = 0;
115 /// VerifyScheduledSequence - Verify that all SUnits are scheduled and
116 /// consistent with the Sequence of scheduled instructions.
117 void VerifyScheduledSequence(bool isBottomUp);
119 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
120 /// according to the order specified in Sequence.
122 MachineBasicBlock *EmitSchedule(MachineBasicBlock::iterator &InsertPos);
124 virtual void dumpNode(const SUnit *SU) const;
126 void dumpSchedule() const;
128 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
130 virtual std::string getDAGName() const;
132 virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
134 /// RegDefIter - In place iteration over the values defined by an
135 /// SUnit. This does not need copies of the iterator or any other STLisms.
136 /// The iterator creates itself, rather than being provided by the SchedDAG.
138 const ScheduleDAGSDNodes *SchedDAG;
141 unsigned NodeNumDefs;
144 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
146 bool IsValid() const { return Node != NULL; }
148 EVT GetValue() const {
149 assert(IsValid() && "bad iterator");
153 const SDNode *GetNode() const {
157 unsigned GetIdx() const {
163 void InitNodeNumDefs();
167 /// ClusterNeighboringLoads - Cluster loads from "near" addresses into
169 void ClusterNeighboringLoads(SDNode *Node);
170 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
174 /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
175 void BuildSchedUnits();
176 void AddSchedEdges();
178 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
179 MachineBasicBlock::iterator InsertPos);