1 //===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down list schedulers, using standard
11 // algorithms. The basic approach uses a priority queue of available nodes to
12 // schedule. One at a time, nodes are taken from the priority queue (thus in
13 // priority order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "sched"
22 #include "llvm/CodeGen/ScheduleDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/MRegisterInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
38 cl::opt<bool> SchedVertically("sched-vertically", cl::Hidden);
39 cl::opt<bool> SchedLowerDefNUse("sched-lower-defnuse", cl::Hidden);
43 Statistic<> NumNoops ("scheduler", "Number of noops inserted");
44 Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
46 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
47 /// a group of nodes flagged together.
49 SDNode *Node; // Representative node.
50 std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
52 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
53 // is true if the edge is a token chain edge, false if it is a value edge.
54 std::set<std::pair<SUnit*,bool> > Preds; // All sunit predecessors.
55 std::set<std::pair<SUnit*,bool> > Succs; // All sunit successors.
57 short NumPredsLeft; // # of preds not scheduled.
58 short NumSuccsLeft; // # of succs not scheduled.
59 short NumChainPredsLeft; // # of chain preds not scheduled.
60 short NumChainSuccsLeft; // # of chain succs not scheduled.
61 bool isTwoAddress : 1; // Is a two-address instruction.
62 bool isDefNUseOperand : 1; // Is a def&use operand.
63 bool isPending : 1; // True once pending.
64 bool isAvailable : 1; // True once available.
65 bool isScheduled : 1; // True once scheduled.
66 unsigned short Latency; // Node latency.
67 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
68 unsigned Cycle; // Once scheduled, the cycle of the op.
69 unsigned NodeNum; // Entry # of node in the node vector.
71 SUnit(SDNode *node, unsigned nodenum)
72 : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
73 NumChainPredsLeft(0), NumChainSuccsLeft(0),
74 isTwoAddress(false), isDefNUseOperand(false),
75 isPending(false), isAvailable(false), isScheduled(false),
76 Latency(0), CycleBound(0), Cycle(0), NodeNum(nodenum) {}
78 void dump(const SelectionDAG *G) const;
79 void dumpAll(const SelectionDAG *G) const;
83 void SUnit::dump(const SelectionDAG *G) const {
84 std::cerr << "SU(" << NodeNum << "): ";
87 if (FlaggedNodes.size() != 0) {
88 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
90 FlaggedNodes[i]->dump(G);
96 void SUnit::dumpAll(const SelectionDAG *G) const {
99 std::cerr << " # preds left : " << NumPredsLeft << "\n";
100 std::cerr << " # succs left : " << NumSuccsLeft << "\n";
101 std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
102 std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
103 std::cerr << " Latency : " << Latency << "\n";
105 if (Preds.size() != 0) {
106 std::cerr << " Predecessors:\n";
107 for (std::set<std::pair<SUnit*,bool> >::const_iterator I = Preds.begin(),
108 E = Preds.end(); I != E; ++I) {
112 std::cerr << " val ";
116 if (Succs.size() != 0) {
117 std::cerr << " Successors:\n";
118 for (std::set<std::pair<SUnit*, bool> >::const_iterator I = Succs.begin(),
119 E = Succs.end(); I != E; ++I) {
123 std::cerr << " val ";
130 //===----------------------------------------------------------------------===//
131 /// SchedulingPriorityQueue - This interface is used to plug different
132 /// priorities computation algorithms into the list scheduler. It implements the
133 /// interface of a standard priority queue, where nodes are inserted in
134 /// arbitrary order and returned in priority order. The computation of the
135 /// priority and the representation of the queue are totally up to the
136 /// implementation to decide.
139 class SchedulingPriorityQueue {
141 virtual ~SchedulingPriorityQueue() {}
143 virtual void initNodes(const std::vector<SUnit> &SUnits) = 0;
144 virtual void releaseState() = 0;
146 virtual bool empty() const = 0;
147 virtual void push(SUnit *U) = 0;
149 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0;
150 virtual SUnit *pop() = 0;
152 virtual void RemoveFromPriorityQueue(SUnit *SU) = 0;
154 /// ScheduledNode - As each node is scheduled, this method is invoked. This
155 /// allows the priority function to adjust the priority of node that have
156 /// already been emitted.
157 virtual void ScheduledNode(SUnit *Node) {}
164 //===----------------------------------------------------------------------===//
165 /// ScheduleDAGList - The actual list scheduler implementation. This supports
166 /// both top-down and bottom-up scheduling.
168 class ScheduleDAGList : public ScheduleDAG {
170 // SDNode to SUnit mapping (many to one).
171 std::map<SDNode*, SUnit*> SUnitMap;
173 // The schedule. Null SUnit*'s represent noop instructions.
174 std::vector<SUnit*> Sequence;
176 // The scheduling units.
177 std::vector<SUnit> SUnits;
179 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
183 /// AvailableQueue - The priority queue to use for the available SUnits.
185 SchedulingPriorityQueue *AvailableQueue;
187 /// PendingQueue - This contains all of the instructions whose operands have
188 /// been issued, but their results are not ready yet (due to the latency of
189 /// the operation). Once the operands becomes available, the instruction is
190 /// added to the AvailableQueue. This keeps track of each SUnit and the
191 /// number of cycles left to execute before the operation is available.
192 std::vector<std::pair<unsigned, SUnit*> > PendingQueue;
194 /// HazardRec - The hazard recognizer to use.
195 HazardRecognizer *HazardRec;
197 /// OpenNodes - Nodes with open live ranges, i.e. predecessors or successors
198 /// of scheduled nodes which are not themselves scheduled.
199 std::map<const TargetRegisterClass*, std::set<SUnit*> > OpenNodes;
201 /// RegPressureLimits - Keep track of upper limit of register pressure for
202 /// each register class that allows the scheduler to go into vertical mode.
203 std::map<const TargetRegisterClass*, unsigned> RegPressureLimits;
206 ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
207 const TargetMachine &tm, bool isbottomup,
208 SchedulingPriorityQueue *availqueue,
209 HazardRecognizer *HR)
210 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
211 AvailableQueue(availqueue), HazardRec(HR) {
216 delete AvailableQueue;
221 void dumpSchedule() const;
224 SUnit *NewSUnit(SDNode *N);
225 void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle);
226 void ReleaseSucc(SUnit *SuccSU, bool isChain);
227 void ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle, bool Veritical=true);
228 void ScheduleVertically(SUnit *SU, unsigned& CurCycle);
229 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
230 void ListScheduleTopDown();
231 void ListScheduleBottomUp();
232 void BuildSchedUnits();
235 } // end anonymous namespace
237 HazardRecognizer::~HazardRecognizer() {}
240 /// NewSUnit - Creates a new SUnit and return a ptr to it.
241 SUnit *ScheduleDAGList::NewSUnit(SDNode *N) {
242 SUnits.push_back(SUnit(N, SUnits.size()));
243 return &SUnits.back();
246 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
247 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
248 /// together nodes with a single SUnit.
249 void ScheduleDAGList::BuildSchedUnits() {
250 // Reserve entries in the vector for each of the SUnits we are creating. This
251 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
253 SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
255 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
257 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
258 E = DAG.allnodes_end(); NI != E; ++NI) {
259 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
262 // If this node has already been processed, stop now.
263 if (SUnitMap[NI]) continue;
265 SUnit *NodeSUnit = NewSUnit(NI);
267 // See if anything is flagged to this node, if so, add them to flagged
268 // nodes. Nodes can have at most one flag input and one flag output. Flags
269 // are required the be the last operand and result of a node.
271 // Scan up, adding flagged preds to FlaggedNodes.
273 while (N->getNumOperands() &&
274 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
275 N = N->getOperand(N->getNumOperands()-1).Val;
276 NodeSUnit->FlaggedNodes.push_back(N);
277 SUnitMap[N] = NodeSUnit;
280 // Scan down, adding this node and any flagged succs to FlaggedNodes if they
281 // have a user of the flag operand.
283 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
284 SDOperand FlagVal(N, N->getNumValues()-1);
286 // There are either zero or one users of the Flag result.
287 bool HasFlagUse = false;
288 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
290 if (FlagVal.isOperand(*UI)) {
292 NodeSUnit->FlaggedNodes.push_back(N);
293 SUnitMap[N] = NodeSUnit;
297 if (!HasFlagUse) break;
300 // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
303 SUnitMap[N] = NodeSUnit;
305 // Compute the latency for the node. We use the sum of the latencies for
306 // all nodes flagged together into this SUnit.
307 if (InstrItins.isEmpty()) {
308 // No latency information.
309 NodeSUnit->Latency = 1;
311 NodeSUnit->Latency = 0;
312 if (N->isTargetOpcode()) {
313 unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
314 InstrStage *S = InstrItins.begin(SchedClass);
315 InstrStage *E = InstrItins.end(SchedClass);
317 NodeSUnit->Latency += S->Cycles;
319 for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
320 SDNode *FNode = NodeSUnit->FlaggedNodes[i];
321 if (FNode->isTargetOpcode()) {
322 unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
323 InstrStage *S = InstrItins.begin(SchedClass);
324 InstrStage *E = InstrItins.end(SchedClass);
326 NodeSUnit->Latency += S->Cycles;
332 // Pass 2: add the preds, succs, etc.
333 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
334 SUnit *SU = &SUnits[su];
335 SDNode *MainNode = SU->Node;
337 if (MainNode->isTargetOpcode()) {
338 unsigned Opc = MainNode->getTargetOpcode();
339 if (TII->isTwoAddrInstr(Opc)) {
340 SU->isTwoAddress = true;
341 SDNode *OpN = MainNode->getOperand(0).Val;
342 SUnit *OpSU = SUnitMap[OpN];
344 OpSU->isDefNUseOperand = true;
348 // Find all predecessors and successors of the group.
349 // Temporarily add N to make code simpler.
350 SU->FlaggedNodes.push_back(MainNode);
352 for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
353 SDNode *N = SU->FlaggedNodes[n];
355 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
356 SDNode *OpN = N->getOperand(i).Val;
357 if (isPassiveNode(OpN)) continue; // Not scheduled.
358 SUnit *OpSU = SUnitMap[OpN];
359 assert(OpSU && "Node has no SUnit!");
360 if (OpSU == SU) continue; // In the same group.
362 MVT::ValueType OpVT = N->getOperand(i).getValueType();
363 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
364 bool isChain = OpVT == MVT::Other;
366 if (SU->Preds.insert(std::make_pair(OpSU, isChain)).second) {
370 SU->NumChainPredsLeft++;
373 if (OpSU->Succs.insert(std::make_pair(SU, isChain)).second) {
375 OpSU->NumSuccsLeft++;
377 OpSU->NumChainSuccsLeft++;
383 // Remove MainNode from FlaggedNodes again.
384 SU->FlaggedNodes.pop_back();
387 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
388 SUnits[su].dumpAll(&DAG));
392 /// EmitSchedule - Emit the machine code in scheduled order.
393 void ScheduleDAGList::EmitSchedule() {
394 std::map<SDNode*, unsigned> VRBaseMap;
395 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
396 if (SUnit *SU = Sequence[i]) {
397 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
398 EmitNode(SU->FlaggedNodes[j], VRBaseMap);
399 EmitNode(SU->Node, VRBaseMap);
401 // Null SUnit* is a noop.
407 /// dump - dump the schedule.
408 void ScheduleDAGList::dumpSchedule() const {
409 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
410 if (SUnit *SU = Sequence[i])
413 std::cerr << "**** NOOP ****\n";
417 /// Schedule - Schedule the DAG using list scheduling.
418 void ScheduleDAGList::Schedule() {
419 DEBUG(std::cerr << "********** List Scheduling **********\n");
421 // Build scheduling units.
424 AvailableQueue->initNodes(SUnits);
426 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
428 ListScheduleBottomUp();
430 ListScheduleTopDown();
432 AvailableQueue->releaseState();
434 DEBUG(std::cerr << "*** Final schedule ***\n");
435 DEBUG(dumpSchedule());
436 DEBUG(std::cerr << "\n");
438 // Emit in scheduled order
442 //===----------------------------------------------------------------------===//
443 // Bottom-Up Scheduling
444 //===----------------------------------------------------------------------===//
446 static const TargetRegisterClass *getRegClass(SUnit *SU,
447 const TargetInstrInfo *TII,
448 const MRegisterInfo *MRI,
450 if (SU->Node->isTargetOpcode()) {
451 unsigned Opc = SU->Node->getTargetOpcode();
452 const TargetInstrDescriptor &II = TII->get(Opc);
453 return II.OpInfo->RegClass;
455 assert(SU->Node->getOpcode() == ISD::CopyFromReg);
456 unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
457 if (MRegisterInfo::isVirtualRegister(SrcReg))
458 return RegMap->getRegClass(SrcReg);
460 for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
461 E = MRI->regclass_end(); I != E; ++I)
462 if ((*I)->hasType(SU->Node->getValueType(0)) &&
463 (*I)->contains(SrcReg))
465 assert(false && "Couldn't find register class for reg copy!");
471 static unsigned getNumResults(SUnit *SU) {
472 unsigned NumResults = 0;
473 for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
474 MVT::ValueType VT = SU->Node->getValueType(i);
475 if (VT != MVT::Other && VT != MVT::Flag)
481 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
482 /// the Available queue is the count reaches zero. Also update its cycle bound.
483 void ScheduleDAGList::ReleasePred(SUnit *PredSU, bool isChain,
485 // FIXME: the distance between two nodes is not always == the predecessor's
486 // latency. For example, the reader can very well read the register written
487 // by the predecessor later than the issue cycle. It also depends on the
488 // interrupt model (drain vs. freeze).
489 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
492 PredSU->NumSuccsLeft--;
494 PredSU->NumChainSuccsLeft--;
497 if (PredSU->NumSuccsLeft < 0 || PredSU->NumChainSuccsLeft < 0) {
498 std::cerr << "*** List scheduling failed! ***\n";
500 std::cerr << " has been released too many times!\n";
505 if ((PredSU->NumSuccsLeft + PredSU->NumChainSuccsLeft) == 0) {
506 // EntryToken has to go last! Special case it here.
507 if (PredSU->Node->getOpcode() != ISD::EntryToken) {
508 PredSU->isAvailable = true;
509 AvailableQueue->push(PredSU);
513 if (getNumResults(PredSU) > 0) {
514 const TargetRegisterClass *RegClass = getRegClass(PredSU, TII, MRI, RegMap);
515 OpenNodes[RegClass].insert(PredSU);
519 /// SharesOperandWithTwoAddr - Check if there is a unscheduled two-address node
520 /// with which SU shares an operand. If so, returns the node.
521 static SUnit *SharesOperandWithTwoAddr(SUnit *SU) {
522 assert(!SU->isTwoAddress && "Node cannot be two-address op");
523 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
524 E = SU->Preds.end(); I != E; ++I) {
525 if (I->second) continue;
526 SUnit *PredSU = I->first;
527 for (std::set<std::pair<SUnit*, bool> >::iterator II =
528 PredSU->Succs.begin(), EE = PredSU->Succs.end(); II != EE; ++II) {
529 if (II->second) continue;
530 SUnit *SSU = II->first;
531 if (SSU->isTwoAddress && !SSU->isScheduled) {
539 static bool isFloater(const SUnit *SU) {
540 unsigned Opc = SU->Node->getOpcode();
541 return (Opc != ISD::CopyFromReg && SU->NumPredsLeft == 0);
544 static bool isSimpleFloaterUse(const SUnit *SU) {
546 for (std::set<std::pair<SUnit*, bool> >::const_iterator I = SU->Preds.begin(),
547 E = SU->Preds.end(); I != E; ++I) {
548 if (I->second) continue;
551 if (!isFloater(I->first))
557 /// ScheduleVertically - Schedule vertically. That is, follow up the D&U chain
558 /// (of two-address code) and schedule floaters aggressively.
559 void ScheduleDAGList::ScheduleVertically(SUnit *SU, unsigned& CurCycle) {
560 // Try scheduling Def&Use operand if register pressure is low.
561 const TargetRegisterClass *RegClass = getRegClass(SU, TII, MRI, RegMap);
562 unsigned Pressure = OpenNodes[RegClass].size();
563 unsigned Limit = RegPressureLimits[RegClass];
565 // See if we can schedule any predecessor that takes no registers.
566 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
567 E = SU->Preds.end(); I != E; ++I) {
568 if (I->second) continue;
570 SUnit *PredSU = I->first;
571 if (!PredSU->isAvailable || PredSU->isScheduled)
574 if (isFloater(PredSU)) {
575 DEBUG(std::cerr<<"*** Scheduling floater\n");
576 AvailableQueue->RemoveFromPriorityQueue(PredSU);
577 ScheduleNodeBottomUp(PredSU, CurCycle, false);
582 if (SU->isTwoAddress && Pressure < Limit) {
583 DUSU = SUnitMap[SU->Node->getOperand(0).Val];
584 if (!DUSU->isAvailable || DUSU->isScheduled)
586 else if (!DUSU->isTwoAddress) {
587 SUnit *SSU = SharesOperandWithTwoAddr(DUSU);
588 if (SSU && SSU->isAvailable) {
589 AvailableQueue->RemoveFromPriorityQueue(SSU);
590 ScheduleNodeBottomUp(SSU, CurCycle, false);
591 Pressure = OpenNodes[RegClass].size();
592 if (Pressure >= Limit)
599 DEBUG(std::cerr<<"*** Low register pressure: scheduling D&U operand\n");
600 AvailableQueue->RemoveFromPriorityQueue(DUSU);
601 ScheduleNodeBottomUp(DUSU, CurCycle, false);
602 Pressure = OpenNodes[RegClass].size();
603 ScheduleVertically(DUSU, CurCycle);
607 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
608 /// count of its predecessors. If a predecessor pending count is zero, add it to
609 /// the Available queue.
610 void ScheduleDAGList::ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle,
612 DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
613 DEBUG(SU->dump(&DAG));
614 SU->Cycle = CurCycle;
616 AvailableQueue->ScheduledNode(SU);
617 Sequence.push_back(SU);
619 // Bottom up: release predecessors
620 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
621 E = SU->Preds.end(); I != E; ++I)
622 ReleasePred(I->first, I->second, CurCycle);
623 SU->isScheduled = true;
626 if (getNumResults(SU) != 0) {
627 const TargetRegisterClass *RegClass = getRegClass(SU, TII, MRI, RegMap);
628 OpenNodes[RegClass].erase(SU);
630 if (SchedVertically && Vertical)
631 ScheduleVertically(SU, CurCycle);
635 /// isReady - True if node's lower cycle bound is less or equal to the current
636 /// scheduling cycle. Always true if all nodes have uniform latency 1.
637 static inline bool isReady(SUnit *SU, unsigned CurCycle) {
638 return SU->CycleBound <= CurCycle;
641 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
643 void ScheduleDAGList::ListScheduleBottomUp() {
644 // Determine rough register pressure limit.
645 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
646 E = MRI->regclass_end(); RCI != E; ++RCI) {
647 const TargetRegisterClass *RC = *RCI;
648 unsigned Limit = RC->getNumRegs();
649 Limit = (Limit > 2) ? Limit - 2 : 0;
650 std::map<const TargetRegisterClass*, unsigned>::iterator RPI =
651 RegPressureLimits.find(RC);
652 if (RPI == RegPressureLimits.end())
653 RegPressureLimits[RC] = Limit;
655 unsigned &OldLimit = RegPressureLimits[RC];
656 if (Limit < OldLimit)
661 unsigned CurCycle = 0;
662 // Add root to Available queue.
663 AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
665 // While Available queue is not empty, grab the node with the highest
666 // priority. If it is not ready put it back. Schedule the node.
667 std::vector<SUnit*> NotReady;
668 SUnit *CurNode = NULL;
669 while (!AvailableQueue->empty()) {
670 SUnit *CurNode = AvailableQueue->pop();
671 while (!isReady(CurNode, CurCycle)) {
672 NotReady.push_back(CurNode);
673 CurNode = AvailableQueue->pop();
676 // Add the nodes that aren't ready back onto the available list.
677 AvailableQueue->push_all(NotReady);
680 ScheduleNodeBottomUp(CurNode, CurCycle);
683 // Add entry node last
684 if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
685 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
686 Sequence.push_back(Entry);
689 // Reverse the order if it is bottom up.
690 std::reverse(Sequence.begin(), Sequence.end());
694 // Verify that all SUnits were scheduled.
695 bool AnyNotSched = false;
696 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
697 if (SUnits[i].NumSuccsLeft != 0 || SUnits[i].NumChainSuccsLeft != 0) {
699 std::cerr << "*** List scheduling failed! ***\n";
700 SUnits[i].dump(&DAG);
701 std::cerr << "has not been scheduled!\n";
705 assert(!AnyNotSched);
709 //===----------------------------------------------------------------------===//
710 // Top-Down Scheduling
711 //===----------------------------------------------------------------------===//
713 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
714 /// the PendingQueue if the count reaches zero.
715 void ScheduleDAGList::ReleaseSucc(SUnit *SuccSU, bool isChain) {
717 SuccSU->NumPredsLeft--;
719 SuccSU->NumChainPredsLeft--;
721 assert(SuccSU->NumPredsLeft >= 0 && SuccSU->NumChainPredsLeft >= 0 &&
722 "List scheduling internal error");
724 if ((SuccSU->NumPredsLeft + SuccSU->NumChainPredsLeft) == 0) {
725 // Compute how many cycles it will be before this actually becomes
726 // available. This is the max of the start time of all predecessors plus
728 unsigned AvailableCycle = 0;
729 for (std::set<std::pair<SUnit*, bool> >::iterator I = SuccSU->Preds.begin(),
730 E = SuccSU->Preds.end(); I != E; ++I) {
731 // If this is a token edge, we don't need to wait for the latency of the
732 // preceeding instruction (e.g. a long-latency load) unless there is also
733 // some other data dependence.
734 unsigned PredDoneCycle = I->first->Cycle;
736 PredDoneCycle += I->first->Latency;
737 else if (I->first->Latency)
740 AvailableCycle = std::max(AvailableCycle, PredDoneCycle);
743 PendingQueue.push_back(std::make_pair(AvailableCycle, SuccSU));
747 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
748 /// count of its successors. If a successor pending count is zero, add it to
749 /// the Available queue.
750 void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
751 DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
752 DEBUG(SU->dump(&DAG));
754 Sequence.push_back(SU);
755 SU->Cycle = CurCycle;
757 // Bottom up: release successors.
758 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Succs.begin(),
759 E = SU->Succs.end(); I != E; ++I)
760 ReleaseSucc(I->first, I->second);
763 /// ListScheduleTopDown - The main loop of list scheduling for top-down
765 void ScheduleDAGList::ListScheduleTopDown() {
766 unsigned CurCycle = 0;
767 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
769 // All leaves to Available queue.
770 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
771 // It is available if it has no predecessors.
772 if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
773 AvailableQueue->push(&SUnits[i]);
774 SUnits[i].isAvailable = SUnits[i].isPending = true;
778 // Emit the entry node first.
779 ScheduleNodeTopDown(Entry, CurCycle);
780 HazardRec->EmitInstruction(Entry->Node);
782 // While Available queue is not empty, grab the node with the highest
783 // priority. If it is not ready put it back. Schedule the node.
784 std::vector<SUnit*> NotReady;
785 while (!AvailableQueue->empty() || !PendingQueue.empty()) {
786 // Check to see if any of the pending instructions are ready to issue. If
787 // so, add them to the available queue.
788 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
789 if (PendingQueue[i].first == CurCycle) {
790 AvailableQueue->push(PendingQueue[i].second);
791 PendingQueue[i].second->isAvailable = true;
792 PendingQueue[i] = PendingQueue.back();
793 PendingQueue.pop_back();
796 assert(PendingQueue[i].first > CurCycle && "Negative latency?");
800 // If there are no instructions available, don't try to issue anything, and
801 // don't advance the hazard recognizer.
802 if (AvailableQueue->empty()) {
807 SUnit *FoundSUnit = 0;
808 SDNode *FoundNode = 0;
810 bool HasNoopHazards = false;
811 while (!AvailableQueue->empty()) {
812 SUnit *CurSUnit = AvailableQueue->pop();
814 // Get the node represented by this SUnit.
815 FoundNode = CurSUnit->Node;
817 // If this is a pseudo op, like copyfromreg, look to see if there is a
818 // real target node flagged to it. If so, use the target node.
819 for (unsigned i = 0, e = CurSUnit->FlaggedNodes.size();
820 FoundNode->getOpcode() < ISD::BUILTIN_OP_END && i != e; ++i)
821 FoundNode = CurSUnit->FlaggedNodes[i];
823 HazardRecognizer::HazardType HT = HazardRec->getHazardType(FoundNode);
824 if (HT == HazardRecognizer::NoHazard) {
825 FoundSUnit = CurSUnit;
829 // Remember if this is a noop hazard.
830 HasNoopHazards |= HT == HazardRecognizer::NoopHazard;
832 NotReady.push_back(CurSUnit);
835 // Add the nodes that aren't ready back onto the available list.
836 if (!NotReady.empty()) {
837 AvailableQueue->push_all(NotReady);
841 // If we found a node to schedule, do it now.
843 ScheduleNodeTopDown(FoundSUnit, CurCycle);
844 HazardRec->EmitInstruction(FoundNode);
845 FoundSUnit->isScheduled = true;
846 AvailableQueue->ScheduledNode(FoundSUnit);
848 // If this is a pseudo-op node, we don't want to increment the current
850 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
852 } else if (!HasNoopHazards) {
853 // Otherwise, we have a pipeline stall, but no other problem, just advance
854 // the current cycle and try again.
855 DEBUG(std::cerr << "*** Advancing cycle, no work to do\n");
856 HazardRec->AdvanceCycle();
860 // Otherwise, we have no instructions to issue and we have instructions
861 // that will fault if we don't do this right. This is the case for
862 // processors without pipeline interlocks and other cases.
863 DEBUG(std::cerr << "*** Emitting noop\n");
864 HazardRec->EmitNoop();
865 Sequence.push_back(0); // NULL SUnit* -> noop
872 // Verify that all SUnits were scheduled.
873 bool AnyNotSched = false;
874 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
875 if (SUnits[i].NumPredsLeft != 0 || SUnits[i].NumChainPredsLeft != 0) {
877 std::cerr << "*** List scheduling failed! ***\n";
878 SUnits[i].dump(&DAG);
879 std::cerr << "has not been scheduled!\n";
883 assert(!AnyNotSched);
887 //===----------------------------------------------------------------------===//
888 // RegReductionPriorityQueue Implementation
889 //===----------------------------------------------------------------------===//
891 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
892 // to reduce register pressure.
896 class RegReductionPriorityQueue;
898 /// Sorting functions for the Available queue.
899 struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
900 RegReductionPriorityQueue<ls_rr_sort> *SPQ;
901 ls_rr_sort(RegReductionPriorityQueue<ls_rr_sort> *spq) : SPQ(spq) {}
902 ls_rr_sort(const ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
904 bool operator()(const SUnit* left, const SUnit* right) const;
906 } // end anonymous namespace
910 class RegReductionPriorityQueue : public SchedulingPriorityQueue {
911 // SUnits - The SUnits for the current graph.
912 const std::vector<SUnit> *SUnits;
914 // SethiUllmanNumbers - The SethiUllman number for each node.
915 std::vector<int> SethiUllmanNumbers;
917 std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
919 RegReductionPriorityQueue() :
920 Queue(ls_rr_sort(this)) {}
922 void initNodes(const std::vector<SUnit> &sunits) {
924 // Add pseudo dependency edges for two-address nodes.
925 if (SchedLowerDefNUse)
926 AddPseudoTwoAddrDeps();
927 // Calculate node priorities.
928 CalculatePriorities();
930 void releaseState() {
932 SethiUllmanNumbers.clear();
935 int getSethiUllmanNumber(unsigned NodeNum) const {
936 assert(NodeNum < SethiUllmanNumbers.size());
937 return SethiUllmanNumbers[NodeNum];
940 bool empty() const { return Queue.empty(); }
942 void push(SUnit *U) {
945 void push_all(const std::vector<SUnit *> &Nodes) {
946 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
947 Queue.push(Nodes[i]);
951 SUnit *V = Queue.top();
956 /// RemoveFromPriorityQueue - This is a really inefficient way to remove a
957 /// node from a priority queue. We should roll our own heap to make this
958 /// better or something.
959 void RemoveFromPriorityQueue(SUnit *SU) {
960 std::vector<SUnit*> Temp;
962 assert(!Queue.empty() && "Not in queue!");
963 while (Queue.top() != SU) {
964 Temp.push_back(Queue.top());
966 assert(!Queue.empty() && "Not in queue!");
969 // Remove the node from the PQ.
972 // Add all the other nodes back.
973 for (unsigned i = 0, e = Temp.size(); i != e; ++i)
978 void AddPseudoTwoAddrDeps();
979 void CalculatePriorities();
980 int CalcNodePriority(const SUnit *SU);
984 bool ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
985 unsigned LeftNum = left->NodeNum;
986 unsigned RightNum = right->NodeNum;
987 bool LIsTarget = left->Node->isTargetOpcode();
988 bool RIsTarget = right->Node->isTargetOpcode();
989 int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
990 int RPriority = SPQ->getSethiUllmanNumber(RightNum);
991 bool LIsFloater = LIsTarget && (LPriority == 1 || LPriority == 0);
992 bool RIsFloater = RIsTarget && (RPriority == 1 || RPriority == 0);
996 // Schedule floaters (e.g. load from some constant address) and those nodes
997 // with a single predecessor each first. They maintain / reduce register
1004 if (!SchedLowerDefNUse) {
1005 // Special tie breaker: if two nodes share a operand, the one that use it
1006 // as a def&use operand is preferred.
1007 if (LIsTarget && RIsTarget) {
1008 if (left->isTwoAddress && !right->isTwoAddress) {
1009 SDNode *DUNode = left->Node->getOperand(0).Val;
1010 if (DUNode->isOperand(right->Node))
1013 if (!left->isTwoAddress && right->isTwoAddress) {
1014 SDNode *DUNode = right->Node->getOperand(0).Val;
1015 if (DUNode->isOperand(left->Node))
1021 if (LPriority+LBonus < RPriority+RBonus)
1023 else if (LPriority+LBonus == RPriority+RBonus)
1024 if (left->NumPredsLeft > right->NumPredsLeft)
1026 else if (left->NumPredsLeft+LBonus == right->NumPredsLeft+RBonus)
1027 if (left->CycleBound > right->CycleBound)
1032 static inline bool isCopyFromLiveIn(const SUnit *SU) {
1033 SDNode *N = SU->Node;
1034 return N->getOpcode() == ISD::CopyFromReg &&
1035 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
1038 // FIXME: This is probably too slow!
1039 static void isReachable(SUnit *SU, SUnit *TargetSU,
1040 std::set<SUnit *> &Visited, bool &Reached) {
1041 if (Reached) return;
1042 if (SU == TargetSU) {
1046 if (!Visited.insert(SU).second) return;
1048 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
1049 E = SU->Preds.end(); I != E; ++I)
1050 isReachable(I->first, TargetSU, Visited, Reached);
1053 static bool isReachable(SUnit *SU, SUnit *TargetSU) {
1054 std::set<SUnit *> Visited;
1055 bool Reached = false;
1056 isReachable(SU, TargetSU, Visited, Reached);
1060 static SUnit *getDefUsePredecessor(SUnit *SU) {
1061 SDNode *DU = SU->Node->getOperand(0).Val;
1062 for (std::set<std::pair<SUnit*, bool> >::iterator
1063 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
1064 if (I->second) continue; // ignore chain preds
1065 SUnit *PredSU = I->first;
1066 if (PredSU->Node == DU)
1074 static bool canClobber(SUnit *SU, SUnit *Op) {
1075 if (SU->isTwoAddress)
1076 return Op == getDefUsePredecessor(SU);
1080 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
1081 /// it as a def&use operand. Add a pseudo control edge from it to the other
1082 /// node (if it won't create a cycle) so the two-address one will be scheduled
1083 /// first (lower in the schedule).
1085 void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
1086 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
1087 SUnit *SU = (SUnit *)&((*SUnits)[i]);
1088 SDNode *Node = SU->Node;
1089 if (!Node->isTargetOpcode())
1092 if (SU->isTwoAddress) {
1093 unsigned Depth = SU->Node->getNodeDepth();
1094 SUnit *DUSU = getDefUsePredecessor(SU);
1095 if (!DUSU) continue;
1097 for (std::set<std::pair<SUnit*, bool> >::iterator I = DUSU->Succs.begin(),
1098 E = DUSU->Succs.end(); I != E; ++I) {
1099 SUnit *SuccSU = I->first;
1100 if (SuccSU != SU && !canClobber(SuccSU, DUSU)) {
1101 if (SuccSU->Node->getNodeDepth() <= Depth+2 &&
1102 !isReachable(SuccSU, SU)) {
1103 DEBUG(std::cerr << "Adding an edge from SU # " << SU->NodeNum
1104 << " to SU #" << SuccSU->NodeNum << "\n");
1105 if (SU->Preds.insert(std::make_pair(SuccSU, true)).second)
1106 SU->NumChainPredsLeft++;
1107 if (SuccSU->Succs.insert(std::make_pair(SU, true)).second)
1108 SuccSU->NumChainSuccsLeft++;
1116 /// CalcNodePriority - Priority is the Sethi Ullman number.
1117 /// Smaller number is the higher priority.
1119 int RegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
1120 int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1121 if (SethiUllmanNumber != 0)
1122 return SethiUllmanNumber;
1124 unsigned Opc = SU->Node->getOpcode();
1125 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1126 SethiUllmanNumber = INT_MAX - 10;
1127 else if (SU->NumSuccsLeft == 0)
1128 // If SU does not have a use, i.e. it doesn't produce a value that would
1129 // be consumed (e.g. store), then it terminates a chain of computation.
1130 // Give it a small SethiUllman number so it will be scheduled right before its
1131 // predecessors that it doesn't lengthen their live ranges.
1132 SethiUllmanNumber = INT_MIN + 10;
1133 else if (SU->NumPredsLeft == 0 &&
1134 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
1135 SethiUllmanNumber = 1;
1138 for (std::set<std::pair<SUnit*, bool> >::const_iterator
1139 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
1140 if (I->second) continue; // ignore chain preds
1141 SUnit *PredSU = I->first;
1142 int PredSethiUllman = CalcNodePriority(PredSU);
1143 if (PredSethiUllman > SethiUllmanNumber) {
1144 SethiUllmanNumber = PredSethiUllman;
1146 } else if (PredSethiUllman == SethiUllmanNumber && !I->second)
1150 SethiUllmanNumber += Extra;
1153 return SethiUllmanNumber;
1156 /// CalculatePriorities - Calculate priorities of all scheduling units.
1158 void RegReductionPriorityQueue<SF>::CalculatePriorities() {
1159 SethiUllmanNumbers.assign(SUnits->size(), 0);
1161 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1162 CalcNodePriority(&(*SUnits)[i]);
1165 //===----------------------------------------------------------------------===//
1166 // LatencyPriorityQueue Implementation
1167 //===----------------------------------------------------------------------===//
1169 // This is a SchedulingPriorityQueue that schedules using latency information to
1170 // reduce the length of the critical path through the basic block.
1173 class LatencyPriorityQueue;
1175 /// Sorting functions for the Available queue.
1176 struct latency_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1177 LatencyPriorityQueue *PQ;
1178 latency_sort(LatencyPriorityQueue *pq) : PQ(pq) {}
1179 latency_sort(const latency_sort &RHS) : PQ(RHS.PQ) {}
1181 bool operator()(const SUnit* left, const SUnit* right) const;
1183 } // end anonymous namespace
1186 class LatencyPriorityQueue : public SchedulingPriorityQueue {
1187 // SUnits - The SUnits for the current graph.
1188 const std::vector<SUnit> *SUnits;
1190 // Latencies - The latency (max of latency from this node to the bb exit)
1192 std::vector<int> Latencies;
1194 /// NumNodesSolelyBlocking - This vector contains, for every node in the
1195 /// Queue, the number of nodes that the node is the sole unscheduled
1196 /// predecessor for. This is used as a tie-breaker heuristic for better
1198 std::vector<unsigned> NumNodesSolelyBlocking;
1200 std::priority_queue<SUnit*, std::vector<SUnit*>, latency_sort> Queue;
1202 LatencyPriorityQueue() : Queue(latency_sort(this)) {
1205 void initNodes(const std::vector<SUnit> &sunits) {
1207 // Calculate node priorities.
1208 CalculatePriorities();
1210 void releaseState() {
1215 unsigned getLatency(unsigned NodeNum) const {
1216 assert(NodeNum < Latencies.size());
1217 return Latencies[NodeNum];
1220 unsigned getNumSolelyBlockNodes(unsigned NodeNum) const {
1221 assert(NodeNum < NumNodesSolelyBlocking.size());
1222 return NumNodesSolelyBlocking[NodeNum];
1225 bool empty() const { return Queue.empty(); }
1227 virtual void push(SUnit *U) {
1230 void push_impl(SUnit *U);
1232 void push_all(const std::vector<SUnit *> &Nodes) {
1233 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
1234 push_impl(Nodes[i]);
1238 SUnit *V = Queue.top();
1243 /// RemoveFromPriorityQueue - This is a really inefficient way to remove a
1244 /// node from a priority queue. We should roll our own heap to make this
1245 /// better or something.
1246 void RemoveFromPriorityQueue(SUnit *SU) {
1247 std::vector<SUnit*> Temp;
1249 assert(!Queue.empty() && "Not in queue!");
1250 while (Queue.top() != SU) {
1251 Temp.push_back(Queue.top());
1253 assert(!Queue.empty() && "Not in queue!");
1256 // Remove the node from the PQ.
1259 // Add all the other nodes back.
1260 for (unsigned i = 0, e = Temp.size(); i != e; ++i)
1261 Queue.push(Temp[i]);
1264 // ScheduledNode - As nodes are scheduled, we look to see if there are any
1265 // successor nodes that have a single unscheduled predecessor. If so, that
1266 // single predecessor has a higher priority, since scheduling it will make
1267 // the node available.
1268 void ScheduledNode(SUnit *Node);
1271 void CalculatePriorities();
1272 int CalcLatency(const SUnit &SU);
1273 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
1277 bool latency_sort::operator()(const SUnit *LHS, const SUnit *RHS) const {
1278 unsigned LHSNum = LHS->NodeNum;
1279 unsigned RHSNum = RHS->NodeNum;
1281 // The most important heuristic is scheduling the critical path.
1282 unsigned LHSLatency = PQ->getLatency(LHSNum);
1283 unsigned RHSLatency = PQ->getLatency(RHSNum);
1284 if (LHSLatency < RHSLatency) return true;
1285 if (LHSLatency > RHSLatency) return false;
1287 // After that, if two nodes have identical latencies, look to see if one will
1288 // unblock more other nodes than the other.
1289 unsigned LHSBlocked = PQ->getNumSolelyBlockNodes(LHSNum);
1290 unsigned RHSBlocked = PQ->getNumSolelyBlockNodes(RHSNum);
1291 if (LHSBlocked < RHSBlocked) return true;
1292 if (LHSBlocked > RHSBlocked) return false;
1294 // Finally, just to provide a stable ordering, use the node number as a
1296 return LHSNum < RHSNum;
1300 /// CalcNodePriority - Calculate the maximal path from the node to the exit.
1302 int LatencyPriorityQueue::CalcLatency(const SUnit &SU) {
1303 int &Latency = Latencies[SU.NodeNum];
1307 int MaxSuccLatency = 0;
1308 for (std::set<std::pair<SUnit*, bool> >::const_iterator I = SU.Succs.begin(),
1309 E = SU.Succs.end(); I != E; ++I)
1310 MaxSuccLatency = std::max(MaxSuccLatency, CalcLatency(*I->first));
1312 return Latency = MaxSuccLatency + SU.Latency;
1315 /// CalculatePriorities - Calculate priorities of all scheduling units.
1316 void LatencyPriorityQueue::CalculatePriorities() {
1317 Latencies.assign(SUnits->size(), -1);
1318 NumNodesSolelyBlocking.assign(SUnits->size(), 0);
1320 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1321 CalcLatency((*SUnits)[i]);
1324 /// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor
1325 /// of SU, return it, otherwise return null.
1326 static SUnit *getSingleUnscheduledPred(SUnit *SU) {
1327 SUnit *OnlyAvailablePred = 0;
1328 for (std::set<std::pair<SUnit*, bool> >::const_iterator I = SU->Preds.begin(),
1329 E = SU->Preds.end(); I != E; ++I)
1330 if (!I->first->isScheduled) {
1331 // We found an available, but not scheduled, predecessor. If it's the
1332 // only one we have found, keep track of it... otherwise give up.
1333 if (OnlyAvailablePred && OnlyAvailablePred != I->first)
1335 OnlyAvailablePred = I->first;
1338 return OnlyAvailablePred;
1341 void LatencyPriorityQueue::push_impl(SUnit *SU) {
1342 // Look at all of the successors of this node. Count the number of nodes that
1343 // this node is the sole unscheduled node for.
1344 unsigned NumNodesBlocking = 0;
1345 for (std::set<std::pair<SUnit*, bool> >::const_iterator I = SU->Succs.begin(),
1346 E = SU->Succs.end(); I != E; ++I)
1347 if (getSingleUnscheduledPred(I->first) == SU)
1349 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
1355 // ScheduledNode - As nodes are scheduled, we look to see if there are any
1356 // successor nodes that have a single unscheduled predecessor. If so, that
1357 // single predecessor has a higher priority, since scheduling it will make
1358 // the node available.
1359 void LatencyPriorityQueue::ScheduledNode(SUnit *SU) {
1360 for (std::set<std::pair<SUnit*, bool> >::const_iterator I = SU->Succs.begin(),
1361 E = SU->Succs.end(); I != E; ++I)
1362 AdjustPriorityOfUnscheduledPreds(I->first);
1365 /// AdjustPriorityOfUnscheduledPreds - One of the predecessors of SU was just
1366 /// scheduled. If SU is not itself available, then there is at least one
1367 /// predecessor node that has not been scheduled yet. If SU has exactly ONE
1368 /// unscheduled predecessor, we want to increase its priority: it getting
1369 /// scheduled will make this node available, so it is better than some other
1370 /// node of the same priority that will not make a node available.
1371 void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) {
1372 if (SU->isPending) return; // All preds scheduled.
1374 SUnit *OnlyAvailablePred = getSingleUnscheduledPred(SU);
1375 if (OnlyAvailablePred == 0 || !OnlyAvailablePred->isAvailable) return;
1377 // Okay, we found a single predecessor that is available, but not scheduled.
1378 // Since it is available, it must be in the priority queue. First remove it.
1379 RemoveFromPriorityQueue(OnlyAvailablePred);
1381 // Reinsert the node into the priority queue, which recomputes its
1382 // NumNodesSolelyBlocking value.
1383 push(OnlyAvailablePred);
1387 //===----------------------------------------------------------------------===//
1388 // Public Constructor Functions
1389 //===----------------------------------------------------------------------===//
1391 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
1392 MachineBasicBlock *BB) {
1393 return new ScheduleDAGList(DAG, BB, DAG.getTarget(), true,
1394 new RegReductionPriorityQueue<ls_rr_sort>(),
1395 new HazardRecognizer());
1398 /// createTDListDAGScheduler - This creates a top-down list scheduler with the
1399 /// specified hazard recognizer.
1400 ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG &DAG,
1401 MachineBasicBlock *BB,
1402 HazardRecognizer *HR) {
1403 return new ScheduleDAGList(DAG, BB, DAG.getTarget(), false,
1404 new LatencyPriorityQueue(),