1 //===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Support/Debug.h"
31 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
32 /// group of nodes flagged together.
34 SDNode *Node; // Representative node.
35 std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
36 std::set<SUnit*> Preds; // All real predecessors.
37 std::set<SUnit*> ChainPreds; // All chain predecessors.
38 std::set<SUnit*> Succs; // All real successors.
39 std::set<SUnit*> ChainSuccs; // All chain successors.
40 int NumPredsLeft; // # of preds not scheduled.
41 int NumSuccsLeft; // # of succs not scheduled.
42 int NumChainPredsLeft; // # of chain preds not scheduled.
43 int NumChainSuccsLeft; // # of chain succs not scheduled.
44 int Priority1; // Scheduling priority 1.
45 int Priority2; // Scheduling priority 2.
46 bool isTwoAddress; // Is a two-address instruction.
47 bool isDefNUseOperand; // Is a def&use operand.
48 unsigned Latency; // Node latency.
49 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
50 unsigned Slot; // Cycle node is scheduled at.
54 : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
55 NumChainPredsLeft(0), NumChainSuccsLeft(0),
56 Priority1(INT_MIN), Priority2(INT_MIN),
57 isTwoAddress(false), isDefNUseOperand(false),
58 Latency(0), CycleBound(0), Slot(0), Next(NULL) {}
60 void dump(const SelectionDAG *G, bool All=true) const;
63 void SUnit::dump(const SelectionDAG *G, bool All) const {
67 if (FlaggedNodes.size() != 0) {
68 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
70 FlaggedNodes[i]->dump(G);
76 std::cerr << "# preds left : " << NumPredsLeft << "\n";
77 std::cerr << "# succs left : " << NumSuccsLeft << "\n";
78 std::cerr << "# chain preds left : " << NumChainPredsLeft << "\n";
79 std::cerr << "# chain succs left : " << NumChainSuccsLeft << "\n";
80 std::cerr << "Latency : " << Latency << "\n";
81 std::cerr << "Priority : " << Priority1 << " , " << Priority2 << "\n";
83 if (Preds.size() != 0) {
84 std::cerr << "Predecessors :\n";
85 for (std::set<SUnit*>::const_iterator I = Preds.begin(),
86 E = Preds.end(); I != E; ++I) {
91 if (ChainPreds.size() != 0) {
92 std::cerr << "Chained Preds :\n";
93 for (std::set<SUnit*>::const_iterator I = ChainPreds.begin(),
94 E = ChainPreds.end(); I != E; ++I) {
99 if (Succs.size() != 0) {
100 std::cerr << "Successors :\n";
101 for (std::set<SUnit*>::const_iterator I = Succs.begin(),
102 E = Succs.end(); I != E; ++I) {
104 (*I)->dump(G, false);
107 if (ChainSuccs.size() != 0) {
108 std::cerr << "Chained succs :\n";
109 for (std::set<SUnit*>::const_iterator I = ChainSuccs.begin(),
110 E = ChainSuccs.end(); I != E; ++I) {
112 (*I)->dump(G, false);
118 /// Sorting functions for the Available queue.
119 struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
120 bool operator()(const SUnit* left, const SUnit* right) const {
121 bool LFloater = (left ->Preds.size() == 0);
122 bool RFloater = (right->Preds.size() == 0);
123 int LBonus = (int)left ->isDefNUseOperand;
124 int RBonus = (int)right->isDefNUseOperand;
126 // Special tie breaker: if two nodes share a operand, the one that
127 // use it as a def&use operand is preferred.
128 if (left->isTwoAddress && !right->isTwoAddress) {
129 SDNode *DUNode = left->Node->getOperand(0).Val;
130 if (DUNode->isOperand(right->Node))
133 if (!left->isTwoAddress && right->isTwoAddress) {
134 SDNode *DUNode = right->Node->getOperand(0).Val;
135 if (DUNode->isOperand(left->Node))
139 int LPriority1 = left ->Priority1 - LBonus;
140 int RPriority1 = right->Priority1 - RBonus;
141 int LPriority2 = left ->Priority2 + LBonus;
142 int RPriority2 = right->Priority2 + RBonus;
144 // Favor floaters (i.e. node with no non-passive predecessors):
146 if (!LFloater && RFloater)
148 else if (LFloater == RFloater)
149 if (LPriority1 > RPriority1)
151 else if (LPriority1 == RPriority1)
152 if (LPriority2 < RPriority2)
154 else if (LPriority1 == RPriority1)
155 if (left->CycleBound > right->CycleBound)
162 /// ScheduleDAGList - List scheduler.
163 class ScheduleDAGList : public ScheduleDAG {
165 // SDNode to SUnit mapping (many to one).
166 std::map<SDNode*, SUnit*> SUnitMap;
168 std::vector<SUnit*> Sequence;
169 // Current scheduling cycle.
171 // First and last SUnit created.
172 SUnit *HeadSUnit, *TailSUnit;
174 typedef std::priority_queue<SUnit*, std::vector<SUnit*>, ls_rr_sort>
178 ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
179 const TargetMachine &tm)
180 : ScheduleDAG(listSchedulingBURR, dag, bb, tm),
181 CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL) {};
184 SUnit *SU = HeadSUnit;
186 SUnit *NextSU = SU->Next;
197 SUnit *NewSUnit(SDNode *N);
198 void ReleasePred(AvailableQueueTy &Avail,SUnit *PredSU, bool isChain = false);
199 void ScheduleNode(AvailableQueueTy &Avail, SUnit *SU);
200 int CalcNodePriority(SUnit *SU);
201 void CalculatePriorities();
203 void BuildSchedUnits();
209 /// NewSUnit - Creates a new SUnit and return a ptr to it.
210 SUnit *ScheduleDAGList::NewSUnit(SDNode *N) {
211 SUnit *CurrSUnit = new SUnit(N);
213 if (HeadSUnit == NULL)
214 HeadSUnit = CurrSUnit;
215 if (TailSUnit != NULL)
216 TailSUnit->Next = CurrSUnit;
217 TailSUnit = CurrSUnit;
222 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
223 /// the Available queue is the count reaches zero. Also update its cycle bound.
224 void ScheduleDAGList::ReleasePred(AvailableQueueTy &Available,
225 SUnit *PredSU, bool isChain) {
226 SDNode *PredNode = PredSU->Node;
228 // FIXME: the distance between two nodes is not always == the predecessor's
229 // latency. For example, the reader can very well read the register written
230 // by the predecessor later than the issue cycle. It also depends on the
231 // interrupt model (drain vs. freeze).
232 PredSU->CycleBound = std::max(PredSU->CycleBound, CurrCycle + PredSU->Latency);
235 PredSU->NumSuccsLeft--;
238 PredSU->NumChainSuccsLeft--;
239 if (PredSU->NumSuccsLeft == 0 && PredSU->NumChainSuccsLeft == 0) {
240 // EntryToken has to go last!
241 if (PredNode->getOpcode() != ISD::EntryToken)
242 Available.push(PredSU);
243 } else if (PredSU->NumSuccsLeft < 0) {
245 std::cerr << "*** List scheduling failed! ***\n";
247 std::cerr << " has been released too many times!\n";
253 /// ScheduleNode - Add the node to the schedule. Decrement the pending count of
254 /// its predecessors. If a predecessor pending count is zero, add it to the
256 void ScheduleDAGList::ScheduleNode(AvailableQueueTy &Available, SUnit *SU) {
257 DEBUG(std::cerr << "*** Scheduling: ");
258 DEBUG(SU->dump(&DAG, false));
260 Sequence.push_back(SU);
261 SU->Slot = CurrCycle;
263 // Bottom up: release predecessors
264 for (std::set<SUnit*>::iterator I1 = SU->Preds.begin(),
265 E1 = SU->Preds.end(); I1 != E1; ++I1) {
266 ReleasePred(Available, *I1);
270 for (std::set<SUnit*>::iterator I2 = SU->ChainPreds.begin(),
271 E2 = SU->ChainPreds.end(); I2 != E2; ++I2)
272 ReleasePred(Available, *I2, true);
277 /// isReady - True if node's lower cycle bound is less or equal to the current
278 /// scheduling cycle. Always true if all nodes have uniform latency 1.
279 static inline bool isReady(SUnit *SU, unsigned CurrCycle) {
280 return SU->CycleBound <= CurrCycle;
283 /// ListSchedule - The main loop of list scheduling.
284 void ScheduleDAGList::ListSchedule() {
286 AvailableQueueTy Available;
288 // Add root to Available queue.
289 SUnit *Root = SUnitMap[DAG.getRoot().Val];
290 Available.push(Root);
292 // While Available queue is not empty, grab the node with the highest
293 // priority. If it is not ready put it back. Schedule the node.
294 std::vector<SUnit*> NotReady;
295 while (!Available.empty()) {
296 SUnit *CurrNode = Available.top();
300 while (!isReady(CurrNode, CurrCycle)) {
301 NotReady.push_back(CurrNode);
302 CurrNode = Available.top();
305 for (unsigned i = 0, e = NotReady.size(); i != e; ++i)
306 Available.push(NotReady[i]);
308 ScheduleNode(Available, CurrNode);
311 // Add entry node last
312 if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
313 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
314 Entry->Slot = CurrCycle;
315 Sequence.push_back(Entry);
319 bool AnyNotSched = false;
320 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
321 if (SU->NumSuccsLeft != 0 || SU->NumChainSuccsLeft != 0) {
323 std::cerr << "*** List scheduling failed! ***\n";
325 std::cerr << "has not been scheduled!\n";
329 assert(!AnyNotSched);
333 // Reverse the order if it is bottom up.
334 std::reverse(Sequence.begin(), Sequence.end());
336 DEBUG(std::cerr << "*** Final schedule ***\n");
338 DEBUG(std::cerr << "\n");
341 /// CalcNodePriority - Priority1 is just the number of live range genned -
342 /// number of live range killed. Priority2 is the Sethi Ullman number. It
343 /// returns Priority2 since it is calculated recursively.
344 /// Smaller number is the higher priority for Priority2. Reverse is true for
346 int ScheduleDAGList::CalcNodePriority(SUnit *SU) {
347 if (SU->Priority2 != INT_MIN)
348 return SU->Priority2;
350 SU->Priority1 = SU->NumPredsLeft - SU->NumSuccsLeft;
352 if (SU->Preds.size() == 0) {
356 for (std::set<SUnit*>::iterator I = SU->Preds.begin(),
357 E = SU->Preds.end(); I != E; ++I) {
359 int PredPriority = CalcNodePriority(PredSU);
360 if (PredPriority > SU->Priority2) {
361 SU->Priority2 = PredPriority;
363 } else if (PredPriority == SU->Priority2)
367 if (SU->Node->getOpcode() != ISD::TokenFactor)
368 SU->Priority2 += Extra;
370 SU->Priority2 = (Extra == 1) ? 0 : Extra-1;
373 return SU->Priority2;
376 /// CalculatePriorities - Calculate priorities of all scheduling units.
377 void ScheduleDAGList::CalculatePriorities() {
378 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
379 // FIXME: assumes uniform latency for now.
381 (void)CalcNodePriority(SU);
382 DEBUG(SU->dump(&DAG));
383 DEBUG(std::cerr << "\n");
387 void ScheduleDAGList::BuildSchedUnits() {
388 // Pass 1: create the SUnit's.
389 for (unsigned i = 0, NC = NodeCount; i < NC; i++) {
390 NodeInfo *NI = &Info[i];
391 SDNode *N = NI->Node;
392 if (isPassiveNode(N))
396 if (NI->isInGroup()) {
397 if (NI != NI->Group->getBottom()) // Bottom up, so only look at bottom
398 continue; // node of the NodeGroup
401 // Find the flagged nodes.
402 SDOperand FlagOp = N->getOperand(N->getNumOperands() - 1);
403 SDNode *Flag = FlagOp.Val;
404 unsigned ResNo = FlagOp.ResNo;
405 while (Flag->getValueType(ResNo) == MVT::Flag) {
406 NodeInfo *FNI = getNI(Flag);
407 assert(FNI->Group == NI->Group);
408 SU->FlaggedNodes.insert(SU->FlaggedNodes.begin(), Flag);
411 FlagOp = Flag->getOperand(Flag->getNumOperands() - 1);
413 ResNo = FlagOp.ResNo;
421 // Pass 2: add the preds, succs, etc.
422 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
423 SDNode *N = SU->Node;
424 NodeInfo *NI = getNI(N);
426 if (N->isTargetOpcode() && TII->isTwoAddrInstr(N->getTargetOpcode()))
427 SU->isTwoAddress = true;
429 if (NI->isInGroup()) {
430 // Find all predecessors (of the group).
431 NodeGroupOpIterator NGOI(NI);
432 while (!NGOI.isEnd()) {
433 SDOperand Op = NGOI.next();
434 SDNode *OpN = Op.Val;
435 MVT::ValueType VT = OpN->getValueType(Op.ResNo);
436 NodeInfo *OpNI = getNI(OpN);
437 if (OpNI->Group != NI->Group && !isPassiveNode(OpN)) {
438 assert(VT != MVT::Flag);
439 SUnit *OpSU = SUnitMap[OpN];
440 if (VT == MVT::Other) {
441 if (SU->ChainPreds.insert(OpSU).second)
442 SU->NumChainPredsLeft++;
443 if (OpSU->ChainSuccs.insert(SU).second)
444 OpSU->NumChainSuccsLeft++;
446 if (SU->Preds.insert(OpSU).second)
448 if (OpSU->Succs.insert(SU).second)
449 OpSU->NumSuccsLeft++;
454 // Find node predecessors.
455 for (unsigned j = 0, e = N->getNumOperands(); j != e; j++) {
456 SDOperand Op = N->getOperand(j);
457 SDNode *OpN = Op.Val;
458 MVT::ValueType VT = OpN->getValueType(Op.ResNo);
459 if (!isPassiveNode(OpN)) {
460 assert(VT != MVT::Flag);
461 SUnit *OpSU = SUnitMap[OpN];
462 if (VT == MVT::Other) {
463 if (SU->ChainPreds.insert(OpSU).second)
464 SU->NumChainPredsLeft++;
465 if (OpSU->ChainSuccs.insert(SU).second)
466 OpSU->NumChainSuccsLeft++;
468 if (SU->Preds.insert(OpSU).second)
470 if (OpSU->Succs.insert(SU).second)
471 OpSU->NumSuccsLeft++;
472 if (j == 0 && SU->isTwoAddress)
473 OpSU->isDefNUseOperand = true;
481 /// EmitSchedule - Emit the machine code in scheduled order.
482 void ScheduleDAGList::EmitSchedule() {
483 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
485 SUnit *SU = Sequence[i];
486 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++) {
487 N = SU->FlaggedNodes[j];
490 EmitNode(getNI(SU->Node));
494 /// dump - dump the schedule.
495 void ScheduleDAGList::dump() const {
496 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
497 SUnit *SU = Sequence[i];
498 SU->dump(&DAG, false);
502 /// Schedule - Schedule the DAG using list scheduling.
503 /// FIXME: Right now it only supports the burr (bottom up register reducing)
505 void ScheduleDAGList::Schedule() {
506 DEBUG(std::cerr << "********** List Scheduling **********\n");
508 // Build scheduling units.
511 // Calculate node prirorities.
512 CalculatePriorities();
514 // Execute the actual scheduling loop.
517 // Emit in scheduled order
521 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
522 MachineBasicBlock *BB) {
523 return new ScheduleDAGList(DAG, BB, DAG.getTarget());