1 //===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple code linearizer for DAGs. This is not a very good
11 // way to emit code, but gets working code quickly.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/SSARegMap.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Support/CommandLine.h"
27 ViewDAGs("view-sched-dags", cl::Hidden,
28 cl::desc("Pop up a window to show sched dags as they are processed"));
30 static const bool ViewDAGS = 0;
36 MachineBasicBlock *BB;
37 const TargetMachine &TM;
38 const TargetInstrInfo &TII;
39 const MRegisterInfo &MRI;
42 std::map<SDNode *, unsigned> EmittedOps;
44 SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
45 : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
46 MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
47 assert(&TII && "Target doesn't provide instr info?");
48 assert(&MRI && "Target doesn't provide register info?");
56 unsigned Emit(SDOperand Op);
60 unsigned SimpleSched::Emit(SDOperand Op) {
61 // Check to see if we have already emitted this. If so, return the value
62 // already emitted. Note that if a node has a single use it cannot be
63 // revisited, so don't bother putting it in the map.
65 if (Op.Val->hasOneUse()) {
66 OpSlot = 0; // No reuse possible.
68 std::map<SDNode *, unsigned>::iterator OpI = EmittedOps.lower_bound(Op.Val);
69 if (OpI != EmittedOps.end() && OpI->first == Op.Val)
70 return OpI->second + Op.ResNo;
71 OpSlot = &EmittedOps.insert(OpI, std::make_pair(Op.Val, 0))->second;
74 unsigned ResultReg = 0;
75 if (Op.isTargetOpcode()) {
76 unsigned Opc = Op.getTargetOpcode();
77 const TargetInstrDescriptor &II = TII.get(Opc);
79 // Target nodes have any register or immediate operands before any chain
80 // nodes. Check that the DAG matches the TD files's expectation of #
82 unsigned NumResults = Op.Val->getNumValues();
83 if (NumResults && Op.getOperand(NumResults-1).getValueType() == MVT::Other)
86 unsigned Operands = Op.getNumOperands();
87 if (Operands && Op.getOperand(Operands-1).getValueType() == MVT::Other)
89 assert(unsigned(II.numOperands) == Operands+NumResults &&
90 "#operands for dag node doesn't match .td file!");
93 // Create the new machine instruction.
94 MachineInstr *MI = new MachineInstr(Opc, II.numOperands, true, true);
96 // Add result register values for things that are defined by this
99 // Create the result registers for this node and add the result regs to
100 // the machine instruction.
101 const TargetOperandInfo *OpInfo = II.OpInfo;
102 ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
103 MI->addRegOperand(ResultReg, MachineOperand::Def);
104 for (unsigned i = 1; i != NumResults; ++i) {
105 assert(OpInfo[i].RegClass && "Isn't a register operand!");
106 MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[0].RegClass),
107 MachineOperand::Def);
111 // Emit all of the operands of this instruction, adding them to the
112 // instruction as appropriate.
113 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
115 MI->addZeroExtImm64Operand(C->getValue());
116 } else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
117 MI->addRegOperand(R->getReg(), MachineOperand::Use);
119 unsigned R = Emit(Op.getOperand(i));
120 // Add an operand, unless this corresponds to a chain node.
121 if (Op.getOperand(i).getValueType() != MVT::Other)
122 MI->addRegOperand(R, MachineOperand::Use);
126 // Now that we have emitted all operands, emit this instruction itself.
127 BB->insert(BB->end(), MI);
129 switch (Op.getOpcode()) {
132 assert(0 && "This target-independent node should have been selected!");
133 case ISD::EntryToken: break;
134 case ISD::TokenFactor:
135 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
136 Emit(Op.getOperand(i));
138 case ISD::CopyToReg: {
139 Emit(Op.getOperand(0)); // Emit the chain.
140 unsigned Val = Emit(Op.getOperand(2));
141 MRI.copyRegToReg(*BB, BB->end(),
142 cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
143 RegMap->getRegClass(Val));
146 case ISD::CopyFromReg: {
147 Emit(Op.getOperand(0)); // Emit the chain.
148 unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
150 // Figure out the register class to create for the destreg.
151 const TargetRegisterClass *TRC;
152 if (MRegisterInfo::isVirtualRegister(SrcReg)) {
153 TRC = RegMap->getRegClass(SrcReg);
155 // FIXME: we don't know what register class to generate this for. Do
156 // a brute force search and pick the first match. :(
157 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
158 E = MRI.regclass_end(); I != E; ++I)
159 if ((*I)->contains(SrcReg)) {
163 assert(TRC && "Couldn't find register class for reg copy!");
166 // Create the reg, emit the copy.
167 ResultReg = RegMap->createVirtualRegister(TRC);
168 MRI.copyRegToReg(*BB, BB->end(), ResultReg, SrcReg, TRC);
174 if (OpSlot) *OpSlot = ResultReg;
175 return ResultReg+Op.ResNo;
179 /// Pick a safe ordering and emit instructions for each target node in the
181 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
182 if (ViewDAGs) SD.viewGraph();
183 SimpleSched(SD, BB).Run();