1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
28 //===----------------------------------------------------------------------===//
29 // Result Vector Scalarization: <1 x ty> -> ty.
30 //===----------------------------------------------------------------------===//
32 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
35 SDValue R = SDValue();
37 switch (N->getOpcode()) {
40 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to scalarize the result of this operator!");
46 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
47 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
48 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
49 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
50 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
51 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
52 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
53 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
54 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
55 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
56 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
57 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
58 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
59 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
79 case ISD::SIGN_EXTEND:
80 case ISD::ZERO_EXTEND:
82 R = ScalarizeVecRes_UnaryOp(N);
104 R = ScalarizeVecRes_BinOp(N);
108 // If R is null, the sub-method took care of registering the result.
110 SetScalarizedVector(SDValue(N, ResNo), R);
113 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
114 SDValue LHS = GetScalarizedVector(N->getOperand(0));
115 SDValue RHS = GetScalarizedVector(N->getOperand(1));
116 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
117 LHS.getValueType(), LHS, RHS);
120 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
121 MVT NewVT = N->getValueType(0).getVectorElementType();
122 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
123 NewVT, N->getOperand(0));
126 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
127 MVT NewVT = N->getValueType(0).getVectorElementType();
128 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
129 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
130 Op0, DAG.getValueType(NewVT),
131 DAG.getValueType(Op0.getValueType()),
134 cast<CvtRndSatSDNode>(N)->getCvtCode());
137 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
138 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
139 N->getValueType(0).getVectorElementType(),
140 N->getOperand(0), N->getOperand(1));
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
144 SDValue Op = GetScalarizedVector(N->getOperand(0));
145 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
146 Op.getValueType(), Op, N->getOperand(1));
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
150 // The value to insert may have a wider type than the vector element type,
151 // so be sure to truncate it to the element type if necessary.
152 SDValue Op = N->getOperand(1);
153 MVT EltVT = N->getValueType(0).getVectorElementType();
154 if (Op.getValueType() != EltVT)
155 // FIXME: Can this happen for floating point types?
156 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
161 assert(N->isUnindexed() && "Indexed vector load?");
163 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
164 N->getExtensionType(),
165 N->getValueType(0).getVectorElementType(),
166 N->getChain(), N->getBasePtr(),
167 DAG.getUNDEF(N->getBasePtr().getValueType()),
168 N->getSrcValue(), N->getSrcValueOffset(),
169 N->getMemoryVT().getVectorElementType(),
170 N->isVolatile(), N->getAlignment());
172 // Legalized the chain result - switch anything that used the old chain to
174 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
178 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
179 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
180 MVT DestVT = N->getValueType(0).getVectorElementType();
181 SDValue Op = GetScalarizedVector(N->getOperand(0));
182 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
186 // If the operand is wider than the vector element type then it is implicitly
187 // truncated. Make that explicit here.
188 MVT EltVT = N->getValueType(0).getVectorElementType();
189 SDValue InOp = N->getOperand(0);
190 if (InOp.getValueType() != EltVT)
191 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
195 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
196 SDValue LHS = GetScalarizedVector(N->getOperand(1));
197 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
198 LHS.getValueType(), N->getOperand(0), LHS,
199 GetScalarizedVector(N->getOperand(2)));
202 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
203 SDValue LHS = GetScalarizedVector(N->getOperand(2));
204 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
205 N->getOperand(0), N->getOperand(1),
206 LHS, GetScalarizedVector(N->getOperand(3)),
210 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
211 SDValue LHS = GetScalarizedVector(N->getOperand(0));
212 SDValue RHS = GetScalarizedVector(N->getOperand(1));
213 DebugLoc DL = N->getDebugLoc();
215 // Turn it into a scalar SETCC.
216 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
219 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
220 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
224 // Figure out if the scalar is the LHS or RHS and return it.
225 SDValue Arg = N->getOperand(2).getOperand(0);
226 if (Arg.getOpcode() == ISD::UNDEF)
227 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
228 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
229 return GetScalarizedVector(N->getOperand(Op));
232 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
233 SDValue LHS = GetScalarizedVector(N->getOperand(0));
234 SDValue RHS = GetScalarizedVector(N->getOperand(1));
235 MVT NVT = N->getValueType(0).getVectorElementType();
236 MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
237 DebugLoc DL = N->getDebugLoc();
239 // Turn it into a scalar SETCC.
240 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
242 // VSETCC always returns a sign-extended value, while SETCC may not. The
243 // SETCC result type may not match the vector element type. Correct these.
244 if (NVT.bitsLE(SVT)) {
245 // The SETCC result type is bigger than the vector element type.
246 // Ensure the SETCC result is sign-extended.
247 if (TLI.getBooleanContents() !=
248 TargetLowering::ZeroOrNegativeOneBooleanContent)
249 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
250 DAG.getValueType(MVT::i1));
251 // Truncate to the final type.
252 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
255 // The SETCC result type is smaller than the vector element type.
256 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
257 if (TLI.getBooleanContents() !=
258 TargetLowering::ZeroOrNegativeOneBooleanContent)
259 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
260 // Sign extend to the final type.
261 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
265 //===----------------------------------------------------------------------===//
266 // Operand Vector Scalarization <1 x ty> -> ty.
267 //===----------------------------------------------------------------------===//
269 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
270 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
272 SDValue Res = SDValue();
274 if (Res.getNode() == 0) {
275 switch (N->getOpcode()) {
278 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
279 N->dump(&DAG); cerr << "\n";
281 assert(0 && "Do not know how to scalarize this operator's operand!");
282 case ISD::BIT_CONVERT:
283 Res = ScalarizeVecOp_BIT_CONVERT(N);
285 case ISD::CONCAT_VECTORS:
286 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
288 case ISD::EXTRACT_VECTOR_ELT:
289 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
292 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
297 // If the result is null, the sub-method took care of registering results etc.
298 if (!Res.getNode()) return false;
300 // If the result is N, the sub-method updated N in place. Tell the legalizer
302 if (Res.getNode() == N)
305 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
306 "Invalid operand expansion");
308 ReplaceValueWith(SDValue(N, 0), Res);
312 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
313 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
314 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
315 SDValue Elt = GetScalarizedVector(N->getOperand(0));
316 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
317 N->getValueType(0), Elt);
320 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
321 /// use a BUILD_VECTOR instead.
322 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
323 SmallVector<SDValue, 8> Ops(N->getNumOperands());
324 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
325 Ops[i] = GetScalarizedVector(N->getOperand(i));
326 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
327 &Ops[0], Ops.size());
330 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
331 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
333 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
334 return GetScalarizedVector(N->getOperand(0));
337 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
338 /// scalarized, it must be <1 x ty>. Just store the element.
339 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
340 assert(N->isUnindexed() && "Indexed store of one-element vector?");
341 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
342 DebugLoc dl = N->getDebugLoc();
344 if (N->isTruncatingStore())
345 return DAG.getTruncStore(N->getChain(), dl,
346 GetScalarizedVector(N->getOperand(1)),
348 N->getSrcValue(), N->getSrcValueOffset(),
349 N->getMemoryVT().getVectorElementType(),
350 N->isVolatile(), N->getAlignment());
352 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
353 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
354 N->isVolatile(), N->getAlignment());
358 //===----------------------------------------------------------------------===//
359 // Result Vector Splitting
360 //===----------------------------------------------------------------------===//
362 /// SplitVectorResult - This method is called when the specified result of the
363 /// specified node is found to need vector splitting. At this point, the node
364 /// may also have invalid operands or may have other results that need
365 /// legalization, we just know that (at least) one result needs vector
367 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
368 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
371 switch (N->getOpcode()) {
374 cerr << "SplitVectorResult #" << ResNo << ": ";
375 N->dump(&DAG); cerr << "\n";
377 assert(0 && "Do not know how to split the result of this operator!");
380 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
381 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
382 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
383 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
385 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
386 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
387 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
388 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
389 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
390 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
391 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
392 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
394 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
398 SplitVecRes_SETCC(N, Lo, Hi);
400 case ISD::VECTOR_SHUFFLE:
401 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
416 case ISD::FNEARBYINT:
417 case ISD::FP_TO_SINT:
418 case ISD::FP_TO_UINT:
419 case ISD::SINT_TO_FP:
420 case ISD::UINT_TO_FP:
422 case ISD::SIGN_EXTEND:
423 case ISD::ZERO_EXTEND:
424 case ISD::ANY_EXTEND:
425 SplitVecRes_UnaryOp(N, Lo, Hi);
447 SplitVecRes_BinOp(N, Lo, Hi);
451 // If Lo/Hi is null, the sub-method took care of registering results etc.
453 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
456 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
458 SDValue LHSLo, LHSHi;
459 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
460 SDValue RHSLo, RHSHi;
461 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
462 DebugLoc dl = N->getDebugLoc();
464 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
465 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
468 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
470 // We know the result is a vector. The input may be either a vector or a
473 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
474 DebugLoc dl = N->getDebugLoc();
476 SDValue InOp = N->getOperand(0);
477 MVT InVT = InOp.getValueType();
479 // Handle some special cases efficiently.
480 switch (getTypeAction(InVT)) {
482 assert(false && "Unknown type action!");
486 case ScalarizeVector:
490 // A scalar to vector conversion, where the scalar needs expansion.
491 // If the vector is being split in two then we can just convert the
494 GetExpandedOp(InOp, Lo, Hi);
495 if (TLI.isBigEndian())
497 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
498 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
503 // If the input is a vector that needs to be split, convert each split
504 // piece of the input now.
505 GetSplitVector(InOp, Lo, Hi);
506 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
507 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
511 // In the general case, convert the input to an integer and split it by hand.
512 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
513 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
514 if (TLI.isBigEndian())
515 std::swap(LoIntVT, HiIntVT);
517 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
519 if (TLI.isBigEndian())
521 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
522 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
525 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
528 DebugLoc dl = N->getDebugLoc();
529 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
530 unsigned LoNumElts = LoVT.getVectorNumElements();
531 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
532 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
534 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
535 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
538 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
540 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
541 DebugLoc dl = N->getDebugLoc();
542 unsigned NumSubvectors = N->getNumOperands() / 2;
543 if (NumSubvectors == 1) {
544 Lo = N->getOperand(0);
545 Hi = N->getOperand(1);
550 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
552 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
553 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
555 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
556 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
559 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
562 DebugLoc dl = N->getDebugLoc();
563 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
565 SDValue DTyOpLo = DAG.getValueType(LoVT);
566 SDValue DTyOpHi = DAG.getValueType(HiVT);
568 SDValue RndOp = N->getOperand(3);
569 SDValue SatOp = N->getOperand(4);
570 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
574 MVT InVT = N->getOperand(0).getValueType();
575 switch (getTypeAction(InVT)) {
576 default: assert(0 && "Unexpected type action!");
578 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
579 LoVT.getVectorNumElements());
580 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
581 DAG.getIntPtrConstant(0));
582 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
583 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
587 GetSplitVector(N->getOperand(0), VLo, VHi);
590 // If the result needs to be split and the input needs to be widened,
591 // the two types must have different lengths. Use the widened result
592 // and extract from it to do the split.
593 SDValue InOp = GetWidenedVector(N->getOperand(0));
594 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
595 LoVT.getVectorNumElements());
596 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
597 DAG.getIntPtrConstant(0));
598 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
599 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
604 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
605 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
607 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
609 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
613 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
615 SDValue Vec = N->getOperand(0);
616 SDValue Idx = N->getOperand(1);
617 MVT IdxVT = Idx.getValueType();
618 DebugLoc dl = N->getDebugLoc();
621 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
623 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
624 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
625 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
626 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
629 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
631 DebugLoc dl = N->getDebugLoc();
632 GetSplitVector(N->getOperand(0), Lo, Hi);
633 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
634 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
637 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
639 SDValue Vec = N->getOperand(0);
640 SDValue Elt = N->getOperand(1);
641 SDValue Idx = N->getOperand(2);
642 DebugLoc dl = N->getDebugLoc();
643 GetSplitVector(Vec, Lo, Hi);
645 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
646 unsigned IdxVal = CIdx->getZExtValue();
647 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
648 if (IdxVal < LoNumElts)
649 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
650 Lo.getValueType(), Lo, Elt, Idx);
652 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
653 DAG.getIntPtrConstant(IdxVal - LoNumElts));
657 // Spill the vector to the stack.
658 MVT VecVT = Vec.getValueType();
659 MVT EltVT = VecVT.getVectorElementType();
660 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
661 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
663 // Store the new element. This may be larger than the vector element type,
664 // so use a truncating store.
665 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
667 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
668 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
670 // Load the Lo part from the stack slot.
671 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0);
673 // Increment the pointer to the other part.
674 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
675 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
676 DAG.getIntPtrConstant(IncrementSize));
678 // Load the Hi part from the stack slot.
679 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
680 MinAlign(Alignment, IncrementSize));
683 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
686 DebugLoc dl = N->getDebugLoc();
687 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
688 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
689 Hi = DAG.getUNDEF(HiVT);
692 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
694 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
696 DebugLoc dl = LD->getDebugLoc();
697 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
699 ISD::LoadExtType ExtType = LD->getExtensionType();
700 SDValue Ch = LD->getChain();
701 SDValue Ptr = LD->getBasePtr();
702 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
703 const Value *SV = LD->getSrcValue();
704 int SVOffset = LD->getSrcValueOffset();
705 MVT MemoryVT = LD->getMemoryVT();
706 unsigned Alignment = LD->getAlignment();
707 bool isVolatile = LD->isVolatile();
709 MVT LoMemVT, HiMemVT;
710 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
712 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
713 SV, SVOffset, LoMemVT, isVolatile, Alignment);
715 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
716 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
717 DAG.getIntPtrConstant(IncrementSize));
718 SVOffset += IncrementSize;
719 Alignment = MinAlign(Alignment, IncrementSize);
720 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
721 SV, SVOffset, HiMemVT, isVolatile, Alignment);
723 // Build a factor node to remember that this load is independent of the
725 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
728 // Legalized the chain result - switch anything that used the old chain to
730 ReplaceValueWith(SDValue(LD, 1), Ch);
733 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
735 DebugLoc DL = N->getDebugLoc();
736 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
739 MVT InVT = N->getOperand(0).getValueType();
740 SDValue LL, LH, RL, RH;
741 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
742 LoVT.getVectorNumElements());
743 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
744 DAG.getIntPtrConstant(0));
745 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
746 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
748 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
749 DAG.getIntPtrConstant(0));
750 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
751 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
753 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
754 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
757 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
759 // Get the dest types - they may not match the input types, e.g. int_to_fp.
761 DebugLoc dl = N->getDebugLoc();
762 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
765 MVT InVT = N->getOperand(0).getValueType();
766 switch (getTypeAction(InVT)) {
767 default: assert(0 && "Unexpected type action!");
769 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
770 LoVT.getVectorNumElements());
771 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
772 DAG.getIntPtrConstant(0));
773 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
774 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
778 GetSplitVector(N->getOperand(0), Lo, Hi);
781 // If the result needs to be split and the input needs to be widened,
782 // the two types must have different lengths. Use the widened result
783 // and extract from it to do the split.
784 SDValue InOp = GetWidenedVector(N->getOperand(0));
785 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
786 LoVT.getVectorNumElements());
787 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
788 DAG.getIntPtrConstant(0));
789 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
790 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
795 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
796 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
799 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
800 SDValue &Lo, SDValue &Hi) {
801 // The low and high parts of the original input give four input vectors.
803 DebugLoc dl = N->getDebugLoc();
804 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
805 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
806 MVT NewVT = Inputs[0].getValueType();
807 unsigned NewElts = NewVT.getVectorNumElements();
809 // If Lo or Hi uses elements from at most two of the four input vectors, then
810 // express it as a vector shuffle of those two inputs. Otherwise extract the
811 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
812 SmallVector<int, 16> Ops;
813 for (unsigned High = 0; High < 2; ++High) {
814 SDValue &Output = High ? Hi : Lo;
816 // Build a shuffle mask for the output, discovering on the fly which
817 // input vectors to use as shuffle operands (recorded in InputUsed).
818 // If building a suitable shuffle vector proves too hard, then bail
819 // out with useBuildVector set.
820 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
821 unsigned FirstMaskIdx = High * NewElts;
822 bool useBuildVector = false;
823 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
824 // The mask element. This indexes into the input.
825 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
827 // The input vector this mask element indexes into.
828 unsigned Input = (unsigned)Idx / NewElts;
830 if (Input >= array_lengthof(Inputs)) {
831 // The mask element does not index into any input vector.
836 // Turn the index into an offset from the start of the input vector.
837 Idx -= Input * NewElts;
839 // Find or create a shuffle vector operand to hold this input.
841 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
842 if (InputUsed[OpNo] == Input) {
843 // This input vector is already an operand.
845 } else if (InputUsed[OpNo] == -1U) {
846 // Create a new operand for this input vector.
847 InputUsed[OpNo] = Input;
852 if (OpNo >= array_lengthof(InputUsed)) {
853 // More than two input vectors used! Give up on trying to create a
854 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
855 useBuildVector = true;
859 // Add the mask index for the new shuffle vector.
860 Ops.push_back(Idx + OpNo * NewElts);
863 if (useBuildVector) {
864 MVT EltVT = NewVT.getVectorElementType();
865 SmallVector<SDValue, 16> SVOps;
867 // Extract the input elements by hand.
868 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
869 // The mask element. This indexes into the input.
870 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
872 // The input vector this mask element indexes into.
873 unsigned Input = (unsigned)Idx / NewElts;
875 if (Input >= array_lengthof(Inputs)) {
876 // The mask element is "undef" or indexes off the end of the input.
877 SVOps.push_back(DAG.getUNDEF(EltVT));
881 // Turn the index into an offset from the start of the input vector.
882 Idx -= Input * NewElts;
884 // Extract the vector element by hand.
885 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
886 Inputs[Input], DAG.getIntPtrConstant(Idx)));
889 // Construct the Lo/Hi output using a BUILD_VECTOR.
890 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
891 } else if (InputUsed[0] == -1U) {
892 // No input vectors were used! The result is undefined.
893 Output = DAG.getUNDEF(NewVT);
895 SDValue Op0 = Inputs[InputUsed[0]];
896 // If only one input was used, use an undefined vector for the other.
897 SDValue Op1 = InputUsed[1] == -1U ?
898 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
899 // At least one input vector was used. Create a new shuffle vector.
900 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
908 //===----------------------------------------------------------------------===//
909 // Operand Vector Splitting
910 //===----------------------------------------------------------------------===//
912 /// SplitVectorOperand - This method is called when the specified operand of the
913 /// specified node is found to need vector splitting. At this point, all of the
914 /// result types of the node are known to be legal, but other operands of the
915 /// node may need legalization as well as the specified one.
916 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
917 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
918 SDValue Res = SDValue();
920 if (Res.getNode() == 0) {
921 switch (N->getOpcode()) {
924 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
925 N->dump(&DAG); cerr << "\n";
927 assert(0 && "Do not know how to split this operator's operand!");
930 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
931 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
932 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
934 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
940 case ISD::FP_TO_SINT:
941 case ISD::FP_TO_UINT:
942 case ISD::SINT_TO_FP:
943 case ISD::UINT_TO_FP:
945 case ISD::SIGN_EXTEND:
946 case ISD::ZERO_EXTEND:
947 case ISD::ANY_EXTEND:
948 Res = SplitVecOp_UnaryOp(N);
953 // If the result is null, the sub-method took care of registering results etc.
954 if (!Res.getNode()) return false;
956 // If the result is N, the sub-method updated N in place. Tell the legalizer
958 if (Res.getNode() == N)
961 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
962 "Invalid operand expansion");
964 ReplaceValueWith(SDValue(N, 0), Res);
968 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
969 // The result has a legal vector type, but the input needs splitting.
970 MVT ResVT = N->getValueType(0);
972 DebugLoc dl = N->getDebugLoc();
973 GetSplitVector(N->getOperand(0), Lo, Hi);
974 MVT InVT = Lo.getValueType();
976 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
977 InVT.getVectorNumElements());
979 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
980 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
982 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
985 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
986 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
987 // end up being split all the way down to individual components. Convert the
988 // split pieces into integers and reassemble.
990 GetSplitVector(N->getOperand(0), Lo, Hi);
991 Lo = BitConvertToInteger(Lo);
992 Hi = BitConvertToInteger(Hi);
994 if (TLI.isBigEndian())
997 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
998 JoinIntegers(Lo, Hi));
1001 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1002 // We know that the extracted result type is legal. For now, assume the index
1004 MVT SubVT = N->getValueType(0);
1005 SDValue Idx = N->getOperand(1);
1006 DebugLoc dl = N->getDebugLoc();
1008 GetSplitVector(N->getOperand(0), Lo, Hi);
1010 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1011 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1013 if (IdxVal < LoElts) {
1014 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1015 "Extracted subvector crosses vector split!");
1016 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1018 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1019 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1023 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1024 SDValue Vec = N->getOperand(0);
1025 SDValue Idx = N->getOperand(1);
1026 MVT VecVT = Vec.getValueType();
1028 if (isa<ConstantSDNode>(Idx)) {
1029 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1030 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1033 GetSplitVector(Vec, Lo, Hi);
1035 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1037 if (IdxVal < LoElts)
1038 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
1039 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
1040 DAG.getConstant(IdxVal - LoElts,
1041 Idx.getValueType()));
1044 // Store the vector to the stack.
1045 MVT EltVT = VecVT.getVectorElementType();
1046 DebugLoc dl = N->getDebugLoc();
1047 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1048 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1049 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1050 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0);
1052 // Load back the required element.
1053 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1054 return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0);
1057 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1058 assert(N->isUnindexed() && "Indexed store of vector?");
1059 assert(OpNo == 1 && "Can only split the stored value");
1060 DebugLoc dl = N->getDebugLoc();
1062 bool isTruncating = N->isTruncatingStore();
1063 SDValue Ch = N->getChain();
1064 SDValue Ptr = N->getBasePtr();
1065 int SVOffset = N->getSrcValueOffset();
1066 MVT MemoryVT = N->getMemoryVT();
1067 unsigned Alignment = N->getAlignment();
1068 bool isVol = N->isVolatile();
1070 GetSplitVector(N->getOperand(1), Lo, Hi);
1072 MVT LoMemVT, HiMemVT;
1073 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1075 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1078 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1079 LoMemVT, isVol, Alignment);
1081 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1084 // Increment the pointer to the other half.
1085 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1086 DAG.getIntPtrConstant(IncrementSize));
1089 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
1090 N->getSrcValue(), SVOffset+IncrementSize,
1092 isVol, MinAlign(Alignment, IncrementSize));
1094 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1095 isVol, MinAlign(Alignment, IncrementSize));
1097 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1101 //===----------------------------------------------------------------------===//
1102 // Result Vector Widening
1103 //===----------------------------------------------------------------------===//
1105 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1106 DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG);
1108 SDValue Res = SDValue();
1110 switch (N->getOpcode()) {
1113 cerr << "WidenVectorResult #" << ResNo << ": ";
1114 N->dump(&DAG); cerr << "\n";
1116 assert(0 && "Do not know how to widen the result of this operator!");
1119 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1120 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1121 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1122 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1123 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1124 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1125 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1126 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1127 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1128 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1129 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1130 case ISD::VECTOR_SHUFFLE:
1131 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1134 Res = WidenVecRes_VSETCC(N);
1141 case ISD::FCOPYSIGN:
1158 Res = WidenVecRes_Binary(N);
1164 Res = WidenVecRes_Shift(N);
1168 case ISD::FP_TO_SINT:
1169 case ISD::FP_TO_UINT:
1170 case ISD::SINT_TO_FP:
1171 case ISD::UINT_TO_FP:
1173 case ISD::SIGN_EXTEND:
1174 case ISD::ZERO_EXTEND:
1175 case ISD::ANY_EXTEND:
1176 Res = WidenVecRes_Convert(N);
1187 Res = WidenVecRes_Unary(N);
1191 // If Res is null, the sub-method took care of registering the result.
1193 SetWidenedVector(SDValue(N, ResNo), Res);
1196 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1197 // Binary op widening.
1198 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1199 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1200 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1201 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
1204 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1205 SDValue InOp = N->getOperand(0);
1206 DebugLoc dl = N->getDebugLoc();
1208 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1209 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1211 MVT InVT = InOp.getValueType();
1212 MVT InEltVT = InVT.getVectorElementType();
1213 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1215 unsigned Opcode = N->getOpcode();
1216 unsigned InVTNumElts = InVT.getVectorNumElements();
1218 if (getTypeAction(InVT) == WidenVector) {
1219 InOp = GetWidenedVector(N->getOperand(0));
1220 InVT = InOp.getValueType();
1221 InVTNumElts = InVT.getVectorNumElements();
1222 if (InVTNumElts == WidenNumElts)
1223 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1226 if (TLI.isTypeLegal(InWidenVT)) {
1227 // Because the result and the input are different vector types, widening
1228 // the result could create a legal type but widening the input might make
1229 // it an illegal type that might lead to repeatedly splitting the input
1230 // and then widening it. To avoid this, we widen the input only if
1231 // it results in a legal type.
1232 if (WidenNumElts % InVTNumElts == 0) {
1233 // Widen the input and call convert on the widened input vector.
1234 unsigned NumConcat = WidenNumElts/InVTNumElts;
1235 SmallVector<SDValue, 16> Ops(NumConcat);
1237 SDValue UndefVal = DAG.getUNDEF(InVT);
1238 for (unsigned i = 1; i != NumConcat; ++i)
1240 return DAG.getNode(Opcode, dl, WidenVT,
1241 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1242 &Ops[0], NumConcat));
1245 if (InVTNumElts % WidenNumElts == 0) {
1246 // Extract the input and convert the shorten input vector.
1247 return DAG.getNode(Opcode, dl, WidenVT,
1248 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1249 InOp, DAG.getIntPtrConstant(0)));
1253 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1254 SmallVector<SDValue, 16> Ops(WidenNumElts);
1255 MVT EltVT = WidenVT.getVectorElementType();
1256 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1258 for (i=0; i < MinElts; ++i)
1259 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1260 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1261 DAG.getIntPtrConstant(i)));
1263 SDValue UndefVal = DAG.getUNDEF(EltVT);
1264 for (; i < WidenNumElts; ++i)
1267 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1270 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1271 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1272 SDValue InOp = GetWidenedVector(N->getOperand(0));
1273 SDValue ShOp = N->getOperand(1);
1275 MVT ShVT = ShOp.getValueType();
1276 if (getTypeAction(ShVT) == WidenVector) {
1277 ShOp = GetWidenedVector(ShOp);
1278 ShVT = ShOp.getValueType();
1280 MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
1281 WidenVT.getVectorNumElements());
1282 if (ShVT != ShWidenVT)
1283 ShOp = ModifyToType(ShOp, ShWidenVT);
1285 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1288 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1289 // Unary op widening.
1290 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1291 SDValue InOp = GetWidenedVector(N->getOperand(0));
1292 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1295 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1296 SDValue InOp = N->getOperand(0);
1297 MVT InVT = InOp.getValueType();
1298 MVT VT = N->getValueType(0);
1299 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1300 DebugLoc dl = N->getDebugLoc();
1302 switch (getTypeAction(InVT)) {
1304 assert(false && "Unknown type action!");
1308 case PromoteInteger:
1309 // If the InOp is promoted to the same size, convert it. Otherwise,
1310 // fall out of the switch and widen the promoted input.
1311 InOp = GetPromotedInteger(InOp);
1312 InVT = InOp.getValueType();
1313 if (WidenVT.bitsEq(InVT))
1314 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1319 case ScalarizeVector:
1323 // If the InOp is widened to the same size, convert it. Otherwise, fall
1324 // out of the switch and widen the widened input.
1325 InOp = GetWidenedVector(InOp);
1326 InVT = InOp.getValueType();
1327 if (WidenVT.bitsEq(InVT))
1328 // The input widens to the same size. Convert to the widen value.
1329 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1333 unsigned WidenSize = WidenVT.getSizeInBits();
1334 unsigned InSize = InVT.getSizeInBits();
1335 if (WidenSize % InSize == 0) {
1336 // Determine new input vector type. The new input vector type will use
1337 // the same element type (if its a vector) or use the input type as a
1338 // vector. It is the same size as the type to widen to.
1340 unsigned NewNumElts = WidenSize / InSize;
1341 if (InVT.isVector()) {
1342 MVT InEltVT = InVT.getVectorElementType();
1343 NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
1345 NewInVT = MVT::getVectorVT(InVT, NewNumElts);
1348 if (TLI.isTypeLegal(NewInVT)) {
1349 // Because the result and the input are different vector types, widening
1350 // the result could create a legal type but widening the input might make
1351 // it an illegal type that might lead to repeatedly splitting the input
1352 // and then widening it. To avoid this, we widen the input only if
1353 // it results in a legal type.
1354 SmallVector<SDValue, 16> Ops(NewNumElts);
1355 SDValue UndefVal = DAG.getUNDEF(InVT);
1357 for (unsigned i = 1; i < NewNumElts; ++i)
1361 if (InVT.isVector())
1362 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1363 NewInVT, &Ops[0], NewNumElts);
1365 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1366 NewInVT, &Ops[0], NewNumElts);
1367 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1371 // This should occur rarely. Lower the bit-convert to a store/load
1372 // from the stack. Create the stack frame object. Make sure it is aligned
1373 // for both the source and destination types.
1374 SDValue FIPtr = DAG.CreateStackTemporary(InVT, WidenVT);
1375 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1376 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1378 // Emit a store to the stack slot.
1379 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
1381 // Result is a load from the stack slot.
1382 return DAG.getLoad(WidenVT, dl, Store, FIPtr, SV, 0);
1385 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1386 DebugLoc dl = N->getDebugLoc();
1387 // Build a vector with undefined for the new nodes.
1388 MVT VT = N->getValueType(0);
1389 MVT EltVT = VT.getVectorElementType();
1390 unsigned NumElts = VT.getVectorNumElements();
1392 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1393 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1395 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1396 NewOps.reserve(WidenNumElts);
1397 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1398 NewOps.push_back(DAG.getUNDEF(EltVT));
1400 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1403 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1404 MVT InVT = N->getOperand(0).getValueType();
1405 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1406 DebugLoc dl = N->getDebugLoc();
1407 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1408 unsigned NumOperands = N->getNumOperands();
1410 bool InputWidened = false; // Indicates we need to widen the input.
1411 if (getTypeAction(InVT) != WidenVector) {
1412 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1413 // Add undef vectors to widen to correct length.
1414 unsigned NumConcat = WidenVT.getVectorNumElements() /
1415 InVT.getVectorNumElements();
1416 SDValue UndefVal = DAG.getUNDEF(InVT);
1417 SmallVector<SDValue, 16> Ops(NumConcat);
1418 for (unsigned i=0; i < NumOperands; ++i)
1419 Ops[i] = N->getOperand(i);
1420 for (unsigned i = NumOperands; i != NumConcat; ++i)
1422 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1425 InputWidened = true;
1426 if (WidenVT == TLI.getTypeToTransformTo(InVT)) {
1427 // The inputs and the result are widen to the same value.
1429 for (i=1; i < NumOperands; ++i)
1430 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1433 if (i > NumOperands)
1434 // Everything but the first operand is an UNDEF so just return the
1435 // widened first operand.
1436 return GetWidenedVector(N->getOperand(0));
1438 if (NumOperands == 2) {
1439 // Replace concat of two operands with a shuffle.
1440 SmallVector<int, 16> MaskOps(WidenNumElts);
1441 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1443 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1445 return DAG.getVectorShuffle(WidenVT, dl,
1446 GetWidenedVector(N->getOperand(0)),
1447 GetWidenedVector(N->getOperand(1)),
1453 // Fall back to use extracts and build vector.
1454 MVT EltVT = WidenVT.getVectorElementType();
1455 unsigned NumInElts = InVT.getVectorNumElements();
1456 SmallVector<SDValue, 16> Ops(WidenNumElts);
1458 for (unsigned i=0; i < NumOperands; ++i) {
1459 SDValue InOp = N->getOperand(i);
1461 InOp = GetWidenedVector(InOp);
1462 for (unsigned j=0; j < NumInElts; ++j)
1463 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1464 DAG.getIntPtrConstant(j));
1466 SDValue UndefVal = DAG.getUNDEF(EltVT);
1467 for (; Idx < WidenNumElts; ++Idx)
1468 Ops[Idx] = UndefVal;
1469 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1472 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1473 DebugLoc dl = N->getDebugLoc();
1474 SDValue InOp = N->getOperand(0);
1475 SDValue RndOp = N->getOperand(3);
1476 SDValue SatOp = N->getOperand(4);
1478 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1479 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1481 MVT InVT = InOp.getValueType();
1482 MVT InEltVT = InVT.getVectorElementType();
1483 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1485 SDValue DTyOp = DAG.getValueType(WidenVT);
1486 SDValue STyOp = DAG.getValueType(InWidenVT);
1487 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1489 unsigned InVTNumElts = InVT.getVectorNumElements();
1490 if (getTypeAction(InVT) == WidenVector) {
1491 InOp = GetWidenedVector(InOp);
1492 InVT = InOp.getValueType();
1493 InVTNumElts = InVT.getVectorNumElements();
1494 if (InVTNumElts == WidenNumElts)
1495 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1499 if (TLI.isTypeLegal(InWidenVT)) {
1500 // Because the result and the input are different vector types, widening
1501 // the result could create a legal type but widening the input might make
1502 // it an illegal type that might lead to repeatedly splitting the input
1503 // and then widening it. To avoid this, we widen the input only if
1504 // it results in a legal type.
1505 if (WidenNumElts % InVTNumElts == 0) {
1506 // Widen the input and call convert on the widened input vector.
1507 unsigned NumConcat = WidenNumElts/InVTNumElts;
1508 SmallVector<SDValue, 16> Ops(NumConcat);
1510 SDValue UndefVal = DAG.getUNDEF(InVT);
1511 for (unsigned i = 1; i != NumConcat; ++i) {
1514 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1515 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1519 if (InVTNumElts % WidenNumElts == 0) {
1520 // Extract the input and convert the shorten input vector.
1521 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1522 DAG.getIntPtrConstant(0));
1523 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1528 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1529 SmallVector<SDValue, 16> Ops(WidenNumElts);
1530 MVT EltVT = WidenVT.getVectorElementType();
1531 DTyOp = DAG.getValueType(EltVT);
1532 STyOp = DAG.getValueType(InEltVT);
1534 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1536 for (i=0; i < MinElts; ++i) {
1537 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1538 DAG.getIntPtrConstant(i));
1539 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1543 SDValue UndefVal = DAG.getUNDEF(EltVT);
1544 for (; i < WidenNumElts; ++i)
1547 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1550 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1551 MVT VT = N->getValueType(0);
1552 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1553 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1554 SDValue InOp = N->getOperand(0);
1555 SDValue Idx = N->getOperand(1);
1556 DebugLoc dl = N->getDebugLoc();
1558 if (getTypeAction(InOp.getValueType()) == WidenVector)
1559 InOp = GetWidenedVector(InOp);
1561 MVT InVT = InOp.getValueType();
1563 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1565 unsigned IdxVal = CIdx->getZExtValue();
1566 // Check if we can just return the input vector after widening.
1567 if (IdxVal == 0 && InVT == WidenVT)
1570 // Check if we can extract from the vector.
1571 unsigned InNumElts = InVT.getVectorNumElements();
1572 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1573 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1576 // We could try widening the input to the right length but for now, extract
1577 // the original elements, fill the rest with undefs and build a vector.
1578 SmallVector<SDValue, 16> Ops(WidenNumElts);
1579 MVT EltVT = VT.getVectorElementType();
1580 MVT IdxVT = Idx.getValueType();
1581 unsigned NumElts = VT.getVectorNumElements();
1584 unsigned IdxVal = CIdx->getZExtValue();
1585 for (i=0; i < NumElts; ++i)
1586 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1587 DAG.getConstant(IdxVal+i, IdxVT));
1589 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1590 for (i=1; i < NumElts; ++i) {
1591 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1592 DAG.getConstant(i, IdxVT));
1593 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1597 SDValue UndefVal = DAG.getUNDEF(EltVT);
1598 for (; i < WidenNumElts; ++i)
1600 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1603 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1604 SDValue InOp = GetWidenedVector(N->getOperand(0));
1605 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1606 InOp.getValueType(), InOp,
1607 N->getOperand(1), N->getOperand(2));
1610 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1611 LoadSDNode *LD = cast<LoadSDNode>(N);
1612 MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1613 MVT LdVT = LD->getMemoryVT();
1614 DebugLoc dl = N->getDebugLoc();
1615 assert(LdVT.isVector() && WidenVT.isVector());
1618 SDValue Chain = LD->getChain();
1619 SDValue BasePtr = LD->getBasePtr();
1620 int SVOffset = LD->getSrcValueOffset();
1621 unsigned Align = LD->getAlignment();
1622 bool isVolatile = LD->isVolatile();
1623 const Value *SV = LD->getSrcValue();
1624 ISD::LoadExtType ExtType = LD->getExtensionType();
1627 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1628 if (ExtType != ISD::NON_EXTLOAD) {
1629 // For extension loads, we can not play the tricks of chopping legal
1630 // vector types and bit cast it to the right type. Instead, we unroll
1631 // the load and build a vector.
1632 MVT EltVT = WidenVT.getVectorElementType();
1633 MVT LdEltVT = LdVT.getVectorElementType();
1634 unsigned NumElts = LdVT.getVectorNumElements();
1636 // Load each element and widen
1637 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1638 SmallVector<SDValue, 16> Ops(WidenNumElts);
1639 unsigned Increment = LdEltVT.getSizeInBits() / 8;
1640 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
1641 LdEltVT, isVolatile, Align);
1642 LdChain.push_back(Ops[0].getValue(1));
1643 unsigned i = 0, Offset = Increment;
1644 for (i=1; i < NumElts; ++i, Offset += Increment) {
1645 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1646 BasePtr, DAG.getIntPtrConstant(Offset));
1647 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
1648 SVOffset + Offset, LdEltVT, isVolatile, Align);
1649 LdChain.push_back(Ops[i].getValue(1));
1652 // Fill the rest with undefs
1653 SDValue UndefVal = DAG.getUNDEF(EltVT);
1654 for (; i != WidenNumElts; ++i)
1657 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
1659 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
1660 unsigned int LdWidth = LdVT.getSizeInBits();
1661 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
1662 Align, isVolatile, LdWidth, WidenVT, dl);
1665 // If we generate a single load, we can use that for the chain. Otherwise,
1666 // build a factor node to remember the multiple loads are independent and
1669 if (LdChain.size() == 1)
1670 NewChain = LdChain[0];
1672 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
1675 // Modified the chain - switch anything that used the old chain to use
1677 ReplaceValueWith(SDValue(N, 1), Chain);
1682 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1683 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1684 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1685 WidenVT, N->getOperand(0));
1688 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1689 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1690 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1692 SDValue Cond1 = N->getOperand(0);
1693 MVT CondVT = Cond1.getValueType();
1694 if (CondVT.isVector()) {
1695 MVT CondEltVT = CondVT.getVectorElementType();
1696 MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
1697 if (getTypeAction(CondVT) == WidenVector)
1698 Cond1 = GetWidenedVector(Cond1);
1700 if (Cond1.getValueType() != CondWidenVT)
1701 Cond1 = ModifyToType(Cond1, CondWidenVT);
1704 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1705 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1706 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1707 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1708 WidenVT, Cond1, InOp1, InOp2);
1711 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1712 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1713 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1714 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1715 InOp1.getValueType(), N->getOperand(0),
1716 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1719 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1720 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1721 return DAG.getUNDEF(WidenVT);
1724 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1725 MVT VT = N->getValueType(0);
1726 DebugLoc dl = N->getDebugLoc();
1728 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1729 unsigned NumElts = VT.getVectorNumElements();
1730 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1732 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1733 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1735 // Adjust mask based on new input vector length.
1736 SmallVector<int, 16> NewMask;
1737 for (unsigned i = 0; i != NumElts; ++i) {
1738 int Idx = N->getMaskElt(i);
1739 if (Idx < (int)NumElts)
1740 NewMask.push_back(Idx);
1742 NewMask.push_back(Idx - NumElts + WidenNumElts);
1744 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1745 NewMask.push_back(-1);
1746 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1749 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1750 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1751 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1753 SDValue InOp1 = N->getOperand(0);
1754 MVT InVT = InOp1.getValueType();
1755 assert(InVT.isVector() && "can not widen non vector type");
1756 MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
1757 InOp1 = GetWidenedVector(InOp1);
1758 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1760 // Assume that the input and output will be widen appropriately. If not,
1761 // we will have to unroll it at some point.
1762 assert(InOp1.getValueType() == WidenInVT &&
1763 InOp2.getValueType() == WidenInVT &&
1764 "Input not widened to expected type!");
1765 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1766 WidenVT, InOp1, InOp2, N->getOperand(2));
1770 //===----------------------------------------------------------------------===//
1771 // Widen Vector Operand
1772 //===----------------------------------------------------------------------===//
1773 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1774 DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG);
1776 SDValue Res = SDValue();
1778 switch (N->getOpcode()) {
1781 cerr << "WidenVectorOperand op #" << ResNo << ": ";
1782 N->dump(&DAG); cerr << "\n";
1784 assert(0 && "Do not know how to widen this operator's operand!");
1787 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1788 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1789 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1790 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1793 case ISD::FP_TO_SINT:
1794 case ISD::FP_TO_UINT:
1795 case ISD::SINT_TO_FP:
1796 case ISD::UINT_TO_FP:
1798 case ISD::SIGN_EXTEND:
1799 case ISD::ZERO_EXTEND:
1800 case ISD::ANY_EXTEND:
1801 Res = WidenVecOp_Convert(N);
1805 // If Res is null, the sub-method took care of registering the result.
1806 if (!Res.getNode()) return false;
1808 // If the result is N, the sub-method updated N in place. Tell the legalizer
1810 if (Res.getNode() == N)
1814 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1815 "Invalid operand expansion");
1817 ReplaceValueWith(SDValue(N, 0), Res);
1821 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1822 // Since the result is legal and the input is illegal, it is unlikely
1823 // that we can fix the input to a legal type so unroll the convert
1824 // into some scalar code and create a nasty build vector.
1825 MVT VT = N->getValueType(0);
1826 MVT EltVT = VT.getVectorElementType();
1827 DebugLoc dl = N->getDebugLoc();
1828 unsigned NumElts = VT.getVectorNumElements();
1829 SDValue InOp = N->getOperand(0);
1830 if (getTypeAction(InOp.getValueType()) == WidenVector)
1831 InOp = GetWidenedVector(InOp);
1832 MVT InVT = InOp.getValueType();
1833 MVT InEltVT = InVT.getVectorElementType();
1835 unsigned Opcode = N->getOpcode();
1836 SmallVector<SDValue, 16> Ops(NumElts);
1837 for (unsigned i=0; i < NumElts; ++i)
1838 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1839 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1840 DAG.getIntPtrConstant(i)));
1842 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1845 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
1846 MVT VT = N->getValueType(0);
1847 SDValue InOp = GetWidenedVector(N->getOperand(0));
1848 MVT InWidenVT = InOp.getValueType();
1849 DebugLoc dl = N->getDebugLoc();
1851 // Check if we can convert between two legal vector types and extract.
1852 unsigned InWidenSize = InWidenVT.getSizeInBits();
1853 unsigned Size = VT.getSizeInBits();
1854 if (InWidenSize % Size == 0 && !VT.isVector()) {
1855 unsigned NewNumElts = InWidenSize / Size;
1856 MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
1857 if (TLI.isTypeLegal(NewVT)) {
1858 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
1859 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
1860 DAG.getIntPtrConstant(0));
1864 // Lower the bit-convert to a store/load from the stack. Create the stack
1865 // frame object. Make sure it is aligned for both the source and destination
1867 SDValue FIPtr = DAG.CreateStackTemporary(InWidenVT, VT);
1868 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1869 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1871 // Emit a store to the stack slot.
1872 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
1874 // Result is a load from the stack slot.
1875 return DAG.getLoad(VT, dl, Store, FIPtr, SV, 0);
1878 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1879 // If the input vector is not legal, it is likely that we will not find a
1880 // legal vector of the same size. Replace the concatenate vector with a
1881 // nasty build vector.
1882 MVT VT = N->getValueType(0);
1883 MVT EltVT = VT.getVectorElementType();
1884 DebugLoc dl = N->getDebugLoc();
1885 unsigned NumElts = VT.getVectorNumElements();
1886 SmallVector<SDValue, 16> Ops(NumElts);
1888 MVT InVT = N->getOperand(0).getValueType();
1889 unsigned NumInElts = InVT.getVectorNumElements();
1892 unsigned NumOperands = N->getNumOperands();
1893 for (unsigned i=0; i < NumOperands; ++i) {
1894 SDValue InOp = N->getOperand(i);
1895 if (getTypeAction(InOp.getValueType()) == WidenVector)
1896 InOp = GetWidenedVector(InOp);
1897 for (unsigned j=0; j < NumInElts; ++j)
1898 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1899 DAG.getIntPtrConstant(j));
1901 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1904 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1905 SDValue InOp = GetWidenedVector(N->getOperand(0));
1906 MVT EltVT = InOp.getValueType().getVectorElementType();
1907 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
1908 EltVT, InOp, N->getOperand(1));
1911 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1912 // We have to widen the value but we want only to store the original
1914 StoreSDNode *ST = cast<StoreSDNode>(N);
1915 SDValue Chain = ST->getChain();
1916 SDValue BasePtr = ST->getBasePtr();
1917 const Value *SV = ST->getSrcValue();
1918 int SVOffset = ST->getSrcValueOffset();
1919 unsigned Align = ST->getAlignment();
1920 bool isVolatile = ST->isVolatile();
1921 SDValue ValOp = GetWidenedVector(ST->getValue());
1922 DebugLoc dl = N->getDebugLoc();
1924 MVT StVT = ST->getMemoryVT();
1925 MVT ValVT = ValOp.getValueType();
1926 // It must be true that we the widen vector type is bigger than where
1927 // we need to store.
1928 assert(StVT.isVector() && ValOp.getValueType().isVector());
1929 assert(StVT.bitsLT(ValOp.getValueType()));
1931 SmallVector<SDValue, 16> StChain;
1932 if (ST->isTruncatingStore()) {
1933 // For truncating stores, we can not play the tricks of chopping legal
1934 // vector types and bit cast it to the right type. Instead, we unroll
1936 MVT StEltVT = StVT.getVectorElementType();
1937 MVT ValEltVT = ValVT.getVectorElementType();
1938 unsigned Increment = ValEltVT.getSizeInBits() / 8;
1939 unsigned NumElts = StVT.getVectorNumElements();
1940 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1941 DAG.getIntPtrConstant(0));
1942 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
1944 isVolatile, Align));
1945 unsigned Offset = Increment;
1946 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
1947 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1948 BasePtr, DAG.getIntPtrConstant(Offset));
1949 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1950 DAG.getIntPtrConstant(0));
1951 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
1952 SVOffset + Offset, StEltVT,
1953 isVolatile, MinAlign(Align, Offset)));
1957 assert(StVT.getVectorElementType() == ValVT.getVectorElementType());
1959 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset,
1960 Align, isVolatile, ValOp, StVT.getSizeInBits(), dl);
1962 if (StChain.size() == 1)
1965 return DAG.getNode(ISD::TokenFactor, dl,
1966 MVT::Other,&StChain[0],StChain.size());
1969 //===----------------------------------------------------------------------===//
1970 // Vector Widening Utilities
1971 //===----------------------------------------------------------------------===//
1974 // Utility function to find a vector type and its associated element
1975 // type from a preferred width and whose vector type must be the same size
1977 // TLI: Target lowering used to determine legal types.
1978 // Width: Preferred width to store.
1979 // VecVT: Vector value type whose size we must match.
1980 // Returns NewVecVT and NewEltVT - the vector type and its associated
1982 static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
1984 MVT& NewEltVT, MVT& NewVecVT) {
1985 unsigned EltWidth = Width + 1;
1986 if (TLI.isTypeLegal(VecVT)) {
1987 // We start with the preferred with, making it a power of 2 and find a
1988 // legal vector type of that width. If not, we reduce it by another of 2.
1989 // For incoming type is legal, this process will end as a vector of the
1990 // smallest loadable type should always be legal.
1992 assert(EltWidth > 0);
1993 EltWidth = 1 << Log2_32(EltWidth - 1);
1994 NewEltVT = MVT::getIntegerVT(EltWidth);
1995 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1996 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1997 } while (!TLI.isTypeLegal(NewVecVT) ||
1998 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
2000 // The incoming vector type is illegal and is the result of widening
2001 // a vector to a power of 2. In this case, we will use the preferred
2002 // with as long as it is a multiple of the incoming vector length.
2003 // The legalization process will eventually make this into a legal type
2004 // and remove the illegal bit converts (which would turn to stack converts
2005 // if they are allow to exist).
2007 assert(EltWidth > 0);
2008 EltWidth = 1 << Log2_32(EltWidth - 1);
2009 NewEltVT = MVT::getIntegerVT(EltWidth);
2010 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
2011 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
2012 } while (!TLI.isTypeLegal(NewEltVT) ||
2013 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
2017 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
2027 // The strategy assumes that we can efficiently load powers of two widths.
2028 // The routines chops the vector into the largest power of 2 load and
2029 // can be inserted into a legal vector and then cast the result into the
2030 // vector type we want. This avoids unnecessary stack converts.
2032 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
2033 // the load is nonvolatile, we an use a wider load for the value.
2035 // Find the vector type that can load from.
2036 MVT NewEltVT, NewVecVT;
2037 unsigned NewEltVTWidth;
2038 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2039 NewEltVTWidth = NewEltVT.getSizeInBits();
2041 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset,
2042 isVolatile, Alignment);
2043 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2044 LdChain.push_back(LdOp.getValue(1));
2046 // Check if we can load the element with one instruction
2047 if (LdWidth == NewEltVTWidth) {
2048 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2052 LdWidth -= NewEltVTWidth;
2053 unsigned Offset = 0;
2055 while (LdWidth > 0) {
2056 unsigned Increment = NewEltVTWidth / 8;
2057 Offset += Increment;
2058 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2059 DAG.getIntPtrConstant(Increment));
2061 if (LdWidth < NewEltVTWidth) {
2062 // Our current type we are using is too large, use a smaller size by
2063 // using a smaller power of 2
2064 unsigned oNewEltVTWidth = NewEltVTWidth;
2065 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2066 NewEltVTWidth = NewEltVT.getSizeInBits();
2067 // Readjust position and vector position based on new load type
2068 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2069 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2072 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV,
2073 SVOffset+Offset, isVolatile,
2074 MinAlign(Alignment, Offset));
2075 LdChain.push_back(LdOp.getValue(1));
2076 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOp,
2077 DAG.getIntPtrConstant(Idx++));
2079 LdWidth -= NewEltVTWidth;
2082 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2085 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2095 // Breaks the stores into a series of power of 2 width stores. For any
2096 // width, we convert the vector to the vector of element size that we
2097 // want to store. This avoids requiring a stack convert.
2099 // Find a width of the element type we can store with
2100 MVT WidenVT = ValOp.getValueType();
2101 MVT NewEltVT, NewVecVT;
2103 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2104 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
2106 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2107 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2108 DAG.getIntPtrConstant(0));
2109 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
2110 isVolatile, Alignment);
2111 StChain.push_back(StOp);
2113 // Check if we are done
2114 if (StWidth == NewEltVTWidth) {
2119 StWidth -= NewEltVTWidth;
2120 unsigned Offset = 0;
2122 while (StWidth > 0) {
2123 unsigned Increment = NewEltVTWidth / 8;
2124 Offset += Increment;
2125 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2126 DAG.getIntPtrConstant(Increment));
2128 if (StWidth < NewEltVTWidth) {
2129 // Our current type we are using is too large, use a smaller size by
2130 // using a smaller power of 2
2131 unsigned oNewEltVTWidth = NewEltVTWidth;
2132 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2133 NewEltVTWidth = NewEltVT.getSizeInBits();
2134 // Readjust position and vector position based on new load type
2135 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2136 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2139 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2140 DAG.getIntPtrConstant(Idx++));
2141 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2142 SVOffset + Offset, isVolatile,
2143 MinAlign(Alignment, Offset)));
2144 StWidth -= NewEltVTWidth;
2148 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2149 /// input vector must have the same element type as NVT.
2150 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
2151 // Note that InOp might have been widened so it might already have
2152 // the right width or it might need be narrowed.
2153 MVT InVT = InOp.getValueType();
2154 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2155 "input and widen element type must match");
2156 DebugLoc dl = InOp.getDebugLoc();
2158 // Check if InOp already has the right width.
2162 unsigned InNumElts = InVT.getVectorNumElements();
2163 unsigned WidenNumElts = NVT.getVectorNumElements();
2164 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2165 unsigned NumConcat = WidenNumElts / InNumElts;
2166 SmallVector<SDValue, 16> Ops(NumConcat);
2167 SDValue UndefVal = DAG.getUNDEF(InVT);
2169 for (unsigned i = 1; i != NumConcat; ++i)
2172 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2175 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2176 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2177 DAG.getIntPtrConstant(0));
2179 // Fall back to extract and build.
2180 SmallVector<SDValue, 16> Ops(WidenNumElts);
2181 MVT EltVT = NVT.getVectorElementType();
2182 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2184 for (Idx = 0; Idx < MinNumElts; ++Idx)
2185 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2186 DAG.getIntPtrConstant(Idx));
2188 SDValue UndefVal = DAG.getUNDEF(EltVT);
2189 for ( ; Idx < WidenNumElts; ++Idx)
2190 Ops[Idx] = UndefVal;
2191 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);