1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDValue R = SDValue();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
46 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
47 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
48 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
49 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
50 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
51 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
52 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
53 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
54 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
73 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
90 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
93 // If R is null, the sub-method took care of registering the result.
95 SetScalarizedVector(SDValue(N, ResNo), R);
98 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
99 SDValue LHS = GetScalarizedVector(N->getOperand(0));
100 SDValue RHS = GetScalarizedVector(N->getOperand(1));
101 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
104 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
105 MVT NewVT = N->getValueType(0).getVectorElementType();
106 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
109 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
110 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
111 N->getValueType(0).getVectorElementType(),
112 N->getOperand(0), N->getOperand(1));
115 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
116 SDValue Op = GetScalarizedVector(N->getOperand(0));
117 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
120 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
121 // The value to insert may have a wider type than the vector element type,
122 // so be sure to truncate it to the element type if necessary.
123 SDValue Op = N->getOperand(1);
124 MVT EltVT = N->getValueType(0).getVectorElementType();
125 if (Op.getValueType() != EltVT)
126 // FIXME: Can this happen for floating point types?
127 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
131 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
132 assert(N->isUnindexed() && "Indexed vector load?");
134 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
135 N->getValueType(0).getVectorElementType(),
136 N->getChain(), N->getBasePtr(),
137 DAG.getNode(ISD::UNDEF,
138 N->getBasePtr().getValueType()),
139 N->getSrcValue(), N->getSrcValueOffset(),
140 N->getMemoryVT().getVectorElementType(),
141 N->isVolatile(), N->getAlignment());
143 // Legalized the chain result - switch anything that used the old chain to
145 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
150 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
151 MVT DestVT = N->getValueType(0).getVectorElementType();
152 SDValue Op = GetScalarizedVector(N->getOperand(0));
153 return DAG.getNode(N->getOpcode(), DestVT, Op);
156 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
157 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
161 SDValue LHS = GetScalarizedVector(N->getOperand(1));
162 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
163 GetScalarizedVector(N->getOperand(2)));
166 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
167 SDValue LHS = GetScalarizedVector(N->getOperand(2));
168 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
169 N->getOperand(0), N->getOperand(1),
170 LHS, GetScalarizedVector(N->getOperand(3)),
174 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
175 // Figure out if the scalar is the LHS or RHS and return it.
176 SDValue Arg = N->getOperand(2).getOperand(0);
177 if (Arg.getOpcode() == ISD::UNDEF)
178 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
179 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
180 return GetScalarizedVector(N->getOperand(Op));
183 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
184 MVT NewVT = N->getValueType(0).getVectorElementType();
185 SDValue LHS = GetScalarizedVector(N->getOperand(0));
186 SDValue RHS = GetScalarizedVector(N->getOperand(1));
187 LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
190 DAG.getNode(ISD::SELECT, NewVT, LHS,
191 DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
193 DAG.getConstant(0ULL, NewVT));
197 //===----------------------------------------------------------------------===//
198 // Operand Vector Scalarization <1 x ty> -> ty.
199 //===----------------------------------------------------------------------===//
201 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
202 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
204 SDValue Res = SDValue();
206 if (Res.getNode() == 0) {
207 switch (N->getOpcode()) {
210 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
211 N->dump(&DAG); cerr << "\n";
213 assert(0 && "Do not know how to scalarize this operator's operand!");
216 case ISD::BIT_CONVERT:
217 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
219 case ISD::CONCAT_VECTORS:
220 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
222 case ISD::EXTRACT_VECTOR_ELT:
223 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
226 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
230 // If the result is null, the sub-method took care of registering results etc.
231 if (!Res.getNode()) return false;
233 // If the result is N, the sub-method updated N in place. Check to see if any
234 // operands are new, and if so, mark them.
235 if (Res.getNode() == N) {
236 // Mark N as new and remark N and its operands. This allows us to correctly
237 // revisit N if it needs another step of promotion and allows us to visit
238 // any new operands to N.
243 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
244 "Invalid operand expansion");
246 ReplaceValueWith(SDValue(N, 0), Res);
250 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
251 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
252 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
253 SDValue Elt = GetScalarizedVector(N->getOperand(0));
254 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
257 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
258 /// use a BUILD_VECTOR instead.
259 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
260 SmallVector<SDValue, 8> Ops(N->getNumOperands());
261 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
262 Ops[i] = GetScalarizedVector(N->getOperand(i));
263 return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
264 &Ops[0], Ops.size());
267 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
268 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
270 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
271 return GetScalarizedVector(N->getOperand(0));
274 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
275 /// scalarized, it must be <1 x ty>. Just store the element.
276 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
277 assert(N->isUnindexed() && "Indexed store of one-element vector?");
278 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
280 if (N->isTruncatingStore())
281 return DAG.getTruncStore(N->getChain(),
282 GetScalarizedVector(N->getOperand(1)),
284 N->getSrcValue(), N->getSrcValueOffset(),
285 N->getMemoryVT().getVectorElementType(),
286 N->isVolatile(), N->getAlignment());
288 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
289 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
290 N->isVolatile(), N->getAlignment());
294 //===----------------------------------------------------------------------===//
295 // Result Vector Splitting
296 //===----------------------------------------------------------------------===//
298 /// SplitVectorResult - This method is called when the specified result of the
299 /// specified node is found to need vector splitting. At this point, the node
300 /// may also have invalid operands or may have other results that need
301 /// legalization, we just know that (at least) one result needs vector
303 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
304 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
307 switch (N->getOpcode()) {
310 cerr << "SplitVectorResult #" << ResNo << ": ";
311 N->dump(&DAG); cerr << "\n";
313 assert(0 && "Do not know how to split the result of this operator!");
316 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
317 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
318 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
319 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
321 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
322 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
323 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
324 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
325 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
326 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
327 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
328 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
342 case ISD::FNEARBYINT:
343 case ISD::FP_TO_SINT:
344 case ISD::FP_TO_UINT:
345 case ISD::SINT_TO_FP:
347 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
364 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
367 // If Lo/Hi is null, the sub-method took care of registering results etc.
369 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
372 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
374 SDValue LHSLo, LHSHi;
375 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
376 SDValue RHSLo, RHSHi;
377 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
379 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
380 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
383 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
385 // We know the result is a vector. The input may be either a vector or a
388 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
390 SDValue InOp = N->getOperand(0);
391 MVT InVT = InOp.getValueType();
393 // Handle some special cases efficiently.
394 switch (getTypeAction(InVT)) {
396 assert(false && "Unknown type action!");
400 case ScalarizeVector:
404 // A scalar to vector conversion, where the scalar needs expansion.
405 // If the vector is being split in two then we can just convert the
408 GetExpandedOp(InOp, Lo, Hi);
409 if (TLI.isBigEndian())
411 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
412 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
417 // If the input is a vector that needs to be split, convert each split
418 // piece of the input now.
419 GetSplitVector(InOp, Lo, Hi);
420 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
421 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
425 // In the general case, convert the input to an integer and split it by hand.
426 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
427 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
428 if (TLI.isBigEndian())
429 std::swap(LoIntVT, HiIntVT);
431 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
433 if (TLI.isBigEndian())
435 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
436 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
439 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
442 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
443 unsigned LoNumElts = LoVT.getVectorNumElements();
444 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
445 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
447 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
448 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
451 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
453 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
454 unsigned NumSubvectors = N->getNumOperands() / 2;
455 if (NumSubvectors == 1) {
456 Lo = N->getOperand(0);
457 Hi = N->getOperand(1);
462 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
464 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
465 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
467 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
468 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
471 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
473 GetSplitVector(N->getOperand(0), Lo, Hi);
474 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
475 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
478 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
480 SDValue Vec = N->getOperand(0);
481 SDValue Elt = N->getOperand(1);
482 SDValue Idx = N->getOperand(2);
483 GetSplitVector(Vec, Lo, Hi);
485 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
486 unsigned IdxVal = CIdx->getZExtValue();
487 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
488 if (IdxVal < LoNumElts)
489 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
491 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
492 DAG.getIntPtrConstant(IdxVal - LoNumElts));
496 // Spill the vector to the stack.
497 MVT VecVT = Vec.getValueType();
498 MVT EltVT = VecVT.getVectorElementType();
499 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
500 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
502 // Store the new element. This may be larger than the vector element type,
503 // so use a truncating store.
504 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
505 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
507 // Reload the vector from the stack.
508 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
511 SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
514 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
516 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
518 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
520 ISD::LoadExtType ExtType = LD->getExtensionType();
521 SDValue Ch = LD->getChain();
522 SDValue Ptr = LD->getBasePtr();
523 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
524 const Value *SV = LD->getSrcValue();
525 int SVOffset = LD->getSrcValueOffset();
526 MVT MemoryVT = LD->getMemoryVT();
527 unsigned Alignment = LD->getAlignment();
528 bool isVolatile = LD->isVolatile();
530 MVT LoMemVT, HiMemVT;
531 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
533 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
534 SV, SVOffset, LoMemVT, isVolatile, Alignment);
536 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
537 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
538 DAG.getIntPtrConstant(IncrementSize));
539 SVOffset += IncrementSize;
540 Alignment = MinAlign(Alignment, IncrementSize);
541 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
542 SV, SVOffset, HiMemVT, isVolatile, Alignment);
544 // Build a factor node to remember that this load is independent of the
546 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
549 // Legalized the chain result - switch anything that used the old chain to
551 ReplaceValueWith(SDValue(LD, 1), Ch);
554 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
556 // Get the dest types - they may not match the input types, e.g. int_to_fp.
558 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
561 MVT InVT = N->getOperand(0).getValueType();
562 switch (getTypeAction(InVT)) {
563 default: assert(0 && "Unexpected type action!");
565 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
566 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
567 LoVT.getVectorNumElements());
568 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
569 DAG.getIntPtrConstant(0));
570 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
571 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
575 GetSplitVector(N->getOperand(0), Lo, Hi);
579 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
580 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
583 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
585 // Build the low part.
586 SDValue Mask = N->getOperand(2);
587 SmallVector<SDValue, 16> Ops;
589 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
590 MVT EltVT = LoVT.getVectorElementType();
591 unsigned LoNumElts = LoVT.getVectorNumElements();
592 unsigned NumElements = Mask.getNumOperands();
594 // Insert all of the elements from the input that are needed. We use
595 // buildvector of extractelement here because the input vectors will have
596 // to be legalized, so this makes the code simpler.
597 for (unsigned i = 0; i != LoNumElts; ++i) {
598 SDValue Arg = Mask.getOperand(i);
599 if (Arg.getOpcode() == ISD::UNDEF) {
600 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
602 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
603 SDValue InVec = N->getOperand(0);
604 if (Idx >= NumElements) {
605 InVec = N->getOperand(1);
608 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
609 DAG.getIntPtrConstant(Idx)));
612 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
615 for (unsigned i = LoNumElts; i != NumElements; ++i) {
616 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
617 SDValue InVec = N->getOperand(0);
618 if (Idx >= NumElements) {
619 InVec = N->getOperand(1);
622 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
623 DAG.getIntPtrConstant(Idx)));
625 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
628 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
631 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
633 SDValue LL, LH, RL, RH;
634 GetSplitVector(N->getOperand(0), LL, LH);
635 GetSplitVector(N->getOperand(1), RL, RH);
637 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
638 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
642 //===----------------------------------------------------------------------===//
643 // Operand Vector Splitting
644 //===----------------------------------------------------------------------===//
646 /// SplitVectorOperand - This method is called when the specified operand of the
647 /// specified node is found to need vector splitting. At this point, all of the
648 /// result types of the node are known to be legal, but other operands of the
649 /// node may need legalization as well as the specified one.
650 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
651 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
652 SDValue Res = SDValue();
654 if (Res.getNode() == 0) {
655 switch (N->getOpcode()) {
658 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
659 N->dump(&DAG); cerr << "\n";
661 assert(0 && "Do not know how to split this operator's operand!");
664 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
665 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
666 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
667 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
669 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
674 case ISD::FP_TO_SINT:
675 case ISD::FP_TO_UINT:
676 case ISD::SINT_TO_FP:
678 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
682 // If the result is null, the sub-method took care of registering results etc.
683 if (!Res.getNode()) return false;
685 // If the result is N, the sub-method updated N in place. Check to see if any
686 // operands are new, and if so, mark them.
687 if (Res.getNode() == N) {
688 // Mark N as new and remark N and its operands. This allows us to correctly
689 // revisit N if it needs another step of promotion and allows us to visit
690 // any new operands to N.
695 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
696 "Invalid operand expansion");
698 ReplaceValueWith(SDValue(N, 0), Res);
702 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
703 // The result has a legal vector type, but the input needs splitting.
704 MVT ResVT = N->getValueType(0);
706 GetSplitVector(N->getOperand(0), Lo, Hi);
707 assert(Lo.getValueType() == Hi.getValueType() &&
708 "Returns legal non-power-of-two vector type?");
709 MVT InVT = Lo.getValueType();
711 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
712 InVT.getVectorNumElements());
714 Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
715 Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
717 return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
720 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
721 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
722 // end up being split all the way down to individual components. Convert the
723 // split pieces into integers and reassemble.
725 GetSplitVector(N->getOperand(0), Lo, Hi);
726 Lo = BitConvertToInteger(Lo);
727 Hi = BitConvertToInteger(Hi);
729 if (TLI.isBigEndian())
732 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
733 JoinIntegers(Lo, Hi));
736 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
737 // We know that the extracted result type is legal. For now, assume the index
739 MVT SubVT = N->getValueType(0);
740 SDValue Idx = N->getOperand(1);
742 GetSplitVector(N->getOperand(0), Lo, Hi);
744 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
745 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
747 if (IdxVal < LoElts) {
748 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
749 "Extracted subvector crosses vector split!");
750 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
752 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
753 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
757 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
758 SDValue Vec = N->getOperand(0);
759 SDValue Idx = N->getOperand(1);
760 MVT VecVT = Vec.getValueType();
762 if (isa<ConstantSDNode>(Idx)) {
763 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
764 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
767 GetSplitVector(Vec, Lo, Hi);
769 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
772 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
774 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
775 DAG.getConstant(IdxVal - LoElts,
776 Idx.getValueType()));
779 // Store the vector to the stack.
780 MVT EltVT = VecVT.getVectorElementType();
781 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
782 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
784 // Load back the required element.
785 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
786 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
789 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
790 assert(N->isUnindexed() && "Indexed store of vector?");
791 assert(OpNo == 1 && "Can only split the stored value");
793 bool isTruncating = N->isTruncatingStore();
794 SDValue Ch = N->getChain();
795 SDValue Ptr = N->getBasePtr();
796 int SVOffset = N->getSrcValueOffset();
797 MVT MemoryVT = N->getMemoryVT();
798 unsigned Alignment = N->getAlignment();
799 bool isVol = N->isVolatile();
801 GetSplitVector(N->getOperand(1), Lo, Hi);
803 MVT LoMemVT, HiMemVT;
804 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
806 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
809 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
810 LoMemVT, isVol, Alignment);
812 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
815 // Increment the pointer to the other half.
816 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
817 DAG.getIntPtrConstant(IncrementSize));
820 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
821 N->getSrcValue(), SVOffset+IncrementSize,
823 isVol, MinAlign(Alignment, IncrementSize));
825 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
826 isVol, MinAlign(Alignment, IncrementSize));
828 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
831 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
832 assert(OpNo == 2 && "Shuffle source type differs from result type?");
833 SDValue Mask = N->getOperand(2);
834 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
835 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
836 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
838 // Look for a legal vector type to place the mask values in.
839 // Note that there may not be *any* legal vector-of-integer
840 // type for which the element type is legal!
841 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
842 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
843 // Integer values types are consecutively numbered. Exploit this.
844 EltVT = MVT::SimpleValueType(EltVT + 1)) {
846 // Is the element type big enough to hold the values?
847 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
851 // Is the vector type legal?
852 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
853 if (!isTypeLegal(VecVT))
857 // If the element type is not legal, find a larger legal type to use for
858 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
859 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
860 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
861 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
862 // Integer values types are consecutively numbered. Exploit this.
863 OpVT = MVT::SimpleValueType(OpVT + 1)) {
864 if (!isTypeLegal(OpVT))
867 // Success! Rebuild the vector using the legal types.
868 SmallVector<SDValue, 16> Ops(MaskLength);
869 for (unsigned i = 0; i < MaskLength; ++i) {
870 SDValue Arg = Mask.getOperand(i);
871 if (Arg.getOpcode() == ISD::UNDEF) {
872 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
874 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
875 Ops[i] = DAG.getConstant(Idx, OpVT);
878 return DAG.UpdateNodeOperands(SDValue(N,0),
879 N->getOperand(0), N->getOperand(1),
880 DAG.getNode(ISD::BUILD_VECTOR,
881 VecVT, &Ops[0], Ops.size()));
884 // Continuing is pointless - failure is certain.
887 assert(false && "Failed to find an appropriate mask type!");
888 return SDValue(N, 0);