1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDValue R = SDValue();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
46 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
47 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
48 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
49 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
50 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
51 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
52 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
65 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
82 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
85 // If R is null, the sub-method took care of registering the result.
87 SetScalarizedVector(SDValue(N, ResNo), R);
90 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
91 SDValue LHS = GetScalarizedVector(N->getOperand(0));
92 SDValue RHS = GetScalarizedVector(N->getOperand(1));
93 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
96 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
97 MVT NewVT = N->getValueType(0).getVectorElementType();
98 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
101 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
102 SDValue Op = GetScalarizedVector(N->getOperand(0));
103 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
106 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
107 // The value to insert may have a wider type than the vector element type,
108 // so be sure to truncate it to the element type if necessary.
109 SDValue Op = N->getOperand(1);
110 MVT EltVT = N->getValueType(0).getVectorElementType();
111 if (Op.getValueType() != EltVT)
112 // FIXME: Can this happen for floating point types?
113 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
117 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
118 assert(N->isUnindexed() && "Indexed vector load?");
120 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
121 N->getValueType(0).getVectorElementType(),
122 N->getChain(), N->getBasePtr(),
123 DAG.getNode(ISD::UNDEF,
124 N->getBasePtr().getValueType()),
125 N->getSrcValue(), N->getSrcValueOffset(),
126 N->getMemoryVT().getVectorElementType(),
127 N->isVolatile(), N->getAlignment());
129 // Legalized the chain result - switch anything that used the old chain to
131 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
135 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
136 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
137 MVT DestVT = TLI.getTypeToTransformTo(N->getValueType(0));
138 SDValue Op = GetScalarizedVector(N->getOperand(0));
139 return DAG.getNode(N->getOpcode(), DestVT, Op);
142 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
143 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
146 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
147 SDValue LHS = GetScalarizedVector(N->getOperand(1));
148 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
149 GetScalarizedVector(N->getOperand(2)));
152 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
153 // Figure out if the scalar is the LHS or RHS and return it.
154 SDValue EltNum = N->getOperand(2).getOperand(0);
155 unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0;
156 return GetScalarizedVector(N->getOperand(Op));
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
160 MVT NewVT = N->getValueType(0).getVectorElementType();
161 SDValue LHS = GetScalarizedVector(N->getOperand(0));
162 SDValue RHS = GetScalarizedVector(N->getOperand(1));
163 LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
166 DAG.getNode(ISD::SELECT, NewVT, LHS,
167 DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
169 DAG.getConstant(0ULL, NewVT));
173 //===----------------------------------------------------------------------===//
174 // Operand Vector Scalarization <1 x ty> -> ty.
175 //===----------------------------------------------------------------------===//
177 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
178 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
180 SDValue Res = SDValue();
183 switch (N->getOpcode()) {
186 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
187 N->dump(&DAG); cerr << "\n";
189 assert(0 && "Do not know how to scalarize this operator's operand!");
192 case ISD::BIT_CONVERT:
193 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
195 case ISD::EXTRACT_VECTOR_ELT:
196 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
199 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
203 // If the result is null, the sub-method took care of registering results etc.
204 if (!Res.Val) return false;
206 // If the result is N, the sub-method updated N in place. Check to see if any
207 // operands are new, and if so, mark them.
209 // Mark N as new and remark N and its operands. This allows us to correctly
210 // revisit N if it needs another step of promotion and allows us to visit
211 // any new operands to N.
216 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
217 "Invalid operand expansion");
219 ReplaceValueWith(SDValue(N, 0), Res);
223 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
224 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
225 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
226 SDValue Elt = GetScalarizedVector(N->getOperand(0));
227 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
230 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
231 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
233 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
234 return GetScalarizedVector(N->getOperand(0));
237 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
238 /// scalarized, it must be <1 x ty>. Just store the element.
239 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
240 assert(N->isUnindexed() && "Indexed store of one-element vector?");
241 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
243 if (N->isTruncatingStore())
244 return DAG.getTruncStore(N->getChain(),
245 GetScalarizedVector(N->getOperand(1)),
247 N->getSrcValue(), N->getSrcValueOffset(),
248 N->getMemoryVT().getVectorElementType(),
249 N->isVolatile(), N->getAlignment());
251 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
252 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
253 N->isVolatile(), N->getAlignment());
257 //===----------------------------------------------------------------------===//
258 // Result Vector Splitting
259 //===----------------------------------------------------------------------===//
261 /// SplitVectorResult - This method is called when the specified result of the
262 /// specified node is found to need vector splitting. At this point, the node
263 /// may also have invalid operands or may have other results that need
264 /// legalization, we just know that (at least) one result needs vector
266 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
267 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
270 switch (N->getOpcode()) {
273 cerr << "SplitVectorResult #" << ResNo << ": ";
274 N->dump(&DAG); cerr << "\n";
276 assert(0 && "Do not know how to split the result of this operator!");
279 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
280 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
281 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
282 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
284 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
285 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
286 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
287 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
288 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
289 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
290 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
291 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
301 case ISD::FP_TO_SINT:
302 case ISD::FP_TO_UINT:
303 case ISD::SINT_TO_FP:
304 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
321 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
324 // If Lo/Hi is null, the sub-method took care of registering results etc.
326 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
329 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
331 SDValue LHSLo, LHSHi;
332 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
333 SDValue RHSLo, RHSHi;
334 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
336 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
337 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
340 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
342 // We know the result is a vector. The input may be either a vector or a
345 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
347 SDValue InOp = N->getOperand(0);
348 MVT InVT = InOp.getValueType();
350 // Handle some special cases efficiently.
351 switch (getTypeAction(InVT)) {
353 assert(false && "Unknown type action!");
357 case ScalarizeVector:
361 // A scalar to vector conversion, where the scalar needs expansion.
362 // If the vector is being split in two then we can just convert the
365 GetExpandedOp(InOp, Lo, Hi);
366 if (TLI.isBigEndian())
368 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
369 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
374 // If the input is a vector that needs to be split, convert each split
375 // piece of the input now.
376 GetSplitVector(InOp, Lo, Hi);
377 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
378 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
382 // In the general case, convert the input to an integer and split it by hand.
383 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
384 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
385 if (TLI.isBigEndian())
386 std::swap(LoIntVT, HiIntVT);
388 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
390 if (TLI.isBigEndian())
392 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
393 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
396 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
399 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
400 unsigned LoNumElts = LoVT.getVectorNumElements();
401 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
402 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
404 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
405 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
408 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
410 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
411 unsigned NumSubvectors = N->getNumOperands() / 2;
412 if (NumSubvectors == 1) {
413 Lo = N->getOperand(0);
414 Hi = N->getOperand(1);
419 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
421 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
422 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
424 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
425 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
428 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
430 GetSplitVector(N->getOperand(0), Lo, Hi);
431 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
432 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
435 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
437 SDValue Vec = N->getOperand(0);
438 SDValue Elt = N->getOperand(1);
439 SDValue Idx = N->getOperand(2);
440 GetSplitVector(Vec, Lo, Hi);
442 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
443 unsigned IdxVal = CIdx->getValue();
444 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
445 if (IdxVal < LoNumElts)
446 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
448 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
449 DAG.getIntPtrConstant(IdxVal - LoNumElts));
453 // Spill the vector to the stack.
454 MVT VecVT = Vec.getValueType();
455 MVT EltVT = VecVT.getVectorElementType();
456 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
457 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
459 // Store the new element. This may be larger than the vector element type,
460 // so use a truncating store.
461 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
462 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
464 // Reload the vector from the stack.
465 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
468 SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
471 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
473 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
475 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
477 ISD::LoadExtType ExtType = LD->getExtensionType();
478 SDValue Ch = LD->getChain();
479 SDValue Ptr = LD->getBasePtr();
480 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
481 const Value *SV = LD->getSrcValue();
482 int SVOffset = LD->getSrcValueOffset();
483 MVT MemoryVT = LD->getMemoryVT();
484 unsigned Alignment = LD->getAlignment();
485 bool isVolatile = LD->isVolatile();
487 MVT LoMemVT, HiMemVT;
488 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
490 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
491 SV, SVOffset, LoMemVT, isVolatile, Alignment);
493 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
494 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
495 DAG.getIntPtrConstant(IncrementSize));
496 SVOffset += IncrementSize;
497 Alignment = MinAlign(Alignment, IncrementSize);
498 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
499 SV, SVOffset, HiMemVT, isVolatile, Alignment);
501 // Build a factor node to remember that this load is independent of the
503 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
506 // Legalized the chain result - switch anything that used the old chain to
508 ReplaceValueWith(SDValue(LD, 1), Ch);
511 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
513 // Get the dest types - they may not match the input types, e.g. int_to_fp.
515 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
517 GetSplitVector(N->getOperand(0), Lo, Hi);
518 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
519 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
522 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
524 // Build the low part.
525 SDValue Mask = N->getOperand(2);
526 SmallVector<SDValue, 16> Ops;
528 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
529 MVT EltVT = LoVT.getVectorElementType();
530 unsigned LoNumElts = LoVT.getVectorNumElements();
531 unsigned NumElements = Mask.getNumOperands();
533 // Insert all of the elements from the input that are needed. We use
534 // buildvector of extractelement here because the input vectors will have
535 // to be legalized, so this makes the code simpler.
536 for (unsigned i = 0; i != LoNumElts; ++i) {
537 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
538 SDValue InVec = N->getOperand(0);
539 if (Idx >= NumElements) {
540 InVec = N->getOperand(1);
543 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
544 DAG.getIntPtrConstant(Idx)));
546 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
549 for (unsigned i = LoNumElts; i != NumElements; ++i) {
550 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
551 SDValue InVec = N->getOperand(0);
552 if (Idx >= NumElements) {
553 InVec = N->getOperand(1);
556 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
557 DAG.getIntPtrConstant(Idx)));
559 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
562 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
565 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
567 SDValue LL, LH, RL, RH;
568 GetSplitVector(N->getOperand(0), LL, LH);
569 GetSplitVector(N->getOperand(1), RL, RH);
571 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
572 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
576 //===----------------------------------------------------------------------===//
577 // Operand Vector Splitting
578 //===----------------------------------------------------------------------===//
580 /// SplitVectorOperand - This method is called when the specified operand of the
581 /// specified node is found to need vector splitting. At this point, all of the
582 /// result types of the node are known to be legal, but other operands of the
583 /// node may need legalization as well as the specified one.
584 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
585 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
586 SDValue Res = SDValue();
589 switch (N->getOpcode()) {
592 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
593 N->dump(&DAG); cerr << "\n";
595 assert(0 && "Do not know how to split this operator's operand!");
598 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
599 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
600 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
601 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
603 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
607 // If the result is null, the sub-method took care of registering results etc.
608 if (!Res.Val) return false;
610 // If the result is N, the sub-method updated N in place. Check to see if any
611 // operands are new, and if so, mark them.
613 // Mark N as new and remark N and its operands. This allows us to correctly
614 // revisit N if it needs another step of promotion and allows us to visit
615 // any new operands to N.
620 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
621 "Invalid operand expansion");
623 ReplaceValueWith(SDValue(N, 0), Res);
627 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
628 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
629 // end up being split all the way down to individual components. Convert the
630 // split pieces into integers and reassemble.
632 GetSplitVector(N->getOperand(0), Lo, Hi);
633 Lo = BitConvertToInteger(Lo);
634 Hi = BitConvertToInteger(Hi);
636 if (TLI.isBigEndian())
639 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
640 JoinIntegers(Lo, Hi));
643 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
644 // We know that the extracted result type is legal. For now, assume the index
646 MVT SubVT = N->getValueType(0);
647 SDValue Idx = N->getOperand(1);
649 GetSplitVector(N->getOperand(0), Lo, Hi);
651 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
652 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
654 if (IdxVal < LoElts) {
655 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
656 "Extracted subvector crosses vector split!");
657 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
659 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
660 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
664 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
665 SDValue Vec = N->getOperand(0);
666 SDValue Idx = N->getOperand(1);
667 MVT VecVT = Vec.getValueType();
669 if (isa<ConstantSDNode>(Idx)) {
670 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
671 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
674 GetSplitVector(Vec, Lo, Hi);
676 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
679 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
681 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
682 DAG.getConstant(IdxVal - LoElts,
683 Idx.getValueType()));
686 // Store the vector to the stack.
687 MVT EltVT = VecVT.getVectorElementType();
688 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
689 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
691 // Load back the required element.
692 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
693 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
696 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
697 assert(N->isUnindexed() && "Indexed store of vector?");
698 assert(OpNo == 1 && "Can only split the stored value");
700 bool isTruncating = N->isTruncatingStore();
701 SDValue Ch = N->getChain();
702 SDValue Ptr = N->getBasePtr();
703 int SVOffset = N->getSrcValueOffset();
704 MVT MemoryVT = N->getMemoryVT();
705 unsigned Alignment = N->getAlignment();
706 bool isVol = N->isVolatile();
708 GetSplitVector(N->getOperand(1), Lo, Hi);
710 MVT LoMemVT, HiMemVT;
711 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
713 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
716 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
717 LoMemVT, isVol, Alignment);
719 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
722 // Increment the pointer to the other half.
723 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
724 DAG.getIntPtrConstant(IncrementSize));
727 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
728 N->getSrcValue(), SVOffset+IncrementSize,
730 isVol, MinAlign(Alignment, IncrementSize));
732 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
733 isVol, MinAlign(Alignment, IncrementSize));
735 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
738 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
739 assert(OpNo == 2 && "Shuffle source type differs from result type?");
740 SDValue Mask = N->getOperand(2);
741 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
742 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
743 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
745 // Look for a legal vector type to place the mask values in.
746 // Note that there may not be *any* legal vector-of-integer
747 // type for which the element type is legal!
748 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
749 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
750 // Integer values types are consecutively numbered. Exploit this.
751 EltVT = MVT::SimpleValueType(EltVT + 1)) {
753 // Is the element type big enough to hold the values?
754 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
758 // Is the vector type legal?
759 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
760 if (!isTypeLegal(VecVT))
764 // If the element type is not legal, find a larger legal type to use for
765 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
766 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
767 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
768 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
769 // Integer values types are consecutively numbered. Exploit this.
770 OpVT = MVT::SimpleValueType(OpVT + 1)) {
771 if (!isTypeLegal(OpVT))
774 // Success! Rebuild the vector using the legal types.
775 SmallVector<SDValue, 16> Ops(MaskLength);
776 for (unsigned i = 0; i < MaskLength; ++i) {
778 cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
779 Ops[i] = DAG.getConstant(Idx, OpVT);
781 return DAG.UpdateNodeOperands(SDValue(N,0),
782 N->getOperand(0), N->getOperand(1),
783 DAG.getNode(ISD::BUILD_VECTOR,
784 VecVT, &Ops[0], Ops.size()));
787 // Continuing is pointless - failure is certain.
790 assert(false && "Failed to find an appropriate mask type!");
791 return SDValue(N, 0);