1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 //===----------------------------------------------------------------------===//
30 // Result Vector Scalarization: <1 x ty> -> ty.
31 //===----------------------------------------------------------------------===//
33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
37 SDValue R = SDValue();
39 switch (N->getOpcode()) {
42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
46 report_fatal_error("Do not know how to scalarize the result of this "
49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
89 case ISD::SIGN_EXTEND:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
116 R = ScalarizeVecRes_BinOp(N);
120 // If R is null, the sub-method took care of registering the result.
122 SetScalarizedVector(SDValue(N, ResNo), R);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
129 LHS.getValueType(), LHS, RHS);
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return GetScalarizedVector(Op);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
139 EVT NewVT = N->getValueType(0).getVectorElementType();
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
141 NewVT, N->getOperand(0));
144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
145 EVT NewVT = N->getValueType(0).getVectorElementType();
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
148 Op0, DAG.getValueType(NewVT),
149 DAG.getValueType(Op0.getValueType()),
152 cast<CvtRndSatSDNode>(N)->getCvtCode());
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
157 N->getValueType(0).getVectorElementType(),
158 N->getOperand(0), N->getOperand(1));
161 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
162 EVT NewVT = N->getValueType(0).getVectorElementType();
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
165 NewVT, Op, N->getOperand(1));
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
169 SDValue Op = GetScalarizedVector(N->getOperand(0));
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
171 Op.getValueType(), Op, N->getOperand(1));
174 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
175 // The value to insert may have a wider type than the vector element type,
176 // so be sure to truncate it to the element type if necessary.
177 SDValue Op = N->getOperand(1);
178 EVT EltVT = N->getValueType(0).getVectorElementType();
179 if (Op.getValueType() != EltVT)
180 // FIXME: Can this happen for floating point types?
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
186 assert(N->isUnindexed() && "Indexed vector load?");
188 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
189 N->getExtensionType(),
190 N->getValueType(0).getVectorElementType(),
192 N->getChain(), N->getBasePtr(),
193 DAG.getUNDEF(N->getBasePtr().getValueType()),
195 N->getMemoryVT().getVectorElementType(),
196 N->isVolatile(), N->isNonTemporal(),
197 N->isInvariant(), N->getOriginalAlignment());
199 // Legalized the chain result - switch anything that used the old chain to
201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
207 EVT DestVT = N->getValueType(0).getVectorElementType();
208 SDValue Op = GetScalarizedVector(N->getOperand(0));
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
212 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
213 EVT EltVT = N->getValueType(0).getVectorElementType();
214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
215 SDValue LHS = GetScalarizedVector(N->getOperand(0));
216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
217 LHS, DAG.getValueType(ExtVT));
220 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
221 // If the operand is wider than the vector element type then it is implicitly
222 // truncated. Make that explicit here.
223 EVT EltVT = N->getValueType(0).getVectorElementType();
224 SDValue InOp = N->getOperand(0);
225 if (InOp.getValueType() != EltVT)
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
230 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
231 SDValue Cond = GetScalarizedVector(N->getOperand(0));
232 SDValue LHS = GetScalarizedVector(N->getOperand(1));
233 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false);
234 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true);
235 if (ScalarBool != VecBool) {
236 EVT CondVT = Cond.getValueType();
237 switch (ScalarBool) {
238 default: llvm_unreachable("Unknown boolean content enum");
239 case TargetLowering::UndefinedBooleanContent:
241 case TargetLowering::ZeroOrOneBooleanContent:
242 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
243 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
244 // Vector read from all ones, scalar expects a single 1 so mask.
245 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT,
246 Cond, DAG.getConstant(1, CondVT));
248 case TargetLowering::ZeroOrNegativeOneBooleanContent:
249 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
250 VecBool == TargetLowering::ZeroOrOneBooleanContent);
251 // Vector reads from a one, scalar from all ones so sign extend.
252 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
253 Cond, DAG.getValueType(MVT::i1));
257 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
258 LHS.getValueType(), Cond, LHS,
259 GetScalarizedVector(N->getOperand(2)));
262 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
263 SDValue LHS = GetScalarizedVector(N->getOperand(1));
264 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
265 LHS.getValueType(), N->getOperand(0), LHS,
266 GetScalarizedVector(N->getOperand(2)));
269 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
270 SDValue LHS = GetScalarizedVector(N->getOperand(2));
271 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
272 N->getOperand(0), N->getOperand(1),
273 LHS, GetScalarizedVector(N->getOperand(3)),
277 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
278 assert(N->getValueType(0).isVector() ==
279 N->getOperand(0).getValueType().isVector() &&
280 "Scalar/Vector type mismatch");
282 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
284 SDValue LHS = GetScalarizedVector(N->getOperand(0));
285 SDValue RHS = GetScalarizedVector(N->getOperand(1));
286 DebugLoc DL = N->getDebugLoc();
288 // Turn it into a scalar SETCC.
289 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
292 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
293 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
296 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
297 // Figure out if the scalar is the LHS or RHS and return it.
298 SDValue Arg = N->getOperand(2).getOperand(0);
299 if (Arg.getOpcode() == ISD::UNDEF)
300 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
301 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
302 return GetScalarizedVector(N->getOperand(Op));
305 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
306 assert(N->getValueType(0).isVector() &&
307 N->getOperand(0).getValueType().isVector() &&
308 "Operand types must be vectors");
310 SDValue LHS = GetScalarizedVector(N->getOperand(0));
311 SDValue RHS = GetScalarizedVector(N->getOperand(1));
312 EVT NVT = N->getValueType(0).getVectorElementType();
313 DebugLoc DL = N->getDebugLoc();
315 // Turn it into a scalar SETCC.
316 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
318 // Vectors may have a different boolean contents to scalars. Promote the
319 // value appropriately.
320 ISD::NodeType ExtendCode =
321 TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
322 return DAG.getNode(ExtendCode, DL, NVT, Res);
326 //===----------------------------------------------------------------------===//
327 // Operand Vector Scalarization <1 x ty> -> ty.
328 //===----------------------------------------------------------------------===//
330 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
331 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
334 SDValue Res = SDValue();
336 if (Res.getNode() == 0) {
337 switch (N->getOpcode()) {
340 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
344 llvm_unreachable("Do not know how to scalarize this operator's operand!");
346 Res = ScalarizeVecOp_BITCAST(N);
348 case ISD::CONCAT_VECTORS:
349 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
351 case ISD::EXTRACT_VECTOR_ELT:
352 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
355 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
360 // If the result is null, the sub-method took care of registering results etc.
361 if (!Res.getNode()) return false;
363 // If the result is N, the sub-method updated N in place. Tell the legalizer
365 if (Res.getNode() == N)
368 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
369 "Invalid operand expansion");
371 ReplaceValueWith(SDValue(N, 0), Res);
375 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
376 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
377 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
378 SDValue Elt = GetScalarizedVector(N->getOperand(0));
379 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
380 N->getValueType(0), Elt);
383 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
384 /// use a BUILD_VECTOR instead.
385 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
386 SmallVector<SDValue, 8> Ops(N->getNumOperands());
387 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
388 Ops[i] = GetScalarizedVector(N->getOperand(i));
389 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
390 &Ops[0], Ops.size());
393 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
394 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
396 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
397 SDValue Res = GetScalarizedVector(N->getOperand(0));
398 if (Res.getValueType() != N->getValueType(0))
399 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
404 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
405 /// scalarized, it must be <1 x ty>. Just store the element.
406 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
407 assert(N->isUnindexed() && "Indexed store of one-element vector?");
408 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
409 DebugLoc dl = N->getDebugLoc();
411 if (N->isTruncatingStore())
412 return DAG.getTruncStore(N->getChain(), dl,
413 GetScalarizedVector(N->getOperand(1)),
414 N->getBasePtr(), N->getPointerInfo(),
415 N->getMemoryVT().getVectorElementType(),
416 N->isVolatile(), N->isNonTemporal(),
419 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
420 N->getBasePtr(), N->getPointerInfo(),
421 N->isVolatile(), N->isNonTemporal(),
422 N->getOriginalAlignment());
426 //===----------------------------------------------------------------------===//
427 // Result Vector Splitting
428 //===----------------------------------------------------------------------===//
430 /// SplitVectorResult - This method is called when the specified result of the
431 /// specified node is found to need vector splitting. At this point, the node
432 /// may also have invalid operands or may have other results that need
433 /// legalization, we just know that (at least) one result needs vector
435 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
436 DEBUG(dbgs() << "Split node result: ";
441 // See if the target wants to custom expand this node.
442 if (CustomLowerNode(N, N->getValueType(ResNo), true))
445 switch (N->getOpcode()) {
448 dbgs() << "SplitVectorResult #" << ResNo << ": ";
452 llvm_unreachable("Do not know how to split the result of this operator!");
454 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
456 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
457 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
458 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
459 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
460 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
461 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
462 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
463 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
464 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
465 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
466 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
467 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
469 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
472 SplitVecRes_SETCC(N, Lo, Hi);
474 case ISD::VECTOR_SHUFFLE:
475 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
478 case ISD::ANY_EXTEND:
479 case ISD::CONVERT_RNDSAT:
482 case ISD::CTLZ_ZERO_UNDEF:
483 case ISD::CTTZ_ZERO_UNDEF:
494 case ISD::FNEARBYINT:
498 case ISD::FP_TO_SINT:
499 case ISD::FP_TO_UINT:
504 case ISD::SIGN_EXTEND:
505 case ISD::SINT_TO_FP:
507 case ISD::UINT_TO_FP:
508 case ISD::ZERO_EXTEND:
509 SplitVecRes_UnaryOp(N, Lo, Hi);
531 SplitVecRes_BinOp(N, Lo, Hi);
535 // If Lo/Hi is null, the sub-method took care of registering results etc.
537 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
540 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
542 SDValue LHSLo, LHSHi;
543 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
544 SDValue RHSLo, RHSHi;
545 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
546 DebugLoc dl = N->getDebugLoc();
548 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
549 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
552 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
554 // We know the result is a vector. The input may be either a vector or a
557 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
558 DebugLoc dl = N->getDebugLoc();
560 SDValue InOp = N->getOperand(0);
561 EVT InVT = InOp.getValueType();
563 // Handle some special cases efficiently.
564 switch (getTypeAction(InVT)) {
565 case TargetLowering::TypeLegal:
566 case TargetLowering::TypePromoteInteger:
567 case TargetLowering::TypeSoftenFloat:
568 case TargetLowering::TypeScalarizeVector:
569 case TargetLowering::TypeWidenVector:
571 case TargetLowering::TypeExpandInteger:
572 case TargetLowering::TypeExpandFloat:
573 // A scalar to vector conversion, where the scalar needs expansion.
574 // If the vector is being split in two then we can just convert the
577 GetExpandedOp(InOp, Lo, Hi);
578 if (TLI.isBigEndian())
580 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
581 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
585 case TargetLowering::TypeSplitVector:
586 // If the input is a vector that needs to be split, convert each split
587 // piece of the input now.
588 GetSplitVector(InOp, Lo, Hi);
589 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
590 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
594 // In the general case, convert the input to an integer and split it by hand.
595 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
596 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
597 if (TLI.isBigEndian())
598 std::swap(LoIntVT, HiIntVT);
600 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
602 if (TLI.isBigEndian())
604 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
605 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
608 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
611 DebugLoc dl = N->getDebugLoc();
612 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
613 unsigned LoNumElts = LoVT.getVectorNumElements();
614 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
615 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
617 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
618 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
621 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
623 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
624 DebugLoc dl = N->getDebugLoc();
625 unsigned NumSubvectors = N->getNumOperands() / 2;
626 if (NumSubvectors == 1) {
627 Lo = N->getOperand(0);
628 Hi = N->getOperand(1);
633 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
635 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
636 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
638 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
639 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
642 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
644 SDValue Vec = N->getOperand(0);
645 SDValue Idx = N->getOperand(1);
646 DebugLoc dl = N->getDebugLoc();
649 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
651 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
652 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
653 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
654 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
657 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
659 DebugLoc dl = N->getDebugLoc();
660 GetSplitVector(N->getOperand(0), Lo, Hi);
661 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
662 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
665 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
667 SDValue LHSLo, LHSHi;
668 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
669 DebugLoc dl = N->getDebugLoc();
672 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
674 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
675 DAG.getValueType(LoVT));
676 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
677 DAG.getValueType(HiVT));
680 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
682 SDValue Vec = N->getOperand(0);
683 SDValue Elt = N->getOperand(1);
684 SDValue Idx = N->getOperand(2);
685 DebugLoc dl = N->getDebugLoc();
686 GetSplitVector(Vec, Lo, Hi);
688 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
689 unsigned IdxVal = CIdx->getZExtValue();
690 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
691 if (IdxVal < LoNumElts)
692 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
693 Lo.getValueType(), Lo, Elt, Idx);
695 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
696 DAG.getIntPtrConstant(IdxVal - LoNumElts));
700 // Spill the vector to the stack.
701 EVT VecVT = Vec.getValueType();
702 EVT EltVT = VecVT.getVectorElementType();
703 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
704 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
705 MachinePointerInfo(), false, false, 0);
707 // Store the new element. This may be larger than the vector element type,
708 // so use a truncating store.
709 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
710 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
712 TLI.getTargetData()->getPrefTypeAlignment(VecType);
713 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
716 // Load the Lo part from the stack slot.
717 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
718 false, false, false, 0);
720 // Increment the pointer to the other part.
721 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
722 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
723 DAG.getIntPtrConstant(IncrementSize));
725 // Load the Hi part from the stack slot.
726 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
727 false, false, false, MinAlign(Alignment, IncrementSize));
730 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
733 DebugLoc dl = N->getDebugLoc();
734 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
735 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
736 Hi = DAG.getUNDEF(HiVT);
739 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
741 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
743 DebugLoc dl = LD->getDebugLoc();
744 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
746 ISD::LoadExtType ExtType = LD->getExtensionType();
747 SDValue Ch = LD->getChain();
748 SDValue Ptr = LD->getBasePtr();
749 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
750 EVT MemoryVT = LD->getMemoryVT();
751 unsigned Alignment = LD->getOriginalAlignment();
752 bool isVolatile = LD->isVolatile();
753 bool isNonTemporal = LD->isNonTemporal();
754 bool isInvariant = LD->isInvariant();
756 EVT LoMemVT, HiMemVT;
757 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
759 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
760 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
761 isInvariant, Alignment);
763 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
764 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
765 DAG.getIntPtrConstant(IncrementSize));
766 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
767 LD->getPointerInfo().getWithOffset(IncrementSize),
768 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment);
770 // Build a factor node to remember that this load is independent of the
772 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
775 // Legalized the chain result - switch anything that used the old chain to
777 ReplaceValueWith(SDValue(LD, 1), Ch);
780 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
781 assert(N->getValueType(0).isVector() &&
782 N->getOperand(0).getValueType().isVector() &&
783 "Operand types must be vectors");
786 DebugLoc DL = N->getDebugLoc();
787 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
790 EVT InVT = N->getOperand(0).getValueType();
791 SDValue LL, LH, RL, RH;
792 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
793 LoVT.getVectorNumElements());
794 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
795 DAG.getIntPtrConstant(0));
796 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
797 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
799 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
800 DAG.getIntPtrConstant(0));
801 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
802 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
804 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
805 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
808 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
810 // Get the dest types - they may not match the input types, e.g. int_to_fp.
812 DebugLoc dl = N->getDebugLoc();
813 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
815 // If the input also splits, handle it directly for a compile time speedup.
816 // Otherwise split it by hand.
817 EVT InVT = N->getOperand(0).getValueType();
818 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
819 GetSplitVector(N->getOperand(0), Lo, Hi);
821 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
822 LoVT.getVectorNumElements());
823 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
824 DAG.getIntPtrConstant(0));
825 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
826 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
829 if (N->getOpcode() == ISD::FP_ROUND) {
830 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
831 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
832 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
833 SDValue DTyOpLo = DAG.getValueType(LoVT);
834 SDValue DTyOpHi = DAG.getValueType(HiVT);
835 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
836 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
837 SDValue RndOp = N->getOperand(3);
838 SDValue SatOp = N->getOperand(4);
839 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
840 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
842 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
845 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
846 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
850 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
851 SDValue &Lo, SDValue &Hi) {
852 // The low and high parts of the original input give four input vectors.
854 DebugLoc dl = N->getDebugLoc();
855 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
856 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
857 EVT NewVT = Inputs[0].getValueType();
858 unsigned NewElts = NewVT.getVectorNumElements();
860 // If Lo or Hi uses elements from at most two of the four input vectors, then
861 // express it as a vector shuffle of those two inputs. Otherwise extract the
862 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
863 SmallVector<int, 16> Ops;
864 for (unsigned High = 0; High < 2; ++High) {
865 SDValue &Output = High ? Hi : Lo;
867 // Build a shuffle mask for the output, discovering on the fly which
868 // input vectors to use as shuffle operands (recorded in InputUsed).
869 // If building a suitable shuffle vector proves too hard, then bail
870 // out with useBuildVector set.
871 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
872 unsigned FirstMaskIdx = High * NewElts;
873 bool useBuildVector = false;
874 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
875 // The mask element. This indexes into the input.
876 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
878 // The input vector this mask element indexes into.
879 unsigned Input = (unsigned)Idx / NewElts;
881 if (Input >= array_lengthof(Inputs)) {
882 // The mask element does not index into any input vector.
887 // Turn the index into an offset from the start of the input vector.
888 Idx -= Input * NewElts;
890 // Find or create a shuffle vector operand to hold this input.
892 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
893 if (InputUsed[OpNo] == Input) {
894 // This input vector is already an operand.
896 } else if (InputUsed[OpNo] == -1U) {
897 // Create a new operand for this input vector.
898 InputUsed[OpNo] = Input;
903 if (OpNo >= array_lengthof(InputUsed)) {
904 // More than two input vectors used! Give up on trying to create a
905 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
906 useBuildVector = true;
910 // Add the mask index for the new shuffle vector.
911 Ops.push_back(Idx + OpNo * NewElts);
914 if (useBuildVector) {
915 EVT EltVT = NewVT.getVectorElementType();
916 SmallVector<SDValue, 16> SVOps;
918 // Extract the input elements by hand.
919 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
920 // The mask element. This indexes into the input.
921 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
923 // The input vector this mask element indexes into.
924 unsigned Input = (unsigned)Idx / NewElts;
926 if (Input >= array_lengthof(Inputs)) {
927 // The mask element is "undef" or indexes off the end of the input.
928 SVOps.push_back(DAG.getUNDEF(EltVT));
932 // Turn the index into an offset from the start of the input vector.
933 Idx -= Input * NewElts;
935 // Extract the vector element by hand.
936 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
937 Inputs[Input], DAG.getIntPtrConstant(Idx)));
940 // Construct the Lo/Hi output using a BUILD_VECTOR.
941 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
942 } else if (InputUsed[0] == -1U) {
943 // No input vectors were used! The result is undefined.
944 Output = DAG.getUNDEF(NewVT);
946 SDValue Op0 = Inputs[InputUsed[0]];
947 // If only one input was used, use an undefined vector for the other.
948 SDValue Op1 = InputUsed[1] == -1U ?
949 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
950 // At least one input vector was used. Create a new shuffle vector.
951 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
959 //===----------------------------------------------------------------------===//
960 // Operand Vector Splitting
961 //===----------------------------------------------------------------------===//
963 /// SplitVectorOperand - This method is called when the specified operand of the
964 /// specified node is found to need vector splitting. At this point, all of the
965 /// result types of the node are known to be legal, but other operands of the
966 /// node may need legalization as well as the specified one.
967 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
968 DEBUG(dbgs() << "Split node operand: ";
971 SDValue Res = SDValue();
973 if (Res.getNode() == 0) {
974 switch (N->getOpcode()) {
977 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
981 llvm_unreachable("Do not know how to split this operator's operand!");
982 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
983 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
984 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
985 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
986 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
987 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
989 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
996 case ISD::FP_TO_SINT:
997 case ISD::FP_TO_UINT:
998 case ISD::SINT_TO_FP:
999 case ISD::UINT_TO_FP:
1002 case ISD::SIGN_EXTEND:
1003 case ISD::ZERO_EXTEND:
1004 case ISD::ANY_EXTEND:
1005 Res = SplitVecOp_UnaryOp(N);
1010 // If the result is null, the sub-method took care of registering results etc.
1011 if (!Res.getNode()) return false;
1013 // If the result is N, the sub-method updated N in place. Tell the legalizer
1015 if (Res.getNode() == N)
1018 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1019 "Invalid operand expansion");
1021 ReplaceValueWith(SDValue(N, 0), Res);
1025 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1026 // The result has a legal vector type, but the input needs splitting.
1027 EVT ResVT = N->getValueType(0);
1029 DebugLoc dl = N->getDebugLoc();
1030 GetSplitVector(N->getOperand(0), Lo, Hi);
1031 EVT InVT = Lo.getValueType();
1033 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1034 InVT.getVectorNumElements());
1036 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1037 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1039 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1042 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1043 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1044 // end up being split all the way down to individual components. Convert the
1045 // split pieces into integers and reassemble.
1047 GetSplitVector(N->getOperand(0), Lo, Hi);
1048 Lo = BitConvertToInteger(Lo);
1049 Hi = BitConvertToInteger(Hi);
1051 if (TLI.isBigEndian())
1054 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1055 JoinIntegers(Lo, Hi));
1058 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1059 // We know that the extracted result type is legal.
1060 EVT SubVT = N->getValueType(0);
1061 SDValue Idx = N->getOperand(1);
1062 DebugLoc dl = N->getDebugLoc();
1064 GetSplitVector(N->getOperand(0), Lo, Hi);
1066 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1067 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1069 if (IdxVal < LoElts) {
1070 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1071 "Extracted subvector crosses vector split!");
1072 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1074 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1075 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1079 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1080 SDValue Vec = N->getOperand(0);
1081 SDValue Idx = N->getOperand(1);
1082 EVT VecVT = Vec.getValueType();
1084 if (isa<ConstantSDNode>(Idx)) {
1085 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1086 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1089 GetSplitVector(Vec, Lo, Hi);
1091 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1093 if (IdxVal < LoElts)
1094 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1095 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1096 DAG.getConstant(IdxVal - LoElts,
1097 Idx.getValueType())), 0);
1100 // Store the vector to the stack.
1101 EVT EltVT = VecVT.getVectorElementType();
1102 DebugLoc dl = N->getDebugLoc();
1103 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1104 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1105 MachinePointerInfo(), false, false, 0);
1107 // Load back the required element.
1108 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1109 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1110 MachinePointerInfo(), EltVT, false, false, 0);
1113 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1114 assert(N->isUnindexed() && "Indexed store of vector?");
1115 assert(OpNo == 1 && "Can only split the stored value");
1116 DebugLoc DL = N->getDebugLoc();
1118 bool isTruncating = N->isTruncatingStore();
1119 SDValue Ch = N->getChain();
1120 SDValue Ptr = N->getBasePtr();
1121 EVT MemoryVT = N->getMemoryVT();
1122 unsigned Alignment = N->getOriginalAlignment();
1123 bool isVol = N->isVolatile();
1124 bool isNT = N->isNonTemporal();
1126 GetSplitVector(N->getOperand(1), Lo, Hi);
1128 EVT LoMemVT, HiMemVT;
1129 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1131 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1134 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1135 LoMemVT, isVol, isNT, Alignment);
1137 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1138 isVol, isNT, Alignment);
1140 // Increment the pointer to the other half.
1141 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1142 DAG.getIntPtrConstant(IncrementSize));
1145 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1146 N->getPointerInfo().getWithOffset(IncrementSize),
1147 HiMemVT, isVol, isNT, Alignment);
1149 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1150 N->getPointerInfo().getWithOffset(IncrementSize),
1151 isVol, isNT, Alignment);
1153 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1156 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1157 DebugLoc DL = N->getDebugLoc();
1159 // The input operands all must have the same type, and we know the result the
1160 // result type is valid. Convert this to a buildvector which extracts all the
1162 // TODO: If the input elements are power-two vectors, we could convert this to
1163 // a new CONCAT_VECTORS node with elements that are half-wide.
1164 SmallVector<SDValue, 32> Elts;
1165 EVT EltVT = N->getValueType(0).getVectorElementType();
1166 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1167 SDValue Op = N->getOperand(op);
1168 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1170 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1171 Op, DAG.getIntPtrConstant(i)));
1176 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1177 &Elts[0], Elts.size());
1180 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1181 assert(N->getValueType(0).isVector() &&
1182 N->getOperand(0).getValueType().isVector() &&
1183 "Operand types must be vectors");
1184 // The result has a legal vector type, but the input needs splitting.
1185 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1186 DebugLoc DL = N->getDebugLoc();
1187 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1188 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1189 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1190 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1191 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1193 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1194 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1195 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1196 return PromoteTargetBoolean(Con, N->getValueType(0));
1200 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1201 // The result has a legal vector type, but the input needs splitting.
1202 EVT ResVT = N->getValueType(0);
1204 DebugLoc DL = N->getDebugLoc();
1205 GetSplitVector(N->getOperand(0), Lo, Hi);
1206 EVT InVT = Lo.getValueType();
1208 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1209 InVT.getVectorNumElements());
1211 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1212 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1214 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1219 //===----------------------------------------------------------------------===//
1220 // Result Vector Widening
1221 //===----------------------------------------------------------------------===//
1223 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1224 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1228 // See if the target wants to custom widen this node.
1229 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1232 SDValue Res = SDValue();
1233 switch (N->getOpcode()) {
1236 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1240 llvm_unreachable("Do not know how to widen the result of this operator!");
1242 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1243 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1244 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1245 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1246 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1247 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1248 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1249 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1250 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1251 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1252 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1254 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1255 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1256 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1257 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1258 case ISD::VECTOR_SHUFFLE:
1259 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1265 case ISD::FCOPYSIGN:
1281 Res = WidenVecRes_Binary(N);
1285 Res = WidenVecRes_POWI(N);
1291 Res = WidenVecRes_Shift(N);
1294 case ISD::ANY_EXTEND:
1295 case ISD::FP_EXTEND:
1297 case ISD::FP_TO_SINT:
1298 case ISD::FP_TO_UINT:
1299 case ISD::SIGN_EXTEND:
1300 case ISD::SINT_TO_FP:
1302 case ISD::UINT_TO_FP:
1303 case ISD::ZERO_EXTEND:
1304 Res = WidenVecRes_Convert(N);
1319 case ISD::FNEARBYINT:
1325 Res = WidenVecRes_Unary(N);
1329 // If Res is null, the sub-method took care of registering the result.
1331 SetWidenedVector(SDValue(N, ResNo), Res);
1334 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1335 // Binary op widening.
1336 unsigned Opcode = N->getOpcode();
1337 DebugLoc dl = N->getDebugLoc();
1338 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1339 EVT WidenEltVT = WidenVT.getVectorElementType();
1341 unsigned NumElts = VT.getVectorNumElements();
1342 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1343 NumElts = NumElts / 2;
1344 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1347 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1348 // Operation doesn't trap so just widen as normal.
1349 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1350 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1351 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1354 // No legal vector version so unroll the vector operation and then widen.
1356 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1358 // Since the operation can trap, apply operation on the original vector.
1360 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1361 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1362 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1364 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1365 unsigned ConcatEnd = 0; // Current ConcatOps index.
1366 int Idx = 0; // Current Idx into input vectors.
1368 // NumElts := greatest legal vector size (at most WidenVT)
1369 // while (orig. vector has unhandled elements) {
1370 // take munches of size NumElts from the beginning and add to ConcatOps
1371 // NumElts := next smaller supported vector size or 1
1373 while (CurNumElts != 0) {
1374 while (CurNumElts >= NumElts) {
1375 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1376 DAG.getIntPtrConstant(Idx));
1377 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1378 DAG.getIntPtrConstant(Idx));
1379 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1381 CurNumElts -= NumElts;
1384 NumElts = NumElts / 2;
1385 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1386 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1389 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1390 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1391 InOp1, DAG.getIntPtrConstant(Idx));
1392 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1393 InOp2, DAG.getIntPtrConstant(Idx));
1394 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1401 // Check to see if we have a single operation with the widen type.
1402 if (ConcatEnd == 1) {
1403 VT = ConcatOps[0].getValueType();
1405 return ConcatOps[0];
1408 // while (Some element of ConcatOps is not of type MaxVT) {
1409 // From the end of ConcatOps, collect elements of the same type and put
1410 // them into an op of the next larger supported type
1412 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1413 Idx = ConcatEnd - 1;
1414 VT = ConcatOps[Idx--].getValueType();
1415 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1418 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1422 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1423 } while (!TLI.isTypeLegal(NextVT));
1425 if (!VT.isVector()) {
1426 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1427 SDValue VecOp = DAG.getUNDEF(NextVT);
1428 unsigned NumToInsert = ConcatEnd - Idx - 1;
1429 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1430 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1431 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1433 ConcatOps[Idx+1] = VecOp;
1434 ConcatEnd = Idx + 2;
1436 // Vector type, create a CONCAT_VECTORS of type NextVT
1437 SDValue undefVec = DAG.getUNDEF(VT);
1438 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1439 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1440 unsigned RealVals = ConcatEnd - Idx - 1;
1441 unsigned SubConcatEnd = 0;
1442 unsigned SubConcatIdx = Idx + 1;
1443 while (SubConcatEnd < RealVals)
1444 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1445 while (SubConcatEnd < OpsToConcat)
1446 SubConcatOps[SubConcatEnd++] = undefVec;
1447 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1448 NextVT, &SubConcatOps[0],
1450 ConcatEnd = SubConcatIdx + 1;
1454 // Check to see if we have a single operation with the widen type.
1455 if (ConcatEnd == 1) {
1456 VT = ConcatOps[0].getValueType();
1458 return ConcatOps[0];
1461 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1462 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1463 if (NumOps != ConcatEnd ) {
1464 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1465 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1466 ConcatOps[j] = UndefVal;
1468 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1471 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1472 SDValue InOp = N->getOperand(0);
1473 DebugLoc DL = N->getDebugLoc();
1475 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1476 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1478 EVT InVT = InOp.getValueType();
1479 EVT InEltVT = InVT.getVectorElementType();
1480 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1482 unsigned Opcode = N->getOpcode();
1483 unsigned InVTNumElts = InVT.getVectorNumElements();
1485 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1486 InOp = GetWidenedVector(N->getOperand(0));
1487 InVT = InOp.getValueType();
1488 InVTNumElts = InVT.getVectorNumElements();
1489 if (InVTNumElts == WidenNumElts) {
1490 if (N->getNumOperands() == 1)
1491 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1492 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1496 if (TLI.isTypeLegal(InWidenVT)) {
1497 // Because the result and the input are different vector types, widening
1498 // the result could create a legal type but widening the input might make
1499 // it an illegal type that might lead to repeatedly splitting the input
1500 // and then widening it. To avoid this, we widen the input only if
1501 // it results in a legal type.
1502 if (WidenNumElts % InVTNumElts == 0) {
1503 // Widen the input and call convert on the widened input vector.
1504 unsigned NumConcat = WidenNumElts/InVTNumElts;
1505 SmallVector<SDValue, 16> Ops(NumConcat);
1507 SDValue UndefVal = DAG.getUNDEF(InVT);
1508 for (unsigned i = 1; i != NumConcat; ++i)
1510 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1511 &Ops[0], NumConcat);
1512 if (N->getNumOperands() == 1)
1513 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1514 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1517 if (InVTNumElts % WidenNumElts == 0) {
1518 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1519 InOp, DAG.getIntPtrConstant(0));
1520 // Extract the input and convert the shorten input vector.
1521 if (N->getNumOperands() == 1)
1522 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1523 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1527 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1528 SmallVector<SDValue, 16> Ops(WidenNumElts);
1529 EVT EltVT = WidenVT.getVectorElementType();
1530 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1532 for (i=0; i < MinElts; ++i) {
1533 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1534 DAG.getIntPtrConstant(i));
1535 if (N->getNumOperands() == 1)
1536 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1538 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1541 SDValue UndefVal = DAG.getUNDEF(EltVT);
1542 for (; i < WidenNumElts; ++i)
1545 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1548 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1549 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1550 SDValue InOp = GetWidenedVector(N->getOperand(0));
1551 SDValue ShOp = N->getOperand(1);
1552 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1555 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1556 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1557 SDValue InOp = GetWidenedVector(N->getOperand(0));
1558 SDValue ShOp = N->getOperand(1);
1560 EVT ShVT = ShOp.getValueType();
1561 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1562 ShOp = GetWidenedVector(ShOp);
1563 ShVT = ShOp.getValueType();
1565 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1566 ShVT.getVectorElementType(),
1567 WidenVT.getVectorNumElements());
1568 if (ShVT != ShWidenVT)
1569 ShOp = ModifyToType(ShOp, ShWidenVT);
1571 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1574 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1575 // Unary op widening.
1576 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1577 SDValue InOp = GetWidenedVector(N->getOperand(0));
1578 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1581 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1582 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1583 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1584 cast<VTSDNode>(N->getOperand(1))->getVT()
1585 .getVectorElementType(),
1586 WidenVT.getVectorNumElements());
1587 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1588 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1589 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1592 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
1593 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
1594 return GetWidenedVector(WidenVec);
1597 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1598 SDValue InOp = N->getOperand(0);
1599 EVT InVT = InOp.getValueType();
1600 EVT VT = N->getValueType(0);
1601 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1602 DebugLoc dl = N->getDebugLoc();
1604 switch (getTypeAction(InVT)) {
1605 case TargetLowering::TypeLegal:
1607 case TargetLowering::TypePromoteInteger:
1608 // If the incoming type is a vector that is being promoted, then
1609 // we know that the elements are arranged differently and that we
1610 // must perform the conversion using a stack slot.
1611 if (InVT.isVector())
1614 // If the InOp is promoted to the same size, convert it. Otherwise,
1615 // fall out of the switch and widen the promoted input.
1616 InOp = GetPromotedInteger(InOp);
1617 InVT = InOp.getValueType();
1618 if (WidenVT.bitsEq(InVT))
1619 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1621 case TargetLowering::TypeSoftenFloat:
1622 case TargetLowering::TypeExpandInteger:
1623 case TargetLowering::TypeExpandFloat:
1624 case TargetLowering::TypeScalarizeVector:
1625 case TargetLowering::TypeSplitVector:
1627 case TargetLowering::TypeWidenVector:
1628 // If the InOp is widened to the same size, convert it. Otherwise, fall
1629 // out of the switch and widen the widened input.
1630 InOp = GetWidenedVector(InOp);
1631 InVT = InOp.getValueType();
1632 if (WidenVT.bitsEq(InVT))
1633 // The input widens to the same size. Convert to the widen value.
1634 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1638 unsigned WidenSize = WidenVT.getSizeInBits();
1639 unsigned InSize = InVT.getSizeInBits();
1640 // x86mmx is not an acceptable vector element type, so don't try.
1641 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1642 // Determine new input vector type. The new input vector type will use
1643 // the same element type (if its a vector) or use the input type as a
1644 // vector. It is the same size as the type to widen to.
1646 unsigned NewNumElts = WidenSize / InSize;
1647 if (InVT.isVector()) {
1648 EVT InEltVT = InVT.getVectorElementType();
1649 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1650 WidenSize / InEltVT.getSizeInBits());
1652 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1655 if (TLI.isTypeLegal(NewInVT)) {
1656 // Because the result and the input are different vector types, widening
1657 // the result could create a legal type but widening the input might make
1658 // it an illegal type that might lead to repeatedly splitting the input
1659 // and then widening it. To avoid this, we widen the input only if
1660 // it results in a legal type.
1661 SmallVector<SDValue, 16> Ops(NewNumElts);
1662 SDValue UndefVal = DAG.getUNDEF(InVT);
1664 for (unsigned i = 1; i < NewNumElts; ++i)
1668 if (InVT.isVector())
1669 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1670 NewInVT, &Ops[0], NewNumElts);
1672 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1673 NewInVT, &Ops[0], NewNumElts);
1674 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1678 return CreateStackStoreLoad(InOp, WidenVT);
1681 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1682 DebugLoc dl = N->getDebugLoc();
1683 // Build a vector with undefined for the new nodes.
1684 EVT VT = N->getValueType(0);
1685 EVT EltVT = VT.getVectorElementType();
1686 unsigned NumElts = VT.getVectorNumElements();
1688 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1689 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1691 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1692 NewOps.reserve(WidenNumElts);
1693 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1694 NewOps.push_back(DAG.getUNDEF(EltVT));
1696 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1699 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1700 EVT InVT = N->getOperand(0).getValueType();
1701 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1702 DebugLoc dl = N->getDebugLoc();
1703 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1704 unsigned NumInElts = InVT.getVectorNumElements();
1705 unsigned NumOperands = N->getNumOperands();
1707 bool InputWidened = false; // Indicates we need to widen the input.
1708 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1709 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1710 // Add undef vectors to widen to correct length.
1711 unsigned NumConcat = WidenVT.getVectorNumElements() /
1712 InVT.getVectorNumElements();
1713 SDValue UndefVal = DAG.getUNDEF(InVT);
1714 SmallVector<SDValue, 16> Ops(NumConcat);
1715 for (unsigned i=0; i < NumOperands; ++i)
1716 Ops[i] = N->getOperand(i);
1717 for (unsigned i = NumOperands; i != NumConcat; ++i)
1719 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1722 InputWidened = true;
1723 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1724 // The inputs and the result are widen to the same value.
1726 for (i=1; i < NumOperands; ++i)
1727 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1730 if (i == NumOperands)
1731 // Everything but the first operand is an UNDEF so just return the
1732 // widened first operand.
1733 return GetWidenedVector(N->getOperand(0));
1735 if (NumOperands == 2) {
1736 // Replace concat of two operands with a shuffle.
1737 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1738 for (unsigned i = 0; i < NumInElts; ++i) {
1740 MaskOps[i + NumInElts] = i + WidenNumElts;
1742 return DAG.getVectorShuffle(WidenVT, dl,
1743 GetWidenedVector(N->getOperand(0)),
1744 GetWidenedVector(N->getOperand(1)),
1750 // Fall back to use extracts and build vector.
1751 EVT EltVT = WidenVT.getVectorElementType();
1752 SmallVector<SDValue, 16> Ops(WidenNumElts);
1754 for (unsigned i=0; i < NumOperands; ++i) {
1755 SDValue InOp = N->getOperand(i);
1757 InOp = GetWidenedVector(InOp);
1758 for (unsigned j=0; j < NumInElts; ++j)
1759 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1760 DAG.getIntPtrConstant(j));
1762 SDValue UndefVal = DAG.getUNDEF(EltVT);
1763 for (; Idx < WidenNumElts; ++Idx)
1764 Ops[Idx] = UndefVal;
1765 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1768 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1769 DebugLoc dl = N->getDebugLoc();
1770 SDValue InOp = N->getOperand(0);
1771 SDValue RndOp = N->getOperand(3);
1772 SDValue SatOp = N->getOperand(4);
1774 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1775 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1777 EVT InVT = InOp.getValueType();
1778 EVT InEltVT = InVT.getVectorElementType();
1779 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1781 SDValue DTyOp = DAG.getValueType(WidenVT);
1782 SDValue STyOp = DAG.getValueType(InWidenVT);
1783 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1785 unsigned InVTNumElts = InVT.getVectorNumElements();
1786 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1787 InOp = GetWidenedVector(InOp);
1788 InVT = InOp.getValueType();
1789 InVTNumElts = InVT.getVectorNumElements();
1790 if (InVTNumElts == WidenNumElts)
1791 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1795 if (TLI.isTypeLegal(InWidenVT)) {
1796 // Because the result and the input are different vector types, widening
1797 // the result could create a legal type but widening the input might make
1798 // it an illegal type that might lead to repeatedly splitting the input
1799 // and then widening it. To avoid this, we widen the input only if
1800 // it results in a legal type.
1801 if (WidenNumElts % InVTNumElts == 0) {
1802 // Widen the input and call convert on the widened input vector.
1803 unsigned NumConcat = WidenNumElts/InVTNumElts;
1804 SmallVector<SDValue, 16> Ops(NumConcat);
1806 SDValue UndefVal = DAG.getUNDEF(InVT);
1807 for (unsigned i = 1; i != NumConcat; ++i)
1810 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1811 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1815 if (InVTNumElts % WidenNumElts == 0) {
1816 // Extract the input and convert the shorten input vector.
1817 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1818 DAG.getIntPtrConstant(0));
1819 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1824 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1825 SmallVector<SDValue, 16> Ops(WidenNumElts);
1826 EVT EltVT = WidenVT.getVectorElementType();
1827 DTyOp = DAG.getValueType(EltVT);
1828 STyOp = DAG.getValueType(InEltVT);
1830 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1832 for (i=0; i < MinElts; ++i) {
1833 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1834 DAG.getIntPtrConstant(i));
1835 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1839 SDValue UndefVal = DAG.getUNDEF(EltVT);
1840 for (; i < WidenNumElts; ++i)
1843 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1846 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1847 EVT VT = N->getValueType(0);
1848 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1849 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1850 SDValue InOp = N->getOperand(0);
1851 SDValue Idx = N->getOperand(1);
1852 DebugLoc dl = N->getDebugLoc();
1854 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1855 InOp = GetWidenedVector(InOp);
1857 EVT InVT = InOp.getValueType();
1859 // Check if we can just return the input vector after widening.
1860 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1861 if (IdxVal == 0 && InVT == WidenVT)
1864 // Check if we can extract from the vector.
1865 unsigned InNumElts = InVT.getVectorNumElements();
1866 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1867 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1869 // We could try widening the input to the right length but for now, extract
1870 // the original elements, fill the rest with undefs and build a vector.
1871 SmallVector<SDValue, 16> Ops(WidenNumElts);
1872 EVT EltVT = VT.getVectorElementType();
1873 unsigned NumElts = VT.getVectorNumElements();
1875 for (i=0; i < NumElts; ++i)
1876 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1877 DAG.getIntPtrConstant(IdxVal+i));
1879 SDValue UndefVal = DAG.getUNDEF(EltVT);
1880 for (; i < WidenNumElts; ++i)
1882 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1885 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1886 SDValue InOp = GetWidenedVector(N->getOperand(0));
1887 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1888 InOp.getValueType(), InOp,
1889 N->getOperand(1), N->getOperand(2));
1892 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1893 LoadSDNode *LD = cast<LoadSDNode>(N);
1894 ISD::LoadExtType ExtType = LD->getExtensionType();
1897 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1898 if (ExtType != ISD::NON_EXTLOAD)
1899 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1901 Result = GenWidenVectorLoads(LdChain, LD);
1903 // If we generate a single load, we can use that for the chain. Otherwise,
1904 // build a factor node to remember the multiple loads are independent and
1907 if (LdChain.size() == 1)
1908 NewChain = LdChain[0];
1910 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1911 &LdChain[0], LdChain.size());
1913 // Modified the chain - switch anything that used the old chain to use
1915 ReplaceValueWith(SDValue(N, 1), NewChain);
1920 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1921 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1922 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1923 WidenVT, N->getOperand(0));
1926 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1927 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1928 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1930 SDValue Cond1 = N->getOperand(0);
1931 EVT CondVT = Cond1.getValueType();
1932 if (CondVT.isVector()) {
1933 EVT CondEltVT = CondVT.getVectorElementType();
1934 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1935 CondEltVT, WidenNumElts);
1936 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
1937 Cond1 = GetWidenedVector(Cond1);
1939 if (Cond1.getValueType() != CondWidenVT)
1940 Cond1 = ModifyToType(Cond1, CondWidenVT);
1943 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1944 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1945 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1946 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1947 WidenVT, Cond1, InOp1, InOp2);
1950 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1951 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1952 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1953 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1954 InOp1.getValueType(), N->getOperand(0),
1955 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1958 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1959 assert(N->getValueType(0).isVector() ==
1960 N->getOperand(0).getValueType().isVector() &&
1961 "Scalar/Vector type mismatch");
1962 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
1964 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1965 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1966 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1967 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1968 InOp1, InOp2, N->getOperand(2));
1971 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1972 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1973 return DAG.getUNDEF(WidenVT);
1976 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1977 EVT VT = N->getValueType(0);
1978 DebugLoc dl = N->getDebugLoc();
1980 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1981 unsigned NumElts = VT.getVectorNumElements();
1982 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1984 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1985 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1987 // Adjust mask based on new input vector length.
1988 SmallVector<int, 16> NewMask;
1989 for (unsigned i = 0; i != NumElts; ++i) {
1990 int Idx = N->getMaskElt(i);
1991 if (Idx < (int)NumElts)
1992 NewMask.push_back(Idx);
1994 NewMask.push_back(Idx - NumElts + WidenNumElts);
1996 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1997 NewMask.push_back(-1);
1998 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2001 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2002 assert(N->getValueType(0).isVector() &&
2003 N->getOperand(0).getValueType().isVector() &&
2004 "Operands must be vectors");
2005 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2006 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2008 SDValue InOp1 = N->getOperand(0);
2009 EVT InVT = InOp1.getValueType();
2010 assert(InVT.isVector() && "can not widen non vector type");
2011 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2012 InVT.getVectorElementType(), WidenNumElts);
2013 InOp1 = GetWidenedVector(InOp1);
2014 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2016 // Assume that the input and output will be widen appropriately. If not,
2017 // we will have to unroll it at some point.
2018 assert(InOp1.getValueType() == WidenInVT &&
2019 InOp2.getValueType() == WidenInVT &&
2020 "Input not widened to expected type!");
2022 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2023 WidenVT, InOp1, InOp2, N->getOperand(2));
2027 //===----------------------------------------------------------------------===//
2028 // Widen Vector Operand
2029 //===----------------------------------------------------------------------===//
2030 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
2031 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
2034 SDValue Res = SDValue();
2036 switch (N->getOpcode()) {
2039 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
2043 llvm_unreachable("Do not know how to widen this operator's operand!");
2045 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2046 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2047 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2048 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2049 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2050 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2052 case ISD::FP_EXTEND:
2053 case ISD::FP_TO_SINT:
2054 case ISD::FP_TO_UINT:
2055 case ISD::SINT_TO_FP:
2056 case ISD::UINT_TO_FP:
2058 case ISD::SIGN_EXTEND:
2059 case ISD::ZERO_EXTEND:
2060 case ISD::ANY_EXTEND:
2061 Res = WidenVecOp_Convert(N);
2065 // If Res is null, the sub-method took care of registering the result.
2066 if (!Res.getNode()) return false;
2068 // If the result is N, the sub-method updated N in place. Tell the legalizer
2070 if (Res.getNode() == N)
2074 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2075 "Invalid operand expansion");
2077 ReplaceValueWith(SDValue(N, 0), Res);
2081 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2082 // Since the result is legal and the input is illegal, it is unlikely
2083 // that we can fix the input to a legal type so unroll the convert
2084 // into some scalar code and create a nasty build vector.
2085 EVT VT = N->getValueType(0);
2086 EVT EltVT = VT.getVectorElementType();
2087 DebugLoc dl = N->getDebugLoc();
2088 unsigned NumElts = VT.getVectorNumElements();
2089 SDValue InOp = N->getOperand(0);
2090 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2091 InOp = GetWidenedVector(InOp);
2092 EVT InVT = InOp.getValueType();
2093 EVT InEltVT = InVT.getVectorElementType();
2095 unsigned Opcode = N->getOpcode();
2096 SmallVector<SDValue, 16> Ops(NumElts);
2097 for (unsigned i=0; i < NumElts; ++i)
2098 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2099 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2100 DAG.getIntPtrConstant(i)));
2102 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2105 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2106 EVT VT = N->getValueType(0);
2107 SDValue InOp = GetWidenedVector(N->getOperand(0));
2108 EVT InWidenVT = InOp.getValueType();
2109 DebugLoc dl = N->getDebugLoc();
2111 // Check if we can convert between two legal vector types and extract.
2112 unsigned InWidenSize = InWidenVT.getSizeInBits();
2113 unsigned Size = VT.getSizeInBits();
2114 // x86mmx is not an acceptable vector element type, so don't try.
2115 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2116 unsigned NewNumElts = InWidenSize / Size;
2117 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2118 if (TLI.isTypeLegal(NewVT)) {
2119 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2120 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2121 DAG.getIntPtrConstant(0));
2125 return CreateStackStoreLoad(InOp, VT);
2128 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2129 // If the input vector is not legal, it is likely that we will not find a
2130 // legal vector of the same size. Replace the concatenate vector with a
2131 // nasty build vector.
2132 EVT VT = N->getValueType(0);
2133 EVT EltVT = VT.getVectorElementType();
2134 DebugLoc dl = N->getDebugLoc();
2135 unsigned NumElts = VT.getVectorNumElements();
2136 SmallVector<SDValue, 16> Ops(NumElts);
2138 EVT InVT = N->getOperand(0).getValueType();
2139 unsigned NumInElts = InVT.getVectorNumElements();
2142 unsigned NumOperands = N->getNumOperands();
2143 for (unsigned i=0; i < NumOperands; ++i) {
2144 SDValue InOp = N->getOperand(i);
2145 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2146 InOp = GetWidenedVector(InOp);
2147 for (unsigned j=0; j < NumInElts; ++j)
2148 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2149 DAG.getIntPtrConstant(j));
2151 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2154 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2155 SDValue InOp = GetWidenedVector(N->getOperand(0));
2156 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2157 N->getValueType(0), InOp, N->getOperand(1));
2160 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2161 SDValue InOp = GetWidenedVector(N->getOperand(0));
2162 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2163 N->getValueType(0), InOp, N->getOperand(1));
2166 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2167 // We have to widen the value but we want only to store the original
2169 StoreSDNode *ST = cast<StoreSDNode>(N);
2171 SmallVector<SDValue, 16> StChain;
2172 if (ST->isTruncatingStore())
2173 GenWidenVectorTruncStores(StChain, ST);
2175 GenWidenVectorStores(StChain, ST);
2177 if (StChain.size() == 1)
2180 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2181 MVT::Other,&StChain[0],StChain.size());
2184 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2185 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2186 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2187 DebugLoc dl = N->getDebugLoc();
2189 // WARNING: In this code we widen the compare instruction with garbage.
2190 // This garbage may contain denormal floats which may be slow. Is this a real
2191 // concern ? Should we zero the unused lanes if this is a float compare ?
2193 // Get a new SETCC node to compare the newly widened operands.
2194 // Only some of the compared elements are legal.
2195 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType());
2196 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2197 SVT, InOp0, InOp1, N->getOperand(2));
2199 // Extract the needed results from the result vector.
2200 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2201 SVT.getVectorElementType(),
2202 N->getValueType(0).getVectorNumElements());
2203 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2204 ResVT, WideSETCC, DAG.getIntPtrConstant(0));
2206 return PromoteTargetBoolean(CC, N->getValueType(0));
2210 //===----------------------------------------------------------------------===//
2211 // Vector Widening Utilities
2212 //===----------------------------------------------------------------------===//
2214 // Utility function to find the type to chop up a widen vector for load/store
2215 // TLI: Target lowering used to determine legal types.
2216 // Width: Width left need to load/store.
2217 // WidenVT: The widen vector type to load to/store from
2218 // Align: If 0, don't allow use of a wider type
2219 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2221 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2222 unsigned Width, EVT WidenVT,
2223 unsigned Align = 0, unsigned WidenEx = 0) {
2224 EVT WidenEltVT = WidenVT.getVectorElementType();
2225 unsigned WidenWidth = WidenVT.getSizeInBits();
2226 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2227 unsigned AlignInBits = Align*8;
2229 // If we have one element to load/store, return it.
2230 EVT RetVT = WidenEltVT;
2231 if (Width == WidenEltWidth)
2234 // See if there is larger legal integer than the element type to load/store
2236 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2237 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2238 EVT MemVT((MVT::SimpleValueType) VT);
2239 unsigned MemVTWidth = MemVT.getSizeInBits();
2240 if (MemVT.getSizeInBits() <= WidenEltWidth)
2242 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2243 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2244 (MemVTWidth <= Width ||
2245 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2251 // See if there is a larger vector type to load/store that has the same vector
2252 // element type and is evenly divisible with the WidenVT.
2253 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2254 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2255 EVT MemVT = (MVT::SimpleValueType) VT;
2256 unsigned MemVTWidth = MemVT.getSizeInBits();
2257 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2258 (WidenWidth % MemVTWidth) == 0 &&
2259 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2260 (MemVTWidth <= Width ||
2261 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2262 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2270 // Builds a vector type from scalar loads
2271 // VecTy: Resulting Vector type
2272 // LDOps: Load operators to build a vector type
2273 // [Start,End) the list of loads to use.
2274 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2275 SmallVector<SDValue, 16>& LdOps,
2276 unsigned Start, unsigned End) {
2277 DebugLoc dl = LdOps[Start].getDebugLoc();
2278 EVT LdTy = LdOps[Start].getValueType();
2279 unsigned Width = VecTy.getSizeInBits();
2280 unsigned NumElts = Width / LdTy.getSizeInBits();
2281 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2284 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2286 for (unsigned i = Start + 1; i != End; ++i) {
2287 EVT NewLdTy = LdOps[i].getValueType();
2288 if (NewLdTy != LdTy) {
2289 NumElts = Width / NewLdTy.getSizeInBits();
2290 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2291 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2292 // Readjust position and vector position based on new load type
2293 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2296 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2297 DAG.getIntPtrConstant(Idx++));
2299 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2302 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2304 // The strategy assumes that we can efficiently load powers of two widths.
2305 // The routines chops the vector into the largest vector loads with the same
2306 // element type or scalar loads and then recombines it to the widen vector
2308 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2309 unsigned WidenWidth = WidenVT.getSizeInBits();
2310 EVT LdVT = LD->getMemoryVT();
2311 DebugLoc dl = LD->getDebugLoc();
2312 assert(LdVT.isVector() && WidenVT.isVector());
2313 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2316 SDValue Chain = LD->getChain();
2317 SDValue BasePtr = LD->getBasePtr();
2318 unsigned Align = LD->getAlignment();
2319 bool isVolatile = LD->isVolatile();
2320 bool isNonTemporal = LD->isNonTemporal();
2321 bool isInvariant = LD->isInvariant();
2323 int LdWidth = LdVT.getSizeInBits();
2324 int WidthDiff = WidenWidth - LdWidth; // Difference
2325 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2327 // Find the vector type that can load from.
2328 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2329 int NewVTWidth = NewVT.getSizeInBits();
2330 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2331 isVolatile, isNonTemporal, isInvariant, Align);
2332 LdChain.push_back(LdOp.getValue(1));
2334 // Check if we can load the element with one instruction
2335 if (LdWidth <= NewVTWidth) {
2336 if (!NewVT.isVector()) {
2337 unsigned NumElts = WidenWidth / NewVTWidth;
2338 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2339 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2340 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2342 if (NewVT == WidenVT)
2345 assert(WidenWidth % NewVTWidth == 0);
2346 unsigned NumConcat = WidenWidth / NewVTWidth;
2347 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2348 SDValue UndefVal = DAG.getUNDEF(NewVT);
2349 ConcatOps[0] = LdOp;
2350 for (unsigned i = 1; i != NumConcat; ++i)
2351 ConcatOps[i] = UndefVal;
2352 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2356 // Load vector by using multiple loads from largest vector to scalar
2357 SmallVector<SDValue, 16> LdOps;
2358 LdOps.push_back(LdOp);
2360 LdWidth -= NewVTWidth;
2361 unsigned Offset = 0;
2363 while (LdWidth > 0) {
2364 unsigned Increment = NewVTWidth / 8;
2365 Offset += Increment;
2366 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2367 DAG.getIntPtrConstant(Increment));
2370 if (LdWidth < NewVTWidth) {
2371 // Our current type we are using is too large, find a better size
2372 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2373 NewVTWidth = NewVT.getSizeInBits();
2374 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2375 LD->getPointerInfo().getWithOffset(Offset),
2377 isNonTemporal, isInvariant,
2378 MinAlign(Align, Increment));
2379 LdChain.push_back(L.getValue(1));
2380 if (L->getValueType(0).isVector()) {
2381 SmallVector<SDValue, 16> Loads;
2383 unsigned size = L->getValueSizeInBits(0);
2384 while (size < LdOp->getValueSizeInBits(0)) {
2385 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
2386 size += L->getValueSizeInBits(0);
2388 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
2389 &Loads[0], Loads.size());
2392 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2393 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2394 isNonTemporal, isInvariant, MinAlign(Align, Increment));
2395 LdChain.push_back(L.getValue(1));
2401 LdWidth -= NewVTWidth;
2404 // Build the vector from the loads operations
2405 unsigned End = LdOps.size();
2406 if (!LdOps[0].getValueType().isVector())
2407 // All the loads are scalar loads.
2408 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2410 // If the load contains vectors, build the vector using concat vector.
2411 // All of the vectors used to loads are power of 2 and the scalars load
2412 // can be combined to make a power of 2 vector.
2413 SmallVector<SDValue, 16> ConcatOps(End);
2416 EVT LdTy = LdOps[i].getValueType();
2417 // First combine the scalar loads to a vector
2418 if (!LdTy.isVector()) {
2419 for (--i; i >= 0; --i) {
2420 LdTy = LdOps[i].getValueType();
2421 if (LdTy.isVector())
2424 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2426 ConcatOps[--Idx] = LdOps[i];
2427 for (--i; i >= 0; --i) {
2428 EVT NewLdTy = LdOps[i].getValueType();
2429 if (NewLdTy != LdTy) {
2430 // Create a larger vector
2431 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2432 &ConcatOps[Idx], End - Idx);
2436 ConcatOps[--Idx] = LdOps[i];
2439 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2440 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2441 &ConcatOps[Idx], End - Idx);
2443 // We need to fill the rest with undefs to build the vector
2444 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2445 SmallVector<SDValue, 16> WidenOps(NumOps);
2446 SDValue UndefVal = DAG.getUNDEF(LdTy);
2449 for (; i != End-Idx; ++i)
2450 WidenOps[i] = ConcatOps[Idx+i];
2451 for (; i != NumOps; ++i)
2452 WidenOps[i] = UndefVal;
2454 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2458 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2460 ISD::LoadExtType ExtType) {
2461 // For extension loads, it may not be more efficient to chop up the vector
2462 // and then extended it. Instead, we unroll the load and build a new vector.
2463 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2464 EVT LdVT = LD->getMemoryVT();
2465 DebugLoc dl = LD->getDebugLoc();
2466 assert(LdVT.isVector() && WidenVT.isVector());
2469 SDValue Chain = LD->getChain();
2470 SDValue BasePtr = LD->getBasePtr();
2471 unsigned Align = LD->getAlignment();
2472 bool isVolatile = LD->isVolatile();
2473 bool isNonTemporal = LD->isNonTemporal();
2475 EVT EltVT = WidenVT.getVectorElementType();
2476 EVT LdEltVT = LdVT.getVectorElementType();
2477 unsigned NumElts = LdVT.getVectorNumElements();
2479 // Load each element and widen
2480 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2481 SmallVector<SDValue, 16> Ops(WidenNumElts);
2482 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2483 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2484 LD->getPointerInfo(),
2485 LdEltVT, isVolatile, isNonTemporal, Align);
2486 LdChain.push_back(Ops[0].getValue(1));
2487 unsigned i = 0, Offset = Increment;
2488 for (i=1; i < NumElts; ++i, Offset += Increment) {
2489 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2490 BasePtr, DAG.getIntPtrConstant(Offset));
2491 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2492 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2493 isVolatile, isNonTemporal, Align);
2494 LdChain.push_back(Ops[i].getValue(1));
2497 // Fill the rest with undefs
2498 SDValue UndefVal = DAG.getUNDEF(EltVT);
2499 for (; i != WidenNumElts; ++i)
2502 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2506 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2508 // The strategy assumes that we can efficiently store powers of two widths.
2509 // The routines chops the vector into the largest vector stores with the same
2510 // element type or scalar stores.
2511 SDValue Chain = ST->getChain();
2512 SDValue BasePtr = ST->getBasePtr();
2513 unsigned Align = ST->getAlignment();
2514 bool isVolatile = ST->isVolatile();
2515 bool isNonTemporal = ST->isNonTemporal();
2516 SDValue ValOp = GetWidenedVector(ST->getValue());
2517 DebugLoc dl = ST->getDebugLoc();
2519 EVT StVT = ST->getMemoryVT();
2520 unsigned StWidth = StVT.getSizeInBits();
2521 EVT ValVT = ValOp.getValueType();
2522 unsigned ValWidth = ValVT.getSizeInBits();
2523 EVT ValEltVT = ValVT.getVectorElementType();
2524 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2525 assert(StVT.getVectorElementType() == ValEltVT);
2527 int Idx = 0; // current index to store
2528 unsigned Offset = 0; // offset from base to store
2529 while (StWidth != 0) {
2530 // Find the largest vector type we can store with
2531 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2532 unsigned NewVTWidth = NewVT.getSizeInBits();
2533 unsigned Increment = NewVTWidth / 8;
2534 if (NewVT.isVector()) {
2535 unsigned NumVTElts = NewVT.getVectorNumElements();
2537 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2538 DAG.getIntPtrConstant(Idx));
2539 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2540 ST->getPointerInfo().getWithOffset(Offset),
2541 isVolatile, isNonTemporal,
2542 MinAlign(Align, Offset)));
2543 StWidth -= NewVTWidth;
2544 Offset += Increment;
2546 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2547 DAG.getIntPtrConstant(Increment));
2548 } while (StWidth != 0 && StWidth >= NewVTWidth);
2550 // Cast the vector to the scalar type we can store
2551 unsigned NumElts = ValWidth / NewVTWidth;
2552 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2553 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2554 // Readjust index position based on new vector type
2555 Idx = Idx * ValEltWidth / NewVTWidth;
2557 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2558 DAG.getIntPtrConstant(Idx++));
2559 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2560 ST->getPointerInfo().getWithOffset(Offset),
2561 isVolatile, isNonTemporal,
2562 MinAlign(Align, Offset)));
2563 StWidth -= NewVTWidth;
2564 Offset += Increment;
2565 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2566 DAG.getIntPtrConstant(Increment));
2567 } while (StWidth != 0 && StWidth >= NewVTWidth);
2568 // Restore index back to be relative to the original widen element type
2569 Idx = Idx * NewVTWidth / ValEltWidth;
2575 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2577 // For extension loads, it may not be more efficient to truncate the vector
2578 // and then store it. Instead, we extract each element and then store it.
2579 SDValue Chain = ST->getChain();
2580 SDValue BasePtr = ST->getBasePtr();
2581 unsigned Align = ST->getAlignment();
2582 bool isVolatile = ST->isVolatile();
2583 bool isNonTemporal = ST->isNonTemporal();
2584 SDValue ValOp = GetWidenedVector(ST->getValue());
2585 DebugLoc dl = ST->getDebugLoc();
2587 EVT StVT = ST->getMemoryVT();
2588 EVT ValVT = ValOp.getValueType();
2590 // It must be true that we the widen vector type is bigger than where
2591 // we need to store.
2592 assert(StVT.isVector() && ValOp.getValueType().isVector());
2593 assert(StVT.bitsLT(ValOp.getValueType()));
2595 // For truncating stores, we can not play the tricks of chopping legal
2596 // vector types and bit cast it to the right type. Instead, we unroll
2598 EVT StEltVT = StVT.getVectorElementType();
2599 EVT ValEltVT = ValVT.getVectorElementType();
2600 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2601 unsigned NumElts = StVT.getVectorNumElements();
2602 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2603 DAG.getIntPtrConstant(0));
2604 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2605 ST->getPointerInfo(), StEltVT,
2606 isVolatile, isNonTemporal, Align));
2607 unsigned Offset = Increment;
2608 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2609 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2610 BasePtr, DAG.getIntPtrConstant(Offset));
2611 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2612 DAG.getIntPtrConstant(0));
2613 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2614 ST->getPointerInfo().getWithOffset(Offset),
2615 StEltVT, isVolatile, isNonTemporal,
2616 MinAlign(Align, Offset)));
2620 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2621 /// input vector must have the same element type as NVT.
2622 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2623 // Note that InOp might have been widened so it might already have
2624 // the right width or it might need be narrowed.
2625 EVT InVT = InOp.getValueType();
2626 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2627 "input and widen element type must match");
2628 DebugLoc dl = InOp.getDebugLoc();
2630 // Check if InOp already has the right width.
2634 unsigned InNumElts = InVT.getVectorNumElements();
2635 unsigned WidenNumElts = NVT.getVectorNumElements();
2636 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2637 unsigned NumConcat = WidenNumElts / InNumElts;
2638 SmallVector<SDValue, 16> Ops(NumConcat);
2639 SDValue UndefVal = DAG.getUNDEF(InVT);
2641 for (unsigned i = 1; i != NumConcat; ++i)
2644 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2647 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2648 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2649 DAG.getIntPtrConstant(0));
2651 // Fall back to extract and build.
2652 SmallVector<SDValue, 16> Ops(WidenNumElts);
2653 EVT EltVT = NVT.getVectorElementType();
2654 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2656 for (Idx = 0; Idx < MinNumElts; ++Idx)
2657 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2658 DAG.getIntPtrConstant(Idx));
2660 SDValue UndefVal = DAG.getUNDEF(EltVT);
2661 for ( ; Idx < WidenNumElts; ++Idx)
2662 Ops[Idx] = UndefVal;
2663 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);