1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_SETCC(N, Lo, Hi);
606 case ISD::VECTOR_SHUFFLE:
607 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
611 case ISD::CONVERT_RNDSAT:
614 case ISD::CTLZ_ZERO_UNDEF:
615 case ISD::CTTZ_ZERO_UNDEF:
626 case ISD::FNEARBYINT:
630 case ISD::FP_TO_SINT:
631 case ISD::FP_TO_UINT:
637 case ISD::SINT_TO_FP:
639 case ISD::UINT_TO_FP:
640 SplitVecRes_UnaryOp(N, Lo, Hi);
643 case ISD::ANY_EXTEND:
644 case ISD::SIGN_EXTEND:
645 case ISD::ZERO_EXTEND:
646 SplitVecRes_ExtendOp(N, Lo, Hi);
671 SplitVecRes_BinOp(N, Lo, Hi);
674 SplitVecRes_TernaryOp(N, Lo, Hi);
678 // If Lo/Hi is null, the sub-method took care of registering results etc.
680 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
683 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
685 SDValue LHSLo, LHSHi;
686 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
687 SDValue RHSLo, RHSHi;
688 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
691 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
692 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
695 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
697 SDValue Op0Lo, Op0Hi;
698 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
699 SDValue Op1Lo, Op1Hi;
700 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
701 SDValue Op2Lo, Op2Hi;
702 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
705 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
706 Op0Lo, Op1Lo, Op2Lo);
707 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
708 Op0Hi, Op1Hi, Op2Hi);
711 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
713 // We know the result is a vector. The input may be either a vector or a
716 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
719 SDValue InOp = N->getOperand(0);
720 EVT InVT = InOp.getValueType();
722 // Handle some special cases efficiently.
723 switch (getTypeAction(InVT)) {
724 case TargetLowering::TypeLegal:
725 case TargetLowering::TypePromoteInteger:
726 case TargetLowering::TypeSoftenFloat:
727 case TargetLowering::TypeScalarizeVector:
728 case TargetLowering::TypeWidenVector:
730 case TargetLowering::TypeExpandInteger:
731 case TargetLowering::TypeExpandFloat:
732 // A scalar to vector conversion, where the scalar needs expansion.
733 // If the vector is being split in two then we can just convert the
736 GetExpandedOp(InOp, Lo, Hi);
737 if (TLI.isBigEndian())
739 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
740 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
744 case TargetLowering::TypeSplitVector:
745 // If the input is a vector that needs to be split, convert each split
746 // piece of the input now.
747 GetSplitVector(InOp, Lo, Hi);
748 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
749 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
753 // In the general case, convert the input to an integer and split it by hand.
754 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
755 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
756 if (TLI.isBigEndian())
757 std::swap(LoIntVT, HiIntVT);
759 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
761 if (TLI.isBigEndian())
763 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
764 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
767 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
771 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
772 unsigned LoNumElts = LoVT.getVectorNumElements();
773 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
774 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
776 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
777 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
780 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
782 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
784 unsigned NumSubvectors = N->getNumOperands() / 2;
785 if (NumSubvectors == 1) {
786 Lo = N->getOperand(0);
787 Hi = N->getOperand(1);
792 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
794 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
795 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
797 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
798 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
801 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
803 SDValue Vec = N->getOperand(0);
804 SDValue Idx = N->getOperand(1);
808 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
811 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
813 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
814 TLI.getVectorIdxTy()));
817 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
819 SDValue Vec = N->getOperand(0);
820 SDValue SubVec = N->getOperand(1);
821 SDValue Idx = N->getOperand(2);
823 GetSplitVector(Vec, Lo, Hi);
825 // Spill the vector to the stack.
826 EVT VecVT = Vec.getValueType();
827 EVT SubVecVT = VecVT.getVectorElementType();
828 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
829 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
830 MachinePointerInfo(), false, false, 0);
832 // Store the new subvector into the specified index.
833 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
834 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
835 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
836 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
839 // Load the Lo part from the stack slot.
840 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
841 false, false, false, 0);
843 // Increment the pointer to the other part.
844 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
846 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
847 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
849 // Load the Hi part from the stack slot.
850 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
851 false, false, false, MinAlign(Alignment, IncrementSize));
854 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
857 GetSplitVector(N->getOperand(0), Lo, Hi);
858 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
859 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
862 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
864 SDValue LHSLo, LHSHi;
865 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
869 std::tie(LoVT, HiVT) =
870 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
872 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
873 DAG.getValueType(LoVT));
874 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
875 DAG.getValueType(HiVT));
878 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
880 SDValue Vec = N->getOperand(0);
881 SDValue Elt = N->getOperand(1);
882 SDValue Idx = N->getOperand(2);
884 GetSplitVector(Vec, Lo, Hi);
886 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
887 unsigned IdxVal = CIdx->getZExtValue();
888 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
889 if (IdxVal < LoNumElts)
890 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
891 Lo.getValueType(), Lo, Elt, Idx);
893 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
894 DAG.getConstant(IdxVal - LoNumElts,
895 TLI.getVectorIdxTy()));
899 // See if the target wants to custom expand this node.
900 if (CustomLowerNode(N, N->getValueType(0), true))
903 // Spill the vector to the stack.
904 EVT VecVT = Vec.getValueType();
905 EVT EltVT = VecVT.getVectorElementType();
906 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
907 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
908 MachinePointerInfo(), false, false, 0);
910 // Store the new element. This may be larger than the vector element type,
911 // so use a truncating store.
912 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
913 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
915 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
916 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
919 // Load the Lo part from the stack slot.
920 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
921 false, false, false, 0);
923 // Increment the pointer to the other part.
924 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
925 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
926 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
928 // Load the Hi part from the stack slot.
929 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
930 false, false, false, MinAlign(Alignment, IncrementSize));
933 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
937 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
938 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
939 Hi = DAG.getUNDEF(HiVT);
942 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
944 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
947 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
949 ISD::LoadExtType ExtType = LD->getExtensionType();
950 SDValue Ch = LD->getChain();
951 SDValue Ptr = LD->getBasePtr();
952 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
953 EVT MemoryVT = LD->getMemoryVT();
954 unsigned Alignment = LD->getOriginalAlignment();
955 bool isVolatile = LD->isVolatile();
956 bool isNonTemporal = LD->isNonTemporal();
957 bool isInvariant = LD->isInvariant();
958 AAMDNodes AAInfo = LD->getAAInfo();
960 EVT LoMemVT, HiMemVT;
961 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
963 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
964 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
965 isInvariant, Alignment, AAInfo);
967 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
968 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
969 DAG.getConstant(IncrementSize, Ptr.getValueType()));
970 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
971 LD->getPointerInfo().getWithOffset(IncrementSize),
972 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
975 // Build a factor node to remember that this load is independent of the
977 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
980 // Legalized the chain result - switch anything that used the old chain to
982 ReplaceValueWith(SDValue(LD, 1), Ch);
985 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
986 SDValue &Lo, SDValue &Hi) {
989 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
991 SDValue Ch = MLD->getChain();
992 SDValue Ptr = MLD->getBasePtr();
993 SDValue Mask = MLD->getMask();
994 unsigned Alignment = MLD->getOriginalAlignment();
995 ISD::LoadExtType ExtType = MLD->getExtensionType();
997 // if Alignment is equal to the vector size,
998 // take the half of it for the second part
999 unsigned SecondHalfAlignment =
1000 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1001 Alignment/2 : Alignment;
1003 SDValue MaskLo, MaskHi;
1004 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1006 EVT MemoryVT = MLD->getMemoryVT();
1007 EVT LoMemVT, HiMemVT;
1008 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1010 SDValue Src0 = MLD->getSrc0();
1011 SDValue Src0Lo, Src0Hi;
1012 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1014 MachineMemOperand *MMO = DAG.getMachineFunction().
1015 getMachineMemOperand(MLD->getPointerInfo(),
1016 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1017 Alignment, MLD->getAAInfo(), MLD->getRanges());
1019 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1022 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1024 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1026 MMO = DAG.getMachineFunction().
1027 getMachineMemOperand(MLD->getPointerInfo(),
1028 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1029 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1031 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1035 // Build a factor node to remember that this load is independent of the
1037 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1040 // Legalized the chain result - switch anything that used the old chain to
1042 ReplaceValueWith(SDValue(MLD, 1), Ch);
1046 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1047 assert(N->getValueType(0).isVector() &&
1048 N->getOperand(0).getValueType().isVector() &&
1049 "Operand types must be vectors");
1053 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1056 SDValue LL, LH, RL, RH;
1057 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1058 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1060 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1061 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1064 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1066 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1069 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1071 // If the input also splits, handle it directly for a compile time speedup.
1072 // Otherwise split it by hand.
1073 EVT InVT = N->getOperand(0).getValueType();
1074 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1075 GetSplitVector(N->getOperand(0), Lo, Hi);
1077 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1079 if (N->getOpcode() == ISD::FP_ROUND) {
1080 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1081 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1082 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1083 SDValue DTyOpLo = DAG.getValueType(LoVT);
1084 SDValue DTyOpHi = DAG.getValueType(HiVT);
1085 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1086 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1087 SDValue RndOp = N->getOperand(3);
1088 SDValue SatOp = N->getOperand(4);
1089 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1090 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1092 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1095 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1096 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1100 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1103 EVT SrcVT = N->getOperand(0).getValueType();
1104 EVT DestVT = N->getValueType(0);
1106 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1108 // We can do better than a generic split operation if the extend is doing
1109 // more than just doubling the width of the elements and the following are
1111 // - The number of vector elements is even,
1112 // - the source type is legal,
1113 // - the type of a split source is illegal,
1114 // - the type of an extended (by doubling element size) source is legal, and
1115 // - the type of that extended source when split is legal.
1117 // This won't necessarily completely legalize the operation, but it will
1118 // more effectively move in the right direction and prevent falling down
1119 // to scalarization in many cases due to the input vector being split too
1121 unsigned NumElements = SrcVT.getVectorNumElements();
1122 if ((NumElements & 1) == 0 &&
1123 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1124 LLVMContext &Ctx = *DAG.getContext();
1125 EVT NewSrcVT = EVT::getVectorVT(
1126 Ctx, EVT::getIntegerVT(
1127 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1130 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1131 EVT SplitLoVT, SplitHiVT;
1132 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1133 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1134 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1135 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1136 N->dump(&DAG); dbgs() << "\n");
1137 // Extend the source vector by one step.
1139 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1140 // Get the low and high halves of the new, extended one step, vector.
1141 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1142 // Extend those vector halves the rest of the way.
1143 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1144 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1148 // Fall back to the generic unary operator splitting otherwise.
1149 SplitVecRes_UnaryOp(N, Lo, Hi);
1152 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1153 SDValue &Lo, SDValue &Hi) {
1154 // The low and high parts of the original input give four input vectors.
1157 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1158 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1159 EVT NewVT = Inputs[0].getValueType();
1160 unsigned NewElts = NewVT.getVectorNumElements();
1162 // If Lo or Hi uses elements from at most two of the four input vectors, then
1163 // express it as a vector shuffle of those two inputs. Otherwise extract the
1164 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1165 SmallVector<int, 16> Ops;
1166 for (unsigned High = 0; High < 2; ++High) {
1167 SDValue &Output = High ? Hi : Lo;
1169 // Build a shuffle mask for the output, discovering on the fly which
1170 // input vectors to use as shuffle operands (recorded in InputUsed).
1171 // If building a suitable shuffle vector proves too hard, then bail
1172 // out with useBuildVector set.
1173 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1174 unsigned FirstMaskIdx = High * NewElts;
1175 bool useBuildVector = false;
1176 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1177 // The mask element. This indexes into the input.
1178 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1180 // The input vector this mask element indexes into.
1181 unsigned Input = (unsigned)Idx / NewElts;
1183 if (Input >= array_lengthof(Inputs)) {
1184 // The mask element does not index into any input vector.
1189 // Turn the index into an offset from the start of the input vector.
1190 Idx -= Input * NewElts;
1192 // Find or create a shuffle vector operand to hold this input.
1194 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1195 if (InputUsed[OpNo] == Input) {
1196 // This input vector is already an operand.
1198 } else if (InputUsed[OpNo] == -1U) {
1199 // Create a new operand for this input vector.
1200 InputUsed[OpNo] = Input;
1205 if (OpNo >= array_lengthof(InputUsed)) {
1206 // More than two input vectors used! Give up on trying to create a
1207 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1208 useBuildVector = true;
1212 // Add the mask index for the new shuffle vector.
1213 Ops.push_back(Idx + OpNo * NewElts);
1216 if (useBuildVector) {
1217 EVT EltVT = NewVT.getVectorElementType();
1218 SmallVector<SDValue, 16> SVOps;
1220 // Extract the input elements by hand.
1221 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1222 // The mask element. This indexes into the input.
1223 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1225 // The input vector this mask element indexes into.
1226 unsigned Input = (unsigned)Idx / NewElts;
1228 if (Input >= array_lengthof(Inputs)) {
1229 // The mask element is "undef" or indexes off the end of the input.
1230 SVOps.push_back(DAG.getUNDEF(EltVT));
1234 // Turn the index into an offset from the start of the input vector.
1235 Idx -= Input * NewElts;
1237 // Extract the vector element by hand.
1238 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1239 Inputs[Input], DAG.getConstant(Idx,
1240 TLI.getVectorIdxTy())));
1243 // Construct the Lo/Hi output using a BUILD_VECTOR.
1244 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1245 } else if (InputUsed[0] == -1U) {
1246 // No input vectors were used! The result is undefined.
1247 Output = DAG.getUNDEF(NewVT);
1249 SDValue Op0 = Inputs[InputUsed[0]];
1250 // If only one input was used, use an undefined vector for the other.
1251 SDValue Op1 = InputUsed[1] == -1U ?
1252 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1253 // At least one input vector was used. Create a new shuffle vector.
1254 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1262 //===----------------------------------------------------------------------===//
1263 // Operand Vector Splitting
1264 //===----------------------------------------------------------------------===//
1266 /// SplitVectorOperand - This method is called when the specified operand of the
1267 /// specified node is found to need vector splitting. At this point, all of the
1268 /// result types of the node are known to be legal, but other operands of the
1269 /// node may need legalization as well as the specified one.
1270 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1271 DEBUG(dbgs() << "Split node operand: ";
1274 SDValue Res = SDValue();
1276 // See if the target wants to custom split this node.
1277 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1280 if (!Res.getNode()) {
1281 switch (N->getOpcode()) {
1284 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1288 report_fatal_error("Do not know how to split this operator's "
1291 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1292 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1293 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1294 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1295 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1297 Res = SplitVecOp_TruncateHelper(N);
1299 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1301 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1304 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1307 Res = SplitVecOp_VSELECT(N, OpNo);
1309 case ISD::FP_TO_SINT:
1310 case ISD::FP_TO_UINT:
1311 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1312 Res = SplitVecOp_TruncateHelper(N);
1314 Res = SplitVecOp_UnaryOp(N);
1316 case ISD::SINT_TO_FP:
1317 case ISD::UINT_TO_FP:
1318 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1319 Res = SplitVecOp_TruncateHelper(N);
1321 Res = SplitVecOp_UnaryOp(N);
1326 case ISD::FP_EXTEND:
1327 case ISD::SIGN_EXTEND:
1328 case ISD::ZERO_EXTEND:
1329 case ISD::ANY_EXTEND:
1331 Res = SplitVecOp_UnaryOp(N);
1336 // If the result is null, the sub-method took care of registering results etc.
1337 if (!Res.getNode()) return false;
1339 // If the result is N, the sub-method updated N in place. Tell the legalizer
1341 if (Res.getNode() == N)
1344 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1345 "Invalid operand expansion");
1347 ReplaceValueWith(SDValue(N, 0), Res);
1351 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1352 // The only possibility for an illegal operand is the mask, since result type
1353 // legalization would have handled this node already otherwise.
1354 assert(OpNo == 0 && "Illegal operand must be mask");
1356 SDValue Mask = N->getOperand(0);
1357 SDValue Src0 = N->getOperand(1);
1358 SDValue Src1 = N->getOperand(2);
1359 EVT Src0VT = Src0.getValueType();
1361 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1364 GetSplitVector(N->getOperand(0), Lo, Hi);
1365 assert(Lo.getValueType() == Hi.getValueType() &&
1366 "Lo and Hi have differing types");
1369 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1370 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1372 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1373 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1374 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1375 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1378 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1380 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1382 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1385 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1386 // The result has a legal vector type, but the input needs splitting.
1387 EVT ResVT = N->getValueType(0);
1390 GetSplitVector(N->getOperand(0), Lo, Hi);
1391 EVT InVT = Lo.getValueType();
1393 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1394 InVT.getVectorNumElements());
1396 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1397 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1399 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1402 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1403 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1404 // end up being split all the way down to individual components. Convert the
1405 // split pieces into integers and reassemble.
1407 GetSplitVector(N->getOperand(0), Lo, Hi);
1408 Lo = BitConvertToInteger(Lo);
1409 Hi = BitConvertToInteger(Hi);
1411 if (TLI.isBigEndian())
1414 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1415 JoinIntegers(Lo, Hi));
1418 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1419 // We know that the extracted result type is legal.
1420 EVT SubVT = N->getValueType(0);
1421 SDValue Idx = N->getOperand(1);
1424 GetSplitVector(N->getOperand(0), Lo, Hi);
1426 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1427 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1429 if (IdxVal < LoElts) {
1430 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1431 "Extracted subvector crosses vector split!");
1432 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1434 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1435 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1439 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1440 SDValue Vec = N->getOperand(0);
1441 SDValue Idx = N->getOperand(1);
1442 EVT VecVT = Vec.getValueType();
1444 if (isa<ConstantSDNode>(Idx)) {
1445 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1446 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1449 GetSplitVector(Vec, Lo, Hi);
1451 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1453 if (IdxVal < LoElts)
1454 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1455 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1456 DAG.getConstant(IdxVal - LoElts,
1457 Idx.getValueType())), 0);
1460 // See if the target wants to custom expand this node.
1461 if (CustomLowerNode(N, N->getValueType(0), true))
1464 // Store the vector to the stack.
1465 EVT EltVT = VecVT.getVectorElementType();
1467 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1468 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1469 MachinePointerInfo(), false, false, 0);
1471 // Load back the required element.
1472 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1473 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1474 MachinePointerInfo(), EltVT, false, false, false, 0);
1477 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1479 SDValue Ch = N->getChain();
1480 SDValue Ptr = N->getBasePtr();
1481 SDValue Mask = N->getMask();
1482 SDValue Data = N->getValue();
1483 EVT MemoryVT = N->getMemoryVT();
1484 unsigned Alignment = N->getOriginalAlignment();
1487 EVT LoMemVT, HiMemVT;
1488 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1490 SDValue DataLo, DataHi;
1491 GetSplitVector(Data, DataLo, DataHi);
1492 SDValue MaskLo, MaskHi;
1493 GetSplitVector(Mask, MaskLo, MaskHi);
1495 // if Alignment is equal to the vector size,
1496 // take the half of it for the second part
1497 unsigned SecondHalfAlignment =
1498 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1499 Alignment/2 : Alignment;
1502 MachineMemOperand *MMO = DAG.getMachineFunction().
1503 getMachineMemOperand(N->getPointerInfo(),
1504 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1505 Alignment, N->getAAInfo(), N->getRanges());
1507 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1508 N->isTruncatingStore());
1510 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1511 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1512 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1514 MMO = DAG.getMachineFunction().
1515 getMachineMemOperand(N->getPointerInfo(),
1516 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1517 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1519 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1520 N->isTruncatingStore());
1523 // Build a factor node to remember that this store is independent of the
1525 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1529 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1530 assert(N->isUnindexed() && "Indexed store of vector?");
1531 assert(OpNo == 1 && "Can only split the stored value");
1534 bool isTruncating = N->isTruncatingStore();
1535 SDValue Ch = N->getChain();
1536 SDValue Ptr = N->getBasePtr();
1537 EVT MemoryVT = N->getMemoryVT();
1538 unsigned Alignment = N->getOriginalAlignment();
1539 bool isVol = N->isVolatile();
1540 bool isNT = N->isNonTemporal();
1541 AAMDNodes AAInfo = N->getAAInfo();
1543 GetSplitVector(N->getOperand(1), Lo, Hi);
1545 EVT LoMemVT, HiMemVT;
1546 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1548 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1551 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1552 LoMemVT, isVol, isNT, Alignment, AAInfo);
1554 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1555 isVol, isNT, Alignment, AAInfo);
1557 // Increment the pointer to the other half.
1558 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1559 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1562 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1563 N->getPointerInfo().getWithOffset(IncrementSize),
1564 HiMemVT, isVol, isNT, Alignment, AAInfo);
1566 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1567 N->getPointerInfo().getWithOffset(IncrementSize),
1568 isVol, isNT, Alignment, AAInfo);
1570 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1573 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1576 // The input operands all must have the same type, and we know the result
1577 // type is valid. Convert this to a buildvector which extracts all the
1579 // TODO: If the input elements are power-two vectors, we could convert this to
1580 // a new CONCAT_VECTORS node with elements that are half-wide.
1581 SmallVector<SDValue, 32> Elts;
1582 EVT EltVT = N->getValueType(0).getVectorElementType();
1583 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1584 SDValue Op = N->getOperand(op);
1585 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1587 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1588 Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
1593 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1596 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1597 // The result type is legal, but the input type is illegal. If splitting
1598 // ends up with the result type of each half still being legal, just
1599 // do that. If, however, that would result in an illegal result type,
1600 // we can try to get more clever with power-two vectors. Specifically,
1601 // split the input type, but also widen the result element size, then
1602 // concatenate the halves and truncate again. For example, consider a target
1603 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1604 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1605 // %inlo = v4i32 extract_subvector %in, 0
1606 // %inhi = v4i32 extract_subvector %in, 4
1607 // %lo16 = v4i16 trunc v4i32 %inlo
1608 // %hi16 = v4i16 trunc v4i32 %inhi
1609 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1610 // %res = v8i8 trunc v8i16 %in16
1612 // Without this transform, the original truncate would end up being
1613 // scalarized, which is pretty much always a last resort.
1614 SDValue InVec = N->getOperand(0);
1615 EVT InVT = InVec->getValueType(0);
1616 EVT OutVT = N->getValueType(0);
1617 unsigned NumElements = OutVT.getVectorNumElements();
1618 bool IsFloat = OutVT.isFloatingPoint();
1620 // Widening should have already made sure this is a power-two vector
1621 // if we're trying to split it at all. assert() that's true, just in case.
1622 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1624 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1625 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1627 // If the input elements are only 1/2 the width of the result elements,
1628 // just use the normal splitting. Our trick only work if there's room
1629 // to split more than once.
1630 if (InElementSize <= OutElementSize * 2)
1631 return SplitVecOp_UnaryOp(N);
1634 // Extract the halves of the input via extract_subvector.
1635 SDValue InLoVec, InHiVec;
1636 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1637 // Truncate them to 1/2 the element size.
1638 EVT HalfElementVT = IsFloat ?
1639 EVT::getFloatingPointVT(InElementSize/2) :
1640 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1641 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1643 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1644 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1645 // Concatenate them to get the full intermediate truncation result.
1646 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1647 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1649 // Now finish up by truncating all the way down to the original result
1650 // type. This should normally be something that ends up being legal directly,
1651 // but in theory if a target has very wide vectors and an annoyingly
1652 // restricted set of legal types, this split can chain to build things up.
1654 DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1655 DAG.getTargetConstant(0, TLI.getPointerTy())) :
1656 DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1659 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1660 assert(N->getValueType(0).isVector() &&
1661 N->getOperand(0).getValueType().isVector() &&
1662 "Operand types must be vectors");
1663 // The result has a legal vector type, but the input needs splitting.
1664 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1666 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1667 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1668 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1669 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1670 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1672 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1673 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1674 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1675 return PromoteTargetBoolean(Con, N->getValueType(0));
1679 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1680 // The result has a legal vector type, but the input needs splitting.
1681 EVT ResVT = N->getValueType(0);
1684 GetSplitVector(N->getOperand(0), Lo, Hi);
1685 EVT InVT = Lo.getValueType();
1687 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1688 InVT.getVectorNumElements());
1690 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1691 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1693 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1698 //===----------------------------------------------------------------------===//
1699 // Result Vector Widening
1700 //===----------------------------------------------------------------------===//
1702 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1703 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1707 // See if the target wants to custom widen this node.
1708 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1711 SDValue Res = SDValue();
1712 switch (N->getOpcode()) {
1715 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1719 llvm_unreachable("Do not know how to widen the result of this operator!");
1721 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1722 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1723 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1724 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1725 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1726 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1727 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1728 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1729 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1730 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1731 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1733 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1734 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1735 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1736 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1737 case ISD::VECTOR_SHUFFLE:
1738 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1741 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1754 Res = WidenVecRes_Binary(N);
1758 case ISD::FCOPYSIGN:
1768 Res = WidenVecRes_BinaryCanTrap(N);
1772 Res = WidenVecRes_POWI(N);
1778 Res = WidenVecRes_Shift(N);
1781 case ISD::ANY_EXTEND:
1782 case ISD::FP_EXTEND:
1784 case ISD::FP_TO_SINT:
1785 case ISD::FP_TO_UINT:
1786 case ISD::SIGN_EXTEND:
1787 case ISD::SINT_TO_FP:
1789 case ISD::UINT_TO_FP:
1790 case ISD::ZERO_EXTEND:
1791 Res = WidenVecRes_Convert(N);
1807 case ISD::FNEARBYINT:
1814 Res = WidenVecRes_Unary(N);
1817 Res = WidenVecRes_Ternary(N);
1821 // If Res is null, the sub-method took care of registering the result.
1823 SetWidenedVector(SDValue(N, ResNo), Res);
1826 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1827 // Ternary op widening.
1829 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1830 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1831 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1832 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1833 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1836 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1837 // Binary op widening.
1839 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1840 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1841 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1842 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1845 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
1846 // Binary op widening for operations that can trap.
1847 unsigned Opcode = N->getOpcode();
1849 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1850 EVT WidenEltVT = WidenVT.getVectorElementType();
1852 unsigned NumElts = VT.getVectorNumElements();
1853 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1854 NumElts = NumElts / 2;
1855 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1858 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1859 // Operation doesn't trap so just widen as normal.
1860 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1861 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1862 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1865 // No legal vector version so unroll the vector operation and then widen.
1867 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1869 // Since the operation can trap, apply operation on the original vector.
1871 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1872 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1873 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1875 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1876 unsigned ConcatEnd = 0; // Current ConcatOps index.
1877 int Idx = 0; // Current Idx into input vectors.
1879 // NumElts := greatest legal vector size (at most WidenVT)
1880 // while (orig. vector has unhandled elements) {
1881 // take munches of size NumElts from the beginning and add to ConcatOps
1882 // NumElts := next smaller supported vector size or 1
1884 while (CurNumElts != 0) {
1885 while (CurNumElts >= NumElts) {
1886 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1887 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1888 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1889 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1890 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1892 CurNumElts -= NumElts;
1895 NumElts = NumElts / 2;
1896 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1897 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1900 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1901 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1902 InOp1, DAG.getConstant(Idx,
1903 TLI.getVectorIdxTy()));
1904 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1905 InOp2, DAG.getConstant(Idx,
1906 TLI.getVectorIdxTy()));
1907 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1914 // Check to see if we have a single operation with the widen type.
1915 if (ConcatEnd == 1) {
1916 VT = ConcatOps[0].getValueType();
1918 return ConcatOps[0];
1921 // while (Some element of ConcatOps is not of type MaxVT) {
1922 // From the end of ConcatOps, collect elements of the same type and put
1923 // them into an op of the next larger supported type
1925 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1926 Idx = ConcatEnd - 1;
1927 VT = ConcatOps[Idx--].getValueType();
1928 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1931 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1935 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1936 } while (!TLI.isTypeLegal(NextVT));
1938 if (!VT.isVector()) {
1939 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1940 SDValue VecOp = DAG.getUNDEF(NextVT);
1941 unsigned NumToInsert = ConcatEnd - Idx - 1;
1942 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1943 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1944 ConcatOps[OpIdx], DAG.getConstant(i,
1945 TLI.getVectorIdxTy()));
1947 ConcatOps[Idx+1] = VecOp;
1948 ConcatEnd = Idx + 2;
1950 // Vector type, create a CONCAT_VECTORS of type NextVT
1951 SDValue undefVec = DAG.getUNDEF(VT);
1952 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1953 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1954 unsigned RealVals = ConcatEnd - Idx - 1;
1955 unsigned SubConcatEnd = 0;
1956 unsigned SubConcatIdx = Idx + 1;
1957 while (SubConcatEnd < RealVals)
1958 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1959 while (SubConcatEnd < OpsToConcat)
1960 SubConcatOps[SubConcatEnd++] = undefVec;
1961 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1962 NextVT, SubConcatOps);
1963 ConcatEnd = SubConcatIdx + 1;
1967 // Check to see if we have a single operation with the widen type.
1968 if (ConcatEnd == 1) {
1969 VT = ConcatOps[0].getValueType();
1971 return ConcatOps[0];
1974 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1975 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1976 if (NumOps != ConcatEnd ) {
1977 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1978 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1979 ConcatOps[j] = UndefVal;
1981 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
1982 makeArrayRef(ConcatOps.data(), NumOps));
1985 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1986 SDValue InOp = N->getOperand(0);
1989 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1990 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1992 EVT InVT = InOp.getValueType();
1993 EVT InEltVT = InVT.getVectorElementType();
1994 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1996 unsigned Opcode = N->getOpcode();
1997 unsigned InVTNumElts = InVT.getVectorNumElements();
1999 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2000 InOp = GetWidenedVector(N->getOperand(0));
2001 InVT = InOp.getValueType();
2002 InVTNumElts = InVT.getVectorNumElements();
2003 if (InVTNumElts == WidenNumElts) {
2004 if (N->getNumOperands() == 1)
2005 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2006 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
2010 if (TLI.isTypeLegal(InWidenVT)) {
2011 // Because the result and the input are different vector types, widening
2012 // the result could create a legal type but widening the input might make
2013 // it an illegal type that might lead to repeatedly splitting the input
2014 // and then widening it. To avoid this, we widen the input only if
2015 // it results in a legal type.
2016 if (WidenNumElts % InVTNumElts == 0) {
2017 // Widen the input and call convert on the widened input vector.
2018 unsigned NumConcat = WidenNumElts/InVTNumElts;
2019 SmallVector<SDValue, 16> Ops(NumConcat);
2021 SDValue UndefVal = DAG.getUNDEF(InVT);
2022 for (unsigned i = 1; i != NumConcat; ++i)
2024 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2025 if (N->getNumOperands() == 1)
2026 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2027 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2030 if (InVTNumElts % WidenNumElts == 0) {
2031 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
2032 InOp, DAG.getConstant(0,
2033 TLI.getVectorIdxTy()));
2034 // Extract the input and convert the shorten input vector.
2035 if (N->getNumOperands() == 1)
2036 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2037 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2041 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2042 SmallVector<SDValue, 16> Ops(WidenNumElts);
2043 EVT EltVT = WidenVT.getVectorElementType();
2044 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2046 for (i=0; i < MinElts; ++i) {
2047 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2048 DAG.getConstant(i, TLI.getVectorIdxTy()));
2049 if (N->getNumOperands() == 1)
2050 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2052 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2055 SDValue UndefVal = DAG.getUNDEF(EltVT);
2056 for (; i < WidenNumElts; ++i)
2059 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2062 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2063 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2064 SDValue InOp = GetWidenedVector(N->getOperand(0));
2065 SDValue ShOp = N->getOperand(1);
2066 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2069 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2070 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2071 SDValue InOp = GetWidenedVector(N->getOperand(0));
2072 SDValue ShOp = N->getOperand(1);
2074 EVT ShVT = ShOp.getValueType();
2075 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2076 ShOp = GetWidenedVector(ShOp);
2077 ShVT = ShOp.getValueType();
2079 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2080 ShVT.getVectorElementType(),
2081 WidenVT.getVectorNumElements());
2082 if (ShVT != ShWidenVT)
2083 ShOp = ModifyToType(ShOp, ShWidenVT);
2085 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2088 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2089 // Unary op widening.
2090 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2091 SDValue InOp = GetWidenedVector(N->getOperand(0));
2092 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2095 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2096 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2097 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2098 cast<VTSDNode>(N->getOperand(1))->getVT()
2099 .getVectorElementType(),
2100 WidenVT.getVectorNumElements());
2101 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2102 return DAG.getNode(N->getOpcode(), SDLoc(N),
2103 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2106 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2107 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2108 return GetWidenedVector(WidenVec);
2111 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2112 SDValue InOp = N->getOperand(0);
2113 EVT InVT = InOp.getValueType();
2114 EVT VT = N->getValueType(0);
2115 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2118 switch (getTypeAction(InVT)) {
2119 case TargetLowering::TypeLegal:
2121 case TargetLowering::TypePromoteInteger:
2122 // If the incoming type is a vector that is being promoted, then
2123 // we know that the elements are arranged differently and that we
2124 // must perform the conversion using a stack slot.
2125 if (InVT.isVector())
2128 // If the InOp is promoted to the same size, convert it. Otherwise,
2129 // fall out of the switch and widen the promoted input.
2130 InOp = GetPromotedInteger(InOp);
2131 InVT = InOp.getValueType();
2132 if (WidenVT.bitsEq(InVT))
2133 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2135 case TargetLowering::TypeSoftenFloat:
2136 case TargetLowering::TypeExpandInteger:
2137 case TargetLowering::TypeExpandFloat:
2138 case TargetLowering::TypeScalarizeVector:
2139 case TargetLowering::TypeSplitVector:
2141 case TargetLowering::TypeWidenVector:
2142 // If the InOp is widened to the same size, convert it. Otherwise, fall
2143 // out of the switch and widen the widened input.
2144 InOp = GetWidenedVector(InOp);
2145 InVT = InOp.getValueType();
2146 if (WidenVT.bitsEq(InVT))
2147 // The input widens to the same size. Convert to the widen value.
2148 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2152 unsigned WidenSize = WidenVT.getSizeInBits();
2153 unsigned InSize = InVT.getSizeInBits();
2154 // x86mmx is not an acceptable vector element type, so don't try.
2155 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2156 // Determine new input vector type. The new input vector type will use
2157 // the same element type (if its a vector) or use the input type as a
2158 // vector. It is the same size as the type to widen to.
2160 unsigned NewNumElts = WidenSize / InSize;
2161 if (InVT.isVector()) {
2162 EVT InEltVT = InVT.getVectorElementType();
2163 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2164 WidenSize / InEltVT.getSizeInBits());
2166 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2169 if (TLI.isTypeLegal(NewInVT)) {
2170 // Because the result and the input are different vector types, widening
2171 // the result could create a legal type but widening the input might make
2172 // it an illegal type that might lead to repeatedly splitting the input
2173 // and then widening it. To avoid this, we widen the input only if
2174 // it results in a legal type.
2175 SmallVector<SDValue, 16> Ops(NewNumElts);
2176 SDValue UndefVal = DAG.getUNDEF(InVT);
2178 for (unsigned i = 1; i < NewNumElts; ++i)
2182 if (InVT.isVector())
2183 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2185 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2186 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2190 return CreateStackStoreLoad(InOp, WidenVT);
2193 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2195 // Build a vector with undefined for the new nodes.
2196 EVT VT = N->getValueType(0);
2198 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2199 // type. The UNDEFs need to have the same type as the existing operands.
2200 EVT EltVT = N->getOperand(0).getValueType();
2201 unsigned NumElts = VT.getVectorNumElements();
2203 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2204 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2206 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2207 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2208 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2210 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2213 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2214 EVT InVT = N->getOperand(0).getValueType();
2215 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2217 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2218 unsigned NumInElts = InVT.getVectorNumElements();
2219 unsigned NumOperands = N->getNumOperands();
2221 bool InputWidened = false; // Indicates we need to widen the input.
2222 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2223 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2224 // Add undef vectors to widen to correct length.
2225 unsigned NumConcat = WidenVT.getVectorNumElements() /
2226 InVT.getVectorNumElements();
2227 SDValue UndefVal = DAG.getUNDEF(InVT);
2228 SmallVector<SDValue, 16> Ops(NumConcat);
2229 for (unsigned i=0; i < NumOperands; ++i)
2230 Ops[i] = N->getOperand(i);
2231 for (unsigned i = NumOperands; i != NumConcat; ++i)
2233 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2236 InputWidened = true;
2237 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2238 // The inputs and the result are widen to the same value.
2240 for (i=1; i < NumOperands; ++i)
2241 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2244 if (i == NumOperands)
2245 // Everything but the first operand is an UNDEF so just return the
2246 // widened first operand.
2247 return GetWidenedVector(N->getOperand(0));
2249 if (NumOperands == 2) {
2250 // Replace concat of two operands with a shuffle.
2251 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2252 for (unsigned i = 0; i < NumInElts; ++i) {
2254 MaskOps[i + NumInElts] = i + WidenNumElts;
2256 return DAG.getVectorShuffle(WidenVT, dl,
2257 GetWidenedVector(N->getOperand(0)),
2258 GetWidenedVector(N->getOperand(1)),
2264 // Fall back to use extracts and build vector.
2265 EVT EltVT = WidenVT.getVectorElementType();
2266 SmallVector<SDValue, 16> Ops(WidenNumElts);
2268 for (unsigned i=0; i < NumOperands; ++i) {
2269 SDValue InOp = N->getOperand(i);
2271 InOp = GetWidenedVector(InOp);
2272 for (unsigned j=0; j < NumInElts; ++j)
2273 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2274 DAG.getConstant(j, TLI.getVectorIdxTy()));
2276 SDValue UndefVal = DAG.getUNDEF(EltVT);
2277 for (; Idx < WidenNumElts; ++Idx)
2278 Ops[Idx] = UndefVal;
2279 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2282 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2284 SDValue InOp = N->getOperand(0);
2285 SDValue RndOp = N->getOperand(3);
2286 SDValue SatOp = N->getOperand(4);
2288 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2289 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2291 EVT InVT = InOp.getValueType();
2292 EVT InEltVT = InVT.getVectorElementType();
2293 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2295 SDValue DTyOp = DAG.getValueType(WidenVT);
2296 SDValue STyOp = DAG.getValueType(InWidenVT);
2297 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2299 unsigned InVTNumElts = InVT.getVectorNumElements();
2300 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2301 InOp = GetWidenedVector(InOp);
2302 InVT = InOp.getValueType();
2303 InVTNumElts = InVT.getVectorNumElements();
2304 if (InVTNumElts == WidenNumElts)
2305 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2309 if (TLI.isTypeLegal(InWidenVT)) {
2310 // Because the result and the input are different vector types, widening
2311 // the result could create a legal type but widening the input might make
2312 // it an illegal type that might lead to repeatedly splitting the input
2313 // and then widening it. To avoid this, we widen the input only if
2314 // it results in a legal type.
2315 if (WidenNumElts % InVTNumElts == 0) {
2316 // Widen the input and call convert on the widened input vector.
2317 unsigned NumConcat = WidenNumElts/InVTNumElts;
2318 SmallVector<SDValue, 16> Ops(NumConcat);
2320 SDValue UndefVal = DAG.getUNDEF(InVT);
2321 for (unsigned i = 1; i != NumConcat; ++i)
2324 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2325 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2329 if (InVTNumElts % WidenNumElts == 0) {
2330 // Extract the input and convert the shorten input vector.
2331 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2332 DAG.getConstant(0, TLI.getVectorIdxTy()));
2333 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2338 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2339 SmallVector<SDValue, 16> Ops(WidenNumElts);
2340 EVT EltVT = WidenVT.getVectorElementType();
2341 DTyOp = DAG.getValueType(EltVT);
2342 STyOp = DAG.getValueType(InEltVT);
2344 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2346 for (i=0; i < MinElts; ++i) {
2347 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2348 DAG.getConstant(i, TLI.getVectorIdxTy()));
2349 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2353 SDValue UndefVal = DAG.getUNDEF(EltVT);
2354 for (; i < WidenNumElts; ++i)
2357 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2360 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2361 EVT VT = N->getValueType(0);
2362 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2363 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2364 SDValue InOp = N->getOperand(0);
2365 SDValue Idx = N->getOperand(1);
2368 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2369 InOp = GetWidenedVector(InOp);
2371 EVT InVT = InOp.getValueType();
2373 // Check if we can just return the input vector after widening.
2374 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2375 if (IdxVal == 0 && InVT == WidenVT)
2378 // Check if we can extract from the vector.
2379 unsigned InNumElts = InVT.getVectorNumElements();
2380 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2381 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2383 // We could try widening the input to the right length but for now, extract
2384 // the original elements, fill the rest with undefs and build a vector.
2385 SmallVector<SDValue, 16> Ops(WidenNumElts);
2386 EVT EltVT = VT.getVectorElementType();
2387 unsigned NumElts = VT.getVectorNumElements();
2389 for (i=0; i < NumElts; ++i)
2390 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2391 DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
2393 SDValue UndefVal = DAG.getUNDEF(EltVT);
2394 for (; i < WidenNumElts; ++i)
2396 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2399 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2400 SDValue InOp = GetWidenedVector(N->getOperand(0));
2401 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2402 InOp.getValueType(), InOp,
2403 N->getOperand(1), N->getOperand(2));
2406 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2407 LoadSDNode *LD = cast<LoadSDNode>(N);
2408 ISD::LoadExtType ExtType = LD->getExtensionType();
2411 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2412 if (ExtType != ISD::NON_EXTLOAD)
2413 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2415 Result = GenWidenVectorLoads(LdChain, LD);
2417 // If we generate a single load, we can use that for the chain. Otherwise,
2418 // build a factor node to remember the multiple loads are independent and
2421 if (LdChain.size() == 1)
2422 NewChain = LdChain[0];
2424 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2426 // Modified the chain - switch anything that used the old chain to use
2428 ReplaceValueWith(SDValue(N, 1), NewChain);
2433 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2435 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2436 SDValue Mask = N->getMask();
2437 EVT MaskVT = Mask.getValueType();
2438 SDValue Src0 = GetWidenedVector(N->getSrc0());
2439 ISD::LoadExtType ExtType = N->getExtensionType();
2442 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2443 Mask = GetWidenedVector(Mask);
2445 EVT BoolVT = getSetCCResultType(WidenVT);
2447 // We can't use ModifyToType() because we should fill the mask with
2449 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2450 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2452 unsigned NumConcat = WidenNumElts / MaskNumElts;
2453 SmallVector<SDValue, 16> Ops(NumConcat);
2454 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
2456 for (unsigned i = 1; i != NumConcat; ++i)
2459 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2462 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2463 Mask, Src0, N->getMemoryVT(),
2464 N->getMemOperand(), ExtType);
2465 // Legalized the chain result - switch anything that used the old chain to
2467 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2471 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2472 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2473 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2474 WidenVT, N->getOperand(0));
2477 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2478 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2479 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2481 SDValue Cond1 = N->getOperand(0);
2482 EVT CondVT = Cond1.getValueType();
2483 if (CondVT.isVector()) {
2484 EVT CondEltVT = CondVT.getVectorElementType();
2485 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2486 CondEltVT, WidenNumElts);
2487 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2488 Cond1 = GetWidenedVector(Cond1);
2490 // If we have to split the condition there is no point in widening the
2491 // select. This would result in an cycle of widening the select ->
2492 // widening the condition operand -> splitting the condition operand ->
2493 // splitting the select -> widening the select. Instead split this select
2494 // further and widen the resulting type.
2495 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2496 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2497 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2501 if (Cond1.getValueType() != CondWidenVT)
2502 Cond1 = ModifyToType(Cond1, CondWidenVT);
2505 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2506 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2507 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2508 return DAG.getNode(N->getOpcode(), SDLoc(N),
2509 WidenVT, Cond1, InOp1, InOp2);
2512 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2513 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2514 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2515 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2516 InOp1.getValueType(), N->getOperand(0),
2517 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2520 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2521 assert(N->getValueType(0).isVector() ==
2522 N->getOperand(0).getValueType().isVector() &&
2523 "Scalar/Vector type mismatch");
2524 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2526 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2527 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2528 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2529 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2530 InOp1, InOp2, N->getOperand(2));
2533 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2534 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2535 return DAG.getUNDEF(WidenVT);
2538 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2539 EVT VT = N->getValueType(0);
2542 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2543 unsigned NumElts = VT.getVectorNumElements();
2544 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2546 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2547 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2549 // Adjust mask based on new input vector length.
2550 SmallVector<int, 16> NewMask;
2551 for (unsigned i = 0; i != NumElts; ++i) {
2552 int Idx = N->getMaskElt(i);
2553 if (Idx < (int)NumElts)
2554 NewMask.push_back(Idx);
2556 NewMask.push_back(Idx - NumElts + WidenNumElts);
2558 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2559 NewMask.push_back(-1);
2560 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2563 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2564 assert(N->getValueType(0).isVector() &&
2565 N->getOperand(0).getValueType().isVector() &&
2566 "Operands must be vectors");
2567 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2568 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2570 SDValue InOp1 = N->getOperand(0);
2571 EVT InVT = InOp1.getValueType();
2572 assert(InVT.isVector() && "can not widen non-vector type");
2573 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2574 InVT.getVectorElementType(), WidenNumElts);
2576 // The input and output types often differ here, and it could be that while
2577 // we'd prefer to widen the result type, the input operands have been split.
2578 // In this case, we also need to split the result of this node as well.
2579 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2580 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2581 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2585 InOp1 = GetWidenedVector(InOp1);
2586 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2588 // Assume that the input and output will be widen appropriately. If not,
2589 // we will have to unroll it at some point.
2590 assert(InOp1.getValueType() == WidenInVT &&
2591 InOp2.getValueType() == WidenInVT &&
2592 "Input not widened to expected type!");
2594 return DAG.getNode(ISD::SETCC, SDLoc(N),
2595 WidenVT, InOp1, InOp2, N->getOperand(2));
2599 //===----------------------------------------------------------------------===//
2600 // Widen Vector Operand
2601 //===----------------------------------------------------------------------===//
2602 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2603 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2606 SDValue Res = SDValue();
2608 // See if the target wants to custom widen this node.
2609 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2612 switch (N->getOpcode()) {
2615 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2619 llvm_unreachable("Do not know how to widen this operator's operand!");
2621 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2622 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2623 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2624 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2625 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2626 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2627 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2629 case ISD::ANY_EXTEND:
2630 case ISD::SIGN_EXTEND:
2631 case ISD::ZERO_EXTEND:
2632 Res = WidenVecOp_EXTEND(N);
2635 case ISD::FP_EXTEND:
2636 case ISD::FP_TO_SINT:
2637 case ISD::FP_TO_UINT:
2638 case ISD::SINT_TO_FP:
2639 case ISD::UINT_TO_FP:
2641 Res = WidenVecOp_Convert(N);
2645 // If Res is null, the sub-method took care of registering the result.
2646 if (!Res.getNode()) return false;
2648 // If the result is N, the sub-method updated N in place. Tell the legalizer
2650 if (Res.getNode() == N)
2654 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2655 "Invalid operand expansion");
2657 ReplaceValueWith(SDValue(N, 0), Res);
2661 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2663 EVT VT = N->getValueType(0);
2665 SDValue InOp = N->getOperand(0);
2666 // If some legalization strategy other than widening is used on the operand,
2667 // we can't safely assume that just extending the low lanes is the correct
2669 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2670 return WidenVecOp_Convert(N);
2671 InOp = GetWidenedVector(InOp);
2672 assert(VT.getVectorNumElements() <
2673 InOp.getValueType().getVectorNumElements() &&
2674 "Input wasn't widened!");
2676 // We may need to further widen the operand until it has the same total
2677 // vector size as the result.
2678 EVT InVT = InOp.getValueType();
2679 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2680 EVT InEltVT = InVT.getVectorElementType();
2681 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2682 EVT FixedVT = (MVT::SimpleValueType)i;
2683 EVT FixedEltVT = FixedVT.getVectorElementType();
2684 if (TLI.isTypeLegal(FixedVT) &&
2685 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2686 FixedEltVT == InEltVT) {
2687 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2688 "Not enough elements in the fixed type for the operand!");
2689 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2690 "We can't have the same type as we started with!");
2691 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2692 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2693 DAG.getUNDEF(FixedVT), InOp,
2694 DAG.getConstant(0, TLI.getVectorIdxTy()));
2696 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2697 DAG.getConstant(0, TLI.getVectorIdxTy()));
2701 InVT = InOp.getValueType();
2702 if (InVT.getSizeInBits() != VT.getSizeInBits())
2703 // We couldn't find a legal vector type that was a widening of the input
2704 // and could be extended in-register to the result type, so we have to
2706 return WidenVecOp_Convert(N);
2709 // Use special DAG nodes to represent the operation of extending the
2711 switch (N->getOpcode()) {
2713 llvm_unreachable("Extend legalization on on extend operation!");
2714 case ISD::ANY_EXTEND:
2715 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2716 case ISD::SIGN_EXTEND:
2717 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2718 case ISD::ZERO_EXTEND:
2719 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2723 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2724 // Since the result is legal and the input is illegal, it is unlikely
2725 // that we can fix the input to a legal type so unroll the convert
2726 // into some scalar code and create a nasty build vector.
2727 EVT VT = N->getValueType(0);
2728 EVT EltVT = VT.getVectorElementType();
2730 unsigned NumElts = VT.getVectorNumElements();
2731 SDValue InOp = N->getOperand(0);
2732 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2733 InOp = GetWidenedVector(InOp);
2734 EVT InVT = InOp.getValueType();
2735 EVT InEltVT = InVT.getVectorElementType();
2737 unsigned Opcode = N->getOpcode();
2738 SmallVector<SDValue, 16> Ops(NumElts);
2739 for (unsigned i=0; i < NumElts; ++i)
2740 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2741 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2742 DAG.getConstant(i, TLI.getVectorIdxTy())));
2744 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2747 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2748 EVT VT = N->getValueType(0);
2749 SDValue InOp = GetWidenedVector(N->getOperand(0));
2750 EVT InWidenVT = InOp.getValueType();
2753 // Check if we can convert between two legal vector types and extract.
2754 unsigned InWidenSize = InWidenVT.getSizeInBits();
2755 unsigned Size = VT.getSizeInBits();
2756 // x86mmx is not an acceptable vector element type, so don't try.
2757 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2758 unsigned NewNumElts = InWidenSize / Size;
2759 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2760 if (TLI.isTypeLegal(NewVT)) {
2761 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2762 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2763 DAG.getConstant(0, TLI.getVectorIdxTy()));
2767 return CreateStackStoreLoad(InOp, VT);
2770 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2771 // If the input vector is not legal, it is likely that we will not find a
2772 // legal vector of the same size. Replace the concatenate vector with a
2773 // nasty build vector.
2774 EVT VT = N->getValueType(0);
2775 EVT EltVT = VT.getVectorElementType();
2777 unsigned NumElts = VT.getVectorNumElements();
2778 SmallVector<SDValue, 16> Ops(NumElts);
2780 EVT InVT = N->getOperand(0).getValueType();
2781 unsigned NumInElts = InVT.getVectorNumElements();
2784 unsigned NumOperands = N->getNumOperands();
2785 for (unsigned i=0; i < NumOperands; ++i) {
2786 SDValue InOp = N->getOperand(i);
2787 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2788 InOp = GetWidenedVector(InOp);
2789 for (unsigned j=0; j < NumInElts; ++j)
2790 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2791 DAG.getConstant(j, TLI.getVectorIdxTy()));
2793 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2796 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2797 SDValue InOp = GetWidenedVector(N->getOperand(0));
2798 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2799 N->getValueType(0), InOp, N->getOperand(1));
2802 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2803 SDValue InOp = GetWidenedVector(N->getOperand(0));
2804 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2805 N->getValueType(0), InOp, N->getOperand(1));
2808 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2809 // We have to widen the value but we want only to store the original
2811 StoreSDNode *ST = cast<StoreSDNode>(N);
2813 SmallVector<SDValue, 16> StChain;
2814 if (ST->isTruncatingStore())
2815 GenWidenVectorTruncStores(StChain, ST);
2817 GenWidenVectorStores(StChain, ST);
2819 if (StChain.size() == 1)
2822 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
2825 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
2826 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
2827 SDValue Mask = MST->getMask();
2828 EVT MaskVT = Mask.getValueType();
2829 SDValue StVal = MST->getValue();
2831 SDValue WideVal = GetWidenedVector(StVal);
2834 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2835 Mask = GetWidenedVector(Mask);
2837 // The mask should be widened as well
2838 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
2839 // We can't use ModifyToType() because we should fill the mask with
2841 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2842 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2844 unsigned NumConcat = WidenNumElts / MaskNumElts;
2845 SmallVector<SDValue, 16> Ops(NumConcat);
2846 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
2848 for (unsigned i = 1; i != NumConcat; ++i)
2851 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2853 assert(Mask.getValueType().getVectorNumElements() ==
2854 WideVal.getValueType().getVectorNumElements() &&
2855 "Mask and data vectors should have the same number of elements");
2856 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
2857 Mask, MST->getMemoryVT(), MST->getMemOperand(),
2861 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2862 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2863 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2866 // WARNING: In this code we widen the compare instruction with garbage.
2867 // This garbage may contain denormal floats which may be slow. Is this a real
2868 // concern ? Should we zero the unused lanes if this is a float compare ?
2870 // Get a new SETCC node to compare the newly widened operands.
2871 // Only some of the compared elements are legal.
2872 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
2873 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
2874 SVT, InOp0, InOp1, N->getOperand(2));
2876 // Extract the needed results from the result vector.
2877 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2878 SVT.getVectorElementType(),
2879 N->getValueType(0).getVectorNumElements());
2880 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2881 ResVT, WideSETCC, DAG.getConstant(0,
2882 TLI.getVectorIdxTy()));
2884 return PromoteTargetBoolean(CC, N->getValueType(0));
2888 //===----------------------------------------------------------------------===//
2889 // Vector Widening Utilities
2890 //===----------------------------------------------------------------------===//
2892 // Utility function to find the type to chop up a widen vector for load/store
2893 // TLI: Target lowering used to determine legal types.
2894 // Width: Width left need to load/store.
2895 // WidenVT: The widen vector type to load to/store from
2896 // Align: If 0, don't allow use of a wider type
2897 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2899 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2900 unsigned Width, EVT WidenVT,
2901 unsigned Align = 0, unsigned WidenEx = 0) {
2902 EVT WidenEltVT = WidenVT.getVectorElementType();
2903 unsigned WidenWidth = WidenVT.getSizeInBits();
2904 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2905 unsigned AlignInBits = Align*8;
2907 // If we have one element to load/store, return it.
2908 EVT RetVT = WidenEltVT;
2909 if (Width == WidenEltWidth)
2912 // See if there is larger legal integer than the element type to load/store
2914 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2915 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2916 EVT MemVT((MVT::SimpleValueType) VT);
2917 unsigned MemVTWidth = MemVT.getSizeInBits();
2918 if (MemVT.getSizeInBits() <= WidenEltWidth)
2920 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2921 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2922 (MemVTWidth <= Width ||
2923 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2929 // See if there is a larger vector type to load/store that has the same vector
2930 // element type and is evenly divisible with the WidenVT.
2931 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2932 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2933 EVT MemVT = (MVT::SimpleValueType) VT;
2934 unsigned MemVTWidth = MemVT.getSizeInBits();
2935 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2936 (WidenWidth % MemVTWidth) == 0 &&
2937 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2938 (MemVTWidth <= Width ||
2939 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2940 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2948 // Builds a vector type from scalar loads
2949 // VecTy: Resulting Vector type
2950 // LDOps: Load operators to build a vector type
2951 // [Start,End) the list of loads to use.
2952 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2953 SmallVectorImpl<SDValue> &LdOps,
2954 unsigned Start, unsigned End) {
2955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2956 SDLoc dl(LdOps[Start]);
2957 EVT LdTy = LdOps[Start].getValueType();
2958 unsigned Width = VecTy.getSizeInBits();
2959 unsigned NumElts = Width / LdTy.getSizeInBits();
2960 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2963 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2965 for (unsigned i = Start + 1; i != End; ++i) {
2966 EVT NewLdTy = LdOps[i].getValueType();
2967 if (NewLdTy != LdTy) {
2968 NumElts = Width / NewLdTy.getSizeInBits();
2969 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2970 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2971 // Readjust position and vector position based on new load type
2972 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2975 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2976 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
2978 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2981 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
2983 // The strategy assumes that we can efficiently load powers of two widths.
2984 // The routines chops the vector into the largest vector loads with the same
2985 // element type or scalar loads and then recombines it to the widen vector
2987 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2988 unsigned WidenWidth = WidenVT.getSizeInBits();
2989 EVT LdVT = LD->getMemoryVT();
2991 assert(LdVT.isVector() && WidenVT.isVector());
2992 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2995 SDValue Chain = LD->getChain();
2996 SDValue BasePtr = LD->getBasePtr();
2997 unsigned Align = LD->getAlignment();
2998 bool isVolatile = LD->isVolatile();
2999 bool isNonTemporal = LD->isNonTemporal();
3000 bool isInvariant = LD->isInvariant();
3001 AAMDNodes AAInfo = LD->getAAInfo();
3003 int LdWidth = LdVT.getSizeInBits();
3004 int WidthDiff = WidenWidth - LdWidth; // Difference
3005 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3007 // Find the vector type that can load from.
3008 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3009 int NewVTWidth = NewVT.getSizeInBits();
3010 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3011 isVolatile, isNonTemporal, isInvariant, Align,
3013 LdChain.push_back(LdOp.getValue(1));
3015 // Check if we can load the element with one instruction
3016 if (LdWidth <= NewVTWidth) {
3017 if (!NewVT.isVector()) {
3018 unsigned NumElts = WidenWidth / NewVTWidth;
3019 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3020 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3021 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3023 if (NewVT == WidenVT)
3026 assert(WidenWidth % NewVTWidth == 0);
3027 unsigned NumConcat = WidenWidth / NewVTWidth;
3028 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3029 SDValue UndefVal = DAG.getUNDEF(NewVT);
3030 ConcatOps[0] = LdOp;
3031 for (unsigned i = 1; i != NumConcat; ++i)
3032 ConcatOps[i] = UndefVal;
3033 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3036 // Load vector by using multiple loads from largest vector to scalar
3037 SmallVector<SDValue, 16> LdOps;
3038 LdOps.push_back(LdOp);
3040 LdWidth -= NewVTWidth;
3041 unsigned Offset = 0;
3043 while (LdWidth > 0) {
3044 unsigned Increment = NewVTWidth / 8;
3045 Offset += Increment;
3046 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3047 DAG.getConstant(Increment, BasePtr.getValueType()));
3050 if (LdWidth < NewVTWidth) {
3051 // Our current type we are using is too large, find a better size
3052 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3053 NewVTWidth = NewVT.getSizeInBits();
3054 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3055 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3056 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3058 LdChain.push_back(L.getValue(1));
3059 if (L->getValueType(0).isVector()) {
3060 SmallVector<SDValue, 16> Loads;
3062 unsigned size = L->getValueSizeInBits(0);
3063 while (size < LdOp->getValueSizeInBits(0)) {
3064 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3065 size += L->getValueSizeInBits(0);
3067 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3070 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3071 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3072 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3074 LdChain.push_back(L.getValue(1));
3080 LdWidth -= NewVTWidth;
3083 // Build the vector from the loads operations
3084 unsigned End = LdOps.size();
3085 if (!LdOps[0].getValueType().isVector())
3086 // All the loads are scalar loads.
3087 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3089 // If the load contains vectors, build the vector using concat vector.
3090 // All of the vectors used to loads are power of 2 and the scalars load
3091 // can be combined to make a power of 2 vector.
3092 SmallVector<SDValue, 16> ConcatOps(End);
3095 EVT LdTy = LdOps[i].getValueType();
3096 // First combine the scalar loads to a vector
3097 if (!LdTy.isVector()) {
3098 for (--i; i >= 0; --i) {
3099 LdTy = LdOps[i].getValueType();
3100 if (LdTy.isVector())
3103 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3105 ConcatOps[--Idx] = LdOps[i];
3106 for (--i; i >= 0; --i) {
3107 EVT NewLdTy = LdOps[i].getValueType();
3108 if (NewLdTy != LdTy) {
3109 // Create a larger vector
3110 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3111 makeArrayRef(&ConcatOps[Idx], End - Idx));
3115 ConcatOps[--Idx] = LdOps[i];
3118 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3119 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3120 makeArrayRef(&ConcatOps[Idx], End - Idx));
3122 // We need to fill the rest with undefs to build the vector
3123 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3124 SmallVector<SDValue, 16> WidenOps(NumOps);
3125 SDValue UndefVal = DAG.getUNDEF(LdTy);
3128 for (; i != End-Idx; ++i)
3129 WidenOps[i] = ConcatOps[Idx+i];
3130 for (; i != NumOps; ++i)
3131 WidenOps[i] = UndefVal;
3133 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3137 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3139 ISD::LoadExtType ExtType) {
3140 // For extension loads, it may not be more efficient to chop up the vector
3141 // and then extended it. Instead, we unroll the load and build a new vector.
3142 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3143 EVT LdVT = LD->getMemoryVT();
3145 assert(LdVT.isVector() && WidenVT.isVector());
3148 SDValue Chain = LD->getChain();
3149 SDValue BasePtr = LD->getBasePtr();
3150 unsigned Align = LD->getAlignment();
3151 bool isVolatile = LD->isVolatile();
3152 bool isNonTemporal = LD->isNonTemporal();
3153 bool isInvariant = LD->isInvariant();
3154 AAMDNodes AAInfo = LD->getAAInfo();
3156 EVT EltVT = WidenVT.getVectorElementType();
3157 EVT LdEltVT = LdVT.getVectorElementType();
3158 unsigned NumElts = LdVT.getVectorNumElements();
3160 // Load each element and widen
3161 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3162 SmallVector<SDValue, 16> Ops(WidenNumElts);
3163 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3164 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3165 LD->getPointerInfo(),
3166 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3168 LdChain.push_back(Ops[0].getValue(1));
3169 unsigned i = 0, Offset = Increment;
3170 for (i=1; i < NumElts; ++i, Offset += Increment) {
3171 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3173 DAG.getConstant(Offset,
3174 BasePtr.getValueType()));
3175 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3176 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3177 isVolatile, isNonTemporal, isInvariant, Align,
3179 LdChain.push_back(Ops[i].getValue(1));
3182 // Fill the rest with undefs
3183 SDValue UndefVal = DAG.getUNDEF(EltVT);
3184 for (; i != WidenNumElts; ++i)
3187 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3191 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3193 // The strategy assumes that we can efficiently store powers of two widths.
3194 // The routines chops the vector into the largest vector stores with the same
3195 // element type or scalar stores.
3196 SDValue Chain = ST->getChain();
3197 SDValue BasePtr = ST->getBasePtr();
3198 unsigned Align = ST->getAlignment();
3199 bool isVolatile = ST->isVolatile();
3200 bool isNonTemporal = ST->isNonTemporal();
3201 AAMDNodes AAInfo = ST->getAAInfo();
3202 SDValue ValOp = GetWidenedVector(ST->getValue());
3205 EVT StVT = ST->getMemoryVT();
3206 unsigned StWidth = StVT.getSizeInBits();
3207 EVT ValVT = ValOp.getValueType();
3208 unsigned ValWidth = ValVT.getSizeInBits();
3209 EVT ValEltVT = ValVT.getVectorElementType();
3210 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3211 assert(StVT.getVectorElementType() == ValEltVT);
3213 int Idx = 0; // current index to store
3214 unsigned Offset = 0; // offset from base to store
3215 while (StWidth != 0) {
3216 // Find the largest vector type we can store with
3217 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3218 unsigned NewVTWidth = NewVT.getSizeInBits();
3219 unsigned Increment = NewVTWidth / 8;
3220 if (NewVT.isVector()) {
3221 unsigned NumVTElts = NewVT.getVectorNumElements();
3223 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3224 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3225 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3226 ST->getPointerInfo().getWithOffset(Offset),
3227 isVolatile, isNonTemporal,
3228 MinAlign(Align, Offset), AAInfo));
3229 StWidth -= NewVTWidth;
3230 Offset += Increment;
3232 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3233 DAG.getConstant(Increment, BasePtr.getValueType()));
3234 } while (StWidth != 0 && StWidth >= NewVTWidth);
3236 // Cast the vector to the scalar type we can store
3237 unsigned NumElts = ValWidth / NewVTWidth;
3238 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3239 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3240 // Readjust index position based on new vector type
3241 Idx = Idx * ValEltWidth / NewVTWidth;
3243 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3244 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
3245 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3246 ST->getPointerInfo().getWithOffset(Offset),
3247 isVolatile, isNonTemporal,
3248 MinAlign(Align, Offset), AAInfo));
3249 StWidth -= NewVTWidth;
3250 Offset += Increment;
3251 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3252 DAG.getConstant(Increment, BasePtr.getValueType()));
3253 } while (StWidth != 0 && StWidth >= NewVTWidth);
3254 // Restore index back to be relative to the original widen element type
3255 Idx = Idx * NewVTWidth / ValEltWidth;
3261 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3263 // For extension loads, it may not be more efficient to truncate the vector
3264 // and then store it. Instead, we extract each element and then store it.
3265 SDValue Chain = ST->getChain();
3266 SDValue BasePtr = ST->getBasePtr();
3267 unsigned Align = ST->getAlignment();
3268 bool isVolatile = ST->isVolatile();
3269 bool isNonTemporal = ST->isNonTemporal();
3270 AAMDNodes AAInfo = ST->getAAInfo();
3271 SDValue ValOp = GetWidenedVector(ST->getValue());
3274 EVT StVT = ST->getMemoryVT();
3275 EVT ValVT = ValOp.getValueType();
3277 // It must be true that we the widen vector type is bigger than where
3278 // we need to store.
3279 assert(StVT.isVector() && ValOp.getValueType().isVector());
3280 assert(StVT.bitsLT(ValOp.getValueType()));
3282 // For truncating stores, we can not play the tricks of chopping legal
3283 // vector types and bit cast it to the right type. Instead, we unroll
3285 EVT StEltVT = StVT.getVectorElementType();
3286 EVT ValEltVT = ValVT.getVectorElementType();
3287 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3288 unsigned NumElts = StVT.getVectorNumElements();
3289 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3290 DAG.getConstant(0, TLI.getVectorIdxTy()));
3291 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3292 ST->getPointerInfo(), StEltVT,
3293 isVolatile, isNonTemporal, Align,
3295 unsigned Offset = Increment;
3296 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3297 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3298 BasePtr, DAG.getConstant(Offset,
3299 BasePtr.getValueType()));
3300 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3301 DAG.getConstant(0, TLI.getVectorIdxTy()));
3302 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3303 ST->getPointerInfo().getWithOffset(Offset),
3304 StEltVT, isVolatile, isNonTemporal,
3305 MinAlign(Align, Offset), AAInfo));
3309 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3310 /// input vector must have the same element type as NVT.
3311 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3312 // Note that InOp might have been widened so it might already have
3313 // the right width or it might need be narrowed.
3314 EVT InVT = InOp.getValueType();
3315 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3316 "input and widen element type must match");
3319 // Check if InOp already has the right width.
3323 unsigned InNumElts = InVT.getVectorNumElements();
3324 unsigned WidenNumElts = NVT.getVectorNumElements();
3325 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3326 unsigned NumConcat = WidenNumElts / InNumElts;
3327 SmallVector<SDValue, 16> Ops(NumConcat);
3328 SDValue UndefVal = DAG.getUNDEF(InVT);
3330 for (unsigned i = 1; i != NumConcat; ++i)
3333 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3336 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3337 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3338 DAG.getConstant(0, TLI.getVectorIdxTy()));
3340 // Fall back to extract and build.
3341 SmallVector<SDValue, 16> Ops(WidenNumElts);
3342 EVT EltVT = NVT.getVectorElementType();
3343 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3345 for (Idx = 0; Idx < MinNumElts; ++Idx)
3346 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3347 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3349 SDValue UndefVal = DAG.getUNDEF(EltVT);
3350 for ( ; Idx < WidenNumElts; ++Idx)
3351 Ops[Idx] = UndefVal;
3352 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);