1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDValue R = SDValue();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
46 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
47 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
48 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
49 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
50 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
51 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
52 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
65 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
82 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
85 // If R is null, the sub-method took care of registering the result.
87 SetScalarizedVector(SDValue(N, ResNo), R);
90 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
91 SDValue LHS = GetScalarizedVector(N->getOperand(0));
92 SDValue RHS = GetScalarizedVector(N->getOperand(1));
93 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
96 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
97 MVT NewVT = N->getValueType(0).getVectorElementType();
98 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
101 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
102 SDValue Op = GetScalarizedVector(N->getOperand(0));
103 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
106 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
107 // The value to insert may have a wider type than the vector element type,
108 // so be sure to truncate it to the element type if necessary.
109 SDValue Op = N->getOperand(1);
110 MVT EltVT = N->getValueType(0).getVectorElementType();
111 if (Op.getValueType() != EltVT)
112 // FIXME: Can this happen for floating point types?
113 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
117 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
118 assert(ISD::isNormalLoad(N) && "Extending load of one-element vector?");
119 SDValue Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
120 N->getChain(), N->getBasePtr(),
121 N->getSrcValue(), N->getSrcValueOffset(),
122 N->isVolatile(), N->getAlignment());
124 // Legalized the chain result - switch anything that used the old chain to
126 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
130 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
131 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
132 MVT DestVT = TLI.getTypeToTransformTo(N->getValueType(0));
133 SDValue Op = GetScalarizedVector(N->getOperand(0));
134 return DAG.getNode(N->getOpcode(), DestVT, Op);
137 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
138 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
141 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
142 SDValue LHS = GetScalarizedVector(N->getOperand(1));
143 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
144 GetScalarizedVector(N->getOperand(2)));
147 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
148 // Figure out if the scalar is the LHS or RHS and return it.
149 SDValue EltNum = N->getOperand(2).getOperand(0);
150 unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0;
151 return GetScalarizedVector(N->getOperand(Op));
154 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
155 MVT NewVT = N->getValueType(0).getVectorElementType();
156 SDValue LHS = GetScalarizedVector(N->getOperand(0));
157 SDValue RHS = GetScalarizedVector(N->getOperand(1));
158 LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
161 DAG.getNode(ISD::SELECT, NewVT, LHS,
162 DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
164 DAG.getConstant(0ULL, NewVT));
168 //===----------------------------------------------------------------------===//
169 // Operand Vector Scalarization <1 x ty> -> ty.
170 //===----------------------------------------------------------------------===//
172 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
173 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
175 SDValue Res = SDValue();
178 switch (N->getOpcode()) {
181 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
182 N->dump(&DAG); cerr << "\n";
184 assert(0 && "Do not know how to scalarize this operator's operand!");
187 case ISD::BIT_CONVERT:
188 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
190 case ISD::EXTRACT_VECTOR_ELT:
191 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
194 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
198 // If the result is null, the sub-method took care of registering results etc.
199 if (!Res.Val) return false;
201 // If the result is N, the sub-method updated N in place. Check to see if any
202 // operands are new, and if so, mark them.
204 // Mark N as new and remark N and its operands. This allows us to correctly
205 // revisit N if it needs another step of promotion and allows us to visit
206 // any new operands to N.
211 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
212 "Invalid operand expansion");
214 ReplaceValueWith(SDValue(N, 0), Res);
218 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
219 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
220 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
221 SDValue Elt = GetScalarizedVector(N->getOperand(0));
222 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
225 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
226 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
228 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
229 return GetScalarizedVector(N->getOperand(0));
232 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
233 /// scalarized, it must be <1 x ty>. Just store the element.
234 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
235 assert(ISD::isNormalStore(N) && "Truncating store of one-element vector?");
236 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
237 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
238 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
239 N->isVolatile(), N->getAlignment());
243 //===----------------------------------------------------------------------===//
244 // Result Vector Splitting
245 //===----------------------------------------------------------------------===//
247 /// SplitVectorResult - This method is called when the specified result of the
248 /// specified node is found to need vector splitting. At this point, the node
249 /// may also have invalid operands or may have other results that need
250 /// legalization, we just know that (at least) one result needs vector
252 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
253 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
256 switch (N->getOpcode()) {
259 cerr << "SplitVectorResult #" << ResNo << ": ";
260 N->dump(&DAG); cerr << "\n";
262 assert(0 && "Do not know how to split the result of this operator!");
265 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
266 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
267 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
268 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
270 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
271 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
272 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
273 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
274 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
275 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
276 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
277 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
287 case ISD::FP_TO_SINT:
288 case ISD::FP_TO_UINT:
289 case ISD::SINT_TO_FP:
290 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
307 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
310 // If Lo/Hi is null, the sub-method took care of registering results etc.
312 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
315 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
317 SDValue LHSLo, LHSHi;
318 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
319 SDValue RHSLo, RHSHi;
320 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
322 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
323 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
326 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
328 // We know the result is a vector. The input may be either a vector or a
331 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
333 SDValue InOp = N->getOperand(0);
334 MVT InVT = InOp.getValueType();
336 // Handle some special cases efficiently.
337 switch (getTypeAction(InVT)) {
339 assert(false && "Unknown type action!");
343 case ScalarizeVector:
347 // A scalar to vector conversion, where the scalar needs expansion.
348 // If the vector is being split in two then we can just convert the
351 GetExpandedOp(InOp, Lo, Hi);
352 if (TLI.isBigEndian())
354 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
355 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
360 // If the input is a vector that needs to be split, convert each split
361 // piece of the input now.
362 GetSplitVector(InOp, Lo, Hi);
363 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
364 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
368 // In the general case, convert the input to an integer and split it by hand.
369 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
370 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
371 if (TLI.isBigEndian())
372 std::swap(LoIntVT, HiIntVT);
374 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
376 if (TLI.isBigEndian())
378 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
379 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
382 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
385 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
386 unsigned LoNumElts = LoVT.getVectorNumElements();
387 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
388 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
390 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
391 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
394 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
396 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
397 unsigned NumSubvectors = N->getNumOperands() / 2;
398 if (NumSubvectors == 1) {
399 Lo = N->getOperand(0);
400 Hi = N->getOperand(1);
405 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
407 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
408 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
410 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
411 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
414 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
416 GetSplitVector(N->getOperand(0), Lo, Hi);
417 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
418 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
421 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
423 SDValue Vec = N->getOperand(0);
424 SDValue Elt = N->getOperand(1);
425 SDValue Idx = N->getOperand(2);
426 GetSplitVector(Vec, Lo, Hi);
428 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
429 unsigned IdxVal = CIdx->getValue();
430 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
431 if (IdxVal < LoNumElts)
432 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
434 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
435 DAG.getIntPtrConstant(IdxVal - LoNumElts));
439 // Spill the vector to the stack.
440 MVT VecVT = Vec.getValueType();
441 MVT EltVT = VecVT.getVectorElementType();
442 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
443 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
445 // Store the new element. This may be larger than the vector element type,
446 // so use a truncating store.
447 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
448 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
450 // Reload the vector from the stack.
451 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
454 SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
457 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
459 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
461 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
463 SDValue Ch = LD->getChain();
464 SDValue Ptr = LD->getBasePtr();
465 const Value *SV = LD->getSrcValue();
466 int SVOffset = LD->getSrcValueOffset();
467 unsigned Alignment = LD->getAlignment();
468 bool isVolatile = LD->isVolatile();
470 Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
472 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
473 unsigned IncrementSize = LoVT.getSizeInBits()/8;
474 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
475 DAG.getIntPtrConstant(IncrementSize));
476 SVOffset += IncrementSize;
477 Alignment = MinAlign(Alignment, IncrementSize);
478 Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
480 // Build a factor node to remember that this load is independent of the
482 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
485 assert(LD->getExtensionType() == ISD::EXTLOAD &&
486 "Unsupported vector extending load!");
487 Hi = DAG.getNode(ISD::UNDEF, HiVT);
491 // Legalized the chain result - switch anything that used the old chain to
493 ReplaceValueWith(SDValue(LD, 1), Ch);
496 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
498 // Get the dest types - they may not match the input types, e.g. int_to_fp.
500 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
502 GetSplitVector(N->getOperand(0), Lo, Hi);
503 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
504 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
507 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
509 // Build the low part.
510 SDValue Mask = N->getOperand(2);
511 SmallVector<SDValue, 16> Ops;
513 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
514 MVT EltVT = LoVT.getVectorElementType();
515 unsigned LoNumElts = LoVT.getVectorNumElements();
516 unsigned NumElements = Mask.getNumOperands();
518 // Insert all of the elements from the input that are needed. We use
519 // buildvector of extractelement here because the input vectors will have
520 // to be legalized, so this makes the code simpler.
521 for (unsigned i = 0; i != LoNumElts; ++i) {
522 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
523 SDValue InVec = N->getOperand(0);
524 if (Idx >= NumElements) {
525 InVec = N->getOperand(1);
528 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
529 DAG.getIntPtrConstant(Idx)));
531 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
534 for (unsigned i = LoNumElts; i != NumElements; ++i) {
535 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
536 SDValue InVec = N->getOperand(0);
537 if (Idx >= NumElements) {
538 InVec = N->getOperand(1);
541 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
542 DAG.getIntPtrConstant(Idx)));
544 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
547 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
550 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
552 SDValue LL, LH, RL, RH;
553 GetSplitVector(N->getOperand(0), LL, LH);
554 GetSplitVector(N->getOperand(1), RL, RH);
556 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
557 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
561 //===----------------------------------------------------------------------===//
562 // Operand Vector Splitting
563 //===----------------------------------------------------------------------===//
565 /// SplitVectorOperand - This method is called when the specified operand of the
566 /// specified node is found to need vector splitting. At this point, all of the
567 /// result types of the node are known to be legal, but other operands of the
568 /// node may need legalization as well as the specified one.
569 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
570 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
571 SDValue Res = SDValue();
574 switch (N->getOpcode()) {
577 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
578 N->dump(&DAG); cerr << "\n";
580 assert(0 && "Do not know how to split this operator's operand!");
583 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
584 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
585 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
586 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
588 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
592 // If the result is null, the sub-method took care of registering results etc.
593 if (!Res.Val) return false;
595 // If the result is N, the sub-method updated N in place. Check to see if any
596 // operands are new, and if so, mark them.
598 // Mark N as new and remark N and its operands. This allows us to correctly
599 // revisit N if it needs another step of promotion and allows us to visit
600 // any new operands to N.
605 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
606 "Invalid operand expansion");
608 ReplaceValueWith(SDValue(N, 0), Res);
612 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
613 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
614 // end up being split all the way down to individual components. Convert the
615 // split pieces into integers and reassemble.
617 GetSplitVector(N->getOperand(0), Lo, Hi);
618 Lo = BitConvertToInteger(Lo);
619 Hi = BitConvertToInteger(Hi);
621 if (TLI.isBigEndian())
624 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
625 JoinIntegers(Lo, Hi));
628 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
629 // We know that the extracted result type is legal. For now, assume the index
631 MVT SubVT = N->getValueType(0);
632 SDValue Idx = N->getOperand(1);
634 GetSplitVector(N->getOperand(0), Lo, Hi);
636 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
637 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
639 if (IdxVal < LoElts) {
640 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
641 "Extracted subvector crosses vector split!");
642 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
644 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
645 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
649 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
650 SDValue Vec = N->getOperand(0);
651 SDValue Idx = N->getOperand(1);
652 MVT VecVT = Vec.getValueType();
654 if (isa<ConstantSDNode>(Idx)) {
655 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
656 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
659 GetSplitVector(Vec, Lo, Hi);
661 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
664 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
666 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
667 DAG.getConstant(IdxVal - LoElts,
668 Idx.getValueType()));
671 // Store the vector to the stack.
672 MVT EltVT = VecVT.getVectorElementType();
673 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
674 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
676 // Load back the required element.
677 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
678 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
681 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
682 assert(ISD::isNormalStore(N) && "Truncating store of vector?");
683 assert(OpNo == 1 && "Can only split the stored value");
685 SDValue Ch = N->getChain();
686 SDValue Ptr = N->getBasePtr();
687 int SVOffset = N->getSrcValueOffset();
688 unsigned Alignment = N->getAlignment();
689 bool isVol = N->isVolatile();
691 GetSplitVector(N->getOperand(1), Lo, Hi);
693 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
695 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
697 // Increment the pointer to the other half.
698 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
699 DAG.getIntPtrConstant(IncrementSize));
701 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
702 isVol, MinAlign(Alignment, IncrementSize));
703 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
706 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
707 assert(OpNo == 2 && "Shuffle source type differs from result type?");
708 SDValue Mask = N->getOperand(2);
709 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
710 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
711 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
713 // Look for a legal vector type to place the mask values in.
714 // Note that there may not be *any* legal vector-of-integer
715 // type for which the element type is legal!
716 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
717 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
718 // Integer values types are consecutively numbered. Exploit this.
719 EltVT = MVT::SimpleValueType(EltVT + 1)) {
721 // Is the element type big enough to hold the values?
722 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
726 // Is the vector type legal?
727 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
728 if (!isTypeLegal(VecVT))
732 // If the element type is not legal, find a larger legal type to use for
733 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
734 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
735 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
736 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
737 // Integer values types are consecutively numbered. Exploit this.
738 OpVT = MVT::SimpleValueType(OpVT + 1)) {
739 if (!isTypeLegal(OpVT))
742 // Success! Rebuild the vector using the legal types.
743 SmallVector<SDValue, 16> Ops(MaskLength);
744 for (unsigned i = 0; i < MaskLength; ++i) {
746 cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
747 Ops[i] = DAG.getConstant(Idx, OpVT);
749 return DAG.UpdateNodeOperands(SDValue(N,0),
750 N->getOperand(0), N->getOperand(1),
751 DAG.getNode(ISD::BUILD_VECTOR,
752 VecVT, &Ops[0], Ops.size()));
755 // Continuing is pointless - failure is certain.
758 assert(false && "Failed to find an appropriate mask type!");
759 return SDValue(N, 0);