1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
73 case ISD::CTLZ_ZERO_UNDEF:
76 case ISD::CTTZ_ZERO_UNDEF:
96 case ISD::SIGN_EXTEND:
100 case ISD::ZERO_EXTEND:
101 R = ScalarizeVecRes_UnaryOp(N);
129 R = ScalarizeVecRes_BinOp(N);
132 R = ScalarizeVecRes_TernaryOp(N);
136 // If R is null, the sub-method took care of registering the result.
138 SetScalarizedVector(SDValue(N, ResNo), R);
141 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
142 SDValue LHS = GetScalarizedVector(N->getOperand(0));
143 SDValue RHS = GetScalarizedVector(N->getOperand(1));
144 return DAG.getNode(N->getOpcode(), SDLoc(N),
145 LHS.getValueType(), LHS, RHS, N->getFlags());
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
149 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
150 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
151 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
152 return DAG.getNode(N->getOpcode(), SDLoc(N),
153 Op0.getValueType(), Op0, Op1, Op2);
156 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
158 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
159 return GetScalarizedVector(Op);
162 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
163 EVT NewVT = N->getValueType(0).getVectorElementType();
164 return DAG.getNode(ISD::BITCAST, SDLoc(N),
165 NewVT, N->getOperand(0));
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
169 EVT EltVT = N->getValueType(0).getVectorElementType();
170 SDValue InOp = N->getOperand(0);
171 // The BUILD_VECTOR operands may be of wider element types and
172 // we may need to truncate them back to the requested return type.
173 if (EltVT.isInteger())
174 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
178 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
179 EVT NewVT = N->getValueType(0).getVectorElementType();
180 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
181 return DAG.getConvertRndSat(NewVT, SDLoc(N),
182 Op0, DAG.getValueType(NewVT),
183 DAG.getValueType(Op0.getValueType()),
186 cast<CvtRndSatSDNode>(N)->getCvtCode());
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
190 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
191 N->getValueType(0).getVectorElementType(),
192 N->getOperand(0), N->getOperand(1));
195 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
196 EVT NewVT = N->getValueType(0).getVectorElementType();
197 SDValue Op = GetScalarizedVector(N->getOperand(0));
198 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
199 NewVT, Op, N->getOperand(1));
202 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
203 SDValue Op = GetScalarizedVector(N->getOperand(0));
204 return DAG.getNode(ISD::FPOWI, SDLoc(N),
205 Op.getValueType(), Op, N->getOperand(1));
208 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
209 // The value to insert may have a wider type than the vector element type,
210 // so be sure to truncate it to the element type if necessary.
211 SDValue Op = N->getOperand(1);
212 EVT EltVT = N->getValueType(0).getVectorElementType();
213 if (Op.getValueType() != EltVT)
214 // FIXME: Can this happen for floating point types?
215 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
219 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
220 assert(N->isUnindexed() && "Indexed vector load?");
222 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
223 N->getExtensionType(),
224 N->getValueType(0).getVectorElementType(),
226 N->getChain(), N->getBasePtr(),
227 DAG.getUNDEF(N->getBasePtr().getValueType()),
229 N->getMemoryVT().getVectorElementType(),
230 N->isVolatile(), N->isNonTemporal(),
231 N->isInvariant(), N->getOriginalAlignment(),
234 // Legalized the chain result - switch anything that used the old chain to
236 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
240 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
241 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
242 EVT DestVT = N->getValueType(0).getVectorElementType();
243 SDValue Op = N->getOperand(0);
244 EVT OpVT = Op.getValueType();
246 // The result needs scalarizing, but it's not a given that the source does.
247 // This is a workaround for targets where it's impossible to scalarize the
248 // result of a conversion, because the source type is legal.
249 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
250 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
251 // legal and was not scalarized.
252 // See the similar logic in ScalarizeVecRes_VSETCC
253 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
254 Op = GetScalarizedVector(Op);
256 EVT VT = OpVT.getVectorElementType();
258 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
259 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
261 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
264 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
265 EVT EltVT = N->getValueType(0).getVectorElementType();
266 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
267 SDValue LHS = GetScalarizedVector(N->getOperand(0));
268 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
269 LHS, DAG.getValueType(ExtVT));
272 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
273 // If the operand is wider than the vector element type then it is implicitly
274 // truncated. Make that explicit here.
275 EVT EltVT = N->getValueType(0).getVectorElementType();
276 SDValue InOp = N->getOperand(0);
277 if (InOp.getValueType() != EltVT)
278 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
283 SDValue Cond = GetScalarizedVector(N->getOperand(0));
284 SDValue LHS = GetScalarizedVector(N->getOperand(1));
285 TargetLowering::BooleanContent ScalarBool =
286 TLI.getBooleanContents(false, false);
287 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
289 // If integer and float booleans have different contents then we can't
290 // reliably optimize in all cases. There is a full explanation for this in
291 // DAGCombiner::visitSELECT() where the same issue affects folding
292 // (select C, 0, 1) to (xor C, 1).
293 if (TLI.getBooleanContents(false, false) !=
294 TLI.getBooleanContents(false, true)) {
295 // At least try the common case where the boolean is generated by a
297 if (Cond->getOpcode() == ISD::SETCC) {
298 EVT OpVT = Cond->getOperand(0)->getValueType(0);
299 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
300 VecBool = TLI.getBooleanContents(OpVT);
302 ScalarBool = TargetLowering::UndefinedBooleanContent;
305 if (ScalarBool != VecBool) {
306 EVT CondVT = Cond.getValueType();
307 switch (ScalarBool) {
308 case TargetLowering::UndefinedBooleanContent:
310 case TargetLowering::ZeroOrOneBooleanContent:
311 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
312 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
313 // Vector read from all ones, scalar expects a single 1 so mask.
314 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
315 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
317 case TargetLowering::ZeroOrNegativeOneBooleanContent:
318 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
319 VecBool == TargetLowering::ZeroOrOneBooleanContent);
320 // Vector reads from a one, scalar from all ones so sign extend.
321 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
322 Cond, DAG.getValueType(MVT::i1));
327 return DAG.getSelect(SDLoc(N),
328 LHS.getValueType(), Cond, LHS,
329 GetScalarizedVector(N->getOperand(2)));
332 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
333 SDValue LHS = GetScalarizedVector(N->getOperand(1));
334 return DAG.getSelect(SDLoc(N),
335 LHS.getValueType(), N->getOperand(0), LHS,
336 GetScalarizedVector(N->getOperand(2)));
339 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
340 SDValue LHS = GetScalarizedVector(N->getOperand(2));
341 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
342 N->getOperand(0), N->getOperand(1),
343 LHS, GetScalarizedVector(N->getOperand(3)),
347 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
348 assert(N->getValueType(0).isVector() ==
349 N->getOperand(0).getValueType().isVector() &&
350 "Scalar/Vector type mismatch");
352 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
354 SDValue LHS = GetScalarizedVector(N->getOperand(0));
355 SDValue RHS = GetScalarizedVector(N->getOperand(1));
358 // Turn it into a scalar SETCC.
359 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
363 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
366 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
367 // Figure out if the scalar is the LHS or RHS and return it.
368 SDValue Arg = N->getOperand(2).getOperand(0);
369 if (Arg.getOpcode() == ISD::UNDEF)
370 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
371 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
372 return GetScalarizedVector(N->getOperand(Op));
375 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
376 assert(N->getValueType(0).isVector() &&
377 N->getOperand(0).getValueType().isVector() &&
378 "Operand types must be vectors");
379 SDValue LHS = N->getOperand(0);
380 SDValue RHS = N->getOperand(1);
381 EVT OpVT = LHS.getValueType();
382 EVT NVT = N->getValueType(0).getVectorElementType();
385 // The result needs scalarizing, but it's not a given that the source does.
386 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
387 LHS = GetScalarizedVector(LHS);
388 RHS = GetScalarizedVector(RHS);
390 EVT VT = OpVT.getVectorElementType();
392 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
393 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
395 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
396 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
399 // Turn it into a scalar SETCC.
400 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
402 // Vectors may have a different boolean contents to scalars. Promote the
403 // value appropriately.
404 ISD::NodeType ExtendCode =
405 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
406 return DAG.getNode(ExtendCode, DL, NVT, Res);
410 //===----------------------------------------------------------------------===//
411 // Operand Vector Scalarization <1 x ty> -> ty.
412 //===----------------------------------------------------------------------===//
414 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
415 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
418 SDValue Res = SDValue();
420 if (!Res.getNode()) {
421 switch (N->getOpcode()) {
424 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
428 llvm_unreachable("Do not know how to scalarize this operator's operand!");
430 Res = ScalarizeVecOp_BITCAST(N);
432 case ISD::ANY_EXTEND:
433 case ISD::ZERO_EXTEND:
434 case ISD::SIGN_EXTEND:
436 case ISD::FP_TO_SINT:
437 case ISD::FP_TO_UINT:
438 case ISD::SINT_TO_FP:
439 case ISD::UINT_TO_FP:
440 Res = ScalarizeVecOp_UnaryOp(N);
442 case ISD::CONCAT_VECTORS:
443 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
445 case ISD::EXTRACT_VECTOR_ELT:
446 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
449 Res = ScalarizeVecOp_VSELECT(N);
452 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
455 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
460 // If the result is null, the sub-method took care of registering results etc.
461 if (!Res.getNode()) return false;
463 // If the result is N, the sub-method updated N in place. Tell the legalizer
465 if (Res.getNode() == N)
468 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
469 "Invalid operand expansion");
471 ReplaceValueWith(SDValue(N, 0), Res);
475 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
476 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
477 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
478 SDValue Elt = GetScalarizedVector(N->getOperand(0));
479 return DAG.getNode(ISD::BITCAST, SDLoc(N),
480 N->getValueType(0), Elt);
483 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
484 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
485 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
486 assert(N->getValueType(0).getVectorNumElements() == 1 &&
487 "Unexpected vector type!");
488 SDValue Elt = GetScalarizedVector(N->getOperand(0));
489 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
490 N->getValueType(0).getScalarType(), Elt);
491 // Revectorize the result so the types line up with what the uses of this
492 // expression expect.
493 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
496 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
497 /// use a BUILD_VECTOR instead.
498 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
499 SmallVector<SDValue, 8> Ops(N->getNumOperands());
500 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
501 Ops[i] = GetScalarizedVector(N->getOperand(i));
502 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
505 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
506 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
508 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
509 SDValue Res = GetScalarizedVector(N->getOperand(0));
510 if (Res.getValueType() != N->getValueType(0))
511 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
517 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
518 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
519 /// (still with vector output type since that was acceptable if we got here).
520 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
521 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
522 EVT VT = N->getValueType(0);
524 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
528 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
529 /// scalarized, it must be <1 x ty>. Just store the element.
530 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
531 assert(N->isUnindexed() && "Indexed store of one-element vector?");
532 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
535 if (N->isTruncatingStore())
536 return DAG.getTruncStore(N->getChain(), dl,
537 GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->getMemoryVT().getVectorElementType(),
540 N->isVolatile(), N->isNonTemporal(),
541 N->getAlignment(), N->getAAInfo());
543 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
544 N->getBasePtr(), N->getPointerInfo(),
545 N->isVolatile(), N->isNonTemporal(),
546 N->getOriginalAlignment(), N->getAAInfo());
549 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
550 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
551 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
552 SDValue Elt = GetScalarizedVector(N->getOperand(0));
553 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
554 N->getValueType(0).getVectorElementType(), Elt,
556 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
559 //===----------------------------------------------------------------------===//
560 // Result Vector Splitting
561 //===----------------------------------------------------------------------===//
563 /// SplitVectorResult - This method is called when the specified result of the
564 /// specified node is found to need vector splitting. At this point, the node
565 /// may also have invalid operands or may have other results that need
566 /// legalization, we just know that (at least) one result needs vector
568 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
569 DEBUG(dbgs() << "Split node result: ";
574 // See if the target wants to custom expand this node.
575 if (CustomLowerNode(N, N->getValueType(ResNo), true))
578 switch (N->getOpcode()) {
581 dbgs() << "SplitVectorResult #" << ResNo << ": ";
585 report_fatal_error("Do not know how to split the result of this "
588 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
590 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
591 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
592 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
593 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
594 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
595 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
596 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
597 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
598 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
599 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
600 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
601 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
602 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
603 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
605 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
608 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
611 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
614 SplitVecRes_SETCC(N, Lo, Hi);
616 case ISD::VECTOR_SHUFFLE:
617 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
620 case ISD::BITREVERSE:
622 case ISD::CONVERT_RNDSAT:
625 case ISD::CTLZ_ZERO_UNDEF:
626 case ISD::CTTZ_ZERO_UNDEF:
637 case ISD::FNEARBYINT:
641 case ISD::FP_TO_SINT:
642 case ISD::FP_TO_UINT:
648 case ISD::SINT_TO_FP:
650 case ISD::UINT_TO_FP:
651 SplitVecRes_UnaryOp(N, Lo, Hi);
654 case ISD::ANY_EXTEND:
655 case ISD::SIGN_EXTEND:
656 case ISD::ZERO_EXTEND:
657 SplitVecRes_ExtendOp(N, Lo, Hi);
689 SplitVecRes_BinOp(N, Lo, Hi);
692 SplitVecRes_TernaryOp(N, Lo, Hi);
696 // If Lo/Hi is null, the sub-method took care of registering results etc.
698 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
701 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
703 SDValue LHSLo, LHSHi;
704 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
705 SDValue RHSLo, RHSHi;
706 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
709 const SDNodeFlags *Flags = N->getFlags();
710 unsigned Opcode = N->getOpcode();
711 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
712 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
715 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
717 SDValue Op0Lo, Op0Hi;
718 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
719 SDValue Op1Lo, Op1Hi;
720 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
721 SDValue Op2Lo, Op2Hi;
722 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
725 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
726 Op0Lo, Op1Lo, Op2Lo);
727 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
728 Op0Hi, Op1Hi, Op2Hi);
731 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
733 // We know the result is a vector. The input may be either a vector or a
736 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
739 SDValue InOp = N->getOperand(0);
740 EVT InVT = InOp.getValueType();
742 // Handle some special cases efficiently.
743 switch (getTypeAction(InVT)) {
744 case TargetLowering::TypeLegal:
745 case TargetLowering::TypePromoteInteger:
746 case TargetLowering::TypePromoteFloat:
747 case TargetLowering::TypeSoftenFloat:
748 case TargetLowering::TypeScalarizeVector:
749 case TargetLowering::TypeWidenVector:
751 case TargetLowering::TypeExpandInteger:
752 case TargetLowering::TypeExpandFloat:
753 // A scalar to vector conversion, where the scalar needs expansion.
754 // If the vector is being split in two then we can just convert the
757 GetExpandedOp(InOp, Lo, Hi);
758 if (DAG.getDataLayout().isBigEndian())
760 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
761 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
765 case TargetLowering::TypeSplitVector:
766 // If the input is a vector that needs to be split, convert each split
767 // piece of the input now.
768 GetSplitVector(InOp, Lo, Hi);
769 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
770 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
774 // In the general case, convert the input to an integer and split it by hand.
775 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
776 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
777 if (DAG.getDataLayout().isBigEndian())
778 std::swap(LoIntVT, HiIntVT);
780 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
782 if (DAG.getDataLayout().isBigEndian())
784 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
785 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
788 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
792 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
793 unsigned LoNumElts = LoVT.getVectorNumElements();
794 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
795 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
797 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
798 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
801 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
803 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
805 unsigned NumSubvectors = N->getNumOperands() / 2;
806 if (NumSubvectors == 1) {
807 Lo = N->getOperand(0);
808 Hi = N->getOperand(1);
813 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
815 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
816 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
818 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
819 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
822 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
824 SDValue Vec = N->getOperand(0);
825 SDValue Idx = N->getOperand(1);
829 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
831 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
832 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
833 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
834 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
835 TLI.getVectorIdxTy(DAG.getDataLayout())));
838 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
840 SDValue Vec = N->getOperand(0);
841 SDValue SubVec = N->getOperand(1);
842 SDValue Idx = N->getOperand(2);
844 GetSplitVector(Vec, Lo, Hi);
846 // Spill the vector to the stack.
847 EVT VecVT = Vec.getValueType();
848 EVT SubVecVT = VecVT.getVectorElementType();
849 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
850 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
851 MachinePointerInfo(), false, false, 0);
853 // Store the new subvector into the specified index.
854 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
855 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
856 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
857 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
860 // Load the Lo part from the stack slot.
861 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
862 false, false, false, 0);
864 // Increment the pointer to the other part.
865 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
867 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
868 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
870 // Load the Hi part from the stack slot.
871 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
872 false, false, false, MinAlign(Alignment, IncrementSize));
875 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
878 GetSplitVector(N->getOperand(0), Lo, Hi);
879 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
880 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
883 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
885 SDValue LHSLo, LHSHi;
886 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
889 SDValue RHSLo, RHSHi;
890 SDValue RHS = N->getOperand(1);
891 EVT RHSVT = RHS.getValueType();
892 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
893 GetSplitVector(RHS, RHSLo, RHSHi);
895 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
898 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
899 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
902 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
904 SDValue LHSLo, LHSHi;
905 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
909 std::tie(LoVT, HiVT) =
910 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
912 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
913 DAG.getValueType(LoVT));
914 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
915 DAG.getValueType(HiVT));
918 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
920 SDValue Vec = N->getOperand(0);
921 SDValue Elt = N->getOperand(1);
922 SDValue Idx = N->getOperand(2);
924 GetSplitVector(Vec, Lo, Hi);
926 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
927 unsigned IdxVal = CIdx->getZExtValue();
928 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
929 if (IdxVal < LoNumElts)
930 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
931 Lo.getValueType(), Lo, Elt, Idx);
934 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
935 DAG.getConstant(IdxVal - LoNumElts, dl,
936 TLI.getVectorIdxTy(DAG.getDataLayout())));
940 // See if the target wants to custom expand this node.
941 if (CustomLowerNode(N, N->getValueType(0), true))
944 // Spill the vector to the stack.
945 EVT VecVT = Vec.getValueType();
946 EVT EltVT = VecVT.getVectorElementType();
947 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
948 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
949 MachinePointerInfo(), false, false, 0);
951 // Store the new element. This may be larger than the vector element type,
952 // so use a truncating store.
953 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
954 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
955 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
956 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
959 // Load the Lo part from the stack slot.
960 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
961 false, false, false, 0);
963 // Increment the pointer to the other part.
964 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
965 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
966 DAG.getConstant(IncrementSize, dl,
967 StackPtr.getValueType()));
969 // Load the Hi part from the stack slot.
970 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
971 false, false, false, MinAlign(Alignment, IncrementSize));
974 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
978 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
979 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
980 Hi = DAG.getUNDEF(HiVT);
983 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
985 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
988 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
990 ISD::LoadExtType ExtType = LD->getExtensionType();
991 SDValue Ch = LD->getChain();
992 SDValue Ptr = LD->getBasePtr();
993 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
994 EVT MemoryVT = LD->getMemoryVT();
995 unsigned Alignment = LD->getOriginalAlignment();
996 bool isVolatile = LD->isVolatile();
997 bool isNonTemporal = LD->isNonTemporal();
998 bool isInvariant = LD->isInvariant();
999 AAMDNodes AAInfo = LD->getAAInfo();
1001 EVT LoMemVT, HiMemVT;
1002 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1004 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1005 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
1006 isInvariant, Alignment, AAInfo);
1008 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1009 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1010 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1011 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1012 LD->getPointerInfo().getWithOffset(IncrementSize),
1013 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
1016 // Build a factor node to remember that this load is independent of the
1018 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1021 // Legalized the chain result - switch anything that used the old chain to
1023 ReplaceValueWith(SDValue(LD, 1), Ch);
1026 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1027 SDValue &Lo, SDValue &Hi) {
1030 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1032 SDValue Ch = MLD->getChain();
1033 SDValue Ptr = MLD->getBasePtr();
1034 SDValue Mask = MLD->getMask();
1035 unsigned Alignment = MLD->getOriginalAlignment();
1036 ISD::LoadExtType ExtType = MLD->getExtensionType();
1038 // if Alignment is equal to the vector size,
1039 // take the half of it for the second part
1040 unsigned SecondHalfAlignment =
1041 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1042 Alignment/2 : Alignment;
1044 SDValue MaskLo, MaskHi;
1045 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1047 EVT MemoryVT = MLD->getMemoryVT();
1048 EVT LoMemVT, HiMemVT;
1049 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1051 SDValue Src0 = MLD->getSrc0();
1052 SDValue Src0Lo, Src0Hi;
1053 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1055 MachineMemOperand *MMO = DAG.getMachineFunction().
1056 getMachineMemOperand(MLD->getPointerInfo(),
1057 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1058 Alignment, MLD->getAAInfo(), MLD->getRanges());
1060 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1063 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1064 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1065 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1067 MMO = DAG.getMachineFunction().
1068 getMachineMemOperand(MLD->getPointerInfo(),
1069 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1070 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1072 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1076 // Build a factor node to remember that this load is independent of the
1078 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1081 // Legalized the chain result - switch anything that used the old chain to
1083 ReplaceValueWith(SDValue(MLD, 1), Ch);
1087 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1088 SDValue &Lo, SDValue &Hi) {
1091 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1093 SDValue Ch = MGT->getChain();
1094 SDValue Ptr = MGT->getBasePtr();
1095 SDValue Mask = MGT->getMask();
1096 unsigned Alignment = MGT->getOriginalAlignment();
1098 SDValue MaskLo, MaskHi;
1099 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1101 EVT MemoryVT = MGT->getMemoryVT();
1102 EVT LoMemVT, HiMemVT;
1103 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1105 SDValue Src0Lo, Src0Hi;
1106 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1108 SDValue IndexHi, IndexLo;
1109 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
1111 MachineMemOperand *MMO = DAG.getMachineFunction().
1112 getMachineMemOperand(MGT->getPointerInfo(),
1113 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1114 Alignment, MGT->getAAInfo(), MGT->getRanges());
1116 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1117 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1120 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1121 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1124 // Build a factor node to remember that this load is independent of the
1126 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1129 // Legalized the chain result - switch anything that used the old chain to
1131 ReplaceValueWith(SDValue(MGT, 1), Ch);
1135 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1136 assert(N->getValueType(0).isVector() &&
1137 N->getOperand(0).getValueType().isVector() &&
1138 "Operand types must be vectors");
1142 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1145 SDValue LL, LH, RL, RH;
1146 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1147 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1149 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1150 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1153 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1155 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1158 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1160 // If the input also splits, handle it directly for a compile time speedup.
1161 // Otherwise split it by hand.
1162 EVT InVT = N->getOperand(0).getValueType();
1163 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1164 GetSplitVector(N->getOperand(0), Lo, Hi);
1166 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1168 if (N->getOpcode() == ISD::FP_ROUND) {
1169 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1170 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1171 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1172 SDValue DTyOpLo = DAG.getValueType(LoVT);
1173 SDValue DTyOpHi = DAG.getValueType(HiVT);
1174 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1175 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1176 SDValue RndOp = N->getOperand(3);
1177 SDValue SatOp = N->getOperand(4);
1178 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1179 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1181 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1184 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1185 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1189 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1192 EVT SrcVT = N->getOperand(0).getValueType();
1193 EVT DestVT = N->getValueType(0);
1195 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1197 // We can do better than a generic split operation if the extend is doing
1198 // more than just doubling the width of the elements and the following are
1200 // - The number of vector elements is even,
1201 // - the source type is legal,
1202 // - the type of a split source is illegal,
1203 // - the type of an extended (by doubling element size) source is legal, and
1204 // - the type of that extended source when split is legal.
1206 // This won't necessarily completely legalize the operation, but it will
1207 // more effectively move in the right direction and prevent falling down
1208 // to scalarization in many cases due to the input vector being split too
1210 unsigned NumElements = SrcVT.getVectorNumElements();
1211 if ((NumElements & 1) == 0 &&
1212 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1213 LLVMContext &Ctx = *DAG.getContext();
1214 EVT NewSrcVT = EVT::getVectorVT(
1215 Ctx, EVT::getIntegerVT(
1216 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1219 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1220 EVT SplitLoVT, SplitHiVT;
1221 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1222 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1223 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1224 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1225 N->dump(&DAG); dbgs() << "\n");
1226 // Extend the source vector by one step.
1228 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1229 // Get the low and high halves of the new, extended one step, vector.
1230 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1231 // Extend those vector halves the rest of the way.
1232 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1233 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1237 // Fall back to the generic unary operator splitting otherwise.
1238 SplitVecRes_UnaryOp(N, Lo, Hi);
1241 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1242 SDValue &Lo, SDValue &Hi) {
1243 // The low and high parts of the original input give four input vectors.
1246 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1247 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1248 EVT NewVT = Inputs[0].getValueType();
1249 unsigned NewElts = NewVT.getVectorNumElements();
1251 // If Lo or Hi uses elements from at most two of the four input vectors, then
1252 // express it as a vector shuffle of those two inputs. Otherwise extract the
1253 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1254 SmallVector<int, 16> Ops;
1255 for (unsigned High = 0; High < 2; ++High) {
1256 SDValue &Output = High ? Hi : Lo;
1258 // Build a shuffle mask for the output, discovering on the fly which
1259 // input vectors to use as shuffle operands (recorded in InputUsed).
1260 // If building a suitable shuffle vector proves too hard, then bail
1261 // out with useBuildVector set.
1262 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1263 unsigned FirstMaskIdx = High * NewElts;
1264 bool useBuildVector = false;
1265 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1266 // The mask element. This indexes into the input.
1267 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1269 // The input vector this mask element indexes into.
1270 unsigned Input = (unsigned)Idx / NewElts;
1272 if (Input >= array_lengthof(Inputs)) {
1273 // The mask element does not index into any input vector.
1278 // Turn the index into an offset from the start of the input vector.
1279 Idx -= Input * NewElts;
1281 // Find or create a shuffle vector operand to hold this input.
1283 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1284 if (InputUsed[OpNo] == Input) {
1285 // This input vector is already an operand.
1287 } else if (InputUsed[OpNo] == -1U) {
1288 // Create a new operand for this input vector.
1289 InputUsed[OpNo] = Input;
1294 if (OpNo >= array_lengthof(InputUsed)) {
1295 // More than two input vectors used! Give up on trying to create a
1296 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1297 useBuildVector = true;
1301 // Add the mask index for the new shuffle vector.
1302 Ops.push_back(Idx + OpNo * NewElts);
1305 if (useBuildVector) {
1306 EVT EltVT = NewVT.getVectorElementType();
1307 SmallVector<SDValue, 16> SVOps;
1309 // Extract the input elements by hand.
1310 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1311 // The mask element. This indexes into the input.
1312 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1314 // The input vector this mask element indexes into.
1315 unsigned Input = (unsigned)Idx / NewElts;
1317 if (Input >= array_lengthof(Inputs)) {
1318 // The mask element is "undef" or indexes off the end of the input.
1319 SVOps.push_back(DAG.getUNDEF(EltVT));
1323 // Turn the index into an offset from the start of the input vector.
1324 Idx -= Input * NewElts;
1326 // Extract the vector element by hand.
1327 SVOps.push_back(DAG.getNode(
1328 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1329 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1332 // Construct the Lo/Hi output using a BUILD_VECTOR.
1333 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1334 } else if (InputUsed[0] == -1U) {
1335 // No input vectors were used! The result is undefined.
1336 Output = DAG.getUNDEF(NewVT);
1338 SDValue Op0 = Inputs[InputUsed[0]];
1339 // If only one input was used, use an undefined vector for the other.
1340 SDValue Op1 = InputUsed[1] == -1U ?
1341 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1342 // At least one input vector was used. Create a new shuffle vector.
1343 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1351 //===----------------------------------------------------------------------===//
1352 // Operand Vector Splitting
1353 //===----------------------------------------------------------------------===//
1355 /// SplitVectorOperand - This method is called when the specified operand of the
1356 /// specified node is found to need vector splitting. At this point, all of the
1357 /// result types of the node are known to be legal, but other operands of the
1358 /// node may need legalization as well as the specified one.
1359 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1360 DEBUG(dbgs() << "Split node operand: ";
1363 SDValue Res = SDValue();
1365 // See if the target wants to custom split this node.
1366 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1369 if (!Res.getNode()) {
1370 switch (N->getOpcode()) {
1373 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1377 report_fatal_error("Do not know how to split this operator's "
1380 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1381 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1382 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1383 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1384 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1386 Res = SplitVecOp_TruncateHelper(N);
1388 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1389 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1391 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1394 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1397 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1400 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1403 Res = SplitVecOp_VSELECT(N, OpNo);
1405 case ISD::FP_TO_SINT:
1406 case ISD::FP_TO_UINT:
1407 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1408 Res = SplitVecOp_TruncateHelper(N);
1410 Res = SplitVecOp_UnaryOp(N);
1412 case ISD::SINT_TO_FP:
1413 case ISD::UINT_TO_FP:
1414 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1415 Res = SplitVecOp_TruncateHelper(N);
1417 Res = SplitVecOp_UnaryOp(N);
1422 case ISD::FP_EXTEND:
1423 case ISD::SIGN_EXTEND:
1424 case ISD::ZERO_EXTEND:
1425 case ISD::ANY_EXTEND:
1427 Res = SplitVecOp_UnaryOp(N);
1432 // If the result is null, the sub-method took care of registering results etc.
1433 if (!Res.getNode()) return false;
1435 // If the result is N, the sub-method updated N in place. Tell the legalizer
1437 if (Res.getNode() == N)
1440 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1441 "Invalid operand expansion");
1443 ReplaceValueWith(SDValue(N, 0), Res);
1447 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1448 // The only possibility for an illegal operand is the mask, since result type
1449 // legalization would have handled this node already otherwise.
1450 assert(OpNo == 0 && "Illegal operand must be mask");
1452 SDValue Mask = N->getOperand(0);
1453 SDValue Src0 = N->getOperand(1);
1454 SDValue Src1 = N->getOperand(2);
1455 EVT Src0VT = Src0.getValueType();
1457 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1460 GetSplitVector(N->getOperand(0), Lo, Hi);
1461 assert(Lo.getValueType() == Hi.getValueType() &&
1462 "Lo and Hi have differing types");
1465 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1466 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1468 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1469 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1470 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1471 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1474 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1476 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1478 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1481 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1482 // The result has a legal vector type, but the input needs splitting.
1483 EVT ResVT = N->getValueType(0);
1486 GetSplitVector(N->getOperand(0), Lo, Hi);
1487 EVT InVT = Lo.getValueType();
1489 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1490 InVT.getVectorNumElements());
1492 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1493 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1495 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1498 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1499 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1500 // end up being split all the way down to individual components. Convert the
1501 // split pieces into integers and reassemble.
1503 GetSplitVector(N->getOperand(0), Lo, Hi);
1504 Lo = BitConvertToInteger(Lo);
1505 Hi = BitConvertToInteger(Hi);
1507 if (DAG.getDataLayout().isBigEndian())
1510 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1511 JoinIntegers(Lo, Hi));
1514 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1515 // We know that the extracted result type is legal.
1516 EVT SubVT = N->getValueType(0);
1517 SDValue Idx = N->getOperand(1);
1520 GetSplitVector(N->getOperand(0), Lo, Hi);
1522 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1523 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1525 if (IdxVal < LoElts) {
1526 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1527 "Extracted subvector crosses vector split!");
1528 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1530 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1531 DAG.getConstant(IdxVal - LoElts, dl,
1532 Idx.getValueType()));
1536 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1537 SDValue Vec = N->getOperand(0);
1538 SDValue Idx = N->getOperand(1);
1539 EVT VecVT = Vec.getValueType();
1541 if (isa<ConstantSDNode>(Idx)) {
1542 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1543 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1546 GetSplitVector(Vec, Lo, Hi);
1548 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1550 if (IdxVal < LoElts)
1551 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1552 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1553 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1554 Idx.getValueType())), 0);
1557 // See if the target wants to custom expand this node.
1558 if (CustomLowerNode(N, N->getValueType(0), true))
1561 // Make the vector elements byte-addressable if they aren't already.
1563 EVT EltVT = VecVT.getVectorElementType();
1564 if (EltVT.getSizeInBits() < 8) {
1565 SmallVector<SDValue, 4> ElementOps;
1566 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1567 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1568 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1569 DAG.getConstant(i, dl, MVT::i8)),
1574 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1575 VecVT.getVectorNumElements());
1576 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
1579 // Store the vector to the stack.
1580 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1581 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1582 MachinePointerInfo(), false, false, 0);
1584 // Load back the required element.
1585 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1586 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1587 MachinePointerInfo(), EltVT, false, false, false, 0);
1590 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1594 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1596 SDValue Ch = MGT->getChain();
1597 SDValue Ptr = MGT->getBasePtr();
1598 SDValue Index = MGT->getIndex();
1599 SDValue Mask = MGT->getMask();
1600 unsigned Alignment = MGT->getOriginalAlignment();
1602 SDValue MaskLo, MaskHi;
1603 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1605 EVT MemoryVT = MGT->getMemoryVT();
1606 EVT LoMemVT, HiMemVT;
1607 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1609 SDValue Src0Lo, Src0Hi;
1610 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1612 SDValue IndexHi, IndexLo;
1613 if (Index.getNode())
1614 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1616 IndexLo = IndexHi = Index;
1618 MachineMemOperand *MMO = DAG.getMachineFunction().
1619 getMachineMemOperand(MGT->getPointerInfo(),
1620 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1621 Alignment, MGT->getAAInfo(), MGT->getRanges());
1623 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1624 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1627 MMO = DAG.getMachineFunction().
1628 getMachineMemOperand(MGT->getPointerInfo(),
1629 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1630 Alignment, MGT->getAAInfo(),
1633 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1634 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1637 // Build a factor node to remember that this load is independent of the
1639 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1642 // Legalized the chain result - switch anything that used the old chain to
1644 ReplaceValueWith(SDValue(MGT, 1), Ch);
1646 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1648 ReplaceValueWith(SDValue(MGT, 0), Res);
1652 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1654 SDValue Ch = N->getChain();
1655 SDValue Ptr = N->getBasePtr();
1656 SDValue Mask = N->getMask();
1657 SDValue Data = N->getValue();
1658 EVT MemoryVT = N->getMemoryVT();
1659 unsigned Alignment = N->getOriginalAlignment();
1662 EVT LoMemVT, HiMemVT;
1663 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1665 SDValue DataLo, DataHi;
1666 GetSplitVector(Data, DataLo, DataHi);
1667 SDValue MaskLo, MaskHi;
1668 GetSplitVector(Mask, MaskLo, MaskHi);
1670 // if Alignment is equal to the vector size,
1671 // take the half of it for the second part
1672 unsigned SecondHalfAlignment =
1673 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1674 Alignment/2 : Alignment;
1677 MachineMemOperand *MMO = DAG.getMachineFunction().
1678 getMachineMemOperand(N->getPointerInfo(),
1679 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1680 Alignment, N->getAAInfo(), N->getRanges());
1682 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1683 N->isTruncatingStore());
1685 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1686 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1687 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1689 MMO = DAG.getMachineFunction().
1690 getMachineMemOperand(N->getPointerInfo(),
1691 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1692 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1694 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1695 N->isTruncatingStore());
1697 // Build a factor node to remember that this store is independent of the
1699 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1702 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1704 SDValue Ch = N->getChain();
1705 SDValue Ptr = N->getBasePtr();
1706 SDValue Mask = N->getMask();
1707 SDValue Index = N->getIndex();
1708 SDValue Data = N->getValue();
1709 EVT MemoryVT = N->getMemoryVT();
1710 unsigned Alignment = N->getOriginalAlignment();
1713 EVT LoMemVT, HiMemVT;
1714 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1716 SDValue DataLo, DataHi;
1717 GetSplitVector(Data, DataLo, DataHi);
1718 SDValue MaskLo, MaskHi;
1719 GetSplitVector(Mask, MaskLo, MaskHi);
1721 SDValue PtrLo, PtrHi;
1722 if (Ptr.getValueType().isVector()) // gather form vector of pointers
1723 std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
1725 PtrLo = PtrHi = Ptr;
1727 SDValue IndexHi, IndexLo;
1728 if (Index.getNode())
1729 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1731 IndexLo = IndexHi = Index;
1734 MachineMemOperand *MMO = DAG.getMachineFunction().
1735 getMachineMemOperand(N->getPointerInfo(),
1736 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1737 Alignment, N->getAAInfo(), N->getRanges());
1739 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1740 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1743 MMO = DAG.getMachineFunction().
1744 getMachineMemOperand(N->getPointerInfo(),
1745 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1746 Alignment, N->getAAInfo(), N->getRanges());
1748 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1749 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1752 // Build a factor node to remember that this store is independent of the
1754 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1757 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1758 assert(N->isUnindexed() && "Indexed store of vector?");
1759 assert(OpNo == 1 && "Can only split the stored value");
1762 bool isTruncating = N->isTruncatingStore();
1763 SDValue Ch = N->getChain();
1764 SDValue Ptr = N->getBasePtr();
1765 EVT MemoryVT = N->getMemoryVT();
1766 unsigned Alignment = N->getOriginalAlignment();
1767 bool isVol = N->isVolatile();
1768 bool isNT = N->isNonTemporal();
1769 AAMDNodes AAInfo = N->getAAInfo();
1771 GetSplitVector(N->getOperand(1), Lo, Hi);
1773 EVT LoMemVT, HiMemVT;
1774 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1776 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1779 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1780 LoMemVT, isVol, isNT, Alignment, AAInfo);
1782 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1783 isVol, isNT, Alignment, AAInfo);
1785 // Increment the pointer to the other half.
1786 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1787 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1790 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1791 N->getPointerInfo().getWithOffset(IncrementSize),
1792 HiMemVT, isVol, isNT, Alignment, AAInfo);
1794 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1795 N->getPointerInfo().getWithOffset(IncrementSize),
1796 isVol, isNT, Alignment, AAInfo);
1798 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1801 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1804 // The input operands all must have the same type, and we know the result
1805 // type is valid. Convert this to a buildvector which extracts all the
1807 // TODO: If the input elements are power-two vectors, we could convert this to
1808 // a new CONCAT_VECTORS node with elements that are half-wide.
1809 SmallVector<SDValue, 32> Elts;
1810 EVT EltVT = N->getValueType(0).getVectorElementType();
1811 for (const SDValue &Op : N->op_values()) {
1812 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1814 Elts.push_back(DAG.getNode(
1815 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1816 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1820 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1823 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1824 // The result type is legal, but the input type is illegal. If splitting
1825 // ends up with the result type of each half still being legal, just
1826 // do that. If, however, that would result in an illegal result type,
1827 // we can try to get more clever with power-two vectors. Specifically,
1828 // split the input type, but also widen the result element size, then
1829 // concatenate the halves and truncate again. For example, consider a target
1830 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1831 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1832 // %inlo = v4i32 extract_subvector %in, 0
1833 // %inhi = v4i32 extract_subvector %in, 4
1834 // %lo16 = v4i16 trunc v4i32 %inlo
1835 // %hi16 = v4i16 trunc v4i32 %inhi
1836 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1837 // %res = v8i8 trunc v8i16 %in16
1839 // Without this transform, the original truncate would end up being
1840 // scalarized, which is pretty much always a last resort.
1841 SDValue InVec = N->getOperand(0);
1842 EVT InVT = InVec->getValueType(0);
1843 EVT OutVT = N->getValueType(0);
1844 unsigned NumElements = OutVT.getVectorNumElements();
1845 bool IsFloat = OutVT.isFloatingPoint();
1847 // Widening should have already made sure this is a power-two vector
1848 // if we're trying to split it at all. assert() that's true, just in case.
1849 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1851 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1852 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1854 // If the input elements are only 1/2 the width of the result elements,
1855 // just use the normal splitting. Our trick only work if there's room
1856 // to split more than once.
1857 if (InElementSize <= OutElementSize * 2)
1858 return SplitVecOp_UnaryOp(N);
1861 // Extract the halves of the input via extract_subvector.
1862 SDValue InLoVec, InHiVec;
1863 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1864 // Truncate them to 1/2 the element size.
1865 EVT HalfElementVT = IsFloat ?
1866 EVT::getFloatingPointVT(InElementSize/2) :
1867 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1868 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1870 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1871 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1872 // Concatenate them to get the full intermediate truncation result.
1873 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1874 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1876 // Now finish up by truncating all the way down to the original result
1877 // type. This should normally be something that ends up being legal directly,
1878 // but in theory if a target has very wide vectors and an annoyingly
1879 // restricted set of legal types, this split can chain to build things up.
1881 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1882 DAG.getTargetConstant(
1883 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1884 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1887 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1888 assert(N->getValueType(0).isVector() &&
1889 N->getOperand(0).getValueType().isVector() &&
1890 "Operand types must be vectors");
1891 // The result has a legal vector type, but the input needs splitting.
1892 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1894 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1895 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1896 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1897 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1898 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1900 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1901 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1902 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1903 return PromoteTargetBoolean(Con, N->getValueType(0));
1907 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1908 // The result has a legal vector type, but the input needs splitting.
1909 EVT ResVT = N->getValueType(0);
1912 GetSplitVector(N->getOperand(0), Lo, Hi);
1913 EVT InVT = Lo.getValueType();
1915 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1916 InVT.getVectorNumElements());
1918 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1919 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1921 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1924 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
1925 // The result (and the first input) has a legal vector type, but the second
1926 // input needs splitting.
1927 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
1931 //===----------------------------------------------------------------------===//
1932 // Result Vector Widening
1933 //===----------------------------------------------------------------------===//
1935 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1936 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1940 // See if the target wants to custom widen this node.
1941 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1944 SDValue Res = SDValue();
1945 switch (N->getOpcode()) {
1948 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1952 llvm_unreachable("Do not know how to widen the result of this operator!");
1954 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1955 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1956 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1957 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1958 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1959 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1960 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1961 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1962 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1963 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1964 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1966 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1967 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1968 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1969 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1970 case ISD::VECTOR_SHUFFLE:
1971 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1974 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1989 Res = WidenVecRes_Binary(N);
2002 Res = WidenVecRes_BinaryCanTrap(N);
2005 case ISD::FCOPYSIGN:
2006 Res = WidenVecRes_FCOPYSIGN(N);
2010 Res = WidenVecRes_POWI(N);
2016 Res = WidenVecRes_Shift(N);
2019 case ISD::ANY_EXTEND:
2020 case ISD::FP_EXTEND:
2022 case ISD::FP_TO_SINT:
2023 case ISD::FP_TO_UINT:
2024 case ISD::SIGN_EXTEND:
2025 case ISD::SINT_TO_FP:
2027 case ISD::UINT_TO_FP:
2028 case ISD::ZERO_EXTEND:
2029 Res = WidenVecRes_Convert(N);
2032 case ISD::BITREVERSE:
2046 case ISD::FNEARBYINT:
2053 Res = WidenVecRes_Unary(N);
2056 Res = WidenVecRes_Ternary(N);
2060 // If Res is null, the sub-method took care of registering the result.
2062 SetWidenedVector(SDValue(N, ResNo), Res);
2065 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2066 // Ternary op widening.
2068 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2069 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2070 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2071 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2072 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2075 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2076 // Binary op widening.
2078 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2079 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2080 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2081 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2084 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2085 // Binary op widening for operations that can trap.
2086 unsigned Opcode = N->getOpcode();
2088 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2089 EVT WidenEltVT = WidenVT.getVectorElementType();
2091 unsigned NumElts = VT.getVectorNumElements();
2092 const SDNodeFlags *Flags = N->getFlags();
2093 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2094 NumElts = NumElts / 2;
2095 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2098 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2099 // Operation doesn't trap so just widen as normal.
2100 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2101 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2102 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2105 // No legal vector version so unroll the vector operation and then widen.
2107 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2109 // Since the operation can trap, apply operation on the original vector.
2111 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2112 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2113 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2115 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2116 unsigned ConcatEnd = 0; // Current ConcatOps index.
2117 int Idx = 0; // Current Idx into input vectors.
2119 // NumElts := greatest legal vector size (at most WidenVT)
2120 // while (orig. vector has unhandled elements) {
2121 // take munches of size NumElts from the beginning and add to ConcatOps
2122 // NumElts := next smaller supported vector size or 1
2124 while (CurNumElts != 0) {
2125 while (CurNumElts >= NumElts) {
2126 SDValue EOp1 = DAG.getNode(
2127 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2128 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2129 SDValue EOp2 = DAG.getNode(
2130 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2131 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2132 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2134 CurNumElts -= NumElts;
2137 NumElts = NumElts / 2;
2138 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2139 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2142 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2143 SDValue EOp1 = DAG.getNode(
2144 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2145 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2146 SDValue EOp2 = DAG.getNode(
2147 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2148 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2149 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2156 // Check to see if we have a single operation with the widen type.
2157 if (ConcatEnd == 1) {
2158 VT = ConcatOps[0].getValueType();
2160 return ConcatOps[0];
2163 // while (Some element of ConcatOps is not of type MaxVT) {
2164 // From the end of ConcatOps, collect elements of the same type and put
2165 // them into an op of the next larger supported type
2167 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2168 Idx = ConcatEnd - 1;
2169 VT = ConcatOps[Idx--].getValueType();
2170 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2173 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2177 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2178 } while (!TLI.isTypeLegal(NextVT));
2180 if (!VT.isVector()) {
2181 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2182 SDValue VecOp = DAG.getUNDEF(NextVT);
2183 unsigned NumToInsert = ConcatEnd - Idx - 1;
2184 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2185 VecOp = DAG.getNode(
2186 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2187 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2189 ConcatOps[Idx+1] = VecOp;
2190 ConcatEnd = Idx + 2;
2192 // Vector type, create a CONCAT_VECTORS of type NextVT
2193 SDValue undefVec = DAG.getUNDEF(VT);
2194 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2195 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2196 unsigned RealVals = ConcatEnd - Idx - 1;
2197 unsigned SubConcatEnd = 0;
2198 unsigned SubConcatIdx = Idx + 1;
2199 while (SubConcatEnd < RealVals)
2200 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2201 while (SubConcatEnd < OpsToConcat)
2202 SubConcatOps[SubConcatEnd++] = undefVec;
2203 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2204 NextVT, SubConcatOps);
2205 ConcatEnd = SubConcatIdx + 1;
2209 // Check to see if we have a single operation with the widen type.
2210 if (ConcatEnd == 1) {
2211 VT = ConcatOps[0].getValueType();
2213 return ConcatOps[0];
2216 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2217 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2218 if (NumOps != ConcatEnd ) {
2219 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2220 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2221 ConcatOps[j] = UndefVal;
2223 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2224 makeArrayRef(ConcatOps.data(), NumOps));
2227 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2228 SDValue InOp = N->getOperand(0);
2231 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2232 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2234 EVT InVT = InOp.getValueType();
2235 EVT InEltVT = InVT.getVectorElementType();
2236 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2238 unsigned Opcode = N->getOpcode();
2239 unsigned InVTNumElts = InVT.getVectorNumElements();
2240 const SDNodeFlags *Flags = N->getFlags();
2241 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2242 InOp = GetWidenedVector(N->getOperand(0));
2243 InVT = InOp.getValueType();
2244 InVTNumElts = InVT.getVectorNumElements();
2245 if (InVTNumElts == WidenNumElts) {
2246 if (N->getNumOperands() == 1)
2247 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2248 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2252 if (TLI.isTypeLegal(InWidenVT)) {
2253 // Because the result and the input are different vector types, widening
2254 // the result could create a legal type but widening the input might make
2255 // it an illegal type that might lead to repeatedly splitting the input
2256 // and then widening it. To avoid this, we widen the input only if
2257 // it results in a legal type.
2258 if (WidenNumElts % InVTNumElts == 0) {
2259 // Widen the input and call convert on the widened input vector.
2260 unsigned NumConcat = WidenNumElts/InVTNumElts;
2261 SmallVector<SDValue, 16> Ops(NumConcat);
2263 SDValue UndefVal = DAG.getUNDEF(InVT);
2264 for (unsigned i = 1; i != NumConcat; ++i)
2266 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2267 if (N->getNumOperands() == 1)
2268 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2269 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2272 if (InVTNumElts % WidenNumElts == 0) {
2273 SDValue InVal = DAG.getNode(
2274 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2275 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2276 // Extract the input and convert the shorten input vector.
2277 if (N->getNumOperands() == 1)
2278 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2279 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2283 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2284 SmallVector<SDValue, 16> Ops(WidenNumElts);
2285 EVT EltVT = WidenVT.getVectorElementType();
2286 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2288 for (i=0; i < MinElts; ++i) {
2289 SDValue Val = DAG.getNode(
2290 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2291 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2292 if (N->getNumOperands() == 1)
2293 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2295 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2298 SDValue UndefVal = DAG.getUNDEF(EltVT);
2299 for (; i < WidenNumElts; ++i)
2302 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2305 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2306 // If this is an FCOPYSIGN with same input types, we can treat it as a
2307 // normal (can trap) binary op.
2308 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2309 return WidenVecRes_BinaryCanTrap(N);
2311 // If the types are different, fall back to unrolling.
2312 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2313 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2316 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2317 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2318 SDValue InOp = GetWidenedVector(N->getOperand(0));
2319 SDValue ShOp = N->getOperand(1);
2320 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2323 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2324 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2325 SDValue InOp = GetWidenedVector(N->getOperand(0));
2326 SDValue ShOp = N->getOperand(1);
2328 EVT ShVT = ShOp.getValueType();
2329 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2330 ShOp = GetWidenedVector(ShOp);
2331 ShVT = ShOp.getValueType();
2333 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2334 ShVT.getVectorElementType(),
2335 WidenVT.getVectorNumElements());
2336 if (ShVT != ShWidenVT)
2337 ShOp = ModifyToType(ShOp, ShWidenVT);
2339 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2342 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2343 // Unary op widening.
2344 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2345 SDValue InOp = GetWidenedVector(N->getOperand(0));
2346 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2349 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2350 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2351 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2352 cast<VTSDNode>(N->getOperand(1))->getVT()
2353 .getVectorElementType(),
2354 WidenVT.getVectorNumElements());
2355 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2356 return DAG.getNode(N->getOpcode(), SDLoc(N),
2357 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2360 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2361 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2362 return GetWidenedVector(WidenVec);
2365 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2366 SDValue InOp = N->getOperand(0);
2367 EVT InVT = InOp.getValueType();
2368 EVT VT = N->getValueType(0);
2369 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2372 switch (getTypeAction(InVT)) {
2373 case TargetLowering::TypeLegal:
2375 case TargetLowering::TypePromoteInteger:
2376 // If the incoming type is a vector that is being promoted, then
2377 // we know that the elements are arranged differently and that we
2378 // must perform the conversion using a stack slot.
2379 if (InVT.isVector())
2382 // If the InOp is promoted to the same size, convert it. Otherwise,
2383 // fall out of the switch and widen the promoted input.
2384 InOp = GetPromotedInteger(InOp);
2385 InVT = InOp.getValueType();
2386 if (WidenVT.bitsEq(InVT))
2387 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2389 case TargetLowering::TypeSoftenFloat:
2390 case TargetLowering::TypePromoteFloat:
2391 case TargetLowering::TypeExpandInteger:
2392 case TargetLowering::TypeExpandFloat:
2393 case TargetLowering::TypeScalarizeVector:
2394 case TargetLowering::TypeSplitVector:
2396 case TargetLowering::TypeWidenVector:
2397 // If the InOp is widened to the same size, convert it. Otherwise, fall
2398 // out of the switch and widen the widened input.
2399 InOp = GetWidenedVector(InOp);
2400 InVT = InOp.getValueType();
2401 if (WidenVT.bitsEq(InVT))
2402 // The input widens to the same size. Convert to the widen value.
2403 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2407 unsigned WidenSize = WidenVT.getSizeInBits();
2408 unsigned InSize = InVT.getSizeInBits();
2409 // x86mmx is not an acceptable vector element type, so don't try.
2410 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2411 // Determine new input vector type. The new input vector type will use
2412 // the same element type (if its a vector) or use the input type as a
2413 // vector. It is the same size as the type to widen to.
2415 unsigned NewNumElts = WidenSize / InSize;
2416 if (InVT.isVector()) {
2417 EVT InEltVT = InVT.getVectorElementType();
2418 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2419 WidenSize / InEltVT.getSizeInBits());
2421 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2424 if (TLI.isTypeLegal(NewInVT)) {
2425 // Because the result and the input are different vector types, widening
2426 // the result could create a legal type but widening the input might make
2427 // it an illegal type that might lead to repeatedly splitting the input
2428 // and then widening it. To avoid this, we widen the input only if
2429 // it results in a legal type.
2430 SmallVector<SDValue, 16> Ops(NewNumElts);
2431 SDValue UndefVal = DAG.getUNDEF(InVT);
2433 for (unsigned i = 1; i < NewNumElts; ++i)
2437 if (InVT.isVector())
2438 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2440 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2441 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2445 return CreateStackStoreLoad(InOp, WidenVT);
2448 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2450 // Build a vector with undefined for the new nodes.
2451 EVT VT = N->getValueType(0);
2453 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2454 // type. The UNDEFs need to have the same type as the existing operands.
2455 EVT EltVT = N->getOperand(0).getValueType();
2456 unsigned NumElts = VT.getVectorNumElements();
2458 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2459 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2461 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2462 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2463 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2465 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2468 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2469 EVT InVT = N->getOperand(0).getValueType();
2470 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2472 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2473 unsigned NumInElts = InVT.getVectorNumElements();
2474 unsigned NumOperands = N->getNumOperands();
2476 bool InputWidened = false; // Indicates we need to widen the input.
2477 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2478 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2479 // Add undef vectors to widen to correct length.
2480 unsigned NumConcat = WidenVT.getVectorNumElements() /
2481 InVT.getVectorNumElements();
2482 SDValue UndefVal = DAG.getUNDEF(InVT);
2483 SmallVector<SDValue, 16> Ops(NumConcat);
2484 for (unsigned i=0; i < NumOperands; ++i)
2485 Ops[i] = N->getOperand(i);
2486 for (unsigned i = NumOperands; i != NumConcat; ++i)
2488 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2491 InputWidened = true;
2492 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2493 // The inputs and the result are widen to the same value.
2495 for (i=1; i < NumOperands; ++i)
2496 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2499 if (i == NumOperands)
2500 // Everything but the first operand is an UNDEF so just return the
2501 // widened first operand.
2502 return GetWidenedVector(N->getOperand(0));
2504 if (NumOperands == 2) {
2505 // Replace concat of two operands with a shuffle.
2506 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2507 for (unsigned i = 0; i < NumInElts; ++i) {
2509 MaskOps[i + NumInElts] = i + WidenNumElts;
2511 return DAG.getVectorShuffle(WidenVT, dl,
2512 GetWidenedVector(N->getOperand(0)),
2513 GetWidenedVector(N->getOperand(1)),
2519 // Fall back to use extracts and build vector.
2520 EVT EltVT = WidenVT.getVectorElementType();
2521 SmallVector<SDValue, 16> Ops(WidenNumElts);
2523 for (unsigned i=0; i < NumOperands; ++i) {
2524 SDValue InOp = N->getOperand(i);
2526 InOp = GetWidenedVector(InOp);
2527 for (unsigned j=0; j < NumInElts; ++j)
2528 Ops[Idx++] = DAG.getNode(
2529 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2530 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2532 SDValue UndefVal = DAG.getUNDEF(EltVT);
2533 for (; Idx < WidenNumElts; ++Idx)
2534 Ops[Idx] = UndefVal;
2535 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2538 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2540 SDValue InOp = N->getOperand(0);
2541 SDValue RndOp = N->getOperand(3);
2542 SDValue SatOp = N->getOperand(4);
2544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2545 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2547 EVT InVT = InOp.getValueType();
2548 EVT InEltVT = InVT.getVectorElementType();
2549 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2551 SDValue DTyOp = DAG.getValueType(WidenVT);
2552 SDValue STyOp = DAG.getValueType(InWidenVT);
2553 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2555 unsigned InVTNumElts = InVT.getVectorNumElements();
2556 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2557 InOp = GetWidenedVector(InOp);
2558 InVT = InOp.getValueType();
2559 InVTNumElts = InVT.getVectorNumElements();
2560 if (InVTNumElts == WidenNumElts)
2561 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2565 if (TLI.isTypeLegal(InWidenVT)) {
2566 // Because the result and the input are different vector types, widening
2567 // the result could create a legal type but widening the input might make
2568 // it an illegal type that might lead to repeatedly splitting the input
2569 // and then widening it. To avoid this, we widen the input only if
2570 // it results in a legal type.
2571 if (WidenNumElts % InVTNumElts == 0) {
2572 // Widen the input and call convert on the widened input vector.
2573 unsigned NumConcat = WidenNumElts/InVTNumElts;
2574 SmallVector<SDValue, 16> Ops(NumConcat);
2576 SDValue UndefVal = DAG.getUNDEF(InVT);
2577 for (unsigned i = 1; i != NumConcat; ++i)
2580 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2581 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2585 if (InVTNumElts % WidenNumElts == 0) {
2586 // Extract the input and convert the shorten input vector.
2588 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2589 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2590 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2595 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2596 SmallVector<SDValue, 16> Ops(WidenNumElts);
2597 EVT EltVT = WidenVT.getVectorElementType();
2598 DTyOp = DAG.getValueType(EltVT);
2599 STyOp = DAG.getValueType(InEltVT);
2601 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2603 for (i=0; i < MinElts; ++i) {
2604 SDValue ExtVal = DAG.getNode(
2605 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2606 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2607 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2611 SDValue UndefVal = DAG.getUNDEF(EltVT);
2612 for (; i < WidenNumElts; ++i)
2615 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2618 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2619 EVT VT = N->getValueType(0);
2620 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2621 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2622 SDValue InOp = N->getOperand(0);
2623 SDValue Idx = N->getOperand(1);
2626 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2627 InOp = GetWidenedVector(InOp);
2629 EVT InVT = InOp.getValueType();
2631 // Check if we can just return the input vector after widening.
2632 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2633 if (IdxVal == 0 && InVT == WidenVT)
2636 // Check if we can extract from the vector.
2637 unsigned InNumElts = InVT.getVectorNumElements();
2638 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2639 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2641 // We could try widening the input to the right length but for now, extract
2642 // the original elements, fill the rest with undefs and build a vector.
2643 SmallVector<SDValue, 16> Ops(WidenNumElts);
2644 EVT EltVT = VT.getVectorElementType();
2645 unsigned NumElts = VT.getVectorNumElements();
2647 for (i=0; i < NumElts; ++i)
2649 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2650 DAG.getConstant(IdxVal + i, dl,
2651 TLI.getVectorIdxTy(DAG.getDataLayout())));
2653 SDValue UndefVal = DAG.getUNDEF(EltVT);
2654 for (; i < WidenNumElts; ++i)
2656 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2659 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2660 SDValue InOp = GetWidenedVector(N->getOperand(0));
2661 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2662 InOp.getValueType(), InOp,
2663 N->getOperand(1), N->getOperand(2));
2666 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2667 LoadSDNode *LD = cast<LoadSDNode>(N);
2668 ISD::LoadExtType ExtType = LD->getExtensionType();
2671 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2672 if (ExtType != ISD::NON_EXTLOAD)
2673 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2675 Result = GenWidenVectorLoads(LdChain, LD);
2677 // If we generate a single load, we can use that for the chain. Otherwise,
2678 // build a factor node to remember the multiple loads are independent and
2681 if (LdChain.size() == 1)
2682 NewChain = LdChain[0];
2684 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2686 // Modified the chain - switch anything that used the old chain to use
2688 ReplaceValueWith(SDValue(N, 1), NewChain);
2693 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2695 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2696 SDValue Mask = N->getMask();
2697 EVT MaskVT = Mask.getValueType();
2698 SDValue Src0 = GetWidenedVector(N->getSrc0());
2699 ISD::LoadExtType ExtType = N->getExtensionType();
2702 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2703 Mask = GetWidenedVector(Mask);
2705 EVT BoolVT = getSetCCResultType(WidenVT);
2707 // We can't use ModifyToType() because we should fill the mask with
2709 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2710 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2712 unsigned NumConcat = WidenNumElts / MaskNumElts;
2713 SmallVector<SDValue, 16> Ops(NumConcat);
2714 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2716 for (unsigned i = 1; i != NumConcat; ++i)
2719 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2722 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2723 Mask, Src0, N->getMemoryVT(),
2724 N->getMemOperand(), ExtType);
2725 // Legalized the chain result - switch anything that used the old chain to
2727 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2731 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2732 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2733 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2734 WidenVT, N->getOperand(0));
2737 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2738 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2739 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2741 SDValue Cond1 = N->getOperand(0);
2742 EVT CondVT = Cond1.getValueType();
2743 if (CondVT.isVector()) {
2744 EVT CondEltVT = CondVT.getVectorElementType();
2745 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2746 CondEltVT, WidenNumElts);
2747 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2748 Cond1 = GetWidenedVector(Cond1);
2750 // If we have to split the condition there is no point in widening the
2751 // select. This would result in an cycle of widening the select ->
2752 // widening the condition operand -> splitting the condition operand ->
2753 // splitting the select -> widening the select. Instead split this select
2754 // further and widen the resulting type.
2755 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2756 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2757 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2761 if (Cond1.getValueType() != CondWidenVT)
2762 Cond1 = ModifyToType(Cond1, CondWidenVT);
2765 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2766 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2767 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2768 return DAG.getNode(N->getOpcode(), SDLoc(N),
2769 WidenVT, Cond1, InOp1, InOp2);
2772 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2773 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2774 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2775 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2776 InOp1.getValueType(), N->getOperand(0),
2777 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2780 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2781 assert(N->getValueType(0).isVector() ==
2782 N->getOperand(0).getValueType().isVector() &&
2783 "Scalar/Vector type mismatch");
2784 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2786 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2787 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2788 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2789 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2790 InOp1, InOp2, N->getOperand(2));
2793 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2794 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2795 return DAG.getUNDEF(WidenVT);
2798 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2799 EVT VT = N->getValueType(0);
2802 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2803 unsigned NumElts = VT.getVectorNumElements();
2804 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2806 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2807 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2809 // Adjust mask based on new input vector length.
2810 SmallVector<int, 16> NewMask;
2811 for (unsigned i = 0; i != NumElts; ++i) {
2812 int Idx = N->getMaskElt(i);
2813 if (Idx < (int)NumElts)
2814 NewMask.push_back(Idx);
2816 NewMask.push_back(Idx - NumElts + WidenNumElts);
2818 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2819 NewMask.push_back(-1);
2820 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2823 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2824 assert(N->getValueType(0).isVector() &&
2825 N->getOperand(0).getValueType().isVector() &&
2826 "Operands must be vectors");
2827 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2828 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2830 SDValue InOp1 = N->getOperand(0);
2831 EVT InVT = InOp1.getValueType();
2832 assert(InVT.isVector() && "can not widen non-vector type");
2833 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2834 InVT.getVectorElementType(), WidenNumElts);
2836 // The input and output types often differ here, and it could be that while
2837 // we'd prefer to widen the result type, the input operands have been split.
2838 // In this case, we also need to split the result of this node as well.
2839 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2840 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2841 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2845 InOp1 = GetWidenedVector(InOp1);
2846 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2848 // Assume that the input and output will be widen appropriately. If not,
2849 // we will have to unroll it at some point.
2850 assert(InOp1.getValueType() == WidenInVT &&
2851 InOp2.getValueType() == WidenInVT &&
2852 "Input not widened to expected type!");
2854 return DAG.getNode(ISD::SETCC, SDLoc(N),
2855 WidenVT, InOp1, InOp2, N->getOperand(2));
2859 //===----------------------------------------------------------------------===//
2860 // Widen Vector Operand
2861 //===----------------------------------------------------------------------===//
2862 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2863 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2866 SDValue Res = SDValue();
2868 // See if the target wants to custom widen this node.
2869 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2872 switch (N->getOpcode()) {
2875 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2879 llvm_unreachable("Do not know how to widen this operator's operand!");
2881 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2882 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2883 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2884 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2885 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2886 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2887 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2888 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
2890 case ISD::ANY_EXTEND:
2891 case ISD::SIGN_EXTEND:
2892 case ISD::ZERO_EXTEND:
2893 Res = WidenVecOp_EXTEND(N);
2896 case ISD::FP_EXTEND:
2897 case ISD::FP_TO_SINT:
2898 case ISD::FP_TO_UINT:
2899 case ISD::SINT_TO_FP:
2900 case ISD::UINT_TO_FP:
2902 Res = WidenVecOp_Convert(N);
2906 // If Res is null, the sub-method took care of registering the result.
2907 if (!Res.getNode()) return false;
2909 // If the result is N, the sub-method updated N in place. Tell the legalizer
2911 if (Res.getNode() == N)
2915 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2916 "Invalid operand expansion");
2918 ReplaceValueWith(SDValue(N, 0), Res);
2922 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2924 EVT VT = N->getValueType(0);
2926 SDValue InOp = N->getOperand(0);
2927 // If some legalization strategy other than widening is used on the operand,
2928 // we can't safely assume that just extending the low lanes is the correct
2930 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2931 return WidenVecOp_Convert(N);
2932 InOp = GetWidenedVector(InOp);
2933 assert(VT.getVectorNumElements() <
2934 InOp.getValueType().getVectorNumElements() &&
2935 "Input wasn't widened!");
2937 // We may need to further widen the operand until it has the same total
2938 // vector size as the result.
2939 EVT InVT = InOp.getValueType();
2940 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2941 EVT InEltVT = InVT.getVectorElementType();
2942 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2943 EVT FixedVT = (MVT::SimpleValueType)i;
2944 EVT FixedEltVT = FixedVT.getVectorElementType();
2945 if (TLI.isTypeLegal(FixedVT) &&
2946 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2947 FixedEltVT == InEltVT) {
2948 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2949 "Not enough elements in the fixed type for the operand!");
2950 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2951 "We can't have the same type as we started with!");
2952 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2954 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
2955 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2958 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2959 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2963 InVT = InOp.getValueType();
2964 if (InVT.getSizeInBits() != VT.getSizeInBits())
2965 // We couldn't find a legal vector type that was a widening of the input
2966 // and could be extended in-register to the result type, so we have to
2968 return WidenVecOp_Convert(N);
2971 // Use special DAG nodes to represent the operation of extending the
2973 switch (N->getOpcode()) {
2975 llvm_unreachable("Extend legalization on on extend operation!");
2976 case ISD::ANY_EXTEND:
2977 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2978 case ISD::SIGN_EXTEND:
2979 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2980 case ISD::ZERO_EXTEND:
2981 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2985 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
2986 // The result (and first input) is legal, but the second input is illegal.
2987 // We can't do much to fix that, so just unroll and let the extracts off of
2988 // the second input be widened as needed later.
2989 return DAG.UnrollVectorOp(N);
2992 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2993 // Since the result is legal and the input is illegal, it is unlikely
2994 // that we can fix the input to a legal type so unroll the convert
2995 // into some scalar code and create a nasty build vector.
2996 EVT VT = N->getValueType(0);
2997 EVT EltVT = VT.getVectorElementType();
2999 unsigned NumElts = VT.getVectorNumElements();
3000 SDValue InOp = N->getOperand(0);
3001 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3002 InOp = GetWidenedVector(InOp);
3003 EVT InVT = InOp.getValueType();
3004 EVT InEltVT = InVT.getVectorElementType();
3006 unsigned Opcode = N->getOpcode();
3007 SmallVector<SDValue, 16> Ops(NumElts);
3008 for (unsigned i=0; i < NumElts; ++i)
3009 Ops[i] = DAG.getNode(
3012 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3013 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3015 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3018 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3019 EVT VT = N->getValueType(0);
3020 SDValue InOp = GetWidenedVector(N->getOperand(0));
3021 EVT InWidenVT = InOp.getValueType();
3024 // Check if we can convert between two legal vector types and extract.
3025 unsigned InWidenSize = InWidenVT.getSizeInBits();
3026 unsigned Size = VT.getSizeInBits();
3027 // x86mmx is not an acceptable vector element type, so don't try.
3028 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3029 unsigned NewNumElts = InWidenSize / Size;
3030 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3031 if (TLI.isTypeLegal(NewVT)) {
3032 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3034 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3035 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3039 return CreateStackStoreLoad(InOp, VT);
3042 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3043 // If the input vector is not legal, it is likely that we will not find a
3044 // legal vector of the same size. Replace the concatenate vector with a
3045 // nasty build vector.
3046 EVT VT = N->getValueType(0);
3047 EVT EltVT = VT.getVectorElementType();
3049 unsigned NumElts = VT.getVectorNumElements();
3050 SmallVector<SDValue, 16> Ops(NumElts);
3052 EVT InVT = N->getOperand(0).getValueType();
3053 unsigned NumInElts = InVT.getVectorNumElements();
3056 unsigned NumOperands = N->getNumOperands();
3057 for (unsigned i=0; i < NumOperands; ++i) {
3058 SDValue InOp = N->getOperand(i);
3059 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3060 InOp = GetWidenedVector(InOp);
3061 for (unsigned j=0; j < NumInElts; ++j)
3062 Ops[Idx++] = DAG.getNode(
3063 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3064 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3066 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3069 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3070 SDValue InOp = GetWidenedVector(N->getOperand(0));
3071 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3072 N->getValueType(0), InOp, N->getOperand(1));
3075 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3076 SDValue InOp = GetWidenedVector(N->getOperand(0));
3077 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3078 N->getValueType(0), InOp, N->getOperand(1));
3081 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3082 // We have to widen the value but we want only to store the original
3084 StoreSDNode *ST = cast<StoreSDNode>(N);
3086 SmallVector<SDValue, 16> StChain;
3087 if (ST->isTruncatingStore())
3088 GenWidenVectorTruncStores(StChain, ST);
3090 GenWidenVectorStores(StChain, ST);
3092 if (StChain.size() == 1)
3095 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3098 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3099 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3100 SDValue Mask = MST->getMask();
3101 EVT MaskVT = Mask.getValueType();
3102 SDValue StVal = MST->getValue();
3104 SDValue WideVal = GetWidenedVector(StVal);
3107 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3108 Mask = GetWidenedVector(Mask);
3110 // The mask should be widened as well
3111 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3112 // We can't use ModifyToType() because we should fill the mask with
3114 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3115 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3117 unsigned NumConcat = WidenNumElts / MaskNumElts;
3118 SmallVector<SDValue, 16> Ops(NumConcat);
3119 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3121 for (unsigned i = 1; i != NumConcat; ++i)
3124 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3126 assert(Mask.getValueType().getVectorNumElements() ==
3127 WideVal.getValueType().getVectorNumElements() &&
3128 "Mask and data vectors should have the same number of elements");
3129 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3130 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3134 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3135 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3136 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3139 // WARNING: In this code we widen the compare instruction with garbage.
3140 // This garbage may contain denormal floats which may be slow. Is this a real
3141 // concern ? Should we zero the unused lanes if this is a float compare ?
3143 // Get a new SETCC node to compare the newly widened operands.
3144 // Only some of the compared elements are legal.
3145 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3146 InOp0.getValueType());
3147 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3148 SVT, InOp0, InOp1, N->getOperand(2));
3150 // Extract the needed results from the result vector.
3151 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3152 SVT.getVectorElementType(),
3153 N->getValueType(0).getVectorNumElements());
3154 SDValue CC = DAG.getNode(
3155 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3156 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3158 return PromoteTargetBoolean(CC, N->getValueType(0));
3162 //===----------------------------------------------------------------------===//
3163 // Vector Widening Utilities
3164 //===----------------------------------------------------------------------===//
3166 // Utility function to find the type to chop up a widen vector for load/store
3167 // TLI: Target lowering used to determine legal types.
3168 // Width: Width left need to load/store.
3169 // WidenVT: The widen vector type to load to/store from
3170 // Align: If 0, don't allow use of a wider type
3171 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3173 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3174 unsigned Width, EVT WidenVT,
3175 unsigned Align = 0, unsigned WidenEx = 0) {
3176 EVT WidenEltVT = WidenVT.getVectorElementType();
3177 unsigned WidenWidth = WidenVT.getSizeInBits();
3178 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3179 unsigned AlignInBits = Align*8;
3181 // If we have one element to load/store, return it.
3182 EVT RetVT = WidenEltVT;
3183 if (Width == WidenEltWidth)
3186 // See if there is larger legal integer than the element type to load/store
3188 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3189 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3190 EVT MemVT((MVT::SimpleValueType) VT);
3191 unsigned MemVTWidth = MemVT.getSizeInBits();
3192 if (MemVT.getSizeInBits() <= WidenEltWidth)
3194 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3195 if ((Action == TargetLowering::TypeLegal ||
3196 Action == TargetLowering::TypePromoteInteger) &&
3197 (WidenWidth % MemVTWidth) == 0 &&
3198 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3199 (MemVTWidth <= Width ||
3200 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3206 // See if there is a larger vector type to load/store that has the same vector
3207 // element type and is evenly divisible with the WidenVT.
3208 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3209 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3210 EVT MemVT = (MVT::SimpleValueType) VT;
3211 unsigned MemVTWidth = MemVT.getSizeInBits();
3212 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3213 (WidenWidth % MemVTWidth) == 0 &&
3214 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3215 (MemVTWidth <= Width ||
3216 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3217 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3225 // Builds a vector type from scalar loads
3226 // VecTy: Resulting Vector type
3227 // LDOps: Load operators to build a vector type
3228 // [Start,End) the list of loads to use.
3229 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3230 SmallVectorImpl<SDValue> &LdOps,
3231 unsigned Start, unsigned End) {
3232 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3233 SDLoc dl(LdOps[Start]);
3234 EVT LdTy = LdOps[Start].getValueType();
3235 unsigned Width = VecTy.getSizeInBits();
3236 unsigned NumElts = Width / LdTy.getSizeInBits();
3237 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3240 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3242 for (unsigned i = Start + 1; i != End; ++i) {
3243 EVT NewLdTy = LdOps[i].getValueType();
3244 if (NewLdTy != LdTy) {
3245 NumElts = Width / NewLdTy.getSizeInBits();
3246 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3247 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3248 // Readjust position and vector position based on new load type
3249 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3252 VecOp = DAG.getNode(
3253 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3254 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3256 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3259 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3261 // The strategy assumes that we can efficiently load powers of two widths.
3262 // The routines chops the vector into the largest vector loads with the same
3263 // element type or scalar loads and then recombines it to the widen vector
3265 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3266 unsigned WidenWidth = WidenVT.getSizeInBits();
3267 EVT LdVT = LD->getMemoryVT();
3269 assert(LdVT.isVector() && WidenVT.isVector());
3270 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3273 SDValue Chain = LD->getChain();
3274 SDValue BasePtr = LD->getBasePtr();
3275 unsigned Align = LD->getAlignment();
3276 bool isVolatile = LD->isVolatile();
3277 bool isNonTemporal = LD->isNonTemporal();
3278 bool isInvariant = LD->isInvariant();
3279 AAMDNodes AAInfo = LD->getAAInfo();
3281 int LdWidth = LdVT.getSizeInBits();
3282 int WidthDiff = WidenWidth - LdWidth; // Difference
3283 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3285 // Find the vector type that can load from.
3286 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3287 int NewVTWidth = NewVT.getSizeInBits();
3288 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3289 isVolatile, isNonTemporal, isInvariant, Align,
3291 LdChain.push_back(LdOp.getValue(1));
3293 // Check if we can load the element with one instruction
3294 if (LdWidth <= NewVTWidth) {
3295 if (!NewVT.isVector()) {
3296 unsigned NumElts = WidenWidth / NewVTWidth;
3297 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3298 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3299 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3301 if (NewVT == WidenVT)
3304 assert(WidenWidth % NewVTWidth == 0);
3305 unsigned NumConcat = WidenWidth / NewVTWidth;
3306 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3307 SDValue UndefVal = DAG.getUNDEF(NewVT);
3308 ConcatOps[0] = LdOp;
3309 for (unsigned i = 1; i != NumConcat; ++i)
3310 ConcatOps[i] = UndefVal;
3311 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3314 // Load vector by using multiple loads from largest vector to scalar
3315 SmallVector<SDValue, 16> LdOps;
3316 LdOps.push_back(LdOp);
3318 LdWidth -= NewVTWidth;
3319 unsigned Offset = 0;
3321 while (LdWidth > 0) {
3322 unsigned Increment = NewVTWidth / 8;
3323 Offset += Increment;
3324 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3325 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3328 if (LdWidth < NewVTWidth) {
3329 // Our current type we are using is too large, find a better size
3330 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3331 NewVTWidth = NewVT.getSizeInBits();
3332 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3333 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3334 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3336 LdChain.push_back(L.getValue(1));
3337 if (L->getValueType(0).isVector()) {
3338 SmallVector<SDValue, 16> Loads;
3340 unsigned size = L->getValueSizeInBits(0);
3341 while (size < LdOp->getValueSizeInBits(0)) {
3342 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3343 size += L->getValueSizeInBits(0);
3345 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3348 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3349 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3350 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3352 LdChain.push_back(L.getValue(1));
3358 LdWidth -= NewVTWidth;
3361 // Build the vector from the loads operations
3362 unsigned End = LdOps.size();
3363 if (!LdOps[0].getValueType().isVector())
3364 // All the loads are scalar loads.
3365 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3367 // If the load contains vectors, build the vector using concat vector.
3368 // All of the vectors used to loads are power of 2 and the scalars load
3369 // can be combined to make a power of 2 vector.
3370 SmallVector<SDValue, 16> ConcatOps(End);
3373 EVT LdTy = LdOps[i].getValueType();
3374 // First combine the scalar loads to a vector
3375 if (!LdTy.isVector()) {
3376 for (--i; i >= 0; --i) {
3377 LdTy = LdOps[i].getValueType();
3378 if (LdTy.isVector())
3381 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3383 ConcatOps[--Idx] = LdOps[i];
3384 for (--i; i >= 0; --i) {
3385 EVT NewLdTy = LdOps[i].getValueType();
3386 if (NewLdTy != LdTy) {
3387 // Create a larger vector
3388 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3389 makeArrayRef(&ConcatOps[Idx], End - Idx));
3393 ConcatOps[--Idx] = LdOps[i];
3396 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3397 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3398 makeArrayRef(&ConcatOps[Idx], End - Idx));
3400 // We need to fill the rest with undefs to build the vector
3401 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3402 SmallVector<SDValue, 16> WidenOps(NumOps);
3403 SDValue UndefVal = DAG.getUNDEF(LdTy);
3406 for (; i != End-Idx; ++i)
3407 WidenOps[i] = ConcatOps[Idx+i];
3408 for (; i != NumOps; ++i)
3409 WidenOps[i] = UndefVal;
3411 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3415 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3417 ISD::LoadExtType ExtType) {
3418 // For extension loads, it may not be more efficient to chop up the vector
3419 // and then extended it. Instead, we unroll the load and build a new vector.
3420 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3421 EVT LdVT = LD->getMemoryVT();
3423 assert(LdVT.isVector() && WidenVT.isVector());
3426 SDValue Chain = LD->getChain();
3427 SDValue BasePtr = LD->getBasePtr();
3428 unsigned Align = LD->getAlignment();
3429 bool isVolatile = LD->isVolatile();
3430 bool isNonTemporal = LD->isNonTemporal();
3431 bool isInvariant = LD->isInvariant();
3432 AAMDNodes AAInfo = LD->getAAInfo();
3434 EVT EltVT = WidenVT.getVectorElementType();
3435 EVT LdEltVT = LdVT.getVectorElementType();
3436 unsigned NumElts = LdVT.getVectorNumElements();
3438 // Load each element and widen
3439 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3440 SmallVector<SDValue, 16> Ops(WidenNumElts);
3441 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3442 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3443 LD->getPointerInfo(),
3444 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3446 LdChain.push_back(Ops[0].getValue(1));
3447 unsigned i = 0, Offset = Increment;
3448 for (i=1; i < NumElts; ++i, Offset += Increment) {
3449 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3451 DAG.getConstant(Offset, dl,
3452 BasePtr.getValueType()));
3453 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3454 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3455 isVolatile, isNonTemporal, isInvariant, Align,
3457 LdChain.push_back(Ops[i].getValue(1));
3460 // Fill the rest with undefs
3461 SDValue UndefVal = DAG.getUNDEF(EltVT);
3462 for (; i != WidenNumElts; ++i)
3465 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3469 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3471 // The strategy assumes that we can efficiently store powers of two widths.
3472 // The routines chops the vector into the largest vector stores with the same
3473 // element type or scalar stores.
3474 SDValue Chain = ST->getChain();
3475 SDValue BasePtr = ST->getBasePtr();
3476 unsigned Align = ST->getAlignment();
3477 bool isVolatile = ST->isVolatile();
3478 bool isNonTemporal = ST->isNonTemporal();
3479 AAMDNodes AAInfo = ST->getAAInfo();
3480 SDValue ValOp = GetWidenedVector(ST->getValue());
3483 EVT StVT = ST->getMemoryVT();
3484 unsigned StWidth = StVT.getSizeInBits();
3485 EVT ValVT = ValOp.getValueType();
3486 unsigned ValWidth = ValVT.getSizeInBits();
3487 EVT ValEltVT = ValVT.getVectorElementType();
3488 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3489 assert(StVT.getVectorElementType() == ValEltVT);
3491 int Idx = 0; // current index to store
3492 unsigned Offset = 0; // offset from base to store
3493 while (StWidth != 0) {
3494 // Find the largest vector type we can store with
3495 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3496 unsigned NewVTWidth = NewVT.getSizeInBits();
3497 unsigned Increment = NewVTWidth / 8;
3498 if (NewVT.isVector()) {
3499 unsigned NumVTElts = NewVT.getVectorNumElements();
3501 SDValue EOp = DAG.getNode(
3502 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3503 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3504 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3505 ST->getPointerInfo().getWithOffset(Offset),
3506 isVolatile, isNonTemporal,
3507 MinAlign(Align, Offset), AAInfo));
3508 StWidth -= NewVTWidth;
3509 Offset += Increment;
3511 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3512 DAG.getConstant(Increment, dl,
3513 BasePtr.getValueType()));
3514 } while (StWidth != 0 && StWidth >= NewVTWidth);
3516 // Cast the vector to the scalar type we can store
3517 unsigned NumElts = ValWidth / NewVTWidth;
3518 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3519 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3520 // Readjust index position based on new vector type
3521 Idx = Idx * ValEltWidth / NewVTWidth;
3523 SDValue EOp = DAG.getNode(
3524 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3525 DAG.getConstant(Idx++, dl,
3526 TLI.getVectorIdxTy(DAG.getDataLayout())));
3527 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3528 ST->getPointerInfo().getWithOffset(Offset),
3529 isVolatile, isNonTemporal,
3530 MinAlign(Align, Offset), AAInfo));
3531 StWidth -= NewVTWidth;
3532 Offset += Increment;
3533 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3534 DAG.getConstant(Increment, dl,
3535 BasePtr.getValueType()));
3536 } while (StWidth != 0 && StWidth >= NewVTWidth);
3537 // Restore index back to be relative to the original widen element type
3538 Idx = Idx * NewVTWidth / ValEltWidth;
3544 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3546 // For extension loads, it may not be more efficient to truncate the vector
3547 // and then store it. Instead, we extract each element and then store it.
3548 SDValue Chain = ST->getChain();
3549 SDValue BasePtr = ST->getBasePtr();
3550 unsigned Align = ST->getAlignment();
3551 bool isVolatile = ST->isVolatile();
3552 bool isNonTemporal = ST->isNonTemporal();
3553 AAMDNodes AAInfo = ST->getAAInfo();
3554 SDValue ValOp = GetWidenedVector(ST->getValue());
3557 EVT StVT = ST->getMemoryVT();
3558 EVT ValVT = ValOp.getValueType();
3560 // It must be true that we the widen vector type is bigger than where
3561 // we need to store.
3562 assert(StVT.isVector() && ValOp.getValueType().isVector());
3563 assert(StVT.bitsLT(ValOp.getValueType()));
3565 // For truncating stores, we can not play the tricks of chopping legal
3566 // vector types and bit cast it to the right type. Instead, we unroll
3568 EVT StEltVT = StVT.getVectorElementType();
3569 EVT ValEltVT = ValVT.getVectorElementType();
3570 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3571 unsigned NumElts = StVT.getVectorNumElements();
3572 SDValue EOp = DAG.getNode(
3573 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3574 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3575 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3576 ST->getPointerInfo(), StEltVT,
3577 isVolatile, isNonTemporal, Align,
3579 unsigned Offset = Increment;
3580 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3581 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3583 DAG.getConstant(Offset, dl,
3584 BasePtr.getValueType()));
3585 SDValue EOp = DAG.getNode(
3586 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3587 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3588 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3589 ST->getPointerInfo().getWithOffset(Offset),
3590 StEltVT, isVolatile, isNonTemporal,
3591 MinAlign(Align, Offset), AAInfo));
3595 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3596 /// input vector must have the same element type as NVT.
3597 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3598 // Note that InOp might have been widened so it might already have
3599 // the right width or it might need be narrowed.
3600 EVT InVT = InOp.getValueType();
3601 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3602 "input and widen element type must match");
3605 // Check if InOp already has the right width.
3609 unsigned InNumElts = InVT.getVectorNumElements();
3610 unsigned WidenNumElts = NVT.getVectorNumElements();
3611 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3612 unsigned NumConcat = WidenNumElts / InNumElts;
3613 SmallVector<SDValue, 16> Ops(NumConcat);
3614 SDValue UndefVal = DAG.getUNDEF(InVT);
3616 for (unsigned i = 1; i != NumConcat; ++i)
3619 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3622 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3624 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3625 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3627 // Fall back to extract and build.
3628 SmallVector<SDValue, 16> Ops(WidenNumElts);
3629 EVT EltVT = NVT.getVectorElementType();
3630 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3632 for (Idx = 0; Idx < MinNumElts; ++Idx)
3633 Ops[Idx] = DAG.getNode(
3634 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3635 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3637 SDValue UndefVal = DAG.getUNDEF(EltVT);
3638 for ( ; Idx < WidenNumElts; ++Idx)
3639 Ops[Idx] = UndefVal;
3640 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);