1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
49 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
54 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
55 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
57 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
60 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
61 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
62 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
63 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
64 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
65 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
89 case ISD::SIGN_EXTEND:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
116 R = ScalarizeVecRes_BinOp(N);
120 // If R is null, the sub-method took care of registering the result.
122 SetScalarizedVector(SDValue(N, ResNo), R);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
129 LHS.getValueType(), LHS, RHS);
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
133 EVT NewVT = N->getValueType(0).getVectorElementType();
134 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
135 NewVT, N->getOperand(0));
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
139 EVT NewVT = N->getValueType(0).getVectorElementType();
140 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
141 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
142 Op0, DAG.getValueType(NewVT),
143 DAG.getValueType(Op0.getValueType()),
146 cast<CvtRndSatSDNode>(N)->getCvtCode());
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
151 N->getValueType(0).getVectorElementType(),
152 N->getOperand(0), N->getOperand(1));
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
156 EVT NewVT = N->getValueType(0).getVectorElementType();
157 SDValue Op = GetScalarizedVector(N->getOperand(0));
158 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
159 NewVT, Op, N->getOperand(1));
162 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
165 Op.getValueType(), Op, N->getOperand(1));
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
169 // The value to insert may have a wider type than the vector element type,
170 // so be sure to truncate it to the element type if necessary.
171 SDValue Op = N->getOperand(1);
172 EVT EltVT = N->getValueType(0).getVectorElementType();
173 if (Op.getValueType() != EltVT)
174 // FIXME: Can this happen for floating point types?
175 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
179 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
180 assert(N->isUnindexed() && "Indexed vector load?");
182 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
183 N->getExtensionType(),
184 N->getValueType(0).getVectorElementType(),
186 N->getChain(), N->getBasePtr(),
187 DAG.getUNDEF(N->getBasePtr().getValueType()),
189 N->getMemoryVT().getVectorElementType(),
190 N->isVolatile(), N->isNonTemporal(),
191 N->getOriginalAlignment());
193 // Legalized the chain result - switch anything that used the old chain to
195 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
200 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
201 EVT DestVT = N->getValueType(0).getVectorElementType();
202 SDValue Op = GetScalarizedVector(N->getOperand(0));
203 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
207 EVT EltVT = N->getValueType(0).getVectorElementType();
208 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
209 SDValue LHS = GetScalarizedVector(N->getOperand(0));
210 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
211 LHS, DAG.getValueType(ExtVT));
214 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
215 // If the operand is wider than the vector element type then it is implicitly
216 // truncated. Make that explicit here.
217 EVT EltVT = N->getValueType(0).getVectorElementType();
218 SDValue InOp = N->getOperand(0);
219 if (InOp.getValueType() != EltVT)
220 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
224 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
225 SDValue LHS = GetScalarizedVector(N->getOperand(1));
226 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
227 LHS.getValueType(), N->getOperand(0), LHS,
228 GetScalarizedVector(N->getOperand(2)));
231 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
232 SDValue LHS = GetScalarizedVector(N->getOperand(2));
233 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
234 N->getOperand(0), N->getOperand(1),
235 LHS, GetScalarizedVector(N->getOperand(3)),
239 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
240 SDValue LHS = GetScalarizedVector(N->getOperand(0));
241 SDValue RHS = GetScalarizedVector(N->getOperand(1));
242 DebugLoc DL = N->getDebugLoc();
244 // Turn it into a scalar SETCC.
245 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
248 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
249 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
252 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
253 // Figure out if the scalar is the LHS or RHS and return it.
254 SDValue Arg = N->getOperand(2).getOperand(0);
255 if (Arg.getOpcode() == ISD::UNDEF)
256 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
257 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
258 return GetScalarizedVector(N->getOperand(Op));
261 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
262 SDValue LHS = GetScalarizedVector(N->getOperand(0));
263 SDValue RHS = GetScalarizedVector(N->getOperand(1));
264 EVT NVT = N->getValueType(0).getVectorElementType();
265 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
266 DebugLoc DL = N->getDebugLoc();
268 // Turn it into a scalar SETCC.
269 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
271 // VSETCC always returns a sign-extended value, while SETCC may not. The
272 // SETCC result type may not match the vector element type. Correct these.
273 if (NVT.bitsLE(SVT)) {
274 // The SETCC result type is bigger than the vector element type.
275 // Ensure the SETCC result is sign-extended.
276 if (TLI.getBooleanContents() !=
277 TargetLowering::ZeroOrNegativeOneBooleanContent)
278 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
279 DAG.getValueType(MVT::i1));
280 // Truncate to the final type.
281 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
284 // The SETCC result type is smaller than the vector element type.
285 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
286 if (TLI.getBooleanContents() !=
287 TargetLowering::ZeroOrNegativeOneBooleanContent)
288 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
289 // Sign extend to the final type.
290 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
294 //===----------------------------------------------------------------------===//
295 // Operand Vector Scalarization <1 x ty> -> ty.
296 //===----------------------------------------------------------------------===//
298 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
302 SDValue Res = SDValue();
304 if (Res.getNode() == 0) {
305 switch (N->getOpcode()) {
308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
312 llvm_unreachable("Do not know how to scalarize this operator's operand!");
314 Res = ScalarizeVecOp_BITCAST(N);
316 case ISD::CONCAT_VECTORS:
317 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
319 case ISD::EXTRACT_VECTOR_ELT:
320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
328 // If the result is null, the sub-method took care of registering results etc.
329 if (!Res.getNode()) return false;
331 // If the result is N, the sub-method updated N in place. Tell the legalizer
333 if (Res.getNode() == N)
336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
337 "Invalid operand expansion");
339 ReplaceValueWith(SDValue(N, 0), Res);
343 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
344 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
345 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
346 SDValue Elt = GetScalarizedVector(N->getOperand(0));
347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
348 N->getValueType(0), Elt);
351 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
352 /// use a BUILD_VECTOR instead.
353 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
354 SmallVector<SDValue, 8> Ops(N->getNumOperands());
355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
356 Ops[i] = GetScalarizedVector(N->getOperand(i));
357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
358 &Ops[0], Ops.size());
361 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
362 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
364 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
365 SDValue Res = GetScalarizedVector(N->getOperand(0));
366 if (Res.getValueType() != N->getValueType(0))
367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
372 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
373 /// scalarized, it must be <1 x ty>. Just store the element.
374 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
375 assert(N->isUnindexed() && "Indexed store of one-element vector?");
376 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
377 DebugLoc dl = N->getDebugLoc();
379 if (N->isTruncatingStore())
380 return DAG.getTruncStore(N->getChain(), dl,
381 GetScalarizedVector(N->getOperand(1)),
382 N->getBasePtr(), N->getPointerInfo(),
383 N->getMemoryVT().getVectorElementType(),
384 N->isVolatile(), N->isNonTemporal(),
387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
388 N->getBasePtr(), N->getPointerInfo(),
389 N->isVolatile(), N->isNonTemporal(),
390 N->getOriginalAlignment());
394 //===----------------------------------------------------------------------===//
395 // Result Vector Splitting
396 //===----------------------------------------------------------------------===//
398 /// SplitVectorResult - This method is called when the specified result of the
399 /// specified node is found to need vector splitting. At this point, the node
400 /// may also have invalid operands or may have other results that need
401 /// legalization, we just know that (at least) one result needs vector
403 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
404 DEBUG(dbgs() << "Split node result: ";
409 switch (N->getOpcode()) {
412 dbgs() << "SplitVectorResult #" << ResNo << ": ";
416 llvm_unreachable("Do not know how to split the result of this operator!");
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
419 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
420 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
421 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
422 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
423 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
424 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
425 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
426 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
427 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
428 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
429 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
430 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
432 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
436 SplitVecRes_SETCC(N, Lo, Hi);
438 case ISD::VECTOR_SHUFFLE:
439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
442 case ISD::ANY_EXTEND:
443 case ISD::CONVERT_RNDSAT:
456 case ISD::FNEARBYINT:
460 case ISD::FP_TO_SINT:
461 case ISD::FP_TO_UINT:
466 case ISD::SIGN_EXTEND:
467 case ISD::SINT_TO_FP:
469 case ISD::UINT_TO_FP:
470 case ISD::ZERO_EXTEND:
471 SplitVecRes_UnaryOp(N, Lo, Hi);
493 SplitVecRes_BinOp(N, Lo, Hi);
497 // If Lo/Hi is null, the sub-method took care of registering results etc.
499 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
502 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
504 SDValue LHSLo, LHSHi;
505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
506 SDValue RHSLo, RHSHi;
507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
508 DebugLoc dl = N->getDebugLoc();
510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
514 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
516 // We know the result is a vector. The input may be either a vector or a
519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
520 DebugLoc dl = N->getDebugLoc();
522 SDValue InOp = N->getOperand(0);
523 EVT InVT = InOp.getValueType();
525 // Handle some special cases efficiently.
526 switch (getTypeAction(InVT)) {
527 case TargetLowering::TypeLegal:
528 case TargetLowering::TypePromoteInteger:
529 case TargetLowering::TypeSoftenFloat:
530 case TargetLowering::TypeScalarizeVector:
531 case TargetLowering::TypeWidenVector:
533 case TargetLowering::TypeExpandInteger:
534 case TargetLowering::TypeExpandFloat:
535 // A scalar to vector conversion, where the scalar needs expansion.
536 // If the vector is being split in two then we can just convert the
539 GetExpandedOp(InOp, Lo, Hi);
540 if (TLI.isBigEndian())
542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
547 case TargetLowering::TypeSplitVector:
548 // If the input is a vector that needs to be split, convert each split
549 // piece of the input now.
550 GetSplitVector(InOp, Lo, Hi);
551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
556 // In the general case, convert the input to an integer and split it by hand.
557 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
558 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
559 if (TLI.isBigEndian())
560 std::swap(LoIntVT, HiIntVT);
562 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
564 if (TLI.isBigEndian())
566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
567 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
570 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
573 DebugLoc dl = N->getDebugLoc();
574 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
575 unsigned LoNumElts = LoVT.getVectorNumElements();
576 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
579 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
583 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
585 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
586 DebugLoc dl = N->getDebugLoc();
587 unsigned NumSubvectors = N->getNumOperands() / 2;
588 if (NumSubvectors == 1) {
589 Lo = N->getOperand(0);
590 Hi = N->getOperand(1);
595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
597 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
600 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
604 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
606 SDValue Vec = N->getOperand(0);
607 SDValue Idx = N->getOperand(1);
608 DebugLoc dl = N->getDebugLoc();
611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
614 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
616 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
619 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
621 DebugLoc dl = N->getDebugLoc();
622 GetSplitVector(N->getOperand(0), Lo, Hi);
623 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
624 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
627 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
629 SDValue LHSLo, LHSHi;
630 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
631 DebugLoc dl = N->getDebugLoc();
634 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
636 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
637 DAG.getValueType(LoVT));
638 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
639 DAG.getValueType(HiVT));
642 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
644 SDValue Vec = N->getOperand(0);
645 SDValue Elt = N->getOperand(1);
646 SDValue Idx = N->getOperand(2);
647 DebugLoc dl = N->getDebugLoc();
648 GetSplitVector(Vec, Lo, Hi);
650 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
651 unsigned IdxVal = CIdx->getZExtValue();
652 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
653 if (IdxVal < LoNumElts)
654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
655 Lo.getValueType(), Lo, Elt, Idx);
657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
658 DAG.getIntPtrConstant(IdxVal - LoNumElts));
662 // Spill the vector to the stack.
663 EVT VecVT = Vec.getValueType();
664 EVT EltVT = VecVT.getVectorElementType();
665 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
667 MachinePointerInfo(), false, false, 0);
669 // Store the new element. This may be larger than the vector element type,
670 // so use a truncating store.
671 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
672 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
674 TLI.getTargetData()->getPrefTypeAlignment(VecType);
675 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
678 // Load the Lo part from the stack slot.
679 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
682 // Increment the pointer to the other part.
683 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
684 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
685 DAG.getIntPtrConstant(IncrementSize));
687 // Load the Hi part from the stack slot.
688 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
689 false, false, MinAlign(Alignment, IncrementSize));
692 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
695 DebugLoc dl = N->getDebugLoc();
696 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
698 Hi = DAG.getUNDEF(HiVT);
701 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
703 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
705 DebugLoc dl = LD->getDebugLoc();
706 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
708 ISD::LoadExtType ExtType = LD->getExtensionType();
709 SDValue Ch = LD->getChain();
710 SDValue Ptr = LD->getBasePtr();
711 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
712 EVT MemoryVT = LD->getMemoryVT();
713 unsigned Alignment = LD->getOriginalAlignment();
714 bool isVolatile = LD->isVolatile();
715 bool isNonTemporal = LD->isNonTemporal();
717 EVT LoMemVT, HiMemVT;
718 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
721 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
724 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
726 DAG.getIntPtrConstant(IncrementSize));
727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
728 LD->getPointerInfo().getWithOffset(IncrementSize),
729 HiMemVT, isVolatile, isNonTemporal, Alignment);
731 // Build a factor node to remember that this load is independent of the
733 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
736 // Legalized the chain result - switch anything that used the old chain to
738 ReplaceValueWith(SDValue(LD, 1), Ch);
741 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
743 DebugLoc DL = N->getDebugLoc();
744 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
747 EVT InVT = N->getOperand(0).getValueType();
748 SDValue LL, LH, RL, RH;
749 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
750 LoVT.getVectorNumElements());
751 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
752 DAG.getIntPtrConstant(0));
753 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
754 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
756 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
757 DAG.getIntPtrConstant(0));
758 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
759 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
761 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
762 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
765 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
767 // Get the dest types - they may not match the input types, e.g. int_to_fp.
769 DebugLoc dl = N->getDebugLoc();
770 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
773 EVT InVT = N->getOperand(0).getValueType();
774 switch (getTypeAction(InVT)) {
775 default: llvm_unreachable("Unexpected type action!");
776 case TargetLowering::TypeLegal: {
777 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
778 LoVT.getVectorNumElements());
779 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
780 DAG.getIntPtrConstant(0));
781 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
782 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
785 case TargetLowering::TypePromoteInteger: {
786 SDValue InOp = GetPromotedInteger(N->getOperand(0));
787 EVT InNVT = EVT::getVectorVT(*DAG.getContext(),
788 InOp.getValueType().getVectorElementType(),
789 LoVT.getVectorNumElements());
790 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
791 DAG.getIntPtrConstant(0));
792 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
793 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
796 case TargetLowering::TypeSplitVector:
797 GetSplitVector(N->getOperand(0), Lo, Hi);
799 case TargetLowering::TypeWidenVector: {
800 // If the result needs to be split and the input needs to be widened,
801 // the two types must have different lengths. Use the widened result
802 // and extract from it to do the split.
803 SDValue InOp = GetWidenedVector(N->getOperand(0));
804 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
805 LoVT.getVectorNumElements());
806 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
807 DAG.getIntPtrConstant(0));
808 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
809 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
814 if (N->getOpcode() == ISD::FP_ROUND) {
815 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
816 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
817 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
818 SDValue DTyOpLo = DAG.getValueType(LoVT);
819 SDValue DTyOpHi = DAG.getValueType(HiVT);
820 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
821 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
822 SDValue RndOp = N->getOperand(3);
823 SDValue SatOp = N->getOperand(4);
824 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
825 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
827 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
830 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
831 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
835 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
836 SDValue &Lo, SDValue &Hi) {
837 // The low and high parts of the original input give four input vectors.
839 DebugLoc dl = N->getDebugLoc();
840 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
841 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
842 EVT NewVT = Inputs[0].getValueType();
843 unsigned NewElts = NewVT.getVectorNumElements();
845 // If Lo or Hi uses elements from at most two of the four input vectors, then
846 // express it as a vector shuffle of those two inputs. Otherwise extract the
847 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
848 SmallVector<int, 16> Ops;
849 for (unsigned High = 0; High < 2; ++High) {
850 SDValue &Output = High ? Hi : Lo;
852 // Build a shuffle mask for the output, discovering on the fly which
853 // input vectors to use as shuffle operands (recorded in InputUsed).
854 // If building a suitable shuffle vector proves too hard, then bail
855 // out with useBuildVector set.
856 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
857 unsigned FirstMaskIdx = High * NewElts;
858 bool useBuildVector = false;
859 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
860 // The mask element. This indexes into the input.
861 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
863 // The input vector this mask element indexes into.
864 unsigned Input = (unsigned)Idx / NewElts;
866 if (Input >= array_lengthof(Inputs)) {
867 // The mask element does not index into any input vector.
872 // Turn the index into an offset from the start of the input vector.
873 Idx -= Input * NewElts;
875 // Find or create a shuffle vector operand to hold this input.
877 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
878 if (InputUsed[OpNo] == Input) {
879 // This input vector is already an operand.
881 } else if (InputUsed[OpNo] == -1U) {
882 // Create a new operand for this input vector.
883 InputUsed[OpNo] = Input;
888 if (OpNo >= array_lengthof(InputUsed)) {
889 // More than two input vectors used! Give up on trying to create a
890 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
891 useBuildVector = true;
895 // Add the mask index for the new shuffle vector.
896 Ops.push_back(Idx + OpNo * NewElts);
899 if (useBuildVector) {
900 EVT EltVT = NewVT.getVectorElementType();
901 SmallVector<SDValue, 16> SVOps;
903 // Extract the input elements by hand.
904 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
905 // The mask element. This indexes into the input.
906 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
908 // The input vector this mask element indexes into.
909 unsigned Input = (unsigned)Idx / NewElts;
911 if (Input >= array_lengthof(Inputs)) {
912 // The mask element is "undef" or indexes off the end of the input.
913 SVOps.push_back(DAG.getUNDEF(EltVT));
917 // Turn the index into an offset from the start of the input vector.
918 Idx -= Input * NewElts;
920 // Extract the vector element by hand.
921 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
922 Inputs[Input], DAG.getIntPtrConstant(Idx)));
925 // Construct the Lo/Hi output using a BUILD_VECTOR.
926 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
927 } else if (InputUsed[0] == -1U) {
928 // No input vectors were used! The result is undefined.
929 Output = DAG.getUNDEF(NewVT);
931 SDValue Op0 = Inputs[InputUsed[0]];
932 // If only one input was used, use an undefined vector for the other.
933 SDValue Op1 = InputUsed[1] == -1U ?
934 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
935 // At least one input vector was used. Create a new shuffle vector.
936 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
944 //===----------------------------------------------------------------------===//
945 // Operand Vector Splitting
946 //===----------------------------------------------------------------------===//
948 /// SplitVectorOperand - This method is called when the specified operand of the
949 /// specified node is found to need vector splitting. At this point, all of the
950 /// result types of the node are known to be legal, but other operands of the
951 /// node may need legalization as well as the specified one.
952 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
953 DEBUG(dbgs() << "Split node operand: ";
956 SDValue Res = SDValue();
958 if (Res.getNode() == 0) {
959 switch (N->getOpcode()) {
962 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
966 llvm_unreachable("Do not know how to split this operator's operand!");
968 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
969 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
970 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
971 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
972 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
974 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
981 case ISD::FP_TO_SINT:
982 case ISD::FP_TO_UINT:
983 case ISD::SINT_TO_FP:
984 case ISD::UINT_TO_FP:
987 case ISD::SIGN_EXTEND:
988 case ISD::ZERO_EXTEND:
989 case ISD::ANY_EXTEND:
990 Res = SplitVecOp_UnaryOp(N);
995 // If the result is null, the sub-method took care of registering results etc.
996 if (!Res.getNode()) return false;
998 // If the result is N, the sub-method updated N in place. Tell the legalizer
1000 if (Res.getNode() == N)
1003 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1004 "Invalid operand expansion");
1006 ReplaceValueWith(SDValue(N, 0), Res);
1010 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1011 // The result has a legal vector type, but the input needs splitting.
1012 EVT ResVT = N->getValueType(0);
1014 DebugLoc dl = N->getDebugLoc();
1015 GetSplitVector(N->getOperand(0), Lo, Hi);
1016 EVT InVT = Lo.getValueType();
1018 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1019 InVT.getVectorNumElements());
1021 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1022 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1024 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1027 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1028 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1029 // end up being split all the way down to individual components. Convert the
1030 // split pieces into integers and reassemble.
1032 GetSplitVector(N->getOperand(0), Lo, Hi);
1033 Lo = BitConvertToInteger(Lo);
1034 Hi = BitConvertToInteger(Hi);
1036 if (TLI.isBigEndian())
1039 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1040 JoinIntegers(Lo, Hi));
1043 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1044 // We know that the extracted result type is legal.
1045 EVT SubVT = N->getValueType(0);
1046 SDValue Idx = N->getOperand(1);
1047 DebugLoc dl = N->getDebugLoc();
1049 GetSplitVector(N->getOperand(0), Lo, Hi);
1051 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1052 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1054 if (IdxVal < LoElts) {
1055 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1056 "Extracted subvector crosses vector split!");
1057 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1059 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1060 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1064 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1065 SDValue Vec = N->getOperand(0);
1066 SDValue Idx = N->getOperand(1);
1067 EVT VecVT = Vec.getValueType();
1069 if (isa<ConstantSDNode>(Idx)) {
1070 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1071 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1074 GetSplitVector(Vec, Lo, Hi);
1076 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1078 if (IdxVal < LoElts)
1079 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1080 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1081 DAG.getConstant(IdxVal - LoElts,
1082 Idx.getValueType())), 0);
1085 // Store the vector to the stack.
1086 EVT EltVT = VecVT.getVectorElementType();
1087 DebugLoc dl = N->getDebugLoc();
1088 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1089 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1090 MachinePointerInfo(), false, false, 0);
1092 // Load back the required element.
1093 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1094 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1095 MachinePointerInfo(), EltVT, false, false, 0);
1098 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1099 assert(N->isUnindexed() && "Indexed store of vector?");
1100 assert(OpNo == 1 && "Can only split the stored value");
1101 DebugLoc DL = N->getDebugLoc();
1103 bool isTruncating = N->isTruncatingStore();
1104 SDValue Ch = N->getChain();
1105 SDValue Ptr = N->getBasePtr();
1106 EVT MemoryVT = N->getMemoryVT();
1107 unsigned Alignment = N->getOriginalAlignment();
1108 bool isVol = N->isVolatile();
1109 bool isNT = N->isNonTemporal();
1111 GetSplitVector(N->getOperand(1), Lo, Hi);
1113 EVT LoMemVT, HiMemVT;
1114 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1116 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1119 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1120 LoMemVT, isVol, isNT, Alignment);
1122 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1123 isVol, isNT, Alignment);
1125 // Increment the pointer to the other half.
1126 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1127 DAG.getIntPtrConstant(IncrementSize));
1130 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1131 N->getPointerInfo().getWithOffset(IncrementSize),
1132 HiMemVT, isVol, isNT, Alignment);
1134 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1135 N->getPointerInfo().getWithOffset(IncrementSize),
1136 isVol, isNT, Alignment);
1138 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1141 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1142 DebugLoc DL = N->getDebugLoc();
1144 // The input operands all must have the same type, and we know the result the
1145 // result type is valid. Convert this to a buildvector which extracts all the
1147 // TODO: If the input elements are power-two vectors, we could convert this to
1148 // a new CONCAT_VECTORS node with elements that are half-wide.
1149 SmallVector<SDValue, 32> Elts;
1150 EVT EltVT = N->getValueType(0).getVectorElementType();
1151 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1152 SDValue Op = N->getOperand(op);
1153 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1155 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1156 Op, DAG.getIntPtrConstant(i)));
1161 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1162 &Elts[0], Elts.size());
1165 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1166 // The result has a legal vector type, but the input needs splitting.
1167 EVT ResVT = N->getValueType(0);
1169 DebugLoc DL = N->getDebugLoc();
1170 GetSplitVector(N->getOperand(0), Lo, Hi);
1171 EVT InVT = Lo.getValueType();
1173 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1174 InVT.getVectorNumElements());
1176 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1177 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1179 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1184 //===----------------------------------------------------------------------===//
1185 // Result Vector Widening
1186 //===----------------------------------------------------------------------===//
1188 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1189 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1193 // See if the target wants to custom widen this node.
1194 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1197 SDValue Res = SDValue();
1198 switch (N->getOpcode()) {
1201 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1205 llvm_unreachable("Do not know how to widen the result of this operator!");
1207 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1208 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1209 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1210 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1211 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1212 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1213 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1214 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1215 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1216 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1217 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1218 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1219 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1220 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1221 case ISD::VECTOR_SHUFFLE:
1222 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1225 Res = WidenVecRes_VSETCC(N);
1232 case ISD::FCOPYSIGN:
1248 Res = WidenVecRes_Binary(N);
1252 Res = WidenVecRes_POWI(N);
1258 Res = WidenVecRes_Shift(N);
1261 case ISD::ANY_EXTEND:
1262 case ISD::FP_EXTEND:
1264 case ISD::FP_TO_SINT:
1265 case ISD::FP_TO_UINT:
1266 case ISD::SIGN_EXTEND:
1267 case ISD::SINT_TO_FP:
1269 case ISD::UINT_TO_FP:
1270 case ISD::ZERO_EXTEND:
1271 Res = WidenVecRes_Convert(N);
1286 case ISD::FNEARBYINT:
1292 Res = WidenVecRes_Unary(N);
1296 // If Res is null, the sub-method took care of registering the result.
1298 SetWidenedVector(SDValue(N, ResNo), Res);
1301 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1302 // Binary op widening.
1303 unsigned Opcode = N->getOpcode();
1304 DebugLoc dl = N->getDebugLoc();
1305 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1306 EVT WidenEltVT = WidenVT.getVectorElementType();
1308 unsigned NumElts = VT.getVectorNumElements();
1309 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1310 NumElts = NumElts / 2;
1311 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1314 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1315 // Operation doesn't trap so just widen as normal.
1316 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1317 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1318 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1321 // No legal vector version so unroll the vector operation and then widen.
1323 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1325 // Since the operation can trap, apply operation on the original vector.
1327 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1328 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1329 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1331 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1332 unsigned ConcatEnd = 0; // Current ConcatOps index.
1333 int Idx = 0; // Current Idx into input vectors.
1335 // NumElts := greatest legal vector size (at most WidenVT)
1336 // while (orig. vector has unhandled elements) {
1337 // take munches of size NumElts from the beginning and add to ConcatOps
1338 // NumElts := next smaller supported vector size or 1
1340 while (CurNumElts != 0) {
1341 while (CurNumElts >= NumElts) {
1342 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1343 DAG.getIntPtrConstant(Idx));
1344 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1345 DAG.getIntPtrConstant(Idx));
1346 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1348 CurNumElts -= NumElts;
1351 NumElts = NumElts / 2;
1352 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1353 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1356 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1357 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1358 InOp1, DAG.getIntPtrConstant(Idx));
1359 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1360 InOp2, DAG.getIntPtrConstant(Idx));
1361 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1368 // Check to see if we have a single operation with the widen type.
1369 if (ConcatEnd == 1) {
1370 VT = ConcatOps[0].getValueType();
1372 return ConcatOps[0];
1375 // while (Some element of ConcatOps is not of type MaxVT) {
1376 // From the end of ConcatOps, collect elements of the same type and put
1377 // them into an op of the next larger supported type
1379 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1380 Idx = ConcatEnd - 1;
1381 VT = ConcatOps[Idx--].getValueType();
1382 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1385 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1389 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1390 } while (!TLI.isTypeLegal(NextVT));
1392 if (!VT.isVector()) {
1393 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1394 SDValue VecOp = DAG.getUNDEF(NextVT);
1395 unsigned NumToInsert = ConcatEnd - Idx - 1;
1396 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1397 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1398 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1400 ConcatOps[Idx+1] = VecOp;
1401 ConcatEnd = Idx + 2;
1403 // Vector type, create a CONCAT_VECTORS of type NextVT
1404 SDValue undefVec = DAG.getUNDEF(VT);
1405 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1406 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1407 unsigned RealVals = ConcatEnd - Idx - 1;
1408 unsigned SubConcatEnd = 0;
1409 unsigned SubConcatIdx = Idx + 1;
1410 while (SubConcatEnd < RealVals)
1411 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1412 while (SubConcatEnd < OpsToConcat)
1413 SubConcatOps[SubConcatEnd++] = undefVec;
1414 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1415 NextVT, &SubConcatOps[0],
1417 ConcatEnd = SubConcatIdx + 1;
1421 // Check to see if we have a single operation with the widen type.
1422 if (ConcatEnd == 1) {
1423 VT = ConcatOps[0].getValueType();
1425 return ConcatOps[0];
1428 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1429 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1430 if (NumOps != ConcatEnd ) {
1431 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1432 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1433 ConcatOps[j] = UndefVal;
1435 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1438 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1439 SDValue InOp = N->getOperand(0);
1440 DebugLoc DL = N->getDebugLoc();
1442 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1443 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1445 EVT InVT = InOp.getValueType();
1446 EVT InEltVT = InVT.getVectorElementType();
1447 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1449 unsigned Opcode = N->getOpcode();
1450 unsigned InVTNumElts = InVT.getVectorNumElements();
1452 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1453 InOp = GetWidenedVector(N->getOperand(0));
1454 InVT = InOp.getValueType();
1455 InVTNumElts = InVT.getVectorNumElements();
1456 if (InVTNumElts == WidenNumElts) {
1457 if (N->getNumOperands() == 1)
1458 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1459 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1463 if (TLI.isTypeLegal(InWidenVT)) {
1464 // Because the result and the input are different vector types, widening
1465 // the result could create a legal type but widening the input might make
1466 // it an illegal type that might lead to repeatedly splitting the input
1467 // and then widening it. To avoid this, we widen the input only if
1468 // it results in a legal type.
1469 if (WidenNumElts % InVTNumElts == 0) {
1470 // Widen the input and call convert on the widened input vector.
1471 unsigned NumConcat = WidenNumElts/InVTNumElts;
1472 SmallVector<SDValue, 16> Ops(NumConcat);
1474 SDValue UndefVal = DAG.getUNDEF(InVT);
1475 for (unsigned i = 1; i != NumConcat; ++i)
1477 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1478 &Ops[0], NumConcat);
1479 if (N->getNumOperands() == 1)
1480 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1481 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1484 if (InVTNumElts % WidenNumElts == 0) {
1485 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1486 InOp, DAG.getIntPtrConstant(0));
1487 // Extract the input and convert the shorten input vector.
1488 if (N->getNumOperands() == 1)
1489 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1490 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1494 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1495 SmallVector<SDValue, 16> Ops(WidenNumElts);
1496 EVT EltVT = WidenVT.getVectorElementType();
1497 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1499 for (i=0; i < MinElts; ++i) {
1500 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1501 DAG.getIntPtrConstant(i));
1502 if (N->getNumOperands() == 1)
1503 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1505 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1508 SDValue UndefVal = DAG.getUNDEF(EltVT);
1509 for (; i < WidenNumElts; ++i)
1512 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1515 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1516 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1517 SDValue InOp = GetWidenedVector(N->getOperand(0));
1518 SDValue ShOp = N->getOperand(1);
1519 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1522 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1523 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1524 SDValue InOp = GetWidenedVector(N->getOperand(0));
1525 SDValue ShOp = N->getOperand(1);
1527 EVT ShVT = ShOp.getValueType();
1528 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1529 ShOp = GetWidenedVector(ShOp);
1530 ShVT = ShOp.getValueType();
1532 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1533 ShVT.getVectorElementType(),
1534 WidenVT.getVectorNumElements());
1535 if (ShVT != ShWidenVT)
1536 ShOp = ModifyToType(ShOp, ShWidenVT);
1538 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1541 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1542 // Unary op widening.
1543 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1544 SDValue InOp = GetWidenedVector(N->getOperand(0));
1545 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1548 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1549 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1550 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1551 cast<VTSDNode>(N->getOperand(1))->getVT()
1552 .getVectorElementType(),
1553 WidenVT.getVectorNumElements());
1554 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1555 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1556 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1559 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1560 SDValue InOp = N->getOperand(0);
1561 EVT InVT = InOp.getValueType();
1562 EVT VT = N->getValueType(0);
1563 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1564 DebugLoc dl = N->getDebugLoc();
1566 switch (getTypeAction(InVT)) {
1568 assert(false && "Unknown type action!");
1570 case TargetLowering::TypeLegal:
1572 case TargetLowering::TypePromoteInteger:
1573 // If the InOp is promoted to the same size, convert it. Otherwise,
1574 // fall out of the switch and widen the promoted input.
1575 InOp = GetPromotedInteger(InOp);
1576 InVT = InOp.getValueType();
1577 if (WidenVT.bitsEq(InVT))
1578 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1580 case TargetLowering::TypeSoftenFloat:
1581 case TargetLowering::TypeExpandInteger:
1582 case TargetLowering::TypeExpandFloat:
1583 case TargetLowering::TypeScalarizeVector:
1584 case TargetLowering::TypeSplitVector:
1586 case TargetLowering::TypeWidenVector:
1587 // If the InOp is widened to the same size, convert it. Otherwise, fall
1588 // out of the switch and widen the widened input.
1589 InOp = GetWidenedVector(InOp);
1590 InVT = InOp.getValueType();
1591 if (WidenVT.bitsEq(InVT))
1592 // The input widens to the same size. Convert to the widen value.
1593 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1597 unsigned WidenSize = WidenVT.getSizeInBits();
1598 unsigned InSize = InVT.getSizeInBits();
1599 // x86mmx is not an acceptable vector element type, so don't try.
1600 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1601 // Determine new input vector type. The new input vector type will use
1602 // the same element type (if its a vector) or use the input type as a
1603 // vector. It is the same size as the type to widen to.
1605 unsigned NewNumElts = WidenSize / InSize;
1606 if (InVT.isVector()) {
1607 EVT InEltVT = InVT.getVectorElementType();
1608 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1609 WidenSize / InEltVT.getSizeInBits());
1611 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1614 if (TLI.isTypeLegal(NewInVT)) {
1615 // Because the result and the input are different vector types, widening
1616 // the result could create a legal type but widening the input might make
1617 // it an illegal type that might lead to repeatedly splitting the input
1618 // and then widening it. To avoid this, we widen the input only if
1619 // it results in a legal type.
1620 SmallVector<SDValue, 16> Ops(NewNumElts);
1621 SDValue UndefVal = DAG.getUNDEF(InVT);
1623 for (unsigned i = 1; i < NewNumElts; ++i)
1627 if (InVT.isVector())
1628 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1629 NewInVT, &Ops[0], NewNumElts);
1631 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1632 NewInVT, &Ops[0], NewNumElts);
1633 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1637 return CreateStackStoreLoad(InOp, WidenVT);
1640 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1641 DebugLoc dl = N->getDebugLoc();
1642 // Build a vector with undefined for the new nodes.
1643 EVT VT = N->getValueType(0);
1644 EVT EltVT = VT.getVectorElementType();
1645 unsigned NumElts = VT.getVectorNumElements();
1647 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1648 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1650 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1651 NewOps.reserve(WidenNumElts);
1652 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1653 NewOps.push_back(DAG.getUNDEF(EltVT));
1655 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1658 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1659 EVT InVT = N->getOperand(0).getValueType();
1660 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1661 DebugLoc dl = N->getDebugLoc();
1662 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1663 unsigned NumInElts = InVT.getVectorNumElements();
1664 unsigned NumOperands = N->getNumOperands();
1666 bool InputWidened = false; // Indicates we need to widen the input.
1667 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1668 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1669 // Add undef vectors to widen to correct length.
1670 unsigned NumConcat = WidenVT.getVectorNumElements() /
1671 InVT.getVectorNumElements();
1672 SDValue UndefVal = DAG.getUNDEF(InVT);
1673 SmallVector<SDValue, 16> Ops(NumConcat);
1674 for (unsigned i=0; i < NumOperands; ++i)
1675 Ops[i] = N->getOperand(i);
1676 for (unsigned i = NumOperands; i != NumConcat; ++i)
1678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1681 InputWidened = true;
1682 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1683 // The inputs and the result are widen to the same value.
1685 for (i=1; i < NumOperands; ++i)
1686 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1689 if (i == NumOperands)
1690 // Everything but the first operand is an UNDEF so just return the
1691 // widened first operand.
1692 return GetWidenedVector(N->getOperand(0));
1694 if (NumOperands == 2) {
1695 // Replace concat of two operands with a shuffle.
1696 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1697 for (unsigned i = 0; i < NumInElts; ++i) {
1699 MaskOps[i + NumInElts] = i + WidenNumElts;
1701 return DAG.getVectorShuffle(WidenVT, dl,
1702 GetWidenedVector(N->getOperand(0)),
1703 GetWidenedVector(N->getOperand(1)),
1709 // Fall back to use extracts and build vector.
1710 EVT EltVT = WidenVT.getVectorElementType();
1711 SmallVector<SDValue, 16> Ops(WidenNumElts);
1713 for (unsigned i=0; i < NumOperands; ++i) {
1714 SDValue InOp = N->getOperand(i);
1716 InOp = GetWidenedVector(InOp);
1717 for (unsigned j=0; j < NumInElts; ++j)
1718 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1719 DAG.getIntPtrConstant(j));
1721 SDValue UndefVal = DAG.getUNDEF(EltVT);
1722 for (; Idx < WidenNumElts; ++Idx)
1723 Ops[Idx] = UndefVal;
1724 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1727 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1728 DebugLoc dl = N->getDebugLoc();
1729 SDValue InOp = N->getOperand(0);
1730 SDValue RndOp = N->getOperand(3);
1731 SDValue SatOp = N->getOperand(4);
1733 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1734 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1736 EVT InVT = InOp.getValueType();
1737 EVT InEltVT = InVT.getVectorElementType();
1738 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1740 SDValue DTyOp = DAG.getValueType(WidenVT);
1741 SDValue STyOp = DAG.getValueType(InWidenVT);
1742 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1744 unsigned InVTNumElts = InVT.getVectorNumElements();
1745 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1746 InOp = GetWidenedVector(InOp);
1747 InVT = InOp.getValueType();
1748 InVTNumElts = InVT.getVectorNumElements();
1749 if (InVTNumElts == WidenNumElts)
1750 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1754 if (TLI.isTypeLegal(InWidenVT)) {
1755 // Because the result and the input are different vector types, widening
1756 // the result could create a legal type but widening the input might make
1757 // it an illegal type that might lead to repeatedly splitting the input
1758 // and then widening it. To avoid this, we widen the input only if
1759 // it results in a legal type.
1760 if (WidenNumElts % InVTNumElts == 0) {
1761 // Widen the input and call convert on the widened input vector.
1762 unsigned NumConcat = WidenNumElts/InVTNumElts;
1763 SmallVector<SDValue, 16> Ops(NumConcat);
1765 SDValue UndefVal = DAG.getUNDEF(InVT);
1766 for (unsigned i = 1; i != NumConcat; ++i)
1769 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1770 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1774 if (InVTNumElts % WidenNumElts == 0) {
1775 // Extract the input and convert the shorten input vector.
1776 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1777 DAG.getIntPtrConstant(0));
1778 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1783 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1784 SmallVector<SDValue, 16> Ops(WidenNumElts);
1785 EVT EltVT = WidenVT.getVectorElementType();
1786 DTyOp = DAG.getValueType(EltVT);
1787 STyOp = DAG.getValueType(InEltVT);
1789 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1791 for (i=0; i < MinElts; ++i) {
1792 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1793 DAG.getIntPtrConstant(i));
1794 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1798 SDValue UndefVal = DAG.getUNDEF(EltVT);
1799 for (; i < WidenNumElts; ++i)
1802 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1805 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1806 EVT VT = N->getValueType(0);
1807 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1808 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1809 SDValue InOp = N->getOperand(0);
1810 SDValue Idx = N->getOperand(1);
1811 DebugLoc dl = N->getDebugLoc();
1813 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1814 InOp = GetWidenedVector(InOp);
1816 EVT InVT = InOp.getValueType();
1818 // Check if we can just return the input vector after widening.
1819 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1820 if (IdxVal == 0 && InVT == WidenVT)
1823 // Check if we can extract from the vector.
1824 unsigned InNumElts = InVT.getVectorNumElements();
1825 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1826 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1828 // We could try widening the input to the right length but for now, extract
1829 // the original elements, fill the rest with undefs and build a vector.
1830 SmallVector<SDValue, 16> Ops(WidenNumElts);
1831 EVT EltVT = VT.getVectorElementType();
1832 unsigned NumElts = VT.getVectorNumElements();
1834 for (i=0; i < NumElts; ++i)
1835 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1836 DAG.getIntPtrConstant(IdxVal+i));
1838 SDValue UndefVal = DAG.getUNDEF(EltVT);
1839 for (; i < WidenNumElts; ++i)
1841 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1844 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1845 SDValue InOp = GetWidenedVector(N->getOperand(0));
1846 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1847 InOp.getValueType(), InOp,
1848 N->getOperand(1), N->getOperand(2));
1851 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1852 LoadSDNode *LD = cast<LoadSDNode>(N);
1853 ISD::LoadExtType ExtType = LD->getExtensionType();
1856 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1857 if (ExtType != ISD::NON_EXTLOAD)
1858 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1860 Result = GenWidenVectorLoads(LdChain, LD);
1862 // If we generate a single load, we can use that for the chain. Otherwise,
1863 // build a factor node to remember the multiple loads are independent and
1866 if (LdChain.size() == 1)
1867 NewChain = LdChain[0];
1869 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1870 &LdChain[0], LdChain.size());
1872 // Modified the chain - switch anything that used the old chain to use
1874 ReplaceValueWith(SDValue(N, 1), NewChain);
1879 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1880 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1881 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1882 WidenVT, N->getOperand(0));
1885 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1886 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1887 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1889 SDValue Cond1 = N->getOperand(0);
1890 EVT CondVT = Cond1.getValueType();
1891 if (CondVT.isVector()) {
1892 EVT CondEltVT = CondVT.getVectorElementType();
1893 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1894 CondEltVT, WidenNumElts);
1895 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
1896 Cond1 = GetWidenedVector(Cond1);
1898 if (Cond1.getValueType() != CondWidenVT)
1899 Cond1 = ModifyToType(Cond1, CondWidenVT);
1902 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1903 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1904 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1905 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1906 WidenVT, Cond1, InOp1, InOp2);
1909 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1910 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1911 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1912 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1913 InOp1.getValueType(), N->getOperand(0),
1914 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1917 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1918 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1919 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1920 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1921 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1922 InOp1, InOp2, N->getOperand(2));
1925 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1926 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1927 return DAG.getUNDEF(WidenVT);
1930 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1931 EVT VT = N->getValueType(0);
1932 DebugLoc dl = N->getDebugLoc();
1934 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1935 unsigned NumElts = VT.getVectorNumElements();
1936 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1938 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1939 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1941 // Adjust mask based on new input vector length.
1942 SmallVector<int, 16> NewMask;
1943 for (unsigned i = 0; i != NumElts; ++i) {
1944 int Idx = N->getMaskElt(i);
1945 if (Idx < (int)NumElts)
1946 NewMask.push_back(Idx);
1948 NewMask.push_back(Idx - NumElts + WidenNumElts);
1950 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1951 NewMask.push_back(-1);
1952 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1955 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1956 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1957 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1959 SDValue InOp1 = N->getOperand(0);
1960 EVT InVT = InOp1.getValueType();
1961 assert(InVT.isVector() && "can not widen non vector type");
1962 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
1963 InVT.getVectorElementType(), WidenNumElts);
1964 InOp1 = GetWidenedVector(InOp1);
1965 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1967 // Assume that the input and output will be widen appropriately. If not,
1968 // we will have to unroll it at some point.
1969 assert(InOp1.getValueType() == WidenInVT &&
1970 InOp2.getValueType() == WidenInVT &&
1971 "Input not widened to expected type!");
1972 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1973 WidenVT, InOp1, InOp2, N->getOperand(2));
1977 //===----------------------------------------------------------------------===//
1978 // Widen Vector Operand
1979 //===----------------------------------------------------------------------===//
1980 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1981 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
1984 SDValue Res = SDValue();
1986 switch (N->getOpcode()) {
1989 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
1993 llvm_unreachable("Do not know how to widen this operator's operand!");
1995 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
1996 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1997 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
1998 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1999 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2001 case ISD::FP_EXTEND:
2002 case ISD::FP_TO_SINT:
2003 case ISD::FP_TO_UINT:
2004 case ISD::SINT_TO_FP:
2005 case ISD::UINT_TO_FP:
2007 case ISD::SIGN_EXTEND:
2008 case ISD::ZERO_EXTEND:
2009 case ISD::ANY_EXTEND:
2010 Res = WidenVecOp_Convert(N);
2014 // If Res is null, the sub-method took care of registering the result.
2015 if (!Res.getNode()) return false;
2017 // If the result is N, the sub-method updated N in place. Tell the legalizer
2019 if (Res.getNode() == N)
2023 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2024 "Invalid operand expansion");
2026 ReplaceValueWith(SDValue(N, 0), Res);
2030 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2031 // Since the result is legal and the input is illegal, it is unlikely
2032 // that we can fix the input to a legal type so unroll the convert
2033 // into some scalar code and create a nasty build vector.
2034 EVT VT = N->getValueType(0);
2035 EVT EltVT = VT.getVectorElementType();
2036 DebugLoc dl = N->getDebugLoc();
2037 unsigned NumElts = VT.getVectorNumElements();
2038 SDValue InOp = N->getOperand(0);
2039 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2040 InOp = GetWidenedVector(InOp);
2041 EVT InVT = InOp.getValueType();
2042 EVT InEltVT = InVT.getVectorElementType();
2044 unsigned Opcode = N->getOpcode();
2045 SmallVector<SDValue, 16> Ops(NumElts);
2046 for (unsigned i=0; i < NumElts; ++i)
2047 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2048 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2049 DAG.getIntPtrConstant(i)));
2051 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2054 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2055 EVT VT = N->getValueType(0);
2056 SDValue InOp = GetWidenedVector(N->getOperand(0));
2057 EVT InWidenVT = InOp.getValueType();
2058 DebugLoc dl = N->getDebugLoc();
2060 // Check if we can convert between two legal vector types and extract.
2061 unsigned InWidenSize = InWidenVT.getSizeInBits();
2062 unsigned Size = VT.getSizeInBits();
2063 // x86mmx is not an acceptable vector element type, so don't try.
2064 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2065 unsigned NewNumElts = InWidenSize / Size;
2066 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2067 if (TLI.isTypeLegal(NewVT)) {
2068 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2069 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2070 DAG.getIntPtrConstant(0));
2074 return CreateStackStoreLoad(InOp, VT);
2077 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2078 // If the input vector is not legal, it is likely that we will not find a
2079 // legal vector of the same size. Replace the concatenate vector with a
2080 // nasty build vector.
2081 EVT VT = N->getValueType(0);
2082 EVT EltVT = VT.getVectorElementType();
2083 DebugLoc dl = N->getDebugLoc();
2084 unsigned NumElts = VT.getVectorNumElements();
2085 SmallVector<SDValue, 16> Ops(NumElts);
2087 EVT InVT = N->getOperand(0).getValueType();
2088 unsigned NumInElts = InVT.getVectorNumElements();
2091 unsigned NumOperands = N->getNumOperands();
2092 for (unsigned i=0; i < NumOperands; ++i) {
2093 SDValue InOp = N->getOperand(i);
2094 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2095 InOp = GetWidenedVector(InOp);
2096 for (unsigned j=0; j < NumInElts; ++j)
2097 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2098 DAG.getIntPtrConstant(j));
2100 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2103 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2104 SDValue InOp = GetWidenedVector(N->getOperand(0));
2105 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2106 N->getValueType(0), InOp, N->getOperand(1));
2109 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2110 SDValue InOp = GetWidenedVector(N->getOperand(0));
2111 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2112 N->getValueType(0), InOp, N->getOperand(1));
2115 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2116 // We have to widen the value but we want only to store the original
2118 StoreSDNode *ST = cast<StoreSDNode>(N);
2120 SmallVector<SDValue, 16> StChain;
2121 if (ST->isTruncatingStore())
2122 GenWidenVectorTruncStores(StChain, ST);
2124 GenWidenVectorStores(StChain, ST);
2126 if (StChain.size() == 1)
2129 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2130 MVT::Other,&StChain[0],StChain.size());
2133 //===----------------------------------------------------------------------===//
2134 // Vector Widening Utilities
2135 //===----------------------------------------------------------------------===//
2137 // Utility function to find the type to chop up a widen vector for load/store
2138 // TLI: Target lowering used to determine legal types.
2139 // Width: Width left need to load/store.
2140 // WidenVT: The widen vector type to load to/store from
2141 // Align: If 0, don't allow use of a wider type
2142 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2144 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2145 unsigned Width, EVT WidenVT,
2146 unsigned Align = 0, unsigned WidenEx = 0) {
2147 EVT WidenEltVT = WidenVT.getVectorElementType();
2148 unsigned WidenWidth = WidenVT.getSizeInBits();
2149 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2150 unsigned AlignInBits = Align*8;
2152 // If we have one element to load/store, return it.
2153 EVT RetVT = WidenEltVT;
2154 if (Width == WidenEltWidth)
2157 // See if there is larger legal integer than the element type to load/store
2159 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2160 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2161 EVT MemVT((MVT::SimpleValueType) VT);
2162 unsigned MemVTWidth = MemVT.getSizeInBits();
2163 if (MemVT.getSizeInBits() <= WidenEltWidth)
2165 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2166 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2167 (MemVTWidth <= Width ||
2168 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2174 // See if there is a larger vector type to load/store that has the same vector
2175 // element type and is evenly divisible with the WidenVT.
2176 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2177 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2178 EVT MemVT = (MVT::SimpleValueType) VT;
2179 unsigned MemVTWidth = MemVT.getSizeInBits();
2180 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2181 (WidenWidth % MemVTWidth) == 0 &&
2182 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2183 (MemVTWidth <= Width ||
2184 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2185 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2193 // Builds a vector type from scalar loads
2194 // VecTy: Resulting Vector type
2195 // LDOps: Load operators to build a vector type
2196 // [Start,End) the list of loads to use.
2197 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2198 SmallVector<SDValue, 16>& LdOps,
2199 unsigned Start, unsigned End) {
2200 DebugLoc dl = LdOps[Start].getDebugLoc();
2201 EVT LdTy = LdOps[Start].getValueType();
2202 unsigned Width = VecTy.getSizeInBits();
2203 unsigned NumElts = Width / LdTy.getSizeInBits();
2204 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2207 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2209 for (unsigned i = Start + 1; i != End; ++i) {
2210 EVT NewLdTy = LdOps[i].getValueType();
2211 if (NewLdTy != LdTy) {
2212 NumElts = Width / NewLdTy.getSizeInBits();
2213 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2214 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2215 // Readjust position and vector position based on new load type
2216 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2219 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2220 DAG.getIntPtrConstant(Idx++));
2222 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2225 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2227 // The strategy assumes that we can efficiently load powers of two widths.
2228 // The routines chops the vector into the largest vector loads with the same
2229 // element type or scalar loads and then recombines it to the widen vector
2231 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2232 unsigned WidenWidth = WidenVT.getSizeInBits();
2233 EVT LdVT = LD->getMemoryVT();
2234 DebugLoc dl = LD->getDebugLoc();
2235 assert(LdVT.isVector() && WidenVT.isVector());
2236 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2239 SDValue Chain = LD->getChain();
2240 SDValue BasePtr = LD->getBasePtr();
2241 unsigned Align = LD->getAlignment();
2242 bool isVolatile = LD->isVolatile();
2243 bool isNonTemporal = LD->isNonTemporal();
2245 int LdWidth = LdVT.getSizeInBits();
2246 int WidthDiff = WidenWidth - LdWidth; // Difference
2247 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2249 // Find the vector type that can load from.
2250 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2251 int NewVTWidth = NewVT.getSizeInBits();
2252 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2253 isVolatile, isNonTemporal, Align);
2254 LdChain.push_back(LdOp.getValue(1));
2256 // Check if we can load the element with one instruction
2257 if (LdWidth <= NewVTWidth) {
2258 if (!NewVT.isVector()) {
2259 unsigned NumElts = WidenWidth / NewVTWidth;
2260 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2261 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2262 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2264 if (NewVT == WidenVT)
2267 assert(WidenWidth % NewVTWidth == 0);
2268 unsigned NumConcat = WidenWidth / NewVTWidth;
2269 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2270 SDValue UndefVal = DAG.getUNDEF(NewVT);
2271 ConcatOps[0] = LdOp;
2272 for (unsigned i = 1; i != NumConcat; ++i)
2273 ConcatOps[i] = UndefVal;
2274 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2278 // Load vector by using multiple loads from largest vector to scalar
2279 SmallVector<SDValue, 16> LdOps;
2280 LdOps.push_back(LdOp);
2282 LdWidth -= NewVTWidth;
2283 unsigned Offset = 0;
2285 while (LdWidth > 0) {
2286 unsigned Increment = NewVTWidth / 8;
2287 Offset += Increment;
2288 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2289 DAG.getIntPtrConstant(Increment));
2291 if (LdWidth < NewVTWidth) {
2292 // Our current type we are using is too large, find a better size
2293 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2294 NewVTWidth = NewVT.getSizeInBits();
2297 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2298 LD->getPointerInfo().getWithOffset(Offset),
2300 isNonTemporal, MinAlign(Align, Increment));
2301 LdChain.push_back(LdOp.getValue(1));
2302 LdOps.push_back(LdOp);
2304 LdWidth -= NewVTWidth;
2307 // Build the vector from the loads operations
2308 unsigned End = LdOps.size();
2309 if (!LdOps[0].getValueType().isVector())
2310 // All the loads are scalar loads.
2311 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2313 // If the load contains vectors, build the vector using concat vector.
2314 // All of the vectors used to loads are power of 2 and the scalars load
2315 // can be combined to make a power of 2 vector.
2316 SmallVector<SDValue, 16> ConcatOps(End);
2319 EVT LdTy = LdOps[i].getValueType();
2320 // First combine the scalar loads to a vector
2321 if (!LdTy.isVector()) {
2322 for (--i; i >= 0; --i) {
2323 LdTy = LdOps[i].getValueType();
2324 if (LdTy.isVector())
2327 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2329 ConcatOps[--Idx] = LdOps[i];
2330 for (--i; i >= 0; --i) {
2331 EVT NewLdTy = LdOps[i].getValueType();
2332 if (NewLdTy != LdTy) {
2333 // Create a larger vector
2334 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2335 &ConcatOps[Idx], End - Idx);
2339 ConcatOps[--Idx] = LdOps[i];
2342 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2343 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2344 &ConcatOps[Idx], End - Idx);
2346 // We need to fill the rest with undefs to build the vector
2347 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2348 SmallVector<SDValue, 16> WidenOps(NumOps);
2349 SDValue UndefVal = DAG.getUNDEF(LdTy);
2352 for (; i != End-Idx; ++i)
2353 WidenOps[i] = ConcatOps[Idx+i];
2354 for (; i != NumOps; ++i)
2355 WidenOps[i] = UndefVal;
2357 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2361 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2363 ISD::LoadExtType ExtType) {
2364 // For extension loads, it may not be more efficient to chop up the vector
2365 // and then extended it. Instead, we unroll the load and build a new vector.
2366 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2367 EVT LdVT = LD->getMemoryVT();
2368 DebugLoc dl = LD->getDebugLoc();
2369 assert(LdVT.isVector() && WidenVT.isVector());
2372 SDValue Chain = LD->getChain();
2373 SDValue BasePtr = LD->getBasePtr();
2374 unsigned Align = LD->getAlignment();
2375 bool isVolatile = LD->isVolatile();
2376 bool isNonTemporal = LD->isNonTemporal();
2378 EVT EltVT = WidenVT.getVectorElementType();
2379 EVT LdEltVT = LdVT.getVectorElementType();
2380 unsigned NumElts = LdVT.getVectorNumElements();
2382 // Load each element and widen
2383 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2384 SmallVector<SDValue, 16> Ops(WidenNumElts);
2385 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2386 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2387 LD->getPointerInfo(),
2388 LdEltVT, isVolatile, isNonTemporal, Align);
2389 LdChain.push_back(Ops[0].getValue(1));
2390 unsigned i = 0, Offset = Increment;
2391 for (i=1; i < NumElts; ++i, Offset += Increment) {
2392 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2393 BasePtr, DAG.getIntPtrConstant(Offset));
2394 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2395 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2396 isVolatile, isNonTemporal, Align);
2397 LdChain.push_back(Ops[i].getValue(1));
2400 // Fill the rest with undefs
2401 SDValue UndefVal = DAG.getUNDEF(EltVT);
2402 for (; i != WidenNumElts; ++i)
2405 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2409 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2411 // The strategy assumes that we can efficiently store powers of two widths.
2412 // The routines chops the vector into the largest vector stores with the same
2413 // element type or scalar stores.
2414 SDValue Chain = ST->getChain();
2415 SDValue BasePtr = ST->getBasePtr();
2416 unsigned Align = ST->getAlignment();
2417 bool isVolatile = ST->isVolatile();
2418 bool isNonTemporal = ST->isNonTemporal();
2419 SDValue ValOp = GetWidenedVector(ST->getValue());
2420 DebugLoc dl = ST->getDebugLoc();
2422 EVT StVT = ST->getMemoryVT();
2423 unsigned StWidth = StVT.getSizeInBits();
2424 EVT ValVT = ValOp.getValueType();
2425 unsigned ValWidth = ValVT.getSizeInBits();
2426 EVT ValEltVT = ValVT.getVectorElementType();
2427 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2428 assert(StVT.getVectorElementType() == ValEltVT);
2430 int Idx = 0; // current index to store
2431 unsigned Offset = 0; // offset from base to store
2432 while (StWidth != 0) {
2433 // Find the largest vector type we can store with
2434 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2435 unsigned NewVTWidth = NewVT.getSizeInBits();
2436 unsigned Increment = NewVTWidth / 8;
2437 if (NewVT.isVector()) {
2438 unsigned NumVTElts = NewVT.getVectorNumElements();
2440 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2441 DAG.getIntPtrConstant(Idx));
2442 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2443 ST->getPointerInfo().getWithOffset(Offset),
2444 isVolatile, isNonTemporal,
2445 MinAlign(Align, Offset)));
2446 StWidth -= NewVTWidth;
2447 Offset += Increment;
2449 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2450 DAG.getIntPtrConstant(Increment));
2451 } while (StWidth != 0 && StWidth >= NewVTWidth);
2453 // Cast the vector to the scalar type we can store
2454 unsigned NumElts = ValWidth / NewVTWidth;
2455 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2456 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2457 // Readjust index position based on new vector type
2458 Idx = Idx * ValEltWidth / NewVTWidth;
2460 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2461 DAG.getIntPtrConstant(Idx++));
2462 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2463 ST->getPointerInfo().getWithOffset(Offset),
2464 isVolatile, isNonTemporal,
2465 MinAlign(Align, Offset)));
2466 StWidth -= NewVTWidth;
2467 Offset += Increment;
2468 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2469 DAG.getIntPtrConstant(Increment));
2470 } while (StWidth != 0 && StWidth >= NewVTWidth);
2471 // Restore index back to be relative to the original widen element type
2472 Idx = Idx * NewVTWidth / ValEltWidth;
2478 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2480 // For extension loads, it may not be more efficient to truncate the vector
2481 // and then store it. Instead, we extract each element and then store it.
2482 SDValue Chain = ST->getChain();
2483 SDValue BasePtr = ST->getBasePtr();
2484 unsigned Align = ST->getAlignment();
2485 bool isVolatile = ST->isVolatile();
2486 bool isNonTemporal = ST->isNonTemporal();
2487 SDValue ValOp = GetWidenedVector(ST->getValue());
2488 DebugLoc dl = ST->getDebugLoc();
2490 EVT StVT = ST->getMemoryVT();
2491 EVT ValVT = ValOp.getValueType();
2493 // It must be true that we the widen vector type is bigger than where
2494 // we need to store.
2495 assert(StVT.isVector() && ValOp.getValueType().isVector());
2496 assert(StVT.bitsLT(ValOp.getValueType()));
2498 // For truncating stores, we can not play the tricks of chopping legal
2499 // vector types and bit cast it to the right type. Instead, we unroll
2501 EVT StEltVT = StVT.getVectorElementType();
2502 EVT ValEltVT = ValVT.getVectorElementType();
2503 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2504 unsigned NumElts = StVT.getVectorNumElements();
2505 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2506 DAG.getIntPtrConstant(0));
2507 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2508 ST->getPointerInfo(), StEltVT,
2509 isVolatile, isNonTemporal, Align));
2510 unsigned Offset = Increment;
2511 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2512 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2513 BasePtr, DAG.getIntPtrConstant(Offset));
2514 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2515 DAG.getIntPtrConstant(0));
2516 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2517 ST->getPointerInfo().getWithOffset(Offset),
2518 StEltVT, isVolatile, isNonTemporal,
2519 MinAlign(Align, Offset)));
2523 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2524 /// input vector must have the same element type as NVT.
2525 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2526 // Note that InOp might have been widened so it might already have
2527 // the right width or it might need be narrowed.
2528 EVT InVT = InOp.getValueType();
2529 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2530 "input and widen element type must match");
2531 DebugLoc dl = InOp.getDebugLoc();
2533 // Check if InOp already has the right width.
2537 unsigned InNumElts = InVT.getVectorNumElements();
2538 unsigned WidenNumElts = NVT.getVectorNumElements();
2539 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2540 unsigned NumConcat = WidenNumElts / InNumElts;
2541 SmallVector<SDValue, 16> Ops(NumConcat);
2542 SDValue UndefVal = DAG.getUNDEF(InVT);
2544 for (unsigned i = 1; i != NumConcat; ++i)
2547 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2550 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2551 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2552 DAG.getIntPtrConstant(0));
2554 // Fall back to extract and build.
2555 SmallVector<SDValue, 16> Ops(WidenNumElts);
2556 EVT EltVT = NVT.getVectorElementType();
2557 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2559 for (Idx = 0; Idx < MinNumElts; ++Idx)
2560 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2561 DAG.getIntPtrConstant(Idx));
2563 SDValue UndefVal = DAG.getUNDEF(EltVT);
2564 for ( ; Idx < WidenNumElts; ++Idx)
2565 Ops[Idx] = UndefVal;
2566 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);