1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/Target/TargetData.h"
27 //===----------------------------------------------------------------------===//
28 // Result Vector Scalarization: <1 x ty> -> ty.
29 //===----------------------------------------------------------------------===//
31 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
32 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
34 SDValue R = SDValue();
36 switch (N->getOpcode()) {
39 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
40 N->dump(&DAG); cerr << "\n";
42 assert(0 && "Do not know how to scalarize the result of this operator!");
45 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
46 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
47 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
48 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
49 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
50 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
51 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
52 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
53 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
54 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
55 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
56 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
57 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
76 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
93 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
97 case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break;
100 // If R is null, the sub-method took care of registering the result.
102 SetScalarizedVector(SDValue(N, ResNo), R);
105 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
106 SDValue LHS = GetScalarizedVector(N->getOperand(0));
107 SDValue RHS = GetScalarizedVector(N->getOperand(1));
108 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
111 SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
112 SDValue LHS = GetScalarizedVector(N->getOperand(0));
113 SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1));
114 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
115 ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
116 else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
117 ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
119 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt);
122 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
123 MVT NewVT = N->getValueType(0).getVectorElementType();
124 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
127 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
128 MVT NewVT = N->getValueType(0).getVectorElementType();
129 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
130 return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
131 DAG.getValueType(Op0.getValueType()),
134 cast<CvtRndSatSDNode>(N)->getCvtCode());
137 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
138 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
139 N->getValueType(0).getVectorElementType(),
140 N->getOperand(0), N->getOperand(1));
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
144 SDValue Op = GetScalarizedVector(N->getOperand(0));
145 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
149 // The value to insert may have a wider type than the vector element type,
150 // so be sure to truncate it to the element type if necessary.
151 SDValue Op = N->getOperand(1);
152 MVT EltVT = N->getValueType(0).getVectorElementType();
153 if (Op.getValueType() != EltVT)
154 // FIXME: Can this happen for floating point types?
155 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
160 assert(N->isUnindexed() && "Indexed vector load?");
162 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
163 N->getValueType(0).getVectorElementType(),
164 N->getChain(), N->getBasePtr(),
165 DAG.getNode(ISD::UNDEF,
166 N->getBasePtr().getValueType()),
167 N->getSrcValue(), N->getSrcValueOffset(),
168 N->getMemoryVT().getVectorElementType(),
169 N->isVolatile(), N->getAlignment());
171 // Legalized the chain result - switch anything that used the old chain to
173 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
178 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
179 MVT DestVT = N->getValueType(0).getVectorElementType();
180 SDValue Op = GetScalarizedVector(N->getOperand(0));
181 return DAG.getNode(N->getOpcode(), DestVT, Op);
184 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
185 return N->getOperand(0);
188 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
189 SDValue LHS = GetScalarizedVector(N->getOperand(1));
190 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
191 GetScalarizedVector(N->getOperand(2)));
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
195 SDValue LHS = GetScalarizedVector(N->getOperand(2));
196 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
197 N->getOperand(0), N->getOperand(1),
198 LHS, GetScalarizedVector(N->getOperand(3)),
202 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
203 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
207 // Figure out if the scalar is the LHS or RHS and return it.
208 SDValue Arg = N->getOperand(2).getOperand(0);
209 if (Arg.getOpcode() == ISD::UNDEF)
210 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
211 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
212 return GetScalarizedVector(N->getOperand(Op));
215 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
216 SDValue LHS = GetScalarizedVector(N->getOperand(0));
217 SDValue RHS = GetScalarizedVector(N->getOperand(1));
218 MVT NVT = N->getValueType(0).getVectorElementType();
219 MVT SVT = TLI.getSetCCResultType(LHS);
221 // Turn it into a scalar SETCC.
222 SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
224 // VSETCC always returns a sign-extended value, while SETCC may not. The
225 // SETCC result type may not match the vector element type. Correct these.
226 if (NVT.bitsLE(SVT)) {
227 // The SETCC result type is bigger than the vector element type.
228 // Ensure the SETCC result is sign-extended.
229 if (TLI.getBooleanContents() !=
230 TargetLowering::ZeroOrNegativeOneBooleanContent)
231 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
232 DAG.getValueType(MVT::i1));
233 // Truncate to the final type.
234 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
236 // The SETCC result type is smaller than the vector element type.
237 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
238 if (TLI.getBooleanContents() !=
239 TargetLowering::ZeroOrNegativeOneBooleanContent)
240 Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
241 // Sign extend to the final type.
242 return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
247 //===----------------------------------------------------------------------===//
248 // Operand Vector Scalarization <1 x ty> -> ty.
249 //===----------------------------------------------------------------------===//
251 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
252 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
254 SDValue Res = SDValue();
256 if (Res.getNode() == 0) {
257 switch (N->getOpcode()) {
260 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
261 N->dump(&DAG); cerr << "\n";
263 assert(0 && "Do not know how to scalarize this operator's operand!");
266 case ISD::BIT_CONVERT:
267 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
269 case ISD::CONCAT_VECTORS:
270 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
272 case ISD::EXTRACT_VECTOR_ELT:
273 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
276 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
280 // If the result is null, the sub-method took care of registering results etc.
281 if (!Res.getNode()) return false;
283 // If the result is N, the sub-method updated N in place. Tell the legalizer
285 if (Res.getNode() == N)
288 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
289 "Invalid operand expansion");
291 ReplaceValueWith(SDValue(N, 0), Res);
295 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
296 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
297 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
298 SDValue Elt = GetScalarizedVector(N->getOperand(0));
299 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
302 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
303 /// use a BUILD_VECTOR instead.
304 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
305 SmallVector<SDValue, 8> Ops(N->getNumOperands());
306 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
307 Ops[i] = GetScalarizedVector(N->getOperand(i));
308 return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
309 &Ops[0], Ops.size());
312 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
313 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
315 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
316 return GetScalarizedVector(N->getOperand(0));
319 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
320 /// scalarized, it must be <1 x ty>. Just store the element.
321 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
322 assert(N->isUnindexed() && "Indexed store of one-element vector?");
323 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
325 if (N->isTruncatingStore())
326 return DAG.getTruncStore(N->getChain(),
327 GetScalarizedVector(N->getOperand(1)),
329 N->getSrcValue(), N->getSrcValueOffset(),
330 N->getMemoryVT().getVectorElementType(),
331 N->isVolatile(), N->getAlignment());
333 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
334 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
335 N->isVolatile(), N->getAlignment());
339 //===----------------------------------------------------------------------===//
340 // Result Vector Splitting
341 //===----------------------------------------------------------------------===//
343 /// SplitVectorResult - This method is called when the specified result of the
344 /// specified node is found to need vector splitting. At this point, the node
345 /// may also have invalid operands or may have other results that need
346 /// legalization, we just know that (at least) one result needs vector
348 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
349 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
352 switch (N->getOpcode()) {
355 cerr << "SplitVectorResult #" << ResNo << ": ";
356 N->dump(&DAG); cerr << "\n";
358 assert(0 && "Do not know how to split the result of this operator!");
361 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
362 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
363 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
364 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
366 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
367 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
368 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
369 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
370 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
371 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
372 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
373 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
374 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
375 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
376 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
390 case ISD::FNEARBYINT:
391 case ISD::FP_TO_SINT:
392 case ISD::FP_TO_UINT:
393 case ISD::SINT_TO_FP:
395 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
415 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
418 // If Lo/Hi is null, the sub-method took care of registering results etc.
420 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
423 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
425 SDValue LHSLo, LHSHi;
426 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
427 SDValue RHSLo, RHSHi;
428 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
430 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
431 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
434 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
436 // We know the result is a vector. The input may be either a vector or a
439 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
441 SDValue InOp = N->getOperand(0);
442 MVT InVT = InOp.getValueType();
444 // Handle some special cases efficiently.
445 switch (getTypeAction(InVT)) {
447 assert(false && "Unknown type action!");
451 case ScalarizeVector:
455 // A scalar to vector conversion, where the scalar needs expansion.
456 // If the vector is being split in two then we can just convert the
459 GetExpandedOp(InOp, Lo, Hi);
460 if (TLI.isBigEndian())
462 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
463 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
468 // If the input is a vector that needs to be split, convert each split
469 // piece of the input now.
470 GetSplitVector(InOp, Lo, Hi);
471 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
472 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
476 // In the general case, convert the input to an integer and split it by hand.
477 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
478 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
479 if (TLI.isBigEndian())
480 std::swap(LoIntVT, HiIntVT);
482 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
484 if (TLI.isBigEndian())
486 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
487 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
490 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
493 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
494 unsigned LoNumElts = LoVT.getVectorNumElements();
495 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
496 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
498 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
499 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
502 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
504 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
505 unsigned NumSubvectors = N->getNumOperands() / 2;
506 if (NumSubvectors == 1) {
507 Lo = N->getOperand(0);
508 Hi = N->getOperand(1);
513 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
515 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
516 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
518 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
519 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
522 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
525 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
527 GetSplitVector(N->getOperand(0), VLo, VHi);
528 SDValue DTyOpLo = DAG.getValueType(LoVT);
529 SDValue DTyOpHi = DAG.getValueType(HiVT);
530 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
531 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
533 SDValue RndOp = N->getOperand(3);
534 SDValue SatOp = N->getOperand(4);
535 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
537 Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
538 Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
541 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
543 SDValue Vec = N->getOperand(0);
544 SDValue Idx = N->getOperand(1);
545 MVT IdxVT = Idx.getValueType();
548 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
549 // The indices are not guaranteed to be a multiple of the new vector
550 // size unless the original vector type was split in two.
551 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
553 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
554 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
555 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
556 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
559 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
561 GetSplitVector(N->getOperand(0), Lo, Hi);
562 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
563 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
566 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
568 SDValue Vec = N->getOperand(0);
569 SDValue Elt = N->getOperand(1);
570 SDValue Idx = N->getOperand(2);
571 GetSplitVector(Vec, Lo, Hi);
573 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
574 unsigned IdxVal = CIdx->getZExtValue();
575 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
576 if (IdxVal < LoNumElts)
577 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
579 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
580 DAG.getIntPtrConstant(IdxVal - LoNumElts));
584 // Spill the vector to the stack.
585 MVT VecVT = Vec.getValueType();
586 MVT EltVT = VecVT.getVectorElementType();
587 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
588 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
590 // Store the new element. This may be larger than the vector element type,
591 // so use a truncating store.
592 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
594 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
595 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
597 // Load the Lo part from the stack slot.
598 Lo = DAG.getLoad(Lo.getValueType(), Store, StackPtr, NULL, 0);
600 // Increment the pointer to the other part.
601 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
602 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
603 DAG.getIntPtrConstant(IncrementSize));
605 // Load the Hi part from the stack slot.
606 Hi = DAG.getLoad(Hi.getValueType(), Store, StackPtr, NULL, 0, false,
607 MinAlign(Alignment, IncrementSize));
610 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
613 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
614 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, LoVT, N->getOperand(0));
615 Hi = DAG.getNode(ISD::UNDEF, HiVT);
618 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
620 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
622 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
624 ISD::LoadExtType ExtType = LD->getExtensionType();
625 SDValue Ch = LD->getChain();
626 SDValue Ptr = LD->getBasePtr();
627 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
628 const Value *SV = LD->getSrcValue();
629 int SVOffset = LD->getSrcValueOffset();
630 MVT MemoryVT = LD->getMemoryVT();
631 unsigned Alignment = LD->getAlignment();
632 bool isVolatile = LD->isVolatile();
634 MVT LoMemVT, HiMemVT;
635 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
637 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
638 SV, SVOffset, LoMemVT, isVolatile, Alignment);
640 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
641 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
642 DAG.getIntPtrConstant(IncrementSize));
643 SVOffset += IncrementSize;
644 Alignment = MinAlign(Alignment, IncrementSize);
645 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
646 SV, SVOffset, HiMemVT, isVolatile, Alignment);
648 // Build a factor node to remember that this load is independent of the
650 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
653 // Legalized the chain result - switch anything that used the old chain to
655 ReplaceValueWith(SDValue(LD, 1), Ch);
658 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
660 // Get the dest types - they may not match the input types, e.g. int_to_fp.
662 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
665 MVT InVT = N->getOperand(0).getValueType();
666 switch (getTypeAction(InVT)) {
667 default: assert(0 && "Unexpected type action!");
669 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
670 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
671 LoVT.getVectorNumElements());
672 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
673 DAG.getIntPtrConstant(0));
674 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
675 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
679 GetSplitVector(N->getOperand(0), Lo, Hi);
683 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
684 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
687 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
689 // The low and high parts of the original input give four input vectors.
691 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
692 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
693 MVT NewVT = Inputs[0].getValueType();
694 unsigned NewElts = NewVT.getVectorNumElements();
695 assert(NewVT == Inputs[1].getValueType() &&
696 "Non power-of-two vectors not supported!");
698 // If Lo or Hi uses elements from at most two of the four input vectors, then
699 // express it as a vector shuffle of those two inputs. Otherwise extract the
700 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
701 SDValue Mask = N->getOperand(2);
702 MVT IdxVT = Mask.getValueType().getVectorElementType();
703 SmallVector<SDValue, 16> Ops;
704 Ops.reserve(NewElts);
705 for (unsigned High = 0; High < 2; ++High) {
706 SDValue &Output = High ? Hi : Lo;
708 // Build a shuffle mask for the output, discovering on the fly which
709 // input vectors to use as shuffle operands (recorded in InputUsed).
710 // If building a suitable shuffle vector proves too hard, then bail
711 // out with useBuildVector set.
712 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
713 unsigned FirstMaskIdx = High * NewElts;
714 bool useBuildVector = false;
715 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
716 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
718 // The mask element. This indexes into the input.
719 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
720 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
722 // The input vector this mask element indexes into.
723 unsigned Input = Idx / NewElts;
725 if (Input >= array_lengthof(Inputs)) {
726 // The mask element does not index into any input vector.
727 Ops.push_back(DAG.getNode(ISD::UNDEF, IdxVT));
731 // Turn the index into an offset from the start of the input vector.
732 Idx -= Input * NewElts;
734 // Find or create a shuffle vector operand to hold this input.
736 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
737 if (InputUsed[OpNo] == Input) {
738 // This input vector is already an operand.
740 } else if (InputUsed[OpNo] == -1U) {
741 // Create a new operand for this input vector.
742 InputUsed[OpNo] = Input;
747 if (OpNo >= array_lengthof(InputUsed)) {
748 // More than two input vectors used! Give up on trying to create a
749 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
750 useBuildVector = true;
754 // Add the mask index for the new shuffle vector.
755 Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
758 if (useBuildVector) {
759 MVT EltVT = NewVT.getVectorElementType();
762 // Extract the input elements by hand.
763 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
764 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
766 // The mask element. This indexes into the input.
767 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
768 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
770 // The input vector this mask element indexes into.
771 unsigned Input = Idx / NewElts;
773 if (Input >= array_lengthof(Inputs)) {
774 // The mask element is "undef" or indexes off the end of the input.
775 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
779 // Turn the index into an offset from the start of the input vector.
780 Idx -= Input * NewElts;
782 // Extract the vector element by hand.
783 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT,
784 Inputs[Input], DAG.getIntPtrConstant(Idx)));
787 // Construct the Lo/Hi output using a BUILD_VECTOR.
788 Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &Ops[0], Ops.size());
789 } else if (InputUsed[0] == -1U) {
790 // No input vectors were used! The result is undefined.
791 Output = DAG.getNode(ISD::UNDEF, NewVT);
793 // At least one input vector was used. Create a new shuffle vector.
794 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
795 MVT::getVectorVT(IdxVT, Ops.size()),
796 &Ops[0], Ops.size());
797 SDValue Op0 = Inputs[InputUsed[0]];
798 // If only one input was used, use an undefined vector for the other.
799 SDValue Op1 = InputUsed[1] == -1U ?
800 DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]];
801 Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask);
808 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
811 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
813 SDValue LL, LH, RL, RH;
814 GetSplitVector(N->getOperand(0), LL, LH);
815 GetSplitVector(N->getOperand(1), RL, RH);
817 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
818 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
822 //===----------------------------------------------------------------------===//
823 // Operand Vector Splitting
824 //===----------------------------------------------------------------------===//
826 /// SplitVectorOperand - This method is called when the specified operand of the
827 /// specified node is found to need vector splitting. At this point, all of the
828 /// result types of the node are known to be legal, but other operands of the
829 /// node may need legalization as well as the specified one.
830 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
831 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
832 SDValue Res = SDValue();
834 if (Res.getNode() == 0) {
835 switch (N->getOpcode()) {
838 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
839 N->dump(&DAG); cerr << "\n";
841 assert(0 && "Do not know how to split this operator's operand!");
844 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
845 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
846 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
847 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
849 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
854 case ISD::FP_TO_SINT:
855 case ISD::FP_TO_UINT:
856 case ISD::SINT_TO_FP:
858 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
862 // If the result is null, the sub-method took care of registering results etc.
863 if (!Res.getNode()) return false;
865 // If the result is N, the sub-method updated N in place. Tell the legalizer
867 if (Res.getNode() == N)
870 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
871 "Invalid operand expansion");
873 ReplaceValueWith(SDValue(N, 0), Res);
877 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
878 // The result has a legal vector type, but the input needs splitting.
879 MVT ResVT = N->getValueType(0);
881 GetSplitVector(N->getOperand(0), Lo, Hi);
882 assert(Lo.getValueType() == Hi.getValueType() &&
883 "Returns legal non-power-of-two vector type?");
884 MVT InVT = Lo.getValueType();
886 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
887 InVT.getVectorNumElements());
889 Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
890 Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
892 return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
895 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
896 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
897 // end up being split all the way down to individual components. Convert the
898 // split pieces into integers and reassemble.
900 GetSplitVector(N->getOperand(0), Lo, Hi);
901 Lo = BitConvertToInteger(Lo);
902 Hi = BitConvertToInteger(Hi);
904 if (TLI.isBigEndian())
907 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
908 JoinIntegers(Lo, Hi));
911 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
912 // We know that the extracted result type is legal. For now, assume the index
914 MVT SubVT = N->getValueType(0);
915 SDValue Idx = N->getOperand(1);
917 GetSplitVector(N->getOperand(0), Lo, Hi);
919 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
920 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
922 if (IdxVal < LoElts) {
923 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
924 "Extracted subvector crosses vector split!");
925 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
927 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
928 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
932 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
933 SDValue Vec = N->getOperand(0);
934 SDValue Idx = N->getOperand(1);
935 MVT VecVT = Vec.getValueType();
937 if (isa<ConstantSDNode>(Idx)) {
938 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
939 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
942 GetSplitVector(Vec, Lo, Hi);
944 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
947 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
949 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
950 DAG.getConstant(IdxVal - LoElts,
951 Idx.getValueType()));
954 // Store the vector to the stack.
955 MVT EltVT = VecVT.getVectorElementType();
956 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
957 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
959 // Load back the required element.
960 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
961 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
964 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
965 assert(N->isUnindexed() && "Indexed store of vector?");
966 assert(OpNo == 1 && "Can only split the stored value");
968 bool isTruncating = N->isTruncatingStore();
969 SDValue Ch = N->getChain();
970 SDValue Ptr = N->getBasePtr();
971 int SVOffset = N->getSrcValueOffset();
972 MVT MemoryVT = N->getMemoryVT();
973 unsigned Alignment = N->getAlignment();
974 bool isVol = N->isVolatile();
976 GetSplitVector(N->getOperand(1), Lo, Hi);
978 MVT LoMemVT, HiMemVT;
979 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
981 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
984 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
985 LoMemVT, isVol, Alignment);
987 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
990 // Increment the pointer to the other half.
991 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
992 DAG.getIntPtrConstant(IncrementSize));
995 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
996 N->getSrcValue(), SVOffset+IncrementSize,
998 isVol, MinAlign(Alignment, IncrementSize));
1000 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1001 isVol, MinAlign(Alignment, IncrementSize));
1003 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1006 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
1007 assert(OpNo == 2 && "Shuffle source type differs from result type?");
1008 SDValue Mask = N->getOperand(2);
1009 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
1010 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
1011 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
1013 // Look for a legal vector type to place the mask values in.
1014 // Note that there may not be *any* legal vector-of-integer
1015 // type for which the element type is legal!
1016 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
1017 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
1018 // Integer values types are consecutively numbered. Exploit this.
1019 EltVT = MVT::SimpleValueType(EltVT + 1)) {
1021 // Is the element type big enough to hold the values?
1022 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
1026 // Is the vector type legal?
1027 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
1028 if (!isTypeLegal(VecVT))
1032 // If the element type is not legal, find a larger legal type to use for
1033 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
1034 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
1035 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
1036 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
1037 // Integer values types are consecutively numbered. Exploit this.
1038 OpVT = MVT::SimpleValueType(OpVT + 1)) {
1039 if (!isTypeLegal(OpVT))
1042 // Success! Rebuild the vector using the legal types.
1043 SmallVector<SDValue, 16> Ops(MaskLength);
1044 for (unsigned i = 0; i < MaskLength; ++i) {
1045 SDValue Arg = Mask.getOperand(i);
1046 if (Arg.getOpcode() == ISD::UNDEF) {
1047 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
1049 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1050 Ops[i] = DAG.getConstant(Idx, OpVT);
1053 return DAG.UpdateNodeOperands(SDValue(N,0),
1054 N->getOperand(0), N->getOperand(1),
1055 DAG.getNode(ISD::BUILD_VECTOR,
1056 VecVT, &Ops[0], Ops.size()));
1059 // Continuing is pointless - failure is certain.
1062 assert(false && "Failed to find an appropriate mask type!");
1063 return SDValue(N, 0);
1067 //===----------------------------------------------------------------------===//
1068 // Result Vector Widening
1069 //===----------------------------------------------------------------------===//
1071 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1072 DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG);
1074 SDValue Res = SDValue();
1076 switch (N->getOpcode()) {
1079 cerr << "WidenVectorResult #" << ResNo << ": ";
1080 N->dump(&DAG); cerr << "\n";
1082 assert(0 && "Do not know how to widen the result of this operator!");
1085 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1086 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1087 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1088 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1089 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1090 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1091 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1092 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1093 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1094 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1095 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1096 case ISD::VECTOR_SHUFFLE: Res = WidenVecRes_VECTOR_SHUFFLE(N); break;
1097 case ISD::VSETCC: Res = WidenVecRes_VSETCC(N); break;
1103 case ISD::FCOPYSIGN:
1119 case ISD::XOR: Res = WidenVecRes_Binary(N); break;
1123 case ISD::SRL: Res = WidenVecRes_Shift(N); break;
1125 case ISD::ANY_EXTEND:
1127 case ISD::FP_TO_SINT:
1128 case ISD::FP_TO_UINT:
1129 case ISD::SIGN_EXTEND:
1130 case ISD::SINT_TO_FP:
1132 case ISD::ZERO_EXTEND:
1133 case ISD::UINT_TO_FP: Res = WidenVecRes_Convert(N); break;
1142 case ISD::FSQRT: Res = WidenVecRes_Unary(N); break;
1145 // If Res is null, the sub-method took care of registering the result.
1147 SetWidenedVector(SDValue(N, ResNo), Res);
1150 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1151 // Binary op widening.
1152 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1153 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1154 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1155 return DAG.getNode(N->getOpcode(), WidenVT, InOp1, InOp2);
1158 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1159 SDValue InOp = N->getOperand(0);
1161 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1162 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1164 MVT InVT = InOp.getValueType();
1165 MVT InEltVT = InVT.getVectorElementType();
1166 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1168 unsigned Opcode = N->getOpcode();
1169 unsigned InVTNumElts = InVT.getVectorNumElements();
1171 if (getTypeAction(InVT) == WidenVector) {
1172 InOp = GetWidenedVector(N->getOperand(0));
1173 InVT = InOp.getValueType();
1174 InVTNumElts = InVT.getVectorNumElements();
1175 if (InVTNumElts == WidenNumElts)
1176 return DAG.getNode(Opcode, WidenVT, InOp);
1179 if (TLI.isTypeLegal(InWidenVT)) {
1180 // Because the result and the input are different vector types, widening
1181 // the result could create a legal type but widening the input might make
1182 // it an illegal type that might lead to repeatedly splitting the input
1183 // and then widening it. To avoid this, we widen the input only if
1184 // it results in a legal type.
1185 if (WidenNumElts % InVTNumElts == 0) {
1186 // Widen the input and call convert on the widened input vector.
1187 unsigned NumConcat = WidenNumElts/InVTNumElts;
1188 SmallVector<SDValue, 16> Ops(NumConcat);
1190 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
1191 for (unsigned i = 1; i != NumConcat; ++i)
1193 return DAG.getNode(Opcode, WidenVT,
1194 DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT,
1195 &Ops[0], NumConcat));
1198 if (InVTNumElts % WidenNumElts == 0) {
1199 // Extract the input and convert the shorten input vector.
1200 return DAG.getNode(Opcode, WidenVT,
1201 DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp,
1202 DAG.getIntPtrConstant(0)));
1206 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1207 SmallVector<SDValue, 16> Ops(WidenNumElts);
1208 MVT EltVT = WidenVT.getVectorElementType();
1209 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1211 for (i=0; i < MinElts; ++i)
1212 Ops[i] = DAG.getNode(Opcode, EltVT,
1213 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp,
1214 DAG.getIntPtrConstant(i)));
1216 SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
1217 for (; i < WidenNumElts; ++i)
1220 return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
1223 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1224 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1225 SDValue InOp = GetWidenedVector(N->getOperand(0));
1226 SDValue ShOp = N->getOperand(1);
1228 MVT ShVT = ShOp.getValueType();
1229 if (getTypeAction(ShVT) == WidenVector) {
1230 ShOp = GetWidenedVector(ShOp);
1231 ShVT = ShOp.getValueType();
1233 MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
1234 WidenVT.getVectorNumElements());
1235 if (ShVT != ShWidenVT)
1236 ShOp = ModifyToType(ShOp, ShWidenVT);
1238 return DAG.getNode(N->getOpcode(), WidenVT, InOp, ShOp);
1241 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1242 // Unary op widening.
1243 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1244 SDValue InOp = GetWidenedVector(N->getOperand(0));
1245 return DAG.getNode(N->getOpcode(), WidenVT, InOp);
1248 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1249 SDValue InOp = N->getOperand(0);
1250 MVT InVT = InOp.getValueType();
1251 MVT VT = N->getValueType(0);
1252 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1254 switch (getTypeAction(InVT)) {
1256 assert(false && "Unknown type action!");
1260 case PromoteInteger:
1261 // If the InOp is promoted to the same size, convert it. Otherwise,
1262 // fall out of the switch and widen the promoted input.
1263 InOp = GetPromotedInteger(InOp);
1264 InVT = InOp.getValueType();
1265 if (WidenVT.bitsEq(InVT))
1266 return DAG.getNode(ISD::BIT_CONVERT, WidenVT, InOp);
1271 case ScalarizeVector:
1275 // If the InOp is widened to the same size, convert it. Otherwise, fall
1276 // out of the switch and widen the widened input.
1277 InOp = GetWidenedVector(InOp);
1278 InVT = InOp.getValueType();
1279 if (WidenVT.bitsEq(InVT))
1280 // The input widens to the same size. Convert to the widen value.
1281 return DAG.getNode(ISD::BIT_CONVERT, WidenVT, InOp);
1285 unsigned WidenSize = WidenVT.getSizeInBits();
1286 unsigned InSize = InVT.getSizeInBits();
1287 if (WidenSize % InSize == 0) {
1288 // Determine new input vector type. The new input vector type will use
1289 // the same element type (if its a vector) or use the input type as a
1290 // vector. It is the same size as the type to widen to.
1292 unsigned NewNumElts = WidenSize / InSize;
1293 if (InVT.isVector()) {
1294 MVT InEltVT = InVT.getVectorElementType();
1295 NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
1297 NewInVT = MVT::getVectorVT(InVT, NewNumElts);
1300 if (TLI.isTypeLegal(NewInVT)) {
1301 // Because the result and the input are different vector types, widening
1302 // the result could create a legal type but widening the input might make
1303 // it an illegal type that might lead to repeatedly splitting the input
1304 // and then widening it. To avoid this, we widen the input only if
1305 // it results in a legal type.
1306 SmallVector<SDValue, 16> Ops(NewNumElts);
1307 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
1309 for (unsigned i = 1; i < NewNumElts; ++i)
1313 if (InVT.isVector())
1314 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, NewInVT, &Ops[0], NewNumElts);
1316 NewVec = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
1317 return DAG.getNode(ISD::BIT_CONVERT, WidenVT, NewVec);
1321 // This should occur rarely. Lower the bit-convert to a store/load
1322 // from the stack. Create the stack frame object. Make sure it is aligned
1323 // for both the source and destination types.
1324 SDValue FIPtr = DAG.CreateStackTemporary(InVT, WidenVT);
1326 // Emit a store to the stack slot.
1327 SDValue Store = DAG.getStore(DAG.getEntryNode(), InOp, FIPtr, NULL, 0);
1329 // Result is a load from the stack slot.
1330 return DAG.getLoad(WidenVT, Store, FIPtr, NULL, 0);
1333 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1334 // Build a vector with undefined for the new nodes.
1335 MVT VT = N->getValueType(0);
1336 MVT EltVT = VT.getVectorElementType();
1337 unsigned NumElts = VT.getVectorNumElements();
1339 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1340 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1342 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1343 NewOps.reserve(WidenNumElts);
1344 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1345 NewOps.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1347 return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
1350 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1351 MVT InVT = N->getOperand(0).getValueType();
1352 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1353 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1354 unsigned NumOperands = N->getNumOperands();
1356 bool InputWidened = false; // Indicates we need to widen the input.
1357 if (getTypeAction(InVT) != WidenVector) {
1358 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1359 // Add undef vectors to widen to correct length.
1360 unsigned NumConcat = WidenVT.getVectorNumElements() /
1361 InVT.getVectorNumElements();
1362 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
1363 SmallVector<SDValue, 16> Ops(NumConcat);
1364 for (unsigned i=0; i < NumOperands; ++i)
1365 Ops[i] = N->getOperand(i);
1366 for (unsigned i = NumOperands; i != NumConcat; ++i)
1368 return DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, &Ops[0], NumConcat);
1371 InputWidened = true;
1372 if (WidenVT == TLI.getTypeToTransformTo(InVT)) {
1373 // The inputs and the result are widen to the same value.
1375 for (i=1; i < NumOperands; ++i)
1376 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1379 if (i > NumOperands)
1380 // Everything but the first operand is an UNDEF so just return the
1381 // widened first operand.
1382 return GetWidenedVector(N->getOperand(0));
1384 if (NumOperands == 2) {
1385 // Replace concat of two operands with a shuffle.
1386 MVT PtrVT = TLI.getPointerTy();
1387 SmallVector<SDValue, 16> MaskOps(WidenNumElts);
1388 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1389 MaskOps[i] = DAG.getConstant(i, PtrVT);
1390 MaskOps[i+WidenNumElts/2] = DAG.getConstant(i+WidenNumElts, PtrVT);
1392 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR,
1393 MVT::getVectorVT(PtrVT, WidenNumElts),
1394 &MaskOps[0], WidenNumElts);
1395 return DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT,
1396 GetWidenedVector(N->getOperand(0)),
1397 GetWidenedVector(N->getOperand(1)), Mask);
1402 // Fall back to use extracts and build vector.
1403 MVT EltVT = WidenVT.getVectorElementType();
1404 unsigned NumInElts = InVT.getVectorNumElements();
1405 SmallVector<SDValue, 16> Ops(WidenNumElts);
1407 for (unsigned i=0; i < NumOperands; ++i) {
1408 SDValue InOp = N->getOperand(i);
1410 InOp = GetWidenedVector(InOp);
1411 for (unsigned j=0; j < NumInElts; ++j)
1412 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp,
1413 DAG.getIntPtrConstant(j));
1415 SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
1416 for (; Idx < WidenNumElts; ++Idx)
1417 Ops[Idx] = UndefVal;
1418 return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
1421 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1422 SDValue InOp = N->getOperand(0);
1423 SDValue RndOp = N->getOperand(3);
1424 SDValue SatOp = N->getOperand(4);
1426 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1427 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1429 MVT InVT = InOp.getValueType();
1430 MVT InEltVT = InVT.getVectorElementType();
1431 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1433 SDValue DTyOp = DAG.getValueType(WidenVT);
1434 SDValue STyOp = DAG.getValueType(InWidenVT);
1435 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1437 unsigned InVTNumElts = InVT.getVectorNumElements();
1438 if (getTypeAction(InVT) == WidenVector) {
1439 InOp = GetWidenedVector(InOp);
1440 InVT = InOp.getValueType();
1441 InVTNumElts = InVT.getVectorNumElements();
1442 if (InVTNumElts == WidenNumElts)
1443 return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
1447 if (TLI.isTypeLegal(InWidenVT)) {
1448 // Because the result and the input are different vector types, widening
1449 // the result could create a legal type but widening the input might make
1450 // it an illegal type that might lead to repeatedly splitting the input
1451 // and then widening it. To avoid this, we widen the input only if
1452 // it results in a legal type.
1453 if (WidenNumElts % InVTNumElts == 0) {
1454 // Widen the input and call convert on the widened input vector.
1455 unsigned NumConcat = WidenNumElts/InVTNumElts;
1456 SmallVector<SDValue, 16> Ops(NumConcat);
1458 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
1459 for (unsigned i = 1; i != NumConcat; ++i) {
1462 InOp = DAG.getNode(ISD::CONCAT_VECTORS, InWidenVT, &Ops[0], NumConcat);
1463 return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
1467 if (InVTNumElts % WidenNumElts == 0) {
1468 // Extract the input and convert the shorten input vector.
1469 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InWidenVT, InOp,
1470 DAG.getIntPtrConstant(0));
1471 return DAG.getConvertRndSat(WidenVT, InOp, DTyOp, STyOp, RndOp,
1476 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1477 SmallVector<SDValue, 16> Ops(WidenNumElts);
1478 MVT EltVT = WidenVT.getVectorElementType();
1479 DTyOp = DAG.getValueType(EltVT);
1480 STyOp = DAG.getValueType(InEltVT);
1482 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1484 for (i=0; i < MinElts; ++i) {
1485 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp,
1486 DAG.getIntPtrConstant(i));
1487 Ops[i] = DAG.getConvertRndSat(WidenVT, ExtVal, DTyOp, STyOp, RndOp,
1491 SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
1492 for (; i < WidenNumElts; ++i)
1495 return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
1498 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1499 MVT VT = N->getValueType(0);
1500 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1501 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1502 SDValue InOp = N->getOperand(0);
1503 SDValue Idx = N->getOperand(1);
1505 if (getTypeAction(InOp.getValueType()) == WidenVector)
1506 InOp = GetWidenedVector(InOp);
1508 MVT InVT = InOp.getValueType();
1510 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1512 unsigned IdxVal = CIdx->getZExtValue();
1513 // Check if we can just return the input vector after widening.
1514 if (IdxVal == 0 && InVT == WidenVT)
1517 // Check if we can extract from the vector.
1518 unsigned InNumElts = InVT.getVectorNumElements();
1519 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1520 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, InOp, Idx);
1523 // We could try widening the input to the right length but for now, extract
1524 // the original elements, fill the rest with undefs and build a vector.
1525 SmallVector<SDValue, 16> Ops(WidenNumElts);
1526 MVT EltVT = VT.getVectorElementType();
1527 MVT IdxVT = Idx.getValueType();
1528 unsigned NumElts = VT.getVectorNumElements();
1531 unsigned IdxVal = CIdx->getZExtValue();
1532 for (i=0; i < NumElts; ++i)
1533 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp,
1534 DAG.getConstant(IdxVal+i, IdxVT));
1536 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp, Idx);
1537 for (i=1; i < NumElts; ++i) {
1538 SDValue NewIdx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx,
1539 DAG.getConstant(i, IdxVT));
1540 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp, NewIdx);
1544 SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
1545 for (; i < WidenNumElts; ++i)
1547 return DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], WidenNumElts);
1550 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1551 SDValue InOp = GetWidenedVector(N->getOperand(0));
1552 return DAG.getNode(ISD::INSERT_VECTOR_ELT, InOp.getValueType(), InOp,
1553 N->getOperand(1), N->getOperand(2));
1556 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1557 LoadSDNode *LD = cast<LoadSDNode>(N);
1558 MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1559 MVT LdVT = LD->getMemoryVT();
1560 assert(LdVT.isVector() && WidenVT.isVector());
1563 SDValue Chain = LD->getChain();
1564 SDValue BasePtr = LD->getBasePtr();
1565 int SVOffset = LD->getSrcValueOffset();
1566 unsigned Align = LD->getAlignment();
1567 bool isVolatile = LD->isVolatile();
1568 const Value *SV = LD->getSrcValue();
1569 ISD::LoadExtType ExtType = LD->getExtensionType();
1572 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1573 if (ExtType != ISD::NON_EXTLOAD) {
1574 // For extension loads, we can not play the tricks of chopping legal
1575 // vector types and bit cast it to the right type. Instead, we unroll
1576 // the load and build a vector.
1577 MVT EltVT = WidenVT.getVectorElementType();
1578 MVT LdEltVT = LdVT.getVectorElementType();
1579 unsigned NumElts = LdVT.getVectorNumElements();
1581 // Load each element and widen
1582 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1583 SmallVector<SDValue, 16> Ops(WidenNumElts);
1584 unsigned Increment = LdEltVT.getSizeInBits() / 8;
1585 Ops[0] = DAG.getExtLoad(ExtType, EltVT, Chain, BasePtr, SV, SVOffset,
1586 LdEltVT, isVolatile, Align);
1587 LdChain.push_back(Ops[0].getValue(1));
1588 unsigned i = 0, Offset = Increment;
1589 for (i=1; i < NumElts; ++i, Offset += Increment) {
1590 SDValue NewBasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(),
1591 BasePtr, DAG.getIntPtrConstant(Offset));
1592 Ops[i] = DAG.getExtLoad(ExtType, EltVT, Chain, NewBasePtr, SV,
1593 SVOffset + Offset, LdEltVT, isVolatile, Align);
1594 LdChain.push_back(Ops[i].getValue(1));
1597 // Fill the rest with undefs
1598 SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
1599 for (; i != WidenNumElts; ++i)
1602 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &Ops[0], Ops.size());
1604 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
1605 unsigned int LdWidth = LdVT.getSizeInBits();
1606 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
1607 Align, isVolatile, LdWidth, WidenVT);
1610 // If we generate a single load, we can use that for the chain. Otherwise,
1611 // build a factor node to remember the multiple loads are independent and
1614 if (LdChain.size() == 1)
1615 NewChain = LdChain[0];
1617 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0],
1620 // Modified the chain - switch anything that used the old chain to use
1622 ReplaceValueWith(SDValue(N, 1), Chain);
1627 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1628 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1629 return DAG.getNode(ISD::SCALAR_TO_VECTOR, WidenVT, N->getOperand(0));
1632 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1633 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1634 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1636 SDValue Cond1 = N->getOperand(0);
1637 MVT CondVT = Cond1.getValueType();
1638 if (CondVT.isVector()) {
1639 MVT CondEltVT = CondVT.getVectorElementType();
1640 MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
1641 if (getTypeAction(CondVT) == WidenVector)
1642 Cond1 = GetWidenedVector(Cond1);
1644 if (Cond1.getValueType() != CondWidenVT)
1645 Cond1 = ModifyToType(Cond1, CondWidenVT);
1648 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1649 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1650 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1651 return DAG.getNode(ISD::SELECT, WidenVT, Cond1, InOp1, InOp2);
1654 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1655 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1656 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1657 return DAG.getNode(ISD::SELECT_CC, InOp1.getValueType(), N->getOperand(0),
1658 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1661 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1662 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1663 return DAG.getNode(ISD::UNDEF, WidenVT);
1666 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
1667 MVT VT = N->getValueType(0);
1668 unsigned NumElts = VT.getVectorNumElements();
1670 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1671 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1673 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1674 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1676 // Adjust mask based on new input vector length.
1677 SDValue Mask = N->getOperand(2);
1678 SmallVector<SDValue, 16> MaskOps(WidenNumElts);
1679 MVT IdxVT = Mask.getValueType().getVectorElementType();
1680 for (unsigned i = 0; i < NumElts; ++i) {
1681 SDValue Arg = Mask.getOperand(i);
1682 if (Arg.getOpcode() == ISD::UNDEF)
1685 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1689 MaskOps[i] = DAG.getConstant(Idx - NumElts + WidenNumElts, IdxVT);
1692 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1693 MaskOps[i] = DAG.getNode(ISD::UNDEF, IdxVT);
1694 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
1695 MVT::getVectorVT(IdxVT, WidenNumElts),
1696 &MaskOps[0], WidenNumElts);
1698 return DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, InOp1, InOp2, NewMask);
1701 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1702 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1703 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1705 SDValue InOp1 = N->getOperand(0);
1706 MVT InVT = InOp1.getValueType();
1707 assert(InVT.isVector() && "can not widen non vector type");
1708 MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
1709 InOp1 = GetWidenedVector(InOp1);
1710 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1712 // Assume that the input and output will be widen appropriately. If not,
1713 // we will have to unroll it at some point.
1714 assert(InOp1.getValueType() == WidenInVT &&
1715 InOp2.getValueType() == WidenInVT &&
1716 "Input not widened to expected type!");
1717 return DAG.getNode(ISD::VSETCC, WidenVT, InOp1, InOp2, N->getOperand(2));
1721 //===----------------------------------------------------------------------===//
1722 // Widen Vector Operand
1723 //===----------------------------------------------------------------------===//
1724 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1725 DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG);
1727 SDValue Res = SDValue();
1729 switch (N->getOpcode()) {
1732 cerr << "WidenVectorOperand op #" << ResNo << ": ";
1733 N->dump(&DAG); cerr << "\n";
1735 assert(0 && "Do not know how to widen this operator's operand!");
1738 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1739 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1740 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1743 case ISD::FP_TO_SINT:
1744 case ISD::FP_TO_UINT:
1745 case ISD::SINT_TO_FP:
1747 case ISD::UINT_TO_FP: Res = WidenVecOp_Convert(N); break;
1750 // If Res is null, the sub-method took care of registering the result.
1751 if (!Res.getNode()) return false;
1753 // If the result is N, the sub-method updated N in place. Tell the legalizer
1755 if (Res.getNode() == N)
1759 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1760 "Invalid operand expansion");
1762 ReplaceValueWith(SDValue(N, 0), Res);
1766 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1767 // Since the result is legal and the input is illegal, it is unlikely
1768 // that we can fix the input to a legal type so unroll the convert
1769 // into some scalar code and create a nasty build vector.
1770 MVT VT = N->getValueType(0);
1771 MVT EltVT = VT.getVectorElementType();
1772 unsigned NumElts = VT.getVectorNumElements();
1773 SDValue InOp = N->getOperand(0);
1774 if (getTypeAction(InOp.getValueType()) == WidenVector)
1775 InOp = GetWidenedVector(InOp);
1776 MVT InVT = InOp.getValueType();
1777 MVT InEltVT = InVT.getVectorElementType();
1779 unsigned Opcode = N->getOpcode();
1780 SmallVector<SDValue, 16> Ops(NumElts);
1781 for (unsigned i=0; i < NumElts; ++i)
1782 Ops[i] = DAG.getNode(Opcode, EltVT,
1783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, InEltVT, InOp,
1784 DAG.getIntPtrConstant(i)));
1786 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElts);
1789 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1790 // If the input vector is not legal, it is likely that we will not find a
1791 // legal vector of the same size. Replace the concatenate vector with a
1792 // nasty build vector.
1793 MVT VT = N->getValueType(0);
1794 MVT EltVT = VT.getVectorElementType();
1795 unsigned NumElts = VT.getVectorNumElements();
1796 SmallVector<SDValue, 16> Ops(NumElts);
1798 MVT InVT = N->getOperand(0).getValueType();
1799 unsigned NumInElts = InVT.getVectorNumElements();
1802 unsigned NumOperands = N->getNumOperands();
1803 for (unsigned i=0; i < NumOperands; ++i) {
1804 SDValue InOp = N->getOperand(i);
1805 if (getTypeAction(InOp.getValueType()) == WidenVector)
1806 InOp = GetWidenedVector(InOp);
1807 for (unsigned j=0; j < NumInElts; ++j)
1808 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp,
1809 DAG.getIntPtrConstant(j));
1811 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElts);
1814 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1815 SDValue InOp = GetWidenedVector(N->getOperand(0));
1816 MVT EltVT = InOp.getValueType().getVectorElementType();
1817 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp, N->getOperand(1));
1820 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1821 // We have to widen the value but we want only to store the original
1823 StoreSDNode *ST = cast<StoreSDNode>(N);
1824 SDValue Chain = ST->getChain();
1825 SDValue BasePtr = ST->getBasePtr();
1826 const Value *SV = ST->getSrcValue();
1827 int SVOffset = ST->getSrcValueOffset();
1828 unsigned Align = ST->getAlignment();
1829 bool isVolatile = ST->isVolatile();
1830 SDValue ValOp = GetWidenedVector(ST->getValue());
1832 MVT StVT = ST->getMemoryVT();
1833 MVT ValVT = ValOp.getValueType();
1834 // It must be true that we the widen vector type is bigger than where
1835 // we need to store.
1836 assert(StVT.isVector() && ValOp.getValueType().isVector());
1837 assert(StVT.getSizeInBits() < ValOp.getValueType().getSizeInBits());
1839 SmallVector<SDValue, 16> StChain;
1840 if (ST->isTruncatingStore()) {
1841 // For truncating stores, we can not play the tricks of chopping legal
1842 // vector types and bit cast it to the right type. Instead, we unroll
1844 MVT StEltVT = StVT.getVectorElementType();
1845 MVT ValEltVT = ValVT.getVectorElementType();
1846 unsigned Increment = ValEltVT.getSizeInBits() / 8;
1847 unsigned NumElts = StVT.getVectorNumElements();
1848 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, ValEltVT, ValOp,
1849 DAG.getIntPtrConstant(0));
1850 StChain.push_back(DAG.getTruncStore(Chain, EOp, BasePtr, SV,
1852 isVolatile, Align));
1853 unsigned Offset = Increment;
1854 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
1855 SDValue NewBasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(),
1856 BasePtr, DAG.getIntPtrConstant(Offset));
1857 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, ValEltVT, ValOp,
1858 DAG.getIntPtrConstant(0));
1859 StChain.push_back(DAG.getTruncStore(Chain, EOp, NewBasePtr, SV,
1860 SVOffset + Offset, StEltVT,
1861 isVolatile, MinAlign(Align, Offset)));
1865 assert(StVT.getVectorElementType() == ValVT.getVectorElementType());
1867 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset,
1868 Align, isVolatile, ValOp, StVT.getSizeInBits());
1870 if (StChain.size() == 1)
1873 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
1876 //===----------------------------------------------------------------------===//
1877 // Vector Widening Utilities
1878 //===----------------------------------------------------------------------===//
1881 // Utility function to find a vector type and its associated element
1882 // type from a preferred width and whose vector type must be the same size
1884 // TLI: Target lowering used to determine legal types.
1885 // Width: Preferred width to store.
1886 // VecVT: Vector value type whose size we must match.
1887 // Returns NewVecVT and NewEltVT - the vector type and its associated
1889 static void FindAssocWidenVecType(TargetLowering &TLI, unsigned Width, MVT VecVT,
1890 MVT& NewEltVT, MVT& NewVecVT) {
1891 unsigned EltWidth = Width + 1;
1892 if (TLI.isTypeLegal(VecVT)) {
1893 // We start with the preferred with, making it a power of 2 and find a
1894 // legal vector type of that width. If not, we reduce it by another of 2.
1895 // For incoming type is legal, this process will end as a vector of the
1896 // smallest loadable type should always be legal.
1898 assert(EltWidth > 0);
1899 EltWidth = 1 << Log2_32(EltWidth - 1);
1900 NewEltVT = MVT::getIntegerVT(EltWidth);
1901 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1902 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1903 } while (!TLI.isTypeLegal(NewVecVT) ||
1904 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1906 // The incoming vector type is illegal and is the result of widening
1907 // a vector to a power of 2. In this case, we will use the preferred
1908 // with as long as it is a multiple of the incoming vector length.
1909 // The legalization process will eventually make this into a legal type
1910 // and remove the illegal bit converts (which would turn to stack converts
1911 // if they are allow to exist).
1913 assert(EltWidth > 0);
1914 EltWidth = 1 << Log2_32(EltWidth - 1);
1915 NewEltVT = MVT::getIntegerVT(EltWidth);
1916 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1917 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1918 } while (!TLI.isTypeLegal(NewEltVT) ||
1919 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1923 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
1932 // The strategy assumes that we can efficiently load powers of two widths.
1933 // The routines chops the vector into the largest power of 2 load and
1934 // can be inserted into a legal vector and then cast the result into the
1935 // vector type we want. This avoids unnecessary stack converts.
1937 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
1938 // the load is nonvolatile, we an use a wider load for the value.
1940 // Find the vector type that can load from.
1941 MVT NewEltVT, NewVecVT;
1942 unsigned NewEltVTWidth;
1943 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
1944 NewEltVTWidth = NewEltVT.getSizeInBits();
1946 SDValue LdOp = DAG.getLoad(NewEltVT, Chain, BasePtr, SV, SVOffset, isVolatile,
1948 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, NewVecVT, LdOp);
1949 LdChain.push_back(LdOp.getValue(1));
1951 // Check if we can load the element with one instruction
1952 if (LdWidth == NewEltVTWidth) {
1953 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
1957 LdWidth -= NewEltVTWidth;
1958 unsigned Offset = 0;
1960 while (LdWidth > 0) {
1961 unsigned Increment = NewEltVTWidth / 8;
1962 Offset += Increment;
1963 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
1964 DAG.getIntPtrConstant(Increment));
1966 if (LdWidth < NewEltVTWidth) {
1967 // Our current type we are using is too large, use a smaller size by
1968 // using a smaller power of 2
1969 unsigned oNewEltVTWidth = NewEltVTWidth;
1970 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
1971 NewEltVTWidth = NewEltVT.getSizeInBits();
1972 // Readjust position and vector position based on new load type
1973 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
1974 VecOp = DAG.getNode(ISD::BIT_CONVERT, NewVecVT, VecOp);
1977 SDValue LdOp = DAG.getLoad(NewEltVT, Chain, BasePtr, SV,
1978 SVOffset+Offset, isVolatile,
1979 MinAlign(Alignment, Offset));
1980 LdChain.push_back(LdOp.getValue(1));
1981 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVecVT, VecOp, LdOp,
1982 DAG.getIntPtrConstant(Idx++));
1984 LdWidth -= NewEltVTWidth;
1987 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
1990 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
1999 // Breaks the stores into a series of power of 2 width stores. For any
2000 // width, we convert the vector to the vector of element size that we
2001 // want to store. This avoids requiring a stack convert.
2003 // Find a width of the element type we can store with
2004 MVT WidenVT = ValOp.getValueType();
2005 MVT NewEltVT, NewVecVT;
2007 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2008 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
2010 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, NewVecVT, ValOp);
2011 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, VecOp,
2012 DAG.getIntPtrConstant(0));
2013 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
2014 isVolatile, Alignment);
2015 StChain.push_back(StOp);
2017 // Check if we are done
2018 if (StWidth == NewEltVTWidth) {
2023 StWidth -= NewEltVTWidth;
2024 unsigned Offset = 0;
2026 while (StWidth > 0) {
2027 unsigned Increment = NewEltVTWidth / 8;
2028 Offset += Increment;
2029 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
2030 DAG.getIntPtrConstant(Increment));
2032 if (StWidth < NewEltVTWidth) {
2033 // Our current type we are using is too large, use a smaller size by
2034 // using a smaller power of 2
2035 unsigned oNewEltVTWidth = NewEltVTWidth;
2036 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2037 NewEltVTWidth = NewEltVT.getSizeInBits();
2038 // Readjust position and vector position based on new load type
2039 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2040 VecOp = DAG.getNode(ISD::BIT_CONVERT, NewVecVT, VecOp);
2043 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, VecOp,
2044 DAG.getIntPtrConstant(Idx++));
2045 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
2046 SVOffset + Offset, isVolatile,
2047 MinAlign(Alignment, Offset)));
2048 StWidth -= NewEltVTWidth;
2052 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2053 /// input vector must have the same element type as NVT.
2054 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
2055 // Note that InOp might have been widened so it might already have
2056 // the right width or it might need be narrowed.
2057 MVT InVT = InOp.getValueType();
2058 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2059 "input and widen element type must match");
2061 // Check if InOp already has the right width.
2065 unsigned InNumElts = InVT.getVectorNumElements();
2066 unsigned WidenNumElts = NVT.getVectorNumElements();
2067 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2068 unsigned NumConcat = WidenNumElts / InNumElts;
2069 SmallVector<SDValue, 16> Ops(NumConcat);
2070 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
2072 for (unsigned i = 1; i != NumConcat; ++i)
2075 return DAG.getNode(ISD::CONCAT_VECTORS, NVT, &Ops[0], NumConcat);
2078 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2079 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, NVT, InOp,
2080 DAG.getIntPtrConstant(0));
2082 // Fall back to extract and build.
2083 SmallVector<SDValue, 16> Ops(WidenNumElts);
2084 MVT EltVT = NVT.getVectorElementType();
2085 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2087 for (Idx = 0; Idx < MinNumElts; ++Idx)
2088 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InOp,
2089 DAG.getIntPtrConstant(Idx));
2091 SDValue UndefVal = DAG.getNode(ISD::UNDEF, EltVT);
2092 for ( ; Idx < WidenNumElts; ++Idx)
2093 Ops[Idx] = UndefVal;
2094 return DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], WidenNumElts);