1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDValue R = SDValue();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
46 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
47 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
48 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
49 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
50 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
51 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
52 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
53 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
54 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
55 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
56 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
75 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
92 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
95 // If R is null, the sub-method took care of registering the result.
97 SetScalarizedVector(SDValue(N, ResNo), R);
100 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
101 SDValue LHS = GetScalarizedVector(N->getOperand(0));
102 SDValue RHS = GetScalarizedVector(N->getOperand(1));
103 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
106 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
107 MVT NewVT = N->getValueType(0).getVectorElementType();
108 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
111 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
112 MVT NewVT = N->getValueType(0).getVectorElementType();
113 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
114 return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
115 DAG.getValueType(Op0.getValueType()),
118 cast<CvtRndSatSDNode>(N)->getCvtCode());
121 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
122 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
123 N->getValueType(0).getVectorElementType(),
124 N->getOperand(0), N->getOperand(1));
127 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
128 SDValue Op = GetScalarizedVector(N->getOperand(0));
129 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
133 // The value to insert may have a wider type than the vector element type,
134 // so be sure to truncate it to the element type if necessary.
135 SDValue Op = N->getOperand(1);
136 MVT EltVT = N->getValueType(0).getVectorElementType();
137 if (Op.getValueType() != EltVT)
138 // FIXME: Can this happen for floating point types?
139 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
144 assert(N->isUnindexed() && "Indexed vector load?");
146 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
147 N->getValueType(0).getVectorElementType(),
148 N->getChain(), N->getBasePtr(),
149 DAG.getNode(ISD::UNDEF,
150 N->getBasePtr().getValueType()),
151 N->getSrcValue(), N->getSrcValueOffset(),
152 N->getMemoryVT().getVectorElementType(),
153 N->isVolatile(), N->getAlignment());
155 // Legalized the chain result - switch anything that used the old chain to
157 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
161 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
162 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
163 MVT DestVT = N->getValueType(0).getVectorElementType();
164 SDValue Op = GetScalarizedVector(N->getOperand(0));
165 return DAG.getNode(N->getOpcode(), DestVT, Op);
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
169 return N->getOperand(0);
172 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
173 SDValue LHS = GetScalarizedVector(N->getOperand(1));
174 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
175 GetScalarizedVector(N->getOperand(2)));
178 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
179 SDValue LHS = GetScalarizedVector(N->getOperand(2));
180 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
181 N->getOperand(0), N->getOperand(1),
182 LHS, GetScalarizedVector(N->getOperand(3)),
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
187 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
190 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
191 // Figure out if the scalar is the LHS or RHS and return it.
192 SDValue Arg = N->getOperand(2).getOperand(0);
193 if (Arg.getOpcode() == ISD::UNDEF)
194 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
195 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
196 return GetScalarizedVector(N->getOperand(Op));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
200 SDValue LHS = GetScalarizedVector(N->getOperand(0));
201 SDValue RHS = GetScalarizedVector(N->getOperand(1));
202 MVT NVT = N->getValueType(0).getVectorElementType();
203 MVT SVT = TLI.getSetCCResultType(LHS);
205 // Turn it into a scalar SETCC.
206 SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
208 // VSETCC always returns a sign-extended value, while SETCC may not. The
209 // SETCC result type may not match the vector element type. Correct these.
210 if (NVT.bitsLE(SVT)) {
211 // The SETCC result type is bigger than the vector element type.
212 // Ensure the SETCC result is sign-extended.
213 if (TLI.getBooleanContents() !=
214 TargetLowering::ZeroOrNegativeOneBooleanContent)
215 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
216 DAG.getValueType(MVT::i1));
217 // Truncate to the final type.
218 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
220 // The SETCC result type is smaller than the vector element type.
221 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
222 if (TLI.getBooleanContents() !=
223 TargetLowering::ZeroOrNegativeOneBooleanContent)
224 Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
225 // Sign extend to the final type.
226 return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
231 //===----------------------------------------------------------------------===//
232 // Operand Vector Scalarization <1 x ty> -> ty.
233 //===----------------------------------------------------------------------===//
235 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
236 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
238 SDValue Res = SDValue();
240 if (Res.getNode() == 0) {
241 switch (N->getOpcode()) {
244 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
245 N->dump(&DAG); cerr << "\n";
247 assert(0 && "Do not know how to scalarize this operator's operand!");
250 case ISD::BIT_CONVERT:
251 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
253 case ISD::CONCAT_VECTORS:
254 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
256 case ISD::EXTRACT_VECTOR_ELT:
257 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
260 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
264 // If the result is null, the sub-method took care of registering results etc.
265 if (!Res.getNode()) return false;
267 // If the result is N, the sub-method updated N in place. Check to see if any
268 // operands are new, and if so, mark them.
269 if (Res.getNode() == N) {
270 // Mark N as new and remark N and its operands. This allows us to correctly
271 // revisit N if it needs another step of promotion and allows us to visit
272 // any new operands to N.
277 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
278 "Invalid operand expansion");
280 ReplaceValueWith(SDValue(N, 0), Res);
284 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
285 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
286 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
287 SDValue Elt = GetScalarizedVector(N->getOperand(0));
288 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
291 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
292 /// use a BUILD_VECTOR instead.
293 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
294 SmallVector<SDValue, 8> Ops(N->getNumOperands());
295 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
296 Ops[i] = GetScalarizedVector(N->getOperand(i));
297 return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
298 &Ops[0], Ops.size());
301 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
302 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
304 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
305 return GetScalarizedVector(N->getOperand(0));
308 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
309 /// scalarized, it must be <1 x ty>. Just store the element.
310 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
311 assert(N->isUnindexed() && "Indexed store of one-element vector?");
312 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
314 if (N->isTruncatingStore())
315 return DAG.getTruncStore(N->getChain(),
316 GetScalarizedVector(N->getOperand(1)),
318 N->getSrcValue(), N->getSrcValueOffset(),
319 N->getMemoryVT().getVectorElementType(),
320 N->isVolatile(), N->getAlignment());
322 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
323 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
324 N->isVolatile(), N->getAlignment());
328 //===----------------------------------------------------------------------===//
329 // Result Vector Splitting
330 //===----------------------------------------------------------------------===//
332 /// SplitVectorResult - This method is called when the specified result of the
333 /// specified node is found to need vector splitting. At this point, the node
334 /// may also have invalid operands or may have other results that need
335 /// legalization, we just know that (at least) one result needs vector
337 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
338 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
341 switch (N->getOpcode()) {
344 cerr << "SplitVectorResult #" << ResNo << ": ";
345 N->dump(&DAG); cerr << "\n";
347 assert(0 && "Do not know how to split the result of this operator!");
350 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
351 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
352 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
353 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
355 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
356 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
357 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
358 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
359 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
360 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
361 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
362 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
363 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
364 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
365 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
379 case ISD::FNEARBYINT:
380 case ISD::FP_TO_SINT:
381 case ISD::FP_TO_UINT:
382 case ISD::SINT_TO_FP:
384 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
401 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
404 // If Lo/Hi is null, the sub-method took care of registering results etc.
406 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
409 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
411 SDValue LHSLo, LHSHi;
412 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
413 SDValue RHSLo, RHSHi;
414 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
416 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
417 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
420 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
422 // We know the result is a vector. The input may be either a vector or a
425 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
427 SDValue InOp = N->getOperand(0);
428 MVT InVT = InOp.getValueType();
430 // Handle some special cases efficiently.
431 switch (getTypeAction(InVT)) {
433 assert(false && "Unknown type action!");
437 case ScalarizeVector:
441 // A scalar to vector conversion, where the scalar needs expansion.
442 // If the vector is being split in two then we can just convert the
445 GetExpandedOp(InOp, Lo, Hi);
446 if (TLI.isBigEndian())
448 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
449 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
454 // If the input is a vector that needs to be split, convert each split
455 // piece of the input now.
456 GetSplitVector(InOp, Lo, Hi);
457 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
458 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
462 // In the general case, convert the input to an integer and split it by hand.
463 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
464 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
465 if (TLI.isBigEndian())
466 std::swap(LoIntVT, HiIntVT);
468 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
470 if (TLI.isBigEndian())
472 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
473 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
476 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
479 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
480 unsigned LoNumElts = LoVT.getVectorNumElements();
481 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
482 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
484 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
485 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
488 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
490 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
491 unsigned NumSubvectors = N->getNumOperands() / 2;
492 if (NumSubvectors == 1) {
493 Lo = N->getOperand(0);
494 Hi = N->getOperand(1);
499 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
501 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
502 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
504 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
505 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
508 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
511 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
513 GetSplitVector(N->getOperand(0), VLo, VHi);
514 SDValue DTyOpLo = DAG.getValueType(LoVT);
515 SDValue DTyOpHi = DAG.getValueType(HiVT);
516 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
517 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
519 SDValue RndOp = N->getOperand(3);
520 SDValue SatOp = N->getOperand(4);
521 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
523 Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
524 Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
527 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
529 SDValue Vec = N->getOperand(0);
530 SDValue Idx = N->getOperand(1);
531 MVT IdxVT = Idx.getValueType();
534 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
535 // The indices are not guaranteed to be a multiple of the new vector
536 // size unless the original vector type was split in two.
537 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
539 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
540 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
541 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
542 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
545 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
547 GetSplitVector(N->getOperand(0), Lo, Hi);
548 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
549 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
552 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
554 SDValue Vec = N->getOperand(0);
555 SDValue Elt = N->getOperand(1);
556 SDValue Idx = N->getOperand(2);
557 GetSplitVector(Vec, Lo, Hi);
559 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
560 unsigned IdxVal = CIdx->getZExtValue();
561 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
562 if (IdxVal < LoNumElts)
563 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
565 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
566 DAG.getIntPtrConstant(IdxVal - LoNumElts));
570 // Spill the vector to the stack.
571 MVT VecVT = Vec.getValueType();
572 MVT EltVT = VecVT.getVectorElementType();
573 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
574 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
576 // Store the new element. This may be larger than the vector element type,
577 // so use a truncating store.
578 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
579 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
581 // Reload the vector from the stack.
582 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
585 SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
588 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
591 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
592 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, LoVT, N->getOperand(0));
593 Hi = DAG.getNode(ISD::UNDEF, HiVT);
596 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
598 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
600 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
602 ISD::LoadExtType ExtType = LD->getExtensionType();
603 SDValue Ch = LD->getChain();
604 SDValue Ptr = LD->getBasePtr();
605 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
606 const Value *SV = LD->getSrcValue();
607 int SVOffset = LD->getSrcValueOffset();
608 MVT MemoryVT = LD->getMemoryVT();
609 unsigned Alignment = LD->getAlignment();
610 bool isVolatile = LD->isVolatile();
612 MVT LoMemVT, HiMemVT;
613 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
615 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
616 SV, SVOffset, LoMemVT, isVolatile, Alignment);
618 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
619 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
620 DAG.getIntPtrConstant(IncrementSize));
621 SVOffset += IncrementSize;
622 Alignment = MinAlign(Alignment, IncrementSize);
623 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
624 SV, SVOffset, HiMemVT, isVolatile, Alignment);
626 // Build a factor node to remember that this load is independent of the
628 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
631 // Legalized the chain result - switch anything that used the old chain to
633 ReplaceValueWith(SDValue(LD, 1), Ch);
636 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
638 // Get the dest types - they may not match the input types, e.g. int_to_fp.
640 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
643 MVT InVT = N->getOperand(0).getValueType();
644 switch (getTypeAction(InVT)) {
645 default: assert(0 && "Unexpected type action!");
647 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
648 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
649 LoVT.getVectorNumElements());
650 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
651 DAG.getIntPtrConstant(0));
652 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
653 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
657 GetSplitVector(N->getOperand(0), Lo, Hi);
661 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
662 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
665 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
667 // The low and high parts of the original input give four input vectors.
669 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
670 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
671 MVT NewVT = Inputs[0].getValueType();
672 unsigned NewElts = NewVT.getVectorNumElements();
673 assert(NewVT == Inputs[1].getValueType() &&
674 "Non power-of-two vectors not supported!");
676 // If Lo or Hi uses elements from at most two of the four input vectors, then
677 // express it as a vector shuffle of those two inputs. Otherwise extract the
678 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
679 SDValue Mask = N->getOperand(2);
680 MVT IdxVT = Mask.getValueType().getVectorElementType();
681 SmallVector<SDValue, 16> Ops;
682 Ops.reserve(NewElts);
683 for (unsigned High = 0; High < 2; ++High) {
684 SDValue &Output = High ? Hi : Lo;
686 // Build a shuffle mask for the output, discovering on the fly which
687 // input vectors to use as shuffle operands (recorded in InputUsed).
688 // If building a suitable shuffle vector proves too hard, then bail
689 // out with useBuildVector set.
690 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
691 unsigned FirstMaskIdx = High * NewElts;
692 bool useBuildVector = false;
693 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
694 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
696 // The mask element. This indexes into the input.
697 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
698 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
700 // The input vector this mask element indexes into.
701 unsigned Input = Idx / NewElts;
703 if (Input >= array_lengthof(Inputs)) {
704 // The mask element does not index into any input vector.
705 Ops.push_back(DAG.getNode(ISD::UNDEF, IdxVT));
709 // Turn the index into an offset from the start of the input vector.
710 Idx -= Input * NewElts;
712 // Find or create a shuffle vector operand to hold this input.
714 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
715 if (InputUsed[OpNo] == Input) {
716 // This input vector is already an operand.
718 } else if (InputUsed[OpNo] == -1U) {
719 // Create a new operand for this input vector.
720 InputUsed[OpNo] = Input;
725 if (OpNo >= array_lengthof(InputUsed)) {
726 // More than two input vectors used! Give up on trying to create a
727 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
728 useBuildVector = true;
732 // Add the mask index for the new shuffle vector.
733 Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
736 if (useBuildVector) {
737 MVT EltVT = NewVT.getVectorElementType();
740 // Extract the input elements by hand.
741 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
742 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
744 // The mask element. This indexes into the input.
745 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
746 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
748 // The input vector this mask element indexes into.
749 unsigned Input = Idx / NewElts;
751 if (Input >= array_lengthof(Inputs)) {
752 // The mask element is "undef" or indexes off the end of the input.
753 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
757 // Turn the index into an offset from the start of the input vector.
758 Idx -= Input * NewElts;
760 // Extract the vector element by hand.
761 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT,
762 Inputs[Input], DAG.getIntPtrConstant(Idx)));
765 // Construct the Lo/Hi output using a BUILD_VECTOR.
766 Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &Ops[0], Ops.size());
767 } else if (InputUsed[0] == -1U) {
768 // No input vectors were used! The result is undefined.
769 Output = DAG.getNode(ISD::UNDEF, NewVT);
771 // At least one input vector was used. Create a new shuffle vector.
772 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
773 MVT::getVectorVT(IdxVT, Ops.size()),
774 &Ops[0], Ops.size());
775 SDValue Op0 = Inputs[InputUsed[0]];
776 // If only one input was used, use an undefined vector for the other.
777 SDValue Op1 = InputUsed[1] == -1U ?
778 DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]];
779 Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask);
786 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
789 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
791 SDValue LL, LH, RL, RH;
792 GetSplitVector(N->getOperand(0), LL, LH);
793 GetSplitVector(N->getOperand(1), RL, RH);
795 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
796 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
800 //===----------------------------------------------------------------------===//
801 // Operand Vector Splitting
802 //===----------------------------------------------------------------------===//
804 /// SplitVectorOperand - This method is called when the specified operand of the
805 /// specified node is found to need vector splitting. At this point, all of the
806 /// result types of the node are known to be legal, but other operands of the
807 /// node may need legalization as well as the specified one.
808 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
809 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
810 SDValue Res = SDValue();
812 if (Res.getNode() == 0) {
813 switch (N->getOpcode()) {
816 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
817 N->dump(&DAG); cerr << "\n";
819 assert(0 && "Do not know how to split this operator's operand!");
822 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
823 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
824 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
825 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
827 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
832 case ISD::FP_TO_SINT:
833 case ISD::FP_TO_UINT:
834 case ISD::SINT_TO_FP:
836 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
840 // If the result is null, the sub-method took care of registering results etc.
841 if (!Res.getNode()) return false;
843 // If the result is N, the sub-method updated N in place. Check to see if any
844 // operands are new, and if so, mark them.
845 if (Res.getNode() == N) {
846 // Mark N as new and remark N and its operands. This allows us to correctly
847 // revisit N if it needs another step of promotion and allows us to visit
848 // any new operands to N.
853 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
854 "Invalid operand expansion");
856 ReplaceValueWith(SDValue(N, 0), Res);
860 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
861 // The result has a legal vector type, but the input needs splitting.
862 MVT ResVT = N->getValueType(0);
864 GetSplitVector(N->getOperand(0), Lo, Hi);
865 assert(Lo.getValueType() == Hi.getValueType() &&
866 "Returns legal non-power-of-two vector type?");
867 MVT InVT = Lo.getValueType();
869 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
870 InVT.getVectorNumElements());
872 Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
873 Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
875 return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
878 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
879 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
880 // end up being split all the way down to individual components. Convert the
881 // split pieces into integers and reassemble.
883 GetSplitVector(N->getOperand(0), Lo, Hi);
884 Lo = BitConvertToInteger(Lo);
885 Hi = BitConvertToInteger(Hi);
887 if (TLI.isBigEndian())
890 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
891 JoinIntegers(Lo, Hi));
894 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
895 // We know that the extracted result type is legal. For now, assume the index
897 MVT SubVT = N->getValueType(0);
898 SDValue Idx = N->getOperand(1);
900 GetSplitVector(N->getOperand(0), Lo, Hi);
902 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
903 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
905 if (IdxVal < LoElts) {
906 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
907 "Extracted subvector crosses vector split!");
908 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
910 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
911 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
915 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
916 SDValue Vec = N->getOperand(0);
917 SDValue Idx = N->getOperand(1);
918 MVT VecVT = Vec.getValueType();
920 if (isa<ConstantSDNode>(Idx)) {
921 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
922 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
925 GetSplitVector(Vec, Lo, Hi);
927 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
930 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
932 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
933 DAG.getConstant(IdxVal - LoElts,
934 Idx.getValueType()));
937 // Store the vector to the stack.
938 MVT EltVT = VecVT.getVectorElementType();
939 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
940 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
942 // Load back the required element.
943 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
944 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
947 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
948 assert(N->isUnindexed() && "Indexed store of vector?");
949 assert(OpNo == 1 && "Can only split the stored value");
951 bool isTruncating = N->isTruncatingStore();
952 SDValue Ch = N->getChain();
953 SDValue Ptr = N->getBasePtr();
954 int SVOffset = N->getSrcValueOffset();
955 MVT MemoryVT = N->getMemoryVT();
956 unsigned Alignment = N->getAlignment();
957 bool isVol = N->isVolatile();
959 GetSplitVector(N->getOperand(1), Lo, Hi);
961 MVT LoMemVT, HiMemVT;
962 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
964 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
967 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
968 LoMemVT, isVol, Alignment);
970 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
973 // Increment the pointer to the other half.
974 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
975 DAG.getIntPtrConstant(IncrementSize));
978 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
979 N->getSrcValue(), SVOffset+IncrementSize,
981 isVol, MinAlign(Alignment, IncrementSize));
983 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
984 isVol, MinAlign(Alignment, IncrementSize));
986 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
989 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
990 assert(OpNo == 2 && "Shuffle source type differs from result type?");
991 SDValue Mask = N->getOperand(2);
992 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
993 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
994 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
996 // Look for a legal vector type to place the mask values in.
997 // Note that there may not be *any* legal vector-of-integer
998 // type for which the element type is legal!
999 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
1000 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
1001 // Integer values types are consecutively numbered. Exploit this.
1002 EltVT = MVT::SimpleValueType(EltVT + 1)) {
1004 // Is the element type big enough to hold the values?
1005 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
1009 // Is the vector type legal?
1010 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
1011 if (!isTypeLegal(VecVT))
1015 // If the element type is not legal, find a larger legal type to use for
1016 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
1017 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
1018 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
1019 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
1020 // Integer values types are consecutively numbered. Exploit this.
1021 OpVT = MVT::SimpleValueType(OpVT + 1)) {
1022 if (!isTypeLegal(OpVT))
1025 // Success! Rebuild the vector using the legal types.
1026 SmallVector<SDValue, 16> Ops(MaskLength);
1027 for (unsigned i = 0; i < MaskLength; ++i) {
1028 SDValue Arg = Mask.getOperand(i);
1029 if (Arg.getOpcode() == ISD::UNDEF) {
1030 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
1032 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1033 Ops[i] = DAG.getConstant(Idx, OpVT);
1036 return DAG.UpdateNodeOperands(SDValue(N,0),
1037 N->getOperand(0), N->getOperand(1),
1038 DAG.getNode(ISD::BUILD_VECTOR,
1039 VecVT, &Ops[0], Ops.size()));
1042 // Continuing is pointless - failure is certain.
1045 assert(false && "Failed to find an appropriate mask type!");
1046 return SDValue(N, 0);