1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(errs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 errs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
49 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
54 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
55 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
56 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
57 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
58 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
59 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
60 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
61 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
62 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
82 case ISD::SIGN_EXTEND:
83 case ISD::ZERO_EXTEND:
85 R = ScalarizeVecRes_UnaryOp(N);
107 R = ScalarizeVecRes_BinOp(N);
111 // If R is null, the sub-method took care of registering the result.
113 SetScalarizedVector(SDValue(N, ResNo), R);
116 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
117 SDValue LHS = GetScalarizedVector(N->getOperand(0));
118 SDValue RHS = GetScalarizedVector(N->getOperand(1));
119 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
120 LHS.getValueType(), LHS, RHS);
123 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
124 EVT NewVT = N->getValueType(0).getVectorElementType();
125 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
126 NewVT, N->getOperand(0));
129 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
130 EVT NewVT = N->getValueType(0).getVectorElementType();
131 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
132 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
133 Op0, DAG.getValueType(NewVT),
134 DAG.getValueType(Op0.getValueType()),
137 cast<CvtRndSatSDNode>(N)->getCvtCode());
140 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
141 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
142 N->getValueType(0).getVectorElementType(),
143 N->getOperand(0), N->getOperand(1));
146 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
147 SDValue Op = GetScalarizedVector(N->getOperand(0));
148 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
149 Op.getValueType(), Op, N->getOperand(1));
152 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
153 // The value to insert may have a wider type than the vector element type,
154 // so be sure to truncate it to the element type if necessary.
155 SDValue Op = N->getOperand(1);
156 EVT EltVT = N->getValueType(0).getVectorElementType();
157 if (Op.getValueType() != EltVT)
158 // FIXME: Can this happen for floating point types?
159 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
163 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
164 assert(N->isUnindexed() && "Indexed vector load?");
166 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
167 N->getExtensionType(),
168 N->getValueType(0).getVectorElementType(),
169 N->getChain(), N->getBasePtr(),
170 DAG.getUNDEF(N->getBasePtr().getValueType()),
171 N->getSrcValue(), N->getSrcValueOffset(),
172 N->getMemoryVT().getVectorElementType(),
173 N->isVolatile(), N->getAlignment(),
174 N->getOriginalAlignment());
176 // Legalized the chain result - switch anything that used the old chain to
178 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
183 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
184 EVT DestVT = N->getValueType(0).getVectorElementType();
185 SDValue Op = GetScalarizedVector(N->getOperand(0));
186 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
190 // If the operand is wider than the vector element type then it is implicitly
191 // truncated. Make that explicit here.
192 EVT EltVT = N->getValueType(0).getVectorElementType();
193 SDValue InOp = N->getOperand(0);
194 if (InOp.getValueType() != EltVT)
195 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
200 SDValue LHS = GetScalarizedVector(N->getOperand(1));
201 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
202 LHS.getValueType(), N->getOperand(0), LHS,
203 GetScalarizedVector(N->getOperand(2)));
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
207 SDValue LHS = GetScalarizedVector(N->getOperand(2));
208 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
209 N->getOperand(0), N->getOperand(1),
210 LHS, GetScalarizedVector(N->getOperand(3)),
214 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
215 SDValue LHS = GetScalarizedVector(N->getOperand(0));
216 SDValue RHS = GetScalarizedVector(N->getOperand(1));
217 DebugLoc DL = N->getDebugLoc();
219 // Turn it into a scalar SETCC.
220 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
224 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
227 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
228 // Figure out if the scalar is the LHS or RHS and return it.
229 SDValue Arg = N->getOperand(2).getOperand(0);
230 if (Arg.getOpcode() == ISD::UNDEF)
231 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
232 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
233 return GetScalarizedVector(N->getOperand(Op));
236 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
237 SDValue LHS = GetScalarizedVector(N->getOperand(0));
238 SDValue RHS = GetScalarizedVector(N->getOperand(1));
239 EVT NVT = N->getValueType(0).getVectorElementType();
240 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
241 DebugLoc DL = N->getDebugLoc();
243 // Turn it into a scalar SETCC.
244 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
246 // VSETCC always returns a sign-extended value, while SETCC may not. The
247 // SETCC result type may not match the vector element type. Correct these.
248 if (NVT.bitsLE(SVT)) {
249 // The SETCC result type is bigger than the vector element type.
250 // Ensure the SETCC result is sign-extended.
251 if (TLI.getBooleanContents() !=
252 TargetLowering::ZeroOrNegativeOneBooleanContent)
253 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
254 DAG.getValueType(MVT::i1));
255 // Truncate to the final type.
256 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
259 // The SETCC result type is smaller than the vector element type.
260 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
261 if (TLI.getBooleanContents() !=
262 TargetLowering::ZeroOrNegativeOneBooleanContent)
263 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
264 // Sign extend to the final type.
265 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
269 //===----------------------------------------------------------------------===//
270 // Operand Vector Scalarization <1 x ty> -> ty.
271 //===----------------------------------------------------------------------===//
273 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
274 DEBUG(errs() << "Scalarize node operand " << OpNo << ": ";
277 SDValue Res = SDValue();
279 if (Res.getNode() == 0) {
280 switch (N->getOpcode()) {
283 errs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
287 llvm_unreachable("Do not know how to scalarize this operator's operand!");
288 case ISD::BIT_CONVERT:
289 Res = ScalarizeVecOp_BIT_CONVERT(N);
291 case ISD::CONCAT_VECTORS:
292 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
294 case ISD::EXTRACT_VECTOR_ELT:
295 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
298 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
303 // If the result is null, the sub-method took care of registering results etc.
304 if (!Res.getNode()) return false;
306 // If the result is N, the sub-method updated N in place. Tell the legalizer
308 if (Res.getNode() == N)
311 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
312 "Invalid operand expansion");
314 ReplaceValueWith(SDValue(N, 0), Res);
318 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
319 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
320 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
321 SDValue Elt = GetScalarizedVector(N->getOperand(0));
322 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
323 N->getValueType(0), Elt);
326 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
327 /// use a BUILD_VECTOR instead.
328 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
329 SmallVector<SDValue, 8> Ops(N->getNumOperands());
330 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
331 Ops[i] = GetScalarizedVector(N->getOperand(i));
332 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
333 &Ops[0], Ops.size());
336 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
337 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
339 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
340 SDValue Res = GetScalarizedVector(N->getOperand(0));
341 if (Res.getValueType() != N->getValueType(0))
342 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
347 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
348 /// scalarized, it must be <1 x ty>. Just store the element.
349 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
350 assert(N->isUnindexed() && "Indexed store of one-element vector?");
351 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
352 DebugLoc dl = N->getDebugLoc();
354 if (N->isTruncatingStore())
355 return DAG.getTruncStore(N->getChain(), dl,
356 GetScalarizedVector(N->getOperand(1)),
358 N->getSrcValue(), N->getSrcValueOffset(),
359 N->getMemoryVT().getVectorElementType(),
360 N->isVolatile(), N->getAlignment());
362 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
363 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
364 N->isVolatile(), N->getAlignment(),
365 N->getOriginalAlignment());
369 //===----------------------------------------------------------------------===//
370 // Result Vector Splitting
371 //===----------------------------------------------------------------------===//
373 /// SplitVectorResult - This method is called when the specified result of the
374 /// specified node is found to need vector splitting. At this point, the node
375 /// may also have invalid operands or may have other results that need
376 /// legalization, we just know that (at least) one result needs vector
378 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
379 DEBUG(errs() << "Split node result: ";
384 switch (N->getOpcode()) {
387 errs() << "SplitVectorResult #" << ResNo << ": ";
391 llvm_unreachable("Do not know how to split the result of this operator!");
393 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
394 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
395 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
396 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
398 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
399 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
400 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
401 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
402 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
403 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
404 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
405 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
407 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
411 SplitVecRes_SETCC(N, Lo, Hi);
413 case ISD::VECTOR_SHUFFLE:
414 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
429 case ISD::FNEARBYINT:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
435 case ISD::SIGN_EXTEND:
436 case ISD::ZERO_EXTEND:
437 case ISD::ANY_EXTEND:
438 SplitVecRes_UnaryOp(N, Lo, Hi);
460 SplitVecRes_BinOp(N, Lo, Hi);
464 // If Lo/Hi is null, the sub-method took care of registering results etc.
466 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
469 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
471 SDValue LHSLo, LHSHi;
472 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
473 SDValue RHSLo, RHSHi;
474 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
475 DebugLoc dl = N->getDebugLoc();
477 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
478 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
481 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
483 // We know the result is a vector. The input may be either a vector or a
486 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
487 DebugLoc dl = N->getDebugLoc();
489 SDValue InOp = N->getOperand(0);
490 EVT InVT = InOp.getValueType();
492 // Handle some special cases efficiently.
493 switch (getTypeAction(InVT)) {
495 assert(false && "Unknown type action!");
499 case ScalarizeVector:
503 // A scalar to vector conversion, where the scalar needs expansion.
504 // If the vector is being split in two then we can just convert the
507 GetExpandedOp(InOp, Lo, Hi);
508 if (TLI.isBigEndian())
510 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
511 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
516 // If the input is a vector that needs to be split, convert each split
517 // piece of the input now.
518 GetSplitVector(InOp, Lo, Hi);
519 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
520 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
524 // In the general case, convert the input to an integer and split it by hand.
525 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
526 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
527 if (TLI.isBigEndian())
528 std::swap(LoIntVT, HiIntVT);
530 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
532 if (TLI.isBigEndian())
534 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
535 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
538 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
541 DebugLoc dl = N->getDebugLoc();
542 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
543 unsigned LoNumElts = LoVT.getVectorNumElements();
544 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
545 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
547 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
548 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
551 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
553 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
554 DebugLoc dl = N->getDebugLoc();
555 unsigned NumSubvectors = N->getNumOperands() / 2;
556 if (NumSubvectors == 1) {
557 Lo = N->getOperand(0);
558 Hi = N->getOperand(1);
563 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
565 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
566 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
568 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
569 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
572 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
575 DebugLoc dl = N->getDebugLoc();
576 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
578 SDValue DTyOpLo = DAG.getValueType(LoVT);
579 SDValue DTyOpHi = DAG.getValueType(HiVT);
581 SDValue RndOp = N->getOperand(3);
582 SDValue SatOp = N->getOperand(4);
583 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
587 EVT InVT = N->getOperand(0).getValueType();
588 switch (getTypeAction(InVT)) {
589 default: llvm_unreachable("Unexpected type action!");
591 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
592 LoVT.getVectorNumElements());
593 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
594 DAG.getIntPtrConstant(0));
595 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
596 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
600 GetSplitVector(N->getOperand(0), VLo, VHi);
603 // If the result needs to be split and the input needs to be widened,
604 // the two types must have different lengths. Use the widened result
605 // and extract from it to do the split.
606 SDValue InOp = GetWidenedVector(N->getOperand(0));
607 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
608 LoVT.getVectorNumElements());
609 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
610 DAG.getIntPtrConstant(0));
611 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
612 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
617 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
618 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
620 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
622 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
626 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
628 SDValue Vec = N->getOperand(0);
629 SDValue Idx = N->getOperand(1);
630 EVT IdxVT = Idx.getValueType();
631 DebugLoc dl = N->getDebugLoc();
634 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
636 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
637 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
638 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
639 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
642 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
644 DebugLoc dl = N->getDebugLoc();
645 GetSplitVector(N->getOperand(0), Lo, Hi);
646 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
647 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
650 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
652 SDValue Vec = N->getOperand(0);
653 SDValue Elt = N->getOperand(1);
654 SDValue Idx = N->getOperand(2);
655 DebugLoc dl = N->getDebugLoc();
656 GetSplitVector(Vec, Lo, Hi);
658 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
659 unsigned IdxVal = CIdx->getZExtValue();
660 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
661 if (IdxVal < LoNumElts)
662 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
663 Lo.getValueType(), Lo, Elt, Idx);
665 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
666 DAG.getIntPtrConstant(IdxVal - LoNumElts));
670 // Spill the vector to the stack.
671 EVT VecVT = Vec.getValueType();
672 EVT EltVT = VecVT.getVectorElementType();
673 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
674 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
676 // Store the new element. This may be larger than the vector element type,
677 // so use a truncating store.
678 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
680 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT(*DAG.getContext()));
681 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
683 // Load the Lo part from the stack slot.
684 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0);
686 // Increment the pointer to the other part.
687 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
688 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
689 DAG.getIntPtrConstant(IncrementSize));
691 // Load the Hi part from the stack slot.
692 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
693 MinAlign(Alignment, IncrementSize));
696 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
699 DebugLoc dl = N->getDebugLoc();
700 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
701 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
702 Hi = DAG.getUNDEF(HiVT);
705 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
707 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
709 DebugLoc dl = LD->getDebugLoc();
710 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
712 ISD::LoadExtType ExtType = LD->getExtensionType();
713 SDValue Ch = LD->getChain();
714 SDValue Ptr = LD->getBasePtr();
715 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
716 const Value *SV = LD->getSrcValue();
717 int SVOffset = LD->getSrcValueOffset();
718 EVT MemoryVT = LD->getMemoryVT();
719 unsigned Alignment = LD->getAlignment();
720 unsigned OrigAlignment = LD->getOriginalAlignment();
721 bool isVolatile = LD->isVolatile();
723 EVT LoMemVT, HiMemVT;
724 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
726 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
727 SV, SVOffset, LoMemVT, isVolatile, Alignment, OrigAlignment);
729 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
730 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
731 DAG.getIntPtrConstant(IncrementSize));
732 SVOffset += IncrementSize;
733 Alignment = MinAlign(Alignment, IncrementSize);
734 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
735 SV, SVOffset, HiMemVT, isVolatile, Alignment, OrigAlignment);
737 // Build a factor node to remember that this load is independent of the
739 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
742 // Legalized the chain result - switch anything that used the old chain to
744 ReplaceValueWith(SDValue(LD, 1), Ch);
747 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
749 DebugLoc DL = N->getDebugLoc();
750 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
753 EVT InVT = N->getOperand(0).getValueType();
754 SDValue LL, LH, RL, RH;
755 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
756 LoVT.getVectorNumElements());
757 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
758 DAG.getIntPtrConstant(0));
759 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
760 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
762 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
763 DAG.getIntPtrConstant(0));
764 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
765 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
767 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
768 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
771 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
773 // Get the dest types - they may not match the input types, e.g. int_to_fp.
775 DebugLoc dl = N->getDebugLoc();
776 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
779 EVT InVT = N->getOperand(0).getValueType();
780 switch (getTypeAction(InVT)) {
781 default: llvm_unreachable("Unexpected type action!");
783 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
784 LoVT.getVectorNumElements());
785 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
786 DAG.getIntPtrConstant(0));
787 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
788 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
792 GetSplitVector(N->getOperand(0), Lo, Hi);
795 // If the result needs to be split and the input needs to be widened,
796 // the two types must have different lengths. Use the widened result
797 // and extract from it to do the split.
798 SDValue InOp = GetWidenedVector(N->getOperand(0));
799 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
800 LoVT.getVectorNumElements());
801 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
802 DAG.getIntPtrConstant(0));
803 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
804 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
809 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
810 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
813 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
814 SDValue &Lo, SDValue &Hi) {
815 // The low and high parts of the original input give four input vectors.
817 DebugLoc dl = N->getDebugLoc();
818 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
819 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
820 EVT NewVT = Inputs[0].getValueType();
821 unsigned NewElts = NewVT.getVectorNumElements();
823 // If Lo or Hi uses elements from at most two of the four input vectors, then
824 // express it as a vector shuffle of those two inputs. Otherwise extract the
825 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
826 SmallVector<int, 16> Ops;
827 for (unsigned High = 0; High < 2; ++High) {
828 SDValue &Output = High ? Hi : Lo;
830 // Build a shuffle mask for the output, discovering on the fly which
831 // input vectors to use as shuffle operands (recorded in InputUsed).
832 // If building a suitable shuffle vector proves too hard, then bail
833 // out with useBuildVector set.
834 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
835 unsigned FirstMaskIdx = High * NewElts;
836 bool useBuildVector = false;
837 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
838 // The mask element. This indexes into the input.
839 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
841 // The input vector this mask element indexes into.
842 unsigned Input = (unsigned)Idx / NewElts;
844 if (Input >= array_lengthof(Inputs)) {
845 // The mask element does not index into any input vector.
850 // Turn the index into an offset from the start of the input vector.
851 Idx -= Input * NewElts;
853 // Find or create a shuffle vector operand to hold this input.
855 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
856 if (InputUsed[OpNo] == Input) {
857 // This input vector is already an operand.
859 } else if (InputUsed[OpNo] == -1U) {
860 // Create a new operand for this input vector.
861 InputUsed[OpNo] = Input;
866 if (OpNo >= array_lengthof(InputUsed)) {
867 // More than two input vectors used! Give up on trying to create a
868 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
869 useBuildVector = true;
873 // Add the mask index for the new shuffle vector.
874 Ops.push_back(Idx + OpNo * NewElts);
877 if (useBuildVector) {
878 EVT EltVT = NewVT.getVectorElementType();
879 SmallVector<SDValue, 16> SVOps;
881 // Extract the input elements by hand.
882 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
883 // The mask element. This indexes into the input.
884 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
886 // The input vector this mask element indexes into.
887 unsigned Input = (unsigned)Idx / NewElts;
889 if (Input >= array_lengthof(Inputs)) {
890 // The mask element is "undef" or indexes off the end of the input.
891 SVOps.push_back(DAG.getUNDEF(EltVT));
895 // Turn the index into an offset from the start of the input vector.
896 Idx -= Input * NewElts;
898 // Extract the vector element by hand.
899 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
900 Inputs[Input], DAG.getIntPtrConstant(Idx)));
903 // Construct the Lo/Hi output using a BUILD_VECTOR.
904 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
905 } else if (InputUsed[0] == -1U) {
906 // No input vectors were used! The result is undefined.
907 Output = DAG.getUNDEF(NewVT);
909 SDValue Op0 = Inputs[InputUsed[0]];
910 // If only one input was used, use an undefined vector for the other.
911 SDValue Op1 = InputUsed[1] == -1U ?
912 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
913 // At least one input vector was used. Create a new shuffle vector.
914 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
922 //===----------------------------------------------------------------------===//
923 // Operand Vector Splitting
924 //===----------------------------------------------------------------------===//
926 /// SplitVectorOperand - This method is called when the specified operand of the
927 /// specified node is found to need vector splitting. At this point, all of the
928 /// result types of the node are known to be legal, but other operands of the
929 /// node may need legalization as well as the specified one.
930 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
931 DEBUG(errs() << "Split node operand: ";
934 SDValue Res = SDValue();
936 if (Res.getNode() == 0) {
937 switch (N->getOpcode()) {
940 errs() << "SplitVectorOperand Op #" << OpNo << ": ";
944 llvm_unreachable("Do not know how to split this operator's operand!");
946 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
947 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
948 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
950 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
956 case ISD::FP_TO_SINT:
957 case ISD::FP_TO_UINT:
958 case ISD::SINT_TO_FP:
959 case ISD::UINT_TO_FP:
961 case ISD::SIGN_EXTEND:
962 case ISD::ZERO_EXTEND:
963 case ISD::ANY_EXTEND:
964 Res = SplitVecOp_UnaryOp(N);
969 // If the result is null, the sub-method took care of registering results etc.
970 if (!Res.getNode()) return false;
972 // If the result is N, the sub-method updated N in place. Tell the legalizer
974 if (Res.getNode() == N)
977 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
978 "Invalid operand expansion");
980 ReplaceValueWith(SDValue(N, 0), Res);
984 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
985 // The result has a legal vector type, but the input needs splitting.
986 EVT ResVT = N->getValueType(0);
988 DebugLoc dl = N->getDebugLoc();
989 GetSplitVector(N->getOperand(0), Lo, Hi);
990 EVT InVT = Lo.getValueType();
992 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
993 InVT.getVectorNumElements());
995 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
996 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
998 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1001 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
1002 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
1003 // end up being split all the way down to individual components. Convert the
1004 // split pieces into integers and reassemble.
1006 GetSplitVector(N->getOperand(0), Lo, Hi);
1007 Lo = BitConvertToInteger(Lo);
1008 Hi = BitConvertToInteger(Hi);
1010 if (TLI.isBigEndian())
1013 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
1014 JoinIntegers(Lo, Hi));
1017 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1018 // We know that the extracted result type is legal. For now, assume the index
1020 EVT SubVT = N->getValueType(0);
1021 SDValue Idx = N->getOperand(1);
1022 DebugLoc dl = N->getDebugLoc();
1024 GetSplitVector(N->getOperand(0), Lo, Hi);
1026 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1027 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1029 if (IdxVal < LoElts) {
1030 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1031 "Extracted subvector crosses vector split!");
1032 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1034 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1035 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1039 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1040 SDValue Vec = N->getOperand(0);
1041 SDValue Idx = N->getOperand(1);
1042 EVT VecVT = Vec.getValueType();
1044 if (isa<ConstantSDNode>(Idx)) {
1045 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1046 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1049 GetSplitVector(Vec, Lo, Hi);
1051 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1053 if (IdxVal < LoElts)
1054 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
1055 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
1056 DAG.getConstant(IdxVal - LoElts,
1057 Idx.getValueType()));
1060 // Store the vector to the stack.
1061 EVT EltVT = VecVT.getVectorElementType();
1062 DebugLoc dl = N->getDebugLoc();
1063 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1064 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1065 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1066 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0);
1068 // Load back the required element.
1069 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1070 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1074 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1075 assert(N->isUnindexed() && "Indexed store of vector?");
1076 assert(OpNo == 1 && "Can only split the stored value");
1077 DebugLoc dl = N->getDebugLoc();
1079 bool isTruncating = N->isTruncatingStore();
1080 SDValue Ch = N->getChain();
1081 SDValue Ptr = N->getBasePtr();
1082 int SVOffset = N->getSrcValueOffset();
1083 EVT MemoryVT = N->getMemoryVT();
1084 unsigned Alignment = N->getAlignment();
1085 unsigned OrigAlignment = N->getOriginalAlignment();
1086 bool isVol = N->isVolatile();
1088 GetSplitVector(N->getOperand(1), Lo, Hi);
1090 EVT LoMemVT, HiMemVT;
1091 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1093 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1096 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1097 LoMemVT, isVol, Alignment);
1099 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1100 isVol, Alignment, OrigAlignment);
1102 // Increment the pointer to the other half.
1103 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1104 DAG.getIntPtrConstant(IncrementSize));
1107 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
1108 N->getSrcValue(), SVOffset+IncrementSize,
1110 isVol, MinAlign(Alignment, IncrementSize));
1112 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1113 isVol, MinAlign(Alignment, IncrementSize),
1116 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1120 //===----------------------------------------------------------------------===//
1121 // Result Vector Widening
1122 //===----------------------------------------------------------------------===//
1124 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1125 DEBUG(errs() << "Widen node result " << ResNo << ": ";
1128 SDValue Res = SDValue();
1130 switch (N->getOpcode()) {
1133 errs() << "WidenVectorResult #" << ResNo << ": ";
1137 llvm_unreachable("Do not know how to widen the result of this operator!");
1139 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1140 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1141 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1142 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1143 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1144 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1145 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1146 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1147 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1148 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1149 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1150 case ISD::VECTOR_SHUFFLE:
1151 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1154 Res = WidenVecRes_VSETCC(N);
1161 case ISD::FCOPYSIGN:
1178 Res = WidenVecRes_Binary(N);
1184 Res = WidenVecRes_Shift(N);
1188 case ISD::FP_TO_SINT:
1189 case ISD::FP_TO_UINT:
1190 case ISD::SINT_TO_FP:
1191 case ISD::UINT_TO_FP:
1193 case ISD::SIGN_EXTEND:
1194 case ISD::ZERO_EXTEND:
1195 case ISD::ANY_EXTEND:
1196 Res = WidenVecRes_Convert(N);
1207 Res = WidenVecRes_Unary(N);
1211 // If Res is null, the sub-method took care of registering the result.
1213 SetWidenedVector(SDValue(N, ResNo), Res);
1216 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1217 // Binary op widening.
1218 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1219 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1220 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1221 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
1224 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1225 SDValue InOp = N->getOperand(0);
1226 DebugLoc dl = N->getDebugLoc();
1228 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1229 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1231 EVT InVT = InOp.getValueType();
1232 EVT InEltVT = InVT.getVectorElementType();
1233 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1235 unsigned Opcode = N->getOpcode();
1236 unsigned InVTNumElts = InVT.getVectorNumElements();
1238 if (getTypeAction(InVT) == WidenVector) {
1239 InOp = GetWidenedVector(N->getOperand(0));
1240 InVT = InOp.getValueType();
1241 InVTNumElts = InVT.getVectorNumElements();
1242 if (InVTNumElts == WidenNumElts)
1243 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1246 if (TLI.isTypeLegal(InWidenVT)) {
1247 // Because the result and the input are different vector types, widening
1248 // the result could create a legal type but widening the input might make
1249 // it an illegal type that might lead to repeatedly splitting the input
1250 // and then widening it. To avoid this, we widen the input only if
1251 // it results in a legal type.
1252 if (WidenNumElts % InVTNumElts == 0) {
1253 // Widen the input and call convert on the widened input vector.
1254 unsigned NumConcat = WidenNumElts/InVTNumElts;
1255 SmallVector<SDValue, 16> Ops(NumConcat);
1257 SDValue UndefVal = DAG.getUNDEF(InVT);
1258 for (unsigned i = 1; i != NumConcat; ++i)
1260 return DAG.getNode(Opcode, dl, WidenVT,
1261 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1262 &Ops[0], NumConcat));
1265 if (InVTNumElts % WidenNumElts == 0) {
1266 // Extract the input and convert the shorten input vector.
1267 return DAG.getNode(Opcode, dl, WidenVT,
1268 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1269 InOp, DAG.getIntPtrConstant(0)));
1273 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1274 SmallVector<SDValue, 16> Ops(WidenNumElts);
1275 EVT EltVT = WidenVT.getVectorElementType();
1276 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1278 for (i=0; i < MinElts; ++i)
1279 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1280 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1281 DAG.getIntPtrConstant(i)));
1283 SDValue UndefVal = DAG.getUNDEF(EltVT);
1284 for (; i < WidenNumElts; ++i)
1287 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1290 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1291 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1292 SDValue InOp = GetWidenedVector(N->getOperand(0));
1293 SDValue ShOp = N->getOperand(1);
1295 EVT ShVT = ShOp.getValueType();
1296 if (getTypeAction(ShVT) == WidenVector) {
1297 ShOp = GetWidenedVector(ShOp);
1298 ShVT = ShOp.getValueType();
1300 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), ShVT.getVectorElementType(),
1301 WidenVT.getVectorNumElements());
1302 if (ShVT != ShWidenVT)
1303 ShOp = ModifyToType(ShOp, ShWidenVT);
1305 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1308 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1309 // Unary op widening.
1310 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1311 SDValue InOp = GetWidenedVector(N->getOperand(0));
1312 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1315 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1316 SDValue InOp = N->getOperand(0);
1317 EVT InVT = InOp.getValueType();
1318 EVT VT = N->getValueType(0);
1319 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1320 DebugLoc dl = N->getDebugLoc();
1322 switch (getTypeAction(InVT)) {
1324 assert(false && "Unknown type action!");
1328 case PromoteInteger:
1329 // If the InOp is promoted to the same size, convert it. Otherwise,
1330 // fall out of the switch and widen the promoted input.
1331 InOp = GetPromotedInteger(InOp);
1332 InVT = InOp.getValueType();
1333 if (WidenVT.bitsEq(InVT))
1334 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1339 case ScalarizeVector:
1343 // If the InOp is widened to the same size, convert it. Otherwise, fall
1344 // out of the switch and widen the widened input.
1345 InOp = GetWidenedVector(InOp);
1346 InVT = InOp.getValueType();
1347 if (WidenVT.bitsEq(InVT))
1348 // The input widens to the same size. Convert to the widen value.
1349 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1353 unsigned WidenSize = WidenVT.getSizeInBits();
1354 unsigned InSize = InVT.getSizeInBits();
1355 if (WidenSize % InSize == 0) {
1356 // Determine new input vector type. The new input vector type will use
1357 // the same element type (if its a vector) or use the input type as a
1358 // vector. It is the same size as the type to widen to.
1360 unsigned NewNumElts = WidenSize / InSize;
1361 if (InVT.isVector()) {
1362 EVT InEltVT = InVT.getVectorElementType();
1363 NewInVT= EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenSize / InEltVT.getSizeInBits());
1365 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1368 if (TLI.isTypeLegal(NewInVT)) {
1369 // Because the result and the input are different vector types, widening
1370 // the result could create a legal type but widening the input might make
1371 // it an illegal type that might lead to repeatedly splitting the input
1372 // and then widening it. To avoid this, we widen the input only if
1373 // it results in a legal type.
1374 SmallVector<SDValue, 16> Ops(NewNumElts);
1375 SDValue UndefVal = DAG.getUNDEF(InVT);
1377 for (unsigned i = 1; i < NewNumElts; ++i)
1381 if (InVT.isVector())
1382 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1383 NewInVT, &Ops[0], NewNumElts);
1385 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1386 NewInVT, &Ops[0], NewNumElts);
1387 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1391 return CreateStackStoreLoad(InOp, WidenVT);
1394 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1395 DebugLoc dl = N->getDebugLoc();
1396 // Build a vector with undefined for the new nodes.
1397 EVT VT = N->getValueType(0);
1398 EVT EltVT = VT.getVectorElementType();
1399 unsigned NumElts = VT.getVectorNumElements();
1401 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1402 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1404 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1405 NewOps.reserve(WidenNumElts);
1406 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1407 NewOps.push_back(DAG.getUNDEF(EltVT));
1409 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1412 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1413 EVT InVT = N->getOperand(0).getValueType();
1414 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1415 DebugLoc dl = N->getDebugLoc();
1416 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1417 unsigned NumOperands = N->getNumOperands();
1419 bool InputWidened = false; // Indicates we need to widen the input.
1420 if (getTypeAction(InVT) != WidenVector) {
1421 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1422 // Add undef vectors to widen to correct length.
1423 unsigned NumConcat = WidenVT.getVectorNumElements() /
1424 InVT.getVectorNumElements();
1425 SDValue UndefVal = DAG.getUNDEF(InVT);
1426 SmallVector<SDValue, 16> Ops(NumConcat);
1427 for (unsigned i=0; i < NumOperands; ++i)
1428 Ops[i] = N->getOperand(i);
1429 for (unsigned i = NumOperands; i != NumConcat; ++i)
1431 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1434 InputWidened = true;
1435 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1436 // The inputs and the result are widen to the same value.
1438 for (i=1; i < NumOperands; ++i)
1439 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1442 if (i > NumOperands)
1443 // Everything but the first operand is an UNDEF so just return the
1444 // widened first operand.
1445 return GetWidenedVector(N->getOperand(0));
1447 if (NumOperands == 2) {
1448 // Replace concat of two operands with a shuffle.
1449 SmallVector<int, 16> MaskOps(WidenNumElts);
1450 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1452 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1454 return DAG.getVectorShuffle(WidenVT, dl,
1455 GetWidenedVector(N->getOperand(0)),
1456 GetWidenedVector(N->getOperand(1)),
1462 // Fall back to use extracts and build vector.
1463 EVT EltVT = WidenVT.getVectorElementType();
1464 unsigned NumInElts = InVT.getVectorNumElements();
1465 SmallVector<SDValue, 16> Ops(WidenNumElts);
1467 for (unsigned i=0; i < NumOperands; ++i) {
1468 SDValue InOp = N->getOperand(i);
1470 InOp = GetWidenedVector(InOp);
1471 for (unsigned j=0; j < NumInElts; ++j)
1472 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1473 DAG.getIntPtrConstant(j));
1475 SDValue UndefVal = DAG.getUNDEF(EltVT);
1476 for (; Idx < WidenNumElts; ++Idx)
1477 Ops[Idx] = UndefVal;
1478 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1481 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1482 DebugLoc dl = N->getDebugLoc();
1483 SDValue InOp = N->getOperand(0);
1484 SDValue RndOp = N->getOperand(3);
1485 SDValue SatOp = N->getOperand(4);
1487 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1488 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1490 EVT InVT = InOp.getValueType();
1491 EVT InEltVT = InVT.getVectorElementType();
1492 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1494 SDValue DTyOp = DAG.getValueType(WidenVT);
1495 SDValue STyOp = DAG.getValueType(InWidenVT);
1496 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1498 unsigned InVTNumElts = InVT.getVectorNumElements();
1499 if (getTypeAction(InVT) == WidenVector) {
1500 InOp = GetWidenedVector(InOp);
1501 InVT = InOp.getValueType();
1502 InVTNumElts = InVT.getVectorNumElements();
1503 if (InVTNumElts == WidenNumElts)
1504 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1508 if (TLI.isTypeLegal(InWidenVT)) {
1509 // Because the result and the input are different vector types, widening
1510 // the result could create a legal type but widening the input might make
1511 // it an illegal type that might lead to repeatedly splitting the input
1512 // and then widening it. To avoid this, we widen the input only if
1513 // it results in a legal type.
1514 if (WidenNumElts % InVTNumElts == 0) {
1515 // Widen the input and call convert on the widened input vector.
1516 unsigned NumConcat = WidenNumElts/InVTNumElts;
1517 SmallVector<SDValue, 16> Ops(NumConcat);
1519 SDValue UndefVal = DAG.getUNDEF(InVT);
1520 for (unsigned i = 1; i != NumConcat; ++i) {
1523 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1524 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1528 if (InVTNumElts % WidenNumElts == 0) {
1529 // Extract the input and convert the shorten input vector.
1530 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1531 DAG.getIntPtrConstant(0));
1532 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1537 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1538 SmallVector<SDValue, 16> Ops(WidenNumElts);
1539 EVT EltVT = WidenVT.getVectorElementType();
1540 DTyOp = DAG.getValueType(EltVT);
1541 STyOp = DAG.getValueType(InEltVT);
1543 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1545 for (i=0; i < MinElts; ++i) {
1546 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1547 DAG.getIntPtrConstant(i));
1548 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1552 SDValue UndefVal = DAG.getUNDEF(EltVT);
1553 for (; i < WidenNumElts; ++i)
1556 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1559 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1560 EVT VT = N->getValueType(0);
1561 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1562 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1563 SDValue InOp = N->getOperand(0);
1564 SDValue Idx = N->getOperand(1);
1565 DebugLoc dl = N->getDebugLoc();
1567 if (getTypeAction(InOp.getValueType()) == WidenVector)
1568 InOp = GetWidenedVector(InOp);
1570 EVT InVT = InOp.getValueType();
1572 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1574 unsigned IdxVal = CIdx->getZExtValue();
1575 // Check if we can just return the input vector after widening.
1576 if (IdxVal == 0 && InVT == WidenVT)
1579 // Check if we can extract from the vector.
1580 unsigned InNumElts = InVT.getVectorNumElements();
1581 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1582 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1585 // We could try widening the input to the right length but for now, extract
1586 // the original elements, fill the rest with undefs and build a vector.
1587 SmallVector<SDValue, 16> Ops(WidenNumElts);
1588 EVT EltVT = VT.getVectorElementType();
1589 EVT IdxVT = Idx.getValueType();
1590 unsigned NumElts = VT.getVectorNumElements();
1593 unsigned IdxVal = CIdx->getZExtValue();
1594 for (i=0; i < NumElts; ++i)
1595 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1596 DAG.getConstant(IdxVal+i, IdxVT));
1598 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1599 for (i=1; i < NumElts; ++i) {
1600 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1601 DAG.getConstant(i, IdxVT));
1602 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1606 SDValue UndefVal = DAG.getUNDEF(EltVT);
1607 for (; i < WidenNumElts; ++i)
1609 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1612 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1613 SDValue InOp = GetWidenedVector(N->getOperand(0));
1614 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1615 InOp.getValueType(), InOp,
1616 N->getOperand(1), N->getOperand(2));
1619 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1620 LoadSDNode *LD = cast<LoadSDNode>(N);
1621 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
1622 EVT LdVT = LD->getMemoryVT();
1623 DebugLoc dl = N->getDebugLoc();
1624 assert(LdVT.isVector() && WidenVT.isVector());
1627 SDValue Chain = LD->getChain();
1628 SDValue BasePtr = LD->getBasePtr();
1629 int SVOffset = LD->getSrcValueOffset();
1630 unsigned Align = LD->getAlignment();
1631 bool isVolatile = LD->isVolatile();
1632 const Value *SV = LD->getSrcValue();
1633 ISD::LoadExtType ExtType = LD->getExtensionType();
1636 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1637 if (ExtType != ISD::NON_EXTLOAD) {
1638 // For extension loads, we can not play the tricks of chopping legal
1639 // vector types and bit cast it to the right type. Instead, we unroll
1640 // the load and build a vector.
1641 EVT EltVT = WidenVT.getVectorElementType();
1642 EVT LdEltVT = LdVT.getVectorElementType();
1643 unsigned NumElts = LdVT.getVectorNumElements();
1645 // Load each element and widen
1646 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1647 SmallVector<SDValue, 16> Ops(WidenNumElts);
1648 unsigned Increment = LdEltVT.getSizeInBits() / 8;
1649 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
1650 LdEltVT, isVolatile, Align);
1651 LdChain.push_back(Ops[0].getValue(1));
1652 unsigned i = 0, Offset = Increment;
1653 for (i=1; i < NumElts; ++i, Offset += Increment) {
1654 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1655 BasePtr, DAG.getIntPtrConstant(Offset));
1656 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
1657 SVOffset + Offset, LdEltVT, isVolatile, Align);
1658 LdChain.push_back(Ops[i].getValue(1));
1661 // Fill the rest with undefs
1662 SDValue UndefVal = DAG.getUNDEF(EltVT);
1663 for (; i != WidenNumElts; ++i)
1666 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
1668 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
1669 unsigned int LdWidth = LdVT.getSizeInBits();
1670 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
1671 Align, isVolatile, LdWidth, WidenVT, dl);
1674 // If we generate a single load, we can use that for the chain. Otherwise,
1675 // build a factor node to remember the multiple loads are independent and
1678 if (LdChain.size() == 1)
1679 NewChain = LdChain[0];
1681 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
1684 // Modified the chain - switch anything that used the old chain to use
1686 ReplaceValueWith(SDValue(N, 1), NewChain);
1691 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1692 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1693 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1694 WidenVT, N->getOperand(0));
1697 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1698 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1699 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1701 SDValue Cond1 = N->getOperand(0);
1702 EVT CondVT = Cond1.getValueType();
1703 if (CondVT.isVector()) {
1704 EVT CondEltVT = CondVT.getVectorElementType();
1705 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), CondEltVT, WidenNumElts);
1706 if (getTypeAction(CondVT) == WidenVector)
1707 Cond1 = GetWidenedVector(Cond1);
1709 if (Cond1.getValueType() != CondWidenVT)
1710 Cond1 = ModifyToType(Cond1, CondWidenVT);
1713 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1714 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1715 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1716 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1717 WidenVT, Cond1, InOp1, InOp2);
1720 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1721 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1722 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1723 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1724 InOp1.getValueType(), N->getOperand(0),
1725 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1728 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1729 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1730 return DAG.getUNDEF(WidenVT);
1733 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1734 EVT VT = N->getValueType(0);
1735 DebugLoc dl = N->getDebugLoc();
1737 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1738 unsigned NumElts = VT.getVectorNumElements();
1739 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1741 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1742 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1744 // Adjust mask based on new input vector length.
1745 SmallVector<int, 16> NewMask;
1746 for (unsigned i = 0; i != NumElts; ++i) {
1747 int Idx = N->getMaskElt(i);
1748 if (Idx < (int)NumElts)
1749 NewMask.push_back(Idx);
1751 NewMask.push_back(Idx - NumElts + WidenNumElts);
1753 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1754 NewMask.push_back(-1);
1755 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1758 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1759 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1760 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1762 SDValue InOp1 = N->getOperand(0);
1763 EVT InVT = InOp1.getValueType();
1764 assert(InVT.isVector() && "can not widen non vector type");
1765 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), WidenNumElts);
1766 InOp1 = GetWidenedVector(InOp1);
1767 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1769 // Assume that the input and output will be widen appropriately. If not,
1770 // we will have to unroll it at some point.
1771 assert(InOp1.getValueType() == WidenInVT &&
1772 InOp2.getValueType() == WidenInVT &&
1773 "Input not widened to expected type!");
1774 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1775 WidenVT, InOp1, InOp2, N->getOperand(2));
1779 //===----------------------------------------------------------------------===//
1780 // Widen Vector Operand
1781 //===----------------------------------------------------------------------===//
1782 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1783 DEBUG(errs() << "Widen node operand " << ResNo << ": ";
1786 SDValue Res = SDValue();
1788 switch (N->getOpcode()) {
1791 errs() << "WidenVectorOperand op #" << ResNo << ": ";
1795 llvm_unreachable("Do not know how to widen this operator's operand!");
1797 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1798 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1799 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1800 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1803 case ISD::FP_TO_SINT:
1804 case ISD::FP_TO_UINT:
1805 case ISD::SINT_TO_FP:
1806 case ISD::UINT_TO_FP:
1808 case ISD::SIGN_EXTEND:
1809 case ISD::ZERO_EXTEND:
1810 case ISD::ANY_EXTEND:
1811 Res = WidenVecOp_Convert(N);
1815 // If Res is null, the sub-method took care of registering the result.
1816 if (!Res.getNode()) return false;
1818 // If the result is N, the sub-method updated N in place. Tell the legalizer
1820 if (Res.getNode() == N)
1824 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1825 "Invalid operand expansion");
1827 ReplaceValueWith(SDValue(N, 0), Res);
1831 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1832 // Since the result is legal and the input is illegal, it is unlikely
1833 // that we can fix the input to a legal type so unroll the convert
1834 // into some scalar code and create a nasty build vector.
1835 EVT VT = N->getValueType(0);
1836 EVT EltVT = VT.getVectorElementType();
1837 DebugLoc dl = N->getDebugLoc();
1838 unsigned NumElts = VT.getVectorNumElements();
1839 SDValue InOp = N->getOperand(0);
1840 if (getTypeAction(InOp.getValueType()) == WidenVector)
1841 InOp = GetWidenedVector(InOp);
1842 EVT InVT = InOp.getValueType();
1843 EVT InEltVT = InVT.getVectorElementType();
1845 unsigned Opcode = N->getOpcode();
1846 SmallVector<SDValue, 16> Ops(NumElts);
1847 for (unsigned i=0; i < NumElts; ++i)
1848 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1849 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1850 DAG.getIntPtrConstant(i)));
1852 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1855 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
1856 EVT VT = N->getValueType(0);
1857 SDValue InOp = GetWidenedVector(N->getOperand(0));
1858 EVT InWidenVT = InOp.getValueType();
1859 DebugLoc dl = N->getDebugLoc();
1861 // Check if we can convert between two legal vector types and extract.
1862 unsigned InWidenSize = InWidenVT.getSizeInBits();
1863 unsigned Size = VT.getSizeInBits();
1864 if (InWidenSize % Size == 0 && !VT.isVector()) {
1865 unsigned NewNumElts = InWidenSize / Size;
1866 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
1867 if (TLI.isTypeLegal(NewVT)) {
1868 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
1869 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
1870 DAG.getIntPtrConstant(0));
1874 return CreateStackStoreLoad(InOp, VT);
1877 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1878 // If the input vector is not legal, it is likely that we will not find a
1879 // legal vector of the same size. Replace the concatenate vector with a
1880 // nasty build vector.
1881 EVT VT = N->getValueType(0);
1882 EVT EltVT = VT.getVectorElementType();
1883 DebugLoc dl = N->getDebugLoc();
1884 unsigned NumElts = VT.getVectorNumElements();
1885 SmallVector<SDValue, 16> Ops(NumElts);
1887 EVT InVT = N->getOperand(0).getValueType();
1888 unsigned NumInElts = InVT.getVectorNumElements();
1891 unsigned NumOperands = N->getNumOperands();
1892 for (unsigned i=0; i < NumOperands; ++i) {
1893 SDValue InOp = N->getOperand(i);
1894 if (getTypeAction(InOp.getValueType()) == WidenVector)
1895 InOp = GetWidenedVector(InOp);
1896 for (unsigned j=0; j < NumInElts; ++j)
1897 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1898 DAG.getIntPtrConstant(j));
1900 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1903 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1904 SDValue InOp = GetWidenedVector(N->getOperand(0));
1905 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
1906 N->getValueType(0), InOp, N->getOperand(1));
1909 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1910 // We have to widen the value but we want only to store the original
1912 StoreSDNode *ST = cast<StoreSDNode>(N);
1913 SDValue Chain = ST->getChain();
1914 SDValue BasePtr = ST->getBasePtr();
1915 const Value *SV = ST->getSrcValue();
1916 int SVOffset = ST->getSrcValueOffset();
1917 unsigned Align = ST->getAlignment();
1918 bool isVolatile = ST->isVolatile();
1919 SDValue ValOp = GetWidenedVector(ST->getValue());
1920 DebugLoc dl = N->getDebugLoc();
1922 EVT StVT = ST->getMemoryVT();
1923 EVT ValVT = ValOp.getValueType();
1924 // It must be true that we the widen vector type is bigger than where
1925 // we need to store.
1926 assert(StVT.isVector() && ValOp.getValueType().isVector());
1927 assert(StVT.bitsLT(ValOp.getValueType()));
1929 SmallVector<SDValue, 16> StChain;
1930 if (ST->isTruncatingStore()) {
1931 // For truncating stores, we can not play the tricks of chopping legal
1932 // vector types and bit cast it to the right type. Instead, we unroll
1934 EVT StEltVT = StVT.getVectorElementType();
1935 EVT ValEltVT = ValVT.getVectorElementType();
1936 unsigned Increment = ValEltVT.getSizeInBits() / 8;
1937 unsigned NumElts = StVT.getVectorNumElements();
1938 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1939 DAG.getIntPtrConstant(0));
1940 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
1942 isVolatile, Align));
1943 unsigned Offset = Increment;
1944 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
1945 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1946 BasePtr, DAG.getIntPtrConstant(Offset));
1947 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1948 DAG.getIntPtrConstant(0));
1949 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
1950 SVOffset + Offset, StEltVT,
1951 isVolatile, MinAlign(Align, Offset)));
1955 assert(StVT.getVectorElementType() == ValVT.getVectorElementType());
1957 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset,
1958 Align, isVolatile, ValOp, StVT.getSizeInBits(), dl);
1960 if (StChain.size() == 1)
1963 return DAG.getNode(ISD::TokenFactor, dl,
1964 MVT::Other,&StChain[0],StChain.size());
1967 //===----------------------------------------------------------------------===//
1968 // Vector Widening Utilities
1969 //===----------------------------------------------------------------------===//
1972 // Utility function to find a vector type and its associated element
1973 // type from a preferred width and whose vector type must be the same size
1975 // TLI: Target lowering used to determine legal types.
1976 // Width: Preferred width to store.
1977 // VecVT: Vector value type whose size we must match.
1978 // Returns NewVecVT and NewEltVT - the vector type and its associated
1980 static void FindAssocWidenVecType(SelectionDAG& DAG,
1981 const TargetLowering &TLI, unsigned Width,
1983 EVT& NewEltVT, EVT& NewVecVT) {
1984 unsigned EltWidth = Width + 1;
1985 if (TLI.isTypeLegal(VecVT)) {
1986 // We start with the preferred with, making it a power of 2 and find a
1987 // legal vector type of that width. If not, we reduce it by another of 2.
1988 // For incoming type is legal, this process will end as a vector of the
1989 // smallest loadable type should always be legal.
1991 assert(EltWidth > 0);
1992 EltWidth = 1 << Log2_32(EltWidth - 1);
1993 NewEltVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
1994 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1995 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, NumElts);
1996 } while (!TLI.isTypeLegal(NewVecVT) ||
1997 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1999 // The incoming vector type is illegal and is the result of widening
2000 // a vector to a power of 2. In this case, we will use the preferred
2001 // with as long as it is a multiple of the incoming vector length.
2002 // The legalization process will eventually make this into a legal type
2003 // and remove the illegal bit converts (which would turn to stack converts
2004 // if they are allow to exist).
2006 assert(EltWidth > 0);
2007 EltWidth = 1 << Log2_32(EltWidth - 1);
2008 NewEltVT = EVT::getIntegerVT(*DAG.getContext(), EltWidth);
2009 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
2010 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, NumElts);
2011 } while (!TLI.isTypeLegal(NewEltVT) ||
2012 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
2016 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
2026 // The strategy assumes that we can efficiently load powers of two widths.
2027 // The routines chops the vector into the largest power of 2 load and
2028 // can be inserted into a legal vector and then cast the result into the
2029 // vector type we want. This avoids unnecessary stack converts.
2031 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
2032 // the load is nonvolatile, we an use a wider load for the value.
2034 // Find the vector type that can load from.
2035 EVT NewEltVT, NewVecVT;
2036 unsigned NewEltVTWidth;
2037 FindAssocWidenVecType(DAG, TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2038 NewEltVTWidth = NewEltVT.getSizeInBits();
2040 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset,
2041 isVolatile, Alignment);
2042 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2043 LdChain.push_back(LdOp.getValue(1));
2045 // Check if we can load the element with one instruction
2046 if (LdWidth == NewEltVTWidth) {
2047 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2051 LdWidth -= NewEltVTWidth;
2052 unsigned Offset = 0;
2054 while (LdWidth > 0) {
2055 unsigned Increment = NewEltVTWidth / 8;
2056 Offset += Increment;
2057 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2058 DAG.getIntPtrConstant(Increment));
2060 if (LdWidth < NewEltVTWidth) {
2061 // Our current type we are using is too large, use a smaller size by
2062 // using a smaller power of 2
2063 unsigned oNewEltVTWidth = NewEltVTWidth;
2064 FindAssocWidenVecType(DAG, TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2065 NewEltVTWidth = NewEltVT.getSizeInBits();
2066 // Readjust position and vector position based on new load type
2067 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2068 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2071 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV,
2072 SVOffset+Offset, isVolatile,
2073 MinAlign(Alignment, Offset));
2074 LdChain.push_back(LdOp.getValue(1));
2075 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOp,
2076 DAG.getIntPtrConstant(Idx++));
2078 LdWidth -= NewEltVTWidth;
2081 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2084 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2094 // Breaks the stores into a series of power of 2 width stores. For any
2095 // width, we convert the vector to the vector of element size that we
2096 // want to store. This avoids requiring a stack convert.
2098 // Find a width of the element type we can store with
2099 EVT WidenVT = ValOp.getValueType();
2100 EVT NewEltVT, NewVecVT;
2102 FindAssocWidenVecType(DAG, TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2103 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
2105 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2106 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2107 DAG.getIntPtrConstant(0));
2108 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
2109 isVolatile, Alignment);
2110 StChain.push_back(StOp);
2112 // Check if we are done
2113 if (StWidth == NewEltVTWidth) {
2118 StWidth -= NewEltVTWidth;
2119 unsigned Offset = 0;
2121 while (StWidth > 0) {
2122 unsigned Increment = NewEltVTWidth / 8;
2123 Offset += Increment;
2124 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2125 DAG.getIntPtrConstant(Increment));
2127 if (StWidth < NewEltVTWidth) {
2128 // Our current type we are using is too large, use a smaller size by
2129 // using a smaller power of 2
2130 unsigned oNewEltVTWidth = NewEltVTWidth;
2131 FindAssocWidenVecType(DAG, TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2132 NewEltVTWidth = NewEltVT.getSizeInBits();
2133 // Readjust position and vector position based on new load type
2134 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2135 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2138 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2139 DAG.getIntPtrConstant(Idx++));
2140 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2141 SVOffset + Offset, isVolatile,
2142 MinAlign(Alignment, Offset)));
2143 StWidth -= NewEltVTWidth;
2147 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2148 /// input vector must have the same element type as NVT.
2149 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2150 // Note that InOp might have been widened so it might already have
2151 // the right width or it might need be narrowed.
2152 EVT InVT = InOp.getValueType();
2153 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2154 "input and widen element type must match");
2155 DebugLoc dl = InOp.getDebugLoc();
2157 // Check if InOp already has the right width.
2161 unsigned InNumElts = InVT.getVectorNumElements();
2162 unsigned WidenNumElts = NVT.getVectorNumElements();
2163 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2164 unsigned NumConcat = WidenNumElts / InNumElts;
2165 SmallVector<SDValue, 16> Ops(NumConcat);
2166 SDValue UndefVal = DAG.getUNDEF(InVT);
2168 for (unsigned i = 1; i != NumConcat; ++i)
2171 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2174 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2175 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2176 DAG.getIntPtrConstant(0));
2178 // Fall back to extract and build.
2179 SmallVector<SDValue, 16> Ops(WidenNumElts);
2180 EVT EltVT = NVT.getVectorElementType();
2181 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2183 for (Idx = 0; Idx < MinNumElts; ++Idx)
2184 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2185 DAG.getIntPtrConstant(Idx));
2187 SDValue UndefVal = DAG.getUNDEF(EltVT);
2188 for ( ; Idx < WidenNumElts; ++Idx)
2189 Ops[Idx] = UndefVal;
2190 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);