1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 report_fatal_error("Do not know how to scalarize the result of this "
50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
53 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
55 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
56 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
57 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
59 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
60 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
89 case ISD::SIGN_EXTEND:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
116 R = ScalarizeVecRes_BinOp(N);
120 // If R is null, the sub-method took care of registering the result.
122 SetScalarizedVector(SDValue(N, ResNo), R);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
129 LHS.getValueType(), LHS, RHS);
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return GetScalarizedVector(Op);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
139 EVT NewVT = N->getValueType(0).getVectorElementType();
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
141 NewVT, N->getOperand(0));
144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
145 EVT NewVT = N->getValueType(0).getVectorElementType();
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
148 Op0, DAG.getValueType(NewVT),
149 DAG.getValueType(Op0.getValueType()),
152 cast<CvtRndSatSDNode>(N)->getCvtCode());
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
157 N->getValueType(0).getVectorElementType(),
158 N->getOperand(0), N->getOperand(1));
161 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
162 EVT NewVT = N->getValueType(0).getVectorElementType();
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
165 NewVT, Op, N->getOperand(1));
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
169 SDValue Op = GetScalarizedVector(N->getOperand(0));
170 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
171 Op.getValueType(), Op, N->getOperand(1));
174 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
175 // The value to insert may have a wider type than the vector element type,
176 // so be sure to truncate it to the element type if necessary.
177 SDValue Op = N->getOperand(1);
178 EVT EltVT = N->getValueType(0).getVectorElementType();
179 if (Op.getValueType() != EltVT)
180 // FIXME: Can this happen for floating point types?
181 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
186 assert(N->isUnindexed() && "Indexed vector load?");
188 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
189 N->getExtensionType(),
190 N->getValueType(0).getVectorElementType(),
192 N->getChain(), N->getBasePtr(),
193 DAG.getUNDEF(N->getBasePtr().getValueType()),
195 N->getMemoryVT().getVectorElementType(),
196 N->isVolatile(), N->isNonTemporal(),
197 N->getOriginalAlignment());
199 // Legalized the chain result - switch anything that used the old chain to
201 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
206 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
207 EVT DestVT = N->getValueType(0).getVectorElementType();
208 SDValue Op = GetScalarizedVector(N->getOperand(0));
209 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
212 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
213 EVT EltVT = N->getValueType(0).getVectorElementType();
214 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
215 SDValue LHS = GetScalarizedVector(N->getOperand(0));
216 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
217 LHS, DAG.getValueType(ExtVT));
220 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
221 // If the operand is wider than the vector element type then it is implicitly
222 // truncated. Make that explicit here.
223 EVT EltVT = N->getValueType(0).getVectorElementType();
224 SDValue InOp = N->getOperand(0);
225 if (InOp.getValueType() != EltVT)
226 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
230 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
231 SDValue LHS = GetScalarizedVector(N->getOperand(1));
232 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
233 LHS.getValueType(), N->getOperand(0), LHS,
234 GetScalarizedVector(N->getOperand(2)));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
238 SDValue LHS = GetScalarizedVector(N->getOperand(2));
239 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
240 N->getOperand(0), N->getOperand(1),
241 LHS, GetScalarizedVector(N->getOperand(3)),
245 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
246 assert(N->getValueType(0).isVector() ==
247 N->getOperand(0).getValueType().isVector() &&
248 "Scalar/Vector type mismatch");
250 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
252 SDValue LHS = GetScalarizedVector(N->getOperand(0));
253 SDValue RHS = GetScalarizedVector(N->getOperand(1));
254 DebugLoc DL = N->getDebugLoc();
256 // Turn it into a scalar SETCC.
257 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
261 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
264 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
265 // Figure out if the scalar is the LHS or RHS and return it.
266 SDValue Arg = N->getOperand(2).getOperand(0);
267 if (Arg.getOpcode() == ISD::UNDEF)
268 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
269 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
270 return GetScalarizedVector(N->getOperand(Op));
273 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
274 assert(N->getValueType(0).isVector() &&
275 N->getOperand(0).getValueType().isVector() &&
276 "Operand types must be vectors");
278 SDValue LHS = GetScalarizedVector(N->getOperand(0));
279 SDValue RHS = GetScalarizedVector(N->getOperand(1));
280 EVT NVT = N->getValueType(0).getVectorElementType();
281 DebugLoc DL = N->getDebugLoc();
283 // Turn it into a scalar SETCC.
284 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
286 // Vectors may have a different boolean contents to scalars. Promote the
287 // value appropriately.
288 ISD::NodeType ExtendCode =
289 TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
290 return DAG.getNode(ExtendCode, DL, NVT, Res);
294 //===----------------------------------------------------------------------===//
295 // Operand Vector Scalarization <1 x ty> -> ty.
296 //===----------------------------------------------------------------------===//
298 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
302 SDValue Res = SDValue();
304 if (Res.getNode() == 0) {
305 switch (N->getOpcode()) {
308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
312 llvm_unreachable("Do not know how to scalarize this operator's operand!");
314 Res = ScalarizeVecOp_BITCAST(N);
316 case ISD::CONCAT_VECTORS:
317 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
319 case ISD::EXTRACT_VECTOR_ELT:
320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
328 // If the result is null, the sub-method took care of registering results etc.
329 if (!Res.getNode()) return false;
331 // If the result is N, the sub-method updated N in place. Tell the legalizer
333 if (Res.getNode() == N)
336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
337 "Invalid operand expansion");
339 ReplaceValueWith(SDValue(N, 0), Res);
343 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
344 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
345 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
346 SDValue Elt = GetScalarizedVector(N->getOperand(0));
347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
348 N->getValueType(0), Elt);
351 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
352 /// use a BUILD_VECTOR instead.
353 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
354 SmallVector<SDValue, 8> Ops(N->getNumOperands());
355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
356 Ops[i] = GetScalarizedVector(N->getOperand(i));
357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
358 &Ops[0], Ops.size());
361 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
362 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
364 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
365 SDValue Res = GetScalarizedVector(N->getOperand(0));
366 if (Res.getValueType() != N->getValueType(0))
367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
372 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
373 /// scalarized, it must be <1 x ty>. Just store the element.
374 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
375 assert(N->isUnindexed() && "Indexed store of one-element vector?");
376 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
377 DebugLoc dl = N->getDebugLoc();
379 if (N->isTruncatingStore())
380 return DAG.getTruncStore(N->getChain(), dl,
381 GetScalarizedVector(N->getOperand(1)),
382 N->getBasePtr(), N->getPointerInfo(),
383 N->getMemoryVT().getVectorElementType(),
384 N->isVolatile(), N->isNonTemporal(),
387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
388 N->getBasePtr(), N->getPointerInfo(),
389 N->isVolatile(), N->isNonTemporal(),
390 N->getOriginalAlignment());
394 //===----------------------------------------------------------------------===//
395 // Result Vector Splitting
396 //===----------------------------------------------------------------------===//
398 /// SplitVectorResult - This method is called when the specified result of the
399 /// specified node is found to need vector splitting. At this point, the node
400 /// may also have invalid operands or may have other results that need
401 /// legalization, we just know that (at least) one result needs vector
403 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
404 DEBUG(dbgs() << "Split node result: ";
409 switch (N->getOpcode()) {
412 dbgs() << "SplitVectorResult #" << ResNo << ": ";
416 llvm_unreachable("Do not know how to split the result of this operator!");
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
420 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
421 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
422 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
427 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
428 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
430 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
433 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
436 SplitVecRes_SETCC(N, Lo, Hi);
438 case ISD::VECTOR_SHUFFLE:
439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
442 case ISD::ANY_EXTEND:
443 case ISD::CONVERT_RNDSAT:
456 case ISD::FNEARBYINT:
460 case ISD::FP_TO_SINT:
461 case ISD::FP_TO_UINT:
466 case ISD::SIGN_EXTEND:
467 case ISD::SINT_TO_FP:
469 case ISD::UINT_TO_FP:
470 case ISD::ZERO_EXTEND:
471 SplitVecRes_UnaryOp(N, Lo, Hi);
493 SplitVecRes_BinOp(N, Lo, Hi);
497 // If Lo/Hi is null, the sub-method took care of registering results etc.
499 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
502 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
504 SDValue LHSLo, LHSHi;
505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
506 SDValue RHSLo, RHSHi;
507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
508 DebugLoc dl = N->getDebugLoc();
510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
514 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
516 // We know the result is a vector. The input may be either a vector or a
519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
520 DebugLoc dl = N->getDebugLoc();
522 SDValue InOp = N->getOperand(0);
523 EVT InVT = InOp.getValueType();
525 // Handle some special cases efficiently.
526 switch (getTypeAction(InVT)) {
527 case TargetLowering::TypeLegal:
528 case TargetLowering::TypePromoteInteger:
529 case TargetLowering::TypeSoftenFloat:
530 case TargetLowering::TypeScalarizeVector:
531 case TargetLowering::TypeWidenVector:
533 case TargetLowering::TypeExpandInteger:
534 case TargetLowering::TypeExpandFloat:
535 // A scalar to vector conversion, where the scalar needs expansion.
536 // If the vector is being split in two then we can just convert the
539 GetExpandedOp(InOp, Lo, Hi);
540 if (TLI.isBigEndian())
542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
547 case TargetLowering::TypeSplitVector:
548 // If the input is a vector that needs to be split, convert each split
549 // piece of the input now.
550 GetSplitVector(InOp, Lo, Hi);
551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
556 // In the general case, convert the input to an integer and split it by hand.
557 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
558 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
559 if (TLI.isBigEndian())
560 std::swap(LoIntVT, HiIntVT);
562 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
564 if (TLI.isBigEndian())
566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
567 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
570 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
573 DebugLoc dl = N->getDebugLoc();
574 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
575 unsigned LoNumElts = LoVT.getVectorNumElements();
576 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
579 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
583 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
585 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
586 DebugLoc dl = N->getDebugLoc();
587 unsigned NumSubvectors = N->getNumOperands() / 2;
588 if (NumSubvectors == 1) {
589 Lo = N->getOperand(0);
590 Hi = N->getOperand(1);
595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
597 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
600 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
604 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
606 SDValue Vec = N->getOperand(0);
607 SDValue Idx = N->getOperand(1);
608 DebugLoc dl = N->getDebugLoc();
611 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
614 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
616 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
619 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
621 DebugLoc dl = N->getDebugLoc();
622 GetSplitVector(N->getOperand(0), Lo, Hi);
623 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
624 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
627 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
629 SDValue LHSLo, LHSHi;
630 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
631 DebugLoc dl = N->getDebugLoc();
634 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
636 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
637 DAG.getValueType(LoVT));
638 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
639 DAG.getValueType(HiVT));
642 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
644 SDValue Vec = N->getOperand(0);
645 SDValue Elt = N->getOperand(1);
646 SDValue Idx = N->getOperand(2);
647 DebugLoc dl = N->getDebugLoc();
648 GetSplitVector(Vec, Lo, Hi);
650 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
651 unsigned IdxVal = CIdx->getZExtValue();
652 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
653 if (IdxVal < LoNumElts)
654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
655 Lo.getValueType(), Lo, Elt, Idx);
657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
658 DAG.getIntPtrConstant(IdxVal - LoNumElts));
662 // Spill the vector to the stack.
663 EVT VecVT = Vec.getValueType();
664 EVT EltVT = VecVT.getVectorElementType();
665 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
667 MachinePointerInfo(), false, false, 0);
669 // Store the new element. This may be larger than the vector element type,
670 // so use a truncating store.
671 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
672 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
674 TLI.getTargetData()->getPrefTypeAlignment(VecType);
675 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
678 // Load the Lo part from the stack slot.
679 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
682 // Increment the pointer to the other part.
683 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
684 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
685 DAG.getIntPtrConstant(IncrementSize));
687 // Load the Hi part from the stack slot.
688 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
689 false, false, MinAlign(Alignment, IncrementSize));
692 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
695 DebugLoc dl = N->getDebugLoc();
696 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
697 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
698 Hi = DAG.getUNDEF(HiVT);
701 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
703 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
705 DebugLoc dl = LD->getDebugLoc();
706 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
708 ISD::LoadExtType ExtType = LD->getExtensionType();
709 SDValue Ch = LD->getChain();
710 SDValue Ptr = LD->getBasePtr();
711 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
712 EVT MemoryVT = LD->getMemoryVT();
713 unsigned Alignment = LD->getOriginalAlignment();
714 bool isVolatile = LD->isVolatile();
715 bool isNonTemporal = LD->isNonTemporal();
717 EVT LoMemVT, HiMemVT;
718 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
721 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
724 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
726 DAG.getIntPtrConstant(IncrementSize));
727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
728 LD->getPointerInfo().getWithOffset(IncrementSize),
729 HiMemVT, isVolatile, isNonTemporal, Alignment);
731 // Build a factor node to remember that this load is independent of the
733 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
736 // Legalized the chain result - switch anything that used the old chain to
738 ReplaceValueWith(SDValue(LD, 1), Ch);
741 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
742 assert(N->getValueType(0).isVector() &&
743 N->getOperand(0).getValueType().isVector() &&
744 "Operand types must be vectors");
747 DebugLoc DL = N->getDebugLoc();
748 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
751 EVT InVT = N->getOperand(0).getValueType();
752 SDValue LL, LH, RL, RH;
753 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
754 LoVT.getVectorNumElements());
755 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
756 DAG.getIntPtrConstant(0));
757 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
758 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
760 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
761 DAG.getIntPtrConstant(0));
762 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
763 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
765 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
766 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
769 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
771 // Get the dest types - they may not match the input types, e.g. int_to_fp.
773 DebugLoc dl = N->getDebugLoc();
774 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
777 EVT InVT = N->getOperand(0).getValueType();
778 switch (getTypeAction(InVT)) {
779 default: llvm_unreachable("Unexpected type action!");
780 case TargetLowering::TypeLegal: {
781 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
782 LoVT.getVectorNumElements());
783 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
784 DAG.getIntPtrConstant(0));
785 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
786 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
789 case TargetLowering::TypePromoteInteger: {
790 SDValue InOp = GetPromotedInteger(N->getOperand(0));
791 EVT InNVT = EVT::getVectorVT(*DAG.getContext(),
792 InOp.getValueType().getVectorElementType(),
793 LoVT.getVectorNumElements());
794 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
795 DAG.getIntPtrConstant(0));
796 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
797 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
800 case TargetLowering::TypeSplitVector:
801 GetSplitVector(N->getOperand(0), Lo, Hi);
803 case TargetLowering::TypeWidenVector: {
804 // If the result needs to be split and the input needs to be widened,
805 // the two types must have different lengths. Use the widened result
806 // and extract from it to do the split.
807 SDValue InOp = GetWidenedVector(N->getOperand(0));
808 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
809 LoVT.getVectorNumElements());
810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
811 DAG.getIntPtrConstant(0));
812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
813 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
818 if (N->getOpcode() == ISD::FP_ROUND) {
819 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
820 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
821 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
822 SDValue DTyOpLo = DAG.getValueType(LoVT);
823 SDValue DTyOpHi = DAG.getValueType(HiVT);
824 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
825 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
826 SDValue RndOp = N->getOperand(3);
827 SDValue SatOp = N->getOperand(4);
828 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
829 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
831 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
834 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
835 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
839 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
840 SDValue &Lo, SDValue &Hi) {
841 // The low and high parts of the original input give four input vectors.
843 DebugLoc dl = N->getDebugLoc();
844 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
845 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
846 EVT NewVT = Inputs[0].getValueType();
847 unsigned NewElts = NewVT.getVectorNumElements();
849 // If Lo or Hi uses elements from at most two of the four input vectors, then
850 // express it as a vector shuffle of those two inputs. Otherwise extract the
851 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
852 SmallVector<int, 16> Ops;
853 for (unsigned High = 0; High < 2; ++High) {
854 SDValue &Output = High ? Hi : Lo;
856 // Build a shuffle mask for the output, discovering on the fly which
857 // input vectors to use as shuffle operands (recorded in InputUsed).
858 // If building a suitable shuffle vector proves too hard, then bail
859 // out with useBuildVector set.
860 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
861 unsigned FirstMaskIdx = High * NewElts;
862 bool useBuildVector = false;
863 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
864 // The mask element. This indexes into the input.
865 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
867 // The input vector this mask element indexes into.
868 unsigned Input = (unsigned)Idx / NewElts;
870 if (Input >= array_lengthof(Inputs)) {
871 // The mask element does not index into any input vector.
876 // Turn the index into an offset from the start of the input vector.
877 Idx -= Input * NewElts;
879 // Find or create a shuffle vector operand to hold this input.
881 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
882 if (InputUsed[OpNo] == Input) {
883 // This input vector is already an operand.
885 } else if (InputUsed[OpNo] == -1U) {
886 // Create a new operand for this input vector.
887 InputUsed[OpNo] = Input;
892 if (OpNo >= array_lengthof(InputUsed)) {
893 // More than two input vectors used! Give up on trying to create a
894 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
895 useBuildVector = true;
899 // Add the mask index for the new shuffle vector.
900 Ops.push_back(Idx + OpNo * NewElts);
903 if (useBuildVector) {
904 EVT EltVT = NewVT.getVectorElementType();
905 SmallVector<SDValue, 16> SVOps;
907 // Extract the input elements by hand.
908 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
909 // The mask element. This indexes into the input.
910 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
912 // The input vector this mask element indexes into.
913 unsigned Input = (unsigned)Idx / NewElts;
915 if (Input >= array_lengthof(Inputs)) {
916 // The mask element is "undef" or indexes off the end of the input.
917 SVOps.push_back(DAG.getUNDEF(EltVT));
921 // Turn the index into an offset from the start of the input vector.
922 Idx -= Input * NewElts;
924 // Extract the vector element by hand.
925 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
926 Inputs[Input], DAG.getIntPtrConstant(Idx)));
929 // Construct the Lo/Hi output using a BUILD_VECTOR.
930 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
931 } else if (InputUsed[0] == -1U) {
932 // No input vectors were used! The result is undefined.
933 Output = DAG.getUNDEF(NewVT);
935 SDValue Op0 = Inputs[InputUsed[0]];
936 // If only one input was used, use an undefined vector for the other.
937 SDValue Op1 = InputUsed[1] == -1U ?
938 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
939 // At least one input vector was used. Create a new shuffle vector.
940 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
948 //===----------------------------------------------------------------------===//
949 // Operand Vector Splitting
950 //===----------------------------------------------------------------------===//
952 /// SplitVectorOperand - This method is called when the specified operand of the
953 /// specified node is found to need vector splitting. At this point, all of the
954 /// result types of the node are known to be legal, but other operands of the
955 /// node may need legalization as well as the specified one.
956 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
957 DEBUG(dbgs() << "Split node operand: ";
960 SDValue Res = SDValue();
962 if (Res.getNode() == 0) {
963 switch (N->getOpcode()) {
966 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
970 llvm_unreachable("Do not know how to split this operator's operand!");
971 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
972 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
973 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
974 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
975 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
976 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
978 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
985 case ISD::FP_TO_SINT:
986 case ISD::FP_TO_UINT:
987 case ISD::SINT_TO_FP:
988 case ISD::UINT_TO_FP:
991 case ISD::SIGN_EXTEND:
992 case ISD::ZERO_EXTEND:
993 case ISD::ANY_EXTEND:
994 Res = SplitVecOp_UnaryOp(N);
999 // If the result is null, the sub-method took care of registering results etc.
1000 if (!Res.getNode()) return false;
1002 // If the result is N, the sub-method updated N in place. Tell the legalizer
1004 if (Res.getNode() == N)
1007 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1008 "Invalid operand expansion");
1010 ReplaceValueWith(SDValue(N, 0), Res);
1014 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1015 // The result has a legal vector type, but the input needs splitting.
1016 EVT ResVT = N->getValueType(0);
1018 DebugLoc dl = N->getDebugLoc();
1019 GetSplitVector(N->getOperand(0), Lo, Hi);
1020 EVT InVT = Lo.getValueType();
1022 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1023 InVT.getVectorNumElements());
1025 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1026 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1028 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1031 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1032 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1033 // end up being split all the way down to individual components. Convert the
1034 // split pieces into integers and reassemble.
1036 GetSplitVector(N->getOperand(0), Lo, Hi);
1037 Lo = BitConvertToInteger(Lo);
1038 Hi = BitConvertToInteger(Hi);
1040 if (TLI.isBigEndian())
1043 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1044 JoinIntegers(Lo, Hi));
1047 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1048 // We know that the extracted result type is legal.
1049 EVT SubVT = N->getValueType(0);
1050 SDValue Idx = N->getOperand(1);
1051 DebugLoc dl = N->getDebugLoc();
1053 GetSplitVector(N->getOperand(0), Lo, Hi);
1055 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1056 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1058 if (IdxVal < LoElts) {
1059 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1060 "Extracted subvector crosses vector split!");
1061 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1063 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1064 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1068 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1069 SDValue Vec = N->getOperand(0);
1070 SDValue Idx = N->getOperand(1);
1071 EVT VecVT = Vec.getValueType();
1073 if (isa<ConstantSDNode>(Idx)) {
1074 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1075 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1078 GetSplitVector(Vec, Lo, Hi);
1080 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1082 if (IdxVal < LoElts)
1083 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1084 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1085 DAG.getConstant(IdxVal - LoElts,
1086 Idx.getValueType())), 0);
1089 // Store the vector to the stack.
1090 EVT EltVT = VecVT.getVectorElementType();
1091 DebugLoc dl = N->getDebugLoc();
1092 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1093 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1094 MachinePointerInfo(), false, false, 0);
1096 // Load back the required element.
1097 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1098 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1099 MachinePointerInfo(), EltVT, false, false, 0);
1102 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1103 assert(N->isUnindexed() && "Indexed store of vector?");
1104 assert(OpNo == 1 && "Can only split the stored value");
1105 DebugLoc DL = N->getDebugLoc();
1107 bool isTruncating = N->isTruncatingStore();
1108 SDValue Ch = N->getChain();
1109 SDValue Ptr = N->getBasePtr();
1110 EVT MemoryVT = N->getMemoryVT();
1111 unsigned Alignment = N->getOriginalAlignment();
1112 bool isVol = N->isVolatile();
1113 bool isNT = N->isNonTemporal();
1115 GetSplitVector(N->getOperand(1), Lo, Hi);
1117 EVT LoMemVT, HiMemVT;
1118 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1120 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1123 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1124 LoMemVT, isVol, isNT, Alignment);
1126 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1127 isVol, isNT, Alignment);
1129 // Increment the pointer to the other half.
1130 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1131 DAG.getIntPtrConstant(IncrementSize));
1134 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1135 N->getPointerInfo().getWithOffset(IncrementSize),
1136 HiMemVT, isVol, isNT, Alignment);
1138 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1139 N->getPointerInfo().getWithOffset(IncrementSize),
1140 isVol, isNT, Alignment);
1142 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1145 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1146 DebugLoc DL = N->getDebugLoc();
1148 // The input operands all must have the same type, and we know the result the
1149 // result type is valid. Convert this to a buildvector which extracts all the
1151 // TODO: If the input elements are power-two vectors, we could convert this to
1152 // a new CONCAT_VECTORS node with elements that are half-wide.
1153 SmallVector<SDValue, 32> Elts;
1154 EVT EltVT = N->getValueType(0).getVectorElementType();
1155 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1156 SDValue Op = N->getOperand(op);
1157 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1159 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1160 Op, DAG.getIntPtrConstant(i)));
1165 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1166 &Elts[0], Elts.size());
1169 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1170 assert(N->getValueType(0).isVector() &&
1171 N->getOperand(0).getValueType().isVector() &&
1172 "Operand types must be vectors");
1173 // The result has a legal vector type, but the input needs splitting.
1174 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1175 DebugLoc DL = N->getDebugLoc();
1176 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1177 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1178 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1179 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1180 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1182 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1183 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1184 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1185 return PromoteTargetBoolean(Con, N->getValueType(0));
1189 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1190 // The result has a legal vector type, but the input needs splitting.
1191 EVT ResVT = N->getValueType(0);
1193 DebugLoc DL = N->getDebugLoc();
1194 GetSplitVector(N->getOperand(0), Lo, Hi);
1195 EVT InVT = Lo.getValueType();
1197 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1198 InVT.getVectorNumElements());
1200 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1201 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1203 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1208 //===----------------------------------------------------------------------===//
1209 // Result Vector Widening
1210 //===----------------------------------------------------------------------===//
1212 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1213 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1217 // See if the target wants to custom widen this node.
1218 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1221 SDValue Res = SDValue();
1222 switch (N->getOpcode()) {
1225 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1229 llvm_unreachable("Do not know how to widen the result of this operator!");
1231 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1232 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1233 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1234 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1235 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1236 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1237 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1238 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1239 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1240 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1241 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1242 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1243 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1244 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1245 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1246 case ISD::VECTOR_SHUFFLE:
1247 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1253 case ISD::FCOPYSIGN:
1269 Res = WidenVecRes_Binary(N);
1273 Res = WidenVecRes_POWI(N);
1279 Res = WidenVecRes_Shift(N);
1282 case ISD::ANY_EXTEND:
1283 case ISD::FP_EXTEND:
1285 case ISD::FP_TO_SINT:
1286 case ISD::FP_TO_UINT:
1287 case ISD::SIGN_EXTEND:
1288 case ISD::SINT_TO_FP:
1290 case ISD::UINT_TO_FP:
1291 case ISD::ZERO_EXTEND:
1292 Res = WidenVecRes_Convert(N);
1307 case ISD::FNEARBYINT:
1313 Res = WidenVecRes_Unary(N);
1317 // If Res is null, the sub-method took care of registering the result.
1319 SetWidenedVector(SDValue(N, ResNo), Res);
1322 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1323 // Binary op widening.
1324 unsigned Opcode = N->getOpcode();
1325 DebugLoc dl = N->getDebugLoc();
1326 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1327 EVT WidenEltVT = WidenVT.getVectorElementType();
1329 unsigned NumElts = VT.getVectorNumElements();
1330 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1331 NumElts = NumElts / 2;
1332 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1335 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1336 // Operation doesn't trap so just widen as normal.
1337 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1338 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1339 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1342 // No legal vector version so unroll the vector operation and then widen.
1344 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1346 // Since the operation can trap, apply operation on the original vector.
1348 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1349 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1350 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1352 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1353 unsigned ConcatEnd = 0; // Current ConcatOps index.
1354 int Idx = 0; // Current Idx into input vectors.
1356 // NumElts := greatest legal vector size (at most WidenVT)
1357 // while (orig. vector has unhandled elements) {
1358 // take munches of size NumElts from the beginning and add to ConcatOps
1359 // NumElts := next smaller supported vector size or 1
1361 while (CurNumElts != 0) {
1362 while (CurNumElts >= NumElts) {
1363 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1364 DAG.getIntPtrConstant(Idx));
1365 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1366 DAG.getIntPtrConstant(Idx));
1367 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1369 CurNumElts -= NumElts;
1372 NumElts = NumElts / 2;
1373 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1374 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1377 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1378 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1379 InOp1, DAG.getIntPtrConstant(Idx));
1380 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1381 InOp2, DAG.getIntPtrConstant(Idx));
1382 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1389 // Check to see if we have a single operation with the widen type.
1390 if (ConcatEnd == 1) {
1391 VT = ConcatOps[0].getValueType();
1393 return ConcatOps[0];
1396 // while (Some element of ConcatOps is not of type MaxVT) {
1397 // From the end of ConcatOps, collect elements of the same type and put
1398 // them into an op of the next larger supported type
1400 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1401 Idx = ConcatEnd - 1;
1402 VT = ConcatOps[Idx--].getValueType();
1403 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1406 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1410 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1411 } while (!TLI.isTypeLegal(NextVT));
1413 if (!VT.isVector()) {
1414 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1415 SDValue VecOp = DAG.getUNDEF(NextVT);
1416 unsigned NumToInsert = ConcatEnd - Idx - 1;
1417 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1418 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1419 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1421 ConcatOps[Idx+1] = VecOp;
1422 ConcatEnd = Idx + 2;
1424 // Vector type, create a CONCAT_VECTORS of type NextVT
1425 SDValue undefVec = DAG.getUNDEF(VT);
1426 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1427 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1428 unsigned RealVals = ConcatEnd - Idx - 1;
1429 unsigned SubConcatEnd = 0;
1430 unsigned SubConcatIdx = Idx + 1;
1431 while (SubConcatEnd < RealVals)
1432 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1433 while (SubConcatEnd < OpsToConcat)
1434 SubConcatOps[SubConcatEnd++] = undefVec;
1435 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1436 NextVT, &SubConcatOps[0],
1438 ConcatEnd = SubConcatIdx + 1;
1442 // Check to see if we have a single operation with the widen type.
1443 if (ConcatEnd == 1) {
1444 VT = ConcatOps[0].getValueType();
1446 return ConcatOps[0];
1449 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1450 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1451 if (NumOps != ConcatEnd ) {
1452 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1453 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1454 ConcatOps[j] = UndefVal;
1456 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1459 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1460 SDValue InOp = N->getOperand(0);
1461 DebugLoc DL = N->getDebugLoc();
1463 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1464 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1466 EVT InVT = InOp.getValueType();
1467 EVT InEltVT = InVT.getVectorElementType();
1468 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1470 unsigned Opcode = N->getOpcode();
1471 unsigned InVTNumElts = InVT.getVectorNumElements();
1473 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1474 InOp = GetWidenedVector(N->getOperand(0));
1475 InVT = InOp.getValueType();
1476 InVTNumElts = InVT.getVectorNumElements();
1477 if (InVTNumElts == WidenNumElts) {
1478 if (N->getNumOperands() == 1)
1479 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1480 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1484 if (TLI.isTypeLegal(InWidenVT)) {
1485 // Because the result and the input are different vector types, widening
1486 // the result could create a legal type but widening the input might make
1487 // it an illegal type that might lead to repeatedly splitting the input
1488 // and then widening it. To avoid this, we widen the input only if
1489 // it results in a legal type.
1490 if (WidenNumElts % InVTNumElts == 0) {
1491 // Widen the input and call convert on the widened input vector.
1492 unsigned NumConcat = WidenNumElts/InVTNumElts;
1493 SmallVector<SDValue, 16> Ops(NumConcat);
1495 SDValue UndefVal = DAG.getUNDEF(InVT);
1496 for (unsigned i = 1; i != NumConcat; ++i)
1498 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1499 &Ops[0], NumConcat);
1500 if (N->getNumOperands() == 1)
1501 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1502 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1505 if (InVTNumElts % WidenNumElts == 0) {
1506 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1507 InOp, DAG.getIntPtrConstant(0));
1508 // Extract the input and convert the shorten input vector.
1509 if (N->getNumOperands() == 1)
1510 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1511 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1515 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1516 SmallVector<SDValue, 16> Ops(WidenNumElts);
1517 EVT EltVT = WidenVT.getVectorElementType();
1518 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1520 for (i=0; i < MinElts; ++i) {
1521 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1522 DAG.getIntPtrConstant(i));
1523 if (N->getNumOperands() == 1)
1524 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1526 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1529 SDValue UndefVal = DAG.getUNDEF(EltVT);
1530 for (; i < WidenNumElts; ++i)
1533 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1536 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1537 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1538 SDValue InOp = GetWidenedVector(N->getOperand(0));
1539 SDValue ShOp = N->getOperand(1);
1540 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1543 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1545 SDValue InOp = GetWidenedVector(N->getOperand(0));
1546 SDValue ShOp = N->getOperand(1);
1548 EVT ShVT = ShOp.getValueType();
1549 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1550 ShOp = GetWidenedVector(ShOp);
1551 ShVT = ShOp.getValueType();
1553 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1554 ShVT.getVectorElementType(),
1555 WidenVT.getVectorNumElements());
1556 if (ShVT != ShWidenVT)
1557 ShOp = ModifyToType(ShOp, ShWidenVT);
1559 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1562 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1563 // Unary op widening.
1564 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1565 SDValue InOp = GetWidenedVector(N->getOperand(0));
1566 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1569 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1570 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1571 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1572 cast<VTSDNode>(N->getOperand(1))->getVT()
1573 .getVectorElementType(),
1574 WidenVT.getVectorNumElements());
1575 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1576 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1577 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1580 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
1581 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
1582 return GetWidenedVector(WidenVec);
1585 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1586 SDValue InOp = N->getOperand(0);
1587 EVT InVT = InOp.getValueType();
1588 EVT VT = N->getValueType(0);
1589 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1590 DebugLoc dl = N->getDebugLoc();
1592 switch (getTypeAction(InVT)) {
1594 assert(false && "Unknown type action!");
1596 case TargetLowering::TypeLegal:
1598 case TargetLowering::TypePromoteInteger:
1599 // If the InOp is promoted to the same size, convert it. Otherwise,
1600 // fall out of the switch and widen the promoted input.
1601 InOp = GetPromotedInteger(InOp);
1602 InVT = InOp.getValueType();
1603 if (WidenVT.bitsEq(InVT))
1604 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1606 case TargetLowering::TypeSoftenFloat:
1607 case TargetLowering::TypeExpandInteger:
1608 case TargetLowering::TypeExpandFloat:
1609 case TargetLowering::TypeScalarizeVector:
1610 case TargetLowering::TypeSplitVector:
1612 case TargetLowering::TypeWidenVector:
1613 // If the InOp is widened to the same size, convert it. Otherwise, fall
1614 // out of the switch and widen the widened input.
1615 InOp = GetWidenedVector(InOp);
1616 InVT = InOp.getValueType();
1617 if (WidenVT.bitsEq(InVT))
1618 // The input widens to the same size. Convert to the widen value.
1619 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1623 unsigned WidenSize = WidenVT.getSizeInBits();
1624 unsigned InSize = InVT.getSizeInBits();
1625 // x86mmx is not an acceptable vector element type, so don't try.
1626 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1627 // Determine new input vector type. The new input vector type will use
1628 // the same element type (if its a vector) or use the input type as a
1629 // vector. It is the same size as the type to widen to.
1631 unsigned NewNumElts = WidenSize / InSize;
1632 if (InVT.isVector()) {
1633 EVT InEltVT = InVT.getVectorElementType();
1634 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1635 WidenSize / InEltVT.getSizeInBits());
1637 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1640 if (TLI.isTypeLegal(NewInVT)) {
1641 // Because the result and the input are different vector types, widening
1642 // the result could create a legal type but widening the input might make
1643 // it an illegal type that might lead to repeatedly splitting the input
1644 // and then widening it. To avoid this, we widen the input only if
1645 // it results in a legal type.
1646 SmallVector<SDValue, 16> Ops(NewNumElts);
1647 SDValue UndefVal = DAG.getUNDEF(InVT);
1649 for (unsigned i = 1; i < NewNumElts; ++i)
1653 if (InVT.isVector())
1654 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1655 NewInVT, &Ops[0], NewNumElts);
1657 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1658 NewInVT, &Ops[0], NewNumElts);
1659 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1663 return CreateStackStoreLoad(InOp, WidenVT);
1666 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1667 DebugLoc dl = N->getDebugLoc();
1668 // Build a vector with undefined for the new nodes.
1669 EVT VT = N->getValueType(0);
1670 EVT EltVT = VT.getVectorElementType();
1671 unsigned NumElts = VT.getVectorNumElements();
1673 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1674 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1676 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1677 NewOps.reserve(WidenNumElts);
1678 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1679 NewOps.push_back(DAG.getUNDEF(EltVT));
1681 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1684 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1685 EVT InVT = N->getOperand(0).getValueType();
1686 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1687 DebugLoc dl = N->getDebugLoc();
1688 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1689 unsigned NumInElts = InVT.getVectorNumElements();
1690 unsigned NumOperands = N->getNumOperands();
1692 bool InputWidened = false; // Indicates we need to widen the input.
1693 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1694 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1695 // Add undef vectors to widen to correct length.
1696 unsigned NumConcat = WidenVT.getVectorNumElements() /
1697 InVT.getVectorNumElements();
1698 SDValue UndefVal = DAG.getUNDEF(InVT);
1699 SmallVector<SDValue, 16> Ops(NumConcat);
1700 for (unsigned i=0; i < NumOperands; ++i)
1701 Ops[i] = N->getOperand(i);
1702 for (unsigned i = NumOperands; i != NumConcat; ++i)
1704 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1707 InputWidened = true;
1708 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1709 // The inputs and the result are widen to the same value.
1711 for (i=1; i < NumOperands; ++i)
1712 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1715 if (i == NumOperands)
1716 // Everything but the first operand is an UNDEF so just return the
1717 // widened first operand.
1718 return GetWidenedVector(N->getOperand(0));
1720 if (NumOperands == 2) {
1721 // Replace concat of two operands with a shuffle.
1722 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1723 for (unsigned i = 0; i < NumInElts; ++i) {
1725 MaskOps[i + NumInElts] = i + WidenNumElts;
1727 return DAG.getVectorShuffle(WidenVT, dl,
1728 GetWidenedVector(N->getOperand(0)),
1729 GetWidenedVector(N->getOperand(1)),
1735 // Fall back to use extracts and build vector.
1736 EVT EltVT = WidenVT.getVectorElementType();
1737 SmallVector<SDValue, 16> Ops(WidenNumElts);
1739 for (unsigned i=0; i < NumOperands; ++i) {
1740 SDValue InOp = N->getOperand(i);
1742 InOp = GetWidenedVector(InOp);
1743 for (unsigned j=0; j < NumInElts; ++j)
1744 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1745 DAG.getIntPtrConstant(j));
1747 SDValue UndefVal = DAG.getUNDEF(EltVT);
1748 for (; Idx < WidenNumElts; ++Idx)
1749 Ops[Idx] = UndefVal;
1750 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1753 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1754 DebugLoc dl = N->getDebugLoc();
1755 SDValue InOp = N->getOperand(0);
1756 SDValue RndOp = N->getOperand(3);
1757 SDValue SatOp = N->getOperand(4);
1759 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1760 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1762 EVT InVT = InOp.getValueType();
1763 EVT InEltVT = InVT.getVectorElementType();
1764 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1766 SDValue DTyOp = DAG.getValueType(WidenVT);
1767 SDValue STyOp = DAG.getValueType(InWidenVT);
1768 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1770 unsigned InVTNumElts = InVT.getVectorNumElements();
1771 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1772 InOp = GetWidenedVector(InOp);
1773 InVT = InOp.getValueType();
1774 InVTNumElts = InVT.getVectorNumElements();
1775 if (InVTNumElts == WidenNumElts)
1776 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1780 if (TLI.isTypeLegal(InWidenVT)) {
1781 // Because the result and the input are different vector types, widening
1782 // the result could create a legal type but widening the input might make
1783 // it an illegal type that might lead to repeatedly splitting the input
1784 // and then widening it. To avoid this, we widen the input only if
1785 // it results in a legal type.
1786 if (WidenNumElts % InVTNumElts == 0) {
1787 // Widen the input and call convert on the widened input vector.
1788 unsigned NumConcat = WidenNumElts/InVTNumElts;
1789 SmallVector<SDValue, 16> Ops(NumConcat);
1791 SDValue UndefVal = DAG.getUNDEF(InVT);
1792 for (unsigned i = 1; i != NumConcat; ++i)
1795 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1796 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1800 if (InVTNumElts % WidenNumElts == 0) {
1801 // Extract the input and convert the shorten input vector.
1802 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1803 DAG.getIntPtrConstant(0));
1804 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1809 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1810 SmallVector<SDValue, 16> Ops(WidenNumElts);
1811 EVT EltVT = WidenVT.getVectorElementType();
1812 DTyOp = DAG.getValueType(EltVT);
1813 STyOp = DAG.getValueType(InEltVT);
1815 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1817 for (i=0; i < MinElts; ++i) {
1818 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1819 DAG.getIntPtrConstant(i));
1820 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1824 SDValue UndefVal = DAG.getUNDEF(EltVT);
1825 for (; i < WidenNumElts; ++i)
1828 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1831 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1832 EVT VT = N->getValueType(0);
1833 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1834 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1835 SDValue InOp = N->getOperand(0);
1836 SDValue Idx = N->getOperand(1);
1837 DebugLoc dl = N->getDebugLoc();
1839 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1840 InOp = GetWidenedVector(InOp);
1842 EVT InVT = InOp.getValueType();
1844 // Check if we can just return the input vector after widening.
1845 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1846 if (IdxVal == 0 && InVT == WidenVT)
1849 // Check if we can extract from the vector.
1850 unsigned InNumElts = InVT.getVectorNumElements();
1851 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1852 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1854 // We could try widening the input to the right length but for now, extract
1855 // the original elements, fill the rest with undefs and build a vector.
1856 SmallVector<SDValue, 16> Ops(WidenNumElts);
1857 EVT EltVT = VT.getVectorElementType();
1858 unsigned NumElts = VT.getVectorNumElements();
1860 for (i=0; i < NumElts; ++i)
1861 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1862 DAG.getIntPtrConstant(IdxVal+i));
1864 SDValue UndefVal = DAG.getUNDEF(EltVT);
1865 for (; i < WidenNumElts; ++i)
1867 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1870 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1871 SDValue InOp = GetWidenedVector(N->getOperand(0));
1872 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1873 InOp.getValueType(), InOp,
1874 N->getOperand(1), N->getOperand(2));
1877 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1878 LoadSDNode *LD = cast<LoadSDNode>(N);
1879 ISD::LoadExtType ExtType = LD->getExtensionType();
1882 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1883 if (ExtType != ISD::NON_EXTLOAD)
1884 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1886 Result = GenWidenVectorLoads(LdChain, LD);
1888 // If we generate a single load, we can use that for the chain. Otherwise,
1889 // build a factor node to remember the multiple loads are independent and
1892 if (LdChain.size() == 1)
1893 NewChain = LdChain[0];
1895 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1896 &LdChain[0], LdChain.size());
1898 // Modified the chain - switch anything that used the old chain to use
1900 ReplaceValueWith(SDValue(N, 1), NewChain);
1905 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1906 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1907 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1908 WidenVT, N->getOperand(0));
1911 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1912 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1913 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1915 SDValue Cond1 = N->getOperand(0);
1916 EVT CondVT = Cond1.getValueType();
1917 if (CondVT.isVector()) {
1918 EVT CondEltVT = CondVT.getVectorElementType();
1919 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1920 CondEltVT, WidenNumElts);
1921 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
1922 Cond1 = GetWidenedVector(Cond1);
1924 if (Cond1.getValueType() != CondWidenVT)
1925 Cond1 = ModifyToType(Cond1, CondWidenVT);
1928 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1929 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1930 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1931 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1932 WidenVT, Cond1, InOp1, InOp2);
1935 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1936 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1937 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1938 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1939 InOp1.getValueType(), N->getOperand(0),
1940 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1943 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1944 assert(N->getValueType(0).isVector() ==
1945 N->getOperand(0).getValueType().isVector() &&
1946 "Scalar/Vector type mismatch");
1947 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
1949 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1950 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1951 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1952 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1953 InOp1, InOp2, N->getOperand(2));
1956 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1957 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1958 return DAG.getUNDEF(WidenVT);
1961 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1962 EVT VT = N->getValueType(0);
1963 DebugLoc dl = N->getDebugLoc();
1965 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1966 unsigned NumElts = VT.getVectorNumElements();
1967 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1969 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1970 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1972 // Adjust mask based on new input vector length.
1973 SmallVector<int, 16> NewMask;
1974 for (unsigned i = 0; i != NumElts; ++i) {
1975 int Idx = N->getMaskElt(i);
1976 if (Idx < (int)NumElts)
1977 NewMask.push_back(Idx);
1979 NewMask.push_back(Idx - NumElts + WidenNumElts);
1981 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1982 NewMask.push_back(-1);
1983 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1986 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1987 assert(N->getValueType(0).isVector() &&
1988 N->getOperand(0).getValueType().isVector() &&
1989 "Operands must be vectors");
1990 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1991 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1993 SDValue InOp1 = N->getOperand(0);
1994 EVT InVT = InOp1.getValueType();
1995 assert(InVT.isVector() && "can not widen non vector type");
1996 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
1997 InVT.getVectorElementType(), WidenNumElts);
1998 InOp1 = GetWidenedVector(InOp1);
1999 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2001 // Assume that the input and output will be widen appropriately. If not,
2002 // we will have to unroll it at some point.
2003 assert(InOp1.getValueType() == WidenInVT &&
2004 InOp2.getValueType() == WidenInVT &&
2005 "Input not widened to expected type!");
2007 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2008 WidenVT, InOp1, InOp2, N->getOperand(2));
2012 //===----------------------------------------------------------------------===//
2013 // Widen Vector Operand
2014 //===----------------------------------------------------------------------===//
2015 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
2016 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
2019 SDValue Res = SDValue();
2021 switch (N->getOpcode()) {
2024 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
2028 llvm_unreachable("Do not know how to widen this operator's operand!");
2030 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2031 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2032 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2033 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2034 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2036 case ISD::FP_EXTEND:
2037 case ISD::FP_TO_SINT:
2038 case ISD::FP_TO_UINT:
2039 case ISD::SINT_TO_FP:
2040 case ISD::UINT_TO_FP:
2042 case ISD::SIGN_EXTEND:
2043 case ISD::ZERO_EXTEND:
2044 case ISD::ANY_EXTEND:
2045 Res = WidenVecOp_Convert(N);
2049 // If Res is null, the sub-method took care of registering the result.
2050 if (!Res.getNode()) return false;
2052 // If the result is N, the sub-method updated N in place. Tell the legalizer
2054 if (Res.getNode() == N)
2058 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2059 "Invalid operand expansion");
2061 ReplaceValueWith(SDValue(N, 0), Res);
2065 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2066 // Since the result is legal and the input is illegal, it is unlikely
2067 // that we can fix the input to a legal type so unroll the convert
2068 // into some scalar code and create a nasty build vector.
2069 EVT VT = N->getValueType(0);
2070 EVT EltVT = VT.getVectorElementType();
2071 DebugLoc dl = N->getDebugLoc();
2072 unsigned NumElts = VT.getVectorNumElements();
2073 SDValue InOp = N->getOperand(0);
2074 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2075 InOp = GetWidenedVector(InOp);
2076 EVT InVT = InOp.getValueType();
2077 EVT InEltVT = InVT.getVectorElementType();
2079 unsigned Opcode = N->getOpcode();
2080 SmallVector<SDValue, 16> Ops(NumElts);
2081 for (unsigned i=0; i < NumElts; ++i)
2082 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2083 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2084 DAG.getIntPtrConstant(i)));
2086 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2089 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2090 EVT VT = N->getValueType(0);
2091 SDValue InOp = GetWidenedVector(N->getOperand(0));
2092 EVT InWidenVT = InOp.getValueType();
2093 DebugLoc dl = N->getDebugLoc();
2095 // Check if we can convert between two legal vector types and extract.
2096 unsigned InWidenSize = InWidenVT.getSizeInBits();
2097 unsigned Size = VT.getSizeInBits();
2098 // x86mmx is not an acceptable vector element type, so don't try.
2099 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2100 unsigned NewNumElts = InWidenSize / Size;
2101 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2102 if (TLI.isTypeLegal(NewVT)) {
2103 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2104 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2105 DAG.getIntPtrConstant(0));
2109 return CreateStackStoreLoad(InOp, VT);
2112 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2113 // If the input vector is not legal, it is likely that we will not find a
2114 // legal vector of the same size. Replace the concatenate vector with a
2115 // nasty build vector.
2116 EVT VT = N->getValueType(0);
2117 EVT EltVT = VT.getVectorElementType();
2118 DebugLoc dl = N->getDebugLoc();
2119 unsigned NumElts = VT.getVectorNumElements();
2120 SmallVector<SDValue, 16> Ops(NumElts);
2122 EVT InVT = N->getOperand(0).getValueType();
2123 unsigned NumInElts = InVT.getVectorNumElements();
2126 unsigned NumOperands = N->getNumOperands();
2127 for (unsigned i=0; i < NumOperands; ++i) {
2128 SDValue InOp = N->getOperand(i);
2129 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2130 InOp = GetWidenedVector(InOp);
2131 for (unsigned j=0; j < NumInElts; ++j)
2132 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2133 DAG.getIntPtrConstant(j));
2135 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2138 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2139 SDValue InOp = GetWidenedVector(N->getOperand(0));
2140 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2141 N->getValueType(0), InOp, N->getOperand(1));
2144 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2145 SDValue InOp = GetWidenedVector(N->getOperand(0));
2146 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2147 N->getValueType(0), InOp, N->getOperand(1));
2150 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2151 // We have to widen the value but we want only to store the original
2153 StoreSDNode *ST = cast<StoreSDNode>(N);
2155 SmallVector<SDValue, 16> StChain;
2156 if (ST->isTruncatingStore())
2157 GenWidenVectorTruncStores(StChain, ST);
2159 GenWidenVectorStores(StChain, ST);
2161 if (StChain.size() == 1)
2164 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2165 MVT::Other,&StChain[0],StChain.size());
2168 //===----------------------------------------------------------------------===//
2169 // Vector Widening Utilities
2170 //===----------------------------------------------------------------------===//
2172 // Utility function to find the type to chop up a widen vector for load/store
2173 // TLI: Target lowering used to determine legal types.
2174 // Width: Width left need to load/store.
2175 // WidenVT: The widen vector type to load to/store from
2176 // Align: If 0, don't allow use of a wider type
2177 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2179 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2180 unsigned Width, EVT WidenVT,
2181 unsigned Align = 0, unsigned WidenEx = 0) {
2182 EVT WidenEltVT = WidenVT.getVectorElementType();
2183 unsigned WidenWidth = WidenVT.getSizeInBits();
2184 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2185 unsigned AlignInBits = Align*8;
2187 // If we have one element to load/store, return it.
2188 EVT RetVT = WidenEltVT;
2189 if (Width == WidenEltWidth)
2192 // See if there is larger legal integer than the element type to load/store
2194 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2195 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2196 EVT MemVT((MVT::SimpleValueType) VT);
2197 unsigned MemVTWidth = MemVT.getSizeInBits();
2198 if (MemVT.getSizeInBits() <= WidenEltWidth)
2200 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2201 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2202 (MemVTWidth <= Width ||
2203 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2209 // See if there is a larger vector type to load/store that has the same vector
2210 // element type and is evenly divisible with the WidenVT.
2211 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2212 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2213 EVT MemVT = (MVT::SimpleValueType) VT;
2214 unsigned MemVTWidth = MemVT.getSizeInBits();
2215 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2216 (WidenWidth % MemVTWidth) == 0 &&
2217 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2218 (MemVTWidth <= Width ||
2219 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2220 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2228 // Builds a vector type from scalar loads
2229 // VecTy: Resulting Vector type
2230 // LDOps: Load operators to build a vector type
2231 // [Start,End) the list of loads to use.
2232 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2233 SmallVector<SDValue, 16>& LdOps,
2234 unsigned Start, unsigned End) {
2235 DebugLoc dl = LdOps[Start].getDebugLoc();
2236 EVT LdTy = LdOps[Start].getValueType();
2237 unsigned Width = VecTy.getSizeInBits();
2238 unsigned NumElts = Width / LdTy.getSizeInBits();
2239 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2242 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2244 for (unsigned i = Start + 1; i != End; ++i) {
2245 EVT NewLdTy = LdOps[i].getValueType();
2246 if (NewLdTy != LdTy) {
2247 NumElts = Width / NewLdTy.getSizeInBits();
2248 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2249 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2250 // Readjust position and vector position based on new load type
2251 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2254 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2255 DAG.getIntPtrConstant(Idx++));
2257 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2260 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2262 // The strategy assumes that we can efficiently load powers of two widths.
2263 // The routines chops the vector into the largest vector loads with the same
2264 // element type or scalar loads and then recombines it to the widen vector
2266 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2267 unsigned WidenWidth = WidenVT.getSizeInBits();
2268 EVT LdVT = LD->getMemoryVT();
2269 DebugLoc dl = LD->getDebugLoc();
2270 assert(LdVT.isVector() && WidenVT.isVector());
2271 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2274 SDValue Chain = LD->getChain();
2275 SDValue BasePtr = LD->getBasePtr();
2276 unsigned Align = LD->getAlignment();
2277 bool isVolatile = LD->isVolatile();
2278 bool isNonTemporal = LD->isNonTemporal();
2280 int LdWidth = LdVT.getSizeInBits();
2281 int WidthDiff = WidenWidth - LdWidth; // Difference
2282 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2284 // Find the vector type that can load from.
2285 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2286 int NewVTWidth = NewVT.getSizeInBits();
2287 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2288 isVolatile, isNonTemporal, Align);
2289 LdChain.push_back(LdOp.getValue(1));
2291 // Check if we can load the element with one instruction
2292 if (LdWidth <= NewVTWidth) {
2293 if (!NewVT.isVector()) {
2294 unsigned NumElts = WidenWidth / NewVTWidth;
2295 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2296 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2297 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2299 if (NewVT == WidenVT)
2302 assert(WidenWidth % NewVTWidth == 0);
2303 unsigned NumConcat = WidenWidth / NewVTWidth;
2304 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2305 SDValue UndefVal = DAG.getUNDEF(NewVT);
2306 ConcatOps[0] = LdOp;
2307 for (unsigned i = 1; i != NumConcat; ++i)
2308 ConcatOps[i] = UndefVal;
2309 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2313 // Load vector by using multiple loads from largest vector to scalar
2314 SmallVector<SDValue, 16> LdOps;
2315 LdOps.push_back(LdOp);
2317 LdWidth -= NewVTWidth;
2318 unsigned Offset = 0;
2320 while (LdWidth > 0) {
2321 unsigned Increment = NewVTWidth / 8;
2322 Offset += Increment;
2323 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2324 DAG.getIntPtrConstant(Increment));
2326 if (LdWidth < NewVTWidth) {
2327 // Our current type we are using is too large, find a better size
2328 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2329 NewVTWidth = NewVT.getSizeInBits();
2332 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2333 LD->getPointerInfo().getWithOffset(Offset),
2335 isNonTemporal, MinAlign(Align, Increment));
2336 LdChain.push_back(LdOp.getValue(1));
2337 LdOps.push_back(LdOp);
2339 LdWidth -= NewVTWidth;
2342 // Build the vector from the loads operations
2343 unsigned End = LdOps.size();
2344 if (!LdOps[0].getValueType().isVector())
2345 // All the loads are scalar loads.
2346 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2348 // If the load contains vectors, build the vector using concat vector.
2349 // All of the vectors used to loads are power of 2 and the scalars load
2350 // can be combined to make a power of 2 vector.
2351 SmallVector<SDValue, 16> ConcatOps(End);
2354 EVT LdTy = LdOps[i].getValueType();
2355 // First combine the scalar loads to a vector
2356 if (!LdTy.isVector()) {
2357 for (--i; i >= 0; --i) {
2358 LdTy = LdOps[i].getValueType();
2359 if (LdTy.isVector())
2362 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2364 ConcatOps[--Idx] = LdOps[i];
2365 for (--i; i >= 0; --i) {
2366 EVT NewLdTy = LdOps[i].getValueType();
2367 if (NewLdTy != LdTy) {
2368 // Create a larger vector
2369 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2370 &ConcatOps[Idx], End - Idx);
2374 ConcatOps[--Idx] = LdOps[i];
2377 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2378 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2379 &ConcatOps[Idx], End - Idx);
2381 // We need to fill the rest with undefs to build the vector
2382 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2383 SmallVector<SDValue, 16> WidenOps(NumOps);
2384 SDValue UndefVal = DAG.getUNDEF(LdTy);
2387 for (; i != End-Idx; ++i)
2388 WidenOps[i] = ConcatOps[Idx+i];
2389 for (; i != NumOps; ++i)
2390 WidenOps[i] = UndefVal;
2392 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2396 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2398 ISD::LoadExtType ExtType) {
2399 // For extension loads, it may not be more efficient to chop up the vector
2400 // and then extended it. Instead, we unroll the load and build a new vector.
2401 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2402 EVT LdVT = LD->getMemoryVT();
2403 DebugLoc dl = LD->getDebugLoc();
2404 assert(LdVT.isVector() && WidenVT.isVector());
2407 SDValue Chain = LD->getChain();
2408 SDValue BasePtr = LD->getBasePtr();
2409 unsigned Align = LD->getAlignment();
2410 bool isVolatile = LD->isVolatile();
2411 bool isNonTemporal = LD->isNonTemporal();
2413 EVT EltVT = WidenVT.getVectorElementType();
2414 EVT LdEltVT = LdVT.getVectorElementType();
2415 unsigned NumElts = LdVT.getVectorNumElements();
2417 // Load each element and widen
2418 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2419 SmallVector<SDValue, 16> Ops(WidenNumElts);
2420 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2421 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2422 LD->getPointerInfo(),
2423 LdEltVT, isVolatile, isNonTemporal, Align);
2424 LdChain.push_back(Ops[0].getValue(1));
2425 unsigned i = 0, Offset = Increment;
2426 for (i=1; i < NumElts; ++i, Offset += Increment) {
2427 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2428 BasePtr, DAG.getIntPtrConstant(Offset));
2429 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2430 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2431 isVolatile, isNonTemporal, Align);
2432 LdChain.push_back(Ops[i].getValue(1));
2435 // Fill the rest with undefs
2436 SDValue UndefVal = DAG.getUNDEF(EltVT);
2437 for (; i != WidenNumElts; ++i)
2440 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2444 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2446 // The strategy assumes that we can efficiently store powers of two widths.
2447 // The routines chops the vector into the largest vector stores with the same
2448 // element type or scalar stores.
2449 SDValue Chain = ST->getChain();
2450 SDValue BasePtr = ST->getBasePtr();
2451 unsigned Align = ST->getAlignment();
2452 bool isVolatile = ST->isVolatile();
2453 bool isNonTemporal = ST->isNonTemporal();
2454 SDValue ValOp = GetWidenedVector(ST->getValue());
2455 DebugLoc dl = ST->getDebugLoc();
2457 EVT StVT = ST->getMemoryVT();
2458 unsigned StWidth = StVT.getSizeInBits();
2459 EVT ValVT = ValOp.getValueType();
2460 unsigned ValWidth = ValVT.getSizeInBits();
2461 EVT ValEltVT = ValVT.getVectorElementType();
2462 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2463 assert(StVT.getVectorElementType() == ValEltVT);
2465 int Idx = 0; // current index to store
2466 unsigned Offset = 0; // offset from base to store
2467 while (StWidth != 0) {
2468 // Find the largest vector type we can store with
2469 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2470 unsigned NewVTWidth = NewVT.getSizeInBits();
2471 unsigned Increment = NewVTWidth / 8;
2472 if (NewVT.isVector()) {
2473 unsigned NumVTElts = NewVT.getVectorNumElements();
2475 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2476 DAG.getIntPtrConstant(Idx));
2477 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2478 ST->getPointerInfo().getWithOffset(Offset),
2479 isVolatile, isNonTemporal,
2480 MinAlign(Align, Offset)));
2481 StWidth -= NewVTWidth;
2482 Offset += Increment;
2484 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2485 DAG.getIntPtrConstant(Increment));
2486 } while (StWidth != 0 && StWidth >= NewVTWidth);
2488 // Cast the vector to the scalar type we can store
2489 unsigned NumElts = ValWidth / NewVTWidth;
2490 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2491 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2492 // Readjust index position based on new vector type
2493 Idx = Idx * ValEltWidth / NewVTWidth;
2495 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2496 DAG.getIntPtrConstant(Idx++));
2497 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2498 ST->getPointerInfo().getWithOffset(Offset),
2499 isVolatile, isNonTemporal,
2500 MinAlign(Align, Offset)));
2501 StWidth -= NewVTWidth;
2502 Offset += Increment;
2503 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2504 DAG.getIntPtrConstant(Increment));
2505 } while (StWidth != 0 && StWidth >= NewVTWidth);
2506 // Restore index back to be relative to the original widen element type
2507 Idx = Idx * NewVTWidth / ValEltWidth;
2513 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2515 // For extension loads, it may not be more efficient to truncate the vector
2516 // and then store it. Instead, we extract each element and then store it.
2517 SDValue Chain = ST->getChain();
2518 SDValue BasePtr = ST->getBasePtr();
2519 unsigned Align = ST->getAlignment();
2520 bool isVolatile = ST->isVolatile();
2521 bool isNonTemporal = ST->isNonTemporal();
2522 SDValue ValOp = GetWidenedVector(ST->getValue());
2523 DebugLoc dl = ST->getDebugLoc();
2525 EVT StVT = ST->getMemoryVT();
2526 EVT ValVT = ValOp.getValueType();
2528 // It must be true that we the widen vector type is bigger than where
2529 // we need to store.
2530 assert(StVT.isVector() && ValOp.getValueType().isVector());
2531 assert(StVT.bitsLT(ValOp.getValueType()));
2533 // For truncating stores, we can not play the tricks of chopping legal
2534 // vector types and bit cast it to the right type. Instead, we unroll
2536 EVT StEltVT = StVT.getVectorElementType();
2537 EVT ValEltVT = ValVT.getVectorElementType();
2538 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2539 unsigned NumElts = StVT.getVectorNumElements();
2540 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2541 DAG.getIntPtrConstant(0));
2542 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2543 ST->getPointerInfo(), StEltVT,
2544 isVolatile, isNonTemporal, Align));
2545 unsigned Offset = Increment;
2546 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2547 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2548 BasePtr, DAG.getIntPtrConstant(Offset));
2549 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2550 DAG.getIntPtrConstant(0));
2551 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2552 ST->getPointerInfo().getWithOffset(Offset),
2553 StEltVT, isVolatile, isNonTemporal,
2554 MinAlign(Align, Offset)));
2558 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2559 /// input vector must have the same element type as NVT.
2560 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2561 // Note that InOp might have been widened so it might already have
2562 // the right width or it might need be narrowed.
2563 EVT InVT = InOp.getValueType();
2564 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2565 "input and widen element type must match");
2566 DebugLoc dl = InOp.getDebugLoc();
2568 // Check if InOp already has the right width.
2572 unsigned InNumElts = InVT.getVectorNumElements();
2573 unsigned WidenNumElts = NVT.getVectorNumElements();
2574 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2575 unsigned NumConcat = WidenNumElts / InNumElts;
2576 SmallVector<SDValue, 16> Ops(NumConcat);
2577 SDValue UndefVal = DAG.getUNDEF(InVT);
2579 for (unsigned i = 1; i != NumConcat; ++i)
2582 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2585 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2586 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2587 DAG.getIntPtrConstant(0));
2589 // Fall back to extract and build.
2590 SmallVector<SDValue, 16> Ops(WidenNumElts);
2591 EVT EltVT = NVT.getVectorElementType();
2592 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2594 for (Idx = 0; Idx < MinNumElts; ++Idx)
2595 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2596 DAG.getIntPtrConstant(Idx));
2598 SDValue UndefVal = DAG.getUNDEF(EltVT);
2599 for ( ; Idx < WidenNumElts; ++Idx)
2600 Ops[Idx] = UndefVal;
2601 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);