1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 //===----------------------------------------------------------------------===//
30 // Result Vector Scalarization: <1 x ty> -> ty.
31 //===----------------------------------------------------------------------===//
33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
37 SDValue R = SDValue();
39 switch (N->getOpcode()) {
42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
46 report_fatal_error("Do not know how to scalarize the result of this "
49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
89 case ISD::SIGN_EXTEND:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
116 R = ScalarizeVecRes_BinOp(N);
119 R = ScalarizeVecRes_TernaryOp(N);
123 // If R is null, the sub-method took care of registering the result.
125 SetScalarizedVector(SDValue(N, ResNo), R);
128 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
129 SDValue LHS = GetScalarizedVector(N->getOperand(0));
130 SDValue RHS = GetScalarizedVector(N->getOperand(1));
131 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
132 LHS.getValueType(), LHS, RHS);
135 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
136 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
137 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
138 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
139 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
140 Op0.getValueType(), Op0, Op1, Op2);
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
145 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
146 return GetScalarizedVector(Op);
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
150 EVT NewVT = N->getValueType(0).getVectorElementType();
151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
152 NewVT, N->getOperand(0));
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
156 EVT EltVT = N->getValueType(0).getVectorElementType();
157 SDValue InOp = N->getOperand(0);
158 // The BUILD_VECTOR operands may be of wider element types and
159 // we may need to truncate them back to the requested return type.
160 if (EltVT.isInteger())
161 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
166 EVT NewVT = N->getValueType(0).getVectorElementType();
167 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
168 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
169 Op0, DAG.getValueType(NewVT),
170 DAG.getValueType(Op0.getValueType()),
173 cast<CvtRndSatSDNode>(N)->getCvtCode());
176 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
178 N->getValueType(0).getVectorElementType(),
179 N->getOperand(0), N->getOperand(1));
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
183 EVT NewVT = N->getValueType(0).getVectorElementType();
184 SDValue Op = GetScalarizedVector(N->getOperand(0));
185 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
186 NewVT, Op, N->getOperand(1));
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
190 SDValue Op = GetScalarizedVector(N->getOperand(0));
191 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
192 Op.getValueType(), Op, N->getOperand(1));
195 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
196 // The value to insert may have a wider type than the vector element type,
197 // so be sure to truncate it to the element type if necessary.
198 SDValue Op = N->getOperand(1);
199 EVT EltVT = N->getValueType(0).getVectorElementType();
200 if (Op.getValueType() != EltVT)
201 // FIXME: Can this happen for floating point types?
202 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
207 assert(N->isUnindexed() && "Indexed vector load?");
209 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
210 N->getExtensionType(),
211 N->getValueType(0).getVectorElementType(),
213 N->getChain(), N->getBasePtr(),
214 DAG.getUNDEF(N->getBasePtr().getValueType()),
216 N->getMemoryVT().getVectorElementType(),
217 N->isVolatile(), N->isNonTemporal(),
218 N->isInvariant(), N->getOriginalAlignment());
220 // Legalized the chain result - switch anything that used the old chain to
222 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
226 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
227 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
228 EVT DestVT = N->getValueType(0).getVectorElementType();
229 SDValue Op = GetScalarizedVector(N->getOperand(0));
230 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
233 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
234 EVT EltVT = N->getValueType(0).getVectorElementType();
235 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
236 SDValue LHS = GetScalarizedVector(N->getOperand(0));
237 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
238 LHS, DAG.getValueType(ExtVT));
241 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
242 // If the operand is wider than the vector element type then it is implicitly
243 // truncated. Make that explicit here.
244 EVT EltVT = N->getValueType(0).getVectorElementType();
245 SDValue InOp = N->getOperand(0);
246 if (InOp.getValueType() != EltVT)
247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
251 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
252 SDValue Cond = GetScalarizedVector(N->getOperand(0));
253 SDValue LHS = GetScalarizedVector(N->getOperand(1));
254 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false);
255 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true);
256 if (ScalarBool != VecBool) {
257 EVT CondVT = Cond.getValueType();
258 switch (ScalarBool) {
259 case TargetLowering::UndefinedBooleanContent:
261 case TargetLowering::ZeroOrOneBooleanContent:
262 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
263 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
264 // Vector read from all ones, scalar expects a single 1 so mask.
265 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT,
266 Cond, DAG.getConstant(1, CondVT));
268 case TargetLowering::ZeroOrNegativeOneBooleanContent:
269 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
270 VecBool == TargetLowering::ZeroOrOneBooleanContent);
271 // Vector reads from a one, scalar from all ones so sign extend.
272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
273 Cond, DAG.getValueType(MVT::i1));
277 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
278 LHS.getValueType(), Cond, LHS,
279 GetScalarizedVector(N->getOperand(2)));
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
283 SDValue LHS = GetScalarizedVector(N->getOperand(1));
284 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
285 LHS.getValueType(), N->getOperand(0), LHS,
286 GetScalarizedVector(N->getOperand(2)));
289 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
290 SDValue LHS = GetScalarizedVector(N->getOperand(2));
291 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
292 N->getOperand(0), N->getOperand(1),
293 LHS, GetScalarizedVector(N->getOperand(3)),
297 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
298 assert(N->getValueType(0).isVector() ==
299 N->getOperand(0).getValueType().isVector() &&
300 "Scalar/Vector type mismatch");
302 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
304 SDValue LHS = GetScalarizedVector(N->getOperand(0));
305 SDValue RHS = GetScalarizedVector(N->getOperand(1));
306 DebugLoc DL = N->getDebugLoc();
308 // Turn it into a scalar SETCC.
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
312 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
313 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
316 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
317 // Figure out if the scalar is the LHS or RHS and return it.
318 SDValue Arg = N->getOperand(2).getOperand(0);
319 if (Arg.getOpcode() == ISD::UNDEF)
320 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
321 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
322 return GetScalarizedVector(N->getOperand(Op));
325 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
326 assert(N->getValueType(0).isVector() &&
327 N->getOperand(0).getValueType().isVector() &&
328 "Operand types must be vectors");
330 SDValue LHS = GetScalarizedVector(N->getOperand(0));
331 SDValue RHS = GetScalarizedVector(N->getOperand(1));
332 EVT NVT = N->getValueType(0).getVectorElementType();
333 DebugLoc DL = N->getDebugLoc();
335 // Turn it into a scalar SETCC.
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
338 // Vectors may have a different boolean contents to scalars. Promote the
339 // value appropriately.
340 ISD::NodeType ExtendCode =
341 TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
342 return DAG.getNode(ExtendCode, DL, NVT, Res);
346 //===----------------------------------------------------------------------===//
347 // Operand Vector Scalarization <1 x ty> -> ty.
348 //===----------------------------------------------------------------------===//
350 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
351 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
354 SDValue Res = SDValue();
356 if (Res.getNode() == 0) {
357 switch (N->getOpcode()) {
360 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
364 llvm_unreachable("Do not know how to scalarize this operator's operand!");
366 Res = ScalarizeVecOp_BITCAST(N);
368 case ISD::CONCAT_VECTORS:
369 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
371 case ISD::EXTRACT_VECTOR_ELT:
372 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
375 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
380 // If the result is null, the sub-method took care of registering results etc.
381 if (!Res.getNode()) return false;
383 // If the result is N, the sub-method updated N in place. Tell the legalizer
385 if (Res.getNode() == N)
388 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
389 "Invalid operand expansion");
391 ReplaceValueWith(SDValue(N, 0), Res);
395 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
396 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
397 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
398 SDValue Elt = GetScalarizedVector(N->getOperand(0));
399 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
400 N->getValueType(0), Elt);
403 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
404 /// use a BUILD_VECTOR instead.
405 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
406 SmallVector<SDValue, 8> Ops(N->getNumOperands());
407 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
408 Ops[i] = GetScalarizedVector(N->getOperand(i));
409 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
410 &Ops[0], Ops.size());
413 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
414 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
416 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
417 SDValue Res = GetScalarizedVector(N->getOperand(0));
418 if (Res.getValueType() != N->getValueType(0))
419 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
424 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
425 /// scalarized, it must be <1 x ty>. Just store the element.
426 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
427 assert(N->isUnindexed() && "Indexed store of one-element vector?");
428 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
429 DebugLoc dl = N->getDebugLoc();
431 if (N->isTruncatingStore())
432 return DAG.getTruncStore(N->getChain(), dl,
433 GetScalarizedVector(N->getOperand(1)),
434 N->getBasePtr(), N->getPointerInfo(),
435 N->getMemoryVT().getVectorElementType(),
436 N->isVolatile(), N->isNonTemporal(),
439 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
440 N->getBasePtr(), N->getPointerInfo(),
441 N->isVolatile(), N->isNonTemporal(),
442 N->getOriginalAlignment());
446 //===----------------------------------------------------------------------===//
447 // Result Vector Splitting
448 //===----------------------------------------------------------------------===//
450 /// SplitVectorResult - This method is called when the specified result of the
451 /// specified node is found to need vector splitting. At this point, the node
452 /// may also have invalid operands or may have other results that need
453 /// legalization, we just know that (at least) one result needs vector
455 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
456 DEBUG(dbgs() << "Split node result: ";
461 // See if the target wants to custom expand this node.
462 if (CustomLowerNode(N, N->getValueType(ResNo), true))
465 switch (N->getOpcode()) {
468 dbgs() << "SplitVectorResult #" << ResNo << ": ";
472 report_fatal_error("Do not know how to split the result of this "
475 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
477 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
478 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
479 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
480 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
481 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
482 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
483 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
484 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
485 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
486 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
487 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
488 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
490 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
493 SplitVecRes_SETCC(N, Lo, Hi);
495 case ISD::VECTOR_SHUFFLE:
496 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
499 case ISD::ANY_EXTEND:
500 case ISD::CONVERT_RNDSAT:
503 case ISD::CTLZ_ZERO_UNDEF:
504 case ISD::CTTZ_ZERO_UNDEF:
515 case ISD::FNEARBYINT:
519 case ISD::FP_TO_SINT:
520 case ISD::FP_TO_UINT:
525 case ISD::SIGN_EXTEND:
526 case ISD::SINT_TO_FP:
528 case ISD::UINT_TO_FP:
529 case ISD::ZERO_EXTEND:
530 SplitVecRes_UnaryOp(N, Lo, Hi);
552 SplitVecRes_BinOp(N, Lo, Hi);
555 SplitVecRes_TernaryOp(N, Lo, Hi);
559 // If Lo/Hi is null, the sub-method took care of registering results etc.
561 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
564 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
566 SDValue LHSLo, LHSHi;
567 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
568 SDValue RHSLo, RHSHi;
569 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
570 DebugLoc dl = N->getDebugLoc();
572 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
573 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
576 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
578 SDValue Op0Lo, Op0Hi;
579 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
580 SDValue Op1Lo, Op1Hi;
581 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
582 SDValue Op2Lo, Op2Hi;
583 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
584 DebugLoc dl = N->getDebugLoc();
586 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
587 Op0Lo, Op1Lo, Op2Lo);
588 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
589 Op0Hi, Op1Hi, Op2Hi);
592 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
594 // We know the result is a vector. The input may be either a vector or a
597 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
598 DebugLoc dl = N->getDebugLoc();
600 SDValue InOp = N->getOperand(0);
601 EVT InVT = InOp.getValueType();
603 // Handle some special cases efficiently.
604 switch (getTypeAction(InVT)) {
605 case TargetLowering::TypeLegal:
606 case TargetLowering::TypePromoteInteger:
607 case TargetLowering::TypeSoftenFloat:
608 case TargetLowering::TypeScalarizeVector:
609 case TargetLowering::TypeWidenVector:
611 case TargetLowering::TypeExpandInteger:
612 case TargetLowering::TypeExpandFloat:
613 // A scalar to vector conversion, where the scalar needs expansion.
614 // If the vector is being split in two then we can just convert the
617 GetExpandedOp(InOp, Lo, Hi);
618 if (TLI.isBigEndian())
620 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
621 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
625 case TargetLowering::TypeSplitVector:
626 // If the input is a vector that needs to be split, convert each split
627 // piece of the input now.
628 GetSplitVector(InOp, Lo, Hi);
629 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
630 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
634 // In the general case, convert the input to an integer and split it by hand.
635 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
636 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
637 if (TLI.isBigEndian())
638 std::swap(LoIntVT, HiIntVT);
640 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
642 if (TLI.isBigEndian())
644 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
645 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
648 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
651 DebugLoc dl = N->getDebugLoc();
652 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
653 unsigned LoNumElts = LoVT.getVectorNumElements();
654 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
655 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
657 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
658 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
661 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
663 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
664 DebugLoc dl = N->getDebugLoc();
665 unsigned NumSubvectors = N->getNumOperands() / 2;
666 if (NumSubvectors == 1) {
667 Lo = N->getOperand(0);
668 Hi = N->getOperand(1);
673 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
675 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
676 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
678 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
679 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
682 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
684 SDValue Vec = N->getOperand(0);
685 SDValue Idx = N->getOperand(1);
686 DebugLoc dl = N->getDebugLoc();
689 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
691 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
692 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
693 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
694 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
697 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
699 DebugLoc dl = N->getDebugLoc();
700 GetSplitVector(N->getOperand(0), Lo, Hi);
701 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
702 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
705 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
707 SDValue LHSLo, LHSHi;
708 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
709 DebugLoc dl = N->getDebugLoc();
712 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
714 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
715 DAG.getValueType(LoVT));
716 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
717 DAG.getValueType(HiVT));
720 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
722 SDValue Vec = N->getOperand(0);
723 SDValue Elt = N->getOperand(1);
724 SDValue Idx = N->getOperand(2);
725 DebugLoc dl = N->getDebugLoc();
726 GetSplitVector(Vec, Lo, Hi);
728 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
729 unsigned IdxVal = CIdx->getZExtValue();
730 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
731 if (IdxVal < LoNumElts)
732 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
733 Lo.getValueType(), Lo, Elt, Idx);
735 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
736 DAG.getIntPtrConstant(IdxVal - LoNumElts));
740 // Spill the vector to the stack.
741 EVT VecVT = Vec.getValueType();
742 EVT EltVT = VecVT.getVectorElementType();
743 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
744 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
745 MachinePointerInfo(), false, false, 0);
747 // Store the new element. This may be larger than the vector element type,
748 // so use a truncating store.
749 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
750 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
752 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
753 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
756 // Load the Lo part from the stack slot.
757 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
758 false, false, false, 0);
760 // Increment the pointer to the other part.
761 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
762 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
763 DAG.getIntPtrConstant(IncrementSize));
765 // Load the Hi part from the stack slot.
766 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
767 false, false, false, MinAlign(Alignment, IncrementSize));
770 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
773 DebugLoc dl = N->getDebugLoc();
774 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
775 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
776 Hi = DAG.getUNDEF(HiVT);
779 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
781 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
783 DebugLoc dl = LD->getDebugLoc();
784 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
786 ISD::LoadExtType ExtType = LD->getExtensionType();
787 SDValue Ch = LD->getChain();
788 SDValue Ptr = LD->getBasePtr();
789 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
790 EVT MemoryVT = LD->getMemoryVT();
791 unsigned Alignment = LD->getOriginalAlignment();
792 bool isVolatile = LD->isVolatile();
793 bool isNonTemporal = LD->isNonTemporal();
794 bool isInvariant = LD->isInvariant();
796 EVT LoMemVT, HiMemVT;
797 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
799 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
800 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
801 isInvariant, Alignment);
803 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
804 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
805 DAG.getIntPtrConstant(IncrementSize));
806 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
807 LD->getPointerInfo().getWithOffset(IncrementSize),
808 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment);
810 // Build a factor node to remember that this load is independent of the
812 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
815 // Legalized the chain result - switch anything that used the old chain to
817 ReplaceValueWith(SDValue(LD, 1), Ch);
820 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
821 assert(N->getValueType(0).isVector() &&
822 N->getOperand(0).getValueType().isVector() &&
823 "Operand types must be vectors");
826 DebugLoc DL = N->getDebugLoc();
827 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
830 EVT InVT = N->getOperand(0).getValueType();
831 SDValue LL, LH, RL, RH;
832 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
833 LoVT.getVectorNumElements());
834 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
835 DAG.getIntPtrConstant(0));
836 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
837 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
839 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
840 DAG.getIntPtrConstant(0));
841 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
842 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
844 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
845 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
848 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
850 // Get the dest types - they may not match the input types, e.g. int_to_fp.
852 DebugLoc dl = N->getDebugLoc();
853 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
855 // If the input also splits, handle it directly for a compile time speedup.
856 // Otherwise split it by hand.
857 EVT InVT = N->getOperand(0).getValueType();
858 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
859 GetSplitVector(N->getOperand(0), Lo, Hi);
861 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
862 LoVT.getVectorNumElements());
863 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
864 DAG.getIntPtrConstant(0));
865 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
866 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
869 if (N->getOpcode() == ISD::FP_ROUND) {
870 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
871 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
872 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
873 SDValue DTyOpLo = DAG.getValueType(LoVT);
874 SDValue DTyOpHi = DAG.getValueType(HiVT);
875 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
876 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
877 SDValue RndOp = N->getOperand(3);
878 SDValue SatOp = N->getOperand(4);
879 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
880 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
882 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
885 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
886 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
890 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
891 SDValue &Lo, SDValue &Hi) {
892 // The low and high parts of the original input give four input vectors.
894 DebugLoc dl = N->getDebugLoc();
895 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
896 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
897 EVT NewVT = Inputs[0].getValueType();
898 unsigned NewElts = NewVT.getVectorNumElements();
900 // If Lo or Hi uses elements from at most two of the four input vectors, then
901 // express it as a vector shuffle of those two inputs. Otherwise extract the
902 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
903 SmallVector<int, 16> Ops;
904 for (unsigned High = 0; High < 2; ++High) {
905 SDValue &Output = High ? Hi : Lo;
907 // Build a shuffle mask for the output, discovering on the fly which
908 // input vectors to use as shuffle operands (recorded in InputUsed).
909 // If building a suitable shuffle vector proves too hard, then bail
910 // out with useBuildVector set.
911 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
912 unsigned FirstMaskIdx = High * NewElts;
913 bool useBuildVector = false;
914 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
915 // The mask element. This indexes into the input.
916 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
918 // The input vector this mask element indexes into.
919 unsigned Input = (unsigned)Idx / NewElts;
921 if (Input >= array_lengthof(Inputs)) {
922 // The mask element does not index into any input vector.
927 // Turn the index into an offset from the start of the input vector.
928 Idx -= Input * NewElts;
930 // Find or create a shuffle vector operand to hold this input.
932 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
933 if (InputUsed[OpNo] == Input) {
934 // This input vector is already an operand.
936 } else if (InputUsed[OpNo] == -1U) {
937 // Create a new operand for this input vector.
938 InputUsed[OpNo] = Input;
943 if (OpNo >= array_lengthof(InputUsed)) {
944 // More than two input vectors used! Give up on trying to create a
945 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
946 useBuildVector = true;
950 // Add the mask index for the new shuffle vector.
951 Ops.push_back(Idx + OpNo * NewElts);
954 if (useBuildVector) {
955 EVT EltVT = NewVT.getVectorElementType();
956 SmallVector<SDValue, 16> SVOps;
958 // Extract the input elements by hand.
959 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
960 // The mask element. This indexes into the input.
961 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
963 // The input vector this mask element indexes into.
964 unsigned Input = (unsigned)Idx / NewElts;
966 if (Input >= array_lengthof(Inputs)) {
967 // The mask element is "undef" or indexes off the end of the input.
968 SVOps.push_back(DAG.getUNDEF(EltVT));
972 // Turn the index into an offset from the start of the input vector.
973 Idx -= Input * NewElts;
975 // Extract the vector element by hand.
976 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
977 Inputs[Input], DAG.getIntPtrConstant(Idx)));
980 // Construct the Lo/Hi output using a BUILD_VECTOR.
981 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
982 } else if (InputUsed[0] == -1U) {
983 // No input vectors were used! The result is undefined.
984 Output = DAG.getUNDEF(NewVT);
986 SDValue Op0 = Inputs[InputUsed[0]];
987 // If only one input was used, use an undefined vector for the other.
988 SDValue Op1 = InputUsed[1] == -1U ?
989 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
990 // At least one input vector was used. Create a new shuffle vector.
991 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
999 //===----------------------------------------------------------------------===//
1000 // Operand Vector Splitting
1001 //===----------------------------------------------------------------------===//
1003 /// SplitVectorOperand - This method is called when the specified operand of the
1004 /// specified node is found to need vector splitting. At this point, all of the
1005 /// result types of the node are known to be legal, but other operands of the
1006 /// node may need legalization as well as the specified one.
1007 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1008 DEBUG(dbgs() << "Split node operand: ";
1011 SDValue Res = SDValue();
1013 if (Res.getNode() == 0) {
1014 switch (N->getOpcode()) {
1017 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1021 report_fatal_error("Do not know how to split this operator's "
1024 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1025 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1026 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1027 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1028 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1029 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1031 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1034 Res = SplitVecOp_VSELECT(N, OpNo);
1039 case ISD::FP_EXTEND:
1040 case ISD::FP_TO_SINT:
1041 case ISD::FP_TO_UINT:
1042 case ISD::SINT_TO_FP:
1043 case ISD::UINT_TO_FP:
1046 case ISD::SIGN_EXTEND:
1047 case ISD::ZERO_EXTEND:
1048 case ISD::ANY_EXTEND:
1049 Res = SplitVecOp_UnaryOp(N);
1054 // If the result is null, the sub-method took care of registering results etc.
1055 if (!Res.getNode()) return false;
1057 // If the result is N, the sub-method updated N in place. Tell the legalizer
1059 if (Res.getNode() == N)
1062 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1063 "Invalid operand expansion");
1065 ReplaceValueWith(SDValue(N, 0), Res);
1069 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1070 // The only possibility for an illegal operand is the mask, since result type
1071 // legalization would have handled this node already otherwise.
1072 assert(OpNo == 0 && "Illegal operand must be mask");
1074 SDValue Mask = N->getOperand(0);
1075 SDValue Src0 = N->getOperand(1);
1076 SDValue Src1 = N->getOperand(2);
1077 DebugLoc DL = N->getDebugLoc();
1078 EVT MaskVT = Mask.getValueType();
1079 assert(MaskVT.isVector() && "VSELECT without a vector mask?");
1082 GetSplitVector(N->getOperand(0), Lo, Hi);
1083 assert(Lo.getValueType() == Hi.getValueType() &&
1084 "Lo and Hi have differing types");;
1086 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1087 unsigned HiNumElts = Hi.getValueType().getVectorNumElements();
1088 assert(LoNumElts == HiNumElts && "Asymmetric vector split?");
1090 LLVMContext &Ctx = *DAG.getContext();
1091 SDValue Zero = DAG.getIntPtrConstant(0);
1092 SDValue LoElts = DAG.getIntPtrConstant(LoNumElts);
1093 EVT Src0VT = Src0.getValueType();
1094 EVT Src0EltTy = Src0VT.getVectorElementType();
1095 EVT MaskEltTy = MaskVT.getVectorElementType();
1097 EVT LoOpVT = EVT::getVectorVT(Ctx, Src0EltTy, LoNumElts);
1098 EVT LoMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, LoNumElts);
1099 EVT HiOpVT = EVT::getVectorVT(Ctx, Src0EltTy, HiNumElts);
1100 EVT HiMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, HiNumElts);
1102 SDValue LoOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src0, Zero);
1103 SDValue LoOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src1, Zero);
1105 SDValue HiOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src0, LoElts);
1106 SDValue HiOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src1, LoElts);
1109 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoMaskVT, Mask, Zero);
1111 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiMaskVT, Mask, LoElts);
1114 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1116 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1118 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1121 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1122 // The result has a legal vector type, but the input needs splitting.
1123 EVT ResVT = N->getValueType(0);
1125 DebugLoc dl = N->getDebugLoc();
1126 GetSplitVector(N->getOperand(0), Lo, Hi);
1127 EVT InVT = Lo.getValueType();
1129 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1130 InVT.getVectorNumElements());
1132 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1133 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1135 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1138 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1139 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1140 // end up being split all the way down to individual components. Convert the
1141 // split pieces into integers and reassemble.
1143 GetSplitVector(N->getOperand(0), Lo, Hi);
1144 Lo = BitConvertToInteger(Lo);
1145 Hi = BitConvertToInteger(Hi);
1147 if (TLI.isBigEndian())
1150 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1151 JoinIntegers(Lo, Hi));
1154 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1155 // We know that the extracted result type is legal.
1156 EVT SubVT = N->getValueType(0);
1157 SDValue Idx = N->getOperand(1);
1158 DebugLoc dl = N->getDebugLoc();
1160 GetSplitVector(N->getOperand(0), Lo, Hi);
1162 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1163 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1165 if (IdxVal < LoElts) {
1166 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1167 "Extracted subvector crosses vector split!");
1168 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1171 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1175 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1176 SDValue Vec = N->getOperand(0);
1177 SDValue Idx = N->getOperand(1);
1178 EVT VecVT = Vec.getValueType();
1180 if (isa<ConstantSDNode>(Idx)) {
1181 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1182 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1185 GetSplitVector(Vec, Lo, Hi);
1187 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1189 if (IdxVal < LoElts)
1190 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1191 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1192 DAG.getConstant(IdxVal - LoElts,
1193 Idx.getValueType())), 0);
1196 // Store the vector to the stack.
1197 EVT EltVT = VecVT.getVectorElementType();
1198 DebugLoc dl = N->getDebugLoc();
1199 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1200 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1201 MachinePointerInfo(), false, false, 0);
1203 // Load back the required element.
1204 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1205 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1206 MachinePointerInfo(), EltVT, false, false, 0);
1209 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1210 assert(N->isUnindexed() && "Indexed store of vector?");
1211 assert(OpNo == 1 && "Can only split the stored value");
1212 DebugLoc DL = N->getDebugLoc();
1214 bool isTruncating = N->isTruncatingStore();
1215 SDValue Ch = N->getChain();
1216 SDValue Ptr = N->getBasePtr();
1217 EVT MemoryVT = N->getMemoryVT();
1218 unsigned Alignment = N->getOriginalAlignment();
1219 bool isVol = N->isVolatile();
1220 bool isNT = N->isNonTemporal();
1222 GetSplitVector(N->getOperand(1), Lo, Hi);
1224 EVT LoMemVT, HiMemVT;
1225 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1227 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1230 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1231 LoMemVT, isVol, isNT, Alignment);
1233 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1234 isVol, isNT, Alignment);
1236 // Increment the pointer to the other half.
1237 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1238 DAG.getIntPtrConstant(IncrementSize));
1241 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1242 N->getPointerInfo().getWithOffset(IncrementSize),
1243 HiMemVT, isVol, isNT, Alignment);
1245 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1246 N->getPointerInfo().getWithOffset(IncrementSize),
1247 isVol, isNT, Alignment);
1249 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1252 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1253 DebugLoc DL = N->getDebugLoc();
1255 // The input operands all must have the same type, and we know the result the
1256 // result type is valid. Convert this to a buildvector which extracts all the
1258 // TODO: If the input elements are power-two vectors, we could convert this to
1259 // a new CONCAT_VECTORS node with elements that are half-wide.
1260 SmallVector<SDValue, 32> Elts;
1261 EVT EltVT = N->getValueType(0).getVectorElementType();
1262 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1263 SDValue Op = N->getOperand(op);
1264 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1266 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1267 Op, DAG.getIntPtrConstant(i)));
1272 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1273 &Elts[0], Elts.size());
1276 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1277 assert(N->getValueType(0).isVector() &&
1278 N->getOperand(0).getValueType().isVector() &&
1279 "Operand types must be vectors");
1280 // The result has a legal vector type, but the input needs splitting.
1281 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1282 DebugLoc DL = N->getDebugLoc();
1283 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1284 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1285 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1286 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1287 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1289 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1290 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1291 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1292 return PromoteTargetBoolean(Con, N->getValueType(0));
1296 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1297 // The result has a legal vector type, but the input needs splitting.
1298 EVT ResVT = N->getValueType(0);
1300 DebugLoc DL = N->getDebugLoc();
1301 GetSplitVector(N->getOperand(0), Lo, Hi);
1302 EVT InVT = Lo.getValueType();
1304 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1305 InVT.getVectorNumElements());
1307 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1308 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1310 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1315 //===----------------------------------------------------------------------===//
1316 // Result Vector Widening
1317 //===----------------------------------------------------------------------===//
1319 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1320 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1324 // See if the target wants to custom widen this node.
1325 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1328 SDValue Res = SDValue();
1329 switch (N->getOpcode()) {
1332 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1336 llvm_unreachable("Do not know how to widen the result of this operator!");
1338 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1339 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1340 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1341 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1342 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1343 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1344 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1345 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1346 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1347 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1348 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1350 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1351 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1352 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1353 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1354 case ISD::VECTOR_SHUFFLE:
1355 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1361 case ISD::FCOPYSIGN:
1377 Res = WidenVecRes_Binary(N);
1381 Res = WidenVecRes_POWI(N);
1387 Res = WidenVecRes_Shift(N);
1390 case ISD::ANY_EXTEND:
1391 case ISD::FP_EXTEND:
1393 case ISD::FP_TO_SINT:
1394 case ISD::FP_TO_UINT:
1395 case ISD::SIGN_EXTEND:
1396 case ISD::SINT_TO_FP:
1398 case ISD::UINT_TO_FP:
1399 case ISD::ZERO_EXTEND:
1400 Res = WidenVecRes_Convert(N);
1415 case ISD::FNEARBYINT:
1421 Res = WidenVecRes_Unary(N);
1424 Res = WidenVecRes_Ternary(N);
1428 // If Res is null, the sub-method took care of registering the result.
1430 SetWidenedVector(SDValue(N, ResNo), Res);
1433 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1434 // Ternary op widening.
1435 DebugLoc dl = N->getDebugLoc();
1436 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1437 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1438 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1439 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1440 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1443 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1444 // Binary op widening.
1445 unsigned Opcode = N->getOpcode();
1446 DebugLoc dl = N->getDebugLoc();
1447 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1448 EVT WidenEltVT = WidenVT.getVectorElementType();
1450 unsigned NumElts = VT.getVectorNumElements();
1451 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1452 NumElts = NumElts / 2;
1453 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1456 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1457 // Operation doesn't trap so just widen as normal.
1458 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1459 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1460 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1463 // No legal vector version so unroll the vector operation and then widen.
1465 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1467 // Since the operation can trap, apply operation on the original vector.
1469 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1470 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1471 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1473 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1474 unsigned ConcatEnd = 0; // Current ConcatOps index.
1475 int Idx = 0; // Current Idx into input vectors.
1477 // NumElts := greatest legal vector size (at most WidenVT)
1478 // while (orig. vector has unhandled elements) {
1479 // take munches of size NumElts from the beginning and add to ConcatOps
1480 // NumElts := next smaller supported vector size or 1
1482 while (CurNumElts != 0) {
1483 while (CurNumElts >= NumElts) {
1484 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1485 DAG.getIntPtrConstant(Idx));
1486 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1487 DAG.getIntPtrConstant(Idx));
1488 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1490 CurNumElts -= NumElts;
1493 NumElts = NumElts / 2;
1494 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1495 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1498 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1499 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1500 InOp1, DAG.getIntPtrConstant(Idx));
1501 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1502 InOp2, DAG.getIntPtrConstant(Idx));
1503 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1510 // Check to see if we have a single operation with the widen type.
1511 if (ConcatEnd == 1) {
1512 VT = ConcatOps[0].getValueType();
1514 return ConcatOps[0];
1517 // while (Some element of ConcatOps is not of type MaxVT) {
1518 // From the end of ConcatOps, collect elements of the same type and put
1519 // them into an op of the next larger supported type
1521 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1522 Idx = ConcatEnd - 1;
1523 VT = ConcatOps[Idx--].getValueType();
1524 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1527 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1531 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1532 } while (!TLI.isTypeLegal(NextVT));
1534 if (!VT.isVector()) {
1535 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1536 SDValue VecOp = DAG.getUNDEF(NextVT);
1537 unsigned NumToInsert = ConcatEnd - Idx - 1;
1538 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1539 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1540 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1542 ConcatOps[Idx+1] = VecOp;
1543 ConcatEnd = Idx + 2;
1545 // Vector type, create a CONCAT_VECTORS of type NextVT
1546 SDValue undefVec = DAG.getUNDEF(VT);
1547 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1548 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1549 unsigned RealVals = ConcatEnd - Idx - 1;
1550 unsigned SubConcatEnd = 0;
1551 unsigned SubConcatIdx = Idx + 1;
1552 while (SubConcatEnd < RealVals)
1553 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1554 while (SubConcatEnd < OpsToConcat)
1555 SubConcatOps[SubConcatEnd++] = undefVec;
1556 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1557 NextVT, &SubConcatOps[0],
1559 ConcatEnd = SubConcatIdx + 1;
1563 // Check to see if we have a single operation with the widen type.
1564 if (ConcatEnd == 1) {
1565 VT = ConcatOps[0].getValueType();
1567 return ConcatOps[0];
1570 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1571 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1572 if (NumOps != ConcatEnd ) {
1573 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1574 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1575 ConcatOps[j] = UndefVal;
1577 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1580 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1581 SDValue InOp = N->getOperand(0);
1582 DebugLoc DL = N->getDebugLoc();
1584 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1585 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1587 EVT InVT = InOp.getValueType();
1588 EVT InEltVT = InVT.getVectorElementType();
1589 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1591 unsigned Opcode = N->getOpcode();
1592 unsigned InVTNumElts = InVT.getVectorNumElements();
1594 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1595 InOp = GetWidenedVector(N->getOperand(0));
1596 InVT = InOp.getValueType();
1597 InVTNumElts = InVT.getVectorNumElements();
1598 if (InVTNumElts == WidenNumElts) {
1599 if (N->getNumOperands() == 1)
1600 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1601 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1605 if (TLI.isTypeLegal(InWidenVT)) {
1606 // Because the result and the input are different vector types, widening
1607 // the result could create a legal type but widening the input might make
1608 // it an illegal type that might lead to repeatedly splitting the input
1609 // and then widening it. To avoid this, we widen the input only if
1610 // it results in a legal type.
1611 if (WidenNumElts % InVTNumElts == 0) {
1612 // Widen the input and call convert on the widened input vector.
1613 unsigned NumConcat = WidenNumElts/InVTNumElts;
1614 SmallVector<SDValue, 16> Ops(NumConcat);
1616 SDValue UndefVal = DAG.getUNDEF(InVT);
1617 for (unsigned i = 1; i != NumConcat; ++i)
1619 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1620 &Ops[0], NumConcat);
1621 if (N->getNumOperands() == 1)
1622 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1623 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1626 if (InVTNumElts % WidenNumElts == 0) {
1627 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1628 InOp, DAG.getIntPtrConstant(0));
1629 // Extract the input and convert the shorten input vector.
1630 if (N->getNumOperands() == 1)
1631 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1632 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1636 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1637 SmallVector<SDValue, 16> Ops(WidenNumElts);
1638 EVT EltVT = WidenVT.getVectorElementType();
1639 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1641 for (i=0; i < MinElts; ++i) {
1642 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1643 DAG.getIntPtrConstant(i));
1644 if (N->getNumOperands() == 1)
1645 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1647 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1650 SDValue UndefVal = DAG.getUNDEF(EltVT);
1651 for (; i < WidenNumElts; ++i)
1654 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1657 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1658 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1659 SDValue InOp = GetWidenedVector(N->getOperand(0));
1660 SDValue ShOp = N->getOperand(1);
1661 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1664 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1665 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1666 SDValue InOp = GetWidenedVector(N->getOperand(0));
1667 SDValue ShOp = N->getOperand(1);
1669 EVT ShVT = ShOp.getValueType();
1670 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1671 ShOp = GetWidenedVector(ShOp);
1672 ShVT = ShOp.getValueType();
1674 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1675 ShVT.getVectorElementType(),
1676 WidenVT.getVectorNumElements());
1677 if (ShVT != ShWidenVT)
1678 ShOp = ModifyToType(ShOp, ShWidenVT);
1680 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1683 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1684 // Unary op widening.
1685 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1686 SDValue InOp = GetWidenedVector(N->getOperand(0));
1687 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1690 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1691 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1692 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1693 cast<VTSDNode>(N->getOperand(1))->getVT()
1694 .getVectorElementType(),
1695 WidenVT.getVectorNumElements());
1696 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1697 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1698 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1701 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
1702 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
1703 return GetWidenedVector(WidenVec);
1706 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1707 SDValue InOp = N->getOperand(0);
1708 EVT InVT = InOp.getValueType();
1709 EVT VT = N->getValueType(0);
1710 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1711 DebugLoc dl = N->getDebugLoc();
1713 switch (getTypeAction(InVT)) {
1714 case TargetLowering::TypeLegal:
1716 case TargetLowering::TypePromoteInteger:
1717 // If the incoming type is a vector that is being promoted, then
1718 // we know that the elements are arranged differently and that we
1719 // must perform the conversion using a stack slot.
1720 if (InVT.isVector())
1723 // If the InOp is promoted to the same size, convert it. Otherwise,
1724 // fall out of the switch and widen the promoted input.
1725 InOp = GetPromotedInteger(InOp);
1726 InVT = InOp.getValueType();
1727 if (WidenVT.bitsEq(InVT))
1728 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1730 case TargetLowering::TypeSoftenFloat:
1731 case TargetLowering::TypeExpandInteger:
1732 case TargetLowering::TypeExpandFloat:
1733 case TargetLowering::TypeScalarizeVector:
1734 case TargetLowering::TypeSplitVector:
1736 case TargetLowering::TypeWidenVector:
1737 // If the InOp is widened to the same size, convert it. Otherwise, fall
1738 // out of the switch and widen the widened input.
1739 InOp = GetWidenedVector(InOp);
1740 InVT = InOp.getValueType();
1741 if (WidenVT.bitsEq(InVT))
1742 // The input widens to the same size. Convert to the widen value.
1743 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1747 unsigned WidenSize = WidenVT.getSizeInBits();
1748 unsigned InSize = InVT.getSizeInBits();
1749 // x86mmx is not an acceptable vector element type, so don't try.
1750 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1751 // Determine new input vector type. The new input vector type will use
1752 // the same element type (if its a vector) or use the input type as a
1753 // vector. It is the same size as the type to widen to.
1755 unsigned NewNumElts = WidenSize / InSize;
1756 if (InVT.isVector()) {
1757 EVT InEltVT = InVT.getVectorElementType();
1758 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1759 WidenSize / InEltVT.getSizeInBits());
1761 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1764 if (TLI.isTypeLegal(NewInVT)) {
1765 // Because the result and the input are different vector types, widening
1766 // the result could create a legal type but widening the input might make
1767 // it an illegal type that might lead to repeatedly splitting the input
1768 // and then widening it. To avoid this, we widen the input only if
1769 // it results in a legal type.
1770 SmallVector<SDValue, 16> Ops(NewNumElts);
1771 SDValue UndefVal = DAG.getUNDEF(InVT);
1773 for (unsigned i = 1; i < NewNumElts; ++i)
1777 if (InVT.isVector())
1778 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1779 NewInVT, &Ops[0], NewNumElts);
1781 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1782 NewInVT, &Ops[0], NewNumElts);
1783 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1787 return CreateStackStoreLoad(InOp, WidenVT);
1790 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1791 DebugLoc dl = N->getDebugLoc();
1792 // Build a vector with undefined for the new nodes.
1793 EVT VT = N->getValueType(0);
1794 EVT EltVT = VT.getVectorElementType();
1795 unsigned NumElts = VT.getVectorNumElements();
1797 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1798 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1800 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1801 NewOps.reserve(WidenNumElts);
1802 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1803 NewOps.push_back(DAG.getUNDEF(EltVT));
1805 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1808 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1809 EVT InVT = N->getOperand(0).getValueType();
1810 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1811 DebugLoc dl = N->getDebugLoc();
1812 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1813 unsigned NumInElts = InVT.getVectorNumElements();
1814 unsigned NumOperands = N->getNumOperands();
1816 bool InputWidened = false; // Indicates we need to widen the input.
1817 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1818 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1819 // Add undef vectors to widen to correct length.
1820 unsigned NumConcat = WidenVT.getVectorNumElements() /
1821 InVT.getVectorNumElements();
1822 SDValue UndefVal = DAG.getUNDEF(InVT);
1823 SmallVector<SDValue, 16> Ops(NumConcat);
1824 for (unsigned i=0; i < NumOperands; ++i)
1825 Ops[i] = N->getOperand(i);
1826 for (unsigned i = NumOperands; i != NumConcat; ++i)
1828 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1831 InputWidened = true;
1832 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1833 // The inputs and the result are widen to the same value.
1835 for (i=1; i < NumOperands; ++i)
1836 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1839 if (i == NumOperands)
1840 // Everything but the first operand is an UNDEF so just return the
1841 // widened first operand.
1842 return GetWidenedVector(N->getOperand(0));
1844 if (NumOperands == 2) {
1845 // Replace concat of two operands with a shuffle.
1846 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1847 for (unsigned i = 0; i < NumInElts; ++i) {
1849 MaskOps[i + NumInElts] = i + WidenNumElts;
1851 return DAG.getVectorShuffle(WidenVT, dl,
1852 GetWidenedVector(N->getOperand(0)),
1853 GetWidenedVector(N->getOperand(1)),
1859 // Fall back to use extracts and build vector.
1860 EVT EltVT = WidenVT.getVectorElementType();
1861 SmallVector<SDValue, 16> Ops(WidenNumElts);
1863 for (unsigned i=0; i < NumOperands; ++i) {
1864 SDValue InOp = N->getOperand(i);
1866 InOp = GetWidenedVector(InOp);
1867 for (unsigned j=0; j < NumInElts; ++j)
1868 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1869 DAG.getIntPtrConstant(j));
1871 SDValue UndefVal = DAG.getUNDEF(EltVT);
1872 for (; Idx < WidenNumElts; ++Idx)
1873 Ops[Idx] = UndefVal;
1874 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1877 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1878 DebugLoc dl = N->getDebugLoc();
1879 SDValue InOp = N->getOperand(0);
1880 SDValue RndOp = N->getOperand(3);
1881 SDValue SatOp = N->getOperand(4);
1883 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1884 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1886 EVT InVT = InOp.getValueType();
1887 EVT InEltVT = InVT.getVectorElementType();
1888 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1890 SDValue DTyOp = DAG.getValueType(WidenVT);
1891 SDValue STyOp = DAG.getValueType(InWidenVT);
1892 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1894 unsigned InVTNumElts = InVT.getVectorNumElements();
1895 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1896 InOp = GetWidenedVector(InOp);
1897 InVT = InOp.getValueType();
1898 InVTNumElts = InVT.getVectorNumElements();
1899 if (InVTNumElts == WidenNumElts)
1900 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1904 if (TLI.isTypeLegal(InWidenVT)) {
1905 // Because the result and the input are different vector types, widening
1906 // the result could create a legal type but widening the input might make
1907 // it an illegal type that might lead to repeatedly splitting the input
1908 // and then widening it. To avoid this, we widen the input only if
1909 // it results in a legal type.
1910 if (WidenNumElts % InVTNumElts == 0) {
1911 // Widen the input and call convert on the widened input vector.
1912 unsigned NumConcat = WidenNumElts/InVTNumElts;
1913 SmallVector<SDValue, 16> Ops(NumConcat);
1915 SDValue UndefVal = DAG.getUNDEF(InVT);
1916 for (unsigned i = 1; i != NumConcat; ++i)
1919 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1920 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1924 if (InVTNumElts % WidenNumElts == 0) {
1925 // Extract the input and convert the shorten input vector.
1926 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1927 DAG.getIntPtrConstant(0));
1928 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1933 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1934 SmallVector<SDValue, 16> Ops(WidenNumElts);
1935 EVT EltVT = WidenVT.getVectorElementType();
1936 DTyOp = DAG.getValueType(EltVT);
1937 STyOp = DAG.getValueType(InEltVT);
1939 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1941 for (i=0; i < MinElts; ++i) {
1942 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1943 DAG.getIntPtrConstant(i));
1944 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1948 SDValue UndefVal = DAG.getUNDEF(EltVT);
1949 for (; i < WidenNumElts; ++i)
1952 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1955 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1956 EVT VT = N->getValueType(0);
1957 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1958 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1959 SDValue InOp = N->getOperand(0);
1960 SDValue Idx = N->getOperand(1);
1961 DebugLoc dl = N->getDebugLoc();
1963 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1964 InOp = GetWidenedVector(InOp);
1966 EVT InVT = InOp.getValueType();
1968 // Check if we can just return the input vector after widening.
1969 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1970 if (IdxVal == 0 && InVT == WidenVT)
1973 // Check if we can extract from the vector.
1974 unsigned InNumElts = InVT.getVectorNumElements();
1975 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1976 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1978 // We could try widening the input to the right length but for now, extract
1979 // the original elements, fill the rest with undefs and build a vector.
1980 SmallVector<SDValue, 16> Ops(WidenNumElts);
1981 EVT EltVT = VT.getVectorElementType();
1982 unsigned NumElts = VT.getVectorNumElements();
1984 for (i=0; i < NumElts; ++i)
1985 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1986 DAG.getIntPtrConstant(IdxVal+i));
1988 SDValue UndefVal = DAG.getUNDEF(EltVT);
1989 for (; i < WidenNumElts; ++i)
1991 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1994 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1995 SDValue InOp = GetWidenedVector(N->getOperand(0));
1996 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1997 InOp.getValueType(), InOp,
1998 N->getOperand(1), N->getOperand(2));
2001 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2002 LoadSDNode *LD = cast<LoadSDNode>(N);
2003 ISD::LoadExtType ExtType = LD->getExtensionType();
2006 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2007 if (ExtType != ISD::NON_EXTLOAD)
2008 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2010 Result = GenWidenVectorLoads(LdChain, LD);
2012 // If we generate a single load, we can use that for the chain. Otherwise,
2013 // build a factor node to remember the multiple loads are independent and
2016 if (LdChain.size() == 1)
2017 NewChain = LdChain[0];
2019 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
2020 &LdChain[0], LdChain.size());
2022 // Modified the chain - switch anything that used the old chain to use
2024 ReplaceValueWith(SDValue(N, 1), NewChain);
2029 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2030 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2031 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
2032 WidenVT, N->getOperand(0));
2035 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2036 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2037 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2039 SDValue Cond1 = N->getOperand(0);
2040 EVT CondVT = Cond1.getValueType();
2041 if (CondVT.isVector()) {
2042 EVT CondEltVT = CondVT.getVectorElementType();
2043 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2044 CondEltVT, WidenNumElts);
2045 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2046 Cond1 = GetWidenedVector(Cond1);
2048 if (Cond1.getValueType() != CondWidenVT)
2049 Cond1 = ModifyToType(Cond1, CondWidenVT);
2052 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2053 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2054 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2055 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
2056 WidenVT, Cond1, InOp1, InOp2);
2059 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2060 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2061 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2062 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
2063 InOp1.getValueType(), N->getOperand(0),
2064 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2067 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2068 assert(N->getValueType(0).isVector() ==
2069 N->getOperand(0).getValueType().isVector() &&
2070 "Scalar/Vector type mismatch");
2071 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2073 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2074 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2075 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2076 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
2077 InOp1, InOp2, N->getOperand(2));
2080 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2081 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2082 return DAG.getUNDEF(WidenVT);
2085 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2086 EVT VT = N->getValueType(0);
2087 DebugLoc dl = N->getDebugLoc();
2089 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2090 unsigned NumElts = VT.getVectorNumElements();
2091 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2093 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2094 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2096 // Adjust mask based on new input vector length.
2097 SmallVector<int, 16> NewMask;
2098 for (unsigned i = 0; i != NumElts; ++i) {
2099 int Idx = N->getMaskElt(i);
2100 if (Idx < (int)NumElts)
2101 NewMask.push_back(Idx);
2103 NewMask.push_back(Idx - NumElts + WidenNumElts);
2105 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2106 NewMask.push_back(-1);
2107 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2110 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2111 assert(N->getValueType(0).isVector() &&
2112 N->getOperand(0).getValueType().isVector() &&
2113 "Operands must be vectors");
2114 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2115 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2117 SDValue InOp1 = N->getOperand(0);
2118 EVT InVT = InOp1.getValueType();
2119 assert(InVT.isVector() && "can not widen non vector type");
2120 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2121 InVT.getVectorElementType(), WidenNumElts);
2122 InOp1 = GetWidenedVector(InOp1);
2123 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2125 // Assume that the input and output will be widen appropriately. If not,
2126 // we will have to unroll it at some point.
2127 assert(InOp1.getValueType() == WidenInVT &&
2128 InOp2.getValueType() == WidenInVT &&
2129 "Input not widened to expected type!");
2131 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2132 WidenVT, InOp1, InOp2, N->getOperand(2));
2136 //===----------------------------------------------------------------------===//
2137 // Widen Vector Operand
2138 //===----------------------------------------------------------------------===//
2139 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2140 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2143 SDValue Res = SDValue();
2145 // See if the target wants to custom widen this node.
2146 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2149 switch (N->getOpcode()) {
2152 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2156 llvm_unreachable("Do not know how to widen this operator's operand!");
2158 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2159 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2160 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2161 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2162 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2163 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2165 case ISD::FP_EXTEND:
2166 case ISD::FP_TO_SINT:
2167 case ISD::FP_TO_UINT:
2168 case ISD::SINT_TO_FP:
2169 case ISD::UINT_TO_FP:
2171 case ISD::SIGN_EXTEND:
2172 case ISD::ZERO_EXTEND:
2173 case ISD::ANY_EXTEND:
2174 Res = WidenVecOp_Convert(N);
2178 // If Res is null, the sub-method took care of registering the result.
2179 if (!Res.getNode()) return false;
2181 // If the result is N, the sub-method updated N in place. Tell the legalizer
2183 if (Res.getNode() == N)
2187 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2188 "Invalid operand expansion");
2190 ReplaceValueWith(SDValue(N, 0), Res);
2194 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2195 // Since the result is legal and the input is illegal, it is unlikely
2196 // that we can fix the input to a legal type so unroll the convert
2197 // into some scalar code and create a nasty build vector.
2198 EVT VT = N->getValueType(0);
2199 EVT EltVT = VT.getVectorElementType();
2200 DebugLoc dl = N->getDebugLoc();
2201 unsigned NumElts = VT.getVectorNumElements();
2202 SDValue InOp = N->getOperand(0);
2203 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2204 InOp = GetWidenedVector(InOp);
2205 EVT InVT = InOp.getValueType();
2206 EVT InEltVT = InVT.getVectorElementType();
2208 unsigned Opcode = N->getOpcode();
2209 SmallVector<SDValue, 16> Ops(NumElts);
2210 for (unsigned i=0; i < NumElts; ++i)
2211 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2212 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2213 DAG.getIntPtrConstant(i)));
2215 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2218 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2219 EVT VT = N->getValueType(0);
2220 SDValue InOp = GetWidenedVector(N->getOperand(0));
2221 EVT InWidenVT = InOp.getValueType();
2222 DebugLoc dl = N->getDebugLoc();
2224 // Check if we can convert between two legal vector types and extract.
2225 unsigned InWidenSize = InWidenVT.getSizeInBits();
2226 unsigned Size = VT.getSizeInBits();
2227 // x86mmx is not an acceptable vector element type, so don't try.
2228 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2229 unsigned NewNumElts = InWidenSize / Size;
2230 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2231 if (TLI.isTypeLegal(NewVT)) {
2232 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2233 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2234 DAG.getIntPtrConstant(0));
2238 return CreateStackStoreLoad(InOp, VT);
2241 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2242 // If the input vector is not legal, it is likely that we will not find a
2243 // legal vector of the same size. Replace the concatenate vector with a
2244 // nasty build vector.
2245 EVT VT = N->getValueType(0);
2246 EVT EltVT = VT.getVectorElementType();
2247 DebugLoc dl = N->getDebugLoc();
2248 unsigned NumElts = VT.getVectorNumElements();
2249 SmallVector<SDValue, 16> Ops(NumElts);
2251 EVT InVT = N->getOperand(0).getValueType();
2252 unsigned NumInElts = InVT.getVectorNumElements();
2255 unsigned NumOperands = N->getNumOperands();
2256 for (unsigned i=0; i < NumOperands; ++i) {
2257 SDValue InOp = N->getOperand(i);
2258 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2259 InOp = GetWidenedVector(InOp);
2260 for (unsigned j=0; j < NumInElts; ++j)
2261 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2262 DAG.getIntPtrConstant(j));
2264 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2267 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2268 SDValue InOp = GetWidenedVector(N->getOperand(0));
2269 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2270 N->getValueType(0), InOp, N->getOperand(1));
2273 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2274 SDValue InOp = GetWidenedVector(N->getOperand(0));
2275 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2276 N->getValueType(0), InOp, N->getOperand(1));
2279 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2280 // We have to widen the value but we want only to store the original
2282 StoreSDNode *ST = cast<StoreSDNode>(N);
2284 SmallVector<SDValue, 16> StChain;
2285 if (ST->isTruncatingStore())
2286 GenWidenVectorTruncStores(StChain, ST);
2288 GenWidenVectorStores(StChain, ST);
2290 if (StChain.size() == 1)
2293 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2294 MVT::Other,&StChain[0],StChain.size());
2297 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2298 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2299 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2300 DebugLoc dl = N->getDebugLoc();
2302 // WARNING: In this code we widen the compare instruction with garbage.
2303 // This garbage may contain denormal floats which may be slow. Is this a real
2304 // concern ? Should we zero the unused lanes if this is a float compare ?
2306 // Get a new SETCC node to compare the newly widened operands.
2307 // Only some of the compared elements are legal.
2308 EVT SVT = TLI.getSetCCResultType(InOp0.getValueType());
2309 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2310 SVT, InOp0, InOp1, N->getOperand(2));
2312 // Extract the needed results from the result vector.
2313 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2314 SVT.getVectorElementType(),
2315 N->getValueType(0).getVectorNumElements());
2316 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2317 ResVT, WideSETCC, DAG.getIntPtrConstant(0));
2319 return PromoteTargetBoolean(CC, N->getValueType(0));
2323 //===----------------------------------------------------------------------===//
2324 // Vector Widening Utilities
2325 //===----------------------------------------------------------------------===//
2327 // Utility function to find the type to chop up a widen vector for load/store
2328 // TLI: Target lowering used to determine legal types.
2329 // Width: Width left need to load/store.
2330 // WidenVT: The widen vector type to load to/store from
2331 // Align: If 0, don't allow use of a wider type
2332 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2334 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2335 unsigned Width, EVT WidenVT,
2336 unsigned Align = 0, unsigned WidenEx = 0) {
2337 EVT WidenEltVT = WidenVT.getVectorElementType();
2338 unsigned WidenWidth = WidenVT.getSizeInBits();
2339 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2340 unsigned AlignInBits = Align*8;
2342 // If we have one element to load/store, return it.
2343 EVT RetVT = WidenEltVT;
2344 if (Width == WidenEltWidth)
2347 // See if there is larger legal integer than the element type to load/store
2349 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2350 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2351 EVT MemVT((MVT::SimpleValueType) VT);
2352 unsigned MemVTWidth = MemVT.getSizeInBits();
2353 if (MemVT.getSizeInBits() <= WidenEltWidth)
2355 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2356 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2357 (MemVTWidth <= Width ||
2358 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2364 // See if there is a larger vector type to load/store that has the same vector
2365 // element type and is evenly divisible with the WidenVT.
2366 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2367 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2368 EVT MemVT = (MVT::SimpleValueType) VT;
2369 unsigned MemVTWidth = MemVT.getSizeInBits();
2370 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2371 (WidenWidth % MemVTWidth) == 0 &&
2372 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2373 (MemVTWidth <= Width ||
2374 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2375 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2383 // Builds a vector type from scalar loads
2384 // VecTy: Resulting Vector type
2385 // LDOps: Load operators to build a vector type
2386 // [Start,End) the list of loads to use.
2387 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2388 SmallVector<SDValue, 16>& LdOps,
2389 unsigned Start, unsigned End) {
2390 DebugLoc dl = LdOps[Start].getDebugLoc();
2391 EVT LdTy = LdOps[Start].getValueType();
2392 unsigned Width = VecTy.getSizeInBits();
2393 unsigned NumElts = Width / LdTy.getSizeInBits();
2394 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2397 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2399 for (unsigned i = Start + 1; i != End; ++i) {
2400 EVT NewLdTy = LdOps[i].getValueType();
2401 if (NewLdTy != LdTy) {
2402 NumElts = Width / NewLdTy.getSizeInBits();
2403 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2404 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2405 // Readjust position and vector position based on new load type
2406 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2409 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2410 DAG.getIntPtrConstant(Idx++));
2412 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2415 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2417 // The strategy assumes that we can efficiently load powers of two widths.
2418 // The routines chops the vector into the largest vector loads with the same
2419 // element type or scalar loads and then recombines it to the widen vector
2421 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2422 unsigned WidenWidth = WidenVT.getSizeInBits();
2423 EVT LdVT = LD->getMemoryVT();
2424 DebugLoc dl = LD->getDebugLoc();
2425 assert(LdVT.isVector() && WidenVT.isVector());
2426 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2429 SDValue Chain = LD->getChain();
2430 SDValue BasePtr = LD->getBasePtr();
2431 unsigned Align = LD->getAlignment();
2432 bool isVolatile = LD->isVolatile();
2433 bool isNonTemporal = LD->isNonTemporal();
2434 bool isInvariant = LD->isInvariant();
2436 int LdWidth = LdVT.getSizeInBits();
2437 int WidthDiff = WidenWidth - LdWidth; // Difference
2438 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2440 // Find the vector type that can load from.
2441 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2442 int NewVTWidth = NewVT.getSizeInBits();
2443 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2444 isVolatile, isNonTemporal, isInvariant, Align);
2445 LdChain.push_back(LdOp.getValue(1));
2447 // Check if we can load the element with one instruction
2448 if (LdWidth <= NewVTWidth) {
2449 if (!NewVT.isVector()) {
2450 unsigned NumElts = WidenWidth / NewVTWidth;
2451 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2452 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2453 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2455 if (NewVT == WidenVT)
2458 assert(WidenWidth % NewVTWidth == 0);
2459 unsigned NumConcat = WidenWidth / NewVTWidth;
2460 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2461 SDValue UndefVal = DAG.getUNDEF(NewVT);
2462 ConcatOps[0] = LdOp;
2463 for (unsigned i = 1; i != NumConcat; ++i)
2464 ConcatOps[i] = UndefVal;
2465 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2469 // Load vector by using multiple loads from largest vector to scalar
2470 SmallVector<SDValue, 16> LdOps;
2471 LdOps.push_back(LdOp);
2473 LdWidth -= NewVTWidth;
2474 unsigned Offset = 0;
2476 while (LdWidth > 0) {
2477 unsigned Increment = NewVTWidth / 8;
2478 Offset += Increment;
2479 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2480 DAG.getIntPtrConstant(Increment));
2483 if (LdWidth < NewVTWidth) {
2484 // Our current type we are using is too large, find a better size
2485 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2486 NewVTWidth = NewVT.getSizeInBits();
2487 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2488 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2489 isNonTemporal, isInvariant, MinAlign(Align, Increment));
2490 LdChain.push_back(L.getValue(1));
2491 if (L->getValueType(0).isVector()) {
2492 SmallVector<SDValue, 16> Loads;
2494 unsigned size = L->getValueSizeInBits(0);
2495 while (size < LdOp->getValueSizeInBits(0)) {
2496 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
2497 size += L->getValueSizeInBits(0);
2499 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
2500 &Loads[0], Loads.size());
2503 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2504 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2505 isNonTemporal, isInvariant, MinAlign(Align, Increment));
2506 LdChain.push_back(L.getValue(1));
2512 LdWidth -= NewVTWidth;
2515 // Build the vector from the loads operations
2516 unsigned End = LdOps.size();
2517 if (!LdOps[0].getValueType().isVector())
2518 // All the loads are scalar loads.
2519 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2521 // If the load contains vectors, build the vector using concat vector.
2522 // All of the vectors used to loads are power of 2 and the scalars load
2523 // can be combined to make a power of 2 vector.
2524 SmallVector<SDValue, 16> ConcatOps(End);
2527 EVT LdTy = LdOps[i].getValueType();
2528 // First combine the scalar loads to a vector
2529 if (!LdTy.isVector()) {
2530 for (--i; i >= 0; --i) {
2531 LdTy = LdOps[i].getValueType();
2532 if (LdTy.isVector())
2535 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2537 ConcatOps[--Idx] = LdOps[i];
2538 for (--i; i >= 0; --i) {
2539 EVT NewLdTy = LdOps[i].getValueType();
2540 if (NewLdTy != LdTy) {
2541 // Create a larger vector
2542 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2543 &ConcatOps[Idx], End - Idx);
2547 ConcatOps[--Idx] = LdOps[i];
2550 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2551 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2552 &ConcatOps[Idx], End - Idx);
2554 // We need to fill the rest with undefs to build the vector
2555 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2556 SmallVector<SDValue, 16> WidenOps(NumOps);
2557 SDValue UndefVal = DAG.getUNDEF(LdTy);
2560 for (; i != End-Idx; ++i)
2561 WidenOps[i] = ConcatOps[Idx+i];
2562 for (; i != NumOps; ++i)
2563 WidenOps[i] = UndefVal;
2565 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2569 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2571 ISD::LoadExtType ExtType) {
2572 // For extension loads, it may not be more efficient to chop up the vector
2573 // and then extended it. Instead, we unroll the load and build a new vector.
2574 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2575 EVT LdVT = LD->getMemoryVT();
2576 DebugLoc dl = LD->getDebugLoc();
2577 assert(LdVT.isVector() && WidenVT.isVector());
2580 SDValue Chain = LD->getChain();
2581 SDValue BasePtr = LD->getBasePtr();
2582 unsigned Align = LD->getAlignment();
2583 bool isVolatile = LD->isVolatile();
2584 bool isNonTemporal = LD->isNonTemporal();
2586 EVT EltVT = WidenVT.getVectorElementType();
2587 EVT LdEltVT = LdVT.getVectorElementType();
2588 unsigned NumElts = LdVT.getVectorNumElements();
2590 // Load each element and widen
2591 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2592 SmallVector<SDValue, 16> Ops(WidenNumElts);
2593 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2594 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2595 LD->getPointerInfo(),
2596 LdEltVT, isVolatile, isNonTemporal, Align);
2597 LdChain.push_back(Ops[0].getValue(1));
2598 unsigned i = 0, Offset = Increment;
2599 for (i=1; i < NumElts; ++i, Offset += Increment) {
2600 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2601 BasePtr, DAG.getIntPtrConstant(Offset));
2602 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2603 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2604 isVolatile, isNonTemporal, Align);
2605 LdChain.push_back(Ops[i].getValue(1));
2608 // Fill the rest with undefs
2609 SDValue UndefVal = DAG.getUNDEF(EltVT);
2610 for (; i != WidenNumElts; ++i)
2613 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2617 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2619 // The strategy assumes that we can efficiently store powers of two widths.
2620 // The routines chops the vector into the largest vector stores with the same
2621 // element type or scalar stores.
2622 SDValue Chain = ST->getChain();
2623 SDValue BasePtr = ST->getBasePtr();
2624 unsigned Align = ST->getAlignment();
2625 bool isVolatile = ST->isVolatile();
2626 bool isNonTemporal = ST->isNonTemporal();
2627 SDValue ValOp = GetWidenedVector(ST->getValue());
2628 DebugLoc dl = ST->getDebugLoc();
2630 EVT StVT = ST->getMemoryVT();
2631 unsigned StWidth = StVT.getSizeInBits();
2632 EVT ValVT = ValOp.getValueType();
2633 unsigned ValWidth = ValVT.getSizeInBits();
2634 EVT ValEltVT = ValVT.getVectorElementType();
2635 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2636 assert(StVT.getVectorElementType() == ValEltVT);
2638 int Idx = 0; // current index to store
2639 unsigned Offset = 0; // offset from base to store
2640 while (StWidth != 0) {
2641 // Find the largest vector type we can store with
2642 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2643 unsigned NewVTWidth = NewVT.getSizeInBits();
2644 unsigned Increment = NewVTWidth / 8;
2645 if (NewVT.isVector()) {
2646 unsigned NumVTElts = NewVT.getVectorNumElements();
2648 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2649 DAG.getIntPtrConstant(Idx));
2650 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2651 ST->getPointerInfo().getWithOffset(Offset),
2652 isVolatile, isNonTemporal,
2653 MinAlign(Align, Offset)));
2654 StWidth -= NewVTWidth;
2655 Offset += Increment;
2657 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2658 DAG.getIntPtrConstant(Increment));
2659 } while (StWidth != 0 && StWidth >= NewVTWidth);
2661 // Cast the vector to the scalar type we can store
2662 unsigned NumElts = ValWidth / NewVTWidth;
2663 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2664 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2665 // Readjust index position based on new vector type
2666 Idx = Idx * ValEltWidth / NewVTWidth;
2668 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2669 DAG.getIntPtrConstant(Idx++));
2670 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2671 ST->getPointerInfo().getWithOffset(Offset),
2672 isVolatile, isNonTemporal,
2673 MinAlign(Align, Offset)));
2674 StWidth -= NewVTWidth;
2675 Offset += Increment;
2676 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2677 DAG.getIntPtrConstant(Increment));
2678 } while (StWidth != 0 && StWidth >= NewVTWidth);
2679 // Restore index back to be relative to the original widen element type
2680 Idx = Idx * NewVTWidth / ValEltWidth;
2686 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2688 // For extension loads, it may not be more efficient to truncate the vector
2689 // and then store it. Instead, we extract each element and then store it.
2690 SDValue Chain = ST->getChain();
2691 SDValue BasePtr = ST->getBasePtr();
2692 unsigned Align = ST->getAlignment();
2693 bool isVolatile = ST->isVolatile();
2694 bool isNonTemporal = ST->isNonTemporal();
2695 SDValue ValOp = GetWidenedVector(ST->getValue());
2696 DebugLoc dl = ST->getDebugLoc();
2698 EVT StVT = ST->getMemoryVT();
2699 EVT ValVT = ValOp.getValueType();
2701 // It must be true that we the widen vector type is bigger than where
2702 // we need to store.
2703 assert(StVT.isVector() && ValOp.getValueType().isVector());
2704 assert(StVT.bitsLT(ValOp.getValueType()));
2706 // For truncating stores, we can not play the tricks of chopping legal
2707 // vector types and bit cast it to the right type. Instead, we unroll
2709 EVT StEltVT = StVT.getVectorElementType();
2710 EVT ValEltVT = ValVT.getVectorElementType();
2711 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2712 unsigned NumElts = StVT.getVectorNumElements();
2713 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2714 DAG.getIntPtrConstant(0));
2715 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2716 ST->getPointerInfo(), StEltVT,
2717 isVolatile, isNonTemporal, Align));
2718 unsigned Offset = Increment;
2719 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2720 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2721 BasePtr, DAG.getIntPtrConstant(Offset));
2722 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2723 DAG.getIntPtrConstant(0));
2724 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2725 ST->getPointerInfo().getWithOffset(Offset),
2726 StEltVT, isVolatile, isNonTemporal,
2727 MinAlign(Align, Offset)));
2731 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2732 /// input vector must have the same element type as NVT.
2733 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2734 // Note that InOp might have been widened so it might already have
2735 // the right width or it might need be narrowed.
2736 EVT InVT = InOp.getValueType();
2737 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2738 "input and widen element type must match");
2739 DebugLoc dl = InOp.getDebugLoc();
2741 // Check if InOp already has the right width.
2745 unsigned InNumElts = InVT.getVectorNumElements();
2746 unsigned WidenNumElts = NVT.getVectorNumElements();
2747 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2748 unsigned NumConcat = WidenNumElts / InNumElts;
2749 SmallVector<SDValue, 16> Ops(NumConcat);
2750 SDValue UndefVal = DAG.getUNDEF(InVT);
2752 for (unsigned i = 1; i != NumConcat; ++i)
2755 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2758 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2759 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2760 DAG.getIntPtrConstant(0));
2762 // Fall back to extract and build.
2763 SmallVector<SDValue, 16> Ops(WidenNumElts);
2764 EVT EltVT = NVT.getVectorElementType();
2765 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2767 for (Idx = 0; Idx < MinNumElts; ++Idx)
2768 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2769 DAG.getIntPtrConstant(Idx));
2771 SDValue UndefVal = DAG.getUNDEF(EltVT);
2772 for ( ; Idx < WidenNumElts; ++Idx)
2773 Ops[Idx] = UndefVal;
2774 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);