1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108 SDValue ExpandABSDIFF(SDValue Op);
110 /// \brief Implements vector promotion.
112 /// This is essentially just bitcasting the operands to a different type and
113 /// bitcasting the result back to the original type.
114 SDValue Promote(SDValue Op);
116 /// \brief Implements [SU]INT_TO_FP vector promotion.
118 /// This is a [zs]ext of the input operand to the next size up.
119 SDValue PromoteINT_TO_FP(SDValue Op);
121 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
123 /// It is promoted to the next size up integer type. The result is then
124 /// truncated back to the original type.
125 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
128 /// \brief Begin legalizer the vector operations in the DAG.
130 VectorLegalizer(SelectionDAG& dag) :
131 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
134 bool VectorLegalizer::Run() {
135 // Before we start legalizing vector nodes, check if there are any vectors.
136 bool HasVectors = false;
137 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
138 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
139 // Check if the values of the nodes contain vectors. We don't need to check
140 // the operands because we are going to check their values at some point.
141 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
143 HasVectors |= J->isVector();
145 // If we found a vector node we can start the legalization.
150 // If this basic block has no vectors then no need to legalize vectors.
154 // The legalize process is inherently a bottom-up recursive process (users
155 // legalize their uses before themselves). Given infinite stack space, we
156 // could just start legalizing on the root and traverse the whole graph. In
157 // practice however, this causes us to run out of stack space on large basic
158 // blocks. To avoid this problem, compute an ordering of the nodes where each
159 // node is only legalized after all of its operands are legalized.
160 DAG.AssignTopologicalOrder();
161 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
162 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
163 LegalizeOp(SDValue(I, 0));
165 // Finally, it's possible the root changed. Get the new root.
166 SDValue OldRoot = DAG.getRoot();
167 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
168 DAG.setRoot(LegalizedNodes[OldRoot]);
170 LegalizedNodes.clear();
172 // Remove dead nodes now.
173 DAG.RemoveDeadNodes();
178 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
179 // Generic legalization: just pass the operand through.
180 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
181 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
182 return Result.getValue(Op.getResNo());
185 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
186 // Note that LegalizeOp may be reentered even from single-use nodes, which
187 // means that we always must cache transformed nodes.
188 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
189 if (I != LegalizedNodes.end()) return I->second;
191 SDNode* Node = Op.getNode();
193 // Legalize the operands
194 SmallVector<SDValue, 8> Ops;
195 for (const SDValue &Op : Node->op_values())
196 Ops.push_back(LegalizeOp(Op));
198 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
200 bool HasVectorValue = false;
201 if (Op.getOpcode() == ISD::LOAD) {
202 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
203 ISD::LoadExtType ExtType = LD->getExtensionType();
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
205 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
206 LD->getMemoryVT())) {
207 default: llvm_unreachable("This action is not supported yet!");
208 case TargetLowering::Legal:
209 return TranslateLegalizeResults(Op, Result);
210 case TargetLowering::Custom:
211 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
212 if (Lowered == Result)
213 return TranslateLegalizeResults(Op, Lowered);
215 if (Lowered->getNumValues() != Op->getNumValues()) {
216 // This expanded to something other than the load. Assume the
217 // lowering code took care of any chain values, and just handle the
219 assert(Result.getValue(1).use_empty() &&
220 "There are still live users of the old chain!");
221 return LegalizeOp(Lowered);
223 return TranslateLegalizeResults(Op, Lowered);
226 case TargetLowering::Expand:
228 return LegalizeOp(ExpandLoad(Op));
230 } else if (Op.getOpcode() == ISD::STORE) {
231 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
232 EVT StVT = ST->getMemoryVT();
233 MVT ValVT = ST->getValue().getSimpleValueType();
234 if (StVT.isVector() && ST->isTruncatingStore())
235 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
236 default: llvm_unreachable("This action is not supported yet!");
237 case TargetLowering::Legal:
238 return TranslateLegalizeResults(Op, Result);
239 case TargetLowering::Custom: {
240 SDValue Lowered = TLI.LowerOperation(Result, DAG);
241 Changed = Lowered != Result;
242 return TranslateLegalizeResults(Op, Lowered);
244 case TargetLowering::Expand:
246 return LegalizeOp(ExpandStore(Op));
248 } else if (Op.getOpcode() == ISD::MSCATTER)
249 HasVectorValue = true;
251 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
254 HasVectorValue |= J->isVector();
256 return TranslateLegalizeResults(Op, Result);
259 switch (Op.getOpcode()) {
261 return TranslateLegalizeResults(Op, Result);
285 case ISD::CTLZ_ZERO_UNDEF:
286 case ISD::CTTZ_ZERO_UNDEF:
292 case ISD::ZERO_EXTEND:
293 case ISD::ANY_EXTEND:
295 case ISD::SIGN_EXTEND:
296 case ISD::FP_TO_SINT:
297 case ISD::FP_TO_UINT:
318 case ISD::FNEARBYINT:
324 case ISD::SIGN_EXTEND_INREG:
325 case ISD::ANY_EXTEND_VECTOR_INREG:
326 case ISD::SIGN_EXTEND_VECTOR_INREG:
327 case ISD::ZERO_EXTEND_VECTOR_INREG:
334 QueryType = Node->getValueType(0);
336 case ISD::FP_ROUND_INREG:
337 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
339 case ISD::SINT_TO_FP:
340 case ISD::UINT_TO_FP:
341 QueryType = Node->getOperand(0).getValueType();
344 QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
348 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
349 case TargetLowering::Promote:
350 Result = Promote(Op);
353 case TargetLowering::Legal:
355 case TargetLowering::Custom: {
356 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
357 if (Tmp1.getNode()) {
363 case TargetLowering::Expand:
367 // Make sure that the generated code is itself legal.
369 Result = LegalizeOp(Result);
373 // Note that LegalizeOp may be reentered even from single-use nodes, which
374 // means that we always must cache transformed nodes.
375 AddLegalizedOperand(Op, Result);
379 SDValue VectorLegalizer::Promote(SDValue Op) {
380 // For a few operations there is a specific concept for promotion based on
381 // the operand's type.
382 switch (Op.getOpcode()) {
383 case ISD::SINT_TO_FP:
384 case ISD::UINT_TO_FP:
385 // "Promote" the operation by extending the operand.
386 return PromoteINT_TO_FP(Op);
387 case ISD::FP_TO_UINT:
388 case ISD::FP_TO_SINT:
389 // Promote the operation by extending the operand.
390 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
393 // There are currently two cases of vector promotion:
394 // 1) Bitcasting a vector of integers to a different type to a vector of the
395 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
396 // 2) Extending a vector of floats to a vector of the same number of larger
397 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
398 MVT VT = Op.getSimpleValueType();
399 assert(Op.getNode()->getNumValues() == 1 &&
400 "Can't promote a vector with multiple results!");
401 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
403 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
405 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
406 if (Op.getOperand(j).getValueType().isVector())
409 .getVectorElementType()
410 .isFloatingPoint() &&
411 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
412 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
414 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
416 Operands[j] = Op.getOperand(j);
419 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
420 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
421 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
422 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
423 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
425 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
428 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
429 // INT_TO_FP operations may require the input operand be promoted even
430 // when the type is otherwise legal.
431 EVT VT = Op.getOperand(0).getValueType();
432 assert(Op.getNode()->getNumValues() == 1 &&
433 "Can't promote a vector with multiple results!");
435 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
436 // by widening the vector w/ the same element width and twice the number
437 // of elements. We want the other way around, the same number of elements,
438 // each twice the width.
440 // Increase the bitwidth of the element to the next pow-of-two
441 // (which is greater than 8 bits).
443 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
444 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
446 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
448 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
450 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
451 if (Op.getOperand(j).getValueType().isVector())
452 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
454 Operands[j] = Op.getOperand(j);
457 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
460 // For FP_TO_INT we promote the result type to a vector type with wider
461 // elements and then truncate the result. This is different from the default
462 // PromoteVector which uses bitcast to promote thus assumning that the
463 // promoted vector type has the same overall size.
464 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
465 assert(Op.getNode()->getNumValues() == 1 &&
466 "Can't promote a vector with multiple results!");
467 EVT VT = Op.getValueType();
472 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
473 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
474 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
475 NewOpc = ISD::FP_TO_SINT;
478 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
479 NewOpc = ISD::FP_TO_UINT;
485 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
486 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
490 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
492 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
493 SDValue Chain = LD->getChain();
494 SDValue BasePTR = LD->getBasePtr();
495 EVT SrcVT = LD->getMemoryVT();
496 ISD::LoadExtType ExtType = LD->getExtensionType();
498 SmallVector<SDValue, 8> Vals;
499 SmallVector<SDValue, 8> LoadChains;
500 unsigned NumElem = SrcVT.getVectorNumElements();
502 EVT SrcEltVT = SrcVT.getScalarType();
503 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
505 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
506 // When elements in a vector is not byte-addressable, we cannot directly
507 // load each element by advancing pointer, which could only address bytes.
508 // Instead, we load all significant words, mask bits off, and concatenate
509 // them to form each element. Finally, they are extended to destination
510 // scalar type to build the destination vector.
511 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
513 assert(WideVT.isRound() &&
514 "Could not handle the sophisticated case when the widest integer is"
516 assert(WideVT.bitsGE(SrcEltVT) &&
517 "Type is not legalized?");
519 unsigned WideBytes = WideVT.getStoreSize();
521 unsigned RemainingBytes = SrcVT.getStoreSize();
522 SmallVector<SDValue, 8> LoadVals;
524 while (RemainingBytes > 0) {
526 unsigned LoadBytes = WideBytes;
528 if (RemainingBytes >= LoadBytes) {
529 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
530 LD->getPointerInfo().getWithOffset(Offset),
531 LD->isVolatile(), LD->isNonTemporal(),
533 MinAlign(LD->getAlignment(), Offset),
537 while (RemainingBytes < LoadBytes) {
538 LoadBytes >>= 1; // Reduce the load size by half.
539 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
541 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
542 LD->getPointerInfo().getWithOffset(Offset),
543 LoadVT, LD->isVolatile(),
544 LD->isNonTemporal(), LD->isInvariant(),
545 MinAlign(LD->getAlignment(), Offset),
549 RemainingBytes -= LoadBytes;
551 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
552 DAG.getConstant(LoadBytes, dl,
553 BasePTR.getValueType()));
555 LoadVals.push_back(ScalarLoad.getValue(0));
556 LoadChains.push_back(ScalarLoad.getValue(1));
559 // Extract bits, pack and extend/trunc them into destination type.
560 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
561 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
563 unsigned BitOffset = 0;
564 unsigned WideIdx = 0;
565 unsigned WideBits = WideVT.getSizeInBits();
567 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
568 SDValue Lo, Hi, ShAmt;
570 if (BitOffset < WideBits) {
571 ShAmt = DAG.getConstant(
572 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
573 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
574 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
577 BitOffset += SrcEltBits;
578 if (BitOffset >= WideBits) {
580 BitOffset -= WideBits;
582 ShAmt = DAG.getConstant(
583 SrcEltBits - BitOffset, dl,
584 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
585 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
586 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
591 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
594 default: llvm_unreachable("Unknown extended-load op!");
596 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
599 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
603 DAG.getConstant(WideBits - SrcEltBits, dl,
604 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
605 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
606 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
607 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
613 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
615 for (unsigned Idx=0; Idx<NumElem; Idx++) {
616 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
617 Op.getNode()->getValueType(0).getScalarType(),
618 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
619 SrcVT.getScalarType(),
620 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
621 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
623 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
624 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
626 Vals.push_back(ScalarLoad.getValue(0));
627 LoadChains.push_back(ScalarLoad.getValue(1));
631 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
632 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
633 Op.getNode()->getValueType(0), Vals);
635 AddLegalizedOperand(Op.getValue(0), Value);
636 AddLegalizedOperand(Op.getValue(1), NewChain);
638 return (Op.getResNo() ? NewChain : Value);
641 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
643 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
644 SDValue Chain = ST->getChain();
645 SDValue BasePTR = ST->getBasePtr();
646 SDValue Value = ST->getValue();
647 EVT StVT = ST->getMemoryVT();
649 unsigned Alignment = ST->getAlignment();
650 bool isVolatile = ST->isVolatile();
651 bool isNonTemporal = ST->isNonTemporal();
652 AAMDNodes AAInfo = ST->getAAInfo();
654 unsigned NumElem = StVT.getVectorNumElements();
655 // The type of the data we want to save
656 EVT RegVT = Value.getValueType();
657 EVT RegSclVT = RegVT.getScalarType();
658 // The type of data as saved in memory.
659 EVT MemSclVT = StVT.getScalarType();
661 // Cast floats into integers
662 unsigned ScalarSize = MemSclVT.getSizeInBits();
664 // Round odd types to the next pow of two.
665 if (!isPowerOf2_32(ScalarSize))
666 ScalarSize = NextPowerOf2(ScalarSize);
668 // Store Stride in bytes
669 unsigned Stride = ScalarSize/8;
670 // Extract each of the elements from the original vector
671 // and save them into memory individually.
672 SmallVector<SDValue, 8> Stores;
673 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
674 SDValue Ex = DAG.getNode(
675 ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value,
676 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
678 // This scalar TruncStore may be illegal, but we legalize it later.
679 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
680 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
681 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
684 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
685 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
687 Stores.push_back(Store);
689 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
690 AddLegalizedOperand(Op, TF);
694 SDValue VectorLegalizer::Expand(SDValue Op) {
695 switch (Op->getOpcode()) {
696 case ISD::SIGN_EXTEND_INREG:
697 return ExpandSEXTINREG(Op);
698 case ISD::ANY_EXTEND_VECTOR_INREG:
699 return ExpandANY_EXTEND_VECTOR_INREG(Op);
700 case ISD::SIGN_EXTEND_VECTOR_INREG:
701 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
702 case ISD::ZERO_EXTEND_VECTOR_INREG:
703 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
705 return ExpandBSWAP(Op);
707 return ExpandVSELECT(Op);
709 return ExpandSELECT(Op);
710 case ISD::UINT_TO_FP:
711 return ExpandUINT_TO_FLOAT(Op);
713 return ExpandFNEG(Op);
715 return UnrollVSETCC(Op);
718 return ExpandABSDIFF(Op);
720 return DAG.UnrollVectorOp(Op.getNode());
724 SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {
726 SDValue Op0 = Op.getOperand(0);
727 SDValue Op1 = Op.getOperand(1);
728 EVT VT = Op.getValueType();
730 // For unsigned intrinsic, promote the type to handle unsigned overflow.
731 bool isUabsdiff = (Op->getOpcode() == ISD::UABSDIFF);
733 VT = VT.widenIntegerVectorElementType(*DAG.getContext());
734 Op0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op0);
735 Op1 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op1);
739 Flags.setNoSignedWrap(!isUabsdiff);
740 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op0, Op1, &Flags);
742 return DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Sub);
745 DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(DAG.getDataLayout(),
746 *DAG.getContext(), VT),
747 Sub, DAG.getConstant(0, dl, VT), DAG.getCondCode(ISD::SETGE));
748 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Sub, &Flags);
749 return DAG.getNode(ISD::VSELECT, dl, VT, Cmp, Sub, Neg);
752 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
753 // Lower a select instruction where the condition is a scalar and the
754 // operands are vectors. Lower this select to VSELECT and implement it
755 // using XOR AND OR. The selector bit is broadcasted.
756 EVT VT = Op.getValueType();
759 SDValue Mask = Op.getOperand(0);
760 SDValue Op1 = Op.getOperand(1);
761 SDValue Op2 = Op.getOperand(2);
763 assert(VT.isVector() && !Mask.getValueType().isVector()
764 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
766 unsigned NumElem = VT.getVectorNumElements();
768 // If we can't even use the basic vector operations of
769 // AND,OR,XOR, we will have to scalarize the op.
770 // Notice that the operation may be 'promoted' which means that it is
771 // 'bitcasted' to another type which is handled.
772 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
773 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
774 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
775 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
776 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
777 return DAG.UnrollVectorOp(Op.getNode());
779 // Generate a mask operand.
780 EVT MaskTy = VT.changeVectorElementTypeToInteger();
782 // What is the size of each element in the vector mask.
783 EVT BitTy = MaskTy.getScalarType();
785 Mask = DAG.getSelect(DL, BitTy, Mask,
786 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
788 DAG.getConstant(0, DL, BitTy));
790 // Broadcast the mask so that the entire vector is all-one or all zero.
791 SmallVector<SDValue, 8> Ops(NumElem, Mask);
792 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
794 // Bitcast the operands to be the same type as the mask.
795 // This is needed when we select between FP types because
796 // the mask is a vector of integers.
797 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
798 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
800 SDValue AllOnes = DAG.getConstant(
801 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
802 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
804 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
805 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
806 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
807 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
810 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
811 EVT VT = Op.getValueType();
813 // Make sure that the SRA and SHL instructions are available.
814 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
815 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
816 return DAG.UnrollVectorOp(Op.getNode());
819 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
821 unsigned BW = VT.getScalarType().getSizeInBits();
822 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
823 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
825 Op = Op.getOperand(0);
826 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
827 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
830 // Generically expand a vector anyext in register to a shuffle of the relevant
831 // lanes into the appropriate locations, with other lanes left undef.
832 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
834 EVT VT = Op.getValueType();
835 int NumElements = VT.getVectorNumElements();
836 SDValue Src = Op.getOperand(0);
837 EVT SrcVT = Src.getValueType();
838 int NumSrcElements = SrcVT.getVectorNumElements();
840 // Build a base mask of undef shuffles.
841 SmallVector<int, 16> ShuffleMask;
842 ShuffleMask.resize(NumSrcElements, -1);
844 // Place the extended lanes into the correct locations.
845 int ExtLaneScale = NumSrcElements / NumElements;
846 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
847 for (int i = 0; i < NumElements; ++i)
848 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
851 ISD::BITCAST, DL, VT,
852 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
855 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
857 EVT VT = Op.getValueType();
858 SDValue Src = Op.getOperand(0);
859 EVT SrcVT = Src.getValueType();
861 // First build an any-extend node which can be legalized above when we
862 // recurse through it.
863 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
865 // Now we need sign extend. Do this by shifting the elements. Even if these
866 // aren't legal operations, they have a better chance of being legalized
867 // without full scalarization than the sign extension does.
868 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
869 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
870 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
871 return DAG.getNode(ISD::SRA, DL, VT,
872 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
876 // Generically expand a vector zext in register to a shuffle of the relevant
877 // lanes into the appropriate locations, a blend of zero into the high bits,
878 // and a bitcast to the wider element type.
879 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
881 EVT VT = Op.getValueType();
882 int NumElements = VT.getVectorNumElements();
883 SDValue Src = Op.getOperand(0);
884 EVT SrcVT = Src.getValueType();
885 int NumSrcElements = SrcVT.getVectorNumElements();
887 // Build up a zero vector to blend into this one.
888 EVT SrcScalarVT = SrcVT.getScalarType();
889 SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
890 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
891 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
893 // Shuffle the incoming lanes into the correct position, and pull all other
894 // lanes from the zero vector.
895 SmallVector<int, 16> ShuffleMask;
896 ShuffleMask.reserve(NumSrcElements);
897 for (int i = 0; i < NumSrcElements; ++i)
898 ShuffleMask.push_back(i);
900 int ExtLaneScale = NumSrcElements / NumElements;
901 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
902 for (int i = 0; i < NumElements; ++i)
903 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
905 return DAG.getNode(ISD::BITCAST, DL, VT,
906 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
909 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
910 EVT VT = Op.getValueType();
912 // Generate a byte wise shuffle mask for the BSWAP.
913 SmallVector<int, 16> ShuffleMask;
914 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
915 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
916 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
917 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
919 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
921 // Only emit a shuffle if the mask is legal.
922 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
923 return DAG.UnrollVectorOp(Op.getNode());
926 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
927 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
929 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
932 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
933 // Implement VSELECT in terms of XOR, AND, OR
934 // on platforms which do not support blend natively.
937 SDValue Mask = Op.getOperand(0);
938 SDValue Op1 = Op.getOperand(1);
939 SDValue Op2 = Op.getOperand(2);
941 EVT VT = Mask.getValueType();
943 // If we can't even use the basic vector operations of
944 // AND,OR,XOR, we will have to scalarize the op.
945 // Notice that the operation may be 'promoted' which means that it is
946 // 'bitcasted' to another type which is handled.
947 // This operation also isn't safe with AND, OR, XOR when the boolean
948 // type is 0/1 as we need an all ones vector constant to mask with.
949 // FIXME: Sign extend 1 to all ones if thats legal on the target.
950 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
951 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
952 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
953 TLI.getBooleanContents(Op1.getValueType()) !=
954 TargetLowering::ZeroOrNegativeOneBooleanContent)
955 return DAG.UnrollVectorOp(Op.getNode());
957 // If the mask and the type are different sizes, unroll the vector op. This
958 // can occur when getSetCCResultType returns something that is different in
959 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
960 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
961 return DAG.UnrollVectorOp(Op.getNode());
963 // Bitcast the operands to be the same type as the mask.
964 // This is needed when we select between FP types because
965 // the mask is a vector of integers.
966 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
967 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
969 SDValue AllOnes = DAG.getConstant(
970 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT);
971 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
973 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
974 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
975 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
976 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
979 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
980 EVT VT = Op.getOperand(0).getValueType();
983 // Make sure that the SINT_TO_FP and SRL instructions are available.
984 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
985 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
986 return DAG.UnrollVectorOp(Op.getNode());
988 EVT SVT = VT.getScalarType();
989 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
990 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
992 unsigned BW = SVT.getSizeInBits();
993 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
995 // Constants to clear the upper part of the word.
996 // Notice that we can also use SHL+SHR, but using a constant is slightly
998 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
999 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1001 // Two to the power of half-word-size.
1002 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
1004 // Clear upper part of LO, lower HI
1005 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1006 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1008 // Convert hi and lo to floats
1009 // Convert the hi part back to the upper values
1010 // TODO: Can any fast-math-flags be set on these nodes?
1011 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1012 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1013 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1015 // Add the two halves
1016 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1020 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1021 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1023 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1024 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1025 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1026 Zero, Op.getOperand(0));
1028 return DAG.UnrollVectorOp(Op.getNode());
1031 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1032 EVT VT = Op.getValueType();
1033 unsigned NumElems = VT.getVectorNumElements();
1034 EVT EltVT = VT.getVectorElementType();
1035 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1036 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1038 SmallVector<SDValue, 8> Ops(NumElems);
1039 for (unsigned i = 0; i < NumElems; ++i) {
1040 SDValue LHSElem = DAG.getNode(
1041 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1042 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1043 SDValue RHSElem = DAG.getNode(
1044 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1045 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1046 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1047 TLI.getSetCCResultType(DAG.getDataLayout(),
1048 *DAG.getContext(), TmpEltVT),
1049 LHSElem, RHSElem, CC);
1050 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1051 DAG.getConstant(APInt::getAllOnesValue
1052 (EltVT.getSizeInBits()), dl, EltVT),
1053 DAG.getConstant(0, dl, EltVT));
1055 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1060 bool SelectionDAG::LegalizeVectors() {
1061 return VectorLegalizer(*this).Run();