1 //===-- LegalizeTypesSplit.cpp - Vector Splitting for LegalizeTypes -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements vector splitting support for LegalizeTypes. Vector
11 // splitting is the act of changing a computation in an invalid vector type to
12 // be a computation in multiple vectors of a smaller type. For example,
13 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
15 //===----------------------------------------------------------------------===//
17 #include "LegalizeTypes.h"
20 /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector
21 /// type that needs to be split. This handles non-power of two vectors.
22 static void GetSplitDestVTs(MVT::ValueType InVT,
23 MVT::ValueType &Lo, MVT::ValueType &Hi) {
24 MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT);
25 unsigned NumElements = MVT::getVectorNumElements(InVT);
26 if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector.
28 Lo = Hi = MVT::getVectorType(NewEltVT, NumElements);
29 } else { // Non-power-of-two vectors.
30 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements);
31 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
32 Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
33 Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
38 //===----------------------------------------------------------------------===//
39 // Result Vector Splitting
40 //===----------------------------------------------------------------------===//
42 /// SplitResult - This method is called when the specified result of the
43 /// specified node is found to need vector splitting. At this point, the node
44 /// may also have invalid operands or may have other results that need
45 /// legalization, we just know that (at least) one result needs vector
47 void DAGTypeLegalizer::SplitResult(SDNode *N, unsigned ResNo) {
48 DEBUG(cerr << "Expand node result: "; N->dump(&DAG); cerr << "\n");
52 // See if the target wants to custom expand this node.
53 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
54 TargetLowering::Custom) {
55 // If the target wants to, allow it to lower this itself.
56 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
57 // Everything that once used N now uses P. We are guaranteed that the
58 // result value types of N and the result value types of P match.
59 ReplaceNodeWith(N, P);
65 switch (N->getOpcode()) {
68 cerr << "SplitResult #" << ResNo << ": ";
69 N->dump(&DAG); cerr << "\n";
71 assert(0 && "Do not know how to split the result of this operator!");
74 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
75 case ISD::LOAD: SplitRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
76 case ISD::BUILD_PAIR: SplitRes_BUILD_PAIR(N, Lo, Hi); break;
77 case ISD::INSERT_VECTOR_ELT:SplitRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
78 case ISD::VECTOR_SHUFFLE: SplitRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
79 case ISD::BUILD_VECTOR: SplitRes_BUILD_VECTOR(N, Lo, Hi); break;
80 case ISD::CONCAT_VECTORS: SplitRes_CONCAT_VECTORS(N, Lo, Hi); break;
81 case ISD::BIT_CONVERT: SplitRes_BIT_CONVERT(N, Lo, Hi); break;
93 case ISD::UINT_TO_FP: SplitRes_UnOp(N, Lo, Hi); break;
109 case ISD::FREM: SplitRes_BinOp(N, Lo, Hi); break;
110 case ISD::FPOWI: SplitRes_FPOWI(N, Lo, Hi); break;
111 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
114 // If Lo/Hi is null, the sub-method took care of registering results etc.
116 SetSplitOp(SDOperand(N, ResNo), Lo, Hi);
119 void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
120 MVT::ValueType LoVT, HiVT;
121 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
123 Lo = DAG.getNode(ISD::UNDEF, LoVT);
124 Hi = DAG.getNode(ISD::UNDEF, HiVT);
127 void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
128 SDOperand &Lo, SDOperand &Hi) {
129 MVT::ValueType LoVT, HiVT;
130 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
132 SDOperand Ch = LD->getChain();
133 SDOperand Ptr = LD->getBasePtr();
134 const Value *SV = LD->getSrcValue();
135 int SVOffset = LD->getSrcValueOffset();
136 unsigned Alignment = LD->getAlignment();
137 bool isVolatile = LD->isVolatile();
139 Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
140 unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
141 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
142 DAG.getIntPtrConstant(IncrementSize));
143 SVOffset += IncrementSize;
144 Alignment = MinAlign(Alignment, IncrementSize);
145 Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
147 // Build a factor node to remember that this load is independent of the
149 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
152 // Legalized the chain result - switch anything that used the old chain to
154 ReplaceValueWith(SDOperand(LD, 1), TF);
157 void DAGTypeLegalizer::SplitRes_BUILD_PAIR(SDNode *N, SDOperand &Lo,
159 Lo = N->getOperand(0);
160 Hi = N->getOperand(1);
163 void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
165 GetSplitOp(N->getOperand(0), Lo, Hi);
166 unsigned Index = cast<ConstantSDNode>(N->getOperand(2))->getValue();
167 SDOperand ScalarOp = N->getOperand(1);
168 unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType());
169 if (Index < LoNumElts)
170 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp,
173 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, ScalarOp,
174 DAG.getConstant(Index - LoNumElts, TLI.getPointerTy()));
177 void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
178 SDOperand &Lo, SDOperand &Hi) {
179 // Build the low part.
180 SDOperand Mask = N->getOperand(2);
181 SmallVector<SDOperand, 16> Ops;
182 MVT::ValueType PtrVT = TLI.getPointerTy();
184 MVT::ValueType LoVT, HiVT;
185 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
186 MVT::ValueType EltVT = MVT::getVectorElementType(LoVT);
187 unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
188 unsigned NumElements = Mask.getNumOperands();
190 // Insert all of the elements from the input that are needed. We use
191 // buildvector of extractelement here because the input vectors will have
192 // to be legalized, so this makes the code simpler.
193 for (unsigned i = 0; i != LoNumElts; ++i) {
194 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
195 SDOperand InVec = N->getOperand(0);
196 if (Idx >= NumElements) {
197 InVec = N->getOperand(1);
200 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
201 DAG.getConstant(Idx, PtrVT)));
203 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
206 for (unsigned i = LoNumElts; i != NumElements; ++i) {
207 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
208 SDOperand InVec = N->getOperand(0);
209 if (Idx >= NumElements) {
210 InVec = N->getOperand(1);
213 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
214 DAG.getConstant(Idx, PtrVT)));
216 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
219 void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
221 MVT::ValueType LoVT, HiVT;
222 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
223 unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
224 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
225 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
227 SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
228 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
231 void DAGTypeLegalizer::SplitRes_CONCAT_VECTORS(SDNode *N,
232 SDOperand &Lo, SDOperand &Hi) {
233 // FIXME: Handle non-power-of-two vectors?
234 unsigned NumSubvectors = N->getNumOperands() / 2;
235 if (NumSubvectors == 1) {
236 Lo = N->getOperand(0);
237 Hi = N->getOperand(1);
241 MVT::ValueType LoVT, HiVT;
242 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
244 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
245 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
247 SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
248 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
251 void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
252 SDOperand &Lo, SDOperand &Hi) {
253 // We know the result is a vector. The input may be either a vector or a
255 MVT::ValueType LoVT, HiVT;
256 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
258 SDOperand InOp = N->getOperand(0);
259 MVT::ValueType InVT = InOp.getValueType();
260 MVT::ValueType NewInVT = TLI.getTypeToTransformTo(InVT);
262 switch (getTypeAction(InVT)) {
264 assert(false && "Unknown type action!");
270 // While it is tempting to extract the scalarized operand, check whether it
271 // needs expansion, and if so process it in the Expand case below, there is
272 // no guarantee that the scalarized operand has been processed yet. If it
273 // hasn't then the call to GetExpandedOp will abort. So just give up.
276 // A scalar to vector conversion, where the scalar needs expansion.
277 // Check that the vector is being split in two.
278 if (MVT::getSizeInBits(NewInVT) == MVT::getSizeInBits(LoVT)) {
279 // Convert each expanded piece of the scalar now.
280 GetExpandedOp(InOp, Lo, Hi);
281 if (TLI.isBigEndian())
283 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
284 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
289 // If the input is a vector that needs to be split, convert each split
290 // piece of the input now.
291 GetSplitOp(InOp, Lo, Hi);
292 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
293 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
297 // Lower the bit-convert to a store/load from the stack, then split the load.
298 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
299 SplitRes_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
302 void DAGTypeLegalizer::SplitRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
303 SDOperand LHSLo, LHSHi;
304 GetSplitOp(N->getOperand(0), LHSLo, LHSHi);
305 SDOperand RHSLo, RHSHi;
306 GetSplitOp(N->getOperand(1), RHSLo, RHSHi);
308 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
309 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
312 void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
313 // Get the dest types. This doesn't always match input types, e.g. int_to_fp.
314 MVT::ValueType LoVT, HiVT;
315 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
317 GetSplitOp(N->getOperand(0), Lo, Hi);
318 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
319 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
322 void DAGTypeLegalizer::SplitRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
323 GetSplitOp(N->getOperand(0), Lo, Hi);
324 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
325 Hi = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Hi, N->getOperand(1));
329 void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDOperand &Lo, SDOperand &Hi){
330 SDOperand LL, LH, RL, RH;
331 GetSplitOp(N->getOperand(1), LL, LH);
332 GetSplitOp(N->getOperand(2), RL, RH);
334 SDOperand Cond = N->getOperand(0);
335 Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL);
336 Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH);
340 //===----------------------------------------------------------------------===//
341 // Operand Vector Splitting
342 //===----------------------------------------------------------------------===//
344 /// SplitOperand - This method is called when the specified operand of the
345 /// specified node is found to need vector splitting. At this point, all of the
346 /// result types of the node are known to be legal, but other operands of the
347 /// node may need legalization as well as the specified one.
348 bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
349 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
353 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
354 TargetLowering::Custom)
355 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
359 switch (N->getOpcode()) {
362 cerr << "SplitOperand Op #" << OpNo << ": ";
363 N->dump(&DAG); cerr << "\n";
365 assert(0 && "Do not know how to split this operator's operand!");
367 case ISD::STORE: Res = SplitOp_STORE(cast<StoreSDNode>(N), OpNo); break;
368 case ISD::RET: Res = SplitOp_RET(N, OpNo); break;
370 case ISD::BIT_CONVERT: Res = SplitOp_BIT_CONVERT(N); break;
372 case ISD::EXTRACT_VECTOR_ELT: Res = SplitOp_EXTRACT_VECTOR_ELT(N); break;
373 case ISD::EXTRACT_SUBVECTOR: Res = SplitOp_EXTRACT_SUBVECTOR(N); break;
374 case ISD::VECTOR_SHUFFLE: Res = SplitOp_VECTOR_SHUFFLE(N, OpNo); break;
378 // If the result is null, the sub-method took care of registering results etc.
379 if (!Res.Val) return false;
381 // If the result is N, the sub-method updated N in place. Check to see if any
382 // operands are new, and if so, mark them.
384 // Mark N as new and remark N and its operands. This allows us to correctly
385 // revisit N if it needs another step of promotion and allows us to visit
386 // any new operands to N.
391 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
392 "Invalid operand expansion");
394 ReplaceValueWith(SDOperand(N, 0), Res);
398 SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) {
399 assert(OpNo == 1 && "Can only split the stored value");
401 SDOperand Ch = N->getChain();
402 SDOperand Ptr = N->getBasePtr();
403 int SVOffset = N->getSrcValueOffset();
404 unsigned Alignment = N->getAlignment();
405 bool isVol = N->isVolatile();
407 GetSplitOp(N->getOperand(1), Lo, Hi);
409 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
411 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
413 // Increment the pointer to the other half.
414 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
415 DAG.getIntPtrConstant(IncrementSize));
417 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
418 isVol, MinAlign(Alignment, IncrementSize));
419 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
422 SDOperand DAGTypeLegalizer::SplitOp_RET(SDNode *N, unsigned OpNo) {
423 assert(N->getNumOperands() == 3 &&"Can only handle ret of one vector so far");
424 // FIXME: Returns of gcc generic vectors larger than a legal vector
425 // type should be returned by reference!
427 GetSplitOp(N->getOperand(1), Lo, Hi);
429 SDOperand Chain = N->getOperand(0); // The chain.
430 SDOperand Sign = N->getOperand(2); // Signness
432 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
435 SDOperand DAGTypeLegalizer::SplitOp_BIT_CONVERT(SDNode *N) {
436 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
437 // end up being split all the way down to individual components. Convert the
438 // split pieces into integers and reassemble.
440 GetSplitOp(N->getOperand(0), Lo, Hi);
442 unsigned LoBits = MVT::getSizeInBits(Lo.getValueType());
443 Lo = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(LoBits), Lo);
445 unsigned HiBits = MVT::getSizeInBits(Hi.getValueType());
446 Hi = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(HiBits), Hi);
448 if (TLI.isBigEndian())
451 assert(LoBits == HiBits && "Do not know how to assemble odd sized vectors!");
453 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
454 DAG.getNode(ISD::BUILD_PAIR,
455 MVT::getIntegerType(LoBits+HiBits), Lo, Hi));
458 SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
459 SDOperand Vec = N->getOperand(0);
460 SDOperand Idx = N->getOperand(1);
461 MVT::ValueType VecVT = Vec.getValueType();
463 if (isa<ConstantSDNode>(Idx)) {
464 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
465 assert(IdxVal < MVT::getVectorNumElements(VecVT) &&
466 "Invalid vector index!");
469 GetSplitOp(Vec, Lo, Hi);
471 uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
474 return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
476 return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
477 DAG.getConstant(IdxVal - LoElts,
478 Idx.getValueType()));
481 // Store the vector to the stack and load back the required element.
482 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
483 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
485 // Add the offset to the index.
486 MVT::ValueType EltVT = MVT::getVectorElementType(VecVT);
487 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size.
488 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
489 DAG.getConstant(EltSize, Idx.getValueType()));
491 if (MVT::getSizeInBits(Idx.getValueType()) >
492 MVT::getSizeInBits(TLI.getPointerTy()))
493 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
495 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
497 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
498 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
501 SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) {
502 // We know that the extracted result type is legal. For now, assume the index
504 MVT::ValueType SubVT = N->getValueType(0);
505 SDOperand Idx = N->getOperand(1);
507 GetSplitOp(N->getOperand(0), Lo, Hi);
509 uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
510 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
512 if (IdxVal < LoElts) {
513 assert(IdxVal + MVT::getVectorNumElements(SubVT) <= LoElts &&
514 "Extracted subvector crosses vector split!");
515 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
517 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
518 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
522 SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
523 assert(OpNo == 2 && "Shuffle source type differs from result type?");
524 SDOperand Mask = N->getOperand(2);
525 unsigned MaskLength = MVT::getVectorNumElements(Mask.getValueType());
526 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
527 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
529 // Look for a legal vector type to place the mask values in.
530 // Note that there may not be *any* legal vector-of-integer
531 // type for which the element type is legal!
532 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
533 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
534 // Integer values types are consecutively numbered. Exploit this.
535 EltVT = MVT::SimpleValueType(EltVT + 1)) {
537 // Is the element type big enough to hold the values?
538 if (MVT::getSizeInBits(EltVT) < MinimumBitWidth)
542 // Is the vector type legal?
543 MVT::ValueType VecVT = MVT::getVectorType(EltVT, MaskLength);
544 if (!isTypeLegal(VecVT))
548 // If the element type is not legal, find a larger legal type to use for
549 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
550 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
551 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
552 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
553 // Integer values types are consecutively numbered. Exploit this.
554 OpVT = MVT::SimpleValueType(OpVT + 1)) {
555 if (!isTypeLegal(OpVT))
558 // Success! Rebuild the vector using the legal types.
559 SmallVector<SDOperand, 16> Ops(MaskLength);
560 for (unsigned i = 0; i < MaskLength; ++i) {
562 cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
563 Ops[i] = DAG.getConstant(Idx, OpVT);
565 return DAG.UpdateNodeOperands(SDOperand(N,0),
566 N->getOperand(0), N->getOperand(1),
567 DAG.getNode(ISD::BUILD_VECTOR,
568 VecVT, &Ops[0], Ops.size()));
571 // Continuing is pointless - failure is certain.
574 assert(false && "Failed to find an appropriate mask type!");
575 return SDOperand(N, 0);