1 //===-- LegalizeTypesExpand.cpp - Expansion for LegalizeTypes -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements expansion support for LegalizeTypes. Expansion is the
11 // act of changing a computation in an invalid type to be a computation in
12 // multiple registers of a smaller type. For example, implementing i64
13 // arithmetic in two i32 registers (as is often needed on 32-bit targets, for
16 //===----------------------------------------------------------------------===//
18 #include "LegalizeTypes.h"
19 #include "llvm/Constants.h"
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 /// ExpandResult - This method is called when the specified result of the
27 /// specified node is found to need expansion. At this point, the node may also
28 /// have invalid operands or may have other results that need promotion, we just
29 /// know that (at least) one result needs expansion.
30 void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Expand node result: "; N->dump(&DAG); cerr << "\n");
33 Lo = Hi = SDOperand();
35 // See if the target wants to custom expand this node.
36 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
37 TargetLowering::Custom) {
38 // If the target wants to, allow it to lower this itself.
39 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
40 // Everything that once used N now uses P. We are guaranteed that the
41 // result value types of N and the result value types of P match.
42 ReplaceNodeWith(N, P);
47 switch (N->getOpcode()) {
50 cerr << "ExpandResult #" << ResNo << ": ";
51 N->dump(&DAG); cerr << "\n";
53 assert(0 && "Do not know how to expand the result of this operator!");
56 case ISD::UNDEF: ExpandResult_UNDEF(N, Lo, Hi); break;
57 case ISD::Constant: ExpandResult_Constant(N, Lo, Hi); break;
58 case ISD::BUILD_PAIR: ExpandResult_BUILD_PAIR(N, Lo, Hi); break;
59 case ISD::MERGE_VALUES: ExpandResult_MERGE_VALUES(N, Lo, Hi); break;
60 case ISD::ANY_EXTEND: ExpandResult_ANY_EXTEND(N, Lo, Hi); break;
61 case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break;
62 case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break;
63 case ISD::AssertZext: ExpandResult_AssertZext(N, Lo, Hi); break;
64 case ISD::TRUNCATE: ExpandResult_TRUNCATE(N, Lo, Hi); break;
65 case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break;
66 case ISD::SIGN_EXTEND_INREG: ExpandResult_SIGN_EXTEND_INREG(N, Lo, Hi); break;
67 case ISD::LOAD: ExpandResult_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
71 case ISD::XOR: ExpandResult_Logical(N, Lo, Hi); break;
72 case ISD::BSWAP: ExpandResult_BSWAP(N, Lo, Hi); break;
74 case ISD::SUB: ExpandResult_ADDSUB(N, Lo, Hi); break;
76 case ISD::SUBC: ExpandResult_ADDSUBC(N, Lo, Hi); break;
78 case ISD::SUBE: ExpandResult_ADDSUBE(N, Lo, Hi); break;
79 case ISD::SELECT: ExpandResult_SELECT(N, Lo, Hi); break;
80 case ISD::SELECT_CC: ExpandResult_SELECT_CC(N, Lo, Hi); break;
81 case ISD::MUL: ExpandResult_MUL(N, Lo, Hi); break;
84 case ISD::SRL: ExpandResult_Shift(N, Lo, Hi); break;
86 case ISD::CTLZ: ExpandResult_CTLZ(N, Lo, Hi); break;
87 case ISD::CTPOP: ExpandResult_CTPOP(N, Lo, Hi); break;
88 case ISD::CTTZ: ExpandResult_CTTZ(N, Lo, Hi); break;
91 // If Lo/Hi is null, the sub-method took care of registering results etc.
93 SetExpandedOp(SDOperand(N, ResNo), Lo, Hi);
96 void DAGTypeLegalizer::ExpandResult_UNDEF(SDNode *N,
97 SDOperand &Lo, SDOperand &Hi) {
98 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
99 Lo = Hi = DAG.getNode(ISD::UNDEF, NVT);
102 void DAGTypeLegalizer::ExpandResult_Constant(SDNode *N,
103 SDOperand &Lo, SDOperand &Hi) {
104 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
105 uint64_t Cst = cast<ConstantSDNode>(N)->getValue();
106 Lo = DAG.getConstant(Cst, NVT);
107 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
110 void DAGTypeLegalizer::ExpandResult_BUILD_PAIR(SDNode *N,
111 SDOperand &Lo, SDOperand &Hi) {
112 // Return the operands.
113 Lo = N->getOperand(0);
114 Hi = N->getOperand(1);
117 void DAGTypeLegalizer::ExpandResult_MERGE_VALUES(SDNode *N,
118 SDOperand &Lo, SDOperand &Hi) {
119 // A MERGE_VALUES node can produce any number of values. We know that the
120 // first illegal one needs to be expanded into Lo/Hi.
123 // The string of legal results gets turns into the input operands, which have
125 for (i = 0; isTypeLegal(N->getValueType(i)); ++i)
126 ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
128 // The first illegal result must be the one that needs to be expanded.
129 GetExpandedOp(N->getOperand(i), Lo, Hi);
131 // Legalize the rest of the results into the input operands whether they are
133 unsigned e = N->getNumValues();
134 for (++i; i != e; ++i)
135 ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
138 void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
139 SDOperand &Lo, SDOperand &Hi) {
140 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
141 SDOperand Op = N->getOperand(0);
142 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
143 // The low part is any extension of the input (which degenerates to a copy).
144 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
145 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
147 // For example, extension of an i48 to an i64. The operand type necessarily
148 // promotes to the result type, so will end up being expanded too.
149 assert(getTypeAction(Op.getValueType()) == Promote &&
150 "Don't know how to expand this result!");
151 SDOperand Res = GetPromotedOp(Op);
152 assert(Res.getValueType() == N->getValueType(0) &&
153 "Operand over promoted?");
154 // Split the promoted operand. This will simplify when it is expanded.
155 SplitOp(Res, Lo, Hi);
159 void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
160 SDOperand &Lo, SDOperand &Hi) {
161 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
162 SDOperand Op = N->getOperand(0);
163 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
164 // The low part is zero extension of the input (which degenerates to a copy).
165 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
166 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
168 // For example, extension of an i48 to an i64. The operand type necessarily
169 // promotes to the result type, so will end up being expanded too.
170 assert(getTypeAction(Op.getValueType()) == Promote &&
171 "Don't know how to expand this result!");
172 SDOperand Res = GetPromotedOp(Op);
173 assert(Res.getValueType() == N->getValueType(0) &&
174 "Operand over promoted?");
175 // Split the promoted operand. This will simplify when it is expanded.
176 SplitOp(Res, Lo, Hi);
177 unsigned ExcessBits =
178 MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
179 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerType(ExcessBits));
183 void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
184 SDOperand &Lo, SDOperand &Hi) {
185 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
186 SDOperand Op = N->getOperand(0);
187 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
188 // The low part is sign extension of the input (which degenerates to a copy).
189 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
190 // The high part is obtained by SRA'ing all but one of the bits of low part.
191 unsigned LoSize = MVT::getSizeInBits(NVT);
192 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
193 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
195 // For example, extension of an i48 to an i64. The operand type necessarily
196 // promotes to the result type, so will end up being expanded too.
197 assert(getTypeAction(Op.getValueType()) == Promote &&
198 "Don't know how to expand this result!");
199 SDOperand Res = GetPromotedOp(Op);
200 assert(Res.getValueType() == N->getValueType(0) &&
201 "Operand over promoted?");
202 // Split the promoted operand. This will simplify when it is expanded.
203 SplitOp(Res, Lo, Hi);
204 unsigned ExcessBits =
205 MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
206 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
207 DAG.getValueType(MVT::getIntegerType(ExcessBits)));
211 void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N,
212 SDOperand &Lo, SDOperand &Hi) {
213 GetExpandedOp(N->getOperand(0), Lo, Hi);
214 MVT::ValueType NVT = Lo.getValueType();
215 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
216 unsigned NVTBits = MVT::getSizeInBits(NVT);
217 unsigned EVTBits = MVT::getSizeInBits(EVT);
219 if (NVTBits < EVTBits) {
220 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
221 DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits)));
223 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
224 // The high part must be zero, make it explicit.
225 Hi = DAG.getConstant(0, NVT);
229 void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N,
230 SDOperand &Lo, SDOperand &Hi) {
231 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
232 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
233 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
234 DAG.getConstant(MVT::getSizeInBits(NVT),
235 TLI.getShiftAmountTy()));
236 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
239 void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
240 SDOperand &Lo, SDOperand &Hi) {
241 // Lower the bit-convert to a store/load from the stack, then expand the load.
242 SDOperand Op = CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
243 ExpandResult_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
246 void DAGTypeLegalizer::
247 ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
248 GetExpandedOp(N->getOperand(0), Lo, Hi);
249 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
251 if (MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(Lo.getValueType())) {
252 // sext_inreg the low part if needed.
253 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
256 // The high part gets the sign extension from the lo-part. This handles
257 // things like sextinreg V:i64 from i8.
258 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
259 DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1,
260 TLI.getShiftAmountTy()));
262 // For example, extension of an i48 to an i64. Leave the low part alone,
263 // sext_inreg the high part.
264 unsigned ExcessBits =
265 MVT::getSizeInBits(EVT) - MVT::getSizeInBits(Lo.getValueType());
266 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
267 DAG.getValueType(MVT::getIntegerType(ExcessBits)));
271 void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
272 SDOperand &Lo, SDOperand &Hi) {
273 MVT::ValueType VT = N->getValueType(0);
274 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
275 SDOperand Ch = N->getChain(); // Legalize the chain.
276 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
277 ISD::LoadExtType ExtType = N->getExtensionType();
278 int SVOffset = N->getSrcValueOffset();
279 unsigned Alignment = N->getAlignment();
280 bool isVolatile = N->isVolatile();
282 assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
284 if (ExtType == ISD::NON_EXTLOAD) {
285 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
286 isVolatile, Alignment);
287 // Increment the pointer to the other half.
288 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
289 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
290 DAG.getIntPtrConstant(IncrementSize));
291 Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
292 isVolatile, MinAlign(Alignment, IncrementSize));
294 // Build a factor node to remember that this load is independent of the
296 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
299 // Handle endianness of the load.
300 if (TLI.isBigEndian())
302 } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
303 MVT::ValueType EVT = N->getMemoryVT();
305 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
306 isVolatile, Alignment);
308 // Remember the chain.
311 if (ExtType == ISD::SEXTLOAD) {
312 // The high part is obtained by SRA'ing all but one of the bits of the
314 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
315 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
316 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
317 } else if (ExtType == ISD::ZEXTLOAD) {
318 // The high part is just a zero.
319 Hi = DAG.getConstant(0, NVT);
321 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
322 // The high part is undefined.
323 Hi = DAG.getNode(ISD::UNDEF, NVT);
325 } else if (TLI.isLittleEndian()) {
326 // Little-endian - low bits are at low addresses.
327 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
328 isVolatile, Alignment);
330 unsigned ExcessBits =
331 MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
332 MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
334 // Increment the pointer to the other half.
335 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
336 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
337 DAG.getIntPtrConstant(IncrementSize));
338 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
339 SVOffset+IncrementSize, NEVT,
340 isVolatile, MinAlign(Alignment, IncrementSize));
342 // Build a factor node to remember that this load is independent of the
344 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
347 // Big-endian - high bits are at low addresses. Favor aligned loads at
348 // the cost of some bit-fiddling.
349 MVT::ValueType EVT = N->getMemoryVT();
350 unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
351 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
352 unsigned ExcessBits = (EBytes - IncrementSize)*8;
354 // Load both the high bits and maybe some of the low bits.
355 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
356 MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits),
357 isVolatile, Alignment);
359 // Increment the pointer to the other half.
360 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
361 DAG.getIntPtrConstant(IncrementSize));
362 // Load the rest of the low bits.
363 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
364 SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
365 isVolatile, MinAlign(Alignment, IncrementSize));
367 // Build a factor node to remember that this load is independent of the
369 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
372 if (ExcessBits < MVT::getSizeInBits(NVT)) {
373 // Transfer low bits from the bottom of Hi to the top of Lo.
374 Lo = DAG.getNode(ISD::OR, NVT, Lo,
375 DAG.getNode(ISD::SHL, NVT, Hi,
376 DAG.getConstant(ExcessBits,
377 TLI.getShiftAmountTy())));
378 // Move high bits to the right position in Hi.
379 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
380 DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
381 TLI.getShiftAmountTy()));
385 // Legalized the chain result - switch anything that used the old chain to
387 ReplaceValueWith(SDOperand(N, 1), Ch);
390 void DAGTypeLegalizer::ExpandResult_Logical(SDNode *N,
391 SDOperand &Lo, SDOperand &Hi) {
392 SDOperand LL, LH, RL, RH;
393 GetExpandedOp(N->getOperand(0), LL, LH);
394 GetExpandedOp(N->getOperand(1), RL, RH);
395 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
396 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
399 void DAGTypeLegalizer::ExpandResult_BSWAP(SDNode *N,
400 SDOperand &Lo, SDOperand &Hi) {
401 GetExpandedOp(N->getOperand(0), Hi, Lo); // Note swapped operands.
402 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
403 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
406 void DAGTypeLegalizer::ExpandResult_SELECT(SDNode *N,
407 SDOperand &Lo, SDOperand &Hi) {
408 SDOperand LL, LH, RL, RH;
409 GetExpandedOp(N->getOperand(1), LL, LH);
410 GetExpandedOp(N->getOperand(2), RL, RH);
411 Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LL, RL);
413 assert(N->getOperand(0).getValueType() != MVT::f32 &&
414 "FIXME: softfp shouldn't use expand!");
415 Hi = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LH, RH);
418 void DAGTypeLegalizer::ExpandResult_SELECT_CC(SDNode *N,
419 SDOperand &Lo, SDOperand &Hi) {
420 SDOperand LL, LH, RL, RH;
421 GetExpandedOp(N->getOperand(2), LL, LH);
422 GetExpandedOp(N->getOperand(3), RL, RH);
423 Lo = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
424 N->getOperand(1), LL, RL, N->getOperand(4));
426 assert(N->getOperand(0).getValueType() != MVT::f32 &&
427 "FIXME: softfp shouldn't use expand!");
428 Hi = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
429 N->getOperand(1), LH, RH, N->getOperand(4));
432 void DAGTypeLegalizer::ExpandResult_ADDSUB(SDNode *N,
433 SDOperand &Lo, SDOperand &Hi) {
434 // Expand the subcomponents.
435 SDOperand LHSL, LHSH, RHSL, RHSH;
436 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
437 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
438 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
439 SDOperand LoOps[2] = { LHSL, RHSL };
440 SDOperand HiOps[3] = { LHSH, RHSH };
442 if (N->getOpcode() == ISD::ADD) {
443 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
444 HiOps[2] = Lo.getValue(1);
445 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
447 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
448 HiOps[2] = Lo.getValue(1);
449 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
453 void DAGTypeLegalizer::ExpandResult_ADDSUBC(SDNode *N,
454 SDOperand &Lo, SDOperand &Hi) {
455 // Expand the subcomponents.
456 SDOperand LHSL, LHSH, RHSL, RHSH;
457 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
458 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
459 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
460 SDOperand LoOps[2] = { LHSL, RHSL };
461 SDOperand HiOps[3] = { LHSH, RHSH };
463 if (N->getOpcode() == ISD::ADDC) {
464 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
465 HiOps[2] = Lo.getValue(1);
466 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
468 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
469 HiOps[2] = Lo.getValue(1);
470 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
473 // Legalized the flag result - switch anything that used the old flag to
475 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
478 void DAGTypeLegalizer::ExpandResult_ADDSUBE(SDNode *N,
479 SDOperand &Lo, SDOperand &Hi) {
480 // Expand the subcomponents.
481 SDOperand LHSL, LHSH, RHSL, RHSH;
482 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
483 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
484 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
485 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
486 SDOperand HiOps[3] = { LHSH, RHSH };
488 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
489 HiOps[2] = Lo.getValue(1);
490 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
492 // Legalized the flag result - switch anything that used the old flag to
494 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
497 void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N,
498 SDOperand &Lo, SDOperand &Hi) {
499 MVT::ValueType VT = N->getValueType(0);
500 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
502 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
503 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
504 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
505 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
506 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
507 SDOperand LL, LH, RL, RH;
508 GetExpandedOp(N->getOperand(0), LL, LH);
509 GetExpandedOp(N->getOperand(1), RL, RH);
510 unsigned OuterBitSize = MVT::getSizeInBits(VT);
511 unsigned BitSize = MVT::getSizeInBits(NVT);
512 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
513 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
515 if (DAG.MaskedValueIsZero(N->getOperand(0),
516 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
517 DAG.MaskedValueIsZero(N->getOperand(1),
518 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
519 // The inputs are both zero-extended.
521 // We can emit a umul_lohi.
522 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
523 Hi = SDOperand(Lo.Val, 1);
527 // We can emit a mulhu+mul.
528 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
529 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
533 if (LHSSB > BitSize && RHSSB > BitSize) {
534 // The input values are both sign-extended.
536 // We can emit a smul_lohi.
537 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
538 Hi = SDOperand(Lo.Val, 1);
542 // We can emit a mulhs+mul.
543 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
544 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
549 // Lo,Hi = umul LHS, RHS.
550 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
551 DAG.getVTList(NVT, NVT), LL, RL);
553 Hi = UMulLOHI.getValue(1);
554 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
555 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
556 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
557 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
564 // If nothing else, we can make a libcall.
565 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), N,
566 false/*sign irrelevant*/, Hi);
571 void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
572 SDOperand &Lo, SDOperand &Hi) {
573 MVT::ValueType VT = N->getValueType(0);
575 // If we can emit an efficient shift operation, do so now. Check to see if
576 // the RHS is a constant.
577 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
578 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
580 // If we can determine that the high bit of the shift is zero or one, even if
581 // the low bits are variable, emit this shift in an optimized form.
582 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
585 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
587 if (N->getOpcode() == ISD::SHL)
588 PartsOpc = ISD::SHL_PARTS;
589 else if (N->getOpcode() == ISD::SRL)
590 PartsOpc = ISD::SRL_PARTS;
592 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
593 PartsOpc = ISD::SRA_PARTS;
596 // Next check to see if the target supports this SHL_PARTS operation or if it
597 // will custom expand it.
598 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
599 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
600 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
601 Action == TargetLowering::Custom) {
602 // Expand the subcomponents.
603 SDOperand LHSL, LHSH;
604 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
606 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
607 MVT::ValueType VT = LHSL.getValueType();
608 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
615 // Otherwise, emit a libcall.
616 unsigned RuntimeCode = ; // SRL -> SRL_I64 etc.
618 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), N,
619 false/*lshr is unsigned*/, Hi);
623 void DAGTypeLegalizer::ExpandResult_CTLZ(SDNode *N,
624 SDOperand &Lo, SDOperand &Hi) {
625 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
626 GetExpandedOp(N->getOperand(0), Lo, Hi);
627 MVT::ValueType NVT = Lo.getValueType();
629 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
630 DAG.getConstant(0, NVT), ISD::SETNE);
632 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
633 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
635 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
636 DAG.getNode(ISD::ADD, NVT, LoLZ,
637 DAG.getConstant(MVT::getSizeInBits(NVT), NVT)));
638 Hi = DAG.getConstant(0, NVT);
641 void DAGTypeLegalizer::ExpandResult_CTPOP(SDNode *N,
642 SDOperand &Lo, SDOperand &Hi) {
643 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
644 GetExpandedOp(N->getOperand(0), Lo, Hi);
645 MVT::ValueType NVT = Lo.getValueType();
646 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
647 DAG.getNode(ISD::CTPOP, NVT, Hi));
648 Hi = DAG.getConstant(0, NVT);
651 void DAGTypeLegalizer::ExpandResult_CTTZ(SDNode *N,
652 SDOperand &Lo, SDOperand &Hi) {
653 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
654 GetExpandedOp(N->getOperand(0), Lo, Hi);
655 MVT::ValueType NVT = Lo.getValueType();
657 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), Lo,
658 DAG.getConstant(0, NVT), ISD::SETNE);
660 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
661 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
663 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
664 DAG.getNode(ISD::ADD, NVT, HiLZ,
665 DAG.getConstant(MVT::getSizeInBits(NVT), NVT)));
666 Hi = DAG.getConstant(0, NVT);
669 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
670 /// and the shift amount is a constant 'Amt'. Expand the operation.
671 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
672 SDOperand &Lo, SDOperand &Hi) {
673 // Expand the incoming operand to be shifted, so that we have its parts
675 GetExpandedOp(N->getOperand(0), InL, InH);
677 MVT::ValueType NVT = InL.getValueType();
678 unsigned VTBits = MVT::getSizeInBits(N->getValueType(0));
679 unsigned NVTBits = MVT::getSizeInBits(NVT);
680 MVT::ValueType ShTy = N->getOperand(1).getValueType();
682 if (N->getOpcode() == ISD::SHL) {
684 Lo = Hi = DAG.getConstant(0, NVT);
685 } else if (Amt > NVTBits) {
686 Lo = DAG.getConstant(0, NVT);
687 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
688 } else if (Amt == NVTBits) {
689 Lo = DAG.getConstant(0, NVT);
692 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
693 Hi = DAG.getNode(ISD::OR, NVT,
694 DAG.getNode(ISD::SHL, NVT, InH,
695 DAG.getConstant(Amt, ShTy)),
696 DAG.getNode(ISD::SRL, NVT, InL,
697 DAG.getConstant(NVTBits-Amt, ShTy)));
702 if (N->getOpcode() == ISD::SRL) {
704 Lo = DAG.getConstant(0, NVT);
705 Hi = DAG.getConstant(0, NVT);
706 } else if (Amt > NVTBits) {
707 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
708 Hi = DAG.getConstant(0, NVT);
709 } else if (Amt == NVTBits) {
711 Hi = DAG.getConstant(0, NVT);
713 Lo = DAG.getNode(ISD::OR, NVT,
714 DAG.getNode(ISD::SRL, NVT, InL,
715 DAG.getConstant(Amt, ShTy)),
716 DAG.getNode(ISD::SHL, NVT, InH,
717 DAG.getConstant(NVTBits-Amt, ShTy)));
718 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
723 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
725 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
726 DAG.getConstant(NVTBits-1, ShTy));
727 } else if (Amt > NVTBits) {
728 Lo = DAG.getNode(ISD::SRA, NVT, InH,
729 DAG.getConstant(Amt-NVTBits, ShTy));
730 Hi = DAG.getNode(ISD::SRA, NVT, InH,
731 DAG.getConstant(NVTBits-1, ShTy));
732 } else if (Amt == NVTBits) {
734 Hi = DAG.getNode(ISD::SRA, NVT, InH,
735 DAG.getConstant(NVTBits-1, ShTy));
737 Lo = DAG.getNode(ISD::OR, NVT,
738 DAG.getNode(ISD::SRL, NVT, InL,
739 DAG.getConstant(Amt, ShTy)),
740 DAG.getNode(ISD::SHL, NVT, InH,
741 DAG.getConstant(NVTBits-Amt, ShTy)));
742 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
746 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
747 /// this shift based on knowledge of the high bit of the shift amount. If we
748 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
750 bool DAGTypeLegalizer::
751 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
752 SDOperand Amt = N->getOperand(1);
753 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
754 MVT::ValueType ShTy = Amt.getValueType();
755 MVT::ValueType ShBits = MVT::getSizeInBits(ShTy);
756 unsigned NVTBits = MVT::getSizeInBits(NVT);
757 assert(isPowerOf2_32(NVTBits) &&
758 "Expanded integer type size not a power of two!");
760 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
761 APInt KnownZero, KnownOne;
762 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
764 // If we don't know anything about the high bits, exit.
765 if (((KnownZero|KnownOne) & HighBitMask) == 0)
768 // Get the incoming operand to be shifted.
770 GetExpandedOp(N->getOperand(0), InL, InH);
772 // If we know that any of the high bits of the shift amount are one, then we
773 // can do this as a couple of simple shifts.
774 if (KnownOne.intersects(HighBitMask)) {
775 // Mask out the high bit, which we know is set.
776 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
777 DAG.getConstant(~HighBitMask, ShTy));
779 switch (N->getOpcode()) {
780 default: assert(0 && "Unknown shift");
782 Lo = DAG.getConstant(0, NVT); // Low part is zero.
783 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
786 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
787 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
790 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
791 DAG.getConstant(NVTBits-1, ShTy));
792 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
797 // If we know that all of the high bits of the shift amount are zero, then we
798 // can do this as a couple of simple shifts.
799 if ((KnownZero & HighBitMask) == HighBitMask) {
801 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
802 DAG.getConstant(NVTBits, ShTy),
805 switch (N->getOpcode()) {
806 default: assert(0 && "Unknown shift");
807 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
809 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
812 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
813 Hi = DAG.getNode(ISD::OR, NVT,
814 DAG.getNode(Op1, NVT, InH, Amt),
815 DAG.getNode(Op2, NVT, InL, Amt2));
823 //===----------------------------------------------------------------------===//
825 //===----------------------------------------------------------------------===//
827 /// ExpandOperand - This method is called when the specified operand of the
828 /// specified node is found to need expansion. At this point, all of the result
829 /// types of the node are known to be legal, but other operands of the node may
830 /// need promotion or expansion as well as the specified one.
831 bool DAGTypeLegalizer::ExpandOperand(SDNode *N, unsigned OpNo) {
832 DEBUG(cerr << "Expand node operand: "; N->dump(&DAG); cerr << "\n");
835 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
836 == TargetLowering::Custom)
837 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
840 switch (N->getOpcode()) {
843 cerr << "ExpandOperand Op #" << OpNo << ": ";
844 N->dump(&DAG); cerr << "\n";
846 assert(0 && "Do not know how to expand this operator's operand!");
849 case ISD::TRUNCATE: Res = ExpandOperand_TRUNCATE(N); break;
850 case ISD::BIT_CONVERT: Res = ExpandOperand_BIT_CONVERT(N); break;
852 case ISD::SINT_TO_FP:
853 Res = ExpandOperand_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
855 case ISD::UINT_TO_FP:
856 Res = ExpandOperand_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
858 case ISD::EXTRACT_ELEMENT: Res = ExpandOperand_EXTRACT_ELEMENT(N); break;
860 case ISD::BR_CC: Res = ExpandOperand_BR_CC(N); break;
861 case ISD::SETCC: Res = ExpandOperand_SETCC(N); break;
864 Res = ExpandOperand_STORE(cast<StoreSDNode>(N), OpNo);
868 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
870 case ISD::BUILD_VECTOR: Res = ExpandOperand_BUILD_VECTOR(N); break;
874 // If the result is null, the sub-method took care of registering results etc.
875 if (!Res.Val) return false;
876 // If the result is N, the sub-method updated N in place. Check to see if any
877 // operands are new, and if so, mark them.
879 // Mark N as new and remark N and its operands. This allows us to correctly
880 // revisit N if it needs another step of promotion and allows us to visit
881 // any new operands to N.
882 N->setNodeId(NewNode);
887 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
888 "Invalid operand expansion");
890 ReplaceValueWith(SDOperand(N, 0), Res);
894 SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) {
896 GetExpandedOp(N->getOperand(0), InL, InH);
897 // Just truncate the low part of the source.
898 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
901 SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
902 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
905 SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
906 MVT::ValueType DestTy) {
907 // We know the destination is legal, but that the input needs to be expanded.
908 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
910 // Check to see if the target has a custom way to lower this. If so, use it.
911 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
912 default: assert(0 && "This action not implemented for this operation!");
913 case TargetLowering::Legal:
914 case TargetLowering::Expand:
915 break; // This case is handled below.
916 case TargetLowering::Custom:
917 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
919 if (NV.Val) return NV;
920 break; // The target lowered this.
924 if (DestTy == MVT::f32)
925 LC = RTLIB::SINTTOFP_I64_F32;
927 assert(DestTy == MVT::f64 && "Unknown fp value type!");
928 LC = RTLIB::SINTTOFP_I64_F64;
931 assert(0 && "FIXME: no libcalls yet!");
934 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
935 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
936 SDOperand UnusedHiPart;
937 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, true, UnusedHiPart);
941 SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
942 MVT::ValueType DestTy) {
943 // We know the destination is legal, but that the input needs to be expanded.
944 assert(getTypeAction(Source.getValueType()) == Expand &&
945 "This is not an expansion!");
946 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
948 // If this is unsigned, and not supported, first perform the conversion to
949 // signed, then adjust the result if the sign bit is set.
950 SDOperand SignedConv = ExpandOperand_SINT_TO_FP(Source, DestTy);
952 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
953 // incoming integer is set. To handle this, we dynamically test to see if
954 // it is set, and, if so, add a fudge factor.
956 GetExpandedOp(Source, Lo, Hi);
958 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
959 DAG.getConstant(0, Hi.getValueType()),
961 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
962 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
963 SignSet, Four, Zero);
964 uint64_t FF = 0x5f800000ULL;
965 if (TLI.isLittleEndian()) FF <<= 32;
966 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
968 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
969 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
970 SDOperand FudgeInReg;
971 if (DestTy == MVT::f32)
972 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
973 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
974 // FIXME: Avoid the extend by construction the right constantpool?
975 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
976 CPIdx, NULL, 0, MVT::f32);
978 assert(0 && "Unexpected conversion");
980 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
983 SDOperand DAGTypeLegalizer::ExpandOperand_EXTRACT_ELEMENT(SDNode *N) {
985 GetExpandedOp(N->getOperand(0), Lo, Hi);
986 return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
989 SDOperand DAGTypeLegalizer::ExpandOperand_BR_CC(SDNode *N) {
990 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
991 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
992 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
994 // If ExpandSetCCOperands returned a scalar, we need to compare the result
995 // against zero to select between true and false values.
996 if (NewRHS.Val == 0) {
997 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1001 // Update N to have the operands specified.
1002 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1003 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1007 SDOperand DAGTypeLegalizer::ExpandOperand_SETCC(SDNode *N) {
1008 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1009 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1010 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1012 // If ExpandSetCCOperands returned a scalar, use it.
1013 if (NewRHS.Val == 0) return NewLHS;
1015 // Otherwise, update N to have the operands specified.
1016 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1017 DAG.getCondCode(CCCode));
1020 /// ExpandSetCCOperands - Expand the operands of a comparison. This code is
1021 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1022 void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
1023 ISD::CondCode &CCCode) {
1024 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1025 GetExpandedOp(NewLHS, LHSLo, LHSHi);
1026 GetExpandedOp(NewRHS, RHSLo, RHSHi);
1028 MVT::ValueType VT = NewLHS.getValueType();
1029 if (VT == MVT::f32 || VT == MVT::f64) {
1030 assert(0 && "FIXME: softfp not implemented yet! should be promote not exp");
1033 if (VT == MVT::ppcf128) {
1034 // FIXME: This generated code sucks. We want to generate
1035 // FCMP crN, hi1, hi2
1037 // FCMP crN, lo1, lo2
1038 // The following can be improved, but not that much.
1039 SDOperand Tmp1, Tmp2, Tmp3;
1040 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
1041 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
1042 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1043 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
1044 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
1045 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1046 NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
1047 NewRHS = SDOperand(); // LHS is the result, not a compare.
1052 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1054 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1055 if (RHSCST->isAllOnesValue()) {
1056 // Equality comparison to -1.
1057 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1062 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1063 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1064 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1065 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1069 // If this is a comparison of the sign bit, just look at the top part.
1071 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1072 if ((CCCode == ISD::SETLT && CST->getValue() == 0) || // X < 0
1073 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1079 // FIXME: This generated code sucks.
1080 ISD::CondCode LowCC;
1082 default: assert(0 && "Unknown integer setcc!");
1084 case ISD::SETULT: LowCC = ISD::SETULT; break;
1086 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1088 case ISD::SETULE: LowCC = ISD::SETULE; break;
1090 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1093 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1094 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1095 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1097 // NOTE: on targets without efficient SELECT of bools, we can always use
1098 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1099 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1100 SDOperand Tmp1, Tmp2;
1101 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
1102 false, DagCombineInfo);
1104 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
1105 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
1106 CCCode, false, DagCombineInfo);
1108 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,
1109 DAG.getCondCode(CCCode));
1111 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1112 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1113 if ((Tmp1C && Tmp1C->getValue() == 0) ||
1114 (Tmp2C && Tmp2C->getValue() == 0 &&
1115 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1116 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1117 (Tmp2C && Tmp2C->getValue() == 1 &&
1118 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1119 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1120 // low part is known false, returns high part.
1121 // For LE / GE, if high part is known false, ignore the low part.
1122 // For LT / GT, if high part is known true, ignore the low part.
1124 NewRHS = SDOperand();
1128 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
1129 ISD::SETEQ, false, DagCombineInfo);
1131 NewLHS = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
1132 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1133 NewLHS, Tmp1, Tmp2);
1134 NewRHS = SDOperand();
1137 SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
1138 assert(OpNo == 1 && "Can only expand the stored value so far");
1140 MVT::ValueType VT = N->getOperand(1).getValueType();
1141 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1142 SDOperand Ch = N->getChain();
1143 SDOperand Ptr = N->getBasePtr();
1144 int SVOffset = N->getSrcValueOffset();
1145 unsigned Alignment = N->getAlignment();
1146 bool isVolatile = N->isVolatile();
1149 assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
1151 if (!N->isTruncatingStore()) {
1152 unsigned IncrementSize = 0;
1153 GetExpandedOp(N->getValue(), Lo, Hi);
1154 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1156 if (TLI.isBigEndian())
1159 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(),
1160 SVOffset, isVolatile, Alignment);
1162 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1163 DAG.getIntPtrConstant(IncrementSize));
1164 assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
1165 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1166 isVolatile, MinAlign(Alignment, IncrementSize));
1167 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1168 } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
1169 GetExpandedOp(N->getValue(), Lo, Hi);
1170 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1171 N->getMemoryVT(), isVolatile, Alignment);
1172 } else if (TLI.isLittleEndian()) {
1173 // Little-endian - low bits are at low addresses.
1174 GetExpandedOp(N->getValue(), Lo, Hi);
1176 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1177 isVolatile, Alignment);
1179 unsigned ExcessBits =
1180 MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
1181 MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
1183 // Increment the pointer to the other half.
1184 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
1185 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1186 DAG.getIntPtrConstant(IncrementSize));
1187 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1188 SVOffset+IncrementSize, NEVT,
1189 isVolatile, MinAlign(Alignment, IncrementSize));
1190 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1192 // Big-endian - high bits are at low addresses. Favor aligned stores at
1193 // the cost of some bit-fiddling.
1194 GetExpandedOp(N->getValue(), Lo, Hi);
1196 MVT::ValueType EVT = N->getMemoryVT();
1197 unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
1198 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
1199 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1200 MVT::ValueType HiVT =
1201 MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits);
1203 if (ExcessBits < MVT::getSizeInBits(NVT)) {
1204 // Transfer high bits from the top of Lo to the bottom of Hi.
1205 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1206 DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
1207 TLI.getShiftAmountTy()));
1208 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1209 DAG.getNode(ISD::SRL, NVT, Lo,
1210 DAG.getConstant(ExcessBits,
1211 TLI.getShiftAmountTy())));
1214 // Store both the high bits and maybe some of the low bits.
1215 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1216 SVOffset, HiVT, isVolatile, Alignment);
1218 // Increment the pointer to the other half.
1219 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1220 DAG.getIntPtrConstant(IncrementSize));
1221 // Store the lowest ExcessBits bits in the second half.
1222 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
1223 SVOffset+IncrementSize,
1224 MVT::getIntegerType(ExcessBits),
1225 isVolatile, MinAlign(Alignment, IncrementSize));
1226 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1230 SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) {
1231 // The vector type is legal but the element type needs expansion.
1232 MVT::ValueType VecVT = N->getValueType(0);
1233 unsigned NumElts = MVT::getVectorNumElements(VecVT);
1234 MVT::ValueType OldVT = N->getOperand(0).getValueType();
1235 MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT);
1237 assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) &&
1238 "Do not know how to expand this operand!");
1240 // Build a vector of twice the length out of the expanded elements.
1241 // For example <2 x i64> -> <4 x i32>.
1242 std::vector<SDOperand> NewElts;
1243 NewElts.reserve(NumElts*2);
1245 for (unsigned i = 0; i < NumElts; ++i) {
1247 GetExpandedOp(N->getOperand(i), Lo, Hi);
1248 if (TLI.isBigEndian())
1250 NewElts.push_back(Lo);
1251 NewElts.push_back(Hi);
1254 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
1255 MVT::getVectorType(NewVT, NewElts.size()),
1256 &NewElts[0], NewElts.size());
1258 // Convert the new vector to the old vector type.
1259 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);