1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDOperand Result = SDOperand();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
57 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
59 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
60 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
61 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
62 case ISD::EXTRACT_VECTOR_ELT:
63 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
64 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
65 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
66 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
67 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
68 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
69 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
96 // If Result is null, the sub-method took care of registering the result.
98 SetPromotedInteger(SDOperand(N, ResNo), Result);
101 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
102 SDOperand InOp = N->getOperand(0);
103 MVT InVT = InOp.getValueType();
104 MVT NInVT = TLI.getTypeToTransformTo(InVT);
105 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
107 switch (getTypeAction(InVT)) {
109 assert(false && "Unknown type action!");
114 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
115 // The input promotes to the same size. Convert the promoted value.
116 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
119 // Promote the integer operand by hand.
120 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
124 case ScalarizeVector:
125 // Convert the element to an integer and promote it by hand.
126 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
127 BitConvertToInteger(GetScalarizedVector(InOp)));
129 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
130 // pieces of the input into integers and reassemble in the final type.
132 GetSplitVector(N->getOperand(0), Lo, Hi);
133 Lo = BitConvertToInteger(Lo);
134 Hi = BitConvertToInteger(Hi);
136 if (TLI.isBigEndian())
139 InOp = DAG.getNode(ISD::ANY_EXTEND,
140 MVT::getIntegerVT(OutVT.getSizeInBits()),
141 JoinIntegers(Lo, Hi));
142 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
145 // Otherwise, lower the bit-convert to a store/load from the stack, then
147 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
148 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
151 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
152 // The pair element type may be legal, or may not promote to the same type as
153 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
154 return DAG.getNode(ISD::ANY_EXTEND,
155 TLI.getTypeToTransformTo(N->getValueType(0)),
156 JoinIntegers(N->getOperand(0), N->getOperand(1)));
159 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
160 MVT VT = N->getValueType(0);
161 // Zero extend things like i1, sign extend everything else. It shouldn't
162 // matter in theory which one we pick, but this tends to give better code?
163 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
164 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
166 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
170 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
171 SDOperand Op = GetPromotedInteger(N->getOperand(0));
172 MVT OVT = N->getValueType(0);
173 MVT NVT = Op.getValueType();
174 // Zero extend to the promoted type and do the count there.
175 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
176 // Subtract off the extra leading bits in the bigger type.
177 return DAG.getNode(ISD::SUB, NVT, Op,
178 DAG.getConstant(NVT.getSizeInBits() -
179 OVT.getSizeInBits(), NVT));
182 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
183 SDOperand Op = GetPromotedInteger(N->getOperand(0));
184 MVT OVT = N->getValueType(0);
185 MVT NVT = Op.getValueType();
186 // Zero extend to the promoted type and do the count there.
187 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
190 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
191 SDOperand Op = GetPromotedInteger(N->getOperand(0));
192 MVT OVT = N->getValueType(0);
193 MVT NVT = Op.getValueType();
194 // The count is the same in the promoted type except if the original
195 // value was zero. This can be handled by setting the bit just off
196 // the top of the original type.
197 APInt TopBit(NVT.getSizeInBits(), 0);
198 TopBit.set(OVT.getSizeInBits());
199 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
200 return DAG.getNode(ISD::CTTZ, NVT, Op);
203 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
204 MVT OldVT = N->getValueType(0);
205 SDOperand OldVec = N->getOperand(0);
206 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
209 assert(!isTypeLegal(OldVec.getValueType()) &&
210 "Legal one-element vector of a type needing promotion!");
211 // It is tempting to follow GetScalarizedVector by a call to
212 // GetPromotedInteger, but this would be wrong because the
213 // scalarized value may not yet have been processed.
214 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
215 GetScalarizedVector(OldVec));
218 // Convert to a vector half as long with an element type of twice the width,
219 // for example <4 x i16> -> <2 x i32>.
220 assert(!(OldElts & 1) && "Odd length vectors not supported!");
221 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
222 assert(OldVT.isSimple() && NewVT.isSimple());
224 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
225 MVT::getVectorVT(NewVT, OldElts / 2),
228 // Extract the element at OldIdx / 2 from the new vector.
229 SDOperand OldIdx = N->getOperand(1);
230 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
231 DAG.getConstant(1, TLI.getShiftAmountTy()));
232 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
234 // Select the appropriate half of the element: Lo if OldIdx was even,
237 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
238 DAG.getConstant(OldVT.getSizeInBits(),
239 TLI.getShiftAmountTy()));
240 if (TLI.isBigEndian())
243 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
244 DAG.getConstant(1, TLI.getShiftAmountTy()));
245 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
248 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
249 unsigned NewOpc = N->getOpcode();
250 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
252 // If we're promoting a UINT to a larger size, check to see if the new node
253 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
254 // we can use that instead. This allows us to generate better code for
255 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
256 // legal, such as PowerPC.
257 if (N->getOpcode() == ISD::FP_TO_UINT) {
258 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
259 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
260 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
261 NewOpc = ISD::FP_TO_SINT;
264 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
267 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
268 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
270 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
271 SDOperand Res = GetPromotedInteger(N->getOperand(0));
272 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
273 "Extension doesn't make sense!");
275 // If the result and operand types are the same after promotion, simplify
276 // to an in-register extension.
277 if (NVT == Res.getValueType()) {
278 // The high bits are not guaranteed to be anything. Insert an extend.
279 if (N->getOpcode() == ISD::SIGN_EXTEND)
280 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
281 DAG.getValueType(N->getOperand(0).getValueType()));
282 if (N->getOpcode() == ISD::ZERO_EXTEND)
283 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
284 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
289 // Otherwise, just extend the original operand all the way to the larger type.
290 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
293 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
294 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
295 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
296 ISD::LoadExtType ExtType =
297 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
298 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
299 N->getSrcValue(), N->getSrcValueOffset(),
300 N->getMemoryVT(), N->isVolatile(),
303 // Legalized the chain result - switch anything that used the old chain to
305 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
309 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
310 // Sign extend the input.
311 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
312 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
313 MVT VT = N->getValueType(0);
314 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
315 DAG.getValueType(VT));
316 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
317 DAG.getValueType(VT));
319 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
322 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
323 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
324 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
325 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
328 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
329 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
330 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
331 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
332 N->getOperand(1), LHS, RHS, N->getOperand(4));
335 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
336 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
337 && "SetCC type is not legal??");
338 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
339 N->getOperand(0), N->getOperand(1), N->getOperand(2));
342 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
343 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
344 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
347 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
348 // The input may have strange things in the top bits of the registers, but
349 // these operations don't care. They may have weird bits going out, but
350 // that too is okay if they are integer operations.
351 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
352 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
353 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
356 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
357 // The input value must be properly sign extended.
358 MVT VT = N->getValueType(0);
359 MVT NVT = TLI.getTypeToTransformTo(VT);
360 SDOperand Res = GetPromotedInteger(N->getOperand(0));
361 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
362 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
365 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
366 // The input value must be properly zero extended.
367 MVT VT = N->getValueType(0);
368 MVT NVT = TLI.getTypeToTransformTo(VT);
369 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
370 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
373 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
376 switch (getTypeAction(N->getOperand(0).getValueType())) {
377 default: assert(0 && "Unknown type action!");
380 Res = N->getOperand(0);
383 Res = GetPromotedInteger(N->getOperand(0));
387 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
388 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
389 "Truncation doesn't make sense!");
390 if (Res.getValueType() == NVT)
393 // Truncate to NVT instead of VT
394 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
397 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
398 // Zero extend the input.
399 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
400 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
401 MVT VT = N->getValueType(0);
402 LHS = DAG.getZeroExtendInReg(LHS, VT);
403 RHS = DAG.getZeroExtendInReg(RHS, VT);
405 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
408 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
409 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
412 SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
413 SDOperand Chain = N->getOperand(0); // Get the chain.
414 SDOperand Ptr = N->getOperand(1); // Get the pointer.
415 MVT VT = N->getValueType(0);
417 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
418 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
420 // Increment the arg pointer, VAList, to the next vaarg
421 // FIXME: should the ABI size be used for the increment? Think of
422 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
423 // integers of unusual size (such MVT::i1, which gives an increment
425 unsigned Increment = VT.getSizeInBits() / 8;
426 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
427 DAG.getConstant(Increment, TLI.getPointerTy()));
429 // Store the incremented VAList to the pointer.
430 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
432 // Load the actual argument out of the arg pointer VAList.
433 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
434 VAList, NULL, 0, VT);
436 // Legalized the chain result - switch anything that used the old chain to
438 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1));
443 //===----------------------------------------------------------------------===//
444 // Integer Operand Promotion
445 //===----------------------------------------------------------------------===//
447 /// PromoteIntegerOperand - This method is called when the specified operand of
448 /// the specified node is found to need promotion. At this point, all of the
449 /// result types of the node are known to be legal, but other operands of the
450 /// node may need promotion or expansion as well as the specified one.
451 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
452 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
453 SDOperand Res = SDOperand();
455 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
456 == TargetLowering::Custom)
457 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
460 switch (N->getOpcode()) {
463 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
464 N->dump(&DAG); cerr << "\n";
466 assert(0 && "Do not know how to promote this operator's operand!");
469 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
470 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
471 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
472 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
473 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
474 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
475 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
476 case ISD::INSERT_VECTOR_ELT:
477 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
478 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
479 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
480 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
481 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
482 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
483 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
485 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
486 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
488 case ISD::SINT_TO_FP:
489 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
493 // If the result is null, the sub-method took care of registering results etc.
494 if (!Res.Val) return false;
495 // If the result is N, the sub-method updated N in place.
497 // Mark N as new and remark N and its operands. This allows us to correctly
498 // revisit N if it needs another step of promotion and allows us to visit
499 // any new operands to N.
504 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
505 "Invalid operand expansion");
507 ReplaceValueWith(SDOperand(N, 0), Res);
511 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
512 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
513 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
514 ISD::CondCode CCCode) {
515 MVT VT = NewLHS.getValueType();
517 // Get the promoted values.
518 NewLHS = GetPromotedInteger(NewLHS);
519 NewRHS = GetPromotedInteger(NewRHS);
521 // Otherwise, we have to insert explicit sign or zero extends. Note
522 // that we could insert sign extends for ALL conditions, but zero extend
523 // is cheaper on many machines (an AND instead of two shifts), so prefer
526 default: assert(0 && "Unknown integer comparison!");
533 // ALL of these operations will work if we either sign or zero extend
534 // the operands (including the unsigned comparisons!). Zero extend is
535 // usually a simpler/cheaper operation, so prefer it.
536 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
537 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
543 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
544 DAG.getValueType(VT));
545 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
546 DAG.getValueType(VT));
551 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
552 SDOperand Op = GetPromotedInteger(N->getOperand(0));
553 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
556 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
557 assert(OpNo == 2 && "Don't know how to promote this operand!");
559 SDOperand LHS = N->getOperand(2);
560 SDOperand RHS = N->getOperand(3);
561 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
563 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
565 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
566 N->getOperand(1), LHS, RHS, N->getOperand(4));
569 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
570 assert(OpNo == 1 && "only know how to promote condition");
571 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
573 // The top bits of the promoted condition are not necessarily zero, ensure
574 // that the value is properly zero extended.
575 unsigned BitWidth = Cond.getValueSizeInBits();
576 if (!DAG.MaskedValueIsZero(Cond,
577 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
578 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
580 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
581 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
585 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
586 // Since the result type is legal, the operands must promote to it.
587 MVT OVT = N->getOperand(0).getValueType();
588 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
589 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
590 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
592 Lo = DAG.getZeroExtendInReg(Lo, OVT);
593 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
594 DAG.getConstant(OVT.getSizeInBits(),
595 TLI.getShiftAmountTy()));
596 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
599 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
600 // The vector type is legal but the element type is not. This implies
601 // that the vector is a power-of-two in length and that the element
602 // type does not have a strange size (eg: it is not i1).
603 MVT VecVT = N->getValueType(0);
604 unsigned NumElts = VecVT.getVectorNumElements();
605 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
607 // Build a vector of half the length out of elements of twice the bitwidth.
608 // For example <4 x i16> -> <2 x i32>.
609 MVT OldVT = N->getOperand(0).getValueType();
610 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
611 assert(OldVT.isSimple() && NewVT.isSimple());
613 std::vector<SDOperand> NewElts;
614 NewElts.reserve(NumElts/2);
616 for (unsigned i = 0; i < NumElts; i += 2) {
617 // Combine two successive elements into one promoted element.
618 SDOperand Lo = N->getOperand(i);
619 SDOperand Hi = N->getOperand(i+1);
620 if (TLI.isBigEndian())
622 NewElts.push_back(JoinIntegers(Lo, Hi));
625 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
626 MVT::getVectorVT(NewVT, NewElts.size()),
627 &NewElts[0], NewElts.size());
629 // Convert the new vector to the old vector type.
630 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
633 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
634 SDOperand Op = GetPromotedInteger(N->getOperand(0));
635 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
638 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
639 SDOperand Op = GetPromotedInteger(N->getOperand(0));
640 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
641 DAG.getIntPtrConstant(0));
644 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
647 // Promote the inserted value. This is valid because the type does not
648 // have to match the vector element type.
650 // Check that any extra bits introduced will be truncated away.
651 assert(N->getOperand(1).getValueType().getSizeInBits() >=
652 N->getValueType(0).getVectorElementType().getSizeInBits() &&
653 "Type of inserted value narrower than vector element type!");
654 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
655 GetPromotedInteger(N->getOperand(1)),
659 assert(OpNo == 2 && "Different operand and result vector types?");
661 // Promote the index.
662 SDOperand Idx = N->getOperand(2);
663 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
664 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
665 N->getOperand(1), Idx);
668 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
669 SDOperand In = GetPromotedInteger(N->getOperand(0));
670 MVT OpVT = N->getOperand(0).getValueType();
671 if (N->getOpcode() == ISD::UINT_TO_FP)
672 In = DAG.getZeroExtendInReg(In, OpVT);
674 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
675 In, DAG.getValueType(OpVT));
677 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
680 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
682 NewOps[0] = N->getOperand(0);
683 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
684 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
685 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
687 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
688 array_lengthof(NewOps));
691 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
692 assert(OpNo == 0 && "Only know how to promote condition");
693 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
695 // The top bits of the promoted condition are not necessarily zero, ensure
696 // that the value is properly zero extended.
697 unsigned BitWidth = Cond.getValueSizeInBits();
698 if (!DAG.MaskedValueIsZero(Cond,
699 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
700 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
702 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
703 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
707 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
708 assert(OpNo == 0 && "Don't know how to promote this operand!");
710 SDOperand LHS = N->getOperand(0);
711 SDOperand RHS = N->getOperand(1);
712 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
714 // The CC (#4) and the possible return values (#2 and #3) have legal types.
715 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2),
716 N->getOperand(3), N->getOperand(4));
719 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
720 assert(OpNo == 0 && "Don't know how to promote this operand!");
722 SDOperand LHS = N->getOperand(0);
723 SDOperand RHS = N->getOperand(1);
724 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
726 // The CC (#2) is always legal.
727 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
730 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
731 SDOperand Op = GetPromotedInteger(N->getOperand(0));
732 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
733 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
734 Op, DAG.getValueType(N->getOperand(0).getValueType()));
737 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
738 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
739 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
740 int SVOffset = N->getSrcValueOffset();
741 unsigned Alignment = N->getAlignment();
742 bool isVolatile = N->isVolatile();
744 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
746 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
748 // Truncate the value and store the result.
749 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
750 SVOffset, N->getMemoryVT(),
751 isVolatile, Alignment);
754 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
755 SDOperand Op = GetPromotedInteger(N->getOperand(0));
756 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
759 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
760 SDOperand Op = GetPromotedInteger(N->getOperand(0));
761 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
762 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
766 //===----------------------------------------------------------------------===//
767 // Integer Result Expansion
768 //===----------------------------------------------------------------------===//
770 /// ExpandIntegerResult - This method is called when the specified result of the
771 /// specified node is found to need expansion. At this point, the node may also
772 /// have invalid operands or may have other results that need promotion, we just
773 /// know that (at least) one result needs expansion.
774 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
775 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
777 Lo = Hi = SDOperand();
779 // See if the target wants to custom expand this node.
780 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
781 TargetLowering::Custom) {
782 // If the target wants to, allow it to lower this itself.
783 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
784 // Everything that once used N now uses P. We are guaranteed that the
785 // result value types of N and the result value types of P match.
786 ReplaceNodeWith(N, P);
791 switch (N->getOpcode()) {
794 cerr << "ExpandIntegerResult #" << ResNo << ": ";
795 N->dump(&DAG); cerr << "\n";
797 assert(0 && "Do not know how to expand the result of this operator!");
800 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
801 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
802 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
803 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
805 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
806 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
807 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
808 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
810 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
811 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
812 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
813 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
814 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
815 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
816 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
817 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
818 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
819 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
823 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
824 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
826 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
828 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
830 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
831 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
832 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
833 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
834 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
835 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
838 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
840 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
841 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
842 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
845 // If Lo/Hi is null, the sub-method took care of registering results etc.
847 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
850 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
851 SDOperand &Lo, SDOperand &Hi) {
852 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
853 unsigned NBitWidth = NVT.getSizeInBits();
854 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
855 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
856 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
859 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
860 SDOperand &Lo, SDOperand &Hi) {
861 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
862 SDOperand Op = N->getOperand(0);
863 if (Op.getValueType().bitsLE(NVT)) {
864 // The low part is any extension of the input (which degenerates to a copy).
865 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
866 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
868 // For example, extension of an i48 to an i64. The operand type necessarily
869 // promotes to the result type, so will end up being expanded too.
870 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
871 "Only know how to promote this result!");
872 SDOperand Res = GetPromotedInteger(Op);
873 assert(Res.getValueType() == N->getValueType(0) &&
874 "Operand over promoted?");
875 // Split the promoted operand. This will simplify when it is expanded.
876 SplitInteger(Res, Lo, Hi);
880 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
881 SDOperand &Lo, SDOperand &Hi) {
882 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
883 SDOperand Op = N->getOperand(0);
884 if (Op.getValueType().bitsLE(NVT)) {
885 // The low part is zero extension of the input (which degenerates to a copy).
886 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
887 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
889 // For example, extension of an i48 to an i64. The operand type necessarily
890 // promotes to the result type, so will end up being expanded too.
891 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
892 "Only know how to promote this result!");
893 SDOperand Res = GetPromotedInteger(Op);
894 assert(Res.getValueType() == N->getValueType(0) &&
895 "Operand over promoted?");
896 // Split the promoted operand. This will simplify when it is expanded.
897 SplitInteger(Res, Lo, Hi);
898 unsigned ExcessBits =
899 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
900 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
904 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
905 SDOperand &Lo, SDOperand &Hi) {
906 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
907 SDOperand Op = N->getOperand(0);
908 if (Op.getValueType().bitsLE(NVT)) {
909 // The low part is sign extension of the input (which degenerates to a copy).
910 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
911 // The high part is obtained by SRA'ing all but one of the bits of low part.
912 unsigned LoSize = NVT.getSizeInBits();
913 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
914 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
916 // For example, extension of an i48 to an i64. The operand type necessarily
917 // promotes to the result type, so will end up being expanded too.
918 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
919 "Only know how to promote this result!");
920 SDOperand Res = GetPromotedInteger(Op);
921 assert(Res.getValueType() == N->getValueType(0) &&
922 "Operand over promoted?");
923 // Split the promoted operand. This will simplify when it is expanded.
924 SplitInteger(Res, Lo, Hi);
925 unsigned ExcessBits =
926 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
927 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
928 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
932 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
933 SDOperand &Lo, SDOperand &Hi) {
934 GetExpandedInteger(N->getOperand(0), Lo, Hi);
935 MVT NVT = Lo.getValueType();
936 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
937 unsigned NVTBits = NVT.getSizeInBits();
938 unsigned EVTBits = EVT.getSizeInBits();
940 if (NVTBits < EVTBits) {
941 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
942 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
944 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
945 // The high part must be zero, make it explicit.
946 Hi = DAG.getConstant(0, NVT);
950 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
951 SDOperand &Lo, SDOperand &Hi) {
952 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
953 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
954 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
955 DAG.getConstant(NVT.getSizeInBits(),
956 TLI.getShiftAmountTy()));
957 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
960 void DAGTypeLegalizer::
961 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
962 GetExpandedInteger(N->getOperand(0), Lo, Hi);
963 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
965 if (EVT.bitsLE(Lo.getValueType())) {
966 // sext_inreg the low part if needed.
967 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
970 // The high part gets the sign extension from the lo-part. This handles
971 // things like sextinreg V:i64 from i8.
972 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
973 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
974 TLI.getShiftAmountTy()));
976 // For example, extension of an i48 to an i64. Leave the low part alone,
977 // sext_inreg the high part.
978 unsigned ExcessBits =
979 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
980 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
981 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
985 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
987 MVT VT = N->getValueType(0);
988 SDOperand Op = N->getOperand(0);
989 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
991 if (VT == MVT::i32) {
992 if (Op.getValueType() == MVT::f32)
993 LC = RTLIB::FPTOSINT_F32_I32;
994 else if (Op.getValueType() == MVT::f64)
995 LC = RTLIB::FPTOSINT_F64_I32;
996 else if (Op.getValueType() == MVT::f80)
997 LC = RTLIB::FPTOSINT_F80_I32;
998 else if (Op.getValueType() == MVT::ppcf128)
999 LC = RTLIB::FPTOSINT_PPCF128_I32;
1000 } else if (VT == MVT::i64) {
1001 if (Op.getValueType() == MVT::f32)
1002 LC = RTLIB::FPTOSINT_F32_I64;
1003 else if (Op.getValueType() == MVT::f64)
1004 LC = RTLIB::FPTOSINT_F64_I64;
1005 else if (Op.getValueType() == MVT::f80)
1006 LC = RTLIB::FPTOSINT_F80_I64;
1007 else if (Op.getValueType() == MVT::ppcf128)
1008 LC = RTLIB::FPTOSINT_PPCF128_I64;
1009 } else if (VT == MVT::i128) {
1010 if (Op.getValueType() == MVT::f32)
1011 LC = RTLIB::FPTOSINT_F32_I128;
1012 else if (Op.getValueType() == MVT::f64)
1013 LC = RTLIB::FPTOSINT_F64_I128;
1014 else if (Op.getValueType() == MVT::f80)
1015 LC = RTLIB::FPTOSINT_F80_I128;
1016 else if (Op.getValueType() == MVT::ppcf128)
1017 LC = RTLIB::FPTOSINT_PPCF128_I128;
1019 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1020 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1023 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
1025 MVT VT = N->getValueType(0);
1026 SDOperand Op = N->getOperand(0);
1027 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1028 if (VT == MVT::i32) {
1029 if (Op.getValueType() == MVT::f32)
1030 LC = RTLIB::FPTOUINT_F32_I32;
1031 else if (Op.getValueType() == MVT::f64)
1032 LC = RTLIB::FPTOUINT_F64_I32;
1033 else if (Op.getValueType() == MVT::f80)
1034 LC = RTLIB::FPTOUINT_F80_I32;
1035 else if (Op.getValueType() == MVT::ppcf128)
1036 LC = RTLIB::FPTOUINT_PPCF128_I32;
1037 } else if (VT == MVT::i64) {
1038 if (Op.getValueType() == MVT::f32)
1039 LC = RTLIB::FPTOUINT_F32_I64;
1040 else if (Op.getValueType() == MVT::f64)
1041 LC = RTLIB::FPTOUINT_F64_I64;
1042 else if (Op.getValueType() == MVT::f80)
1043 LC = RTLIB::FPTOUINT_F80_I64;
1044 else if (Op.getValueType() == MVT::ppcf128)
1045 LC = RTLIB::FPTOUINT_PPCF128_I64;
1046 } else if (VT == MVT::i128) {
1047 if (Op.getValueType() == MVT::f32)
1048 LC = RTLIB::FPTOUINT_F32_I128;
1049 else if (Op.getValueType() == MVT::f64)
1050 LC = RTLIB::FPTOUINT_F64_I128;
1051 else if (Op.getValueType() == MVT::f80)
1052 LC = RTLIB::FPTOUINT_F80_I128;
1053 else if (Op.getValueType() == MVT::ppcf128)
1054 LC = RTLIB::FPTOUINT_PPCF128_I128;
1056 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1057 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1060 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1061 SDOperand &Lo, SDOperand &Hi) {
1062 if (ISD::isNormalLoad(N)) {
1063 ExpandRes_NormalLoad(N, Lo, Hi);
1067 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1069 MVT VT = N->getValueType(0);
1070 MVT NVT = TLI.getTypeToTransformTo(VT);
1071 SDOperand Ch = N->getChain();
1072 SDOperand Ptr = N->getBasePtr();
1073 ISD::LoadExtType ExtType = N->getExtensionType();
1074 int SVOffset = N->getSrcValueOffset();
1075 unsigned Alignment = N->getAlignment();
1076 bool isVolatile = N->isVolatile();
1078 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1080 if (N->getMemoryVT().bitsLE(NVT)) {
1081 MVT EVT = N->getMemoryVT();
1083 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1084 isVolatile, Alignment);
1086 // Remember the chain.
1087 Ch = Lo.getValue(1);
1089 if (ExtType == ISD::SEXTLOAD) {
1090 // The high part is obtained by SRA'ing all but one of the bits of the
1092 unsigned LoSize = Lo.getValueType().getSizeInBits();
1093 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1094 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1095 } else if (ExtType == ISD::ZEXTLOAD) {
1096 // The high part is just a zero.
1097 Hi = DAG.getConstant(0, NVT);
1099 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1100 // The high part is undefined.
1101 Hi = DAG.getNode(ISD::UNDEF, NVT);
1103 } else if (TLI.isLittleEndian()) {
1104 // Little-endian - low bits are at low addresses.
1105 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1106 isVolatile, Alignment);
1108 unsigned ExcessBits =
1109 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1110 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1112 // Increment the pointer to the other half.
1113 unsigned IncrementSize = NVT.getSizeInBits()/8;
1114 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1115 DAG.getIntPtrConstant(IncrementSize));
1116 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1117 SVOffset+IncrementSize, NEVT,
1118 isVolatile, MinAlign(Alignment, IncrementSize));
1120 // Build a factor node to remember that this load is independent of the
1122 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1125 // Big-endian - high bits are at low addresses. Favor aligned loads at
1126 // the cost of some bit-fiddling.
1127 MVT EVT = N->getMemoryVT();
1128 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1129 unsigned IncrementSize = NVT.getSizeInBits()/8;
1130 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1132 // Load both the high bits and maybe some of the low bits.
1133 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1134 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1135 isVolatile, Alignment);
1137 // Increment the pointer to the other half.
1138 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1139 DAG.getIntPtrConstant(IncrementSize));
1140 // Load the rest of the low bits.
1141 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1142 SVOffset+IncrementSize,
1143 MVT::getIntegerVT(ExcessBits),
1144 isVolatile, MinAlign(Alignment, IncrementSize));
1146 // Build a factor node to remember that this load is independent of the
1148 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1151 if (ExcessBits < NVT.getSizeInBits()) {
1152 // Transfer low bits from the bottom of Hi to the top of Lo.
1153 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1154 DAG.getNode(ISD::SHL, NVT, Hi,
1155 DAG.getConstant(ExcessBits,
1156 TLI.getShiftAmountTy())));
1157 // Move high bits to the right position in Hi.
1158 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1159 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1160 TLI.getShiftAmountTy()));
1164 // Legalized the chain result - switch anything that used the old chain to
1166 ReplaceValueWith(SDOperand(N, 1), Ch);
1169 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1170 SDOperand &Lo, SDOperand &Hi) {
1171 SDOperand LL, LH, RL, RH;
1172 GetExpandedInteger(N->getOperand(0), LL, LH);
1173 GetExpandedInteger(N->getOperand(1), RL, RH);
1174 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1175 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1178 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1179 SDOperand &Lo, SDOperand &Hi) {
1180 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1181 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1182 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1185 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1186 SDOperand &Lo, SDOperand &Hi) {
1187 // Expand the subcomponents.
1188 SDOperand LHSL, LHSH, RHSL, RHSH;
1189 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1190 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1191 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1192 SDOperand LoOps[2] = { LHSL, RHSL };
1193 SDOperand HiOps[3] = { LHSH, RHSH };
1195 if (N->getOpcode() == ISD::ADD) {
1196 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1197 HiOps[2] = Lo.getValue(1);
1198 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1200 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1201 HiOps[2] = Lo.getValue(1);
1202 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1206 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1207 SDOperand &Lo, SDOperand &Hi) {
1208 // Expand the subcomponents.
1209 SDOperand LHSL, LHSH, RHSL, RHSH;
1210 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1211 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1212 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1213 SDOperand LoOps[2] = { LHSL, RHSL };
1214 SDOperand HiOps[3] = { LHSH, RHSH };
1216 if (N->getOpcode() == ISD::ADDC) {
1217 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1218 HiOps[2] = Lo.getValue(1);
1219 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1221 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1222 HiOps[2] = Lo.getValue(1);
1223 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1226 // Legalized the flag result - switch anything that used the old flag to
1228 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1231 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1232 SDOperand &Lo, SDOperand &Hi) {
1233 // Expand the subcomponents.
1234 SDOperand LHSL, LHSH, RHSL, RHSH;
1235 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1236 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1237 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1238 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1239 SDOperand HiOps[3] = { LHSH, RHSH };
1241 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1242 HiOps[2] = Lo.getValue(1);
1243 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1245 // Legalized the flag result - switch anything that used the old flag to
1247 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1250 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1251 SDOperand &Lo, SDOperand &Hi) {
1252 MVT VT = N->getValueType(0);
1253 MVT NVT = TLI.getTypeToTransformTo(VT);
1255 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1256 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1257 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1258 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1259 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1260 SDOperand LL, LH, RL, RH;
1261 GetExpandedInteger(N->getOperand(0), LL, LH);
1262 GetExpandedInteger(N->getOperand(1), RL, RH);
1263 unsigned OuterBitSize = VT.getSizeInBits();
1264 unsigned InnerBitSize = NVT.getSizeInBits();
1265 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1266 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1268 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1269 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1270 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1271 // The inputs are both zero-extended.
1273 // We can emit a umul_lohi.
1274 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1275 Hi = SDOperand(Lo.Val, 1);
1279 // We can emit a mulhu+mul.
1280 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1281 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1285 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1286 // The input values are both sign-extended.
1288 // We can emit a smul_lohi.
1289 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1290 Hi = SDOperand(Lo.Val, 1);
1294 // We can emit a mulhs+mul.
1295 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1296 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1301 // Lo,Hi = umul LHS, RHS.
1302 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1303 DAG.getVTList(NVT, NVT), LL, RL);
1305 Hi = UMulLOHI.getValue(1);
1306 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1307 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1308 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1309 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1313 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1314 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1315 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1316 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1317 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1318 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1323 // If nothing else, we can make a libcall.
1324 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1326 LC = RTLIB::MUL_I32;
1327 else if (VT == MVT::i64)
1328 LC = RTLIB::MUL_I64;
1329 else if (VT == MVT::i128)
1330 LC = RTLIB::MUL_I128;
1331 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1333 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1334 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1337 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1338 SDOperand &Lo, SDOperand &Hi) {
1339 MVT VT = N->getValueType(0);
1341 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1343 LC = RTLIB::SDIV_I32;
1344 else if (VT == MVT::i64)
1345 LC = RTLIB::SDIV_I64;
1346 else if (VT == MVT::i128)
1347 LC = RTLIB::SDIV_I128;
1348 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1350 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1351 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1354 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1355 SDOperand &Lo, SDOperand &Hi) {
1356 MVT VT = N->getValueType(0);
1358 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1360 LC = RTLIB::SREM_I32;
1361 else if (VT == MVT::i64)
1362 LC = RTLIB::SREM_I64;
1363 else if (VT == MVT::i128)
1364 LC = RTLIB::SREM_I128;
1365 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1367 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1368 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1371 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1372 SDOperand &Lo, SDOperand &Hi) {
1373 MVT VT = N->getValueType(0);
1375 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1377 LC = RTLIB::UDIV_I32;
1378 else if (VT == MVT::i64)
1379 LC = RTLIB::UDIV_I64;
1380 else if (VT == MVT::i128)
1381 LC = RTLIB::UDIV_I128;
1382 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1384 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1385 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1388 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1389 SDOperand &Lo, SDOperand &Hi) {
1390 MVT VT = N->getValueType(0);
1392 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1394 LC = RTLIB::UREM_I32;
1395 else if (VT == MVT::i64)
1396 LC = RTLIB::UREM_I64;
1397 else if (VT == MVT::i128)
1398 LC = RTLIB::UREM_I128;
1399 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1401 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1402 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1405 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1406 SDOperand &Lo, SDOperand &Hi) {
1407 MVT VT = N->getValueType(0);
1409 // If we can emit an efficient shift operation, do so now. Check to see if
1410 // the RHS is a constant.
1411 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1412 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1414 // If we can determine that the high bit of the shift is zero or one, even if
1415 // the low bits are variable, emit this shift in an optimized form.
1416 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1419 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1421 if (N->getOpcode() == ISD::SHL) {
1422 PartsOpc = ISD::SHL_PARTS;
1423 } else if (N->getOpcode() == ISD::SRL) {
1424 PartsOpc = ISD::SRL_PARTS;
1426 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1427 PartsOpc = ISD::SRA_PARTS;
1430 // Next check to see if the target supports this SHL_PARTS operation or if it
1431 // will custom expand it.
1432 MVT NVT = TLI.getTypeToTransformTo(VT);
1433 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1434 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1435 Action == TargetLowering::Custom) {
1436 // Expand the subcomponents.
1437 SDOperand LHSL, LHSH;
1438 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1440 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1441 MVT VT = LHSL.getValueType();
1442 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1443 Hi = Lo.getValue(1);
1447 // Otherwise, emit a libcall.
1448 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1450 if (N->getOpcode() == ISD::SHL) {
1451 isSigned = false; /*sign irrelevant*/
1453 LC = RTLIB::SHL_I32;
1454 else if (VT == MVT::i64)
1455 LC = RTLIB::SHL_I64;
1456 else if (VT == MVT::i128)
1457 LC = RTLIB::SHL_I128;
1458 } else if (N->getOpcode() == ISD::SRL) {
1461 LC = RTLIB::SRL_I32;
1462 else if (VT == MVT::i64)
1463 LC = RTLIB::SRL_I64;
1464 else if (VT == MVT::i128)
1465 LC = RTLIB::SRL_I128;
1467 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1470 LC = RTLIB::SRA_I32;
1471 else if (VT == MVT::i64)
1472 LC = RTLIB::SRA_I64;
1473 else if (VT == MVT::i128)
1474 LC = RTLIB::SRA_I128;
1476 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1478 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1479 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1482 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1483 SDOperand &Lo, SDOperand &Hi) {
1484 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1485 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1486 MVT NVT = Lo.getValueType();
1488 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1489 DAG.getConstant(0, NVT), ISD::SETNE);
1491 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1492 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1494 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1495 DAG.getNode(ISD::ADD, NVT, LoLZ,
1496 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1497 Hi = DAG.getConstant(0, NVT);
1500 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1501 SDOperand &Lo, SDOperand &Hi) {
1502 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1503 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1504 MVT NVT = Lo.getValueType();
1505 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1506 DAG.getNode(ISD::CTPOP, NVT, Hi));
1507 Hi = DAG.getConstant(0, NVT);
1510 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1511 SDOperand &Lo, SDOperand &Hi) {
1512 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1513 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1514 MVT NVT = Lo.getValueType();
1516 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1517 DAG.getConstant(0, NVT), ISD::SETNE);
1519 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1520 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1522 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1523 DAG.getNode(ISD::ADD, NVT, HiLZ,
1524 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1525 Hi = DAG.getConstant(0, NVT);
1528 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1529 /// and the shift amount is a constant 'Amt'. Expand the operation.
1530 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1531 SDOperand &Lo, SDOperand &Hi) {
1532 // Expand the incoming operand to be shifted, so that we have its parts
1534 GetExpandedInteger(N->getOperand(0), InL, InH);
1536 MVT NVT = InL.getValueType();
1537 unsigned VTBits = N->getValueType(0).getSizeInBits();
1538 unsigned NVTBits = NVT.getSizeInBits();
1539 MVT ShTy = N->getOperand(1).getValueType();
1541 if (N->getOpcode() == ISD::SHL) {
1543 Lo = Hi = DAG.getConstant(0, NVT);
1544 } else if (Amt > NVTBits) {
1545 Lo = DAG.getConstant(0, NVT);
1546 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1547 } else if (Amt == NVTBits) {
1548 Lo = DAG.getConstant(0, NVT);
1550 } else if (Amt == 1) {
1551 // Emit this X << 1 as X+X.
1552 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1553 SDOperand LoOps[2] = { InL, InL };
1554 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1555 SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
1556 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1558 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1559 Hi = DAG.getNode(ISD::OR, NVT,
1560 DAG.getNode(ISD::SHL, NVT, InH,
1561 DAG.getConstant(Amt, ShTy)),
1562 DAG.getNode(ISD::SRL, NVT, InL,
1563 DAG.getConstant(NVTBits-Amt, ShTy)));
1568 if (N->getOpcode() == ISD::SRL) {
1570 Lo = DAG.getConstant(0, NVT);
1571 Hi = DAG.getConstant(0, NVT);
1572 } else if (Amt > NVTBits) {
1573 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1574 Hi = DAG.getConstant(0, NVT);
1575 } else if (Amt == NVTBits) {
1577 Hi = DAG.getConstant(0, NVT);
1579 Lo = DAG.getNode(ISD::OR, NVT,
1580 DAG.getNode(ISD::SRL, NVT, InL,
1581 DAG.getConstant(Amt, ShTy)),
1582 DAG.getNode(ISD::SHL, NVT, InH,
1583 DAG.getConstant(NVTBits-Amt, ShTy)));
1584 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1589 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1591 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1592 DAG.getConstant(NVTBits-1, ShTy));
1593 } else if (Amt > NVTBits) {
1594 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1595 DAG.getConstant(Amt-NVTBits, ShTy));
1596 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1597 DAG.getConstant(NVTBits-1, ShTy));
1598 } else if (Amt == NVTBits) {
1600 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1601 DAG.getConstant(NVTBits-1, ShTy));
1603 Lo = DAG.getNode(ISD::OR, NVT,
1604 DAG.getNode(ISD::SRL, NVT, InL,
1605 DAG.getConstant(Amt, ShTy)),
1606 DAG.getNode(ISD::SHL, NVT, InH,
1607 DAG.getConstant(NVTBits-Amt, ShTy)));
1608 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1612 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1613 /// this shift based on knowledge of the high bit of the shift amount. If we
1614 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1616 bool DAGTypeLegalizer::
1617 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1618 SDOperand Amt = N->getOperand(1);
1619 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1620 MVT ShTy = Amt.getValueType();
1621 unsigned ShBits = ShTy.getSizeInBits();
1622 unsigned NVTBits = NVT.getSizeInBits();
1623 assert(isPowerOf2_32(NVTBits) &&
1624 "Expanded integer type size not a power of two!");
1626 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1627 APInt KnownZero, KnownOne;
1628 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1630 // If we don't know anything about the high bits, exit.
1631 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1634 // Get the incoming operand to be shifted.
1636 GetExpandedInteger(N->getOperand(0), InL, InH);
1638 // If we know that any of the high bits of the shift amount are one, then we
1639 // can do this as a couple of simple shifts.
1640 if (KnownOne.intersects(HighBitMask)) {
1641 // Mask out the high bit, which we know is set.
1642 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1643 DAG.getConstant(~HighBitMask, ShTy));
1645 switch (N->getOpcode()) {
1646 default: assert(0 && "Unknown shift");
1648 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1649 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1652 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1653 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1656 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1657 DAG.getConstant(NVTBits-1, ShTy));
1658 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1663 // If we know that all of the high bits of the shift amount are zero, then we
1664 // can do this as a couple of simple shifts.
1665 if ((KnownZero & HighBitMask) == HighBitMask) {
1667 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1668 DAG.getConstant(NVTBits, ShTy),
1671 switch (N->getOpcode()) {
1672 default: assert(0 && "Unknown shift");
1673 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1675 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1678 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1679 Hi = DAG.getNode(ISD::OR, NVT,
1680 DAG.getNode(Op1, NVT, InH, Amt),
1681 DAG.getNode(Op2, NVT, InL, Amt2));
1689 //===----------------------------------------------------------------------===//
1690 // Integer Operand Expansion
1691 //===----------------------------------------------------------------------===//
1693 /// ExpandIntegerOperand - This method is called when the specified operand of
1694 /// the specified node is found to need expansion. At this point, all of the
1695 /// result types of the node are known to be legal, but other operands of the
1696 /// node may need promotion or expansion as well as the specified one.
1697 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1698 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1699 SDOperand Res = SDOperand();
1701 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1702 == TargetLowering::Custom)
1703 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
1706 switch (N->getOpcode()) {
1709 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1710 N->dump(&DAG); cerr << "\n";
1712 assert(0 && "Do not know how to expand this operator's operand!");
1715 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1716 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1717 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1719 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1721 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1722 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1724 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1725 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1726 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1729 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1734 // If the result is null, the sub-method took care of registering results etc.
1735 if (!Res.Val) return false;
1736 // If the result is N, the sub-method updated N in place. Check to see if any
1737 // operands are new, and if so, mark them.
1739 // Mark N as new and remark N and its operands. This allows us to correctly
1740 // revisit N if it needs another step of expansion and allows us to visit
1741 // any new operands to N.
1746 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1747 "Invalid operand expansion");
1749 ReplaceValueWith(SDOperand(N, 0), Res);
1753 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1755 GetExpandedInteger(N->getOperand(0), InL, InH);
1756 // Just truncate the low part of the source.
1757 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
1760 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
1761 SDOperand Op = N->getOperand(0);
1762 MVT SrcVT = Op.getValueType();
1763 MVT DstVT = N->getValueType(0);
1765 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1766 if (SrcVT == MVT::i32) {
1767 if (DstVT == MVT::f32)
1768 LC = RTLIB::SINTTOFP_I32_F32;
1769 else if (DstVT == MVT::f64)
1770 LC = RTLIB::SINTTOFP_I32_F64;
1771 else if (DstVT == MVT::f80)
1772 LC = RTLIB::SINTTOFP_I32_F80;
1773 else if (DstVT == MVT::ppcf128)
1774 LC = RTLIB::SINTTOFP_I32_PPCF128;
1775 } else if (SrcVT == MVT::i64) {
1776 if (DstVT == MVT::f32)
1777 LC = RTLIB::SINTTOFP_I64_F32;
1778 else if (DstVT == MVT::f64)
1779 LC = RTLIB::SINTTOFP_I64_F64;
1780 else if (DstVT == MVT::f80)
1781 LC = RTLIB::SINTTOFP_I64_F80;
1782 else if (DstVT == MVT::ppcf128)
1783 LC = RTLIB::SINTTOFP_I64_PPCF128;
1784 } else if (SrcVT == MVT::i128) {
1785 if (DstVT == MVT::f32)
1786 LC = RTLIB::SINTTOFP_I128_F32;
1787 else if (DstVT == MVT::f64)
1788 LC = RTLIB::SINTTOFP_I128_F64;
1789 else if (DstVT == MVT::f80)
1790 LC = RTLIB::SINTTOFP_I128_F80;
1791 else if (DstVT == MVT::ppcf128)
1792 LC = RTLIB::SINTTOFP_I128_PPCF128;
1794 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1795 "Don't know how to expand this SINT_TO_FP!");
1797 return MakeLibCall(LC, DstVT, &Op, 1, true);
1800 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
1801 SDOperand Op = N->getOperand(0);
1802 MVT SrcVT = Op.getValueType();
1803 MVT DstVT = N->getValueType(0);
1805 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
1806 // Do a signed conversion then adjust the result.
1807 SDOperand SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
1808 SignedConv = TLI.LowerOperation(SignedConv, DAG);
1810 // The result of the signed conversion needs adjusting if the 'sign bit' of
1811 // the incoming integer was set. To handle this, we dynamically test to see
1812 // if it is set, and, if so, add a fudge factor.
1814 const uint64_t F32TwoE32 = 0x4F800000ULL;
1815 const uint64_t F32TwoE64 = 0x5F800000ULL;
1816 const uint64_t F32TwoE128 = 0x7F800000ULL;
1819 if (SrcVT == MVT::i32)
1820 FF = APInt(32, F32TwoE32);
1821 else if (SrcVT == MVT::i64)
1822 FF = APInt(32, F32TwoE64);
1823 else if (SrcVT == MVT::i128)
1824 FF = APInt(32, F32TwoE128);
1826 assert(false && "Unsupported UINT_TO_FP!");
1828 // Check whether the sign bit is set.
1830 GetExpandedInteger(Op, Lo, Hi);
1831 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1832 DAG.getConstant(0, Hi.getValueType()),
1835 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
1836 SDOperand FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
1837 TLI.getPointerTy());
1839 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
1840 SDOperand Zero = DAG.getIntPtrConstant(0);
1841 SDOperand Four = DAG.getIntPtrConstant(4);
1842 if (TLI.isBigEndian()) std::swap(Zero, Four);
1843 SDOperand Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
1845 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
1847 // Load the value out, extending it from f32 to the destination float type.
1848 // FIXME: Avoid the extend by constructing the right constant pool?
1849 SDOperand Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
1850 FudgePtr, NULL, 0, MVT::f32);
1851 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
1854 // Otherwise, use a libcall.
1855 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1856 if (SrcVT == MVT::i32) {
1857 if (DstVT == MVT::f32)
1858 LC = RTLIB::UINTTOFP_I32_F32;
1859 else if (DstVT == MVT::f64)
1860 LC = RTLIB::UINTTOFP_I32_F64;
1861 else if (DstVT == MVT::f80)
1862 LC = RTLIB::UINTTOFP_I32_F80;
1863 else if (DstVT == MVT::ppcf128)
1864 LC = RTLIB::UINTTOFP_I32_PPCF128;
1865 } else if (SrcVT == MVT::i64) {
1866 if (DstVT == MVT::f32)
1867 LC = RTLIB::UINTTOFP_I64_F32;
1868 else if (DstVT == MVT::f64)
1869 LC = RTLIB::UINTTOFP_I64_F64;
1870 else if (DstVT == MVT::f80)
1871 LC = RTLIB::UINTTOFP_I64_F80;
1872 else if (DstVT == MVT::ppcf128)
1873 LC = RTLIB::UINTTOFP_I64_PPCF128;
1874 } else if (SrcVT == MVT::i128) {
1875 if (DstVT == MVT::f32)
1876 LC = RTLIB::UINTTOFP_I128_F32;
1877 else if (DstVT == MVT::f64)
1878 LC = RTLIB::UINTTOFP_I128_F64;
1879 else if (DstVT == MVT::f80)
1880 LC = RTLIB::UINTTOFP_I128_F80;
1881 else if (DstVT == MVT::ppcf128)
1882 LC = RTLIB::UINTTOFP_I128_PPCF128;
1884 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1885 "Don't know how to expand this UINT_TO_FP!");
1887 return MakeLibCall(LC, DstVT, &Op, 1, true);
1890 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1891 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1892 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1893 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1895 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1896 // against zero to select between true and false values.
1897 if (NewRHS.Val == 0) {
1898 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1899 CCCode = ISD::SETNE;
1902 // Update N to have the operands specified.
1903 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1904 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1908 SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1909 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1910 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1911 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1913 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1914 // against zero to select between true and false values.
1915 if (NewRHS.Val == 0) {
1916 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1917 CCCode = ISD::SETNE;
1920 // Update N to have the operands specified.
1921 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1922 N->getOperand(2), N->getOperand(3),
1923 DAG.getCondCode(CCCode));
1926 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1927 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1928 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1929 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1931 // If ExpandSetCCOperands returned a scalar, use it.
1932 if (NewRHS.Val == 0) {
1933 assert(NewLHS.getValueType() == N->getValueType(0) &&
1934 "Unexpected setcc expansion!");
1938 // Otherwise, update N to have the operands specified.
1939 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1940 DAG.getCondCode(CCCode));
1943 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1944 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1945 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS,
1947 ISD::CondCode &CCCode) {
1948 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1949 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1950 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1952 MVT VT = NewLHS.getValueType();
1954 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1955 if (RHSLo == RHSHi) {
1956 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1957 if (RHSCST->isAllOnesValue()) {
1958 // Equality comparison to -1.
1959 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1966 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1967 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1968 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1969 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1973 // If this is a comparison of the sign bit, just look at the top part.
1975 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1976 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1977 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1983 // FIXME: This generated code sucks.
1984 ISD::CondCode LowCC;
1986 default: assert(0 && "Unknown integer setcc!");
1988 case ISD::SETULT: LowCC = ISD::SETULT; break;
1990 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1992 case ISD::SETULE: LowCC = ISD::SETULE; break;
1994 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1997 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1998 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1999 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2001 // NOTE: on targets without efficient SELECT of bools, we can always use
2002 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2003 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2004 SDOperand Tmp1, Tmp2;
2005 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
2006 false, DagCombineInfo);
2008 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
2009 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2010 CCCode, false, DagCombineInfo);
2012 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2013 DAG.getCondCode(CCCode));
2015 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
2016 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
2017 if ((Tmp1C && Tmp1C->isNullValue()) ||
2018 (Tmp2C && Tmp2C->isNullValue() &&
2019 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2020 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2021 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2022 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2023 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2024 // low part is known false, returns high part.
2025 // For LE / GE, if high part is known false, ignore the low part.
2026 // For LT / GT, if high part is known true, ignore the low part.
2028 NewRHS = SDOperand();
2032 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2033 ISD::SETEQ, false, DagCombineInfo);
2035 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2037 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2038 NewLHS, Tmp1, Tmp2);
2039 NewRHS = SDOperand();
2042 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2043 if (ISD::isNormalStore(N))
2044 return ExpandOp_NormalStore(N, OpNo);
2046 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2047 assert(OpNo == 1 && "Can only expand the stored value so far");
2049 MVT VT = N->getOperand(1).getValueType();
2050 MVT NVT = TLI.getTypeToTransformTo(VT);
2051 SDOperand Ch = N->getChain();
2052 SDOperand Ptr = N->getBasePtr();
2053 int SVOffset = N->getSrcValueOffset();
2054 unsigned Alignment = N->getAlignment();
2055 bool isVolatile = N->isVolatile();
2058 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2060 if (N->getMemoryVT().bitsLE(NVT)) {
2061 GetExpandedInteger(N->getValue(), Lo, Hi);
2062 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2063 N->getMemoryVT(), isVolatile, Alignment);
2064 } else if (TLI.isLittleEndian()) {
2065 // Little-endian - low bits are at low addresses.
2066 GetExpandedInteger(N->getValue(), Lo, Hi);
2068 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2069 isVolatile, Alignment);
2071 unsigned ExcessBits =
2072 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2073 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2075 // Increment the pointer to the other half.
2076 unsigned IncrementSize = NVT.getSizeInBits()/8;
2077 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2078 DAG.getIntPtrConstant(IncrementSize));
2079 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2080 SVOffset+IncrementSize, NEVT,
2081 isVolatile, MinAlign(Alignment, IncrementSize));
2082 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2084 // Big-endian - high bits are at low addresses. Favor aligned stores at
2085 // the cost of some bit-fiddling.
2086 GetExpandedInteger(N->getValue(), Lo, Hi);
2088 MVT EVT = N->getMemoryVT();
2089 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2090 unsigned IncrementSize = NVT.getSizeInBits()/8;
2091 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2092 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2094 if (ExcessBits < NVT.getSizeInBits()) {
2095 // Transfer high bits from the top of Lo to the bottom of Hi.
2096 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2097 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2098 TLI.getShiftAmountTy()));
2099 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2100 DAG.getNode(ISD::SRL, NVT, Lo,
2101 DAG.getConstant(ExcessBits,
2102 TLI.getShiftAmountTy())));
2105 // Store both the high bits and maybe some of the low bits.
2106 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2107 SVOffset, HiVT, isVolatile, Alignment);
2109 // Increment the pointer to the other half.
2110 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2111 DAG.getIntPtrConstant(IncrementSize));
2112 // Store the lowest ExcessBits bits in the second half.
2113 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2114 SVOffset+IncrementSize,
2115 MVT::getIntegerVT(ExcessBits),
2116 isVolatile, MinAlign(Alignment, IncrementSize));
2117 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);