1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
122 // If the result is null then the sub-method took care of registering it.
124 SetPromotedInteger(SDValue(N, ResNo), Res);
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getMemOperand());
147 // Legalized the chain result - switch anything that used the old chain to
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getMemOperand());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
173 switch (getTypeAction(InVT)) {
175 assert(false && "Unknown type action!");
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
185 // Promote the integer operand by hand.
186 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
190 case ScalarizeVector:
191 // Convert the element to an integer and promote it by hand.
192 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
193 BitConvertToInteger(GetScalarizedVector(InOp)));
195 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
196 // pieces of the input into integers and reassemble in the final type.
198 GetSplitVector(N->getOperand(0), Lo, Hi);
199 Lo = BitConvertToInteger(Lo);
200 Hi = BitConvertToInteger(Hi);
202 if (TLI.isBigEndian())
205 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
206 EVT::getIntegerVT(*DAG.getContext(),
207 NOutVT.getSizeInBits()),
208 JoinIntegers(Lo, Hi));
209 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
212 if (OutVT.bitsEq(NInVT))
213 // The input is widened to the same size. Convert to the widened value.
214 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
217 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
218 CreateStackStoreLoad(InOp, OutVT));
221 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
222 SDValue Op = GetPromotedInteger(N->getOperand(0));
223 EVT OVT = N->getValueType(0);
224 EVT NVT = Op.getValueType();
225 DebugLoc dl = N->getDebugLoc();
227 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
228 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
229 DAG.getConstant(DiffBits, TLI.getPointerTy()));
232 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
233 // The pair element type may be legal, or may not promote to the same type as
234 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
235 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
236 TLI.getTypeToTransformTo(*DAG.getContext(),
237 N->getValueType(0)), JoinIntegers(N->getOperand(0),
241 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
242 EVT VT = N->getValueType(0);
243 // FIXME there is no actual debug info here
244 DebugLoc dl = N->getDebugLoc();
245 // Zero extend things like i1, sign extend everything else. It shouldn't
246 // matter in theory which one we pick, but this tends to give better code?
247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
248 SDValue Result = DAG.getNode(Opc, dl,
249 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
251 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
255 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
256 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
257 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
258 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
259 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
260 "can only promote integers");
261 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
262 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
263 N->getOperand(1), N->getOperand(2),
264 N->getOperand(3), N->getOperand(4), CvtCode);
267 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
268 // Zero extend to the promoted type and do the count there.
269 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
270 DebugLoc dl = N->getDebugLoc();
271 EVT OVT = N->getValueType(0);
272 EVT NVT = Op.getValueType();
273 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
274 // Subtract off the extra leading bits in the bigger type.
275 return DAG.getNode(ISD::SUB, dl, NVT, Op,
276 DAG.getConstant(NVT.getSizeInBits() -
277 OVT.getSizeInBits(), NVT));
280 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
281 // Zero extend to the promoted type and do the count there.
282 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
283 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
286 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
287 SDValue Op = GetPromotedInteger(N->getOperand(0));
288 EVT OVT = N->getValueType(0);
289 EVT NVT = Op.getValueType();
290 DebugLoc dl = N->getDebugLoc();
291 // The count is the same in the promoted type except if the original
292 // value was zero. This can be handled by setting the bit just off
293 // the top of the original type.
294 APInt TopBit(NVT.getSizeInBits(), 0);
295 TopBit.setBit(OVT.getSizeInBits());
296 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
297 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
300 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
301 DebugLoc dl = N->getDebugLoc();
302 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
307 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
308 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
309 unsigned NewOpc = N->getOpcode();
310 DebugLoc dl = N->getDebugLoc();
312 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
313 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
314 // and SINT conversions are Custom, there is no way to tell which is
315 // preferable. We choose SINT because that's the right thing on PPC.)
316 if (N->getOpcode() == ISD::FP_TO_UINT &&
317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
318 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
319 NewOpc = ISD::FP_TO_SINT;
321 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
323 // Assert that the converted value fits in the original type. If it doesn't
324 // (eg: because the value being converted is too big), then the result of the
325 // original operation was undefined anyway, so the assert is still correct.
326 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
327 ISD::AssertZext : ISD::AssertSext, dl,
328 NVT, Res, DAG.getValueType(N->getValueType(0)));
331 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
332 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
333 DebugLoc dl = N->getDebugLoc();
335 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
337 return DAG.getNode(ISD::AssertZext, dl,
338 NVT, Res, DAG.getValueType(N->getValueType(0)));
341 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
342 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
343 DebugLoc dl = N->getDebugLoc();
345 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
346 SDValue Res = GetPromotedInteger(N->getOperand(0));
347 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
349 // If the result and operand types are the same after promotion, simplify
350 // to an in-register extension.
351 if (NVT == Res.getValueType()) {
352 // The high bits are not guaranteed to be anything. Insert an extend.
353 if (N->getOpcode() == ISD::SIGN_EXTEND)
354 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
355 DAG.getValueType(N->getOperand(0).getValueType()));
356 if (N->getOpcode() == ISD::ZERO_EXTEND)
357 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
358 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
363 // Otherwise, just extend the original operand all the way to the larger type.
364 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
367 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
368 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
370 ISD::LoadExtType ExtType =
371 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
372 DebugLoc dl = N->getDebugLoc();
373 SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
375 N->getMemoryVT(), N->isVolatile(),
376 N->isNonTemporal(), N->getAlignment());
378 // Legalized the chain result - switch anything that used the old chain to
380 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
384 /// Promote the overflow flag of an overflowing arithmetic node.
385 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
386 // Simply change the return type of the boolean result.
387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
388 EVT ValueVTs[] = { N->getValueType(0), NVT };
389 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
390 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
391 DAG.getVTList(ValueVTs, 2), Ops, 2);
393 // Modified the sum result - switch anything that used the old sum to use
395 ReplaceValueWith(SDValue(N, 0), Res);
397 return SDValue(Res.getNode(), 1);
400 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
402 return PromoteIntRes_Overflow(N);
404 // The operation overflowed iff the result in the larger type is not the
405 // sign extension of its truncation to the original type.
406 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
407 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
408 EVT OVT = N->getOperand(0).getValueType();
409 EVT NVT = LHS.getValueType();
410 DebugLoc dl = N->getDebugLoc();
412 // Do the arithmetic in the larger type.
413 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
414 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
416 // Calculate the overflow flag: sign extend the arithmetic result from
417 // the original type.
418 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
419 DAG.getValueType(OVT));
420 // Overflowed if and only if this is not equal to Res.
421 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
423 // Use the calculated overflow everywhere.
424 ReplaceValueWith(SDValue(N, 1), Ofl);
429 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
430 // Sign extend the input.
431 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
432 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
433 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
434 LHS.getValueType(), LHS, RHS);
437 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
438 SDValue LHS = GetPromotedInteger(N->getOperand(1));
439 SDValue RHS = GetPromotedInteger(N->getOperand(2));
440 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
441 LHS.getValueType(), N->getOperand(0),LHS,RHS);
444 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
445 SDValue LHS = GetPromotedInteger(N->getOperand(2));
446 SDValue RHS = GetPromotedInteger(N->getOperand(3));
447 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
448 LHS.getValueType(), N->getOperand(0),
449 N->getOperand(1), LHS, RHS, N->getOperand(4));
452 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
453 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
454 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
455 DebugLoc dl = N->getDebugLoc();
457 // Get the SETCC result using the canonical SETCC type.
458 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
459 N->getOperand(1), N->getOperand(2));
461 // Convert to the expected type.
462 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
463 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
464 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
468 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
469 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
470 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
473 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
474 SDValue Op = GetPromotedInteger(N->getOperand(0));
475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
476 Op.getValueType(), Op, N->getOperand(1));
479 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
480 // The input may have strange things in the top bits of the registers, but
481 // these operations don't care. They may have weird bits going out, but
482 // that too is okay if they are integer operations.
483 SDValue LHS = GetPromotedInteger(N->getOperand(0));
484 SDValue RHS = GetPromotedInteger(N->getOperand(1));
485 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
486 LHS.getValueType(), LHS, RHS);
489 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
490 // The input value must be properly sign extended.
491 SDValue Res = SExtPromotedInteger(N->getOperand(0));
492 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
493 Res.getValueType(), Res, N->getOperand(1));
496 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
497 // The input value must be properly zero extended.
498 EVT VT = N->getValueType(0);
499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
500 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
501 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
504 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
505 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
508 switch (getTypeAction(N->getOperand(0).getValueType())) {
509 default: llvm_unreachable("Unknown type action!");
512 Res = N->getOperand(0);
515 Res = GetPromotedInteger(N->getOperand(0));
519 // Truncate to NVT instead of VT
520 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
523 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
525 return PromoteIntRes_Overflow(N);
527 // The operation overflowed iff the result in the larger type is not the
528 // zero extension of its truncation to the original type.
529 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
530 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
531 EVT OVT = N->getOperand(0).getValueType();
532 EVT NVT = LHS.getValueType();
533 DebugLoc dl = N->getDebugLoc();
535 // Do the arithmetic in the larger type.
536 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
537 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
539 // Calculate the overflow flag: zero extend the arithmetic result from
540 // the original type.
541 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
542 // Overflowed if and only if this is not equal to Res.
543 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
545 // Use the calculated overflow everywhere.
546 ReplaceValueWith(SDValue(N, 1), Ofl);
551 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
552 // Zero extend the input.
553 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
554 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
555 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
556 LHS.getValueType(), LHS, RHS);
559 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
560 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
561 N->getValueType(0)));
564 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
565 SDValue Chain = N->getOperand(0); // Get the chain.
566 SDValue Ptr = N->getOperand(1); // Get the pointer.
567 EVT VT = N->getValueType(0);
568 DebugLoc dl = N->getDebugLoc();
570 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
571 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
572 // The argument is passed as NumRegs registers of type RegVT.
574 SmallVector<SDValue, 8> Parts(NumRegs);
575 for (unsigned i = 0; i < NumRegs; ++i) {
576 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
577 N->getConstantOperandVal(3));
578 Chain = Parts[i].getValue(1);
581 // Handle endianness of the load.
582 if (TLI.isBigEndian())
583 std::reverse(Parts.begin(), Parts.end());
585 // Assemble the parts in the promoted type.
586 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
587 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
588 for (unsigned i = 1; i < NumRegs; ++i) {
589 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
590 // Shift it to the right position and "or" it in.
591 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
592 DAG.getConstant(i * RegVT.getSizeInBits(),
593 TLI.getPointerTy()));
594 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
597 // Modified the chain result - switch anything that used the old chain to
599 ReplaceValueWith(SDValue(N, 1), Chain);
604 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
605 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
606 return PromoteIntRes_Overflow(N);
609 //===----------------------------------------------------------------------===//
610 // Integer Operand Promotion
611 //===----------------------------------------------------------------------===//
613 /// PromoteIntegerOperand - This method is called when the specified operand of
614 /// the specified node is found to need promotion. At this point, all of the
615 /// result types of the node are known to be legal, but other operands of the
616 /// node may need promotion or expansion as well as the specified one.
617 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
618 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
619 SDValue Res = SDValue();
621 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
624 switch (N->getOpcode()) {
627 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
628 N->dump(&DAG); dbgs() << "\n";
630 llvm_unreachable("Do not know how to promote this operator's operand!");
632 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
633 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
634 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
635 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
636 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
637 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
638 case ISD::CONVERT_RNDSAT:
639 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
640 case ISD::INSERT_VECTOR_ELT:
641 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
642 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
643 case ISD::SCALAR_TO_VECTOR:
644 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
645 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
646 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
647 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
648 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
649 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
650 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
652 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
653 case ISD::FP16_TO_FP32:
654 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
655 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
661 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
664 // If the result is null, the sub-method took care of registering results etc.
665 if (!Res.getNode()) return false;
667 // If the result is N, the sub-method updated N in place. Tell the legalizer
669 if (Res.getNode() == N)
672 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
673 "Invalid operand expansion");
675 ReplaceValueWith(SDValue(N, 0), Res);
679 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
680 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
681 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
682 ISD::CondCode CCCode) {
683 // We have to insert explicit sign or zero extends. Note that we could
684 // insert sign extends for ALL conditions, but zero extend is cheaper on
685 // many machines (an AND instead of two shifts), so prefer it.
687 default: llvm_unreachable("Unknown integer comparison!");
694 // ALL of these operations will work if we either sign or zero extend
695 // the operands (including the unsigned comparisons!). Zero extend is
696 // usually a simpler/cheaper operation, so prefer it.
697 NewLHS = ZExtPromotedInteger(NewLHS);
698 NewRHS = ZExtPromotedInteger(NewRHS);
704 NewLHS = SExtPromotedInteger(NewLHS);
705 NewRHS = SExtPromotedInteger(NewRHS);
710 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
711 SDValue Op = GetPromotedInteger(N->getOperand(0));
712 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
715 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
716 // This should only occur in unusual situations like bitcasting to an
717 // x86_fp80, so just turn it into a store+load
718 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
721 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
722 assert(OpNo == 2 && "Don't know how to promote this operand!");
724 SDValue LHS = N->getOperand(2);
725 SDValue RHS = N->getOperand(3);
726 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
728 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
730 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
731 N->getOperand(1), LHS, RHS, N->getOperand(4)),
735 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
736 assert(OpNo == 1 && "only know how to promote condition");
738 // Promote all the way up to the canonical SetCC type.
739 EVT SVT = TLI.getSetCCResultType(MVT::Other);
740 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
742 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
743 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
744 N->getOperand(2)), 0);
747 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
748 // Since the result type is legal, the operands must promote to it.
749 EVT OVT = N->getOperand(0).getValueType();
750 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
751 SDValue Hi = GetPromotedInteger(N->getOperand(1));
752 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
753 DebugLoc dl = N->getDebugLoc();
755 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
756 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
757 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
760 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
761 // The vector type is legal but the element type is not. This implies
762 // that the vector is a power-of-two in length and that the element
763 // type does not have a strange size (eg: it is not i1).
764 EVT VecVT = N->getValueType(0);
765 unsigned NumElts = VecVT.getVectorNumElements();
766 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
768 // Promote the inserted value. The type does not need to match the
769 // vector element type. Check that any extra bits introduced will be
771 assert(N->getOperand(0).getValueType().getSizeInBits() >=
772 N->getValueType(0).getVectorElementType().getSizeInBits() &&
773 "Type of inserted value narrower than vector element type!");
775 SmallVector<SDValue, 16> NewOps;
776 for (unsigned i = 0; i < NumElts; ++i)
777 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
779 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
782 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
783 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
784 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
785 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
786 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
787 "can only promote integer arguments");
788 SDValue InOp = GetPromotedInteger(N->getOperand(0));
789 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
790 N->getOperand(1), N->getOperand(2),
791 N->getOperand(3), N->getOperand(4), CvtCode);
794 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
797 // Promote the inserted value. This is valid because the type does not
798 // have to match the vector element type.
800 // Check that any extra bits introduced will be truncated away.
801 assert(N->getOperand(1).getValueType().getSizeInBits() >=
802 N->getValueType(0).getVectorElementType().getSizeInBits() &&
803 "Type of inserted value narrower than vector element type!");
804 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
805 GetPromotedInteger(N->getOperand(1)),
810 assert(OpNo == 2 && "Different operand and result vector types?");
812 // Promote the index.
813 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
814 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
815 N->getOperand(1), Idx), 0);
818 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
820 DebugLoc dl = N->getDebugLoc();
821 NewOps[0] = N->getOperand(0);
822 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
823 SDValue Flag = GetPromotedInteger(N->getOperand(i));
824 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
826 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
829 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
830 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
831 // the operand in place.
832 return SDValue(DAG.UpdateNodeOperands(N,
833 GetPromotedInteger(N->getOperand(0))), 0);
836 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
837 assert(OpNo == 0 && "Only know how to promote condition");
839 // Promote all the way up to the canonical SetCC type.
840 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
841 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
843 return SDValue(DAG.UpdateNodeOperands(N, Cond,
844 N->getOperand(1), N->getOperand(2)), 0);
847 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
848 assert(OpNo == 0 && "Don't know how to promote this operand!");
850 SDValue LHS = N->getOperand(0);
851 SDValue RHS = N->getOperand(1);
852 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
854 // The CC (#4) and the possible return values (#2 and #3) have legal types.
855 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
856 N->getOperand(3), N->getOperand(4)), 0);
859 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
860 assert(OpNo == 0 && "Don't know how to promote this operand!");
862 SDValue LHS = N->getOperand(0);
863 SDValue RHS = N->getOperand(1);
864 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
866 // The CC (#2) is always legal.
867 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
870 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
871 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
872 ZExtPromotedInteger(N->getOperand(1))), 0);
875 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
876 SDValue Op = GetPromotedInteger(N->getOperand(0));
877 DebugLoc dl = N->getDebugLoc();
878 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
879 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
880 Op, DAG.getValueType(N->getOperand(0).getValueType()));
883 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
884 return SDValue(DAG.UpdateNodeOperands(N,
885 SExtPromotedInteger(N->getOperand(0))), 0);
888 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
889 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
890 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
891 unsigned Alignment = N->getAlignment();
892 bool isVolatile = N->isVolatile();
893 bool isNonTemporal = N->isNonTemporal();
894 DebugLoc dl = N->getDebugLoc();
896 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
898 // Truncate the value and store the result.
899 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
901 isVolatile, isNonTemporal, Alignment);
904 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
905 SDValue Op = GetPromotedInteger(N->getOperand(0));
906 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
909 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
910 return SDValue(DAG.UpdateNodeOperands(N,
911 ZExtPromotedInteger(N->getOperand(0))), 0);
914 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
915 DebugLoc dl = N->getDebugLoc();
916 SDValue Op = GetPromotedInteger(N->getOperand(0));
917 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
918 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
922 //===----------------------------------------------------------------------===//
923 // Integer Result Expansion
924 //===----------------------------------------------------------------------===//
926 /// ExpandIntegerResult - This method is called when the specified result of the
927 /// specified node is found to need expansion. At this point, the node may also
928 /// have invalid operands or may have other results that need promotion, we just
929 /// know that (at least) one result needs expansion.
930 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
931 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
935 // See if the target wants to custom expand this node.
936 if (CustomLowerNode(N, N->getValueType(ResNo), true))
939 switch (N->getOpcode()) {
942 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
943 N->dump(&DAG); dbgs() << "\n";
945 llvm_unreachable("Do not know how to expand the result of this operator!");
947 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
948 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
949 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
950 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
952 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
953 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
954 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
955 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
956 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
958 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
959 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
960 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
961 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
962 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
963 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
964 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
965 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
966 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
967 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
968 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
969 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
970 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
971 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
972 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
973 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
974 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
975 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
976 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
977 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
981 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
984 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
987 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
990 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
994 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
997 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
999 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1002 // If Lo/Hi is null, the sub-method took care of registering results etc.
1004 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1007 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1008 /// and the shift amount is a constant 'Amt'. Expand the operation.
1009 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1010 SDValue &Lo, SDValue &Hi) {
1011 DebugLoc dl = N->getDebugLoc();
1012 // Expand the incoming operand to be shifted, so that we have its parts
1014 GetExpandedInteger(N->getOperand(0), InL, InH);
1016 EVT NVT = InL.getValueType();
1017 unsigned VTBits = N->getValueType(0).getSizeInBits();
1018 unsigned NVTBits = NVT.getSizeInBits();
1019 EVT ShTy = N->getOperand(1).getValueType();
1021 if (N->getOpcode() == ISD::SHL) {
1023 Lo = Hi = DAG.getConstant(0, NVT);
1024 } else if (Amt > NVTBits) {
1025 Lo = DAG.getConstant(0, NVT);
1026 Hi = DAG.getNode(ISD::SHL, dl,
1027 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1028 } else if (Amt == NVTBits) {
1029 Lo = DAG.getConstant(0, NVT);
1031 } else if (Amt == 1 &&
1032 TLI.isOperationLegalOrCustom(ISD::ADDC,
1033 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1034 // Emit this X << 1 as X+X.
1035 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1036 SDValue LoOps[2] = { InL, InL };
1037 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1038 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1039 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1041 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1042 Hi = DAG.getNode(ISD::OR, dl, NVT,
1043 DAG.getNode(ISD::SHL, dl, NVT, InH,
1044 DAG.getConstant(Amt, ShTy)),
1045 DAG.getNode(ISD::SRL, dl, NVT, InL,
1046 DAG.getConstant(NVTBits-Amt, ShTy)));
1051 if (N->getOpcode() == ISD::SRL) {
1053 Lo = DAG.getConstant(0, NVT);
1054 Hi = DAG.getConstant(0, NVT);
1055 } else if (Amt > NVTBits) {
1056 Lo = DAG.getNode(ISD::SRL, dl,
1057 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1058 Hi = DAG.getConstant(0, NVT);
1059 } else if (Amt == NVTBits) {
1061 Hi = DAG.getConstant(0, NVT);
1063 Lo = DAG.getNode(ISD::OR, dl, NVT,
1064 DAG.getNode(ISD::SRL, dl, NVT, InL,
1065 DAG.getConstant(Amt, ShTy)),
1066 DAG.getNode(ISD::SHL, dl, NVT, InH,
1067 DAG.getConstant(NVTBits-Amt, ShTy)));
1068 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1073 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1075 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1076 DAG.getConstant(NVTBits-1, ShTy));
1077 } else if (Amt > NVTBits) {
1078 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1079 DAG.getConstant(Amt-NVTBits, ShTy));
1080 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1081 DAG.getConstant(NVTBits-1, ShTy));
1082 } else if (Amt == NVTBits) {
1084 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1085 DAG.getConstant(NVTBits-1, ShTy));
1087 Lo = DAG.getNode(ISD::OR, dl, NVT,
1088 DAG.getNode(ISD::SRL, dl, NVT, InL,
1089 DAG.getConstant(Amt, ShTy)),
1090 DAG.getNode(ISD::SHL, dl, NVT, InH,
1091 DAG.getConstant(NVTBits-Amt, ShTy)));
1092 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1096 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1097 /// this shift based on knowledge of the high bit of the shift amount. If we
1098 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1100 bool DAGTypeLegalizer::
1101 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1102 SDValue Amt = N->getOperand(1);
1103 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1104 EVT ShTy = Amt.getValueType();
1105 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1106 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1107 assert(isPowerOf2_32(NVTBits) &&
1108 "Expanded integer type size not a power of two!");
1109 DebugLoc dl = N->getDebugLoc();
1111 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1112 APInt KnownZero, KnownOne;
1113 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1115 // If we don't know anything about the high bits, exit.
1116 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1119 // Get the incoming operand to be shifted.
1121 GetExpandedInteger(N->getOperand(0), InL, InH);
1123 // If we know that any of the high bits of the shift amount are one, then we
1124 // can do this as a couple of simple shifts.
1125 if (KnownOne.intersects(HighBitMask)) {
1126 // Mask out the high bit, which we know is set.
1127 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1128 DAG.getConstant(~HighBitMask, ShTy));
1130 switch (N->getOpcode()) {
1131 default: llvm_unreachable("Unknown shift");
1133 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1134 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1137 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1138 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1141 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1142 DAG.getConstant(NVTBits-1, ShTy));
1143 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1149 // FIXME: This code is broken for shifts with a zero amount!
1150 // If we know that all of the high bits of the shift amount are zero, then we
1151 // can do this as a couple of simple shifts.
1152 if ((KnownZero & HighBitMask) == HighBitMask) {
1154 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1155 DAG.getConstant(NVTBits, ShTy),
1158 switch (N->getOpcode()) {
1159 default: llvm_unreachable("Unknown shift");
1160 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1162 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1165 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1166 Hi = DAG.getNode(ISD::OR, NVT,
1167 DAG.getNode(Op1, NVT, InH, Amt),
1168 DAG.getNode(Op2, NVT, InL, Amt2));
1176 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1178 bool DAGTypeLegalizer::
1179 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1180 SDValue Amt = N->getOperand(1);
1181 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1182 EVT ShTy = Amt.getValueType();
1183 unsigned NVTBits = NVT.getSizeInBits();
1184 assert(isPowerOf2_32(NVTBits) &&
1185 "Expanded integer type size not a power of two!");
1186 DebugLoc dl = N->getDebugLoc();
1188 // Get the incoming operand to be shifted.
1190 GetExpandedInteger(N->getOperand(0), InL, InH);
1192 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1193 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1194 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1195 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1196 Amt, NVBitsNode, ISD::SETULT);
1198 SDValue LoS, HiS, LoL, HiL;
1199 switch (N->getOpcode()) {
1200 default: llvm_unreachable("Unknown shift");
1202 // Short: ShAmt < NVTBits
1203 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1204 HiS = DAG.getNode(ISD::OR, dl, NVT,
1205 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1206 // FIXME: If Amt is zero, the following shift generates an undefined result
1207 // on some architectures.
1208 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1210 // Long: ShAmt >= NVTBits
1211 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1212 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1214 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1215 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1218 // Short: ShAmt < NVTBits
1219 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1220 LoS = DAG.getNode(ISD::OR, dl, NVT,
1221 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1222 // FIXME: If Amt is zero, the following shift generates an undefined result
1223 // on some architectures.
1224 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1226 // Long: ShAmt >= NVTBits
1227 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1228 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1230 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1231 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1234 // Short: ShAmt < NVTBits
1235 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1236 LoS = DAG.getNode(ISD::OR, dl, NVT,
1237 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1238 // FIXME: If Amt is zero, the following shift generates an undefined result
1239 // on some architectures.
1240 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1242 // Long: ShAmt >= NVTBits
1243 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1244 DAG.getConstant(NVTBits-1, ShTy));
1245 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1247 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1248 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1255 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1256 SDValue &Lo, SDValue &Hi) {
1257 DebugLoc dl = N->getDebugLoc();
1258 // Expand the subcomponents.
1259 SDValue LHSL, LHSH, RHSL, RHSH;
1260 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1261 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1263 EVT NVT = LHSL.getValueType();
1264 SDValue LoOps[2] = { LHSL, RHSL };
1265 SDValue HiOps[3] = { LHSH, RHSH };
1267 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1268 // them. TODO: Teach operation legalization how to expand unsupported
1269 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1270 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1271 // generate a value of this type in the expanded code sequence.
1273 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1274 ISD::ADDC : ISD::SUBC,
1275 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1278 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1279 if (N->getOpcode() == ISD::ADD) {
1280 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1281 HiOps[2] = Lo.getValue(1);
1282 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1284 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1285 HiOps[2] = Lo.getValue(1);
1286 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1289 if (N->getOpcode() == ISD::ADD) {
1290 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1291 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1292 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1294 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1295 DAG.getConstant(1, NVT),
1296 DAG.getConstant(0, NVT));
1297 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1299 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1300 DAG.getConstant(1, NVT), Carry1);
1301 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1303 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1304 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1306 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1307 LoOps[0], LoOps[1], ISD::SETULT);
1308 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1309 DAG.getConstant(1, NVT),
1310 DAG.getConstant(0, NVT));
1311 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1316 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1317 SDValue &Lo, SDValue &Hi) {
1318 // Expand the subcomponents.
1319 SDValue LHSL, LHSH, RHSL, RHSH;
1320 DebugLoc dl = N->getDebugLoc();
1321 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1322 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1323 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1324 SDValue LoOps[2] = { LHSL, RHSL };
1325 SDValue HiOps[3] = { LHSH, RHSH };
1327 if (N->getOpcode() == ISD::ADDC) {
1328 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1329 HiOps[2] = Lo.getValue(1);
1330 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1332 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1333 HiOps[2] = Lo.getValue(1);
1334 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1337 // Legalized the flag result - switch anything that used the old flag to
1339 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1342 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1343 SDValue &Lo, SDValue &Hi) {
1344 // Expand the subcomponents.
1345 SDValue LHSL, LHSH, RHSL, RHSH;
1346 DebugLoc dl = N->getDebugLoc();
1347 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1348 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1349 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1350 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1351 SDValue HiOps[3] = { LHSH, RHSH };
1353 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1354 HiOps[2] = Lo.getValue(1);
1355 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1357 // Legalized the flag result - switch anything that used the old flag to
1359 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1362 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1363 SDValue &Lo, SDValue &Hi) {
1364 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1365 DebugLoc dl = N->getDebugLoc();
1366 SDValue Op = N->getOperand(0);
1367 if (Op.getValueType().bitsLE(NVT)) {
1368 // The low part is any extension of the input (which degenerates to a copy).
1369 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1370 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1372 // For example, extension of an i48 to an i64. The operand type necessarily
1373 // promotes to the result type, so will end up being expanded too.
1374 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1375 "Only know how to promote this result!");
1376 SDValue Res = GetPromotedInteger(Op);
1377 assert(Res.getValueType() == N->getValueType(0) &&
1378 "Operand over promoted?");
1379 // Split the promoted operand. This will simplify when it is expanded.
1380 SplitInteger(Res, Lo, Hi);
1384 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1385 SDValue &Lo, SDValue &Hi) {
1386 DebugLoc dl = N->getDebugLoc();
1387 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1388 EVT NVT = Lo.getValueType();
1389 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1390 unsigned NVTBits = NVT.getSizeInBits();
1391 unsigned EVTBits = EVT.getSizeInBits();
1393 if (NVTBits < EVTBits) {
1394 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1395 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1396 EVTBits - NVTBits)));
1398 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1399 // The high part replicates the sign bit of Lo, make it explicit.
1400 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1401 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1405 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1406 SDValue &Lo, SDValue &Hi) {
1407 DebugLoc dl = N->getDebugLoc();
1408 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1409 EVT NVT = Lo.getValueType();
1410 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1411 unsigned NVTBits = NVT.getSizeInBits();
1412 unsigned EVTBits = EVT.getSizeInBits();
1414 if (NVTBits < EVTBits) {
1415 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1416 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1417 EVTBits - NVTBits)));
1419 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1420 // The high part must be zero, make it explicit.
1421 Hi = DAG.getConstant(0, NVT);
1425 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1426 SDValue &Lo, SDValue &Hi) {
1427 DebugLoc dl = N->getDebugLoc();
1428 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1429 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1430 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1433 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1434 SDValue &Lo, SDValue &Hi) {
1435 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1436 unsigned NBitWidth = NVT.getSizeInBits();
1437 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1438 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1439 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1442 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1443 SDValue &Lo, SDValue &Hi) {
1444 DebugLoc dl = N->getDebugLoc();
1445 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1446 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1447 EVT NVT = Lo.getValueType();
1449 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1450 DAG.getConstant(0, NVT), ISD::SETNE);
1452 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1453 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1455 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1456 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1457 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1458 Hi = DAG.getConstant(0, NVT);
1461 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1462 SDValue &Lo, SDValue &Hi) {
1463 DebugLoc dl = N->getDebugLoc();
1464 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1465 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1466 EVT NVT = Lo.getValueType();
1467 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1468 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1469 Hi = DAG.getConstant(0, NVT);
1472 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1473 SDValue &Lo, SDValue &Hi) {
1474 DebugLoc dl = N->getDebugLoc();
1475 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1476 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1477 EVT NVT = Lo.getValueType();
1479 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1480 DAG.getConstant(0, NVT), ISD::SETNE);
1482 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1483 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1485 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1486 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1487 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1488 Hi = DAG.getConstant(0, NVT);
1491 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1493 DebugLoc dl = N->getDebugLoc();
1494 EVT VT = N->getValueType(0);
1495 SDValue Op = N->getOperand(0);
1496 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1497 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1498 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1501 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1503 DebugLoc dl = N->getDebugLoc();
1504 EVT VT = N->getValueType(0);
1505 SDValue Op = N->getOperand(0);
1506 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1507 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1508 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1511 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1512 SDValue &Lo, SDValue &Hi) {
1513 if (ISD::isNormalLoad(N)) {
1514 ExpandRes_NormalLoad(N, Lo, Hi);
1518 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1520 EVT VT = N->getValueType(0);
1521 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1522 SDValue Ch = N->getChain();
1523 SDValue Ptr = N->getBasePtr();
1524 ISD::LoadExtType ExtType = N->getExtensionType();
1525 unsigned Alignment = N->getAlignment();
1526 bool isVolatile = N->isVolatile();
1527 bool isNonTemporal = N->isNonTemporal();
1528 DebugLoc dl = N->getDebugLoc();
1530 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1532 if (N->getMemoryVT().bitsLE(NVT)) {
1533 EVT MemVT = N->getMemoryVT();
1535 Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1536 MemVT, isVolatile, isNonTemporal, Alignment);
1538 // Remember the chain.
1539 Ch = Lo.getValue(1);
1541 if (ExtType == ISD::SEXTLOAD) {
1542 // The high part is obtained by SRA'ing all but one of the bits of the
1544 unsigned LoSize = Lo.getValueType().getSizeInBits();
1545 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1546 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1547 } else if (ExtType == ISD::ZEXTLOAD) {
1548 // The high part is just a zero.
1549 Hi = DAG.getConstant(0, NVT);
1551 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1552 // The high part is undefined.
1553 Hi = DAG.getUNDEF(NVT);
1555 } else if (TLI.isLittleEndian()) {
1556 // Little-endian - low bits are at low addresses.
1557 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1558 isVolatile, isNonTemporal, Alignment);
1560 unsigned ExcessBits =
1561 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1562 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1564 // Increment the pointer to the other half.
1565 unsigned IncrementSize = NVT.getSizeInBits()/8;
1566 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1567 DAG.getIntPtrConstant(IncrementSize));
1568 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr,
1569 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1570 isVolatile, isNonTemporal,
1571 MinAlign(Alignment, IncrementSize));
1573 // Build a factor node to remember that this load is independent of the
1575 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1578 // Big-endian - high bits are at low addresses. Favor aligned loads at
1579 // the cost of some bit-fiddling.
1580 EVT MemVT = N->getMemoryVT();
1581 unsigned EBytes = MemVT.getStoreSize();
1582 unsigned IncrementSize = NVT.getSizeInBits()/8;
1583 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1585 // Load both the high bits and maybe some of the low bits.
1586 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getPointerInfo(),
1587 EVT::getIntegerVT(*DAG.getContext(),
1588 MemVT.getSizeInBits() - ExcessBits),
1589 isVolatile, isNonTemporal, Alignment);
1591 // Increment the pointer to the other half.
1592 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1593 DAG.getIntPtrConstant(IncrementSize));
1594 // Load the rest of the low bits.
1595 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr,
1596 N->getPointerInfo().getWithOffset(IncrementSize),
1597 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1598 isVolatile, isNonTemporal,
1599 MinAlign(Alignment, IncrementSize));
1601 // Build a factor node to remember that this load is independent of the
1603 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1606 if (ExcessBits < NVT.getSizeInBits()) {
1607 // Transfer low bits from the bottom of Hi to the top of Lo.
1608 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1609 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1610 DAG.getConstant(ExcessBits,
1611 TLI.getPointerTy())));
1612 // Move high bits to the right position in Hi.
1613 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1615 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1616 TLI.getPointerTy()));
1620 // Legalized the chain result - switch anything that used the old chain to
1622 ReplaceValueWith(SDValue(N, 1), Ch);
1625 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1626 SDValue &Lo, SDValue &Hi) {
1627 DebugLoc dl = N->getDebugLoc();
1628 SDValue LL, LH, RL, RH;
1629 GetExpandedInteger(N->getOperand(0), LL, LH);
1630 GetExpandedInteger(N->getOperand(1), RL, RH);
1631 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1632 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1635 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1636 SDValue &Lo, SDValue &Hi) {
1637 EVT VT = N->getValueType(0);
1638 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1639 DebugLoc dl = N->getDebugLoc();
1641 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1642 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1643 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1644 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1645 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1646 SDValue LL, LH, RL, RH;
1647 GetExpandedInteger(N->getOperand(0), LL, LH);
1648 GetExpandedInteger(N->getOperand(1), RL, RH);
1649 unsigned OuterBitSize = VT.getSizeInBits();
1650 unsigned InnerBitSize = NVT.getSizeInBits();
1651 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1652 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1654 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1655 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1656 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1657 // The inputs are both zero-extended.
1659 // We can emit a umul_lohi.
1660 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1661 Hi = SDValue(Lo.getNode(), 1);
1665 // We can emit a mulhu+mul.
1666 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1667 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1671 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1672 // The input values are both sign-extended.
1674 // We can emit a smul_lohi.
1675 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1676 Hi = SDValue(Lo.getNode(), 1);
1680 // We can emit a mulhs+mul.
1681 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1682 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1687 // Lo,Hi = umul LHS, RHS.
1688 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1689 DAG.getVTList(NVT, NVT), LL, RL);
1691 Hi = UMulLOHI.getValue(1);
1692 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1693 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1694 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1695 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1699 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1700 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1701 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1702 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1703 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1704 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1709 // If nothing else, we can make a libcall.
1710 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1712 LC = RTLIB::MUL_I16;
1713 else if (VT == MVT::i32)
1714 LC = RTLIB::MUL_I32;
1715 else if (VT == MVT::i64)
1716 LC = RTLIB::MUL_I64;
1717 else if (VT == MVT::i128)
1718 LC = RTLIB::MUL_I128;
1719 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1721 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1722 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1725 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1726 SDValue &Lo, SDValue &Hi) {
1727 SDValue LHS = Node->getOperand(0);
1728 SDValue RHS = Node->getOperand(1);
1729 DebugLoc dl = Node->getDebugLoc();
1731 // Expand the result by simply replacing it with the equivalent
1732 // non-overflow-checking operation.
1733 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1734 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1736 SplitInteger(Sum, Lo, Hi);
1738 // Compute the overflow.
1740 // LHSSign -> LHS >= 0
1741 // RHSSign -> RHS >= 0
1742 // SumSign -> Sum >= 0
1745 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1747 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1749 EVT OType = Node->getValueType(1);
1750 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1752 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1753 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1754 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1755 Node->getOpcode() == ISD::SADDO ?
1756 ISD::SETEQ : ISD::SETNE);
1758 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1759 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1761 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1763 // Use the calculated overflow everywhere.
1764 ReplaceValueWith(SDValue(Node, 1), Cmp);
1767 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1768 SDValue &Lo, SDValue &Hi) {
1769 EVT VT = N->getValueType(0);
1770 DebugLoc dl = N->getDebugLoc();
1772 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1774 LC = RTLIB::SDIV_I16;
1775 else if (VT == MVT::i32)
1776 LC = RTLIB::SDIV_I32;
1777 else if (VT == MVT::i64)
1778 LC = RTLIB::SDIV_I64;
1779 else if (VT == MVT::i128)
1780 LC = RTLIB::SDIV_I128;
1781 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1783 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1784 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1787 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1788 SDValue &Lo, SDValue &Hi) {
1789 EVT VT = N->getValueType(0);
1790 DebugLoc dl = N->getDebugLoc();
1792 // If we can emit an efficient shift operation, do so now. Check to see if
1793 // the RHS is a constant.
1794 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1795 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1797 // If we can determine that the high bit of the shift is zero or one, even if
1798 // the low bits are variable, emit this shift in an optimized form.
1799 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1802 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1804 if (N->getOpcode() == ISD::SHL) {
1805 PartsOpc = ISD::SHL_PARTS;
1806 } else if (N->getOpcode() == ISD::SRL) {
1807 PartsOpc = ISD::SRL_PARTS;
1809 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1810 PartsOpc = ISD::SRA_PARTS;
1813 // Next check to see if the target supports this SHL_PARTS operation or if it
1814 // will custom expand it.
1815 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1816 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1817 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1818 Action == TargetLowering::Custom) {
1819 // Expand the subcomponents.
1821 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1823 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1824 EVT VT = LHSL.getValueType();
1825 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1826 Hi = Lo.getValue(1);
1830 // Otherwise, emit a libcall.
1831 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1833 if (N->getOpcode() == ISD::SHL) {
1834 isSigned = false; /*sign irrelevant*/
1836 LC = RTLIB::SHL_I16;
1837 else if (VT == MVT::i32)
1838 LC = RTLIB::SHL_I32;
1839 else if (VT == MVT::i64)
1840 LC = RTLIB::SHL_I64;
1841 else if (VT == MVT::i128)
1842 LC = RTLIB::SHL_I128;
1843 } else if (N->getOpcode() == ISD::SRL) {
1846 LC = RTLIB::SRL_I16;
1847 else if (VT == MVT::i32)
1848 LC = RTLIB::SRL_I32;
1849 else if (VT == MVT::i64)
1850 LC = RTLIB::SRL_I64;
1851 else if (VT == MVT::i128)
1852 LC = RTLIB::SRL_I128;
1854 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1857 LC = RTLIB::SRA_I16;
1858 else if (VT == MVT::i32)
1859 LC = RTLIB::SRA_I32;
1860 else if (VT == MVT::i64)
1861 LC = RTLIB::SRA_I64;
1862 else if (VT == MVT::i128)
1863 LC = RTLIB::SRA_I128;
1866 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1867 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1868 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1872 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1873 llvm_unreachable("Unsupported shift!");
1876 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1877 SDValue &Lo, SDValue &Hi) {
1878 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1879 DebugLoc dl = N->getDebugLoc();
1880 SDValue Op = N->getOperand(0);
1881 if (Op.getValueType().bitsLE(NVT)) {
1882 // The low part is sign extension of the input (degenerates to a copy).
1883 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1884 // The high part is obtained by SRA'ing all but one of the bits of low part.
1885 unsigned LoSize = NVT.getSizeInBits();
1886 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1887 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1889 // For example, extension of an i48 to an i64. The operand type necessarily
1890 // promotes to the result type, so will end up being expanded too.
1891 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1892 "Only know how to promote this result!");
1893 SDValue Res = GetPromotedInteger(Op);
1894 assert(Res.getValueType() == N->getValueType(0) &&
1895 "Operand over promoted?");
1896 // Split the promoted operand. This will simplify when it is expanded.
1897 SplitInteger(Res, Lo, Hi);
1898 unsigned ExcessBits =
1899 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1900 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1901 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1906 void DAGTypeLegalizer::
1907 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1908 DebugLoc dl = N->getDebugLoc();
1909 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1910 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1912 if (EVT.bitsLE(Lo.getValueType())) {
1913 // sext_inreg the low part if needed.
1914 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1917 // The high part gets the sign extension from the lo-part. This handles
1918 // things like sextinreg V:i64 from i8.
1919 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1920 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1921 TLI.getPointerTy()));
1923 // For example, extension of an i48 to an i64. Leave the low part alone,
1924 // sext_inreg the high part.
1925 unsigned ExcessBits =
1926 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1927 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1928 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1933 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1934 SDValue &Lo, SDValue &Hi) {
1935 EVT VT = N->getValueType(0);
1936 DebugLoc dl = N->getDebugLoc();
1938 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1940 LC = RTLIB::SREM_I16;
1941 else if (VT == MVT::i32)
1942 LC = RTLIB::SREM_I32;
1943 else if (VT == MVT::i64)
1944 LC = RTLIB::SREM_I64;
1945 else if (VT == MVT::i128)
1946 LC = RTLIB::SREM_I128;
1947 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1949 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1950 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1953 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1954 SDValue &Lo, SDValue &Hi) {
1955 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1956 DebugLoc dl = N->getDebugLoc();
1957 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1958 Hi = DAG.getNode(ISD::SRL, dl,
1959 N->getOperand(0).getValueType(), N->getOperand(0),
1960 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1961 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1964 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
1965 SDValue &Lo, SDValue &Hi) {
1966 SDValue LHS = N->getOperand(0);
1967 SDValue RHS = N->getOperand(1);
1968 DebugLoc dl = N->getDebugLoc();
1970 // Expand the result by simply replacing it with the equivalent
1971 // non-overflow-checking operation.
1972 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
1973 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1975 SplitInteger(Sum, Lo, Hi);
1977 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
1978 // overflows iff a - b > a.
1979 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
1980 N->getOpcode () == ISD::UADDO ?
1981 ISD::SETULT : ISD::SETUGT);
1983 // Use the calculated overflow everywhere.
1984 ReplaceValueWith(SDValue(N, 1), Ofl);
1987 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1988 SDValue &Lo, SDValue &Hi) {
1989 EVT VT = N->getValueType(0);
1990 DebugLoc dl = N->getDebugLoc();
1992 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1994 LC = RTLIB::UDIV_I16;
1995 else if (VT == MVT::i32)
1996 LC = RTLIB::UDIV_I32;
1997 else if (VT == MVT::i64)
1998 LC = RTLIB::UDIV_I64;
1999 else if (VT == MVT::i128)
2000 LC = RTLIB::UDIV_I128;
2001 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2003 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2004 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2007 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2008 SDValue &Lo, SDValue &Hi) {
2009 EVT VT = N->getValueType(0);
2010 DebugLoc dl = N->getDebugLoc();
2012 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2014 LC = RTLIB::UREM_I16;
2015 else if (VT == MVT::i32)
2016 LC = RTLIB::UREM_I32;
2017 else if (VT == MVT::i64)
2018 LC = RTLIB::UREM_I64;
2019 else if (VT == MVT::i128)
2020 LC = RTLIB::UREM_I128;
2021 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2023 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2024 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2027 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2028 SDValue &Lo, SDValue &Hi) {
2029 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2030 DebugLoc dl = N->getDebugLoc();
2031 SDValue Op = N->getOperand(0);
2032 if (Op.getValueType().bitsLE(NVT)) {
2033 // The low part is zero extension of the input (degenerates to a copy).
2034 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2035 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2037 // For example, extension of an i48 to an i64. The operand type necessarily
2038 // promotes to the result type, so will end up being expanded too.
2039 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2040 "Only know how to promote this result!");
2041 SDValue Res = GetPromotedInteger(Op);
2042 assert(Res.getValueType() == N->getValueType(0) &&
2043 "Operand over promoted?");
2044 // Split the promoted operand. This will simplify when it is expanded.
2045 SplitInteger(Res, Lo, Hi);
2046 unsigned ExcessBits =
2047 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2048 Hi = DAG.getZeroExtendInReg(Hi, dl,
2049 EVT::getIntegerVT(*DAG.getContext(),
2055 //===----------------------------------------------------------------------===//
2056 // Integer Operand Expansion
2057 //===----------------------------------------------------------------------===//
2059 /// ExpandIntegerOperand - This method is called when the specified operand of
2060 /// the specified node is found to need expansion. At this point, all of the
2061 /// result types of the node are known to be legal, but other operands of the
2062 /// node may need promotion or expansion as well as the specified one.
2063 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2064 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2065 SDValue Res = SDValue();
2067 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2070 switch (N->getOpcode()) {
2073 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2074 N->dump(&DAG); dbgs() << "\n";
2076 llvm_unreachable("Do not know how to expand this operator's operand!");
2078 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2079 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2080 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2081 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2082 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2083 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2084 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2085 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2086 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2087 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2088 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2089 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2095 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2096 case ISD::RETURNADDR:
2097 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2100 // If the result is null, the sub-method took care of registering results etc.
2101 if (!Res.getNode()) return false;
2103 // If the result is N, the sub-method updated N in place. Tell the legalizer
2105 if (Res.getNode() == N)
2108 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2109 "Invalid operand expansion");
2111 ReplaceValueWith(SDValue(N, 0), Res);
2115 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2116 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2117 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2119 ISD::CondCode &CCCode,
2121 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2122 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2123 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2125 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2126 if (RHSLo == RHSHi) {
2127 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2128 if (RHSCST->isAllOnesValue()) {
2129 // Equality comparison to -1.
2130 NewLHS = DAG.getNode(ISD::AND, dl,
2131 LHSLo.getValueType(), LHSLo, LHSHi);
2138 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2139 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2140 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2141 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2145 // If this is a comparison of the sign bit, just look at the top part.
2147 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2148 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2149 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2155 // FIXME: This generated code sucks.
2156 ISD::CondCode LowCC;
2158 default: llvm_unreachable("Unknown integer setcc!");
2160 case ISD::SETULT: LowCC = ISD::SETULT; break;
2162 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2164 case ISD::SETULE: LowCC = ISD::SETULE; break;
2166 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2169 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2170 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2171 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2173 // NOTE: on targets without efficient SELECT of bools, we can always use
2174 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2175 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2177 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2178 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2179 if (!Tmp1.getNode())
2180 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2181 LHSLo, RHSLo, LowCC);
2182 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2183 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2184 if (!Tmp2.getNode())
2185 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2186 TLI.getSetCCResultType(LHSHi.getValueType()),
2187 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2189 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2190 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2191 if ((Tmp1C && Tmp1C->isNullValue()) ||
2192 (Tmp2C && Tmp2C->isNullValue() &&
2193 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2194 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2195 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2196 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2197 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2198 // low part is known false, returns high part.
2199 // For LE / GE, if high part is known false, ignore the low part.
2200 // For LT / GT, if high part is known true, ignore the low part.
2206 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2207 LHSHi, RHSHi, ISD::SETEQ, false,
2208 DagCombineInfo, dl);
2209 if (!NewLHS.getNode())
2210 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2211 LHSHi, RHSHi, ISD::SETEQ);
2212 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2213 NewLHS, Tmp1, Tmp2);
2217 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2218 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2219 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2220 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2222 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2223 // against zero to select between true and false values.
2224 if (NewRHS.getNode() == 0) {
2225 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2226 CCCode = ISD::SETNE;
2229 // Update N to have the operands specified.
2230 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2231 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2232 N->getOperand(4)), 0);
2235 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2236 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2237 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2238 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2240 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2241 // against zero to select between true and false values.
2242 if (NewRHS.getNode() == 0) {
2243 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2244 CCCode = ISD::SETNE;
2247 // Update N to have the operands specified.
2248 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2249 N->getOperand(2), N->getOperand(3),
2250 DAG.getCondCode(CCCode)), 0);
2253 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2254 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2255 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2256 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2258 // If ExpandSetCCOperands returned a scalar, use it.
2259 if (NewRHS.getNode() == 0) {
2260 assert(NewLHS.getValueType() == N->getValueType(0) &&
2261 "Unexpected setcc expansion!");
2265 // Otherwise, update N to have the operands specified.
2266 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2267 DAG.getCondCode(CCCode)), 0);
2270 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2271 // The value being shifted is legal, but the shift amount is too big.
2272 // It follows that either the result of the shift is undefined, or the
2273 // upper half of the shift amount is zero. Just use the lower half.
2275 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2276 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2279 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2280 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2281 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2282 // constant to valid type.
2284 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2285 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2288 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2289 SDValue Op = N->getOperand(0);
2290 EVT DstVT = N->getValueType(0);
2291 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2292 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2293 "Don't know how to expand this SINT_TO_FP!");
2294 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2297 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2298 if (ISD::isNormalStore(N))
2299 return ExpandOp_NormalStore(N, OpNo);
2301 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2302 assert(OpNo == 1 && "Can only expand the stored value so far");
2304 EVT VT = N->getOperand(1).getValueType();
2305 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2306 SDValue Ch = N->getChain();
2307 SDValue Ptr = N->getBasePtr();
2308 unsigned Alignment = N->getAlignment();
2309 bool isVolatile = N->isVolatile();
2310 bool isNonTemporal = N->isNonTemporal();
2311 DebugLoc dl = N->getDebugLoc();
2314 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2316 if (N->getMemoryVT().bitsLE(NVT)) {
2317 GetExpandedInteger(N->getValue(), Lo, Hi);
2318 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2319 N->getMemoryVT(), isVolatile, isNonTemporal,
2323 if (TLI.isLittleEndian()) {
2324 // Little-endian - low bits are at low addresses.
2325 GetExpandedInteger(N->getValue(), Lo, Hi);
2327 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2328 isVolatile, isNonTemporal, Alignment);
2330 unsigned ExcessBits =
2331 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2332 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2334 // Increment the pointer to the other half.
2335 unsigned IncrementSize = NVT.getSizeInBits()/8;
2336 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2337 DAG.getIntPtrConstant(IncrementSize));
2338 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2339 N->getPointerInfo().getWithOffset(IncrementSize),
2340 NEVT, isVolatile, isNonTemporal,
2341 MinAlign(Alignment, IncrementSize));
2342 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2345 // Big-endian - high bits are at low addresses. Favor aligned stores at
2346 // the cost of some bit-fiddling.
2347 GetExpandedInteger(N->getValue(), Lo, Hi);
2349 EVT ExtVT = N->getMemoryVT();
2350 unsigned EBytes = ExtVT.getStoreSize();
2351 unsigned IncrementSize = NVT.getSizeInBits()/8;
2352 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2353 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2354 ExtVT.getSizeInBits() - ExcessBits);
2356 if (ExcessBits < NVT.getSizeInBits()) {
2357 // Transfer high bits from the top of Lo to the bottom of Hi.
2358 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2359 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2360 TLI.getPointerTy()));
2361 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2362 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2363 DAG.getConstant(ExcessBits,
2364 TLI.getPointerTy())));
2367 // Store both the high bits and maybe some of the low bits.
2368 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2369 HiVT, isVolatile, isNonTemporal, Alignment);
2371 // Increment the pointer to the other half.
2372 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2373 DAG.getIntPtrConstant(IncrementSize));
2374 // Store the lowest ExcessBits bits in the second half.
2375 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2376 N->getPointerInfo().getWithOffset(IncrementSize),
2377 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2378 isVolatile, isNonTemporal,
2379 MinAlign(Alignment, IncrementSize));
2380 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2383 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2385 GetExpandedInteger(N->getOperand(0), InL, InH);
2386 // Just truncate the low part of the source.
2387 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2390 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2391 switch (VT.getSimpleVT().SimpleTy) {
2392 default: llvm_unreachable("Unknown FP format");
2393 case MVT::f32: return &APFloat::IEEEsingle;
2394 case MVT::f64: return &APFloat::IEEEdouble;
2395 case MVT::f80: return &APFloat::x87DoubleExtended;
2396 case MVT::f128: return &APFloat::IEEEquad;
2397 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2401 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2402 SDValue Op = N->getOperand(0);
2403 EVT SrcVT = Op.getValueType();
2404 EVT DstVT = N->getValueType(0);
2405 DebugLoc dl = N->getDebugLoc();
2407 // The following optimization is valid only if every value in SrcVT (when
2408 // treated as signed) is representable in DstVT. Check that the mantissa
2409 // size of DstVT is >= than the number of bits in SrcVT -1.
2410 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2411 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2412 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2413 // Do a signed conversion then adjust the result.
2414 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2415 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2417 // The result of the signed conversion needs adjusting if the 'sign bit' of
2418 // the incoming integer was set. To handle this, we dynamically test to see
2419 // if it is set, and, if so, add a fudge factor.
2421 const uint64_t F32TwoE32 = 0x4F800000ULL;
2422 const uint64_t F32TwoE64 = 0x5F800000ULL;
2423 const uint64_t F32TwoE128 = 0x7F800000ULL;
2426 if (SrcVT == MVT::i32)
2427 FF = APInt(32, F32TwoE32);
2428 else if (SrcVT == MVT::i64)
2429 FF = APInt(32, F32TwoE64);
2430 else if (SrcVT == MVT::i128)
2431 FF = APInt(32, F32TwoE128);
2433 assert(false && "Unsupported UINT_TO_FP!");
2435 // Check whether the sign bit is set.
2437 GetExpandedInteger(Op, Lo, Hi);
2438 SDValue SignSet = DAG.getSetCC(dl,
2439 TLI.getSetCCResultType(Hi.getValueType()),
2440 Hi, DAG.getConstant(0, Hi.getValueType()),
2443 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2444 SDValue FudgePtr = DAG.getConstantPool(
2445 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2446 TLI.getPointerTy());
2448 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2449 SDValue Zero = DAG.getIntPtrConstant(0);
2450 SDValue Four = DAG.getIntPtrConstant(4);
2451 if (TLI.isBigEndian()) std::swap(Zero, Four);
2452 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2454 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2455 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2456 Alignment = std::min(Alignment, 4u);
2458 // Load the value out, extending it from f32 to the destination float type.
2459 // FIXME: Avoid the extend by constructing the right constant pool?
2460 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
2462 MachinePointerInfo::getConstantPool(),
2464 false, false, Alignment);
2465 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2468 // Otherwise, use a libcall.
2469 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2470 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2471 "Don't know how to expand this UINT_TO_FP!");
2472 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);