1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (CustomLowerResults(N, ResNo))
40 switch (N->getOpcode()) {
43 cerr << "PromoteIntegerResult #" << ResNo << ": ";
44 N->dump(&DAG); cerr << "\n";
46 assert(0 && "Do not know how to promote this operator!");
48 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
49 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
50 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
51 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
52 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
53 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
54 case ISD::CONVERT_RNDSAT:
55 Result = PromoteIntRes_CONVERT_RNDSAT(N); break;
56 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
57 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
58 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
59 case ISD::EXTRACT_VECTOR_ELT:
60 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
61 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
62 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
63 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
64 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
65 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
66 case ISD::SIGN_EXTEND_INREG:
67 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
68 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
69 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
70 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
71 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
72 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
74 case ISD::SIGN_EXTEND:
75 case ISD::ZERO_EXTEND:
76 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
79 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
86 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
89 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
92 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
95 case ISD::UADDO: Result = PromoteIntRes_XADDO(N, ResNo); break;
97 case ISD::ATOMIC_LOAD_ADD_8:
98 case ISD::ATOMIC_LOAD_SUB_8:
99 case ISD::ATOMIC_LOAD_AND_8:
100 case ISD::ATOMIC_LOAD_OR_8:
101 case ISD::ATOMIC_LOAD_XOR_8:
102 case ISD::ATOMIC_LOAD_NAND_8:
103 case ISD::ATOMIC_LOAD_MIN_8:
104 case ISD::ATOMIC_LOAD_MAX_8:
105 case ISD::ATOMIC_LOAD_UMIN_8:
106 case ISD::ATOMIC_LOAD_UMAX_8:
107 case ISD::ATOMIC_SWAP_8:
108 case ISD::ATOMIC_LOAD_ADD_16:
109 case ISD::ATOMIC_LOAD_SUB_16:
110 case ISD::ATOMIC_LOAD_AND_16:
111 case ISD::ATOMIC_LOAD_OR_16:
112 case ISD::ATOMIC_LOAD_XOR_16:
113 case ISD::ATOMIC_LOAD_NAND_16:
114 case ISD::ATOMIC_LOAD_MIN_16:
115 case ISD::ATOMIC_LOAD_MAX_16:
116 case ISD::ATOMIC_LOAD_UMIN_16:
117 case ISD::ATOMIC_LOAD_UMAX_16:
118 case ISD::ATOMIC_SWAP_16:
119 case ISD::ATOMIC_LOAD_ADD_32:
120 case ISD::ATOMIC_LOAD_SUB_32:
121 case ISD::ATOMIC_LOAD_AND_32:
122 case ISD::ATOMIC_LOAD_OR_32:
123 case ISD::ATOMIC_LOAD_XOR_32:
124 case ISD::ATOMIC_LOAD_NAND_32:
125 case ISD::ATOMIC_LOAD_MIN_32:
126 case ISD::ATOMIC_LOAD_MAX_32:
127 case ISD::ATOMIC_LOAD_UMIN_32:
128 case ISD::ATOMIC_LOAD_UMAX_32:
129 case ISD::ATOMIC_SWAP_32:
130 case ISD::ATOMIC_LOAD_ADD_64:
131 case ISD::ATOMIC_LOAD_SUB_64:
132 case ISD::ATOMIC_LOAD_AND_64:
133 case ISD::ATOMIC_LOAD_OR_64:
134 case ISD::ATOMIC_LOAD_XOR_64:
135 case ISD::ATOMIC_LOAD_NAND_64:
136 case ISD::ATOMIC_LOAD_MIN_64:
137 case ISD::ATOMIC_LOAD_MAX_64:
138 case ISD::ATOMIC_LOAD_UMIN_64:
139 case ISD::ATOMIC_LOAD_UMAX_64:
140 case ISD::ATOMIC_SWAP_64:
141 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
143 case ISD::ATOMIC_CMP_SWAP_8:
144 case ISD::ATOMIC_CMP_SWAP_16:
145 case ISD::ATOMIC_CMP_SWAP_32:
146 case ISD::ATOMIC_CMP_SWAP_64:
147 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
150 // If Result is null, the sub-method took care of registering the result.
151 if (Result.getNode())
152 SetPromotedInteger(SDValue(N, ResNo), Result);
155 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
156 // Sign-extend the new bits, and continue the assertion.
157 SDValue Op = SExtPromotedInteger(N->getOperand(0));
158 return DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, N->getOperand(1));
161 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
162 // Zero the new bits, and continue the assertion.
163 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
164 return DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
168 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
170 Op2, N->getSrcValue(), N->getAlignment());
171 // Legalized the chain result - switch anything that used the old chain to
173 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
177 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
178 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
179 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
180 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
181 Op2, Op3, N->getSrcValue(), N->getAlignment());
182 // Legalized the chain result - switch anything that used the old chain to
184 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
188 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
189 SDValue InOp = N->getOperand(0);
190 MVT InVT = InOp.getValueType();
191 MVT NInVT = TLI.getTypeToTransformTo(InVT);
192 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
194 switch (getTypeAction(InVT)) {
196 assert(false && "Unknown type action!");
201 if (OutVT.bitsEq(NInVT))
202 // The input promotes to the same size. Convert the promoted value.
203 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
206 // Promote the integer operand by hand.
207 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
211 case ScalarizeVector:
212 // Convert the element to an integer and promote it by hand.
213 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
214 BitConvertToInteger(GetScalarizedVector(InOp)));
216 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
217 // pieces of the input into integers and reassemble in the final type.
219 GetSplitVector(N->getOperand(0), Lo, Hi);
220 Lo = BitConvertToInteger(Lo);
221 Hi = BitConvertToInteger(Hi);
223 if (TLI.isBigEndian())
226 InOp = DAG.getNode(ISD::ANY_EXTEND,
227 MVT::getIntegerVT(OutVT.getSizeInBits()),
228 JoinIntegers(Lo, Hi));
229 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
232 // Otherwise, lower the bit-convert to a store/load from the stack, then
234 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
235 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
238 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
239 SDValue Op = GetPromotedInteger(N->getOperand(0));
240 MVT OVT = N->getValueType(0);
241 MVT NVT = Op.getValueType();
243 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
244 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
245 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
248 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
249 // The pair element type may be legal, or may not promote to the same type as
250 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
251 return DAG.getNode(ISD::ANY_EXTEND,
252 TLI.getTypeToTransformTo(N->getValueType(0)),
253 JoinIntegers(N->getOperand(0), N->getOperand(1)));
256 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
257 MVT VT = N->getValueType(0);
258 // Zero extend things like i1, sign extend everything else. It shouldn't
259 // matter in theory which one we pick, but this tends to give better code?
260 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
261 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
263 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
267 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
268 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
269 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
270 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
271 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
272 "can only promote integers");
273 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
274 return DAG.getConvertRndSat(OutVT, N->getOperand(0),
275 N->getOperand(1), N->getOperand(2),
276 N->getOperand(3), N->getOperand(4), CvtCode);
279 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
280 // Zero extend to the promoted type and do the count there.
281 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
282 MVT OVT = N->getValueType(0);
283 MVT NVT = Op.getValueType();
284 Op = DAG.getNode(ISD::CTLZ, NVT, Op);
285 // Subtract off the extra leading bits in the bigger type.
286 return DAG.getNode(ISD::SUB, NVT, Op,
287 DAG.getConstant(NVT.getSizeInBits() -
288 OVT.getSizeInBits(), NVT));
291 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
292 // Zero extend to the promoted type and do the count there.
293 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
294 return DAG.getNode(ISD::CTPOP, Op.getValueType(), Op);
297 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
298 SDValue Op = GetPromotedInteger(N->getOperand(0));
299 MVT OVT = N->getValueType(0);
300 MVT NVT = Op.getValueType();
301 // The count is the same in the promoted type except if the original
302 // value was zero. This can be handled by setting the bit just off
303 // the top of the original type.
304 APInt TopBit(NVT.getSizeInBits(), 0);
305 TopBit.set(OVT.getSizeInBits());
306 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
307 return DAG.getNode(ISD::CTTZ, NVT, Op);
310 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
311 MVT OldVT = N->getValueType(0);
312 SDValue OldVec = N->getOperand(0);
313 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
316 assert(!isTypeLegal(OldVec.getValueType()) &&
317 "Legal one-element vector of a type needing promotion!");
318 // It is tempting to follow GetScalarizedVector by a call to
319 // GetPromotedInteger, but this would be wrong because the
320 // scalarized value may not yet have been processed.
321 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
322 GetScalarizedVector(OldVec));
325 // Convert to a vector half as long with an element type of twice the width,
326 // for example <4 x i16> -> <2 x i32>.
327 assert(!(OldElts & 1) && "Odd length vectors not supported!");
328 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
329 assert(OldVT.isSimple() && NewVT.isSimple());
331 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
332 MVT::getVectorVT(NewVT, OldElts / 2),
335 // Extract the element at OldIdx / 2 from the new vector.
336 SDValue OldIdx = N->getOperand(1);
337 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
338 DAG.getConstant(1, TLI.getShiftAmountTy()));
339 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
341 // Select the appropriate half of the element: Lo if OldIdx was even,
344 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
345 DAG.getConstant(OldVT.getSizeInBits(),
346 TLI.getShiftAmountTy()));
347 if (TLI.isBigEndian())
350 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
351 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
354 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 unsigned NewOpc = N->getOpcode();
358 // If we're promoting a UINT to a larger size, check to see if the new node
359 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
360 // we can use that instead. This allows us to generate better code for
361 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
362 // legal, such as PowerPC.
363 if (N->getOpcode() == ISD::FP_TO_UINT &&
364 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
365 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT))
366 NewOpc = ISD::FP_TO_SINT;
368 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
370 // Assert that the converted value fits in the original type. If it doesn't
371 // (eg: because the value being converted is too big), then the result of the
372 // original operation was undefined anyway, so the assert is still correct.
373 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
374 ISD::AssertZext : ISD::AssertSext,
375 NVT, Res, DAG.getValueType(N->getValueType(0)));
378 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
379 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
381 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
382 SDValue Res = GetPromotedInteger(N->getOperand(0));
383 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
385 // If the result and operand types are the same after promotion, simplify
386 // to an in-register extension.
387 if (NVT == Res.getValueType()) {
388 // The high bits are not guaranteed to be anything. Insert an extend.
389 if (N->getOpcode() == ISD::SIGN_EXTEND)
390 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
391 DAG.getValueType(N->getOperand(0).getValueType()));
392 if (N->getOpcode() == ISD::ZERO_EXTEND)
393 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
394 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
399 // Otherwise, just extend the original operand all the way to the larger type.
400 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
403 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
404 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
405 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
406 ISD::LoadExtType ExtType =
407 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
408 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
409 N->getSrcValue(), N->getSrcValueOffset(),
410 N->getMemoryVT(), N->isVolatile(),
413 // Legalized the chain result - switch anything that used the old chain to
415 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
419 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
420 // Sign extend the input.
421 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
422 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
423 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
426 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
427 SDValue LHS = GetPromotedInteger(N->getOperand(1));
428 SDValue RHS = GetPromotedInteger(N->getOperand(2));
429 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
432 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
433 SDValue LHS = GetPromotedInteger(N->getOperand(2));
434 SDValue RHS = GetPromotedInteger(N->getOperand(3));
435 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
436 N->getOperand(1), LHS, RHS, N->getOperand(4));
439 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
440 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
441 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
443 // Get the SETCC result using the canonical SETCC type.
444 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
445 N->getOperand(1), N->getOperand(2));
447 // Convert to the expected type.
448 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
449 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
450 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
453 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
454 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
455 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
458 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
459 SDValue Op = GetPromotedInteger(N->getOperand(0));
460 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
464 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
465 // The input may have strange things in the top bits of the registers, but
466 // these operations don't care. They may have weird bits going out, but
467 // that too is okay if they are integer operations.
468 SDValue LHS = GetPromotedInteger(N->getOperand(0));
469 SDValue RHS = GetPromotedInteger(N->getOperand(1));
470 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
473 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
474 // The input value must be properly sign extended.
475 SDValue Res = SExtPromotedInteger(N->getOperand(0));
476 return DAG.getNode(ISD::SRA, Res.getValueType(), Res, N->getOperand(1));
479 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
480 // The input value must be properly zero extended.
481 MVT VT = N->getValueType(0);
482 MVT NVT = TLI.getTypeToTransformTo(VT);
483 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
484 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
487 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
488 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
491 switch (getTypeAction(N->getOperand(0).getValueType())) {
492 default: assert(0 && "Unknown type action!");
495 Res = N->getOperand(0);
498 Res = GetPromotedInteger(N->getOperand(0));
502 // Truncate to NVT instead of VT
503 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
506 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
507 // Zero extend the input.
508 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
509 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
510 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
513 SDValue DAGTypeLegalizer::PromoteIntRes_XADDO(SDNode *N, unsigned ResNo) {
514 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
516 // Simply change the return type of the boolean result.
517 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
518 MVT ValueVTs[] = { N->getValueType(0), NVT };
519 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
520 SDValue Res = DAG.getNode(N->getOpcode(), DAG.getVTList(ValueVTs, 2), Ops, 2);
522 // Modified the sum result - switch anything that used the old sum to use
524 ReplaceValueWith(SDValue(N, 0), Res);
526 return SDValue(Res.getNode(), 1);
529 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
530 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
533 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
534 SDValue Chain = N->getOperand(0); // Get the chain.
535 SDValue Ptr = N->getOperand(1); // Get the pointer.
536 MVT VT = N->getValueType(0);
538 MVT RegVT = TLI.getRegisterType(VT);
539 unsigned NumRegs = TLI.getNumRegisters(VT);
540 // The argument is passed as NumRegs registers of type RegVT.
542 SmallVector<SDValue, 8> Parts(NumRegs);
543 for (unsigned i = 0; i < NumRegs; ++i) {
544 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
545 Chain = Parts[i].getValue(1);
548 // Handle endianness of the load.
549 if (TLI.isBigEndian())
550 std::reverse(Parts.begin(), Parts.end());
552 // Assemble the parts in the promoted type.
553 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
554 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]);
555 for (unsigned i = 1; i < NumRegs; ++i) {
556 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]);
557 // Shift it to the right position and "or" it in.
558 Part = DAG.getNode(ISD::SHL, NVT, Part,
559 DAG.getConstant(i * RegVT.getSizeInBits(),
560 TLI.getShiftAmountTy()));
561 Res = DAG.getNode(ISD::OR, NVT, Res, Part);
564 // Modified the chain result - switch anything that used the old chain to
566 ReplaceValueWith(SDValue(N, 1), Chain);
572 //===----------------------------------------------------------------------===//
573 // Integer Operand Promotion
574 //===----------------------------------------------------------------------===//
576 /// PromoteIntegerOperand - This method is called when the specified operand of
577 /// the specified node is found to need promotion. At this point, all of the
578 /// result types of the node are known to be legal, but other operands of the
579 /// node may need promotion or expansion as well as the specified one.
580 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
581 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
582 SDValue Res = SDValue();
584 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
585 == TargetLowering::Custom)
586 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
588 if (Res.getNode() == 0) {
589 switch (N->getOpcode()) {
592 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
593 N->dump(&DAG); cerr << "\n";
595 assert(0 && "Do not know how to promote this operator's operand!");
598 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
599 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
600 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
601 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
602 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
603 case ISD::CONVERT_RNDSAT:
604 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
605 case ISD::INSERT_VECTOR_ELT:
606 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
607 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
608 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
609 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
610 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
611 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
612 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
613 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
615 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
616 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
617 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
621 // If the result is null, the sub-method took care of registering results etc.
622 if (!Res.getNode()) return false;
623 // If the result is N, the sub-method updated N in place.
624 if (Res.getNode() == N) {
625 // Mark N as new and remark N and its operands. This allows us to correctly
626 // revisit N if it needs another step of promotion and allows us to visit
627 // any new operands to N.
632 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
633 "Invalid operand expansion");
635 ReplaceValueWith(SDValue(N, 0), Res);
639 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
640 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
641 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
642 ISD::CondCode CCCode) {
643 // We have to insert explicit sign or zero extends. Note that we could
644 // insert sign extends for ALL conditions, but zero extend is cheaper on
645 // many machines (an AND instead of two shifts), so prefer it.
647 default: assert(0 && "Unknown integer comparison!");
654 // ALL of these operations will work if we either sign or zero extend
655 // the operands (including the unsigned comparisons!). Zero extend is
656 // usually a simpler/cheaper operation, so prefer it.
657 NewLHS = ZExtPromotedInteger(NewLHS);
658 NewRHS = ZExtPromotedInteger(NewRHS);
664 NewLHS = SExtPromotedInteger(NewLHS);
665 NewRHS = SExtPromotedInteger(NewRHS);
670 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
671 SDValue Op = GetPromotedInteger(N->getOperand(0));
672 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
675 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
676 assert(OpNo == 2 && "Don't know how to promote this operand!");
678 SDValue LHS = N->getOperand(2);
679 SDValue RHS = N->getOperand(3);
680 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
682 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
684 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
685 N->getOperand(1), LHS, RHS, N->getOperand(4));
688 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
689 assert(OpNo == 1 && "only know how to promote condition");
690 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
692 // Make sure the extra bits coming from type promotion conform to
693 // getBooleanContents.
694 unsigned CondBits = Cond.getValueSizeInBits();
695 switch (TLI.getBooleanContents()) {
697 assert(false && "Unknown BooleanContent!");
698 case TargetLowering::UndefinedBooleanContent:
699 // The promoted value, which may contain rubbish in the upper bits, is fine.
701 case TargetLowering::ZeroOrOneBooleanContent:
702 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
703 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
705 case TargetLowering::ZeroOrNegativeOneBooleanContent:
706 if (DAG.ComputeNumSignBits(Cond) != CondBits)
707 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
708 DAG.getValueType(MVT::i1));
712 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
713 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
717 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
718 // Since the result type is legal, the operands must promote to it.
719 MVT OVT = N->getOperand(0).getValueType();
720 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
721 SDValue Hi = GetPromotedInteger(N->getOperand(1));
722 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
724 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
725 DAG.getConstant(OVT.getSizeInBits(),
726 TLI.getShiftAmountTy()));
727 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
730 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
731 // The vector type is legal but the element type is not. This implies
732 // that the vector is a power-of-two in length and that the element
733 // type does not have a strange size (eg: it is not i1).
734 MVT VecVT = N->getValueType(0);
735 unsigned NumElts = VecVT.getVectorNumElements();
736 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
738 // Build a vector of half the length out of elements of twice the bitwidth.
739 // For example <4 x i16> -> <2 x i32>.
740 MVT OldVT = N->getOperand(0).getValueType();
741 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
742 assert(OldVT.isSimple() && NewVT.isSimple());
744 std::vector<SDValue> NewElts;
745 NewElts.reserve(NumElts/2);
747 for (unsigned i = 0; i < NumElts; i += 2) {
748 // Combine two successive elements into one promoted element.
749 SDValue Lo = N->getOperand(i);
750 SDValue Hi = N->getOperand(i+1);
751 if (TLI.isBigEndian())
753 NewElts.push_back(JoinIntegers(Lo, Hi));
756 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
757 MVT::getVectorVT(NewVT, NewElts.size()),
758 &NewElts[0], NewElts.size());
760 // Convert the new vector to the old vector type.
761 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
764 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
765 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
766 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
767 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
768 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
769 "can only promote integer arguments");
770 SDValue InOp = GetPromotedInteger(N->getOperand(0));
771 return DAG.getConvertRndSat(N->getValueType(0), InOp,
772 N->getOperand(1), N->getOperand(2),
773 N->getOperand(3), N->getOperand(4), CvtCode);
776 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
779 // Promote the inserted value. This is valid because the type does not
780 // have to match the vector element type.
782 // Check that any extra bits introduced will be truncated away.
783 assert(N->getOperand(1).getValueType().getSizeInBits() >=
784 N->getValueType(0).getVectorElementType().getSizeInBits() &&
785 "Type of inserted value narrower than vector element type!");
786 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
787 GetPromotedInteger(N->getOperand(1)),
791 assert(OpNo == 2 && "Different operand and result vector types?");
793 // Promote the index.
794 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
795 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
796 N->getOperand(1), Idx);
799 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
801 NewOps[0] = N->getOperand(0);
802 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
803 SDValue Flag = GetPromotedInteger(N->getOperand(i));
804 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
806 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
807 array_lengthof(NewOps));
810 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
811 assert(OpNo == 0 && "Only know how to promote condition");
812 SDValue Cond = GetPromotedInteger(N->getOperand(0));
814 // Promote all the way up to SVT, the canonical SetCC type.
815 // FIXME: Not clear what value to pass to getSetCCResultType.
816 // [This only matters for CellSPU since all other targets
817 // ignore the argument.] We used to pass Cond, resulting in
818 // SVT = MVT::i8, but CellSPU has no select patterns for i8,
819 // causing an abort later. Passing the result type works
820 // around the problem.
821 MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
822 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
823 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
825 // Make sure the extra bits conform to getBooleanContents. There are
826 // two sets of extra bits: those in Cond, which come from type promotion,
827 // and those we need to add to have the final type be SVT (for most targets
828 // this last set of bits is empty).
829 unsigned CondBits = Cond.getValueSizeInBits();
830 ISD::NodeType ExtendCode;
831 switch (TLI.getBooleanContents()) {
833 assert(false && "Unknown BooleanContent!");
834 case TargetLowering::UndefinedBooleanContent:
835 // Extend to SVT by adding rubbish.
836 ExtendCode = ISD::ANY_EXTEND;
838 case TargetLowering::ZeroOrOneBooleanContent:
839 ExtendCode = ISD::ZERO_EXTEND;
840 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
841 // All extra bits need to be cleared. Do this by zero extending the
842 // original condition value all the way to SVT.
843 Cond = N->getOperand(0);
845 case TargetLowering::ZeroOrNegativeOneBooleanContent: {
846 ExtendCode = ISD::SIGN_EXTEND;
847 unsigned SignBits = DAG.ComputeNumSignBits(Cond);
848 if (SignBits != CondBits)
849 // All extra bits need to be sign extended. Do this by sign extending the
850 // original condition value all the way to SVT.
851 Cond = N->getOperand(0);
855 Cond = DAG.getNode(ExtendCode, SVT, Cond);
857 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
858 N->getOperand(1), N->getOperand(2));
861 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
862 assert(OpNo == 0 && "Don't know how to promote this operand!");
864 SDValue LHS = N->getOperand(0);
865 SDValue RHS = N->getOperand(1);
866 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
868 // The CC (#4) and the possible return values (#2 and #3) have legal types.
869 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
870 N->getOperand(3), N->getOperand(4));
873 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
874 assert(OpNo == 0 && "Don't know how to promote this operand!");
876 SDValue LHS = N->getOperand(0);
877 SDValue RHS = N->getOperand(1);
878 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
880 // The CC (#2) is always legal.
881 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
884 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
885 SDValue Op = GetPromotedInteger(N->getOperand(0));
886 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
887 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
888 Op, DAG.getValueType(N->getOperand(0).getValueType()));
891 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
892 return DAG.UpdateNodeOperands(SDValue(N, 0),
893 SExtPromotedInteger(N->getOperand(0)));
896 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
897 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
898 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
899 int SVOffset = N->getSrcValueOffset();
900 unsigned Alignment = N->getAlignment();
901 bool isVolatile = N->isVolatile();
903 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
905 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
907 // Truncate the value and store the result.
908 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
909 SVOffset, N->getMemoryVT(),
910 isVolatile, Alignment);
913 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
914 SDValue Op = GetPromotedInteger(N->getOperand(0));
915 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
918 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
919 return DAG.UpdateNodeOperands(SDValue(N, 0),
920 ZExtPromotedInteger(N->getOperand(0)));
923 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
924 SDValue Op = GetPromotedInteger(N->getOperand(0));
925 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
926 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
930 //===----------------------------------------------------------------------===//
931 // Integer Result Expansion
932 //===----------------------------------------------------------------------===//
934 /// ExpandIntegerResult - This method is called when the specified result of the
935 /// specified node is found to need expansion. At this point, the node may also
936 /// have invalid operands or may have other results that need promotion, we just
937 /// know that (at least) one result needs expansion.
938 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
939 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
943 // See if the target wants to custom expand this node.
944 if (CustomLowerResults(N, ResNo))
947 switch (N->getOpcode()) {
950 cerr << "ExpandIntegerResult #" << ResNo << ": ";
951 N->dump(&DAG); cerr << "\n";
953 assert(0 && "Do not know how to expand the result of this operator!");
956 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
957 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
958 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
959 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
961 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
962 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
963 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
964 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
965 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
967 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
968 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
969 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
970 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
971 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
972 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
973 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
974 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
975 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
976 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
977 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
978 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
979 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
980 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
981 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
982 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
983 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
984 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
985 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
986 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
990 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
993 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
996 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
999 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1003 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1006 // If Lo/Hi is null, the sub-method took care of registering results etc.
1008 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1011 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1012 /// and the shift amount is a constant 'Amt'. Expand the operation.
1013 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1014 SDValue &Lo, SDValue &Hi) {
1015 // Expand the incoming operand to be shifted, so that we have its parts
1017 GetExpandedInteger(N->getOperand(0), InL, InH);
1019 MVT NVT = InL.getValueType();
1020 unsigned VTBits = N->getValueType(0).getSizeInBits();
1021 unsigned NVTBits = NVT.getSizeInBits();
1022 MVT ShTy = N->getOperand(1).getValueType();
1024 if (N->getOpcode() == ISD::SHL) {
1026 Lo = Hi = DAG.getConstant(0, NVT);
1027 } else if (Amt > NVTBits) {
1028 Lo = DAG.getConstant(0, NVT);
1029 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1030 } else if (Amt == NVTBits) {
1031 Lo = DAG.getConstant(0, NVT);
1033 } else if (Amt == 1 &&
1034 TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
1035 // Emit this X << 1 as X+X.
1036 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1037 SDValue LoOps[2] = { InL, InL };
1038 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1039 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1040 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1042 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1043 Hi = DAG.getNode(ISD::OR, NVT,
1044 DAG.getNode(ISD::SHL, NVT, InH,
1045 DAG.getConstant(Amt, ShTy)),
1046 DAG.getNode(ISD::SRL, NVT, InL,
1047 DAG.getConstant(NVTBits-Amt, ShTy)));
1052 if (N->getOpcode() == ISD::SRL) {
1054 Lo = DAG.getConstant(0, NVT);
1055 Hi = DAG.getConstant(0, NVT);
1056 } else if (Amt > NVTBits) {
1057 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1058 Hi = DAG.getConstant(0, NVT);
1059 } else if (Amt == NVTBits) {
1061 Hi = DAG.getConstant(0, NVT);
1063 Lo = DAG.getNode(ISD::OR, NVT,
1064 DAG.getNode(ISD::SRL, NVT, InL,
1065 DAG.getConstant(Amt, ShTy)),
1066 DAG.getNode(ISD::SHL, NVT, InH,
1067 DAG.getConstant(NVTBits-Amt, ShTy)));
1068 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1073 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1075 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1076 DAG.getConstant(NVTBits-1, ShTy));
1077 } else if (Amt > NVTBits) {
1078 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1079 DAG.getConstant(Amt-NVTBits, ShTy));
1080 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1081 DAG.getConstant(NVTBits-1, ShTy));
1082 } else if (Amt == NVTBits) {
1084 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1085 DAG.getConstant(NVTBits-1, ShTy));
1087 Lo = DAG.getNode(ISD::OR, NVT,
1088 DAG.getNode(ISD::SRL, NVT, InL,
1089 DAG.getConstant(Amt, ShTy)),
1090 DAG.getNode(ISD::SHL, NVT, InH,
1091 DAG.getConstant(NVTBits-Amt, ShTy)));
1092 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1096 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1097 /// this shift based on knowledge of the high bit of the shift amount. If we
1098 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1100 bool DAGTypeLegalizer::
1101 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1102 SDValue Amt = N->getOperand(1);
1103 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1104 MVT ShTy = Amt.getValueType();
1105 unsigned ShBits = ShTy.getSizeInBits();
1106 unsigned NVTBits = NVT.getSizeInBits();
1107 assert(isPowerOf2_32(NVTBits) &&
1108 "Expanded integer type size not a power of two!");
1110 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1111 APInt KnownZero, KnownOne;
1112 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1114 // If we don't know anything about the high bits, exit.
1115 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1118 // Get the incoming operand to be shifted.
1120 GetExpandedInteger(N->getOperand(0), InL, InH);
1122 // If we know that any of the high bits of the shift amount are one, then we
1123 // can do this as a couple of simple shifts.
1124 if (KnownOne.intersects(HighBitMask)) {
1125 // Mask out the high bit, which we know is set.
1126 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1127 DAG.getConstant(~HighBitMask, ShTy));
1129 switch (N->getOpcode()) {
1130 default: assert(0 && "Unknown shift");
1132 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1133 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1136 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1137 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1140 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1141 DAG.getConstant(NVTBits-1, ShTy));
1142 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1147 // If we know that all of the high bits of the shift amount are zero, then we
1148 // can do this as a couple of simple shifts.
1149 if ((KnownZero & HighBitMask) == HighBitMask) {
1151 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1152 DAG.getConstant(NVTBits, ShTy),
1155 switch (N->getOpcode()) {
1156 default: assert(0 && "Unknown shift");
1157 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1159 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1162 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1163 Hi = DAG.getNode(ISD::OR, NVT,
1164 DAG.getNode(Op1, NVT, InH, Amt),
1165 DAG.getNode(Op2, NVT, InL, Amt2));
1172 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1173 SDValue &Lo, SDValue &Hi) {
1174 // Expand the subcomponents.
1175 SDValue LHSL, LHSH, RHSL, RHSH;
1176 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1177 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1179 MVT NVT = LHSL.getValueType();
1180 SDValue LoOps[2] = { LHSL, RHSL };
1181 SDValue HiOps[3] = { LHSH, RHSH };
1183 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1184 // them. TODO: Teach operation legalization how to expand unsupported
1185 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1186 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1187 // generate a value of this type in the expanded code sequence.
1189 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC,
1190 TLI.getTypeToExpandTo(NVT));
1193 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1194 if (N->getOpcode() == ISD::ADD) {
1195 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1196 HiOps[2] = Lo.getValue(1);
1197 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1199 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1200 HiOps[2] = Lo.getValue(1);
1201 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1204 if (N->getOpcode() == ISD::ADD) {
1205 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
1206 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
1207 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
1209 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
1210 DAG.getConstant(1, NVT),
1211 DAG.getConstant(0, NVT));
1212 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1],
1214 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
1215 DAG.getConstant(1, NVT), Carry1);
1216 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
1218 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
1219 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
1220 SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]),
1221 LoOps[0], LoOps[1], ISD::SETULT);
1222 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
1223 DAG.getConstant(1, NVT),
1224 DAG.getConstant(0, NVT));
1225 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
1230 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1231 SDValue &Lo, SDValue &Hi) {
1232 // Expand the subcomponents.
1233 SDValue LHSL, LHSH, RHSL, RHSH;
1234 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1235 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1236 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1237 SDValue LoOps[2] = { LHSL, RHSL };
1238 SDValue HiOps[3] = { LHSH, RHSH };
1240 if (N->getOpcode() == ISD::ADDC) {
1241 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1242 HiOps[2] = Lo.getValue(1);
1243 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1245 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1246 HiOps[2] = Lo.getValue(1);
1247 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1250 // Legalized the flag result - switch anything that used the old flag to
1252 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1255 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1256 SDValue &Lo, SDValue &Hi) {
1257 // Expand the subcomponents.
1258 SDValue LHSL, LHSH, RHSL, RHSH;
1259 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1260 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1261 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1262 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1263 SDValue HiOps[3] = { LHSH, RHSH };
1265 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1266 HiOps[2] = Lo.getValue(1);
1267 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1269 // Legalized the flag result - switch anything that used the old flag to
1271 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1274 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1275 SDValue &Lo, SDValue &Hi) {
1276 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1277 SDValue Op = N->getOperand(0);
1278 if (Op.getValueType().bitsLE(NVT)) {
1279 // The low part is any extension of the input (which degenerates to a copy).
1280 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1281 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1283 // For example, extension of an i48 to an i64. The operand type necessarily
1284 // promotes to the result type, so will end up being expanded too.
1285 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1286 "Only know how to promote this result!");
1287 SDValue Res = GetPromotedInteger(Op);
1288 assert(Res.getValueType() == N->getValueType(0) &&
1289 "Operand over promoted?");
1290 // Split the promoted operand. This will simplify when it is expanded.
1291 SplitInteger(Res, Lo, Hi);
1295 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1296 SDValue &Lo, SDValue &Hi) {
1297 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1298 MVT NVT = Lo.getValueType();
1299 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1300 unsigned NVTBits = NVT.getSizeInBits();
1301 unsigned EVTBits = EVT.getSizeInBits();
1303 if (NVTBits < EVTBits) {
1304 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1305 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1307 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1308 // The high part replicates the sign bit of Lo, make it explicit.
1309 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1310 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1314 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1315 SDValue &Lo, SDValue &Hi) {
1316 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1317 MVT NVT = Lo.getValueType();
1318 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1319 unsigned NVTBits = NVT.getSizeInBits();
1320 unsigned EVTBits = EVT.getSizeInBits();
1322 if (NVTBits < EVTBits) {
1323 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1324 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1326 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1327 // The high part must be zero, make it explicit.
1328 Hi = DAG.getConstant(0, NVT);
1332 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1333 SDValue &Lo, SDValue &Hi) {
1334 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1335 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1336 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1339 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1340 SDValue &Lo, SDValue &Hi) {
1341 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1342 unsigned NBitWidth = NVT.getSizeInBits();
1343 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1344 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1345 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1348 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1349 SDValue &Lo, SDValue &Hi) {
1350 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1351 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1352 MVT NVT = Lo.getValueType();
1354 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1355 DAG.getConstant(0, NVT), ISD::SETNE);
1357 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1358 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1360 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1361 DAG.getNode(ISD::ADD, NVT, LoLZ,
1362 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1363 Hi = DAG.getConstant(0, NVT);
1366 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1367 SDValue &Lo, SDValue &Hi) {
1368 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1369 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1370 MVT NVT = Lo.getValueType();
1371 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1372 DAG.getNode(ISD::CTPOP, NVT, Hi));
1373 Hi = DAG.getConstant(0, NVT);
1376 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1377 SDValue &Lo, SDValue &Hi) {
1378 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1379 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1380 MVT NVT = Lo.getValueType();
1382 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1383 DAG.getConstant(0, NVT), ISD::SETNE);
1385 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1386 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1388 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1389 DAG.getNode(ISD::ADD, NVT, HiLZ,
1390 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1391 Hi = DAG.getConstant(0, NVT);
1394 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1396 MVT VT = N->getValueType(0);
1397 SDValue Op = N->getOperand(0);
1398 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1399 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1400 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1403 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1405 MVT VT = N->getValueType(0);
1406 SDValue Op = N->getOperand(0);
1407 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1408 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1409 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1412 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1413 SDValue &Lo, SDValue &Hi) {
1414 if (ISD::isNormalLoad(N)) {
1415 ExpandRes_NormalLoad(N, Lo, Hi);
1419 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1421 MVT VT = N->getValueType(0);
1422 MVT NVT = TLI.getTypeToTransformTo(VT);
1423 SDValue Ch = N->getChain();
1424 SDValue Ptr = N->getBasePtr();
1425 ISD::LoadExtType ExtType = N->getExtensionType();
1426 int SVOffset = N->getSrcValueOffset();
1427 unsigned Alignment = N->getAlignment();
1428 bool isVolatile = N->isVolatile();
1430 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1432 if (N->getMemoryVT().bitsLE(NVT)) {
1433 MVT EVT = N->getMemoryVT();
1435 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1436 isVolatile, Alignment);
1438 // Remember the chain.
1439 Ch = Lo.getValue(1);
1441 if (ExtType == ISD::SEXTLOAD) {
1442 // The high part is obtained by SRA'ing all but one of the bits of the
1444 unsigned LoSize = Lo.getValueType().getSizeInBits();
1445 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1446 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1447 } else if (ExtType == ISD::ZEXTLOAD) {
1448 // The high part is just a zero.
1449 Hi = DAG.getConstant(0, NVT);
1451 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1452 // The high part is undefined.
1453 Hi = DAG.getNode(ISD::UNDEF, NVT);
1455 } else if (TLI.isLittleEndian()) {
1456 // Little-endian - low bits are at low addresses.
1457 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1458 isVolatile, Alignment);
1460 unsigned ExcessBits =
1461 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1462 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1464 // Increment the pointer to the other half.
1465 unsigned IncrementSize = NVT.getSizeInBits()/8;
1466 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1467 DAG.getIntPtrConstant(IncrementSize));
1468 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1469 SVOffset+IncrementSize, NEVT,
1470 isVolatile, MinAlign(Alignment, IncrementSize));
1472 // Build a factor node to remember that this load is independent of the
1474 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1477 // Big-endian - high bits are at low addresses. Favor aligned loads at
1478 // the cost of some bit-fiddling.
1479 MVT EVT = N->getMemoryVT();
1480 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1481 unsigned IncrementSize = NVT.getSizeInBits()/8;
1482 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1484 // Load both the high bits and maybe some of the low bits.
1485 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1486 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1487 isVolatile, Alignment);
1489 // Increment the pointer to the other half.
1490 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1491 DAG.getIntPtrConstant(IncrementSize));
1492 // Load the rest of the low bits.
1493 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1494 SVOffset+IncrementSize,
1495 MVT::getIntegerVT(ExcessBits),
1496 isVolatile, MinAlign(Alignment, IncrementSize));
1498 // Build a factor node to remember that this load is independent of the
1500 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1503 if (ExcessBits < NVT.getSizeInBits()) {
1504 // Transfer low bits from the bottom of Hi to the top of Lo.
1505 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1506 DAG.getNode(ISD::SHL, NVT, Hi,
1507 DAG.getConstant(ExcessBits,
1508 TLI.getShiftAmountTy())));
1509 // Move high bits to the right position in Hi.
1510 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1511 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1512 TLI.getShiftAmountTy()));
1516 // Legalized the chain result - switch anything that used the old chain to
1518 ReplaceValueWith(SDValue(N, 1), Ch);
1521 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1522 SDValue &Lo, SDValue &Hi) {
1523 SDValue LL, LH, RL, RH;
1524 GetExpandedInteger(N->getOperand(0), LL, LH);
1525 GetExpandedInteger(N->getOperand(1), RL, RH);
1526 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1527 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1530 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1531 SDValue &Lo, SDValue &Hi) {
1532 MVT VT = N->getValueType(0);
1533 MVT NVT = TLI.getTypeToTransformTo(VT);
1535 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1536 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1537 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1538 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1539 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1540 SDValue LL, LH, RL, RH;
1541 GetExpandedInteger(N->getOperand(0), LL, LH);
1542 GetExpandedInteger(N->getOperand(1), RL, RH);
1543 unsigned OuterBitSize = VT.getSizeInBits();
1544 unsigned InnerBitSize = NVT.getSizeInBits();
1545 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1546 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1548 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1549 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1550 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1551 // The inputs are both zero-extended.
1553 // We can emit a umul_lohi.
1554 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1555 Hi = SDValue(Lo.getNode(), 1);
1559 // We can emit a mulhu+mul.
1560 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1561 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1565 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1566 // The input values are both sign-extended.
1568 // We can emit a smul_lohi.
1569 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1570 Hi = SDValue(Lo.getNode(), 1);
1574 // We can emit a mulhs+mul.
1575 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1576 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1581 // Lo,Hi = umul LHS, RHS.
1582 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1583 DAG.getVTList(NVT, NVT), LL, RL);
1585 Hi = UMulLOHI.getValue(1);
1586 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1587 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1588 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1589 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1593 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1594 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1595 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1596 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1597 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1598 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1603 // If nothing else, we can make a libcall.
1604 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1606 LC = RTLIB::MUL_I32;
1607 else if (VT == MVT::i64)
1608 LC = RTLIB::MUL_I64;
1609 else if (VT == MVT::i128)
1610 LC = RTLIB::MUL_I128;
1611 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1613 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1614 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1617 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1618 SDValue &Lo, SDValue &Hi) {
1619 MVT VT = N->getValueType(0);
1621 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1623 LC = RTLIB::SDIV_I32;
1624 else if (VT == MVT::i64)
1625 LC = RTLIB::SDIV_I64;
1626 else if (VT == MVT::i128)
1627 LC = RTLIB::SDIV_I128;
1628 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1630 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1631 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1634 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1635 SDValue &Lo, SDValue &Hi) {
1636 MVT VT = N->getValueType(0);
1638 // If we can emit an efficient shift operation, do so now. Check to see if
1639 // the RHS is a constant.
1640 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1641 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1643 // If we can determine that the high bit of the shift is zero or one, even if
1644 // the low bits are variable, emit this shift in an optimized form.
1645 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1648 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1650 if (N->getOpcode() == ISD::SHL) {
1651 PartsOpc = ISD::SHL_PARTS;
1652 } else if (N->getOpcode() == ISD::SRL) {
1653 PartsOpc = ISD::SRL_PARTS;
1655 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1656 PartsOpc = ISD::SRA_PARTS;
1659 // Next check to see if the target supports this SHL_PARTS operation or if it
1660 // will custom expand it.
1661 MVT NVT = TLI.getTypeToTransformTo(VT);
1662 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1663 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1664 Action == TargetLowering::Custom) {
1665 // Expand the subcomponents.
1667 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1669 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1670 MVT VT = LHSL.getValueType();
1671 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1672 Hi = Lo.getValue(1);
1676 // Otherwise, emit a libcall.
1677 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1679 if (N->getOpcode() == ISD::SHL) {
1680 isSigned = false; /*sign irrelevant*/
1682 LC = RTLIB::SHL_I32;
1683 else if (VT == MVT::i64)
1684 LC = RTLIB::SHL_I64;
1685 else if (VT == MVT::i128)
1686 LC = RTLIB::SHL_I128;
1687 } else if (N->getOpcode() == ISD::SRL) {
1690 LC = RTLIB::SRL_I32;
1691 else if (VT == MVT::i64)
1692 LC = RTLIB::SRL_I64;
1693 else if (VT == MVT::i128)
1694 LC = RTLIB::SRL_I128;
1696 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1699 LC = RTLIB::SRA_I32;
1700 else if (VT == MVT::i64)
1701 LC = RTLIB::SRA_I64;
1702 else if (VT == MVT::i128)
1703 LC = RTLIB::SRA_I128;
1705 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1707 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1708 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1711 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1712 SDValue &Lo, SDValue &Hi) {
1713 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1714 SDValue Op = N->getOperand(0);
1715 if (Op.getValueType().bitsLE(NVT)) {
1716 // The low part is sign extension of the input (degenerates to a copy).
1717 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1718 // The high part is obtained by SRA'ing all but one of the bits of low part.
1719 unsigned LoSize = NVT.getSizeInBits();
1720 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1721 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1723 // For example, extension of an i48 to an i64. The operand type necessarily
1724 // promotes to the result type, so will end up being expanded too.
1725 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1726 "Only know how to promote this result!");
1727 SDValue Res = GetPromotedInteger(Op);
1728 assert(Res.getValueType() == N->getValueType(0) &&
1729 "Operand over promoted?");
1730 // Split the promoted operand. This will simplify when it is expanded.
1731 SplitInteger(Res, Lo, Hi);
1732 unsigned ExcessBits =
1733 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1734 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1735 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1739 void DAGTypeLegalizer::
1740 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1741 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1742 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1744 if (EVT.bitsLE(Lo.getValueType())) {
1745 // sext_inreg the low part if needed.
1746 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1749 // The high part gets the sign extension from the lo-part. This handles
1750 // things like sextinreg V:i64 from i8.
1751 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1752 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1753 TLI.getShiftAmountTy()));
1755 // For example, extension of an i48 to an i64. Leave the low part alone,
1756 // sext_inreg the high part.
1757 unsigned ExcessBits =
1758 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1759 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1760 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1764 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1765 SDValue &Lo, SDValue &Hi) {
1766 MVT VT = N->getValueType(0);
1768 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1770 LC = RTLIB::SREM_I32;
1771 else if (VT == MVT::i64)
1772 LC = RTLIB::SREM_I64;
1773 else if (VT == MVT::i128)
1774 LC = RTLIB::SREM_I128;
1775 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1777 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1778 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1781 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1782 SDValue &Lo, SDValue &Hi) {
1783 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1784 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1785 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1786 DAG.getConstant(NVT.getSizeInBits(),
1787 TLI.getShiftAmountTy()));
1788 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1791 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1792 SDValue &Lo, SDValue &Hi) {
1793 MVT VT = N->getValueType(0);
1795 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1797 LC = RTLIB::UDIV_I32;
1798 else if (VT == MVT::i64)
1799 LC = RTLIB::UDIV_I64;
1800 else if (VT == MVT::i128)
1801 LC = RTLIB::UDIV_I128;
1802 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1804 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1805 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1808 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1809 SDValue &Lo, SDValue &Hi) {
1810 MVT VT = N->getValueType(0);
1812 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1814 LC = RTLIB::UREM_I32;
1815 else if (VT == MVT::i64)
1816 LC = RTLIB::UREM_I64;
1817 else if (VT == MVT::i128)
1818 LC = RTLIB::UREM_I128;
1819 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1821 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1822 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1825 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1826 SDValue &Lo, SDValue &Hi) {
1827 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1828 SDValue Op = N->getOperand(0);
1829 if (Op.getValueType().bitsLE(NVT)) {
1830 // The low part is zero extension of the input (degenerates to a copy).
1831 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1832 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1834 // For example, extension of an i48 to an i64. The operand type necessarily
1835 // promotes to the result type, so will end up being expanded too.
1836 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1837 "Only know how to promote this result!");
1838 SDValue Res = GetPromotedInteger(Op);
1839 assert(Res.getValueType() == N->getValueType(0) &&
1840 "Operand over promoted?");
1841 // Split the promoted operand. This will simplify when it is expanded.
1842 SplitInteger(Res, Lo, Hi);
1843 unsigned ExcessBits =
1844 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1845 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1850 //===----------------------------------------------------------------------===//
1851 // Integer Operand Expansion
1852 //===----------------------------------------------------------------------===//
1854 /// ExpandIntegerOperand - This method is called when the specified operand of
1855 /// the specified node is found to need expansion. At this point, all of the
1856 /// result types of the node are known to be legal, but other operands of the
1857 /// node may need promotion or expansion as well as the specified one.
1858 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1859 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1860 SDValue Res = SDValue();
1862 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1863 == TargetLowering::Custom)
1864 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
1866 if (Res.getNode() == 0) {
1867 switch (N->getOpcode()) {
1870 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1871 N->dump(&DAG); cerr << "\n";
1873 assert(0 && "Do not know how to expand this operator's operand!");
1876 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1877 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1878 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1880 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1881 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1882 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1883 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1884 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1886 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1887 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1891 // If the result is null, the sub-method took care of registering results etc.
1892 if (!Res.getNode()) return false;
1893 // If the result is N, the sub-method updated N in place. Check to see if any
1894 // operands are new, and if so, mark them.
1895 if (Res.getNode() == N) {
1896 // Mark N as new and remark N and its operands. This allows us to correctly
1897 // revisit N if it needs another step of expansion and allows us to visit
1898 // any new operands to N.
1903 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1904 "Invalid operand expansion");
1906 ReplaceValueWith(SDValue(N, 0), Res);
1910 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1911 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1912 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1914 ISD::CondCode &CCCode) {
1915 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1916 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1917 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1919 MVT VT = NewLHS.getValueType();
1921 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1922 if (RHSLo == RHSHi) {
1923 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1924 if (RHSCST->isAllOnesValue()) {
1925 // Equality comparison to -1.
1926 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1933 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1934 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1935 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1936 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1940 // If this is a comparison of the sign bit, just look at the top part.
1942 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1943 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1944 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1950 // FIXME: This generated code sucks.
1951 ISD::CondCode LowCC;
1953 default: assert(0 && "Unknown integer setcc!");
1955 case ISD::SETULT: LowCC = ISD::SETULT; break;
1957 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1959 case ISD::SETULE: LowCC = ISD::SETULE; break;
1961 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1964 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1965 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1966 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1968 // NOTE: on targets without efficient SELECT of bools, we can always use
1969 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1970 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1972 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1973 false, DagCombineInfo);
1974 if (!Tmp1.getNode())
1975 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1976 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1977 CCCode, false, DagCombineInfo);
1978 if (!Tmp2.getNode())
1979 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1980 DAG.getCondCode(CCCode));
1982 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
1983 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
1984 if ((Tmp1C && Tmp1C->isNullValue()) ||
1985 (Tmp2C && Tmp2C->isNullValue() &&
1986 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1987 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1988 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1989 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1990 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1991 // low part is known false, returns high part.
1992 // For LE / GE, if high part is known false, ignore the low part.
1993 // For LT / GT, if high part is known true, ignore the low part.
1999 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2000 ISD::SETEQ, false, DagCombineInfo);
2001 if (!NewLHS.getNode())
2002 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2004 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2005 NewLHS, Tmp1, Tmp2);
2009 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2010 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2011 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2012 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2014 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2015 // against zero to select between true and false values.
2016 if (NewRHS.getNode() == 0) {
2017 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2018 CCCode = ISD::SETNE;
2021 // Update N to have the operands specified.
2022 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2023 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2027 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2028 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2029 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2030 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2032 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2033 // against zero to select between true and false values.
2034 if (NewRHS.getNode() == 0) {
2035 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2036 CCCode = ISD::SETNE;
2039 // Update N to have the operands specified.
2040 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2041 N->getOperand(2), N->getOperand(3),
2042 DAG.getCondCode(CCCode));
2045 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2046 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2047 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2048 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2050 // If ExpandSetCCOperands returned a scalar, use it.
2051 if (NewRHS.getNode() == 0) {
2052 assert(NewLHS.getValueType() == N->getValueType(0) &&
2053 "Unexpected setcc expansion!");
2057 // Otherwise, update N to have the operands specified.
2058 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2059 DAG.getCondCode(CCCode));
2062 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2063 SDValue Op = N->getOperand(0);
2064 MVT DstVT = N->getValueType(0);
2065 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2066 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2067 "Don't know how to expand this SINT_TO_FP!");
2068 return MakeLibCall(LC, DstVT, &Op, 1, true);
2071 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2072 if (ISD::isNormalStore(N))
2073 return ExpandOp_NormalStore(N, OpNo);
2075 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2076 assert(OpNo == 1 && "Can only expand the stored value so far");
2078 MVT VT = N->getOperand(1).getValueType();
2079 MVT NVT = TLI.getTypeToTransformTo(VT);
2080 SDValue Ch = N->getChain();
2081 SDValue Ptr = N->getBasePtr();
2082 int SVOffset = N->getSrcValueOffset();
2083 unsigned Alignment = N->getAlignment();
2084 bool isVolatile = N->isVolatile();
2087 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2089 if (N->getMemoryVT().bitsLE(NVT)) {
2090 GetExpandedInteger(N->getValue(), Lo, Hi);
2091 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2092 N->getMemoryVT(), isVolatile, Alignment);
2093 } else if (TLI.isLittleEndian()) {
2094 // Little-endian - low bits are at low addresses.
2095 GetExpandedInteger(N->getValue(), Lo, Hi);
2097 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2098 isVolatile, Alignment);
2100 unsigned ExcessBits =
2101 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2102 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2104 // Increment the pointer to the other half.
2105 unsigned IncrementSize = NVT.getSizeInBits()/8;
2106 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2107 DAG.getIntPtrConstant(IncrementSize));
2108 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2109 SVOffset+IncrementSize, NEVT,
2110 isVolatile, MinAlign(Alignment, IncrementSize));
2111 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2113 // Big-endian - high bits are at low addresses. Favor aligned stores at
2114 // the cost of some bit-fiddling.
2115 GetExpandedInteger(N->getValue(), Lo, Hi);
2117 MVT EVT = N->getMemoryVT();
2118 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2119 unsigned IncrementSize = NVT.getSizeInBits()/8;
2120 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2121 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2123 if (ExcessBits < NVT.getSizeInBits()) {
2124 // Transfer high bits from the top of Lo to the bottom of Hi.
2125 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2126 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2127 TLI.getShiftAmountTy()));
2128 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2129 DAG.getNode(ISD::SRL, NVT, Lo,
2130 DAG.getConstant(ExcessBits,
2131 TLI.getShiftAmountTy())));
2134 // Store both the high bits and maybe some of the low bits.
2135 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2136 SVOffset, HiVT, isVolatile, Alignment);
2138 // Increment the pointer to the other half.
2139 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2140 DAG.getIntPtrConstant(IncrementSize));
2141 // Store the lowest ExcessBits bits in the second half.
2142 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2143 SVOffset+IncrementSize,
2144 MVT::getIntegerVT(ExcessBits),
2145 isVolatile, MinAlign(Alignment, IncrementSize));
2146 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2150 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2152 GetExpandedInteger(N->getOperand(0), InL, InH);
2153 // Just truncate the low part of the source.
2154 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2157 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2158 SDValue Op = N->getOperand(0);
2159 MVT SrcVT = Op.getValueType();
2160 MVT DstVT = N->getValueType(0);
2162 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2163 // Do a signed conversion then adjust the result.
2164 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2165 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2167 // The result of the signed conversion needs adjusting if the 'sign bit' of
2168 // the incoming integer was set. To handle this, we dynamically test to see
2169 // if it is set, and, if so, add a fudge factor.
2171 const uint64_t F32TwoE32 = 0x4F800000ULL;
2172 const uint64_t F32TwoE64 = 0x5F800000ULL;
2173 const uint64_t F32TwoE128 = 0x7F800000ULL;
2176 if (SrcVT == MVT::i32)
2177 FF = APInt(32, F32TwoE32);
2178 else if (SrcVT == MVT::i64)
2179 FF = APInt(32, F32TwoE64);
2180 else if (SrcVT == MVT::i128)
2181 FF = APInt(32, F32TwoE128);
2183 assert(false && "Unsupported UINT_TO_FP!");
2185 // Check whether the sign bit is set.
2187 GetExpandedInteger(Op, Lo, Hi);
2188 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2189 DAG.getConstant(0, Hi.getValueType()),
2192 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2193 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2194 TLI.getPointerTy());
2196 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2197 SDValue Zero = DAG.getIntPtrConstant(0);
2198 SDValue Four = DAG.getIntPtrConstant(4);
2199 if (TLI.isBigEndian()) std::swap(Zero, Four);
2200 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2202 unsigned Alignment =
2203 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2204 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2205 Alignment = std::min(Alignment, 4u);
2207 // Load the value out, extending it from f32 to the destination float type.
2208 // FIXME: Avoid the extend by constructing the right constant pool?
2209 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2210 FudgePtr, NULL, 0, MVT::f32,
2212 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2215 // Otherwise, use a libcall.
2216 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2217 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2218 "Don't know how to expand this UINT_TO_FP!");
2219 return MakeLibCall(LC, DstVT, &Op, 1, true);