1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDOperand Result = SDOperand();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
80 case ISD::SIGN_EXTEND:
81 case ISD::ZERO_EXTEND:
82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
101 // If Result is null, the sub-method took care of registering the result.
103 SetPromotedInteger(SDOperand(N, ResNo), Result);
106 SDOperand DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
107 // Sign-extend the new bits, and continue the assertion.
108 MVT OldVT = N->getValueType(0);
109 SDOperand Op = GetPromotedInteger(N->getOperand(0));
110 return DAG.getNode(ISD::AssertSext, Op.getValueType(),
111 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
112 DAG.getValueType(OldVT)), N->getOperand(1));
115 SDOperand DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
116 // Zero the new bits, and continue the assertion.
117 MVT OldVT = N->getValueType(0);
118 SDOperand Op = GetPromotedInteger(N->getOperand(0));
119 return DAG.getNode(ISD::AssertZext, Op.getValueType(),
120 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
123 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
124 SDOperand InOp = N->getOperand(0);
125 MVT InVT = InOp.getValueType();
126 MVT NInVT = TLI.getTypeToTransformTo(InVT);
127 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
129 switch (getTypeAction(InVT)) {
131 assert(false && "Unknown type action!");
136 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
137 // The input promotes to the same size. Convert the promoted value.
138 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
141 // Promote the integer operand by hand.
142 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
146 case ScalarizeVector:
147 // Convert the element to an integer and promote it by hand.
148 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
149 BitConvertToInteger(GetScalarizedVector(InOp)));
151 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
152 // pieces of the input into integers and reassemble in the final type.
154 GetSplitVector(N->getOperand(0), Lo, Hi);
155 Lo = BitConvertToInteger(Lo);
156 Hi = BitConvertToInteger(Hi);
158 if (TLI.isBigEndian())
161 InOp = DAG.getNode(ISD::ANY_EXTEND,
162 MVT::getIntegerVT(OutVT.getSizeInBits()),
163 JoinIntegers(Lo, Hi));
164 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
167 // Otherwise, lower the bit-convert to a store/load from the stack, then
169 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
170 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
173 SDOperand DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
174 SDOperand Op = GetPromotedInteger(N->getOperand(0));
175 MVT OVT = N->getValueType(0);
176 MVT NVT = Op.getValueType();
178 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
179 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
180 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
183 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
184 // The pair element type may be legal, or may not promote to the same type as
185 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
186 return DAG.getNode(ISD::ANY_EXTEND,
187 TLI.getTypeToTransformTo(N->getValueType(0)),
188 JoinIntegers(N->getOperand(0), N->getOperand(1)));
191 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
192 MVT VT = N->getValueType(0);
193 // Zero extend things like i1, sign extend everything else. It shouldn't
194 // matter in theory which one we pick, but this tends to give better code?
195 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
196 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
198 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
202 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
203 SDOperand Op = GetPromotedInteger(N->getOperand(0));
204 MVT OVT = N->getValueType(0);
205 MVT NVT = Op.getValueType();
206 // Zero extend to the promoted type and do the count there.
207 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
208 // Subtract off the extra leading bits in the bigger type.
209 return DAG.getNode(ISD::SUB, NVT, Op,
210 DAG.getConstant(NVT.getSizeInBits() -
211 OVT.getSizeInBits(), NVT));
214 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
215 SDOperand Op = GetPromotedInteger(N->getOperand(0));
216 MVT OVT = N->getValueType(0);
217 MVT NVT = Op.getValueType();
218 // Zero extend to the promoted type and do the count there.
219 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
222 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
223 SDOperand Op = GetPromotedInteger(N->getOperand(0));
224 MVT OVT = N->getValueType(0);
225 MVT NVT = Op.getValueType();
226 // The count is the same in the promoted type except if the original
227 // value was zero. This can be handled by setting the bit just off
228 // the top of the original type.
229 APInt TopBit(NVT.getSizeInBits(), 0);
230 TopBit.set(OVT.getSizeInBits());
231 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
232 return DAG.getNode(ISD::CTTZ, NVT, Op);
235 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
236 MVT OldVT = N->getValueType(0);
237 SDOperand OldVec = N->getOperand(0);
238 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
241 assert(!isTypeLegal(OldVec.getValueType()) &&
242 "Legal one-element vector of a type needing promotion!");
243 // It is tempting to follow GetScalarizedVector by a call to
244 // GetPromotedInteger, but this would be wrong because the
245 // scalarized value may not yet have been processed.
246 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
247 GetScalarizedVector(OldVec));
250 // Convert to a vector half as long with an element type of twice the width,
251 // for example <4 x i16> -> <2 x i32>.
252 assert(!(OldElts & 1) && "Odd length vectors not supported!");
253 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
254 assert(OldVT.isSimple() && NewVT.isSimple());
256 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
257 MVT::getVectorVT(NewVT, OldElts / 2),
260 // Extract the element at OldIdx / 2 from the new vector.
261 SDOperand OldIdx = N->getOperand(1);
262 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
263 DAG.getConstant(1, TLI.getShiftAmountTy()));
264 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
266 // Select the appropriate half of the element: Lo if OldIdx was even,
269 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
270 DAG.getConstant(OldVT.getSizeInBits(),
271 TLI.getShiftAmountTy()));
272 if (TLI.isBigEndian())
275 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
276 DAG.getConstant(1, TLI.getShiftAmountTy()));
277 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
280 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
281 unsigned NewOpc = N->getOpcode();
282 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
284 // If we're promoting a UINT to a larger size, check to see if the new node
285 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
286 // we can use that instead. This allows us to generate better code for
287 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
288 // legal, such as PowerPC.
289 if (N->getOpcode() == ISD::FP_TO_UINT) {
290 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
291 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
292 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
293 NewOpc = ISD::FP_TO_SINT;
296 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
299 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
300 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
302 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
303 SDOperand Res = GetPromotedInteger(N->getOperand(0));
304 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
305 "Extension doesn't make sense!");
307 // If the result and operand types are the same after promotion, simplify
308 // to an in-register extension.
309 if (NVT == Res.getValueType()) {
310 // The high bits are not guaranteed to be anything. Insert an extend.
311 if (N->getOpcode() == ISD::SIGN_EXTEND)
312 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
313 DAG.getValueType(N->getOperand(0).getValueType()));
314 if (N->getOpcode() == ISD::ZERO_EXTEND)
315 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
316 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
321 // Otherwise, just extend the original operand all the way to the larger type.
322 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
325 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
326 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
327 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
328 ISD::LoadExtType ExtType =
329 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
330 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
331 N->getSrcValue(), N->getSrcValueOffset(),
332 N->getMemoryVT(), N->isVolatile(),
335 // Legalized the chain result - switch anything that used the old chain to
337 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
341 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
342 // Sign extend the input.
343 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
344 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
345 MVT VT = N->getValueType(0);
346 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
347 DAG.getValueType(VT));
348 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
349 DAG.getValueType(VT));
351 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
354 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
355 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
356 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
357 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
360 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
361 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
362 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
363 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
364 N->getOperand(1), LHS, RHS, N->getOperand(4));
367 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
368 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
369 && "SetCC type is not legal??");
370 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
371 N->getOperand(0), N->getOperand(1), N->getOperand(2));
374 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
375 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
376 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
379 SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
380 SDOperand Op = GetPromotedInteger(N->getOperand(0));
381 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
385 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
386 // The input may have strange things in the top bits of the registers, but
387 // these operations don't care. They may have weird bits going out, but
388 // that too is okay if they are integer operations.
389 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
390 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
391 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
394 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
395 // The input value must be properly sign extended.
396 MVT VT = N->getValueType(0);
397 MVT NVT = TLI.getTypeToTransformTo(VT);
398 SDOperand Res = GetPromotedInteger(N->getOperand(0));
399 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
400 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
403 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
404 // The input value must be properly zero extended.
405 MVT VT = N->getValueType(0);
406 MVT NVT = TLI.getTypeToTransformTo(VT);
407 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
408 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
411 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
414 switch (getTypeAction(N->getOperand(0).getValueType())) {
415 default: assert(0 && "Unknown type action!");
418 Res = N->getOperand(0);
421 Res = GetPromotedInteger(N->getOperand(0));
425 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
426 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
427 "Truncation doesn't make sense!");
428 if (Res.getValueType() == NVT)
431 // Truncate to NVT instead of VT
432 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
435 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
436 // Zero extend the input.
437 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
438 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
439 MVT VT = N->getValueType(0);
440 LHS = DAG.getZeroExtendInReg(LHS, VT);
441 RHS = DAG.getZeroExtendInReg(RHS, VT);
443 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
446 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
447 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
450 SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
451 SDOperand Chain = N->getOperand(0); // Get the chain.
452 SDOperand Ptr = N->getOperand(1); // Get the pointer.
453 MVT VT = N->getValueType(0);
455 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
456 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
458 // Increment the arg pointer, VAList, to the next vaarg
459 // FIXME: should the ABI size be used for the increment? Think of
460 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
461 // integers of unusual size (such MVT::i1, which gives an increment
463 unsigned Increment = VT.getSizeInBits() / 8;
464 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
465 DAG.getConstant(Increment, TLI.getPointerTy()));
467 // Store the incremented VAList to the pointer.
468 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
470 // Load the actual argument out of the arg pointer VAList.
471 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
472 VAList, NULL, 0, VT);
474 // Legalized the chain result - switch anything that used the old chain to
476 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1));
481 //===----------------------------------------------------------------------===//
482 // Integer Operand Promotion
483 //===----------------------------------------------------------------------===//
485 /// PromoteIntegerOperand - This method is called when the specified operand of
486 /// the specified node is found to need promotion. At this point, all of the
487 /// result types of the node are known to be legal, but other operands of the
488 /// node may need promotion or expansion as well as the specified one.
489 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
490 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
491 SDOperand Res = SDOperand();
493 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
494 == TargetLowering::Custom)
495 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
498 switch (N->getOpcode()) {
501 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
502 N->dump(&DAG); cerr << "\n";
504 assert(0 && "Do not know how to promote this operator's operand!");
507 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
508 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
509 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
510 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
511 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
512 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
513 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
514 case ISD::INSERT_VECTOR_ELT:
515 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
516 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
517 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
518 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
519 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
520 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
521 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
523 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
524 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
526 case ISD::SINT_TO_FP:
527 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
531 // If the result is null, the sub-method took care of registering results etc.
532 if (!Res.Val) return false;
533 // If the result is N, the sub-method updated N in place.
535 // Mark N as new and remark N and its operands. This allows us to correctly
536 // revisit N if it needs another step of promotion and allows us to visit
537 // any new operands to N.
542 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
543 "Invalid operand expansion");
545 ReplaceValueWith(SDOperand(N, 0), Res);
549 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
550 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
551 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
552 ISD::CondCode CCCode) {
553 MVT VT = NewLHS.getValueType();
555 // Get the promoted values.
556 NewLHS = GetPromotedInteger(NewLHS);
557 NewRHS = GetPromotedInteger(NewRHS);
559 // Otherwise, we have to insert explicit sign or zero extends. Note
560 // that we could insert sign extends for ALL conditions, but zero extend
561 // is cheaper on many machines (an AND instead of two shifts), so prefer
564 default: assert(0 && "Unknown integer comparison!");
571 // ALL of these operations will work if we either sign or zero extend
572 // the operands (including the unsigned comparisons!). Zero extend is
573 // usually a simpler/cheaper operation, so prefer it.
574 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
575 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
581 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
582 DAG.getValueType(VT));
583 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
584 DAG.getValueType(VT));
589 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
590 SDOperand Op = GetPromotedInteger(N->getOperand(0));
591 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
594 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
595 assert(OpNo == 2 && "Don't know how to promote this operand!");
597 SDOperand LHS = N->getOperand(2);
598 SDOperand RHS = N->getOperand(3);
599 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
601 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
603 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
604 N->getOperand(1), LHS, RHS, N->getOperand(4));
607 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
608 assert(OpNo == 1 && "only know how to promote condition");
609 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
611 // The top bits of the promoted condition are not necessarily zero, ensure
612 // that the value is properly zero extended.
613 unsigned BitWidth = Cond.getValueSizeInBits();
614 if (!DAG.MaskedValueIsZero(Cond,
615 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
616 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
618 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
619 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
623 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
624 // Since the result type is legal, the operands must promote to it.
625 MVT OVT = N->getOperand(0).getValueType();
626 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
627 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
628 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
630 Lo = DAG.getZeroExtendInReg(Lo, OVT);
631 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
632 DAG.getConstant(OVT.getSizeInBits(),
633 TLI.getShiftAmountTy()));
634 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
637 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
638 // The vector type is legal but the element type is not. This implies
639 // that the vector is a power-of-two in length and that the element
640 // type does not have a strange size (eg: it is not i1).
641 MVT VecVT = N->getValueType(0);
642 unsigned NumElts = VecVT.getVectorNumElements();
643 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
645 // Build a vector of half the length out of elements of twice the bitwidth.
646 // For example <4 x i16> -> <2 x i32>.
647 MVT OldVT = N->getOperand(0).getValueType();
648 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
649 assert(OldVT.isSimple() && NewVT.isSimple());
651 std::vector<SDOperand> NewElts;
652 NewElts.reserve(NumElts/2);
654 for (unsigned i = 0; i < NumElts; i += 2) {
655 // Combine two successive elements into one promoted element.
656 SDOperand Lo = N->getOperand(i);
657 SDOperand Hi = N->getOperand(i+1);
658 if (TLI.isBigEndian())
660 NewElts.push_back(JoinIntegers(Lo, Hi));
663 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
664 MVT::getVectorVT(NewVT, NewElts.size()),
665 &NewElts[0], NewElts.size());
667 // Convert the new vector to the old vector type.
668 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
671 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
672 SDOperand Op = GetPromotedInteger(N->getOperand(0));
673 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
676 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
677 SDOperand Op = GetPromotedInteger(N->getOperand(0));
678 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
679 DAG.getIntPtrConstant(0));
682 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
685 // Promote the inserted value. This is valid because the type does not
686 // have to match the vector element type.
688 // Check that any extra bits introduced will be truncated away.
689 assert(N->getOperand(1).getValueType().getSizeInBits() >=
690 N->getValueType(0).getVectorElementType().getSizeInBits() &&
691 "Type of inserted value narrower than vector element type!");
692 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
693 GetPromotedInteger(N->getOperand(1)),
697 assert(OpNo == 2 && "Different operand and result vector types?");
699 // Promote the index.
700 SDOperand Idx = N->getOperand(2);
701 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
702 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
703 N->getOperand(1), Idx);
706 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
707 SDOperand In = GetPromotedInteger(N->getOperand(0));
708 MVT OpVT = N->getOperand(0).getValueType();
709 if (N->getOpcode() == ISD::UINT_TO_FP)
710 In = DAG.getZeroExtendInReg(In, OpVT);
712 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
713 In, DAG.getValueType(OpVT));
715 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
718 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
720 NewOps[0] = N->getOperand(0);
721 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
722 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
723 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
725 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
726 array_lengthof(NewOps));
729 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
730 assert(OpNo == 0 && "Only know how to promote condition");
731 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
733 // The top bits of the promoted condition are not necessarily zero, ensure
734 // that the value is properly zero extended.
735 unsigned BitWidth = Cond.getValueSizeInBits();
736 if (!DAG.MaskedValueIsZero(Cond,
737 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
738 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
740 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
741 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
745 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
746 assert(OpNo == 0 && "Don't know how to promote this operand!");
748 SDOperand LHS = N->getOperand(0);
749 SDOperand RHS = N->getOperand(1);
750 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
752 // The CC (#4) and the possible return values (#2 and #3) have legal types.
753 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2),
754 N->getOperand(3), N->getOperand(4));
757 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
758 assert(OpNo == 0 && "Don't know how to promote this operand!");
760 SDOperand LHS = N->getOperand(0);
761 SDOperand RHS = N->getOperand(1);
762 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
764 // The CC (#2) is always legal.
765 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
768 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
769 SDOperand Op = GetPromotedInteger(N->getOperand(0));
770 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
772 Op, DAG.getValueType(N->getOperand(0).getValueType()));
775 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
776 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
777 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
778 int SVOffset = N->getSrcValueOffset();
779 unsigned Alignment = N->getAlignment();
780 bool isVolatile = N->isVolatile();
782 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
784 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
786 // Truncate the value and store the result.
787 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
788 SVOffset, N->getMemoryVT(),
789 isVolatile, Alignment);
792 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
793 SDOperand Op = GetPromotedInteger(N->getOperand(0));
794 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
797 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
798 SDOperand Op = GetPromotedInteger(N->getOperand(0));
799 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
800 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
804 //===----------------------------------------------------------------------===//
805 // Integer Result Expansion
806 //===----------------------------------------------------------------------===//
808 /// ExpandIntegerResult - This method is called when the specified result of the
809 /// specified node is found to need expansion. At this point, the node may also
810 /// have invalid operands or may have other results that need promotion, we just
811 /// know that (at least) one result needs expansion.
812 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
813 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
815 Lo = Hi = SDOperand();
817 // See if the target wants to custom expand this node.
818 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
819 TargetLowering::Custom) {
820 // If the target wants to, allow it to lower this itself.
821 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
822 // Everything that once used N now uses P. We are guaranteed that the
823 // result value types of N and the result value types of P match.
824 ReplaceNodeWith(N, P);
829 switch (N->getOpcode()) {
832 cerr << "ExpandIntegerResult #" << ResNo << ": ";
833 N->dump(&DAG); cerr << "\n";
835 assert(0 && "Do not know how to expand the result of this operator!");
838 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
839 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
840 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
841 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
843 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
844 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
845 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
846 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
848 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
849 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
850 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
851 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
852 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
853 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
854 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
855 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
856 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
857 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
858 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
859 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
860 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
861 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
862 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
863 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
864 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
865 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
866 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
867 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
871 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
874 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
877 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
880 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
884 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
887 // If Lo/Hi is null, the sub-method took care of registering results etc.
889 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
892 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
893 /// and the shift amount is a constant 'Amt'. Expand the operation.
894 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
895 SDOperand &Lo, SDOperand &Hi) {
896 // Expand the incoming operand to be shifted, so that we have its parts
898 GetExpandedInteger(N->getOperand(0), InL, InH);
900 MVT NVT = InL.getValueType();
901 unsigned VTBits = N->getValueType(0).getSizeInBits();
902 unsigned NVTBits = NVT.getSizeInBits();
903 MVT ShTy = N->getOperand(1).getValueType();
905 if (N->getOpcode() == ISD::SHL) {
907 Lo = Hi = DAG.getConstant(0, NVT);
908 } else if (Amt > NVTBits) {
909 Lo = DAG.getConstant(0, NVT);
910 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
911 } else if (Amt == NVTBits) {
912 Lo = DAG.getConstant(0, NVT);
914 } else if (Amt == 1) {
915 // Emit this X << 1 as X+X.
916 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
917 SDOperand LoOps[2] = { InL, InL };
918 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
919 SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) };
920 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
922 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
923 Hi = DAG.getNode(ISD::OR, NVT,
924 DAG.getNode(ISD::SHL, NVT, InH,
925 DAG.getConstant(Amt, ShTy)),
926 DAG.getNode(ISD::SRL, NVT, InL,
927 DAG.getConstant(NVTBits-Amt, ShTy)));
932 if (N->getOpcode() == ISD::SRL) {
934 Lo = DAG.getConstant(0, NVT);
935 Hi = DAG.getConstant(0, NVT);
936 } else if (Amt > NVTBits) {
937 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
938 Hi = DAG.getConstant(0, NVT);
939 } else if (Amt == NVTBits) {
941 Hi = DAG.getConstant(0, NVT);
943 Lo = DAG.getNode(ISD::OR, NVT,
944 DAG.getNode(ISD::SRL, NVT, InL,
945 DAG.getConstant(Amt, ShTy)),
946 DAG.getNode(ISD::SHL, NVT, InH,
947 DAG.getConstant(NVTBits-Amt, ShTy)));
948 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
953 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
955 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
956 DAG.getConstant(NVTBits-1, ShTy));
957 } else if (Amt > NVTBits) {
958 Lo = DAG.getNode(ISD::SRA, NVT, InH,
959 DAG.getConstant(Amt-NVTBits, ShTy));
960 Hi = DAG.getNode(ISD::SRA, NVT, InH,
961 DAG.getConstant(NVTBits-1, ShTy));
962 } else if (Amt == NVTBits) {
964 Hi = DAG.getNode(ISD::SRA, NVT, InH,
965 DAG.getConstant(NVTBits-1, ShTy));
967 Lo = DAG.getNode(ISD::OR, NVT,
968 DAG.getNode(ISD::SRL, NVT, InL,
969 DAG.getConstant(Amt, ShTy)),
970 DAG.getNode(ISD::SHL, NVT, InH,
971 DAG.getConstant(NVTBits-Amt, ShTy)));
972 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
976 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
977 /// this shift based on knowledge of the high bit of the shift amount. If we
978 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
980 bool DAGTypeLegalizer::
981 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
982 SDOperand Amt = N->getOperand(1);
983 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
984 MVT ShTy = Amt.getValueType();
985 unsigned ShBits = ShTy.getSizeInBits();
986 unsigned NVTBits = NVT.getSizeInBits();
987 assert(isPowerOf2_32(NVTBits) &&
988 "Expanded integer type size not a power of two!");
990 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
991 APInt KnownZero, KnownOne;
992 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
994 // If we don't know anything about the high bits, exit.
995 if (((KnownZero|KnownOne) & HighBitMask) == 0)
998 // Get the incoming operand to be shifted.
1000 GetExpandedInteger(N->getOperand(0), InL, InH);
1002 // If we know that any of the high bits of the shift amount are one, then we
1003 // can do this as a couple of simple shifts.
1004 if (KnownOne.intersects(HighBitMask)) {
1005 // Mask out the high bit, which we know is set.
1006 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1007 DAG.getConstant(~HighBitMask, ShTy));
1009 switch (N->getOpcode()) {
1010 default: assert(0 && "Unknown shift");
1012 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1013 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1016 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1017 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1020 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1021 DAG.getConstant(NVTBits-1, ShTy));
1022 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1027 // If we know that all of the high bits of the shift amount are zero, then we
1028 // can do this as a couple of simple shifts.
1029 if ((KnownZero & HighBitMask) == HighBitMask) {
1031 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1032 DAG.getConstant(NVTBits, ShTy),
1035 switch (N->getOpcode()) {
1036 default: assert(0 && "Unknown shift");
1037 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1039 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1042 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1043 Hi = DAG.getNode(ISD::OR, NVT,
1044 DAG.getNode(Op1, NVT, InH, Amt),
1045 DAG.getNode(Op2, NVT, InL, Amt2));
1052 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1053 SDOperand &Lo, SDOperand &Hi) {
1054 // Expand the subcomponents.
1055 SDOperand LHSL, LHSH, RHSL, RHSH;
1056 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1057 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1058 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1059 SDOperand LoOps[2] = { LHSL, RHSL };
1060 SDOperand HiOps[3] = { LHSH, RHSH };
1062 if (N->getOpcode() == ISD::ADD) {
1063 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1064 HiOps[2] = Lo.getValue(1);
1065 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1067 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1068 HiOps[2] = Lo.getValue(1);
1069 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1073 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1074 SDOperand &Lo, SDOperand &Hi) {
1075 // Expand the subcomponents.
1076 SDOperand LHSL, LHSH, RHSL, RHSH;
1077 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1078 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1079 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1080 SDOperand LoOps[2] = { LHSL, RHSL };
1081 SDOperand HiOps[3] = { LHSH, RHSH };
1083 if (N->getOpcode() == ISD::ADDC) {
1084 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1085 HiOps[2] = Lo.getValue(1);
1086 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1088 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1089 HiOps[2] = Lo.getValue(1);
1090 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1093 // Legalized the flag result - switch anything that used the old flag to
1095 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1098 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1099 SDOperand &Lo, SDOperand &Hi) {
1100 // Expand the subcomponents.
1101 SDOperand LHSL, LHSH, RHSL, RHSH;
1102 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1103 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1104 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1105 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1106 SDOperand HiOps[3] = { LHSH, RHSH };
1108 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1109 HiOps[2] = Lo.getValue(1);
1110 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1112 // Legalized the flag result - switch anything that used the old flag to
1114 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1117 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1118 SDOperand &Lo, SDOperand &Hi) {
1119 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1120 SDOperand Op = N->getOperand(0);
1121 if (Op.getValueType().bitsLE(NVT)) {
1122 // The low part is any extension of the input (which degenerates to a copy).
1123 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1124 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1126 // For example, extension of an i48 to an i64. The operand type necessarily
1127 // promotes to the result type, so will end up being expanded too.
1128 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1129 "Only know how to promote this result!");
1130 SDOperand Res = GetPromotedInteger(Op);
1131 assert(Res.getValueType() == N->getValueType(0) &&
1132 "Operand over promoted?");
1133 // Split the promoted operand. This will simplify when it is expanded.
1134 SplitInteger(Res, Lo, Hi);
1138 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1139 SDOperand &Lo, SDOperand &Hi) {
1140 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1141 MVT NVT = Lo.getValueType();
1142 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1143 unsigned NVTBits = NVT.getSizeInBits();
1144 unsigned EVTBits = EVT.getSizeInBits();
1146 if (NVTBits < EVTBits) {
1147 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1148 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1150 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1151 // The high part replicates the sign bit of Lo, make it explicit.
1152 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1153 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1157 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1158 SDOperand &Lo, SDOperand &Hi) {
1159 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1160 MVT NVT = Lo.getValueType();
1161 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1162 unsigned NVTBits = NVT.getSizeInBits();
1163 unsigned EVTBits = EVT.getSizeInBits();
1165 if (NVTBits < EVTBits) {
1166 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1167 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1169 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1170 // The high part must be zero, make it explicit.
1171 Hi = DAG.getConstant(0, NVT);
1175 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1176 SDOperand &Lo, SDOperand &Hi) {
1177 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1178 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1179 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1182 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1183 SDOperand &Lo, SDOperand &Hi) {
1184 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1185 unsigned NBitWidth = NVT.getSizeInBits();
1186 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1187 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1188 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1191 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1192 SDOperand &Lo, SDOperand &Hi) {
1193 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1194 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1195 MVT NVT = Lo.getValueType();
1197 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1198 DAG.getConstant(0, NVT), ISD::SETNE);
1200 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1201 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1203 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1204 DAG.getNode(ISD::ADD, NVT, LoLZ,
1205 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1206 Hi = DAG.getConstant(0, NVT);
1209 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1210 SDOperand &Lo, SDOperand &Hi) {
1211 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1212 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1213 MVT NVT = Lo.getValueType();
1214 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1215 DAG.getNode(ISD::CTPOP, NVT, Hi));
1216 Hi = DAG.getConstant(0, NVT);
1219 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1220 SDOperand &Lo, SDOperand &Hi) {
1221 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1222 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1223 MVT NVT = Lo.getValueType();
1225 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1226 DAG.getConstant(0, NVT), ISD::SETNE);
1228 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1229 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1231 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1232 DAG.getNode(ISD::ADD, NVT, HiLZ,
1233 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1234 Hi = DAG.getConstant(0, NVT);
1237 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
1239 MVT VT = N->getValueType(0);
1240 SDOperand Op = N->getOperand(0);
1241 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1243 if (VT == MVT::i32) {
1244 if (Op.getValueType() == MVT::f32)
1245 LC = RTLIB::FPTOSINT_F32_I32;
1246 else if (Op.getValueType() == MVT::f64)
1247 LC = RTLIB::FPTOSINT_F64_I32;
1248 else if (Op.getValueType() == MVT::f80)
1249 LC = RTLIB::FPTOSINT_F80_I32;
1250 else if (Op.getValueType() == MVT::ppcf128)
1251 LC = RTLIB::FPTOSINT_PPCF128_I32;
1252 } else if (VT == MVT::i64) {
1253 if (Op.getValueType() == MVT::f32)
1254 LC = RTLIB::FPTOSINT_F32_I64;
1255 else if (Op.getValueType() == MVT::f64)
1256 LC = RTLIB::FPTOSINT_F64_I64;
1257 else if (Op.getValueType() == MVT::f80)
1258 LC = RTLIB::FPTOSINT_F80_I64;
1259 else if (Op.getValueType() == MVT::ppcf128)
1260 LC = RTLIB::FPTOSINT_PPCF128_I64;
1261 } else if (VT == MVT::i128) {
1262 if (Op.getValueType() == MVT::f32)
1263 LC = RTLIB::FPTOSINT_F32_I128;
1264 else if (Op.getValueType() == MVT::f64)
1265 LC = RTLIB::FPTOSINT_F64_I128;
1266 else if (Op.getValueType() == MVT::f80)
1267 LC = RTLIB::FPTOSINT_F80_I128;
1268 else if (Op.getValueType() == MVT::ppcf128)
1269 LC = RTLIB::FPTOSINT_PPCF128_I128;
1271 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1272 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1275 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
1277 MVT VT = N->getValueType(0);
1278 SDOperand Op = N->getOperand(0);
1279 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1280 if (VT == MVT::i32) {
1281 if (Op.getValueType() == MVT::f32)
1282 LC = RTLIB::FPTOUINT_F32_I32;
1283 else if (Op.getValueType() == MVT::f64)
1284 LC = RTLIB::FPTOUINT_F64_I32;
1285 else if (Op.getValueType() == MVT::f80)
1286 LC = RTLIB::FPTOUINT_F80_I32;
1287 else if (Op.getValueType() == MVT::ppcf128)
1288 LC = RTLIB::FPTOUINT_PPCF128_I32;
1289 } else if (VT == MVT::i64) {
1290 if (Op.getValueType() == MVT::f32)
1291 LC = RTLIB::FPTOUINT_F32_I64;
1292 else if (Op.getValueType() == MVT::f64)
1293 LC = RTLIB::FPTOUINT_F64_I64;
1294 else if (Op.getValueType() == MVT::f80)
1295 LC = RTLIB::FPTOUINT_F80_I64;
1296 else if (Op.getValueType() == MVT::ppcf128)
1297 LC = RTLIB::FPTOUINT_PPCF128_I64;
1298 } else if (VT == MVT::i128) {
1299 if (Op.getValueType() == MVT::f32)
1300 LC = RTLIB::FPTOUINT_F32_I128;
1301 else if (Op.getValueType() == MVT::f64)
1302 LC = RTLIB::FPTOUINT_F64_I128;
1303 else if (Op.getValueType() == MVT::f80)
1304 LC = RTLIB::FPTOUINT_F80_I128;
1305 else if (Op.getValueType() == MVT::ppcf128)
1306 LC = RTLIB::FPTOUINT_PPCF128_I128;
1308 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1309 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1312 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1313 SDOperand &Lo, SDOperand &Hi) {
1314 if (ISD::isNormalLoad(N)) {
1315 ExpandRes_NormalLoad(N, Lo, Hi);
1319 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1321 MVT VT = N->getValueType(0);
1322 MVT NVT = TLI.getTypeToTransformTo(VT);
1323 SDOperand Ch = N->getChain();
1324 SDOperand Ptr = N->getBasePtr();
1325 ISD::LoadExtType ExtType = N->getExtensionType();
1326 int SVOffset = N->getSrcValueOffset();
1327 unsigned Alignment = N->getAlignment();
1328 bool isVolatile = N->isVolatile();
1330 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1332 if (N->getMemoryVT().bitsLE(NVT)) {
1333 MVT EVT = N->getMemoryVT();
1335 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1336 isVolatile, Alignment);
1338 // Remember the chain.
1339 Ch = Lo.getValue(1);
1341 if (ExtType == ISD::SEXTLOAD) {
1342 // The high part is obtained by SRA'ing all but one of the bits of the
1344 unsigned LoSize = Lo.getValueType().getSizeInBits();
1345 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1346 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1347 } else if (ExtType == ISD::ZEXTLOAD) {
1348 // The high part is just a zero.
1349 Hi = DAG.getConstant(0, NVT);
1351 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1352 // The high part is undefined.
1353 Hi = DAG.getNode(ISD::UNDEF, NVT);
1355 } else if (TLI.isLittleEndian()) {
1356 // Little-endian - low bits are at low addresses.
1357 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1358 isVolatile, Alignment);
1360 unsigned ExcessBits =
1361 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1362 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1364 // Increment the pointer to the other half.
1365 unsigned IncrementSize = NVT.getSizeInBits()/8;
1366 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1367 DAG.getIntPtrConstant(IncrementSize));
1368 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1369 SVOffset+IncrementSize, NEVT,
1370 isVolatile, MinAlign(Alignment, IncrementSize));
1372 // Build a factor node to remember that this load is independent of the
1374 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1377 // Big-endian - high bits are at low addresses. Favor aligned loads at
1378 // the cost of some bit-fiddling.
1379 MVT EVT = N->getMemoryVT();
1380 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1381 unsigned IncrementSize = NVT.getSizeInBits()/8;
1382 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1384 // Load both the high bits and maybe some of the low bits.
1385 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1386 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1387 isVolatile, Alignment);
1389 // Increment the pointer to the other half.
1390 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1391 DAG.getIntPtrConstant(IncrementSize));
1392 // Load the rest of the low bits.
1393 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1394 SVOffset+IncrementSize,
1395 MVT::getIntegerVT(ExcessBits),
1396 isVolatile, MinAlign(Alignment, IncrementSize));
1398 // Build a factor node to remember that this load is independent of the
1400 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1403 if (ExcessBits < NVT.getSizeInBits()) {
1404 // Transfer low bits from the bottom of Hi to the top of Lo.
1405 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1406 DAG.getNode(ISD::SHL, NVT, Hi,
1407 DAG.getConstant(ExcessBits,
1408 TLI.getShiftAmountTy())));
1409 // Move high bits to the right position in Hi.
1410 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1411 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1412 TLI.getShiftAmountTy()));
1416 // Legalized the chain result - switch anything that used the old chain to
1418 ReplaceValueWith(SDOperand(N, 1), Ch);
1421 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1422 SDOperand &Lo, SDOperand &Hi) {
1423 SDOperand LL, LH, RL, RH;
1424 GetExpandedInteger(N->getOperand(0), LL, LH);
1425 GetExpandedInteger(N->getOperand(1), RL, RH);
1426 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1427 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1430 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1431 SDOperand &Lo, SDOperand &Hi) {
1432 MVT VT = N->getValueType(0);
1433 MVT NVT = TLI.getTypeToTransformTo(VT);
1435 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1436 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1437 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1438 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1439 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1440 SDOperand LL, LH, RL, RH;
1441 GetExpandedInteger(N->getOperand(0), LL, LH);
1442 GetExpandedInteger(N->getOperand(1), RL, RH);
1443 unsigned OuterBitSize = VT.getSizeInBits();
1444 unsigned InnerBitSize = NVT.getSizeInBits();
1445 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1446 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1448 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1449 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1450 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1451 // The inputs are both zero-extended.
1453 // We can emit a umul_lohi.
1454 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1455 Hi = SDOperand(Lo.Val, 1);
1459 // We can emit a mulhu+mul.
1460 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1461 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1465 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1466 // The input values are both sign-extended.
1468 // We can emit a smul_lohi.
1469 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1470 Hi = SDOperand(Lo.Val, 1);
1474 // We can emit a mulhs+mul.
1475 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1476 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1481 // Lo,Hi = umul LHS, RHS.
1482 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1483 DAG.getVTList(NVT, NVT), LL, RL);
1485 Hi = UMulLOHI.getValue(1);
1486 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1487 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1488 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1489 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1493 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1494 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1495 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1496 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1497 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1498 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1503 // If nothing else, we can make a libcall.
1504 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1506 LC = RTLIB::MUL_I32;
1507 else if (VT == MVT::i64)
1508 LC = RTLIB::MUL_I64;
1509 else if (VT == MVT::i128)
1510 LC = RTLIB::MUL_I128;
1511 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1513 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1514 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1517 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1518 SDOperand &Lo, SDOperand &Hi) {
1519 MVT VT = N->getValueType(0);
1521 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1523 LC = RTLIB::SDIV_I32;
1524 else if (VT == MVT::i64)
1525 LC = RTLIB::SDIV_I64;
1526 else if (VT == MVT::i128)
1527 LC = RTLIB::SDIV_I128;
1528 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1530 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1531 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1534 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1535 SDOperand &Lo, SDOperand &Hi) {
1536 MVT VT = N->getValueType(0);
1538 // If we can emit an efficient shift operation, do so now. Check to see if
1539 // the RHS is a constant.
1540 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1541 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1543 // If we can determine that the high bit of the shift is zero or one, even if
1544 // the low bits are variable, emit this shift in an optimized form.
1545 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1548 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1550 if (N->getOpcode() == ISD::SHL) {
1551 PartsOpc = ISD::SHL_PARTS;
1552 } else if (N->getOpcode() == ISD::SRL) {
1553 PartsOpc = ISD::SRL_PARTS;
1555 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1556 PartsOpc = ISD::SRA_PARTS;
1559 // Next check to see if the target supports this SHL_PARTS operation or if it
1560 // will custom expand it.
1561 MVT NVT = TLI.getTypeToTransformTo(VT);
1562 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1563 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1564 Action == TargetLowering::Custom) {
1565 // Expand the subcomponents.
1566 SDOperand LHSL, LHSH;
1567 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1569 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1570 MVT VT = LHSL.getValueType();
1571 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1572 Hi = Lo.getValue(1);
1576 // Otherwise, emit a libcall.
1577 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1579 if (N->getOpcode() == ISD::SHL) {
1580 isSigned = false; /*sign irrelevant*/
1582 LC = RTLIB::SHL_I32;
1583 else if (VT == MVT::i64)
1584 LC = RTLIB::SHL_I64;
1585 else if (VT == MVT::i128)
1586 LC = RTLIB::SHL_I128;
1587 } else if (N->getOpcode() == ISD::SRL) {
1590 LC = RTLIB::SRL_I32;
1591 else if (VT == MVT::i64)
1592 LC = RTLIB::SRL_I64;
1593 else if (VT == MVT::i128)
1594 LC = RTLIB::SRL_I128;
1596 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1599 LC = RTLIB::SRA_I32;
1600 else if (VT == MVT::i64)
1601 LC = RTLIB::SRA_I64;
1602 else if (VT == MVT::i128)
1603 LC = RTLIB::SRA_I128;
1605 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1607 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1608 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1611 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1612 SDOperand &Lo, SDOperand &Hi) {
1613 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1614 SDOperand Op = N->getOperand(0);
1615 if (Op.getValueType().bitsLE(NVT)) {
1616 // The low part is sign extension of the input (which degenerates to a copy).
1617 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1618 // The high part is obtained by SRA'ing all but one of the bits of low part.
1619 unsigned LoSize = NVT.getSizeInBits();
1620 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1621 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1623 // For example, extension of an i48 to an i64. The operand type necessarily
1624 // promotes to the result type, so will end up being expanded too.
1625 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1626 "Only know how to promote this result!");
1627 SDOperand Res = GetPromotedInteger(Op);
1628 assert(Res.getValueType() == N->getValueType(0) &&
1629 "Operand over promoted?");
1630 // Split the promoted operand. This will simplify when it is expanded.
1631 SplitInteger(Res, Lo, Hi);
1632 unsigned ExcessBits =
1633 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1634 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1635 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1639 void DAGTypeLegalizer::
1640 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1641 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1642 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1644 if (EVT.bitsLE(Lo.getValueType())) {
1645 // sext_inreg the low part if needed.
1646 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1649 // The high part gets the sign extension from the lo-part. This handles
1650 // things like sextinreg V:i64 from i8.
1651 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1652 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1653 TLI.getShiftAmountTy()));
1655 // For example, extension of an i48 to an i64. Leave the low part alone,
1656 // sext_inreg the high part.
1657 unsigned ExcessBits =
1658 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1659 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1660 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1664 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1665 SDOperand &Lo, SDOperand &Hi) {
1666 MVT VT = N->getValueType(0);
1668 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1670 LC = RTLIB::SREM_I32;
1671 else if (VT == MVT::i64)
1672 LC = RTLIB::SREM_I64;
1673 else if (VT == MVT::i128)
1674 LC = RTLIB::SREM_I128;
1675 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1677 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1678 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1681 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1682 SDOperand &Lo, SDOperand &Hi) {
1683 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1684 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1685 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1686 DAG.getConstant(NVT.getSizeInBits(),
1687 TLI.getShiftAmountTy()));
1688 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1691 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1692 SDOperand &Lo, SDOperand &Hi) {
1693 MVT VT = N->getValueType(0);
1695 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1697 LC = RTLIB::UDIV_I32;
1698 else if (VT == MVT::i64)
1699 LC = RTLIB::UDIV_I64;
1700 else if (VT == MVT::i128)
1701 LC = RTLIB::UDIV_I128;
1702 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1704 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1705 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1708 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1709 SDOperand &Lo, SDOperand &Hi) {
1710 MVT VT = N->getValueType(0);
1712 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1714 LC = RTLIB::UREM_I32;
1715 else if (VT == MVT::i64)
1716 LC = RTLIB::UREM_I64;
1717 else if (VT == MVT::i128)
1718 LC = RTLIB::UREM_I128;
1719 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1721 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1722 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1725 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1726 SDOperand &Lo, SDOperand &Hi) {
1727 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1728 SDOperand Op = N->getOperand(0);
1729 if (Op.getValueType().bitsLE(NVT)) {
1730 // The low part is zero extension of the input (which degenerates to a copy).
1731 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1732 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1734 // For example, extension of an i48 to an i64. The operand type necessarily
1735 // promotes to the result type, so will end up being expanded too.
1736 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1737 "Only know how to promote this result!");
1738 SDOperand Res = GetPromotedInteger(Op);
1739 assert(Res.getValueType() == N->getValueType(0) &&
1740 "Operand over promoted?");
1741 // Split the promoted operand. This will simplify when it is expanded.
1742 SplitInteger(Res, Lo, Hi);
1743 unsigned ExcessBits =
1744 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1745 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1750 //===----------------------------------------------------------------------===//
1751 // Integer Operand Expansion
1752 //===----------------------------------------------------------------------===//
1754 /// ExpandIntegerOperand - This method is called when the specified operand of
1755 /// the specified node is found to need expansion. At this point, all of the
1756 /// result types of the node are known to be legal, but other operands of the
1757 /// node may need promotion or expansion as well as the specified one.
1758 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1759 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1760 SDOperand Res = SDOperand();
1762 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1763 == TargetLowering::Custom)
1764 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG);
1767 switch (N->getOpcode()) {
1770 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1771 N->dump(&DAG); cerr << "\n";
1773 assert(0 && "Do not know how to expand this operator's operand!");
1776 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1777 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1778 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1780 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1781 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1782 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1783 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1784 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1786 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1787 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1791 // If the result is null, the sub-method took care of registering results etc.
1792 if (!Res.Val) return false;
1793 // If the result is N, the sub-method updated N in place. Check to see if any
1794 // operands are new, and if so, mark them.
1796 // Mark N as new and remark N and its operands. This allows us to correctly
1797 // revisit N if it needs another step of expansion and allows us to visit
1798 // any new operands to N.
1803 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1804 "Invalid operand expansion");
1806 ReplaceValueWith(SDOperand(N, 0), Res);
1810 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1811 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1812 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS,
1814 ISD::CondCode &CCCode) {
1815 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1816 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1817 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1819 MVT VT = NewLHS.getValueType();
1821 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1822 if (RHSLo == RHSHi) {
1823 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1824 if (RHSCST->isAllOnesValue()) {
1825 // Equality comparison to -1.
1826 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1833 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1834 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1835 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1836 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1840 // If this is a comparison of the sign bit, just look at the top part.
1842 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1843 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1844 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1850 // FIXME: This generated code sucks.
1851 ISD::CondCode LowCC;
1853 default: assert(0 && "Unknown integer setcc!");
1855 case ISD::SETULT: LowCC = ISD::SETULT; break;
1857 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1859 case ISD::SETULE: LowCC = ISD::SETULE; break;
1861 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1864 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1865 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1866 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1868 // NOTE: on targets without efficient SELECT of bools, we can always use
1869 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1870 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1871 SDOperand Tmp1, Tmp2;
1872 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1873 false, DagCombineInfo);
1875 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1876 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1877 CCCode, false, DagCombineInfo);
1879 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1880 DAG.getCondCode(CCCode));
1882 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1883 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1884 if ((Tmp1C && Tmp1C->isNullValue()) ||
1885 (Tmp2C && Tmp2C->isNullValue() &&
1886 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1887 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1888 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1889 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1890 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1891 // low part is known false, returns high part.
1892 // For LE / GE, if high part is known false, ignore the low part.
1893 // For LT / GT, if high part is known true, ignore the low part.
1895 NewRHS = SDOperand();
1899 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1900 ISD::SETEQ, false, DagCombineInfo);
1902 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1904 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1905 NewLHS, Tmp1, Tmp2);
1906 NewRHS = SDOperand();
1909 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1910 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1911 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1912 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1914 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1915 // against zero to select between true and false values.
1916 if (NewRHS.Val == 0) {
1917 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1918 CCCode = ISD::SETNE;
1921 // Update N to have the operands specified.
1922 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1923 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1927 SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1928 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1929 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1930 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1932 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1933 // against zero to select between true and false values.
1934 if (NewRHS.Val == 0) {
1935 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1936 CCCode = ISD::SETNE;
1939 // Update N to have the operands specified.
1940 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1941 N->getOperand(2), N->getOperand(3),
1942 DAG.getCondCode(CCCode));
1945 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1946 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1947 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1948 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1950 // If ExpandSetCCOperands returned a scalar, use it.
1951 if (NewRHS.Val == 0) {
1952 assert(NewLHS.getValueType() == N->getValueType(0) &&
1953 "Unexpected setcc expansion!");
1957 // Otherwise, update N to have the operands specified.
1958 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1959 DAG.getCondCode(CCCode));
1962 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
1963 SDOperand Op = N->getOperand(0);
1964 MVT SrcVT = Op.getValueType();
1965 MVT DstVT = N->getValueType(0);
1967 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1968 if (SrcVT == MVT::i32) {
1969 if (DstVT == MVT::f32)
1970 LC = RTLIB::SINTTOFP_I32_F32;
1971 else if (DstVT == MVT::f64)
1972 LC = RTLIB::SINTTOFP_I32_F64;
1973 else if (DstVT == MVT::f80)
1974 LC = RTLIB::SINTTOFP_I32_F80;
1975 else if (DstVT == MVT::ppcf128)
1976 LC = RTLIB::SINTTOFP_I32_PPCF128;
1977 } else if (SrcVT == MVT::i64) {
1978 if (DstVT == MVT::f32)
1979 LC = RTLIB::SINTTOFP_I64_F32;
1980 else if (DstVT == MVT::f64)
1981 LC = RTLIB::SINTTOFP_I64_F64;
1982 else if (DstVT == MVT::f80)
1983 LC = RTLIB::SINTTOFP_I64_F80;
1984 else if (DstVT == MVT::ppcf128)
1985 LC = RTLIB::SINTTOFP_I64_PPCF128;
1986 } else if (SrcVT == MVT::i128) {
1987 if (DstVT == MVT::f32)
1988 LC = RTLIB::SINTTOFP_I128_F32;
1989 else if (DstVT == MVT::f64)
1990 LC = RTLIB::SINTTOFP_I128_F64;
1991 else if (DstVT == MVT::f80)
1992 LC = RTLIB::SINTTOFP_I128_F80;
1993 else if (DstVT == MVT::ppcf128)
1994 LC = RTLIB::SINTTOFP_I128_PPCF128;
1996 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1997 "Don't know how to expand this SINT_TO_FP!");
1999 return MakeLibCall(LC, DstVT, &Op, 1, true);
2002 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2003 if (ISD::isNormalStore(N))
2004 return ExpandOp_NormalStore(N, OpNo);
2006 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2007 assert(OpNo == 1 && "Can only expand the stored value so far");
2009 MVT VT = N->getOperand(1).getValueType();
2010 MVT NVT = TLI.getTypeToTransformTo(VT);
2011 SDOperand Ch = N->getChain();
2012 SDOperand Ptr = N->getBasePtr();
2013 int SVOffset = N->getSrcValueOffset();
2014 unsigned Alignment = N->getAlignment();
2015 bool isVolatile = N->isVolatile();
2018 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2020 if (N->getMemoryVT().bitsLE(NVT)) {
2021 GetExpandedInteger(N->getValue(), Lo, Hi);
2022 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2023 N->getMemoryVT(), isVolatile, Alignment);
2024 } else if (TLI.isLittleEndian()) {
2025 // Little-endian - low bits are at low addresses.
2026 GetExpandedInteger(N->getValue(), Lo, Hi);
2028 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2029 isVolatile, Alignment);
2031 unsigned ExcessBits =
2032 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2033 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2035 // Increment the pointer to the other half.
2036 unsigned IncrementSize = NVT.getSizeInBits()/8;
2037 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2038 DAG.getIntPtrConstant(IncrementSize));
2039 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2040 SVOffset+IncrementSize, NEVT,
2041 isVolatile, MinAlign(Alignment, IncrementSize));
2042 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2044 // Big-endian - high bits are at low addresses. Favor aligned stores at
2045 // the cost of some bit-fiddling.
2046 GetExpandedInteger(N->getValue(), Lo, Hi);
2048 MVT EVT = N->getMemoryVT();
2049 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2050 unsigned IncrementSize = NVT.getSizeInBits()/8;
2051 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2052 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2054 if (ExcessBits < NVT.getSizeInBits()) {
2055 // Transfer high bits from the top of Lo to the bottom of Hi.
2056 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2057 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2058 TLI.getShiftAmountTy()));
2059 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2060 DAG.getNode(ISD::SRL, NVT, Lo,
2061 DAG.getConstant(ExcessBits,
2062 TLI.getShiftAmountTy())));
2065 // Store both the high bits and maybe some of the low bits.
2066 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2067 SVOffset, HiVT, isVolatile, Alignment);
2069 // Increment the pointer to the other half.
2070 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2071 DAG.getIntPtrConstant(IncrementSize));
2072 // Store the lowest ExcessBits bits in the second half.
2073 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2074 SVOffset+IncrementSize,
2075 MVT::getIntegerVT(ExcessBits),
2076 isVolatile, MinAlign(Alignment, IncrementSize));
2077 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2081 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2083 GetExpandedInteger(N->getOperand(0), InL, InH);
2084 // Just truncate the low part of the source.
2085 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2088 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2089 SDOperand Op = N->getOperand(0);
2090 MVT SrcVT = Op.getValueType();
2091 MVT DstVT = N->getValueType(0);
2093 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2094 // Do a signed conversion then adjust the result.
2095 SDOperand SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2096 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2098 // The result of the signed conversion needs adjusting if the 'sign bit' of
2099 // the incoming integer was set. To handle this, we dynamically test to see
2100 // if it is set, and, if so, add a fudge factor.
2102 const uint64_t F32TwoE32 = 0x4F800000ULL;
2103 const uint64_t F32TwoE64 = 0x5F800000ULL;
2104 const uint64_t F32TwoE128 = 0x7F800000ULL;
2107 if (SrcVT == MVT::i32)
2108 FF = APInt(32, F32TwoE32);
2109 else if (SrcVT == MVT::i64)
2110 FF = APInt(32, F32TwoE64);
2111 else if (SrcVT == MVT::i128)
2112 FF = APInt(32, F32TwoE128);
2114 assert(false && "Unsupported UINT_TO_FP!");
2116 // Check whether the sign bit is set.
2118 GetExpandedInteger(Op, Lo, Hi);
2119 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2120 DAG.getConstant(0, Hi.getValueType()),
2123 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2124 SDOperand FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2125 TLI.getPointerTy());
2127 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2128 SDOperand Zero = DAG.getIntPtrConstant(0);
2129 SDOperand Four = DAG.getIntPtrConstant(4);
2130 if (TLI.isBigEndian()) std::swap(Zero, Four);
2131 SDOperand Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2133 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2135 // Load the value out, extending it from f32 to the destination float type.
2136 // FIXME: Avoid the extend by constructing the right constant pool?
2137 SDOperand Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2138 FudgePtr, NULL, 0, MVT::f32);
2139 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2142 // Otherwise, use a libcall.
2143 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2144 if (SrcVT == MVT::i32) {
2145 if (DstVT == MVT::f32)
2146 LC = RTLIB::UINTTOFP_I32_F32;
2147 else if (DstVT == MVT::f64)
2148 LC = RTLIB::UINTTOFP_I32_F64;
2149 else if (DstVT == MVT::f80)
2150 LC = RTLIB::UINTTOFP_I32_F80;
2151 else if (DstVT == MVT::ppcf128)
2152 LC = RTLIB::UINTTOFP_I32_PPCF128;
2153 } else if (SrcVT == MVT::i64) {
2154 if (DstVT == MVT::f32)
2155 LC = RTLIB::UINTTOFP_I64_F32;
2156 else if (DstVT == MVT::f64)
2157 LC = RTLIB::UINTTOFP_I64_F64;
2158 else if (DstVT == MVT::f80)
2159 LC = RTLIB::UINTTOFP_I64_F80;
2160 else if (DstVT == MVT::ppcf128)
2161 LC = RTLIB::UINTTOFP_I64_PPCF128;
2162 } else if (SrcVT == MVT::i128) {
2163 if (DstVT == MVT::f32)
2164 LC = RTLIB::UINTTOFP_I128_F32;
2165 else if (DstVT == MVT::f64)
2166 LC = RTLIB::UINTTOFP_I128_F64;
2167 else if (DstVT == MVT::f80)
2168 LC = RTLIB::UINTTOFP_I128_F80;
2169 else if (DstVT == MVT::ppcf128)
2170 LC = RTLIB::UINTTOFP_I128_PPCF128;
2172 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2173 "Don't know how to expand this UINT_TO_FP!");
2175 return MakeLibCall(LC, DstVT, &Op, 1, true);