1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
70 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
71 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
72 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
73 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
74 case ISD::SIGN_EXTEND_INREG:
75 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
77 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
78 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
79 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
80 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
82 case ISD::EXTRACT_SUBVECTOR:
83 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
84 case ISD::VECTOR_SHUFFLE:
85 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
86 case ISD::INSERT_VECTOR_ELT:
87 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
88 case ISD::BUILD_VECTOR:
89 Res = PromoteIntRes_BUILD_VECTOR(N); break;
90 case ISD::SCALAR_TO_VECTOR:
91 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
92 case ISD::CONCAT_VECTORS:
93 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
95 case ISD::SIGN_EXTEND:
96 case ISD::ZERO_EXTEND:
97 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
100 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
102 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
109 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
112 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
115 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
118 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
120 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
122 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
124 case ISD::ATOMIC_LOAD:
125 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
127 case ISD::ATOMIC_LOAD_ADD:
128 case ISD::ATOMIC_LOAD_SUB:
129 case ISD::ATOMIC_LOAD_AND:
130 case ISD::ATOMIC_LOAD_OR:
131 case ISD::ATOMIC_LOAD_XOR:
132 case ISD::ATOMIC_LOAD_NAND:
133 case ISD::ATOMIC_LOAD_MIN:
134 case ISD::ATOMIC_LOAD_MAX:
135 case ISD::ATOMIC_LOAD_UMIN:
136 case ISD::ATOMIC_LOAD_UMAX:
137 case ISD::ATOMIC_SWAP:
138 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
140 case ISD::ATOMIC_CMP_SWAP:
141 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
142 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
146 // If the result is null then the sub-method took care of registering it.
148 SetPromotedInteger(SDValue(N, ResNo), Res);
151 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
154 return GetPromotedInteger(Op);
157 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
158 // Sign-extend the new bits, and continue the assertion.
159 SDValue Op = SExtPromotedInteger(N->getOperand(0));
160 return DAG.getNode(ISD::AssertSext, SDLoc(N),
161 Op.getValueType(), Op, N->getOperand(1));
164 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
165 // Zero the new bits, and continue the assertion.
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
167 return DAG.getNode(ISD::AssertZext, SDLoc(N),
168 Op.getValueType(), Op, N->getOperand(1));
171 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
172 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
173 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
174 N->getMemoryVT(), ResVT,
175 N->getChain(), N->getBasePtr(),
176 N->getMemOperand(), N->getOrdering(),
178 // Legalized the chain result - switch anything that used the old chain to
180 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
184 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
185 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
186 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
188 N->getChain(), N->getBasePtr(),
189 Op2, N->getMemOperand(), N->getOrdering(),
191 // Legalized the chain result - switch anything that used the old chain to
193 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
197 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
200 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
201 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
202 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
204 // Only use the result of getSetCCResultType if it is legal,
205 // otherwise just use the promoted result type (NVT).
206 if (!TLI.isTypeLegal(SVT))
209 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
210 SDValue Res = DAG.getAtomicCmpSwap(
211 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
212 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
213 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
215 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
216 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
217 return Res.getValue(1);
220 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
221 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
223 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
224 SDValue Res = DAG.getAtomicCmpSwap(
225 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
227 N->getFailureOrdering(), N->getSynchScope());
228 // Legalized the chain result - switch anything that used the old chain to
230 unsigned ChainOp = N->getNumValues() - 1;
231 ReplaceValueWith(SDValue(N, ChainOp), Res.getValue(ChainOp));
235 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
236 SDValue InOp = N->getOperand(0);
237 EVT InVT = InOp.getValueType();
238 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
239 EVT OutVT = N->getValueType(0);
240 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
243 switch (getTypeAction(InVT)) {
244 case TargetLowering::TypeLegal:
246 case TargetLowering::TypePromoteInteger:
247 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
248 // The input promotes to the same size. Convert the promoted value.
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
251 case TargetLowering::TypeSoftenFloat:
252 // Promote the integer operand by hand.
253 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
254 case TargetLowering::TypeExpandInteger:
255 case TargetLowering::TypeExpandFloat:
257 case TargetLowering::TypeScalarizeVector:
258 // Convert the element to an integer and promote it by hand.
259 if (!NOutVT.isVector())
260 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
261 BitConvertToInteger(GetScalarizedVector(InOp)));
263 case TargetLowering::TypeSplitVector: {
264 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
265 // pieces of the input into integers and reassemble in the final type.
267 GetSplitVector(N->getOperand(0), Lo, Hi);
268 Lo = BitConvertToInteger(Lo);
269 Hi = BitConvertToInteger(Hi);
271 if (TLI.isBigEndian())
274 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
275 EVT::getIntegerVT(*DAG.getContext(),
276 NOutVT.getSizeInBits()),
277 JoinIntegers(Lo, Hi));
278 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
280 case TargetLowering::TypeWidenVector:
281 // The input is widened to the same size. Convert to the widened value.
282 // Make sure that the outgoing value is not a vector, because this would
283 // make us bitcast between two vectors which are legalized in different ways.
284 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
285 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
288 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
289 CreateStackStoreLoad(InOp, OutVT));
292 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
293 SDValue Op = GetPromotedInteger(N->getOperand(0));
294 EVT OVT = N->getValueType(0);
295 EVT NVT = Op.getValueType();
298 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
299 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
300 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
303 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
304 // The pair element type may be legal, or may not promote to the same type as
305 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
306 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
307 TLI.getTypeToTransformTo(*DAG.getContext(),
308 N->getValueType(0)), JoinIntegers(N->getOperand(0),
312 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
313 EVT VT = N->getValueType(0);
314 // FIXME there is no actual debug info here
316 // Zero extend things like i1, sign extend everything else. It shouldn't
317 // matter in theory which one we pick, but this tends to give better code?
318 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
319 SDValue Result = DAG.getNode(Opc, dl,
320 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
322 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
326 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
327 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
328 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
329 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
330 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
331 "can only promote integers");
332 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
333 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
334 N->getOperand(1), N->getOperand(2),
335 N->getOperand(3), N->getOperand(4), CvtCode);
338 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
339 // Zero extend to the promoted type and do the count there.
340 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
342 EVT OVT = N->getValueType(0);
343 EVT NVT = Op.getValueType();
344 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
345 // Subtract off the extra leading bits in the bigger type.
346 return DAG.getNode(ISD::SUB, dl, NVT, Op,
347 DAG.getConstant(NVT.getSizeInBits() -
348 OVT.getSizeInBits(), NVT));
351 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
352 // Zero extend to the promoted type and do the count there.
353 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
354 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
357 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
358 SDValue Op = GetPromotedInteger(N->getOperand(0));
359 EVT OVT = N->getValueType(0);
360 EVT NVT = Op.getValueType();
362 if (N->getOpcode() == ISD::CTTZ) {
363 // The count is the same in the promoted type except if the original
364 // value was zero. This can be handled by setting the bit just off
365 // the top of the original type.
366 APInt TopBit(NVT.getSizeInBits(), 0);
367 TopBit.setBit(OVT.getSizeInBits());
368 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
370 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
373 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
375 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
376 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
380 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
381 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
382 unsigned NewOpc = N->getOpcode();
385 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
386 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
387 // and SINT conversions are Custom, there is no way to tell which is
388 // preferable. We choose SINT because that's the right thing on PPC.)
389 if (N->getOpcode() == ISD::FP_TO_UINT &&
390 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
391 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
392 NewOpc = ISD::FP_TO_SINT;
394 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
396 // Assert that the converted value fits in the original type. If it doesn't
397 // (eg: because the value being converted is too big), then the result of the
398 // original operation was undefined anyway, so the assert is still correct.
399 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
400 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
401 DAG.getValueType(N->getValueType(0).getScalarType()));
404 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
405 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
408 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
410 return DAG.getNode(ISD::AssertZext, dl,
411 NVT, Res, DAG.getValueType(N->getValueType(0)));
414 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
418 if (getTypeAction(N->getOperand(0).getValueType())
419 == TargetLowering::TypePromoteInteger) {
420 SDValue Res = GetPromotedInteger(N->getOperand(0));
421 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
423 // If the result and operand types are the same after promotion, simplify
424 // to an in-register extension.
425 if (NVT == Res.getValueType()) {
426 // The high bits are not guaranteed to be anything. Insert an extend.
427 if (N->getOpcode() == ISD::SIGN_EXTEND)
428 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
429 DAG.getValueType(N->getOperand(0).getValueType()));
430 if (N->getOpcode() == ISD::ZERO_EXTEND)
431 return DAG.getZeroExtendInReg(Res, dl,
432 N->getOperand(0).getValueType().getScalarType());
433 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
438 // Otherwise, just extend the original operand all the way to the larger type.
439 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
442 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
443 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
444 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
445 ISD::LoadExtType ExtType =
446 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
448 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
449 N->getMemoryVT(), N->getMemOperand());
451 // Legalized the chain result - switch anything that used the old chain to
453 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
457 /// Promote the overflow flag of an overflowing arithmetic node.
458 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
459 // Simply change the return type of the boolean result.
460 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
461 EVT ValueVTs[] = { N->getValueType(0), NVT };
462 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
463 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
464 DAG.getVTList(ValueVTs), Ops);
466 // Modified the sum result - switch anything that used the old sum to use
468 ReplaceValueWith(SDValue(N, 0), Res);
470 return SDValue(Res.getNode(), 1);
473 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
475 return PromoteIntRes_Overflow(N);
477 // The operation overflowed iff the result in the larger type is not the
478 // sign extension of its truncation to the original type.
479 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
480 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
481 EVT OVT = N->getOperand(0).getValueType();
482 EVT NVT = LHS.getValueType();
485 // Do the arithmetic in the larger type.
486 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
487 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
489 // Calculate the overflow flag: sign extend the arithmetic result from
490 // the original type.
491 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
492 DAG.getValueType(OVT));
493 // Overflowed if and only if this is not equal to Res.
494 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
496 // Use the calculated overflow everywhere.
497 ReplaceValueWith(SDValue(N, 1), Ofl);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
503 // Sign extend the input.
504 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
505 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
506 return DAG.getNode(N->getOpcode(), SDLoc(N),
507 LHS.getValueType(), LHS, RHS);
510 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
511 SDValue LHS = GetPromotedInteger(N->getOperand(1));
512 SDValue RHS = GetPromotedInteger(N->getOperand(2));
513 return DAG.getSelect(SDLoc(N),
514 LHS.getValueType(), N->getOperand(0), LHS, RHS);
517 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
518 SDValue Mask = N->getOperand(0);
519 EVT OpTy = N->getOperand(1).getValueType();
521 // Promote all the way up to the canonical SetCC type.
522 Mask = PromoteTargetBoolean(Mask, getSetCCResultType(OpTy));
523 SDValue LHS = GetPromotedInteger(N->getOperand(1));
524 SDValue RHS = GetPromotedInteger(N->getOperand(2));
525 return DAG.getNode(ISD::VSELECT, SDLoc(N),
526 LHS.getValueType(), Mask, LHS, RHS);
529 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
530 SDValue LHS = GetPromotedInteger(N->getOperand(2));
531 SDValue RHS = GetPromotedInteger(N->getOperand(3));
532 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
533 LHS.getValueType(), N->getOperand(0),
534 N->getOperand(1), LHS, RHS, N->getOperand(4));
537 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
538 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
540 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
542 // Only use the result of getSetCCResultType if it is legal,
543 // otherwise just use the promoted result type (NVT).
544 if (!TLI.isTypeLegal(SVT))
548 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
549 "Vector compare must return a vector result!");
551 SDValue LHS = N->getOperand(0);
552 SDValue RHS = N->getOperand(1);
553 if (LHS.getValueType() != RHS.getValueType()) {
554 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
555 !LHS.getValueType().isVector())
556 LHS = GetPromotedInteger(LHS);
557 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
558 !RHS.getValueType().isVector())
559 RHS = GetPromotedInteger(RHS);
562 // Get the SETCC result using the canonical SETCC type.
563 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
566 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
567 // Convert to the expected type.
568 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
571 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
572 SDValue Res = GetPromotedInteger(N->getOperand(0));
573 SDValue Amt = N->getOperand(1);
574 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
575 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
578 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
579 SDValue Op = GetPromotedInteger(N->getOperand(0));
580 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
581 Op.getValueType(), Op, N->getOperand(1));
584 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
585 // The input may have strange things in the top bits of the registers, but
586 // these operations don't care. They may have weird bits going out, but
587 // that too is okay if they are integer operations.
588 SDValue LHS = GetPromotedInteger(N->getOperand(0));
589 SDValue RHS = GetPromotedInteger(N->getOperand(1));
590 return DAG.getNode(N->getOpcode(), SDLoc(N),
591 LHS.getValueType(), LHS, RHS);
594 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
595 // The input value must be properly sign extended.
596 SDValue Res = SExtPromotedInteger(N->getOperand(0));
597 SDValue Amt = N->getOperand(1);
598 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
599 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
602 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
603 // The input value must be properly zero extended.
604 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
605 SDValue Amt = N->getOperand(1);
606 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
607 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
610 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
611 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
613 SDValue InOp = N->getOperand(0);
616 switch (getTypeAction(InOp.getValueType())) {
617 default: llvm_unreachable("Unknown type action!");
618 case TargetLowering::TypeLegal:
619 case TargetLowering::TypeExpandInteger:
622 case TargetLowering::TypePromoteInteger:
623 Res = GetPromotedInteger(InOp);
625 case TargetLowering::TypeSplitVector:
626 EVT InVT = InOp.getValueType();
627 assert(InVT.isVector() && "Cannot split scalar types");
628 unsigned NumElts = InVT.getVectorNumElements();
629 assert(NumElts == NVT.getVectorNumElements() &&
630 "Dst and Src must have the same number of elements");
631 assert(isPowerOf2_32(NumElts) &&
632 "Promoted vector type must be a power of two");
635 GetSplitVector(InOp, EOp1, EOp2);
637 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
639 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
640 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
642 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
645 // Truncate to NVT instead of VT
646 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
649 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
651 return PromoteIntRes_Overflow(N);
653 // The operation overflowed iff the result in the larger type is not the
654 // zero extension of its truncation to the original type.
655 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
656 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
657 EVT OVT = N->getOperand(0).getValueType();
658 EVT NVT = LHS.getValueType();
661 // Do the arithmetic in the larger type.
662 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
663 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
665 // Calculate the overflow flag: zero extend the arithmetic result from
666 // the original type.
667 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
668 // Overflowed if and only if this is not equal to Res.
669 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
671 // Use the calculated overflow everywhere.
672 ReplaceValueWith(SDValue(N, 1), Ofl);
677 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
678 // Promote the overflow bit trivially.
680 return PromoteIntRes_Overflow(N);
682 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
684 EVT SmallVT = LHS.getValueType();
686 // To determine if the result overflowed in a larger type, we extend the
687 // input to the larger type, do the multiply (checking if it overflows),
688 // then also check the high bits of the result to see if overflow happened
690 if (N->getOpcode() == ISD::SMULO) {
691 LHS = SExtPromotedInteger(LHS);
692 RHS = SExtPromotedInteger(RHS);
694 LHS = ZExtPromotedInteger(LHS);
695 RHS = ZExtPromotedInteger(RHS);
697 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
698 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
700 // Overflow occurred if it occurred in the larger type, or if the high part
701 // of the result does not zero/sign-extend the low part. Check this second
702 // possibility first.
704 if (N->getOpcode() == ISD::UMULO) {
705 // Unsigned overflow occurred if the high part is non-zero.
706 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
707 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
708 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
709 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
711 // Signed overflow occurred if the high part does not sign extend the low.
712 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
713 Mul, DAG.getValueType(SmallVT));
714 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
717 // The only other way for overflow to occur is if the multiplication in the
718 // larger type itself overflowed.
719 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
720 SDValue(Mul.getNode(), 1));
722 // Use the calculated overflow everywhere.
723 ReplaceValueWith(SDValue(N, 1), Overflow);
727 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
728 // Zero extend the input.
729 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
730 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
731 return DAG.getNode(N->getOpcode(), SDLoc(N),
732 LHS.getValueType(), LHS, RHS);
735 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
736 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
737 N->getValueType(0)));
740 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
741 SDValue Chain = N->getOperand(0); // Get the chain.
742 SDValue Ptr = N->getOperand(1); // Get the pointer.
743 EVT VT = N->getValueType(0);
746 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
747 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
748 // The argument is passed as NumRegs registers of type RegVT.
750 SmallVector<SDValue, 8> Parts(NumRegs);
751 for (unsigned i = 0; i < NumRegs; ++i) {
752 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
753 N->getConstantOperandVal(3));
754 Chain = Parts[i].getValue(1);
757 // Handle endianness of the load.
758 if (TLI.isBigEndian())
759 std::reverse(Parts.begin(), Parts.end());
761 // Assemble the parts in the promoted type.
762 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
763 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
764 for (unsigned i = 1; i < NumRegs; ++i) {
765 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
766 // Shift it to the right position and "or" it in.
767 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
768 DAG.getConstant(i * RegVT.getSizeInBits(),
769 TLI.getPointerTy()));
770 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
773 // Modified the chain result - switch anything that used the old chain to
775 ReplaceValueWith(SDValue(N, 1), Chain);
780 //===----------------------------------------------------------------------===//
781 // Integer Operand Promotion
782 //===----------------------------------------------------------------------===//
784 /// PromoteIntegerOperand - This method is called when the specified operand of
785 /// the specified node is found to need promotion. At this point, all of the
786 /// result types of the node are known to be legal, but other operands of the
787 /// node may need promotion or expansion as well as the specified one.
788 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
789 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
790 SDValue Res = SDValue();
792 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
795 switch (N->getOpcode()) {
798 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
799 N->dump(&DAG); dbgs() << "\n";
801 llvm_unreachable("Do not know how to promote this operator's operand!");
803 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
804 case ISD::ATOMIC_STORE:
805 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
807 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
808 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
809 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
810 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
811 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
812 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
813 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
814 case ISD::CONVERT_RNDSAT:
815 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
816 case ISD::INSERT_VECTOR_ELT:
817 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
818 case ISD::SCALAR_TO_VECTOR:
819 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
821 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
822 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
823 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
824 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
825 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
826 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
828 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
829 case ISD::FP16_TO_FP32:
830 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
831 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
837 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
840 // If the result is null, the sub-method took care of registering results etc.
841 if (!Res.getNode()) return false;
843 // If the result is N, the sub-method updated N in place. Tell the legalizer
845 if (Res.getNode() == N)
848 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
849 "Invalid operand expansion");
851 ReplaceValueWith(SDValue(N, 0), Res);
855 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
856 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
857 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
858 ISD::CondCode CCCode) {
859 // We have to insert explicit sign or zero extends. Note that we could
860 // insert sign extends for ALL conditions, but zero extend is cheaper on
861 // many machines (an AND instead of two shifts), so prefer it.
863 default: llvm_unreachable("Unknown integer comparison!");
870 // ALL of these operations will work if we either sign or zero extend
871 // the operands (including the unsigned comparisons!). Zero extend is
872 // usually a simpler/cheaper operation, so prefer it.
873 NewLHS = ZExtPromotedInteger(NewLHS);
874 NewRHS = ZExtPromotedInteger(NewRHS);
880 NewLHS = SExtPromotedInteger(NewLHS);
881 NewRHS = SExtPromotedInteger(NewRHS);
886 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
887 SDValue Op = GetPromotedInteger(N->getOperand(0));
888 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
891 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
892 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
893 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
894 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
895 N->getOrdering(), N->getSynchScope());
898 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
899 // This should only occur in unusual situations like bitcasting to an
900 // x86_fp80, so just turn it into a store+load
901 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
904 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
905 assert(OpNo == 2 && "Don't know how to promote this operand!");
907 SDValue LHS = N->getOperand(2);
908 SDValue RHS = N->getOperand(3);
909 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
911 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
913 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
914 N->getOperand(1), LHS, RHS, N->getOperand(4)),
918 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
919 assert(OpNo == 1 && "only know how to promote condition");
921 // Promote all the way up to the canonical SetCC type.
922 EVT SVT = getSetCCResultType(MVT::Other);
923 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
925 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
926 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
927 N->getOperand(2)), 0);
930 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
931 // Since the result type is legal, the operands must promote to it.
932 EVT OVT = N->getOperand(0).getValueType();
933 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
934 SDValue Hi = GetPromotedInteger(N->getOperand(1));
935 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
938 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
939 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
940 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
943 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
944 // The vector type is legal but the element type is not. This implies
945 // that the vector is a power-of-two in length and that the element
946 // type does not have a strange size (eg: it is not i1).
947 EVT VecVT = N->getValueType(0);
948 unsigned NumElts = VecVT.getVectorNumElements();
949 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
950 "Legal vector of one illegal element?");
952 // Promote the inserted value. The type does not need to match the
953 // vector element type. Check that any extra bits introduced will be
955 assert(N->getOperand(0).getValueType().getSizeInBits() >=
956 N->getValueType(0).getVectorElementType().getSizeInBits() &&
957 "Type of inserted value narrower than vector element type!");
959 SmallVector<SDValue, 16> NewOps;
960 for (unsigned i = 0; i < NumElts; ++i)
961 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
963 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
966 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
967 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
968 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
969 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
970 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
971 "can only promote integer arguments");
972 SDValue InOp = GetPromotedInteger(N->getOperand(0));
973 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
974 N->getOperand(1), N->getOperand(2),
975 N->getOperand(3), N->getOperand(4), CvtCode);
978 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
981 // Promote the inserted value. This is valid because the type does not
982 // have to match the vector element type.
984 // Check that any extra bits introduced will be truncated away.
985 assert(N->getOperand(1).getValueType().getSizeInBits() >=
986 N->getValueType(0).getVectorElementType().getSizeInBits() &&
987 "Type of inserted value narrower than vector element type!");
988 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
989 GetPromotedInteger(N->getOperand(1)),
994 assert(OpNo == 2 && "Different operand and result vector types?");
996 // Promote the index.
997 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
998 TLI.getVectorIdxTy());
999 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1000 N->getOperand(1), Idx), 0);
1003 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1004 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1005 // the operand in place.
1006 return SDValue(DAG.UpdateNodeOperands(N,
1007 GetPromotedInteger(N->getOperand(0))), 0);
1010 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1011 assert(OpNo == 0 && "Only know how to promote the condition!");
1012 SDValue Cond = N->getOperand(0);
1013 EVT OpTy = N->getOperand(1).getValueType();
1015 // Promote all the way up to the canonical SetCC type.
1016 EVT SVT = getSetCCResultType(N->getOpcode() == ISD::SELECT ?
1017 OpTy.getScalarType() : OpTy);
1018 Cond = PromoteTargetBoolean(Cond, SVT);
1020 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1021 N->getOperand(2)), 0);
1024 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1025 assert(OpNo == 0 && "Don't know how to promote this operand!");
1027 SDValue LHS = N->getOperand(0);
1028 SDValue RHS = N->getOperand(1);
1029 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1031 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1032 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1033 N->getOperand(3), N->getOperand(4)), 0);
1036 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1037 assert(OpNo == 0 && "Don't know how to promote this operand!");
1039 SDValue LHS = N->getOperand(0);
1040 SDValue RHS = N->getOperand(1);
1041 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1043 // The CC (#2) is always legal.
1044 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1047 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1048 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1049 ZExtPromotedInteger(N->getOperand(1))), 0);
1052 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1053 SDValue Op = GetPromotedInteger(N->getOperand(0));
1055 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1056 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1057 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1060 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1061 return SDValue(DAG.UpdateNodeOperands(N,
1062 SExtPromotedInteger(N->getOperand(0))), 0);
1065 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1066 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1067 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1070 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1072 // Truncate the value and store the result.
1073 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1074 N->getMemoryVT(), N->getMemOperand());
1077 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1078 SDValue Op = GetPromotedInteger(N->getOperand(0));
1079 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1082 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1083 return SDValue(DAG.UpdateNodeOperands(N,
1084 ZExtPromotedInteger(N->getOperand(0))), 0);
1087 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1089 SDValue Op = GetPromotedInteger(N->getOperand(0));
1090 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1091 return DAG.getZeroExtendInReg(Op, dl,
1092 N->getOperand(0).getValueType().getScalarType());
1096 //===----------------------------------------------------------------------===//
1097 // Integer Result Expansion
1098 //===----------------------------------------------------------------------===//
1100 /// ExpandIntegerResult - This method is called when the specified result of the
1101 /// specified node is found to need expansion. At this point, the node may also
1102 /// have invalid operands or may have other results that need promotion, we just
1103 /// know that (at least) one result needs expansion.
1104 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1105 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1107 Lo = Hi = SDValue();
1109 // See if the target wants to custom expand this node.
1110 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1113 switch (N->getOpcode()) {
1116 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1117 N->dump(&DAG); dbgs() << "\n";
1119 llvm_unreachable("Do not know how to expand the result of this operator!");
1121 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1122 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1123 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1124 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1126 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1127 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1128 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1129 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1130 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1132 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1133 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1134 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1135 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1136 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1137 case ISD::CTLZ_ZERO_UNDEF:
1138 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1139 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1140 case ISD::CTTZ_ZERO_UNDEF:
1141 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1142 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1143 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1144 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1145 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1146 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1147 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1148 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1149 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1150 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1151 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1152 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1153 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1154 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1156 case ISD::ATOMIC_LOAD_ADD:
1157 case ISD::ATOMIC_LOAD_SUB:
1158 case ISD::ATOMIC_LOAD_AND:
1159 case ISD::ATOMIC_LOAD_OR:
1160 case ISD::ATOMIC_LOAD_XOR:
1161 case ISD::ATOMIC_LOAD_NAND:
1162 case ISD::ATOMIC_LOAD_MIN:
1163 case ISD::ATOMIC_LOAD_MAX:
1164 case ISD::ATOMIC_LOAD_UMIN:
1165 case ISD::ATOMIC_LOAD_UMAX:
1166 case ISD::ATOMIC_SWAP:
1167 case ISD::ATOMIC_CMP_SWAP: {
1168 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1169 SplitInteger(Tmp.first, Lo, Hi);
1170 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1173 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1174 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1175 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1176 SDValue Tmp = DAG.getAtomicCmpSwap(
1177 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1178 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1179 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1180 AN->getSynchScope());
1182 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1183 // success simply by comparing the loaded value against the ingoing
1185 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1186 N->getOperand(2), ISD::SETEQ);
1188 SplitInteger(Tmp, Lo, Hi);
1189 ReplaceValueWith(SDValue(N, 1), Success);
1190 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1196 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1199 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1202 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1205 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1209 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1212 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1214 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1216 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1219 // If Lo/Hi is null, the sub-method took care of registering results etc.
1221 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1224 /// Lower an atomic node to the appropriate builtin call.
1225 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1226 unsigned Opc = Node->getOpcode();
1227 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1232 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1233 case ISD::ATOMIC_SWAP:
1234 switch (VT.SimpleTy) {
1235 default: llvm_unreachable("Unexpected value type for atomic!");
1236 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1237 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1238 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1239 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1240 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
1243 case ISD::ATOMIC_CMP_SWAP:
1244 switch (VT.SimpleTy) {
1245 default: llvm_unreachable("Unexpected value type for atomic!");
1246 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1247 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1248 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1249 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1250 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
1253 case ISD::ATOMIC_LOAD_ADD:
1254 switch (VT.SimpleTy) {
1255 default: llvm_unreachable("Unexpected value type for atomic!");
1256 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1257 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1258 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1259 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1260 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1263 case ISD::ATOMIC_LOAD_SUB:
1264 switch (VT.SimpleTy) {
1265 default: llvm_unreachable("Unexpected value type for atomic!");
1266 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1267 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1268 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1269 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1270 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1273 case ISD::ATOMIC_LOAD_AND:
1274 switch (VT.SimpleTy) {
1275 default: llvm_unreachable("Unexpected value type for atomic!");
1276 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1277 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1278 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1279 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1280 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1283 case ISD::ATOMIC_LOAD_OR:
1284 switch (VT.SimpleTy) {
1285 default: llvm_unreachable("Unexpected value type for atomic!");
1286 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1287 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1288 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1289 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1290 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1293 case ISD::ATOMIC_LOAD_XOR:
1294 switch (VT.SimpleTy) {
1295 default: llvm_unreachable("Unexpected value type for atomic!");
1296 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1297 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1298 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1299 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1300 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1303 case ISD::ATOMIC_LOAD_NAND:
1304 switch (VT.SimpleTy) {
1305 default: llvm_unreachable("Unexpected value type for atomic!");
1306 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1307 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1308 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1309 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1310 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1315 return ExpandChainLibCall(LC, Node, false);
1318 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1319 /// and the shift amount is a constant 'Amt'. Expand the operation.
1320 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1321 SDValue &Lo, SDValue &Hi) {
1322 assert(Amt && "Expected zero shifts to be already optimized away.");
1324 // Expand the incoming operand to be shifted, so that we have its parts
1326 GetExpandedInteger(N->getOperand(0), InL, InH);
1328 EVT NVT = InL.getValueType();
1329 unsigned VTBits = N->getValueType(0).getSizeInBits();
1330 unsigned NVTBits = NVT.getSizeInBits();
1331 EVT ShTy = N->getOperand(1).getValueType();
1333 if (N->getOpcode() == ISD::SHL) {
1335 Lo = Hi = DAG.getConstant(0, NVT);
1336 } else if (Amt > NVTBits) {
1337 Lo = DAG.getConstant(0, NVT);
1338 Hi = DAG.getNode(ISD::SHL, DL,
1339 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1340 } else if (Amt == NVTBits) {
1341 Lo = DAG.getConstant(0, NVT);
1343 } else if (Amt == 1 &&
1344 TLI.isOperationLegalOrCustom(ISD::ADDC,
1345 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1346 // Emit this X << 1 as X+X.
1347 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1348 SDValue LoOps[2] = { InL, InL };
1349 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1350 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1351 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1353 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1354 Hi = DAG.getNode(ISD::OR, DL, NVT,
1355 DAG.getNode(ISD::SHL, DL, NVT, InH,
1356 DAG.getConstant(Amt, ShTy)),
1357 DAG.getNode(ISD::SRL, DL, NVT, InL,
1358 DAG.getConstant(NVTBits-Amt, ShTy)));
1363 if (N->getOpcode() == ISD::SRL) {
1365 Lo = DAG.getConstant(0, NVT);
1366 Hi = DAG.getConstant(0, NVT);
1367 } else if (Amt > NVTBits) {
1368 Lo = DAG.getNode(ISD::SRL, DL,
1369 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1370 Hi = DAG.getConstant(0, NVT);
1371 } else if (Amt == NVTBits) {
1373 Hi = DAG.getConstant(0, NVT);
1375 Lo = DAG.getNode(ISD::OR, DL, NVT,
1376 DAG.getNode(ISD::SRL, DL, NVT, InL,
1377 DAG.getConstant(Amt, ShTy)),
1378 DAG.getNode(ISD::SHL, DL, NVT, InH,
1379 DAG.getConstant(NVTBits-Amt, ShTy)));
1380 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1385 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1387 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1388 DAG.getConstant(NVTBits-1, ShTy));
1389 } else if (Amt > NVTBits) {
1390 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1391 DAG.getConstant(Amt-NVTBits, ShTy));
1392 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1393 DAG.getConstant(NVTBits-1, ShTy));
1394 } else if (Amt == NVTBits) {
1396 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1397 DAG.getConstant(NVTBits-1, ShTy));
1399 Lo = DAG.getNode(ISD::OR, DL, NVT,
1400 DAG.getNode(ISD::SRL, DL, NVT, InL,
1401 DAG.getConstant(Amt, ShTy)),
1402 DAG.getNode(ISD::SHL, DL, NVT, InH,
1403 DAG.getConstant(NVTBits-Amt, ShTy)));
1404 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1408 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1409 /// this shift based on knowledge of the high bit of the shift amount. If we
1410 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1412 bool DAGTypeLegalizer::
1413 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1414 SDValue Amt = N->getOperand(1);
1415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1416 EVT ShTy = Amt.getValueType();
1417 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1418 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1419 assert(isPowerOf2_32(NVTBits) &&
1420 "Expanded integer type size not a power of two!");
1423 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1424 APInt KnownZero, KnownOne;
1425 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1427 // If we don't know anything about the high bits, exit.
1428 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1431 // Get the incoming operand to be shifted.
1433 GetExpandedInteger(N->getOperand(0), InL, InH);
1435 // If we know that any of the high bits of the shift amount are one, then we
1436 // can do this as a couple of simple shifts.
1437 if (KnownOne.intersects(HighBitMask)) {
1438 // Mask out the high bit, which we know is set.
1439 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1440 DAG.getConstant(~HighBitMask, ShTy));
1442 switch (N->getOpcode()) {
1443 default: llvm_unreachable("Unknown shift");
1445 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1446 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1449 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1450 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1453 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1454 DAG.getConstant(NVTBits-1, ShTy));
1455 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1460 // If we know that all of the high bits of the shift amount are zero, then we
1461 // can do this as a couple of simple shifts.
1462 if ((KnownZero & HighBitMask) == HighBitMask) {
1463 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1464 // shift if x is zero. We can use XOR here because x is known to be smaller
1466 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1467 DAG.getConstant(NVTBits-1, ShTy));
1470 switch (N->getOpcode()) {
1471 default: llvm_unreachable("Unknown shift");
1472 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1474 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1477 // When shifting right the arithmetic for Lo and Hi is swapped.
1478 if (N->getOpcode() != ISD::SHL)
1479 std::swap(InL, InH);
1481 // Use a little trick to get the bits that move from Lo to Hi. First
1482 // shift by one bit.
1483 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1484 // Then compute the remaining shift with amount-1.
1485 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1487 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1488 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1490 if (N->getOpcode() != ISD::SHL)
1498 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1500 bool DAGTypeLegalizer::
1501 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1502 SDValue Amt = N->getOperand(1);
1503 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1504 EVT ShTy = Amt.getValueType();
1505 unsigned NVTBits = NVT.getSizeInBits();
1506 assert(isPowerOf2_32(NVTBits) &&
1507 "Expanded integer type size not a power of two!");
1510 // Get the incoming operand to be shifted.
1512 GetExpandedInteger(N->getOperand(0), InL, InH);
1514 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1515 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1516 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1517 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1518 Amt, NVBitsNode, ISD::SETULT);
1520 SDValue LoS, HiS, LoL, HiL;
1521 switch (N->getOpcode()) {
1522 default: llvm_unreachable("Unknown shift");
1524 // Short: ShAmt < NVTBits
1525 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1526 HiS = DAG.getNode(ISD::OR, dl, NVT,
1527 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1528 // FIXME: If Amt is zero, the following shift generates an undefined result
1529 // on some architectures.
1530 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1532 // Long: ShAmt >= NVTBits
1533 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1534 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1536 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1537 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1540 // Short: ShAmt < NVTBits
1541 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1542 LoS = DAG.getNode(ISD::OR, dl, NVT,
1543 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1544 // FIXME: If Amt is zero, the following shift generates an undefined result
1545 // on some architectures.
1546 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1548 // Long: ShAmt >= NVTBits
1549 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1550 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1552 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1553 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1556 // Short: ShAmt < NVTBits
1557 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1558 LoS = DAG.getNode(ISD::OR, dl, NVT,
1559 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1560 // FIXME: If Amt is zero, the following shift generates an undefined result
1561 // on some architectures.
1562 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1564 // Long: ShAmt >= NVTBits
1565 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1566 DAG.getConstant(NVTBits-1, ShTy));
1567 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1569 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1570 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1575 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1576 SDValue &Lo, SDValue &Hi) {
1578 // Expand the subcomponents.
1579 SDValue LHSL, LHSH, RHSL, RHSH;
1580 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1581 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1583 EVT NVT = LHSL.getValueType();
1584 SDValue LoOps[2] = { LHSL, RHSL };
1585 SDValue HiOps[3] = { LHSH, RHSH };
1587 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1588 // them. TODO: Teach operation legalization how to expand unsupported
1589 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1590 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1591 // generate a value of this type in the expanded code sequence.
1593 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1594 ISD::ADDC : ISD::SUBC,
1595 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1598 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1599 if (N->getOpcode() == ISD::ADD) {
1600 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1601 HiOps[2] = Lo.getValue(1);
1602 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1604 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1605 HiOps[2] = Lo.getValue(1);
1606 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1611 if (N->getOpcode() == ISD::ADD) {
1612 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1613 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1614 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1616 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1617 DAG.getConstant(1, NVT),
1618 DAG.getConstant(0, NVT));
1619 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1621 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1622 DAG.getConstant(1, NVT), Carry1);
1623 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1625 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1626 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1628 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1629 LoOps[0], LoOps[1], ISD::SETULT);
1630 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1631 DAG.getConstant(1, NVT),
1632 DAG.getConstant(0, NVT));
1633 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1637 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1638 SDValue &Lo, SDValue &Hi) {
1639 // Expand the subcomponents.
1640 SDValue LHSL, LHSH, RHSL, RHSH;
1642 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1643 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1644 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1645 SDValue LoOps[2] = { LHSL, RHSL };
1646 SDValue HiOps[3] = { LHSH, RHSH };
1648 if (N->getOpcode() == ISD::ADDC) {
1649 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1650 HiOps[2] = Lo.getValue(1);
1651 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1653 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1654 HiOps[2] = Lo.getValue(1);
1655 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1658 // Legalized the flag result - switch anything that used the old flag to
1660 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1663 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1664 SDValue &Lo, SDValue &Hi) {
1665 // Expand the subcomponents.
1666 SDValue LHSL, LHSH, RHSL, RHSH;
1668 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1669 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1670 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1671 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1672 SDValue HiOps[3] = { LHSH, RHSH };
1674 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1675 HiOps[2] = Lo.getValue(1);
1676 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1678 // Legalized the flag result - switch anything that used the old flag to
1680 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1683 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1684 SDValue &Lo, SDValue &Hi) {
1685 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1686 SplitInteger(Res, Lo, Hi);
1689 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1690 SDValue &Lo, SDValue &Hi) {
1691 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1693 SDValue Op = N->getOperand(0);
1694 if (Op.getValueType().bitsLE(NVT)) {
1695 // The low part is any extension of the input (which degenerates to a copy).
1696 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1697 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1699 // For example, extension of an i48 to an i64. The operand type necessarily
1700 // promotes to the result type, so will end up being expanded too.
1701 assert(getTypeAction(Op.getValueType()) ==
1702 TargetLowering::TypePromoteInteger &&
1703 "Only know how to promote this result!");
1704 SDValue Res = GetPromotedInteger(Op);
1705 assert(Res.getValueType() == N->getValueType(0) &&
1706 "Operand over promoted?");
1707 // Split the promoted operand. This will simplify when it is expanded.
1708 SplitInteger(Res, Lo, Hi);
1712 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1713 SDValue &Lo, SDValue &Hi) {
1715 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1716 EVT NVT = Lo.getValueType();
1717 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1718 unsigned NVTBits = NVT.getSizeInBits();
1719 unsigned EVTBits = EVT.getSizeInBits();
1721 if (NVTBits < EVTBits) {
1722 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1723 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1724 EVTBits - NVTBits)));
1726 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1727 // The high part replicates the sign bit of Lo, make it explicit.
1728 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1729 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1733 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1734 SDValue &Lo, SDValue &Hi) {
1736 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1737 EVT NVT = Lo.getValueType();
1738 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1739 unsigned NVTBits = NVT.getSizeInBits();
1740 unsigned EVTBits = EVT.getSizeInBits();
1742 if (NVTBits < EVTBits) {
1743 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1744 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1745 EVTBits - NVTBits)));
1747 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1748 // The high part must be zero, make it explicit.
1749 Hi = DAG.getConstant(0, NVT);
1753 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1754 SDValue &Lo, SDValue &Hi) {
1756 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1757 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1758 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1761 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1762 SDValue &Lo, SDValue &Hi) {
1763 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1764 unsigned NBitWidth = NVT.getSizeInBits();
1765 auto Constant = cast<ConstantSDNode>(N);
1766 const APInt &Cst = Constant->getAPIntValue();
1767 bool IsTarget = Constant->isTargetOpcode();
1768 bool IsOpaque = Constant->isOpaque();
1769 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
1770 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
1774 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1775 SDValue &Lo, SDValue &Hi) {
1777 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1778 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1779 EVT NVT = Lo.getValueType();
1781 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1782 DAG.getConstant(0, NVT), ISD::SETNE);
1784 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1785 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1787 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1788 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1789 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1790 Hi = DAG.getConstant(0, NVT);
1793 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1794 SDValue &Lo, SDValue &Hi) {
1796 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1797 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1798 EVT NVT = Lo.getValueType();
1799 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1800 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1801 Hi = DAG.getConstant(0, NVT);
1804 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1805 SDValue &Lo, SDValue &Hi) {
1807 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1808 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1809 EVT NVT = Lo.getValueType();
1811 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1812 DAG.getConstant(0, NVT), ISD::SETNE);
1814 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1815 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1817 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1818 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1819 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1820 Hi = DAG.getConstant(0, NVT);
1823 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1826 EVT VT = N->getValueType(0);
1827 SDValue Op = N->getOperand(0);
1828 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1829 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1830 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1835 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1838 EVT VT = N->getValueType(0);
1839 SDValue Op = N->getOperand(0);
1840 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1841 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1842 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1847 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1848 SDValue &Lo, SDValue &Hi) {
1849 if (ISD::isNormalLoad(N)) {
1850 ExpandRes_NormalLoad(N, Lo, Hi);
1854 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1856 EVT VT = N->getValueType(0);
1857 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1858 SDValue Ch = N->getChain();
1859 SDValue Ptr = N->getBasePtr();
1860 ISD::LoadExtType ExtType = N->getExtensionType();
1861 unsigned Alignment = N->getAlignment();
1862 bool isVolatile = N->isVolatile();
1863 bool isNonTemporal = N->isNonTemporal();
1864 bool isInvariant = N->isInvariant();
1865 const MDNode *TBAAInfo = N->getTBAAInfo();
1868 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1870 if (N->getMemoryVT().bitsLE(NVT)) {
1871 EVT MemVT = N->getMemoryVT();
1873 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1874 MemVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
1876 // Remember the chain.
1877 Ch = Lo.getValue(1);
1879 if (ExtType == ISD::SEXTLOAD) {
1880 // The high part is obtained by SRA'ing all but one of the bits of the
1882 unsigned LoSize = Lo.getValueType().getSizeInBits();
1883 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1884 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1885 } else if (ExtType == ISD::ZEXTLOAD) {
1886 // The high part is just a zero.
1887 Hi = DAG.getConstant(0, NVT);
1889 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1890 // The high part is undefined.
1891 Hi = DAG.getUNDEF(NVT);
1893 } else if (TLI.isLittleEndian()) {
1894 // Little-endian - low bits are at low addresses.
1895 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1896 isVolatile, isNonTemporal, isInvariant, Alignment,
1899 unsigned ExcessBits =
1900 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1901 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1903 // Increment the pointer to the other half.
1904 unsigned IncrementSize = NVT.getSizeInBits()/8;
1905 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1906 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1907 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1908 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1909 isVolatile, isNonTemporal,
1910 MinAlign(Alignment, IncrementSize), TBAAInfo);
1912 // Build a factor node to remember that this load is independent of the
1914 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1917 // Big-endian - high bits are at low addresses. Favor aligned loads at
1918 // the cost of some bit-fiddling.
1919 EVT MemVT = N->getMemoryVT();
1920 unsigned EBytes = MemVT.getStoreSize();
1921 unsigned IncrementSize = NVT.getSizeInBits()/8;
1922 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1924 // Load both the high bits and maybe some of the low bits.
1925 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1926 EVT::getIntegerVT(*DAG.getContext(),
1927 MemVT.getSizeInBits() - ExcessBits),
1928 isVolatile, isNonTemporal, Alignment, TBAAInfo);
1930 // Increment the pointer to the other half.
1931 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1932 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1933 // Load the rest of the low bits.
1934 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1935 N->getPointerInfo().getWithOffset(IncrementSize),
1936 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1937 isVolatile, isNonTemporal,
1938 MinAlign(Alignment, IncrementSize), TBAAInfo);
1940 // Build a factor node to remember that this load is independent of the
1942 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1945 if (ExcessBits < NVT.getSizeInBits()) {
1946 // Transfer low bits from the bottom of Hi to the top of Lo.
1947 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1948 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1949 DAG.getConstant(ExcessBits,
1950 TLI.getPointerTy())));
1951 // Move high bits to the right position in Hi.
1952 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1954 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1955 TLI.getPointerTy()));
1959 // Legalized the chain result - switch anything that used the old chain to
1961 ReplaceValueWith(SDValue(N, 1), Ch);
1964 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1965 SDValue &Lo, SDValue &Hi) {
1967 SDValue LL, LH, RL, RH;
1968 GetExpandedInteger(N->getOperand(0), LL, LH);
1969 GetExpandedInteger(N->getOperand(1), RL, RH);
1970 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1971 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1974 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1975 SDValue &Lo, SDValue &Hi) {
1976 EVT VT = N->getValueType(0);
1977 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1980 SDValue LL, LH, RL, RH;
1981 GetExpandedInteger(N->getOperand(0), LL, LH);
1982 GetExpandedInteger(N->getOperand(1), RL, RH);
1984 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
1987 // If nothing else, we can make a libcall.
1988 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1990 LC = RTLIB::MUL_I16;
1991 else if (VT == MVT::i32)
1992 LC = RTLIB::MUL_I32;
1993 else if (VT == MVT::i64)
1994 LC = RTLIB::MUL_I64;
1995 else if (VT == MVT::i128)
1996 LC = RTLIB::MUL_I128;
1997 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1999 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2000 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2005 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2006 SDValue &Lo, SDValue &Hi) {
2007 SDValue LHS = Node->getOperand(0);
2008 SDValue RHS = Node->getOperand(1);
2011 // Expand the result by simply replacing it with the equivalent
2012 // non-overflow-checking operation.
2013 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2014 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2016 SplitInteger(Sum, Lo, Hi);
2018 // Compute the overflow.
2020 // LHSSign -> LHS >= 0
2021 // RHSSign -> RHS >= 0
2022 // SumSign -> Sum >= 0
2025 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2027 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2029 EVT OType = Node->getValueType(1);
2030 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2032 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2033 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2034 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2035 Node->getOpcode() == ISD::SADDO ?
2036 ISD::SETEQ : ISD::SETNE);
2038 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2039 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2041 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2043 // Use the calculated overflow everywhere.
2044 ReplaceValueWith(SDValue(Node, 1), Cmp);
2047 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2048 SDValue &Lo, SDValue &Hi) {
2049 EVT VT = N->getValueType(0);
2052 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2054 LC = RTLIB::SDIV_I16;
2055 else if (VT == MVT::i32)
2056 LC = RTLIB::SDIV_I32;
2057 else if (VT == MVT::i64)
2058 LC = RTLIB::SDIV_I64;
2059 else if (VT == MVT::i128)
2060 LC = RTLIB::SDIV_I128;
2061 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2063 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2064 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2067 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2068 SDValue &Lo, SDValue &Hi) {
2069 EVT VT = N->getValueType(0);
2072 // If we can emit an efficient shift operation, do so now. Check to see if
2073 // the RHS is a constant.
2074 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2075 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2077 // If we can determine that the high bit of the shift is zero or one, even if
2078 // the low bits are variable, emit this shift in an optimized form.
2079 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2082 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2084 if (N->getOpcode() == ISD::SHL) {
2085 PartsOpc = ISD::SHL_PARTS;
2086 } else if (N->getOpcode() == ISD::SRL) {
2087 PartsOpc = ISD::SRL_PARTS;
2089 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2090 PartsOpc = ISD::SRA_PARTS;
2093 // Next check to see if the target supports this SHL_PARTS operation or if it
2094 // will custom expand it.
2095 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2096 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2097 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2098 Action == TargetLowering::Custom) {
2099 // Expand the subcomponents.
2101 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2102 EVT VT = LHSL.getValueType();
2104 // If the shift amount operand is coming from a vector legalization it may
2105 // have an illegal type. Fix that first by casting the operand, otherwise
2106 // the new SHL_PARTS operation would need further legalization.
2107 SDValue ShiftOp = N->getOperand(1);
2108 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2109 assert(ShiftTy.getScalarType().getSizeInBits() >=
2110 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2111 "ShiftAmountTy is too small to cover the range of this type!");
2112 if (ShiftOp.getValueType() != ShiftTy)
2113 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2115 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2116 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2117 Hi = Lo.getValue(1);
2121 // Otherwise, emit a libcall.
2122 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2124 if (N->getOpcode() == ISD::SHL) {
2125 isSigned = false; /*sign irrelevant*/
2127 LC = RTLIB::SHL_I16;
2128 else if (VT == MVT::i32)
2129 LC = RTLIB::SHL_I32;
2130 else if (VT == MVT::i64)
2131 LC = RTLIB::SHL_I64;
2132 else if (VT == MVT::i128)
2133 LC = RTLIB::SHL_I128;
2134 } else if (N->getOpcode() == ISD::SRL) {
2137 LC = RTLIB::SRL_I16;
2138 else if (VT == MVT::i32)
2139 LC = RTLIB::SRL_I32;
2140 else if (VT == MVT::i64)
2141 LC = RTLIB::SRL_I64;
2142 else if (VT == MVT::i128)
2143 LC = RTLIB::SRL_I128;
2145 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2148 LC = RTLIB::SRA_I16;
2149 else if (VT == MVT::i32)
2150 LC = RTLIB::SRA_I32;
2151 else if (VT == MVT::i64)
2152 LC = RTLIB::SRA_I64;
2153 else if (VT == MVT::i128)
2154 LC = RTLIB::SRA_I128;
2157 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2158 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2159 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2164 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2165 llvm_unreachable("Unsupported shift!");
2168 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2169 SDValue &Lo, SDValue &Hi) {
2170 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2172 SDValue Op = N->getOperand(0);
2173 if (Op.getValueType().bitsLE(NVT)) {
2174 // The low part is sign extension of the input (degenerates to a copy).
2175 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2176 // The high part is obtained by SRA'ing all but one of the bits of low part.
2177 unsigned LoSize = NVT.getSizeInBits();
2178 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2179 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2181 // For example, extension of an i48 to an i64. The operand type necessarily
2182 // promotes to the result type, so will end up being expanded too.
2183 assert(getTypeAction(Op.getValueType()) ==
2184 TargetLowering::TypePromoteInteger &&
2185 "Only know how to promote this result!");
2186 SDValue Res = GetPromotedInteger(Op);
2187 assert(Res.getValueType() == N->getValueType(0) &&
2188 "Operand over promoted?");
2189 // Split the promoted operand. This will simplify when it is expanded.
2190 SplitInteger(Res, Lo, Hi);
2191 unsigned ExcessBits =
2192 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2193 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2194 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2199 void DAGTypeLegalizer::
2200 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2202 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2203 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2205 if (EVT.bitsLE(Lo.getValueType())) {
2206 // sext_inreg the low part if needed.
2207 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2210 // The high part gets the sign extension from the lo-part. This handles
2211 // things like sextinreg V:i64 from i8.
2212 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2213 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2214 TLI.getPointerTy()));
2216 // For example, extension of an i48 to an i64. Leave the low part alone,
2217 // sext_inreg the high part.
2218 unsigned ExcessBits =
2219 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2220 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2221 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2226 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2227 SDValue &Lo, SDValue &Hi) {
2228 EVT VT = N->getValueType(0);
2231 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2233 LC = RTLIB::SREM_I16;
2234 else if (VT == MVT::i32)
2235 LC = RTLIB::SREM_I32;
2236 else if (VT == MVT::i64)
2237 LC = RTLIB::SREM_I64;
2238 else if (VT == MVT::i128)
2239 LC = RTLIB::SREM_I128;
2240 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2242 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2243 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2246 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2247 SDValue &Lo, SDValue &Hi) {
2248 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2250 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2251 Hi = DAG.getNode(ISD::SRL, dl,
2252 N->getOperand(0).getValueType(), N->getOperand(0),
2253 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2254 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2257 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2258 SDValue &Lo, SDValue &Hi) {
2259 SDValue LHS = N->getOperand(0);
2260 SDValue RHS = N->getOperand(1);
2263 // Expand the result by simply replacing it with the equivalent
2264 // non-overflow-checking operation.
2265 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2266 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2268 SplitInteger(Sum, Lo, Hi);
2270 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2271 // overflows iff a - b > a.
2272 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2273 N->getOpcode () == ISD::UADDO ?
2274 ISD::SETULT : ISD::SETUGT);
2276 // Use the calculated overflow everywhere.
2277 ReplaceValueWith(SDValue(N, 1), Ofl);
2280 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2281 SDValue &Lo, SDValue &Hi) {
2282 EVT VT = N->getValueType(0);
2285 // A divide for UMULO should be faster than a function call.
2286 if (N->getOpcode() == ISD::UMULO) {
2287 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2289 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2290 SplitInteger(MUL, Lo, Hi);
2292 // A divide for UMULO will be faster than a function call. Select to
2293 // make sure we aren't using 0.
2294 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2295 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2296 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2297 DAG.getConstant(1, VT), RHS);
2298 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2299 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2301 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2302 DAG.getConstant(0, N->getValueType(1)),
2304 ReplaceValueWith(SDValue(N, 1), Overflow);
2308 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2309 EVT PtrVT = TLI.getPointerTy();
2310 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2312 // Replace this with a libcall that will check overflow.
2313 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2315 LC = RTLIB::MULO_I32;
2316 else if (VT == MVT::i64)
2317 LC = RTLIB::MULO_I64;
2318 else if (VT == MVT::i128)
2319 LC = RTLIB::MULO_I128;
2320 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2322 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2323 // Temporary for the overflow value, default it to zero.
2324 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2325 DAG.getConstant(0, PtrVT), Temp,
2326 MachinePointerInfo(), false, false, 0);
2328 TargetLowering::ArgListTy Args;
2329 TargetLowering::ArgListEntry Entry;
2330 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2331 EVT ArgVT = N->getOperand(i).getValueType();
2332 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2333 Entry.Node = N->getOperand(i);
2335 Entry.isSExt = true;
2336 Entry.isZExt = false;
2337 Args.push_back(Entry);
2340 // Also pass the address of the overflow check.
2342 Entry.Ty = PtrTy->getPointerTo();
2343 Entry.isSExt = true;
2344 Entry.isZExt = false;
2345 Args.push_back(Entry);
2347 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2349 TargetLowering::CallLoweringInfo CLI(DAG);
2350 CLI.setDebugLoc(dl).setChain(Chain)
2351 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2354 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2356 SplitInteger(CallInfo.first, Lo, Hi);
2357 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2358 MachinePointerInfo(), false, false, false, 0);
2359 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2360 DAG.getConstant(0, PtrVT),
2362 // Use the overflow from the libcall everywhere.
2363 ReplaceValueWith(SDValue(N, 1), Ofl);
2366 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2367 SDValue &Lo, SDValue &Hi) {
2368 EVT VT = N->getValueType(0);
2371 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2373 LC = RTLIB::UDIV_I16;
2374 else if (VT == MVT::i32)
2375 LC = RTLIB::UDIV_I32;
2376 else if (VT == MVT::i64)
2377 LC = RTLIB::UDIV_I64;
2378 else if (VT == MVT::i128)
2379 LC = RTLIB::UDIV_I128;
2380 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2382 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2383 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2386 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2387 SDValue &Lo, SDValue &Hi) {
2388 EVT VT = N->getValueType(0);
2391 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2393 LC = RTLIB::UREM_I16;
2394 else if (VT == MVT::i32)
2395 LC = RTLIB::UREM_I32;
2396 else if (VT == MVT::i64)
2397 LC = RTLIB::UREM_I64;
2398 else if (VT == MVT::i128)
2399 LC = RTLIB::UREM_I128;
2400 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2402 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2403 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2406 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2407 SDValue &Lo, SDValue &Hi) {
2408 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2410 SDValue Op = N->getOperand(0);
2411 if (Op.getValueType().bitsLE(NVT)) {
2412 // The low part is zero extension of the input (degenerates to a copy).
2413 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2414 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2416 // For example, extension of an i48 to an i64. The operand type necessarily
2417 // promotes to the result type, so will end up being expanded too.
2418 assert(getTypeAction(Op.getValueType()) ==
2419 TargetLowering::TypePromoteInteger &&
2420 "Only know how to promote this result!");
2421 SDValue Res = GetPromotedInteger(Op);
2422 assert(Res.getValueType() == N->getValueType(0) &&
2423 "Operand over promoted?");
2424 // Split the promoted operand. This will simplify when it is expanded.
2425 SplitInteger(Res, Lo, Hi);
2426 unsigned ExcessBits =
2427 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2428 Hi = DAG.getZeroExtendInReg(Hi, dl,
2429 EVT::getIntegerVT(*DAG.getContext(),
2434 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2435 SDValue &Lo, SDValue &Hi) {
2437 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2438 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2439 SDValue Zero = DAG.getConstant(0, VT);
2440 SDValue Swap = DAG.getAtomicCmpSwap(
2441 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2442 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2443 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2444 cast<AtomicSDNode>(N)->getOrdering(),
2445 cast<AtomicSDNode>(N)->getOrdering(),
2446 cast<AtomicSDNode>(N)->getSynchScope());
2448 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2449 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2452 //===----------------------------------------------------------------------===//
2453 // Integer Operand Expansion
2454 //===----------------------------------------------------------------------===//
2456 /// ExpandIntegerOperand - This method is called when the specified operand of
2457 /// the specified node is found to need expansion. At this point, all of the
2458 /// result types of the node are known to be legal, but other operands of the
2459 /// node may need promotion or expansion as well as the specified one.
2460 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2461 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2462 SDValue Res = SDValue();
2464 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2467 switch (N->getOpcode()) {
2470 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2471 N->dump(&DAG); dbgs() << "\n";
2473 llvm_unreachable("Do not know how to expand this operator's operand!");
2475 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2476 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2477 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2478 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2479 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2480 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2481 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2482 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2483 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2484 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2485 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2486 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2492 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2493 case ISD::RETURNADDR:
2494 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2496 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2499 // If the result is null, the sub-method took care of registering results etc.
2500 if (!Res.getNode()) return false;
2502 // If the result is N, the sub-method updated N in place. Tell the legalizer
2504 if (Res.getNode() == N)
2507 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2508 "Invalid operand expansion");
2510 ReplaceValueWith(SDValue(N, 0), Res);
2514 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2515 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2516 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2518 ISD::CondCode &CCCode,
2520 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2521 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2522 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2524 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2525 if (RHSLo == RHSHi) {
2526 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2527 if (RHSCST->isAllOnesValue()) {
2528 // Equality comparison to -1.
2529 NewLHS = DAG.getNode(ISD::AND, dl,
2530 LHSLo.getValueType(), LHSLo, LHSHi);
2537 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2538 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2539 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2540 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2544 // If this is a comparison of the sign bit, just look at the top part.
2546 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2547 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2548 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2554 // FIXME: This generated code sucks.
2555 ISD::CondCode LowCC;
2557 default: llvm_unreachable("Unknown integer setcc!");
2559 case ISD::SETULT: LowCC = ISD::SETULT; break;
2561 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2563 case ISD::SETULE: LowCC = ISD::SETULE; break;
2565 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2568 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2569 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2570 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2572 // NOTE: on targets without efficient SELECT of bools, we can always use
2573 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2574 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2577 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2578 TLI.isTypeLegal(RHSLo.getValueType()))
2579 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2580 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2581 if (!Tmp1.getNode())
2582 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2583 LHSLo, RHSLo, LowCC);
2584 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2585 TLI.isTypeLegal(RHSHi.getValueType()))
2586 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2587 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2588 if (!Tmp2.getNode())
2589 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2590 getSetCCResultType(LHSHi.getValueType()),
2591 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2593 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2594 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2595 if ((Tmp1C && Tmp1C->isNullValue()) ||
2596 (Tmp2C && Tmp2C->isNullValue() &&
2597 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2598 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2599 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2600 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2601 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2602 // low part is known false, returns high part.
2603 // For LE / GE, if high part is known false, ignore the low part.
2604 // For LT / GT, if high part is known true, ignore the low part.
2610 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2611 LHSHi, RHSHi, ISD::SETEQ, false,
2612 DagCombineInfo, dl);
2613 if (!NewLHS.getNode())
2614 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2615 LHSHi, RHSHi, ISD::SETEQ);
2616 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2617 NewLHS, Tmp1, Tmp2);
2621 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2622 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2623 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2624 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2626 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2627 // against zero to select between true and false values.
2628 if (!NewRHS.getNode()) {
2629 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2630 CCCode = ISD::SETNE;
2633 // Update N to have the operands specified.
2634 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2635 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2636 N->getOperand(4)), 0);
2639 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2640 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2641 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2642 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2644 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2645 // against zero to select between true and false values.
2646 if (!NewRHS.getNode()) {
2647 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2648 CCCode = ISD::SETNE;
2651 // Update N to have the operands specified.
2652 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2653 N->getOperand(2), N->getOperand(3),
2654 DAG.getCondCode(CCCode)), 0);
2657 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2658 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2659 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2660 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2662 // If ExpandSetCCOperands returned a scalar, use it.
2663 if (!NewRHS.getNode()) {
2664 assert(NewLHS.getValueType() == N->getValueType(0) &&
2665 "Unexpected setcc expansion!");
2669 // Otherwise, update N to have the operands specified.
2670 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2671 DAG.getCondCode(CCCode)), 0);
2674 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2675 // The value being shifted is legal, but the shift amount is too big.
2676 // It follows that either the result of the shift is undefined, or the
2677 // upper half of the shift amount is zero. Just use the lower half.
2679 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2680 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2683 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2684 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2685 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2686 // constant to valid type.
2688 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2689 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2692 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2693 SDValue Op = N->getOperand(0);
2694 EVT DstVT = N->getValueType(0);
2695 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2696 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2697 "Don't know how to expand this SINT_TO_FP!");
2698 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2701 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2702 if (ISD::isNormalStore(N))
2703 return ExpandOp_NormalStore(N, OpNo);
2705 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2706 assert(OpNo == 1 && "Can only expand the stored value so far");
2708 EVT VT = N->getOperand(1).getValueType();
2709 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2710 SDValue Ch = N->getChain();
2711 SDValue Ptr = N->getBasePtr();
2712 unsigned Alignment = N->getAlignment();
2713 bool isVolatile = N->isVolatile();
2714 bool isNonTemporal = N->isNonTemporal();
2715 const MDNode *TBAAInfo = N->getTBAAInfo();
2719 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2721 if (N->getMemoryVT().bitsLE(NVT)) {
2722 GetExpandedInteger(N->getValue(), Lo, Hi);
2723 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2724 N->getMemoryVT(), isVolatile, isNonTemporal,
2725 Alignment, TBAAInfo);
2728 if (TLI.isLittleEndian()) {
2729 // Little-endian - low bits are at low addresses.
2730 GetExpandedInteger(N->getValue(), Lo, Hi);
2732 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2733 isVolatile, isNonTemporal, Alignment, TBAAInfo);
2735 unsigned ExcessBits =
2736 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2737 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2739 // Increment the pointer to the other half.
2740 unsigned IncrementSize = NVT.getSizeInBits()/8;
2741 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2742 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2743 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2744 N->getPointerInfo().getWithOffset(IncrementSize),
2745 NEVT, isVolatile, isNonTemporal,
2746 MinAlign(Alignment, IncrementSize), TBAAInfo);
2747 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2750 // Big-endian - high bits are at low addresses. Favor aligned stores at
2751 // the cost of some bit-fiddling.
2752 GetExpandedInteger(N->getValue(), Lo, Hi);
2754 EVT ExtVT = N->getMemoryVT();
2755 unsigned EBytes = ExtVT.getStoreSize();
2756 unsigned IncrementSize = NVT.getSizeInBits()/8;
2757 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2758 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2759 ExtVT.getSizeInBits() - ExcessBits);
2761 if (ExcessBits < NVT.getSizeInBits()) {
2762 // Transfer high bits from the top of Lo to the bottom of Hi.
2763 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2764 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2765 TLI.getPointerTy()));
2766 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2767 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2768 DAG.getConstant(ExcessBits,
2769 TLI.getPointerTy())));
2772 // Store both the high bits and maybe some of the low bits.
2773 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2774 HiVT, isVolatile, isNonTemporal, Alignment, TBAAInfo);
2776 // Increment the pointer to the other half.
2777 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2778 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2779 // Store the lowest ExcessBits bits in the second half.
2780 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2781 N->getPointerInfo().getWithOffset(IncrementSize),
2782 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2783 isVolatile, isNonTemporal,
2784 MinAlign(Alignment, IncrementSize), TBAAInfo);
2785 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2788 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2790 GetExpandedInteger(N->getOperand(0), InL, InH);
2791 // Just truncate the low part of the source.
2792 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2795 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2796 SDValue Op = N->getOperand(0);
2797 EVT SrcVT = Op.getValueType();
2798 EVT DstVT = N->getValueType(0);
2801 // The following optimization is valid only if every value in SrcVT (when
2802 // treated as signed) is representable in DstVT. Check that the mantissa
2803 // size of DstVT is >= than the number of bits in SrcVT -1.
2804 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2805 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2806 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2807 // Do a signed conversion then adjust the result.
2808 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2809 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2811 // The result of the signed conversion needs adjusting if the 'sign bit' of
2812 // the incoming integer was set. To handle this, we dynamically test to see
2813 // if it is set, and, if so, add a fudge factor.
2815 const uint64_t F32TwoE32 = 0x4F800000ULL;
2816 const uint64_t F32TwoE64 = 0x5F800000ULL;
2817 const uint64_t F32TwoE128 = 0x7F800000ULL;
2820 if (SrcVT == MVT::i32)
2821 FF = APInt(32, F32TwoE32);
2822 else if (SrcVT == MVT::i64)
2823 FF = APInt(32, F32TwoE64);
2824 else if (SrcVT == MVT::i128)
2825 FF = APInt(32, F32TwoE128);
2827 llvm_unreachable("Unsupported UINT_TO_FP!");
2829 // Check whether the sign bit is set.
2831 GetExpandedInteger(Op, Lo, Hi);
2832 SDValue SignSet = DAG.getSetCC(dl,
2833 getSetCCResultType(Hi.getValueType()),
2834 Hi, DAG.getConstant(0, Hi.getValueType()),
2837 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2838 SDValue FudgePtr = DAG.getConstantPool(
2839 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2840 TLI.getPointerTy());
2842 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2843 SDValue Zero = DAG.getIntPtrConstant(0);
2844 SDValue Four = DAG.getIntPtrConstant(4);
2845 if (TLI.isBigEndian()) std::swap(Zero, Four);
2846 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2848 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2849 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2851 Alignment = std::min(Alignment, 4u);
2853 // Load the value out, extending it from f32 to the destination float type.
2854 // FIXME: Avoid the extend by constructing the right constant pool?
2855 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2857 MachinePointerInfo::getConstantPool(),
2859 false, false, Alignment);
2860 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2863 // Otherwise, use a libcall.
2864 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2865 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2866 "Don't know how to expand this UINT_TO_FP!");
2867 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2870 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2872 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2873 cast<AtomicSDNode>(N)->getMemoryVT(),
2875 N->getOperand(1), N->getOperand(2),
2876 cast<AtomicSDNode>(N)->getMemOperand(),
2877 cast<AtomicSDNode>(N)->getOrdering(),
2878 cast<AtomicSDNode>(N)->getSynchScope());
2879 return Swap.getValue(1);
2883 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2884 SDValue InOp0 = N->getOperand(0);
2885 EVT InVT = InOp0.getValueType();
2887 EVT OutVT = N->getValueType(0);
2888 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2889 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2890 unsigned OutNumElems = OutVT.getVectorNumElements();
2891 EVT NOutVTElem = NOutVT.getVectorElementType();
2894 SDValue BaseIdx = N->getOperand(1);
2896 SmallVector<SDValue, 8> Ops;
2897 Ops.reserve(OutNumElems);
2898 for (unsigned i = 0; i != OutNumElems; ++i) {
2900 // Extract the element from the original vector.
2901 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2902 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2903 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2904 InVT.getVectorElementType(), N->getOperand(0), Index);
2906 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2907 // Insert the converted element to the new vector.
2911 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2915 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2916 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2917 EVT VT = N->getValueType(0);
2920 unsigned NumElts = VT.getVectorNumElements();
2921 SmallVector<int, 8> NewMask;
2922 for (unsigned i = 0; i != NumElts; ++i) {
2923 NewMask.push_back(SV->getMaskElt(i));
2926 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2927 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2928 EVT OutVT = V0.getValueType();
2930 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2934 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2935 EVT OutVT = N->getValueType(0);
2936 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2937 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2938 unsigned NumElems = N->getNumOperands();
2939 EVT NOutVTElem = NOutVT.getVectorElementType();
2943 SmallVector<SDValue, 8> Ops;
2944 Ops.reserve(NumElems);
2945 for (unsigned i = 0; i != NumElems; ++i) {
2947 // BUILD_VECTOR integer operand types are allowed to be larger than the
2948 // result's element type. This may still be true after the promotion. For
2949 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2950 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2951 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2952 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2954 Op = N->getOperand(i);
2958 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2961 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2965 assert(!N->getOperand(0).getValueType().isVector() &&
2966 "Input must be a scalar");
2968 EVT OutVT = N->getValueType(0);
2969 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2970 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2971 EVT NOutVTElem = NOutVT.getVectorElementType();
2973 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2975 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2978 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2981 EVT OutVT = N->getValueType(0);
2982 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2983 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2985 EVT InElemTy = OutVT.getVectorElementType();
2986 EVT OutElemTy = NOutVT.getVectorElementType();
2988 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2989 unsigned NumOutElem = NOutVT.getVectorNumElements();
2990 unsigned NumOperands = N->getNumOperands();
2991 assert(NumElem * NumOperands == NumOutElem &&
2992 "Unexpected number of elements");
2994 // Take the elements from the first vector.
2995 SmallVector<SDValue, 8> Ops(NumOutElem);
2996 for (unsigned i = 0; i < NumOperands; ++i) {
2997 SDValue Op = N->getOperand(i);
2998 for (unsigned j = 0; j < NumElem; ++j) {
2999 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3000 InElemTy, Op, DAG.getConstant(j,
3001 TLI.getVectorIdxTy()));
3002 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3006 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3009 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3010 EVT OutVT = N->getValueType(0);
3011 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3012 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3014 EVT NOutVTElem = NOutVT.getVectorElementType();
3017 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3019 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3020 NOutVTElem, N->getOperand(1));
3021 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3022 V0, ConvElem, N->getOperand(2));
3025 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3027 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3028 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3029 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3030 V0->getValueType(0).getScalarType(), V0, V1);
3032 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3033 // element types. If this is the case then we need to expand the outgoing
3034 // value and not truncate it.
3035 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3038 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3040 unsigned NumElems = N->getNumOperands();
3042 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3044 SmallVector<SDValue, 8> NewOps;
3045 NewOps.reserve(NumElems);
3047 // For each incoming vector
3048 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3049 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3050 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3051 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3053 for (unsigned i=0; i<NumElem; ++i) {
3054 // Extract element from incoming vector
3055 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3056 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3057 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3058 NewOps.push_back(Tr);
3062 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);